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The following document contains information on Cypress products.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-27257-3E
ASSP For Power Supply Applications
6 ch DC/DC Converter IC with
Synchronous Rectification
MB39A123
■ DESCRIPTION
MB39A123 is a 6-channel DC/DC converter IC using pulse width modulation (PWM) , and it is suitable for
up conversion, down conversion, and up/down conversion. MB39A123 is built in 6 channels into LQFP-48P
package and this IC can control and soft-start at each channel. MB39A123 is suitable for power supply of
high performance potable instruments such as a digital still camera (DSC).
■ FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports for step-down with synchronous rectification (ch.1)
Supports for step-down and up/down Zeta conversion (ch.2 to ch.4)
Supports for step-up and up/down Sepic conversion (ch.5, ch.6)
Negative voltage output (Inverting amplifier) (ch.4)
Low voltage start-up (ch.5, ch.6) : 1.7 V
Power supply voltage range
: 2.5 V to 11 V
Reference voltage
: 2.0 V ± 1%
Error amplifier reference voltage : 1.0 V ± 1% (ch.1) , 1.23 V ± 1% (ch.2 to ch.6)
Oscillation frequency range
: 200 kHz to 2.0 MHz
Standby current
: 0 μA (Typ)
Built-in soft-start circuit independent of loads
Built-in totem-pole type output for MOS FET
Short-circuit detection capability by external signal (−INS terminal)
Package
: LQFP-48 pin
■ APPLICATIONS
• Digital still camera (DSC)
• Digital video camera (DVC)
• Surveillance camera
etc.
Copyright©2006-2012 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2012.4
MB39A123
■ PIN ASSIGNMENTS
VCC
CS3
−INE3
FB3
DTC3
DTC2
FB2
−INE2
CS2
CS1
−INE1
FB1
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
CTL3
4
33
OUT2
CTL4
5
32
OUT3
CTL5
6
31
OUT4
CTL6
7
30
OUT5
−INS
8
29
OUT6
VREF
9
28
GNDO
GND
10
27
CS6
RT
11
26
−INE6
CT
12
25
FB6
13
14
15
16
17
18
19
20
21
22
23
24
DTC6
OUT1-2
DTC5
34
FB5
3
−INE5
CTL2
CS5
OUT1-1
−INA
35
OUTA
2
CS4
CTL1
−INE4
VCCO
FB4
36
DTC4
1
CSCP
CTL
(FPT-48P-M49)
2
DS04-27257-3E
MB39A123
■ PIN DESCRIPTIONS
Block
name
Pin No. Pin name
I/O
37
FB1
O
ch.1• Error amplifier output terminal
38
−INE1
I
ch.1• Error amplifier inverted input terminal
39
CS1
⎯
ch.1• Soft-start setting capacitor connection terminal
35
OUT1-1
O
ch.1• P-ch drive output terminal
(External main side FET gate driving)
34
OUT1-2
O
ch.1• N-ch drive output terminal
(External synchronous rectification side FET gate driving)
43
DTC2
I
ch.2 • Dead time control terminal
42
FB2
O
ch.2 • Error amplifier output terminal
41
−INE2
I
ch.2 • Error amplifier inverted input terminal
40
CS2
⎯
ch.2 • Soft-start setting capacitor connection terminal
33
OUT2
O
ch.2 • P-ch drive output terminal
44
DTC3
I
ch.3 • Dead time control terminal
45
FB3
O
ch.3 • Error amplifier output terminal
46
−INE3
I
ch.3 • Error amplifier inverted input terminal
47
CS3
⎯
ch.3 • Soft-start setting capacitor connection terminal
32
OUT3
O
ch.3 • P-ch drive output terminal
14
DTC4
I
ch.4 • Dead time control terminal
15
FB4
O
ch.4 • Error amplifier output terminal
16
−INE4
I
ch.4 • Error amplifier inverted input terminal
17
CS4
⎯
ch.4 • Soft-start setting capacitor connection terminal
31
OUT4
O
ch.4 • P-ch drive output terminal
19
−INA
I
Inverting amplifier input terminal
18
OUTA
O
Inverting amplifier output terminal
23
DTC5
I
ch.5 • Dead time control terminal
22
FB5
O
ch.5 • Error amplifier output terminal
21
−INE5
I
ch.5 • Error amplifier inverted input terminal
20
CS5
⎯
ch.5 • Soft-start setting capacitor connection terminal
30
OUT5
O
ch.5 • N-ch drive output terminal
24
DTC6
I
ch.6 • Dead time control terminal
25
FB6
O
ch.6 • Error amplifier output terminal
26
−INE6
I
ch.6 • Error amplifier inverted input terminal
27
CS6
⎯
ch.6 • Soft-start setting capacitor connection terminal
29
OUT6
O
ch.6 • N-ch drive output terminal
ch.1
ch.2
ch.3
ch.4
ch.5
ch.6
Description
(Continued)
DS04-27257-3E
3
MB39A123
(Continued)
Block
name
OSC
Control
Power
4
Pin No.
Pin name
I/O
Description
12
CT
⎯
Triangular wave frequency setting capacitor connection terminal
11
RT
⎯
Triangular wave frequency setting resistor connection terminal
1
CTL
I
Power supply control terminal
2
CTL1
I
ch.1 control terminal
3
CTL2
I
ch.2 control terminal
4
CTL3
I
ch.3 control terminal
5
CTL4
I
ch.4 control terminal
6
CTL5
I
ch.5 control terminal
7
CTL6
I
ch.6 control terminal
13
CSCP
⎯
8
−INS
I
36
VCCO
⎯
Drive output block power supply terminal
48
VCC
⎯
Power supply terminal
9
VREF
O
Reference voltage output terminal
28
GNDO
⎯
Drive output block ground terminal
10
GND
⎯
Ground terminal
Short-circuit detection circuit capacitor connection terminal
Short-circuit detection comparator inverted input terminal
DS04-27257-3E
MB39A123
■ BLOCK DIAGRAM
Step-down
(Synchronous
Rectification)
A
L priority
38
VREF
1.1 A
CS1
<<ch.1>>
Error
Amp1
+
+
39
+
PWM
Comp.1
-
Dead Time
-INE1
A
(1.0 V)
FB1
37
Reference voltage
1.0 V ± 1 %
Io = 300 mA
at VCCO = 7 V
Drive1-1
P-ch
35
Drive1-2
N-ch
34
41
VREF
1.1 A
CS2
+
+
40
Error
Amp2
OUT1-1
OUT1-2
B
Vo2
(2.5 V)
<<ch.2>>
Max Duty VREF L priority
92 % ± 5 %
PWM
+
+
-
Vo1
(1.2 V)
Io = 300 mA
at VCCO = 7 V
L priority
-INE2
VCCO
Step-down
Dead Time
(td = 50 ns)
B
36
Comp.2
Drive2
P-ch
33
OUT2
1.23 V
FB2
42
DTC2
-INE3
C
L priority
46
VREF
1.1 A
CS3
+
+
47
Step-down
Io = 300 mA
at VCCO = 7 V
Reference voltage
1.23 V ± 1 %
43
Error
Amp3
Max Duty VREF
92 % ± 5 %
L priority
+
+
-
C
Vo3
(3.3 V)
<<ch.3>>
PWM
Comp.3
Drive3
P-ch
32
OUT3
1.23 V
FB3
45
DTC3
-INA
D
Io = 300 mA
at VCCO = 7 V
Reference voltage
1.23 V ± 1 %
44
<<ch.4>>
-
19
+
INVAmp
OUTA
Inverting
18
-INE4
VIN
(5 V-11 V)
16
VREF
1.1 A
CS4
D
L priority
+
+
17
Error
Amp4
Vo4
(-7.5 V)
L priority
Max Duty VREF
PWM
92 % ± 5 %
+
+
-
Comp.4
Drive4
P-ch
31
OUT4
1.23 V
FB4
DTC4
15
Io = 300 mA
at VCCO = 7 V
Reference voltage
1.23 V ± 1 %
14
Step-up
E
-INE5
L priority
21
VREF
1.1 A
CS5
+
+
20
Error
Amp5
+
+
-
E
<<ch.5>>
Max Duty VREF L priority
92 % ± 5 %
PWM
Vo5
(15 V)
Comp.5
Drive5
N-ch
30
OUT5
1.23 V
FB5
22
-INE6
F
Transformer
L priority
26
VREF
1.1 A
CS6
Io = 300 mA
at VCCO = 7 V
Reference voltage
1.23 V ± 1 %
DTC5 23
+
+
27
Error
Amp6
Vo6-1
(15 V)
Vo6-2
(5.0 V)
Max Duty VREF L priority
92 % ± 5 %
PWM
+
+
-
Comp.6
Drive6
N-ch
1.23 V
FB6
DTC6
29
28
25
OUT6
GNDO
Io = 300 mA
at VCCO = 7 V
Reference voltage
1.23 V ± 1 %
24
F
<<ch.6>>
VREF
Short-circuit
detection signal
(L: at short-circuit)
Charge current
1 A
-INS
-
8
1V
CSCP
SCP
Comp.
Error Amp power supply
SCP Comp. power supply
13
H:UVLO release
0.9 V
H:ON
L:OFF
VTH = 1.0 V
H:at SCP
SCP
+
CTL1
2
CTL2
3
CTL3 4
CTL4
5
CTL5
6
CTL6
7
0.4 V
UVLO1
OSC
CHCTL
RT
VREF
CT
VR
Power
ON/OFF
CTL
1
CTL
H:ON (Power ON)
L:OFF(Standby mode)
VTH = 1.0 V
Precision
± 0.8 %
9
12
10
VREF
Precision ± 0.5 %
(2.0 MHz)
DS04-27257-3E
bias
UVLO2
VCC
1.0 V/1.23 V
2.0 V
11
48
Error Amp
reference
Precision
±1 %
GND
<< 48 Pin >>
PKG:LQFP-48 P
5
MB39A123
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Symbol
VCC
Conditions
Rating
Unit
Min
Max
VCC, VCCO terminals
⎯
12
V
Output current
IO
OUT1-1, OUT1-2, OUT2 to OUT6
terminals
⎯
20
mA
Peak output current
IOP
OUT1-1, OUT1-2, OUT2 to OUT6
terminals
Duty ≤ 5%
⎯
400
mA
Power dissipation
PD
Ta ≤ +25 °C (LQFP-48P)
⎯
2000*
mW
−55
+125
°C
Storage temperature
TSTG
⎯
* : When mounted on a 117 mm × 84 mm × 0.8 mm FR-4 boards.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
6
DS04-27257-3E
MB39A123
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Conditions
Value
Min
Typ
Max
Unit
Start power supply voltage
VCC
ch.5, ch.6, VCC, VCCO
terminals
1.7
⎯
11
V
Power supply voltage
VCC
VCC, VCCO terminals
2.5
4
11
V
Reference voltage output
current
IREF
VREF terminal
−1
⎯
0
mA
−INE1 to −INE6 terminals
0
⎯
VCC − 0.9
V
−INA terminal
− 0.2
⎯
VCC − 1.8
V
−INS terminal
0
⎯
VREF
V
VDTC
DTC2 to DTC6 terminals
0
⎯
VREF
V
VCTL
CTL, CTL1 to CTL6
terminals
0
⎯
11
V
Input voltage
Control input voltage
VINE
IO
OUT1-1, OUT1-2, OUT2 to
OUT6 terminals
−15
⎯
+15
mA
Total gate charge of external
FET
Qg
OUT1-1, OUT1-2, OUT2 to
OUT6 terminals
connection FET
fosc = 2 MHz
⎯
2.6
7.5
nC
Oscillation frequency
fOSC
⎯
0.2
1.0
2.0
MHz
Timing capacitor
CT
⎯
27
100
680
pF
Timing resistor
RT
⎯
3.0
6.8
39
kΩ
Soft-start capacitor
CS
⎯
0.1
1.0
μF
Output current
CS1 to CS6 terminals
Short-circuit detection
capacitor
CSCP
⎯
⎯
0.1
1.0
μF
Reference voltage output
capacitor
CREF
⎯
⎯
0.1
1.0
μF
Ta
⎯
−30
+25
+85
°C
Operating ambient
temperature
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
DS04-27257-3E
7
MB39A123
■ ELECTRICAL CHARACTERISTICS
(VCC = VCCO = 4 V, Ta = +25 °C)
Parameter
Pin No.
VREF1
9
VREF2
Conditions
Value
Unit
Min
Typ
Max
VREF = 0 mA
1.98
2.00
2.02
V
9
VCC = 2.5 V to 11 V
1.975 2.000 2.025
V
VREF3
9
VREF = 0 mA to −1 mA
1.975 2.000 2.025
V
Input stability
Line
9
VCC = 2.5 V to 11 V*
⎯
2
⎯
mV
Load stability
Load
9
VREF = 0 mA to −1 mA*
⎯
2
⎯
mV
Temperature
stability
ΔVREF/
VREF
9
Ta = 0 °C to +85 °C*
⎯
0.20
⎯
%
Short-circuit
output current
IOS
9
VREF = 0 V*
⎯
−130
⎯
mA
VCC =
1.7
1.8
1.9
V
0.05
0.1
0.2
V
Output voltage
Reference
Voltage Block
[VREF]
Symbol
Under voltage
lockout
protection
circuit Block
(ch.1 to ch.4)
[UVLO1]
Threshold
voltage
VTH1
35
Hysteresis
width
VH1
35
Reset voltage
VRST1
35
VCC =
1.55
1.7
1.85
V
Under voltage
lockout
protection
circuit Block
(ch.5, ch.6)
[UVLO2]
Threshold
voltage
VTH2
30
VCC =
1.35
1.5
1.65
V
Hysteresis
width
VH2
30
0.02
0.05
0.1
V
VRST2
30
1.27
1.45
1.63
V
VTH
13
⎯
0.65
0.70
0.75
V
ICSCP
13
⎯
−1.4
−1.0
−0.6
μA
fosc1
29 to 35
CT = 100 pF,
RT = 6.8 kΩ
0.95
1.0
1.05
MHz
fosc2
29 to 35
CT = 100 pF, RT = 6.8 kΩ
0.945
VCC = 2.5 V to 11 V
1.0
1.055 MHz
Frequency
Input stability
ΔfOSC/
fOSC
29 to 35
CT = 100 pF, RT = 6.8 kΩ
VCC = 2.5 V to 11 V*
⎯
1.0
⎯
%
Frequency
temperature
stability
ΔfOSC/
fOSC
29 to 35
CT = 100 pF, RT = 6.8 kΩ
Ta = 0 °C to +85 °C*
⎯
1.0
⎯
%
−1.45
−1.1
−0.75
μA
Reset voltage
Threshold
Short-circuit
voltage
detection Block
Input source
[SCP]
current
Oscillation
frequency
Triangular
Wave Oscillator Block
[OSC]
Soft-Start Block
Charge
(ch.1 to ch.6)
current
[CS1 to CS6]
ICS
⎯
⎯
VCC =
17,20,27,
CS1 to CS6 = 0 V
39,40,47
(Continued)
8
DS04-27257-3E
MB39A123
(VCC = VCCO = 4 V, Ta = +25 °C)
Parameter
Reference
voltage
Temperature
stability
Input bias
current
Error Amp Block
Voltage gain
(ch.1)
[Error Amp1]
Frequency
bandwidth
Output
voltage
Output source
current
Output sink
current
Symbol Pin No.
Input bias
Error Amp Block current
(ch.2 to ch.6)
[Error Amp2 to
Error Amp6]
Voltage gain
Frequency
bandwidth
Value
Min
Typ
Max
Unit
VTH1
38
VCC = 2.5 V to 11 V
Ta = +25 °C
0.990 1.000 1.010
V
VTH2
38
VCC = 2.5 V to 11 V
Ta = 0 °C to +85 °C*
0.988 1.000 1.012
V
ΔVTH/
VTH
38
Ta = 0 °C to +85 °C*
IB
38
−INE1 = 0 V
AV
37
BW
37
VOH
37
VOL
37
ISOURCE
37
ISINK
37
VTH3
16, 21,
26, 41,
46
VCC = 2.5 V to 11 V
Ta = +25 °C
1.217 1.230 1.243
V
VTH4
16, 21,
26, 41,
46
VCC = 2.5 V to 11 V
Ta = 0 °C to +85 °C*
1.215 1.230 1.245
V
ΔVTH/
VTH
16, 21,
26, 41,
46
Ta = 0 °C to +85 °C*
⎯
0.1
⎯
%
IB
16, 21,
26, 41,
46
−INE2 to −INE6 = 0 V
−120
−30
⎯
nA
AV
15, 22,
25, 42,
45
DC*
⎯
100
⎯
dB
BW
15, 22,
25, 42,
45
AV = 0 dB*
⎯
1.4
⎯
MHz
VOH
15, 22,
25, 42,
45
⎯
1.7
1.9
⎯
V
VOL
15, 22,
25, 42,
45
⎯
⎯
40
200
mV
Reference
voltage
Temperature
stability
Conditions
Output
voltage
⎯
0.1
⎯
%
−120
−30
⎯
nA
DC*
⎯
100
⎯
dB
AV = 0 dB*
⎯
1.4
⎯
MHz
⎯
1.7
1.9
⎯
V
⎯
⎯
40
200
mV
FB1 = 0.65 V
⎯
−2
−1
mA
FB1 = 0.65 V
150
200
⎯
μA
(Continued)
DS04-27257-3E
9
MB39A123
(VCC = VCCO = 4 V, Ta = +25 °C)
Parameter
Typ
Max
Unit
FB2 to FB6 = 0.65 V
⎯
−2
−1
mA
ISINK
15, 22,
25, 42,
45
FB2 to FB6 = 0.65 V
150
200
⎯
μA
VIO
18
OUTA = 1.23V
−10
0
+ 10
mV
Input bias
current
IB
19
− INA = 0V
−120
−30
⎯
nA
Voltage gain
AV
18
DC*
⎯
100
⎯
dB
Frequency
bandwidth
BW
18
AV = 0 dB*
⎯
1.0
⎯
MHz
VOH
18
⎯
1.7
1.9
⎯
V
VOL
18
⎯
⎯
40
200
mV
ISOURCE
18
OUTA = 1.23V
⎯
−2
−1
mA
ISINK
18
OUTA = 1.23V
150
200
⎯
μA
VT0
34, 35
Duty cycle = 0%
0.35
0.4
0.45
V
VT100
34, 35
Duty cycle = 100%
0.85
0.9
0.95
V
29 to 33 Duty cycle = 0%
0.35
0.4
0.45
V
29 to 33 Duty cycle = 100%
0.85
0.9
0.95
V
Output
voltage
Output source
current
Output sink
current
PWM
Comparator
Block
(ch.2 to ch.6)
[PWM Comp.2 to
PWM Comp.6]
Min
15, 22,
25, 42,
45
Input offset
voltage
PWM
Comparator
Block
(ch.1)
[PWM Comp.1]
Value
Conditions
ISOURCE
Output source
Error Amp Block current
(ch.2 to ch.6)
[Error Amp2 to
Output sink
Error Amp6]
current
Inverting Amp
Block (ch.4)
[Inv Amp]
Symbol Pin No.
Threshold
voltage
Threshold
voltage
VT0
VT100
Maximum duty
cycle
Dtr
29 to 33
CT = 100 pF,
RT = 6.8 kΩ
87
92
97
%
Output source
current
ISOURCE
29 to 35
Duty ≤ 5%
OUT = 0 V
⎯
−130
−75
mA
ISINK
29 to 35
Duty ≤ 5%
OUT = 4 V
75
130
⎯
mA
ROH
29 to 35 OUT = − 15 mA
⎯
18
27
Ω
ROL
29 to 35 OUT = 15 mA
⎯
18
27
Ω
Output sink
current
Output Block
(ch.1 to ch.6)
Output on
[Drive1 to Drive6]
resistor
Dead time
tD1
34, 35
OUT2
− OUT1
*
⎯
50
⎯
ns
tD2
34, 35
OUT1
− OUT2
*
⎯
50
⎯
ns
(Continued)
10
DS04-27257-3E
MB39A123
(Continued)
(VCC = VCCO = 4 V, Ta = +25 °C)
Parameter
Short-Circuit
Detection
Comparator
Block
[SCP Comp.]
Control Block
(CTL,
CTL1 to CTL6)
[CTL, CHCTL]
Conditions
Value
Unit
Min
Typ
Max
0.97
1.00
1.03
V
−INS = 0 V
−25
−20
−17
μA
Threshold
voltage
VTH
35
Input bias
current
IB
8
Output on
condition
VIH
1 to 7
CTL, CTL1 to CTL6
1.5
⎯
11
V
Output off
condition
VIL
1 to 7
CTL, CTL1 to CTL6
0
⎯
0.5
V
ICTLH
1 to 7
CTL, CTL1 to CTL6 = 3 V
5
30
60
μA
ICTLL
1 to 7
CTL, CTL1 to CTL6 = 0 V
⎯
⎯
1
μA
ICCS
48
CTL, CTL1 to CTL6 = 0 V
⎯
0
2
μA
ICCSO
36
CTL = 0 V
⎯
0
1
μA
ICC
48
CTL = 3 V
⎯
4.5
6.8
mA
Input current
General
Symbol Pin No.
Standby
current
Power supply
current
⎯
* : Standard design value
DS04-27257-3E
11
MB39A123
■ TYPICAL CHARACTERISTICS
Power Supply Current vs.
Power Supply Voltage
5
Ta = + 25 °C
CTL = 3 V
Reference Voltage VREF (V)
Power Supply Current ICC (mA)
5
Reference Voltage vs.
Power Supply Voltage
4
3
2
1
Ta = + 25 °C
CTL = 3 V
VREF = 0 mA
4
3
2
1
0
0
0
2
4
6
8
10
0
12
2
Power Supply Voltage VCC (V)
4
6
8
10
12
Power Supply Voltage VCC (V)
Reference Voltage vs.
Operating Ambient Temperature
Reference Voltage VREF (V)
2.05
VCC = 4 V
CTL = 3 V
VREF = 0 mA
2.04
2.03
2.02
2.01
2.00
1.99
1.98
1.97
1.96
1.95
−40
−20
+20
0
+40
+60
+80
+100
Operating Ambient Temperature Ta ( °C)
Reference Voltage vs.
CTL Terminal Voltage
CTL Terminal Current vs.
CTL Terminal Voltage
200
Ta = + 25 °C
VCC = 4 V
VREF = 0 mA
4.0
3.0
2.0
1.0
0.0
0
2
4
6
8
10
CTL Terminal Voltage VCTL (V)
12
CTL Terminal Current ICTL (μA)
Reference Voltage VREF (V)
5.0
Ta = + 25 °C
VCC = 4 V
150
100
50
0
0
2
4
6
8
10
12
CTL Terminal Voltage VCTL (V)
(Continued)
12
DS04-27257-3E
MB39A123
Triangular Wave Oscillation Frequency vs.
Timing Resistor
Triangular Wave Oscillation Frequency vs.
Timing Capacity
10000
10000
Triangular Wave Oscillation
Frequency fOSC (kHz)
Triangular Wave Oscillation
Frequency fOSC (kHz)
Ta = + 25 °C
VCC = 4 V
CTL = 3 V
1000
CT = 27 pF
CT = 100 pF
CT = 680 pF CT = 220 pF
100
10
1
10
100
Ta = + 25 °C
VCC = 4 V
CTL = 3 V
1000
RT = 3 kΩ
RT = 6.8 kΩ
RT = 39 kΩ RT = 13 kΩ
100
10
10
1000
100
Timing Resistor RT (kΩ)
Triangular Wave Upper and Lower
Limit Voltage VCT (V)
1.20
1.10
1.00
Upper limit
0.90
0.80
0.70
0.60
0.50
0.40
Lower limit
0.30
0.20
0
10000
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
Triangular Wave Oscillation Frequency fOSC (kHz)
Triangular Wave Upper and Lower Limit Voltage
vs. Operating Ambient Temperature
Triangular Wave Upper and Lower
Limit Voltage VCT (V)
Triangular Wave Upper and Lower Limit Voltage
vs. Triangular Wave Oscillation Frequency
Ta = + 25 °C
VCC = 4 V
CTL = 3 V
RT = 6.8 kΩ
1000
Timing Capacity CT (pF)
1.20
1.10
1.00
VCC = 4 V
CTL = 3 V
RT = 6.8 kΩ
CT = 100 pF
Upper limit
0.90
0.80
0.70
0.60
0.50
0.40
Lower limit
0.30
0.20
−40
−20
0
+20
+40
+60
+80
+100
Operating Ambient Temperature Ta ( °C)
Triangular Wave Oscillation Frequency
vs. Operating Ambient Temperature
Triangular Wave Oscillation
Frequency fOSC (kHz)
1100
1080
1060
VCC = 4 V
CTL = 3 V
RT = 6.8 kΩ
CT = 100 pF
1040
1020
1000
980
960
940
920
900
−40
−20
0
+20
+40
+60
+80
+100
Operating Ambient Temperature Ta ( °C)
(Continued)
DS04-27257-3E
13
MB39A123
ON Duty Cycle vs. DTC Terminal Voltage
Maximum Duty Cycle vs. Oscillation Frequency
100
100
Ta = + 25 °C
VCC = CTL = 4 V
FB = 2 V
CT = 100 pF
90
fosc = 200 kHz
Maximum Duty Cycle Dtr (%)
ON Duty Cycle Dtr (%)
95
fosc = 1 MHz
85
80
75
fosc = 2 MHz
70
65
60
55
50
0.6
0.65
0.7
0.75
0.8
0.85
0.9
Ta = + 25 °C
VCC = 4 V
CTL = 4 V
FB = 2 V
DTC = Open
95
90
RT = 3 kΩ
RT = 39 kΩ
85
RT = 13 kΩ
RT = 6.8 kΩ
80
75
70
0
200 400 600 800 1000 1200 1400 1600 1800 2000 2200
DTC Terminal Voltage VDTC (V)
Oscillation Frequency fOSC (kHz)
Maximum Duty Cycle vs. Power Supply Voltage
Maximum Duty Cycle vs.
Operating Ambient Temperature
100
100
95
Maximum Duty Cycle Dtr (%)
Maximum Duty Cycle Dtr (%)
fosc = 200 kHz
fosc = 1 MHz
90
85
Ta = + 25 °C
VCC = CTL
DTC pin open
FB = 2 V
CT = 100 pF
fosc = 2 MHz
80
75
70
0
2
4
6
8
10
12
fosc = 200 kHz
95
90
fosc = 1 MHz
85
fosc = 2 MHz
80
Ta = + 25 °C
VCC = CTL = 4 V
DTC pin open
FB = 2 V
CT = 100 pF
75
70
−40
−20
0
+20
+40
+60
+80
+100
Operating Ambient Temperature Ta ( °C)
Power Supply Voltage VCC (V)
Start Power Supply Voltage vs. Timing Resistor
Start Power Supply Voltage VCC (V)
2
At evaluating Fujitsu EV board system
1.9
Ta = −30 °C
1.8
1.7
Ta = + 25 °C
1.6
1.5
1.4
1.3
1.2
VCTL = VCC
CT = 100 pF
1.1
1
1
10
100
Timing Resistor RT (kΩ)
(Continued)
14
DS04-27257-3E
MB39A123
(Continued)
50
225
40
Av
30
Ta = +25 °C
VCC = 7 V
2.0 V
135
φ
20
180
90
10
45
0
0
Phase φ (deg)
Error Amp Voltage Gain AV (dB)
Error Amp Voltage Gain, Phase vs. Frequency
−10
−45
−20
−90
−30
−135
−40
−180
−50
1k
10 k
100 k
1M
10 kΩ
1 μF +
2.4 kΩ
IN
10 kΩ
240 kΩ
37
−
38
+
+
1.5 V
36
OUT
1.0 V Error Amp1
the same as other
channels
−225
10 M
Frequency f (Hz)
Maximum Power Dissipation PD (mW)
Maximum Power Dissipation vs.
Operating Ambient Temperature
(for LQFP-48P)
DS04-27257-3E
2250
2000
1800
1600
1400
1200
1000
800
600
400
200
0
−40
−20
0
+20
+40
+60
+80
+100
Operating Ambient Temperature Ta ( °C)
15
MB39A123
■ FUNCTIONAL DESCRIPTION
1. DC/DC Converter Function
(1) Reference voltage block (VREF)
The reference voltage circuit uses the voltage supplied from VCC terminal (pin 48) to generate a temperature
compensated reference voltage (2.0 V Typ) used as the reference voltage for the internal circuits of the IC.
It is also possible to supply the load current of up to 1 mA to external circuits as a reference voltage through
the VREF terminal (pin 9) .
(2) Triangular wave oscillator block (OSC)
The triangular wave oscillator block generates the triangular wave oscillation waveform width of 0.4 V lower
limit and 0.5 V amplitude by the timing resistor (RT ) connected to the RT terminal (pin 11) , and the timing
capacitor (CT) connected to the CT terminal (pin 12) . The triangular wave is input to the PWM comparator
circuits on the IC.
(3) Error amplifier block (Error Amp1 to Error Amp6)
The error amplifier detects output voltage of the DC/DC converter and outputs PWM control signals. An
arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the output terminal to
inverted input terminal of the error amplifier, enabling stable phase compensation for the system.
You can prevent surge currents when the IC is turned on by connecting soft-start capacitors to the CS1
terminal (pin 39) to CS6 terminal (pin 27) which are the noninverting input terminals of the error amplifier.
The IC is started up at constant soft-start time intervals independent of the output load of the DC/DC converter.
(4) PWM comparator block (PWM Comp.1 to PWM Comp.6)
The PWM comparator block is a voltage-pulse width converter that controls the output duty depending on
the input/output voltage.
An output transistor is turned on, during intervals when the error amplifier output voltage and DTC voltage
(ch.2 to ch.6) are higher than the triangular wave voltage.
(5) Output block (Drive1 to Drive6)
The output circuit uses a totem-pole configuration and is capable of driving an external P-ch MOS FET (main
side of ch.1, ch.2, ch.3 and ch.4) and N-ch MOS FET (synchronous rectification side of ch.1, ch.5 and ch.6).
16
DS04-27257-3E
MB39A123
2. Channel Control Function
Use the CTL terminal (pin 1), CTL1 terminal (pin 2), CTL2 terminal (pin 3), CTL3 terminal (pin 4), CTL4
terminal (pin 5), CTL5 terminal (pin 6), and CTL6 terminal (pin 7) to set ON/OFF to the main and each
channels.
ON/OFF setting conditions for each channel
CTL
CTL1 CTL2 CTL3 CTL4 CTL5 CTL6 Power
ch.1
ch.2
ch.3
ch.4
ch.5
ch.6
L
X
X
X
X
X
X
OFF
OFF
OFF
OFF
OFF
OFF
OFF
H
L
L
L
L
L
L
ON
OFF
OFF
OFF
OFF
OFF
OFF
H
H
L
L
L
L
L
ON
ON
OFF
OFF
OFF
OFF
OFF
H
L
H
L
L
L
L
ON
OFF
ON
OFF
OFF
OFF
OFF
H
L
L
H
L
L
L
ON
OFF
OFF
ON
OFF
OFF
OFF
H
L
L
L
H
L
L
ON
OFF
OFF
OFF
ON
OFF
OFF
H
L
L
L
L
H
L
ON
OFF
OFF
OFF
OFF
ON
OFF
H
L
L
L
L
L
H
ON
OFF
OFF
OFF
OFF
OFF
ON
H
H
H
H
H
H
H
ON
ON
ON
ON
ON
ON
ON
Note : Note that current which is over standby current flows into VCC terminal when the CTL terminal is in “L”
level and one of the terminals between CTL1 to CTL6 terminals is set to “H” level.
(Refer to the following circuit)
• CTL1 to CTL6 terminals equivalent circuit
VCC
48
CTL1
200 k
to
CTL6
86 k
ESD
protection
element
223 k
GND
DS04-27257-3E
10
17
MB39A123
3. Protection Function
(1) Timer-latch short-circuit protection circuit (SCP, SCP Comp.)
The short-circuit detection comparator (SCP) detects the output voltage level of each channel. If the output
voltage of any channel is lower than the short-circuit detection voltage, the timer circuit is actuated to start
charging to the capacitor (Cscp) externally connected to the CSCP terminal (pin 13).
When the capacitor (Cscp) voltage becomes about 0.7 V, the output transistor is turned off and the dead
time is set to 100%.
The short-circuit detection from external input is capable by using −INS terminal (pin 8) on short-circuit
detection comparator (SCP Comp.) .
When the protection circuit is actuated, the power supply is rebooted or the CTL terminal (pin 1) is set to "L"
level, resetting the latch as the voltage at the VREF terminal (pin 9) becomes 1.27 V (Min) or less (Refer to
“■SETTING THE TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION CIRCUIT”) .
(2) Under voltage lockout protection circuit block (UVLO)
The transient state or a momentary decrease in the power supply voltage, which occurs when the power
supply is turned on, may cause the control IC to malfunction, resulting in the breakdown or degradation of
the system. To prevent such malfunctions, under voltage lockout protection circuit detects a decrease in
internal reference voltage level with respect to the power supply voltage, turns off the output transistor, and
sets the dead time to 100% while holding the CSCP terminal (pin 13) at the "L" level.
The system returns to the normal state when the power supply voltage reaches the reference voltage of the
under voltage lockout protection circuit.
(3) Protection circuit operating function table
The following table shows the output state that the protection circuit is operating.
Operation circuit
OUT1-1 OUT1-2 OUT2
OUT3
OUT4
OUT5
OUT6
Short-circuit protection circuit
H
L
H
H
H
L
L
Under voltage lockout protection circuit
H
L
H
H
H
L
L
18
DS04-27257-3E
MB39A123
■ SETTING THE OUTPUT VOLTAGE
• ch.1
R3
Vo
R1
Error
Amp
−
38
−INE1
37
+
+
R2
FB1
1.00 V
CS1
1.00 V
(R1 + R2)
R2
VO
(R1 + R3) ≥
100 μA
VO =
39
Set R1 and R3 to prevent the error amp’s response from decreasing by using above formula.
• ch.2 to ch.6
R3
Vo
R1
Error
Amp
−
−INEX
R2
+
+
1.23 V
CSX
FBX
1.23 V
(R1 + R2)
R2
VO
(R1 + R3) ≥
100 μA
VO =
X : Each channel number
Set R1 and R3 to prevent the error amp’s response from decreasing by using above formula.
DS04-27257-3E
19
MB39A123
• ch.4 (Negative voltage output)
Vo
R1
−INA
19
−
INVAmp
Vo =
+
R2
−1.23 V
R2
R1
OUTA
18
R3
FB4
15
R4
16
−INE4
−
+
+
Error
Amp
1.23 V
CS4
20
17
DS04-27257-3E
MB39A123
■ SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY
The triangular wave oscillation frequency can be set by connecting a timing resistor (RT ) to the RT terminal
(pin 11) and a timing capacitor (CT) to the CT terminal (pin 12).
Triangular wave oscillation frequency : fOSC
fOSC (kHz) =:
DS04-27257-3E
680000
CT (pF) × RT (kΩ)
21
MB39A123
■ SETTING THE SOFT-START TIME
To prevent rush currents when the IC is turned on, you can set a soft-start by connecting soft-start capacitors
(CS1 to CS6) to the CS1 terminal (pin 39) to CS6 terminal (pin 27) respectively.
As illustrated below, when each CTLX is set to “H” from “L”, the soft-start capacitors (CS1 to CS6) externally
connected to the CS1 to CS6 terminals are charged at about 1.1 μA.
The error amplifier output (FB1 to FB6) is determined by comparison between the lower voltage of the two
non-inverted input terminal voltage (1.23 V (ch.1 : 1.0 V) , CS terminal voltage) and the inverted input terminal
voltage (−INE1 to −INE6) . The FB terminal voltage is decided for the soft-start period (CS terminal
voltage < 1.23 V (ch.1 : 1.0 V) ) by the comparison between −INE terminal voltage and CS terminal voltage.
The DC/DC converter output voltage rises in proportion to the CS terminal voltage as the soft-start capacitor
externally connected to the CS terminal is charged. The soft-start time is obtained from the following formula :
Soft-start time : ts (time until output voltage 100%)
ch.1
: ts (s) =: 0.91 × CS1 (μF)
ch.2 to ch.6 : ts (s) =: 1.12 × CSX (μF)
X : Each channel number
Vo
R1
−INEX
VREF
R2
1.1 μA
L priority
Error
AmpX
−
CSX
+
+
CSX
1.23 V (ch.1 : 1.0 V)
FBX
H : CSX can be charged when CTLX is set to "H" and
normal operation is selected
L : CSX is discharged when CTLX is set to "L" and
protective operation is selected
CTLX
CHCTL
X : Each channel number
22
DS04-27257-3E
MB39A123
■ PROCESSING WHEN NOT USING CS TERMINAL
When soft-start function is not used, leave the CS1 terminal (pin 39), the CS2 terminal (pin 40), the CS3
terminal (pin 47), the CS4 terminal (pin 17), the CS5 terminal (pin 20) and the CS6 terminal (pin 27) open.
• When not setting soft-start time
“Open”
“Open”
39
CS1
CS6
27
40
CS2
CS5
20
47
CS3
CS4
17
“Open”
“Open”
“Open”
DS04-27257-3E
“Open”
23
MB39A123
■ SETTING THE TIME CONSTANT FOR TIMER-LATCH SHORT-CIRCUIT PROTECTION
CIRCUIT
Each channel uses the short-circuit detection comparator (SCP) to always compare the error amplifier’s
output level to the reference voltage.
While DC/DC converter load conditions are stable on all channels, the short-circuit detection comparator
output remains at “L” level, and the CSCP terminal (pin 13) is held at “L” level.
If the load condition on a channel changes rapidly due to a short-circuit of the load, causing the output voltage
to drop, the output of the short-circuit detection comparator on that channel goes to “H” level.
This causes the external short-circuit protection capacitor CSCP connected to the CSCP terminal (pin 13) to
be charged at 1 μA.
Short-circuit detection time : tCSCP
tCSCP (s) =: 0.70 × CSCP (μF)
When the capacitor CSCP is charged to the threshold voltage (VTH =: 0.70 V) , the latch is set to and the external
FET is turned off (dead time is set to 100%) . At this time, the latch input is closed and CSCP terminal (pin
13) is held at “L” level.
The short-circuit detection from external input is capable by using −INS terminal (pin 8) . In this case, the
short-circuit detection operates when the −INS terminal voltage becomes the level of the threshold voltage
(VTH =: IV) or less.
Note that the latch is reset as the voltage at the VREF terminal (pin 9) is decreased to 1.27 V (Min) or less
by either recycling the power supply or setting the CTL terminal (pin 1) to “L” level.
24
DS04-27257-3E
MB39A123
• Timer-latch short-circuit protection circuit
Vo
FBX
R1
−
−INEX
Error
AmpX
+
R2
1.23 V (ch.1 : 1.0 V)
SCP
Comp.
+
+
−
1.1 V
1 μA
To each
channel drive
CSCP
CTL
13
VREF
CTL
CSCP
S
R
Latch
DS04-27257-3E
UVLO
X : Each channel
number
25
MB39A123
■ PROCESSING WHEN NOT USING CSCP TERMINAL
To disable the timer-latch short-circuit protection circuit, connect the CSCP terminal (pin 13) to GND in the
shortest distance.
• Processing when not using the CSCP terminal
26
13
CSCP
10
GND
DS04-27257-3E
MB39A123
■ SETTING THE DEAD TIME (ch.2 to ch.6)
When the device is set for step-up or inverted output based on the step-up, step-up/down Zeta method, step
up/down Sepic method, or flyback method, the FB terminal voltage may reach and exceed the triangular
wave voltage due to load fluctuation. If this is the case, the output transistor is fixed to a full-ON state (ON
duty = 100%). To prevent this, set the maximum duty of the output transistor.
When the DTC terminal is opened, the maximum duty is 92% (Typ) because of this IC built-in resistor which
sets the DTC terminal voltage. This is based on the following setting: 1MHz (RT = 6.8kΩ/CT = 100pF).
To disable the DTC terminal, connect it to the VREF terminal (pin 9) as illustrated below (when dead time is
not set).
• When dead time is set:
(Setting with built-in resistor:
1MHz [RT = 6.8kΩ/CT = 100pF] =: 92%)
• When dead time is not set:
9
“Open”
VREF
DTCX
DTCX
X : ch.2 to ch.6
X : ch.2 to ch.6
To change the maximum duty using external resistors, set the DTC terminal voltage by dividing resistance
using the VREF voltage. Refer to “• When dead time is set : (Setting by external resistors)”.
It is possible to set without regard for the built-in resistance value (including tolerance) when setting the
external resistance value to 1/10 of the built-in resistance or less.
Note that the VREF load current must be set such that the total current for all the channels does not exceed
1 mA.
When the DTC terminal voltage is higher than the triangular wave voltage, the output transistor is turned on.
The formula for calculating the maximum duty is as follows, assuming that the triangular wave amplitude
and triangular wave lower limit voltage are about 0.5 V and 0.4 V, respectively.
DUTY (ON) Max =:
Vdt =
Rb
Ra + Rb
Vdt − 0.4 V
0.5 V
× 100 (%)
× VREF (V) (condition : Ra <
R1
10
, Rb <
R2
10
)
Note : DUTY obtained by the above-mentioned formula is a calculated value. For setting, refer to “ON Duty
cycle vs. DTC terminal voltage”.
The maximum duty varies depending on the oscillation frequency, regardless of settings in built-in or external
resistors.
(This is due to the dependency of the peak value of a triangular wave on the oscillation frequency and RT.
Therefore, if RT is greater, the maximum duty decreases, even when the same frequency is used.)
DS04-27257-3E
27
MB39A123
Furthermore, the maximum duty increases when the power supply voltage and the temperature are high. It
is therefore recommended to set the duty, based on the “■ TYPICAL CHARACTERISTICS” data, so that it
does not exceed 95% under the worst conditions.
ON duty cycle vs. DTC terminal voltage
100
Ta = + 25 °C
VCC = CTL = 4 V
FB = 2 V
CT = 100 pF
95
ON duty cycle Dtr (%)
90
fosc = 200 kHz
fosc = 1 MHz
85
Calculated value
fosc = 1 MHz
80
75
fosc = 2 MHz
70
65
60
55
50
0.6
0.65
0.7
0.75
0.8
0.85
0.9
DTC terminal voltage VDTC (V)
• When dead time is set
(Setting by external resistors)
VREF
9
Ra
R1 : 131.9 kΩ
DTCX
Vdt
Rb
GND
To PWM Comp.X
R2 : 97.5 kΩ
10
X: ch.2 to ch.6
28
DS04-27257-3E
MB39A123
Setting example (for an aim maximum ON duty of 80% (Vdt = 0.8 V) with Ra = 13.7 kΩ and Rb = 9.1 kΩ)
• Calculation using external resistors Ra and Rb only
Vdt =
Rb
Ra + Rb
× VREF =: 0.80 V
DUTY (ON) Max =:
Vdt − 0.4 V
0.5 V
× 100 (%) =: 80% ⋅ ⋅ ⋅ ⋅ (1)
• Calculation taking account of the built-in resistor (tolerance ± 20%) also
Vdt =
(Rb, R2 Combined resistance)
(Ra, R1 Combined resistance) + (Rb, R2 Combined resistance)
DUTY (ON) Max =:
Vdt − 0.4 V
0.5 V
× VREF =: 0.80 V ± 0.13%
× 100 (%) =: 80% ± 0.2% ⋅ ⋅ ⋅ ⋅ (2)
Based on (1) and (2) above, selecting external resistances to 1/10th or less of the built-in resistance enables
the built-in resistance to be ignored.
As for the duty dispersion, please expect ± 5% at (fosc = 1 MHz) due to the dispersion of a triangular wave
amplitude.
■ PROCESSING WHEN NOT USING ch.4 INV AMP
Short-circuit the - INA terminal (pin 19) and OUTA terminal (pin 18) in the shortest distance when not using
ch.4 INV Amp.
• When not using ch.4 INV Amp
DS04-27257-3E
19
−INA
18
OUTA
29
MB39A123
■ OPERATION EXPLANATION WHEN CTL TURNING ON AND OFF
When CTL is turned on, internal reference voltage VR and VREF generate. When VREF exceeds each
threshold voltage (VTH) of UVLO (under voltage lockout protection circuit) , UVLO is released, and the
operation of output drive circuit of each channel becomes possible.
When CTL is off, the CS and CSCP terminals are always set to "L" as soon as output drive circuit of each
channel is fixed to full off even if UVLO is released. When VR and VREF fall and VREF decreases the
threshold voltage (VRST) of UVLO (under voltage lockout protection circuit), output drive circuit becomes
the UVLO state.
• CTL block equivalent circuit
SCP
ch.1 to ch.4
To output drive circuit
H : Possible to operate
L : Forced stop
H : at SCP
UVLO1
H : UVLO release
CS1 to CS4
To charge/discharge circuit
H : Possible to charge
L : Forced discharge
To SCP circuit
H : Possible to
operate SCP
L : CSCP
terminal low
ch.5, ch.6
To output drive circuit
H : Possible to operate
L : Forced stop
UVLO2
CS5, CS6
To charge/discharge circuit
H : Possible to charge
L : Forced discharge
H : UVLO release
Error Amp reference
1.0 V/1.23 V
48 VCC
bias
VREF
VR
Power
ON/OFF
CTL
1
CTL
9
VREF
30
DS04-27257-3E
MB39A123
• Operation waveform when CTL turning on and off
H ∗2
∗1
CTL
L
1.23 V
VR
0V
2V
VREF
VTH1
VTH2
VRST1
VRST2
0V
H
UVLO1
UVLO state
L
UVLO release
UVLO state
UVLO release
UVLO state
H
UVLO2
ch.1 to ch.4
Output Drive
circuit control
ch.5, ch.6
Output Drive
circuit control
UVLO state
L
H
Fixed full off
L
Possible operate
Fixed full off
Possible operate
Fixed full off
H
Fixed full off
L
*1 : As shown in the sequence on the above figure, when turning off CTL while each CHCTL is turned on,
intermission state may be generated due to noise around the CTL threshold voltage. To prevent this, it is
recommended to turn off CTL with a slope of -1 V/50 μs or higher so that the CTL voltage does not remain
in the specified threshold voltage range (0.5 V to 1.5 V) . If the above slope setting is difficult to achieve, it
is recommended to turn off CTL after turning off all CHCTLs.
Moreover, a voltage remains in the FB terminal, when VCC is turned off at the same time as CTL and CHCTL,
or when VCC is turned off at the same time as CTL while each CHCTL is still turned on. As this may lead to
an overshoot upon restart, it is recommended to turn off VIN and CTL after turning off all the CHCTLs to reduce
FB to 0 V.
Likewise, it is recommended to turn off CHCTL with a slope of -1 V/50 μs or higher.
*2 : When CTL and CHCTL are turned on at the same time, or when CTL is turned on while each CHCTL is turned
on, there exists a period (approx. 200 ns) when the error Amp output voltage (FB) is higher than the triangular
wave voltage (CT) upon the startup of VREF. As a result, when UVLO is released and then the Output Drive
circuit of each channel becomes operable, the output transistor is turned on, generating a voltage at the DC/
DC converter output.
The voltage to be generated (Vop) depends on L, Co and VIN. (See • Vo characteristics (Vop) when turning
on CTL at CHCTL ON.)
It should be noted that the above event does not occur when CTL is turned on while CHCTL is turned off.
Therefore, it is recommended to turn on each CHCTL after turning on CTL.
DS04-27257-3E
31
MB39A123
• Vo characteristics (Vop) when turning on CTL at CHCTL ON
At evaluating Fujitsu EV board system
Step-down operation
VIN = 7.2 V
Vo = 5 V
L = 15 μH
Co = 2.2 μF
Load = 50 Ω
CHCTL = ON
CTL[V] 10
5
0
CS[V]
CTL
2
2
CS
Vo[V]
1
5
4
0
3
3
2
1
0
Vo
Generated voltage
Vop =: 0.4 V
L
VD
Vo
IL
1
D
0
2
4
6
8
10
12
14
Co
20 t[ms]
16 18
TON
Generated output voltage - Output capacitor value
600
Generated output voltage (mV)
At evaluating Fujitsu EV board system
VD VIN
500
Ta = + 25 °C
VCC = CTL = 7.2 V
400
When no load is
applied
IL
300
200
L = 6.8 μH
This energy Q
moves to Co
100
L = 68 μH
Vo
Vop
0
1
10
Output capacitor value Co (μF)
32
Ip = VIN / L × TON
Ip
100
Vop = Q / Co
DS04-27257-3E
MB39A123
■ ABOUT THE LOW VOLTAGE OPERATION
1.7 V or more is necessary for the VCC terminal (pin 48) and the VCCO terminal (pin 36) for the self-power
supply type to use the step-up circuit as the start voltage.
Even if thereafter VIN voltage decreases to 1.5 V, operation is possible if the VCC terminal (pin 48) voltage
and the VCCO terminal (pin 36) voltage rise to 2.5 V or more after start-up. However, it is necessary not to
exceed the maximum duty set value by the duty due to the VIN decrease. Including other channels, execute
an enough operation margin confirmation when using it.
VIN
A
R1
R2
21
−INE5
Error
Amp5
−
+
+
1.23 V
CS5
20
Max Duty
92% ± 5%
Step-up A
<<ch.5>>
VREF
PWM
Comp.5
Drive5
+
+
N-ch
−
0.9 V
0.4 V
VCCO
36
30
Vo5
(5 V)
OUT5
VCC
48
DTC5
23
DS04-27257-3E
33
MB39A123
■ I/O EQUIVALENT CIRCUIT
• Control block (CTL, CTL1 to CTL6)
• Reference voltage block
VCC
VCC 48
1.23 V
ESD
protection
element
+
−
ESD
protection
element
CTLX
VREF
86 kΩ
ESD
protection
element
223 kΩ
9
79 kΩ
124 kΩ
GND
GND 10
• Soft-start block
VREF
(2.0 V)
• Short-circuit detection block
• Short-circuit detection
comparator block
VCC
VCC
VREF
(2.0 V)
100 kΩ
VCC
CSX
−INS 8
VREF
(2.0 V)
(1 V)
2 kΩ
13 CSCP
GND
GND
• Triangular wave oscillator block (RT)
VREF
(2.0 V)
0.64 V
GND
• Triangular wave oscillator block (CT)
VREF
(2.0 V)
VCC
VCC
+
−
CT 12
11 RT
GND
GND
• Error amplifier block (ch.1 to ch.6)
VCC
VREF
(2.0 V)
−INEX
CSX
FBX
1.0 V (ch.1)
1.23 V (ch.2 to ch.6)
GND
X : Each channel number
(Continued)
34
DS04-27257-3E
MB39A123
(Continued)
• Inverting amplifier block
VCC
VREF
(2.0 V)
OUTA
−INA 19
18
GND
• PWM comparator block
• Output block
VCC
VCCO 36
VREF
(2.0 V)
131.9 kΩ
FB2 to FB6
CT
OUTX
DTCX
97.5 kΩ
GNDO 28
GND
X : Each channel number
DS04-27257-3E
35
MB39A123
■ USAGE PRECAUTIONS
• Printed circuit board ground lines should be set up with consideration for common impedance.
• Take appropriate static electricity measures.
• Containers for semiconductor materials should have anti-static protection or be made of conductive
material.
• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ between body and ground.
• Do not apply a negative voltages.
• The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause
abnormal operation.
36
DS04-27257-3E
MB39A123
■ ORDERING INFORMATION
Part number
MB39A123PMT
Package
Remarks
48-pin plastic LQFP
(FPT-48P- M49)
■ EV BOARD ORDERING INFORMATION
EV board part No.
MB39A123EVB-02
DS04-27257-3E
EV board version No.
Remarks
Board Rev.1.0
LQFP-48P
37
MB39A123
■ RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION
The LSI products of FUJITSU SEMICONDUCTOR with “E1” are compliant with RoHS Directive, and has
observed the standard of lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB),
and polybrominated diphenyl ethers (PBDE) .
The product that conforms to this standard is added “E1” at the end of the part number.
■ MARKING FORMAT (LEAD FREE VERSION)
M B3 9A123
XXXX XXX
E1
INDEX
LQFP-48P
(FPT-48P-M49)
Lead Free version
38
DS04-27257-3E
MB39A123
■ LABELING SAMPLE (LEAD FREE VERSION)
Lead-free mark
JEITA logo
MB123456P - 789 - GE1
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
JEDEC logo
G
Pb
QC PASS
PCS
1,000
MB123456P - 789 - GE1
2006/03/01
ASSEMBLED IN JAPAN
MB123456P - 789 - GE1
1/1
0605 - Z01A
1000
1561190005
The part number of a lead-free product has
the trailing characters “E1”.
DS04-27257-3E
“ASSEMBLED IN CHINA” is printed on the label
of a product assembled in China.
39
MB39A123
■ MB39A123PMT RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL
[FUJITSU SEMICONDUCTOR Recommended Mounting Conditions]
Item
Condition
Mounting Method
IR (infrared reflow) , warm air reflow
Mounting times
2 times
Storage period
Storage conditions
Before opening
Please use it within two years after
manufacture.
From opening to the 2nd
reflow
Less than 8 days
When the storage period after
opening was exceeded
Please process within 8 days
after baking (125 °C ± 3 °C,24H+2H/-0H) .
Baking can be performed up to two times.
5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
[Mounting Conditions]
(1) IR (infrared reflow)
260 °C
255 °C
170 °C
to
190 °C
(b)
RT
H rank : 260 °C Max
(a) Temperature Increase gradient
(b) Preliminary heating
(c) Temperature Increase gradient
(d) Actual heating
(d’)
(e) Cooling
(a)
(c)
(d)
(e)
(d')
: Average 1 °C/s to 4 °C/s
: Temperature 170 °C to 190 °C, 60 s to 180 s
: Average 1 °C/s to 4 °C/s
: Temperature 260 °C Max; 255 °C or more, 10 s or less
: Temperature 230 °C or more, 40 s or less
or
Temperature 225 °C or more, 60 s or less
or
Temperature 220 °C or more, 80 s or less
: Natural cooling or forced cooling
Note : Temperature : the top of the package body
(2) JEDEC condition : Moisture Sensitivity Level 3 (IPC/JEDEC J-STD-020D)
40
DS04-27257-3E
MB39A123
(3) Manual soldering (partial heating method)
Item
Storage period
Storage conditions
Mounting conditions
Condition
Before opening
Within two years after manufacture
Between opening and mounting
Within two years after manufacture
(No need to control moisture during the
storage period because of the partial heating
method.)
5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
Temperature at the tip of a soldering iron: 400 °C Max
Time: Five seconds or below per pin*
*: Make sure that the tip of a soldering iron does not come in contact with the package body.
DS04-27257-3E
41
MB39A123
■ PACKAGE DIMENSIONS
48-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
7.00 mm × 7.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.17 g
(FPT-48P-M49)
48-pin plastic LQFP
(FPT-48P-M49)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
9.00±0.20(.354±.008)SQ
*7.00±0.10(.276±.004)SQ
36
0.145±0.055
(.006±.002)
25
24
37
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
13
48
"A"
0°~8°
1
0.50(.020)
(Mounting height)
.059 –.004
INDEX
0.10±0.10
(.004±.004)
(Stand off)
12
0.22±0.05
(.008±.002)
0.08(.003)
0.25(.010)
M
0.60±0.15
(.024±.006)
C
2010 FUJITSU SEMICONDUCTOR LIMITED HMbF48-49Sc-1-2
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please check the latest package dimension at the following URL.
http://edevice.fujitsu.com/package/en-search/
42
DS04-27257-3E
MB39A123
MEMO
DS04-27257-3E
43
MB39A123
FUJITSU SEMICONDUCTOR LIMITED
Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,
Kohoku-ku Yokohama Kanagawa 222-0033, Japan
Tel: +81-45-415-5858
http://jp.fujitsu.com/fsl/en/
For further information please contact:
North and South America
FUJITSU SEMICONDUCTOR AMERICA, INC.
1250 E. Arques Avenue, M/S 333
Sunnyvale, CA 94085-5401, U.S.A.
Tel: +1-408-737-5600 Fax: +1-408-737-5999
http://us.fujitsu.com/micro/
Asia Pacific
FUJITSU SEMICONDUCTOR ASIA PTE. LTD.
151 Lorong Chuan,
#05-08 New Tech Park 556741 Singapore
Tel : +65-6281-0770 Fax : +65-6281-0220
http://sg.fujitsu.com/semiconductor/
Europe
FUJITSU SEMICONDUCTOR EUROPE GmbH
Pittlerstrasse 47, 63225 Langen, Germany
Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/semiconductor/
FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.
30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District,
Shanghai 201204, China
Tel : +86-21-6146-3688 Fax : +86-21-6146-3660
http://cn.fujitsu.com/fss/
Korea
FUJITSU SEMICONDUCTOR KOREA LTD.
902 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fsk/
FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fsp/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any
third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right
by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or
other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in
nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in
weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of overcurrent levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations
of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department
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