I-A Modulated Digitally Controlled Non-Inverting

I-A  Modulated  Digitally  Controlled Non-Inverting
I-A Modulated Digitally Controlled Non-Inverting
Buck-Boost Converter for
WCDMA RF Power Amplifiers
Rajarshi Paul, Luca Corradini and Dragan Maksimovic
Colorado Power Electronics Center
ECE Department, University of Colorado, Boulder, CO 80309-0425
frajarshi .paul, luca~corradini, maksimov I @colorado.edu
Abstract- This paper focuses on the non-inverting buckboost converter supplying an adjustable DC voltage to a
WCDMA RF power amplifier (RFPA) in order to improve the
system efficiency under different transmitted RF power levels.
It is shown that precise output voltage positioning and low
output voltage ripple over a wide output voltage range,
including buck, boost and buck/boost transition modes, can be
accomplished using 1_-A modulation in combination with a
small, low-power, low-resolution DPWM core. A two-mode
digital controller is presented, in which the compensator
parameters are changed upon buck/boost mode transitions in
order to improve closed-loop dynamic performance. Results
are verified on an experimental test bed that consists of a
prototype 0.5 Fun CMOS chip that integrates power MOSFETs,
drivers and dead-time control logic, and the digital controller
implemented on an FPGA. The worst case output voltage
ripple over buck, boost and mode transition region is within
35mV and the output voltage transients meet the WCDMA
RFPA settling time requirements.
1.
70O
Vk
V.
INTRODUCTION
Non-inverting buck-boost DC-DC power converter is
currently gaining importance in mobile handsets, where it is
used to provide wide adaptive power supply (from 800 mV
to 3.6 V) to WCDMA RF power amplifiers (RFPA) from a
2.7-5.5 V Li-Ion battery, as shown in Fig. 1. As opposed to
operating the converter in buck-boost mode, a preferred
solution is to operate in either buck (step-down) or boost
(step-up) mode, resulting in lower inductor current and thus
allowing smaller size inductor and improved efficiency.
Various realizations of controllers for the non-inverting
buck-boost converter have been discussed in [1-5]. It has
been shown that limitations of standard analog pulse-width
modulator (PWM) circuit realizations can cause
uncontrolled pulse skipping and significantly increased
output voltage ripple when the converter operates around
the buck/boost mode transition [6]. Increased propagation
delay of analog PWM comparators around the corners of the
PWM ramp limits the minimum achievable turn-off time
(and hence maximum buck duty cycle and minimum boost
duty cycle) at SW I and SW2 nodes in Fig. 1. In closed loop
operation, the PWM discontinuity around 100% buck or 0%
boost duty ratio causes PWM pulse skipping (i.e. limit
cycling), which can result in much increased output voltage
An -
-0 -
Odr--
On., DWM
-
-
-
-
-
dcrr 2 made
o
I
mode
cmman~d
-
-
ADC
-
FB
ýV,,,
(P,.
Fig. 1. Non-inverting bock-boost power converter using 2 d order Y-A
modulated DPWM. Switching fr-equency f. = 1.56 MHz, L = 2.2 pHf,
C = 10 liF, 1Io,_,.. = 500 mA, 1',,, = 2.7-5.5V. Also shown is the die
photo of the fabricated power stage and the driver IC in 0.5 gm CMOS
process.
ripple. For example, a minimum achievable turn-off time of
4Ons (or 96% maximum buck duty ratio at 1 MHz switching
frequency) has been shown to result in the ripple amplitudes
as high as 172 mV around the buck/boost mode transition
[6]. This is a significant problem in noise sensitive REPA
applications [7, 8]. The second difficulty associated with
analog controller realizations is related to the requirement
for wide bandwidth closed-loop regulation over the wide
range of output voltages, including the buck and boost
modes with significantly different small-signal converter
dynamics.
The objectives of this paper are to show digital controller
realization techniques aimed at overcoming the difficulties
identified in analog controllers, without compromising the
This work has heen sponsored through the Colorado Power Electronics Center.
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Fig. 2 illustrates standard buck-boost operation of the
non-inverting buck-boost converter. During sub-interval 1
(DT,), switches SlI and S4 are on, while switches S2 and S3
are off. During sub-interval 2 ((l-D)T,), S2 and S3 are on,
while S1 and S4 are off. The DC conversion ratio as a
= D/(l- D). An
function of the duty cycle D is M =,,,V
controller small size or low power consumption
requirements, which are critical for low-power portable
applications. A two-mode PID compensator is presented, in
which the compensator coefficients are selected according
to the converter operating mode (i.e. buck or boost) and
properly switched upon mode transitions. It is shown how
the proposed controller maintains improved closed-loop
dynamic performances compared to a conventional, single
mode PID. Furthermore, following the approach described
in [9], a small, low-resolution (4-bit), low-power DPWM
core is combined with a sigma-delta (I-A) modulator to
achieve an effective 11 -bit DPWM resolution over buck and
boost modes.
Section II introduces the non-inverting buck-boost power
converter and its RFPA application. Section III describes
the prototype chip and the experimental test bed. Digital
PWM realization for the non-inverting buck-boost converter
is described in Section IV, while closed-loop operation of
the two-mode PID compensator is described in Section V.
Results are experimentally verified on a test bed that
consists of a prototype 0.5 Vim CMOS chip (die photo
shown in Fig. 1) that integrates power MOSFETs, drivers
and dead-time control logic, and a digital controller
implemented on an FPGA development platform.
Experimental results presented in Section VI show that the
output voltage ripple is reduced to less than 35 mV at all
operating points including the buck/boost mode transition.
2.51
buck-boost
-
2
Normnalized
Average
Inductor Current
IL101-)
boost
buck
.
07
0.8
......
1.0
0.9
1.1
1.2
1.3
M=Vd.N
Fig. 4. Normalized average inductor current as a function of the DC
conversion ratio M for buck-boost and for buck or boost operation of
the converter. Vi., = 2.7-5.5 V, V-, = 3.6 V, load current is constant.
alternative is to operate the converter as buck (to achieve
step-down conversion ratio) or boost (to obtain step-up
conversion ratio). Fig. 3(a) shows operation of the noninverting buck-boost converter in the buck mode: switches
S I and S2 are operated at buck duty cycle Db,,,k, while S3 is
on and S4 is off at all times. The step-down voltage
conversion ratio is M = Db,5 ,k. In the boost mode, S3 and S4
are operated with a boost duty cycle Dbos, while SI is on
and S2 is off, as shown in Fig. 3(b). The step-up conversion
ratio is M = I/(I-Db,0 ). As shown in Fig. 4, buck or boost
operation results in significantly lower current stresses
compared to buck-boost operation. As a result, the inductor
size and the losses are significantly smaller, which is why
the buck/boost operation is preferred in portable
applications.
Fig. 1 shows the application of the non-inverting buckboost power converter for supplying DC power to an RFPA.
By adjusting the reference command (Vref), the supply
voltage of the RFPA (V,,) is adaptively controlled to
maximize efficiency and linearity of the RFPA under
different transmitted power requirements. For example,
typical V, requirements are 3.4 V during data transmission,
and 800 mV during voice transmission [11]. The WCDMA
power specification requires that, in response to a step
reference command, the output voltage of the power
converter settles within 50pis [12].
111.NON-INVERTING BUCK-BOOST FOR WCDMA RF POWER
AMPLIFIER APPLICATION
curren
Fig. 2. Buck-boost operation of 4-switch power converter
Figure 3(a). Buck-mode sub-intervals I and 2.
iiI. NON-INVERTING BUCK-BOOST PROTOTYPE IC AND
EXPERIMENTAL TEST BED
The power stage and the driver with dead time control has
been implemented in a 0.5 gim CMOS process IC with
Figure 3(b). Boost-mode sub-intervals I and 2.
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2 mnim2 active area as shown in Fig. 1. The buck and boost
PWM pulses, cbarck and cl,, generated from the digital
controller are fed to the inputs of the drivers with dead-time
control circuitry on the prototype power stage IC.
Experimentally, the drivers and the power transistors can
produce SWI and SW2 pulses as short as 10 ns, with about
4 ns dead time. A CMOS power switch (PMOS and NMOS
in parallel) is used as the boost high-side power switch as
shown in Fig. I to allow proper operation over the entire
range of output voltages (800 mnV to 3.6 V). To properly
turn-off the high-side boost PMOS during boost operation,
I1-
t
Fig. 7. Implementation details of an 11 -bit, 2 nd order Y-A DPWM having
ndp_,,-bit core for generating both buck and boost control signals. fldp_,= 4
in actual implementation.
and small area in low-power portable applications, an
effective resolution enhancement approach based on modulation has been described in [9, 10]. As shown in
Fig. 7, this approach is adopted here and applied to the noninverting buck/boost converter to demonstrate low-ripple
precise output voltage positioning using an area and power
efficient low-resolution DPWM core.
VO
Pmos
Sw('oh
Po,,r
1~5OT10mv
Fig. 5. Details of boost high side PMOS driver for proper turn off during
boost mode (as implemented on the experimental ICprototype).
.g. 100
the boost PWM pulses are level shifted with supply from
the output voltage V,0 of the converter and then fed to a
driver (chain of inverters) as shown in Fig. 5. The
experimental prototype test board, with the prototype IC in
the center, is shown in Fig. 6.
a)
0(
C'3
0
25 mV
10 my
I
2
4
3
Number of core DPMVVI bits
(fldp,,-)
Fig. 8. Simulation result showing peak to pea output voltage ripple
(zi V,) as a function of number of core DPWM bits (04,.,,).
The extra output voltage ripple produced by the X-A
DPWM compared to an ideal high-resolution DPWM
depends on the number of bits nd. of the core DPWM.
Fig. 8 summarizes the output voltage ripple as a function of
the core DPWM resolution at a worst-case operating point.
Note that the ideal output voltage ripple with an ideal
analog PWM at this operating point is 2mV. A 4-bit core
DPWM is chosen for implementation with the X-A
modulator, allowing an 11 -bit high-resolution duty cycle
command, as shown in Fig. 7.
In the experimental prototype, the switching frequency is
= 1.56 MHz, The most significant bit (MSB) of a 5-bit
command dLR to the modulator decides the mode (buck or
boost) of operation. The 4 least significant bits (LSB) are
the duty-cycle command to the 4-bit counter-based DPWM
core. The system clock frequency is 2'4f, = 25 MHz. In buck
mode, for dLR[n] less than or equal to 1, the boost control
signal cb,,,, has 0% duty cycle. Hence, referring to Fig. 1,
power-switch 02 is always on and 01 is always off. In
Fig. 6. Experimental prototype board for the power-stage IC and
externally fed PWM pulses from a digital controller implemented on
an FPGA.
IV. I-A MODULATED DIGITAL PWM FOR THE
NON-INVERTING BUCK-BOOST CONVERTER
A high-resolution DPWM is required for precise output
voltage regulation. Design of a high resolution hardware
DPWM amounts to a trade-off between high clock rate
(using a counter-based DPWM architecture), and chip area
(using a delay-line based DPW`M architecture) [13].
Motivated by the requirements of low power, low clock rate
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V. TWO-MODE
DIGITAL COMPENSATOR DESIGN AND
CLOSED LOOP OPERATION
..
.:SW ' ..
To demonstrate closed loop operation, the non-inverting
buck-boost power stage IC is fed with buck and boost PWM
pulses generated from a two-mode digital compensator as
shown in Fig 1. The input voltage '4,n is 2.7-5.5 V and the
regulated output voltage can be set between 0.8 and 3.6 V
with 500 mA maximum load current. The filter components
are L = 2.2 jiH, C = 10 jiF and the switching frequency is
f,= 1.56 MHz. The voltage sensing ADC has a 32 mV LSB
resolution. The digital controller is implemented on an
FPGA with 25 MHz system clock frequency.
(buck switch node)
1-0
24
Output voltage (Vo)ý
u-iR
Chi
=j
5
2.00 V v ChZ
2.O0OV %
2.00 V % M12.00MS Chi X
OutputVoltage
W.a)
-3.36 V
Fig. 9. Experimental waveforms using 4-bit DPWM core showing
low resolution output voltage as duty cycle is ramped from buck to
boost mode. Input voltage is 3V.
~'Jj
ADCsa plIng
instant
(buck switch nlode)
BuckP5W pulse
td
6lons
Tý 640ns
DT- --......
..
(bolost swith node).IIIHIIHIII!111111
T
BoostPWMpulse (i17
(C-.)
Fig. 11. Waveforms illustrating trailing edge modulation with ADC
sampling during off-time. Note that the PWM pulse resolution is 4Ons.
-
Output voltage (l/,)]
20
Chi~-2:66~'
=
V, t62 -
2.00sV to
6kd V
V~ W32.11bmsi -Chl ýf-3
00
-20
Fig. 10. Waveform showing high resolution output voltage using I-A
modulated buck/boost DPWM as duty cycle command is ramped from
buck to boost mode. Input voltage is 3V.
r
-40
boost mode, for d,.,[n] greater than or equal to 1, the buck
PWM control signal cbu,,k has 100% duty ratio, power-switch
UI is always on and power-switch U2 is always off.
Fig. 9 shows the output voltage and the switch-node
waveforms as the command du? is swept from buck mode to
boost mode with no Y.-A modulation in front of the DPWM.
The coarse DPWM resolution, with pulse-width steps of
40 ns results in large output voltage steps. In closed-loop
operation, resulting limit cycling oscillations would produce
unacceptably large output voltage ripple, similar to the
behavior observed with analog controllers around the mode
transition [6]. Using the second-order Y-A modulator in
front of the 4-bit DPWM as shown in Fig. 7 enables highresolution (11-bit) duty-cycle command d[n]. An
experimental sweep of the high-resolution command d is
shown in Fig. 10, demonstrating high-resolution output
voltage positioning in buck and boost modes.
978-1-422-2812-0/09/$25.00 ©02009 IEEE53
0k1k10k50
Frequency (Hz)
Fig. 12. Illustration of wide differences in G,d
1(z) in buck and boost
operating modes.
The digital compensator design is based on exact smallsignal discrete-time model for digitally controlled DC-DC
converters which takes into account ADC sampling,
modulator effects and delays in the control loop [14]. For
both buck and boost modes, the ADC samples the output
voltage 6Ons before the rising edge of the trailing-edge
modulated DPWM output signal. Fig. 11I illustrates the
delay between the ADC sampling of the output voltage and
536
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A two-mode PID compensator is proposed to improve the
closed-loop performance. The two-mode compensator is
designed to achieve the same cross-over frequency
(f,~=f,112) and the same phase margin in both buck and
boost modes as shown in Fig. 14. In the digital controller,
the digital compensator coefficients switch from buck to
boost PD) coefficients as the converter changes from buck
to boost mode. The MSB (111Ph bit) of the high resolution
duty command dun] as shown in Fig 7 is used as the control
signal (Pmode in Fig. 1) to switch the two-mode PD)
coefficients between buck and boost PID. Table I
summarizes the improvement in phase-margin (0m), crossover frequency (f,) and the gain margin (GM) by using the
two-mode PD) compensator compared to the fixed
conservative compensator.
-20
20
buck
-90
-180 12,-
-270:a
100
10k
Frequency (Hz)
1k
look
500 k
Table 1.Summary of small-signal loop-gain responses for buck and boost
modes using a fixed and two-mode PD) compensator design.
Fig. 13. Illustration of differences in loop-gain plot for buck and boost
operating modes using a fixed conservative PID compensator.
Comnpensator
the modulated edge of the output PWM pulse. The delay of
td = (60 ns + DT,) is used to obtain the small-signal discretetime duty-cycle to output voltage transfer function G~d(z)
and is taken into account in the design of the digital PD)
compensator.
-0.988Xz -0.871)
Gd-~)=21.8(z
Z(
)
Mode
f, (kHz)
0.,
GM
buck
boost
130
124
500
16.5 dB
390
11.0 dB
buck
130
500
16.5 dB
boost
126
500
13.5 dB
Fixed PID
GAW=~) 21.8(z-0.988Xz-0.871)
Z(z I)
buck-PID
9
60
G~W=2 1.01(z -0. 13Xz-0.880)
Z(Z1)
boost PID__________
40
20
VI.
____
EXPERIMENTAL RESULTS
0
The two major objectives of this paper are i) low-ripple
precise output voltage positioning using an area and power
efficient DPWM and ii) improved output voltage transient
performance using a two-mode digital compensator.
Experimental verification results are reported in this section.
The steady-state waveforms illustrating the output voltage
ripple in the buck, boost and the buck/boost mode transition
are shown in Figs. 15-17, respectively. The figures also
-20
0
buck.
-90
-180
2
100
n,=2.7V
1k
.
b.-
10k
look
500k
Output volta e ripl
Frequency (Hz)
Fig. 14. Loop-gain plot of buck and boost operating m,odes
maintaining similar '1P,andf, using a 2-mode P11) compensator design.
For the purpose of designing a high performance digital
controller, the change in G04(z) from buck to boost operating
conditions, as illustrated in Fig. 12, requires attention. In
particular, the boost right-half-plane (RHP) zero causes
additional phase margin (0 ) loss, as shown in
the loop-gain magnitude and phase responses of Fig. 13,
based on a fixed, conservatively designed PH) compensator.
Also, the DC gain and the resonant frequency of G0,Az)
change as the converter switches between buck and boost
mode. Fig. 13 shows the effect of this change in G~d(z) on
the loop-gain response for worst-case buck and boost
operating points when using a fixed conservative
compensator in both modes.
978-1-422-28 12-0/09/$25.00 02009 IEEE53
A4
I,
(buck switch node)
$W2
(boost *Witch node)
I
Nh3
%
116317N'
-
*,f0l
* £U
, ur *,
ýumvr
ýuvI~
s .±dJ
U
Fig. 15. Steady state output voltage ripple (ac coupled) during
buck operation with V1,=2.7V and V,=2.2V.
537
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ggý
10--
10
9.5
..
.
..0
.
7..
@9
.n
~8.5*
*
0
'000
0
.~7
*-
buck/boosi
made transition
boast
o 6.5ý
6
2.8
buclý
Vj=3.05 V
-
__
2.9
3
V
3.1
3.2
3.3
Vi.~ MV
Fig. 16. Steady state output voltage ripple (ac coupled) during
boost operation with Vi,=2.7V and V,,=3.2V.
Fig. 18. Experimentally observed worst caae output voltage ripple over
buck, boost and mode transition region as the input voltage is varied
around a fixed output voltage of 3.05V.
Fig. 17. Steady state output voltage ripple (ac coupled) during buck/boost
mode transition operation with Vi,=2.7V and Vi=2.65V.
Fig. 19. Buck output voltage transient from I to 1.6V with
Vin=2.7V, 11...0.
experimentally observed output voltage ripple around the
mode transition for V, = 3.05V and V11. = 2.8 to 3.3 V.
In the experimental closed loop operation, the reference
Vref to the power converter is given digitally within the
FPGA. For step reference transients, the digital reference is
ramped at a constant rate of 80 mV/gs. Fig. 19 shows the
output voltage transient during buck operation when the
output voltage (V,,) changes from I V to 1.6 V with a
settling time of 20 gs. Similarly, Fig. 20 shows the output
voltage transient within boost operating condition from
V, = 2.7 V to 3.3 V for Vi,, = 2.7 V with a 25 ps settling time.
Finally, Fig. 21 illustrates the output voltage transient with a
settling time of 40 pis for V. = 2.2 V in buck mode to
V, = 3.4 V in boost mode, with Vi,, = 2.7 V. Note that the
two-mode controller adaptively switches the compensator
coefficients from buck PU) to boost PID as it changes from
buck to boost operating mode. The advantage of using the
two-mode compensator is that the output voltage can be
show the node voltages (PWM pulses) at SWl (buck switch
node) and SW2 (boost switch node), with reference to Fig. 1.
Note how the PWM pulses are modulated by the E-A
DPWM during buck/boost mode transition, which injects a
modulation on the output voltage ripple. Particularly, during
the mode transition, the converter switches between the
buck and boost modes in a pattern decided by the 2 nd order
Y.-A modulator, resulting in a relatively small output voltage
ripple. To critically observe the worst-case output voltage
ripple during buck/boost mode transition, the output voltage
is kept constant and the input voltage Vi,,1 is swept around the
mode transition by ±250 mV with a step of 10 mV. The
worst case output voltage ripple during mode transition
under all operating conditions, measured using the
oscilloscope "envelope" acquisition mode, is found to be
within 10 mV (or within 35 mV if very short ground
bounces and spikes are included). Fig. 18 summarizes the
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compensator parameters over buck and boost modes, thus
improving closed-loop dynamic performance.
Results are verified on an experimental test bed that
consists of a prototype 0.5 pm CMOS chip that integrates
power MOSFETs, drivers and dead-time control logic, and
the digital controller implemented on an FPGA.
positioned with improved performances in terms of settling
time and damping.
+
Output voltage, (Q
4-
REFERENCES
J. Chen, D. Maksimovic, R. Erickson, "Buck-boost PWM converters
having two independently controlled switches," in Pine. IEEE PESC
Conf., 2001, vol. 2, pp. 736 - 741.
[2] M. Gaboriault, A. Notman, "A high efficiency, non-inverting, buckboost DC-DC conventer," in Proc. IEEE APEC Conf., 2004. vol. 3.
pp. 1411- 1415.
[3] B. Sahu, G. A. Rincon-Mora, "A high efficiency WCDMA RF power
amplifier with adaptive, dual-mode buck-boost supply and biascurrent control," IEEE Microwave and Wireless Components Letters.
vol. 17, issue 3, pp. 238-240, Mar. 2007.
[4] P. Midya, K. Haddad, M. Miller, "Buck or boost tracking power
converter," IEEE Power Electronics Letters, vol. 2, issue 4, pp. 131 134, Dec. 2004.
[5] A. Prodic, D. Maksimovic, "Digital PWM controller and current
estimator for a low-power switching converter," in Proc. IEEE
COMPEL Conf., 2000, pp. 123-128.
[6] R. Paul, D. Maksimovic, "Analysis of PWM nonlinearity in noninverting buck-boost power converters," in Proc. IEEE PESC Conf.
2008, pp. 374 1-3747.
[7] A. V. Bezooijen, R. Mabmioudi, A.H.M van Roermund, "Adaptive
methods to preserve power amplifier linearity under antenna
mismatch conditions," IEEE Trans. on Circuits and Systems I, vol. 52,
issue 10. pp. 2 1 0 1 - 2108, Oct. 2005.
[8] F. H. Raab, P. Asbeck, S. Cripps, P. B. Kenington, Z. B. Popovic, N.
Pothecary, J. F. Sevic, and N. 0. Sokal, "Power amplifiers and
transmitters for RF and microwave," IEEE Trans. Microw. Theory
Tech., vol. 50, no. 3, pp. 814-826, Mar. 2002.
[9] Z. Lukic, N. Rahman, A. Prodic, "Multibit Z-A PWM digital controller
IC for DC-DC converters operating at switching frequencies beyond
10 MHz," IEEE Trans. Power Electron., vol. 22, no. 5, pp. 16931707,2007.
1101 M. Norris, L. Marco, E. Alarcon and D. Maksimovic, "Quantization
noise shaping in digital PWM converters," in Proc. IEEE PESC conf.,
pp. 127-133, 2008.
[11] Maxim application note AN-1205, "W-CDMA Power Supply
Dramatically Improves Transmit Efficiency" -http://www.maximic.com~appnotes.cfm~an..pkI1205
[12] www.3gpp.org., "User Equipment (UE) radio transmission and
reception (FOD) specification-TS 25.101".
[13] A. Syed, E. Ahmed, D. Maksimovic, and E. Alarcon, "Digital pulse
width modulator architectures," in Proc. IEEE PESC'04 conf., 2004,
pp. 4689-4695.
[14] D. Maksimovic and R. Zane, "Small-signal discrete-time modeling of
digitally controlled PWM converters," IEEE Trans. Power Electron.,
vol. 22, no. 6. pp. 2552-2556. Nov. 2007.
[1]
t
1-4 + +
4ý+
4 4. 4 A-+
1
4 4 4 4ý +
4-1; týý f
Inductor current (1L)
IN, I I
I1
11.11 (AAW 000000410
7
M
sourav % Ch4 50G.VQ r*1Z" Jis chl
Fig. 20. Boost output voltage transient from 2.7 to 3.3V with
Ch4 5O6mVQ
Fig. 21. Buck to boost output voltage transient from 2.2 to 3.4V
with V.,,=2.7V, Ik,.,=O.
VII. CONCLUSIONS
This paper describes a X-A modulated digitally controlled
non-inverting buck-boost converter having a wide range of
output voltages (0.8-3.6 V) from a Li-Ion battery (2.75.5 V). The converter serves as an adjustable power supply
for WCDMA RF power amplifiers. It is shown that precise
output voltage positioning and low output voltage ripple
over the wide output voltage range, including buck, boost
and buck/boost transition modes, can be accomplished using
I-A modulation in combination with a small, low-power,
low-resolution DPWM core. Furthermore, a two-mode
digital controller realization allows adjustments of the
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