a AD9831 DIRECT DIGITAL SYNTHESIZER, WAVEFORM GENERATOR

a AD9831 DIRECT DIGITAL SYNTHESIZER, WAVEFORM GENERATOR

a

FEATURES

3 V/5 V Power Supply

25 MHz Speed

On-Chip SINE Look-Up Table

On-Chip 10-Bit DAC

Parallel Loading

Powerdown Option

72 dB SFDR

125 mW (5 V) Power Consumption

40 mW (3 V) Power Consumption

48-Pin

LQFP

APPLICATIONS

DDS Tuning

Digital Demodulation

MCLK

FSELECT

DIRECT DIGITAL SYNTHESIZER,

WAVEFORM GENERATOR

AD9831

GENERAL DESCRIPTION

This DDS device is a numerically controlled oscillator employing a phase accumulator, a sine look-up table and a 10-bit D/A converter integrated on a single CMOS chip. Modulation capabilities are provided for phase modulation and frequency modulation.

Clock rates up to 25 MHz are supported. Frequency accuracy can be controlled to one part in 4 billion. Modulation is effected by loading registers through the parallel microprocessor interface.

A powerdown pin allows external control of a powerdown mode. The part is available in a 48-pin

LQFP package.

Similar DDS products can be found at

http://www.analog.com/DDS

.

FUNCTIONAL BLOCK DIAGRAM

DVDD

DGND AVDD AGND REFOUT FS ADJUST REFIN

ON-BOARD

REFERENCE

FULL-SCALE

CONTROL

COMP

FREQ0 REG

FREQ1 REG

MUX

PHASE

ACCUMULATOR

(32-BIT)

Σ

12

SIN

ROM

10-BIT DAC

IOUT

PHASE0 REG

PHASE1 REG

PHASE2 REG

PHASE3 REG

MUX

AD9831

PARALLEL REGISTER TRANSFER CONTROL

MPU INTERFACE

SLEEP

RESET

D0

PSEL0

PSEL1 D15 WR A0 A1 A2

REV. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

© Analog Devices, Inc.,

2011

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:

781.329.4700

Fax:

781.461.3113

AD9831–SPECIFICATIONS

1

(V

DD

= +3.3 V

6 10%; +5 V 6 10%; AGND = DGND = 0 V; T

A

REFOUT; R

SET

= 3.9 k

V; R

LOAD

= T

MIN

to T

MAX

; REFIN =

= 300

V for IOUT unless otherwise noted)

Parameter AD9831A Units Test Conditions/Comments

SIGNAL DAC SPECIFICATIONS

Resolution

Update Rate (f

MAX

I

OUT

Full Scale

)

10

25

4

5

1.5

Bits

MSPS nom mA nom mA max

V max Output Compliance

DC Accuracy

Integral Nonlinearity

Differential Nonlinearity

DDS SPECIFICATIONS

2

Dynamic Specifications

Signal to Noise Ratio

Total Harmonic Distortion

Spurious Free Dynamic Range (SFDR)

Narrow Band (

±

50 kHz)

3

Wide Band (

±

2 MHz)

Clock Feedthrough

Wake-Up Time

4

Powerdown Option

±

±

1

0.5

50

–53

–72

–70

–50

–60

1

Yes

LSB typ

LSB typ dB min dBc max dBc min dBc min dBc min dBc typ ms typ f f

MCLK

= 25 MHz, f

OUT

= 1 MHz

MCLK

= 25 MHz, f

OUT

= 1 MHz f

MCLK

= 6.25 MHz, f

OUT

= 2.11 MHz

5 V Power Supply

3 V Power Supply

VOLTAGE REFERENCE

Internal Reference @ +25

°

C

T

MIN

to T

MAX

REFIN Input Impedance

Reference TC

REFOUT Output Impedance

1.21

1.21

10

100

300

±

7%

Volts typ

Volts min/max

M

typ ppm/

°

C typ

typ

LOGIC INPUTS

V

INH

, Input High Voltage

V

INL

, Input Low Voltage

I

INH

, Input Current

C

IN

, Input Capacitance

POWER SUPPLIES

AVDD

DVDD

I

AA

I

DD

I

AA

+ I

DD

5

Low Power Sleep Mode

6

V

DD

0.9

10

10

– 0.9

2.97/5.5

2.97/5.5

15

24

1

V

V

µ

A min max pF max max

V min/V max

V min/V max

12 mA max

2.5 + 0.33/MHz mA typ mA mA max max mA max

5 V Power Supply

5 V Power Supply

3 V Power Supply

5 V Power Supply

1 M

Resistor Tied Between REFOUT and AGND

NOTES

1

Operating temperature range is as follows: A Version: –40

°

C to +85

°

C.

2

100% production tested.

3 f

MCLK

= 6.25 MHz, Frequency Word = 5671C71C HEX, f

OUT

= 2.11 MHz.

4

See Figure 11. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested.

5

Measured with the digital inputs static and equal to 0 V or DVDD.

6

The Low Power Sleep Mode current is typically 2 mA when a 1 M

resistor is not tied between REFOUT and AGND.

The AD9831 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenuated. For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF.

Specifications subject to change without notice.

R

SET

3.9k

10nF

REFOUT

ON-BOARD

REFERENCE

REFIN

FULL-SCALE

CONTROL

FS

ADJUST

COMP

AVDD

10nF

12

SIN

ROM

10-BIT DAC

AD9831

IOUT

300

50pF

Figure 1. Test Circuit with Which Specifications Are Tested

–2– REV. B

AD9831

TIMING CHARACTERISTICS

(V

DD

= +3.3 V

6 10%, +5 V 6 10%; AGND = DGND = 0 V, unless otherwise noted)

Parameter

Limit at

T

MIN

to T

MAX

(A Version) Units Test Conditions/Comments

t

7 t

8 t

9

* t

9A

* t

10 t

1 t

2 t

3 t

4

* t

4A

* t

5 t

6 t t

40

16

16

8

8

8

5

3

8

8

1

1

*See Pin Description section.

Guaranteed by design but not production tested.

ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min

MCLK Period

MCLK High Duration

MCLK Low Duration

WR Rising Edge to MCLK Rising Edge

WR Rising Edge After MCLK Rising Edge

WR Pulse Width

Duration between Consecutive WR Pulses

Data/Address Setup Time

Data/Address Hold Time

FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge

FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge

RESET Pulse Duration

t

1

MCLK

t

4 A

t

2

t

3

t

5 t

4

WR

t

6

Figure 2. Clock Synchronization Timing

WR

A0, A1, A2

DATA

t

6

t

5 t

8

t

7

VALID DATA

Figure 3. Parallel Timing

VALID DATA

MCLK

FSELECT

PSEL0, PSEL1

RESET

VALID DATA t

9

t

1 0

VALID DATA t

9 A

VALID DATA

Figure 4. Control Timing

REV. B

–3–

AD9831

ABSOLUTE MAXIMUM RATINGS*

(T

A

= +25

°

C unless otherwise noted)

AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

AGND to DGND. . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V

Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . –40

°

C to +85

°

C

Storage Temperature Range . . . . . . . . . . . . –65

°

C to +150

°

C

Maximum Junction Temperature . . . . . . . . . . . . . . . . +150

°

C

LQFP θ

JA

Thermal Impedance . . . . . . . . . . . . . . . . . 75

°

C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215

°

C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220

°

C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V

*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

PIN CONFIGURATION

AGND

REFOUT

SLEEP

DVDD

DVDD

DGND

MCLK

WR

DVDD

FSELECT

9

10

PSEL0 11

PSEL1

12

3

4

1

2

7

8

5

6

48 47 46 45 44 43 42 41 40 39 38 37

PIN 1

IDENTIFIER

AD9831

TOP VIEW

(Not to Scale)

36

AGND

35 RESET

34 A0

33 A1

32 A2

31

DB0

30 DB1

29 DGND

28 DB2

27

DB3

26 DB4

25 DVDD

13 14 15 16 17 18 19 20 21 22 23 24

NC = NO CONNECT

–4–

REV. B

AD9831

PIN DESCRIPTION

Mnemonic Function

POWER SUPPLY

AVDD Positive power supply for the analog section. A 0.1

µ

F decoupling capacitor should be connected between AVDD and AGND. AVDD can have a value of +5 V

±

10% or +3.3 V

±

10%.

AGND

DVDD

DGND

Analog Ground.

Positive power supply for the digital section. A 0.1

µ

F decoupling capacitor should be connected between DVDD and DGND. DVDD can have a value of +5 V

±

10% or +3.3 V

±

10%.

Digital Ground.

ANALOG SIGNAL AND REFERENCE

IOUT Current Output. This is a high impedance current source. A load resistor should be connected between IOUT and AGND.

FS ADJUST

REFIN

Full-Scale Adjust Control. A resistor (R

SET

) is connected between this pin and AGND. This determines the magnitude of the full-scale DAC current. The relationship between R

SET

and the full-scale current is as follows:

V

REFIN

IOUT

FULL-SCALE

= 12.5

×

V

REFIN

= 1.21 V nominal, R

SET

/R

SET

= 3.9 k

typical

Voltage Reference Input. The AD9831 can be used with either the on-board reference, which is available from pin

REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9831 accepts a reference of 1.21 V nominal.

REFOUT

COMP

Voltage Reference Output. The AD9831 has an on-board reference of value 1.21 V nominal. The reference is made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND.

Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic capacitor should be connected between COMP and AVDD.

DIGITAL INTERFACE AND CONTROL

MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock.

FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase accumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an

MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an uncertainty of one

MCLK cycle as to when control is transferred to the other frequency register. To avoid any uncertainty, a change on FSELECT should not coincide with an MCLK rising edge.

WR Write, Edge-Triggered Digital Input. The WR pin is used when writing data to the AD9831. The data is loaded into the AD9831 on the rising edge of the WR pulse. This data is then loaded into the destination register on the

MCLK rising edge. The WR pulse rising edge should not coincide with the MCLK rising edge as there will be an uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. The WR rising edge should occur before an MCLK rising edge. The data will then be loaded into the destination register on the

MCLK rising edge. Alternatively, the WR rising edge can occur after the MCLK rising edge and the destination register will be loaded on the next MCLK rising edge.

D0–D15

A0–A2

Data Bus, Digital Inputs for destination registers.

Address Digital Inputs. These address bits are used to select the destination register to which the digital data is to be written.

PSEL0, PSEL1 Phase Select Input. The AD9831 has four phase registers. These registers can be used to alter the value being input to the SIN ROM. The contents of the phase register can be added to the phase accumulator output, the inputs PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, PSEL0 and PSEL1 are sampled on the rising MCLK edge. Therefore, these inputs need to be in steady state when an MCLK rising edge occurs or there is an uncertainty of one MCLK cycle as to when control is transferred to the selected phase register.

SLEEP Low Power Control, active low digital input. SLEEP puts the AD9831 into a low power mode. Internal clocks are disabled and the DAC’s current sources and REFOUT are turned off. The AD9831 is re-enabled by taking

SLEEP high.

RESET Reset, active low digital input. RESET resets the phase accumulator to zero which corresponds to an analog output of midscale.

REV. B

–5–

AD9831

TERMINOLOGY

Integral Nonlinearity

This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5

LSB below the first code transition (000 . . . 00 to 000 . . . 01) and full scale, a point 0.5 LSB above the last code transition

(111 . . . 10 to 111 . . . 11). The error is expressed in LSBs.

Differential Nonlinearity

This is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC.

Signal to (Noise + Distortion)

Signal to (Noise + Distortion) is measured signal to noise at the output of the DAC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (f

MCLK

/2) but excluding the dc component. Signal to (Noise + Distortion) is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical Signal to (Noise + Distortion) ratio for a sine wave input is given by

Signal to (Noise + Distortion) = (6.02N + 1.76) dB where N is the number of bits. Thus, for an ideal 10-bit converter, Signal to (Noise + Distortion) = 61.96 dB.

Total Harmonic Distortion

Total Harmonic Distortion (THD) is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the

AD9831, THD is defined as

THD

=

20 log

(V

2

2 +

V

3

2 +

V

4

2 +

V

5

2 +

V

6

2

V

1 where V

1

is the rms amplitude of the fundamental and V

2

, V

3

,

V

4

, V

5

and V

6

are the rms amplitudes of the second through the sixth harmonic.

Output Compliance

The output compliance refers to the maximum voltage which can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output compliance are generated, the AD9831 may not meet the specifications listed in the data sheet.

Spurious Free Dynamic Range

Along with the frequency of interest, harmonics of the fundamental frequency and images of the MCLK frequency are present at the output of a DDS device. The spurious free dynamic range (SFDR) refers to the largest spur or harmonic which is present in the band of interest. The wide band SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the bandwidth

A2

1

1

0

1

1

0

0

0

±

2 MHz about the fundamental frequency. The narrow band

SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of

±

50 kHz about the fundamental frequency.

Clock Feedthrough

There will be feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the

MCLK signal relative to the fundamental frequency in the

AD9831’s output spectrum.

Table I. Control Registers

Register Size Description

FREQ0 REG 32 Bits Frequency Register 0. This defines the output frequency, when

FSELECT = 0, as a fraction of the

MCLK frequency.

FREQ1 REG 32 Bits Frequency Register 1. This defines the output frequency, when

FSELECT = 1, as a fraction of the

MCLK frequency.

PHASE0 REG 12 Bits Phase Offset Register 0. When

PSEL0 = PSEL1 = 0, the contents of this register are added to the output of the phase accumulator.

PHASE1 REG 12 Bits Phase Offset Register 1. When

PSEL0 = 1 and PSEL1 = 0, the contents of this register are added to the output of the phase accumulator.

PHASE2 REG 12 Bits Phase Offset Register 2. When

PSEL0 = 0 and PSEL1 = 1, the contents of this register are added to the output of the phase accumulator.

PHASE3 REG 12 Bits Phase Offset Register 3. When

PSEL0 = PSEL1 = 1, the contents of this register are added to the output of the phase accumulator.

Table II. Addressing the Control Registers

A1

0

1

1

0

1

0

0

1

A0

1

0

1

0

1

0

1

0

Destination Register

FREQ0 REG 16 LSBs

FREQ0 REG 16 MSBs

FREQ1 REG 16 LSBs

FREQ1 REG 16 MSBs

PHASE0 REG

PHASE1 REG

PHASE2 REG

PHASE3 REG

Table III. Frequency Register Bits

D15

MSB

D0

LSB

Table IV. Phase Register Bits

D15 D14 D13 D12 D11

X X X X MSB

–6–

D0

LSB

REV. B

25

T

A

= +25

°

C

20

15

10

5

0

5

+5V

+3.3V

10 15

MCLK FREQUENCY – MHz

20 25

Typical Performance Characteristics–AD9831

–40

AVDD = DVDD = +3.3V

–45

–50

–55

–60

–65

–70

–75

–80

0 0.1

0.2

f

OUT

/f

MCLK

0.3

25MHz

10MHz

0.4

Figure 5. Typical Current Consumption vs. MCLK

Frequency

Figure 8. Wide Band SFDR vs. f

OUT

/f

MCLK

for Various

MCLK Frequencies

–50

–55

f

OUT

/f

MCLK

= 1/3

AVDD = DVDD = +3.3V

–60

–65

–70

–75

–80

10 15 20

MCLK FREQUENCY – MHz

25

Figure 6. Narrow Band SFDR vs. MCLK Frequency

60

AVDD = DVDD = +3.3V

f

OUT

= f

MCLK

/3

55

50

45

–40 f

OUT

/f

MCLK

= 1/3

AVDD = DVDD = +3.3V

–45

–50

–55

–60

–65

10 15 20

MCLK FREQUENCY – MHz

25

Figure 7. Wide Band SFDR vs. MCLK Frequency

40

10 15 20

MCLK FREQUENCY – MHz

Figure 9. SNR vs. MCLK Frequency

25

60

AVDD = DVDD = +3.3V

55

50

10MHz

25MHz

45

40

0 0.1

0.2

f

OUT

/f

MCLK

0.3

0.4

Figure 10. SNR vs. f

OUT

/f

MCLK

for Various MCLK

Frequencies

REV. B

–7–

AD9831–Typical Performance Characteristics

10

AVDD = DVDD = +2.97V

7.5

5.0

2.5

0

–40 –30 –20

TEMPERATURE –

°

C

–10 0

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

START 0Hz

RBW 300Hz

Figure 11. Wake-Up Time vs. Temperature

VBW 1kHz

STOP 12.5MHz

ST 277 SEC

Figure 14. f

MCLK

= 25 MHz, f

OUT

= 3.1 MHz, Frequency

Word = 1FBE76C9

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

START 0Hz

RBW 300Hz VBW 1kHz

STOP 12.5MHz

ST 277 SEC

Figure 12. f

MCLK

= 25 MHz, f

OUT

= 1.1 MHz, Frequency

Word = B439581

–40

–50

–60

–70

0

–10

–20

–30

–80

–90

–100

START 0Hz

RBW 300Hz VBW 1kHz

STOP 12.5MHz

ST 277 SEC

Figure 15. f

MCLK

= 25 MHz, f

OUT

= 4.1 MHz, Frequency

Word = 29FBE76D

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

START 0Hz

RBW 300Hz VBW 1kHz

STOP 12.5MHz

ST 277 SEC

Figure 13. f

MCLK

= 25 MHz, f

OUT

= 2.1 MHz, Frequency

Word = 15810625

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

START 0Hz

RBW 300Hz VBW 1kHz

STOP 12.5MHz

ST 277 SEC

Figure 16. f

MCLK

= 25 MHz, f

OUT

= 5.1 MHz, Frequency

Word = 34395810

–8–

REV. B

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

START 0Hz

RBW 300Hz VBW 1kHz

STOP 12.5MHz

ST 277 SEC

Figure 17. f

MCLK

= 25 MHz, f

OUT

= 6.1 MHz, Frequency

Word = 3E76C8B4

–40

–50

–60

–70

0

–10

–20

–30

–80

–90

–100

START 0Hz

RBW 300Hz VBW 1kHz

STOP 12.5MHz

ST 277 SEC

Figure 18. f

MCLK

= 25 MHz, f

OUT

= 7.1 MHz, Frequency

Word = 48B43958

AD9831

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

START 0Hz

RBW 300Hz

VBW 1kHz

STOP 12.5MHz

ST 277 SEC

Figure 19. f

MCLK

= 25 MHz, f

OUT

= 8.1 MHz, Frequency

Word = 52F1A9FC

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

START 0Hz

RBW 300Hz VBW 1kHz

STOP 12.5MHz

ST 277 SEC

Figure 20. f

MCLK

= 25 MHz, f

OUT

= 9.1 MHz, Frequency

Word = 5D2F1AA0

REV. B

–9–

AD9831

CIRCUIT DESCRIPTION

The AD9831 provides an exciting new level of integration for the RF/Communications system designer. The AD9831 combines the Numerical Controlled Oscillator (NCO), SINE Look-

Up Table, Frequency and Phase Modulators, and a Digital-to-

Analog Converter on a single integrated circuit.

The internal circuitry of the AD9831 consists of three main sections. These are:

Numerical Controlled Oscillator (NCO) + Phase Modulator

SINE Look-Up Table

Digital-to-Analog Converter

The AD9831 is a fully integrated Direct Digital Synthesis

(DDS) chip. The chip requires one reference clock, one low precision resistor and eight decoupling capacitors to provide digitally created sine waves up to 12.5 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain allowing accurate and simple realization of complex modulation algorithms using DSP techniques.

THEORY OF OPERATION

Sine waves are typically thought of in terms of their magnitude form a(t) = sin (

ω t). However, these are nonlinear and not easy to generate except through piece wise construction. On the other hand, the angular information is linear in nature. That is, the phase angle rotates through a fixed angle for each unit of time. The angular rate depends on the frequency of the signal by the traditional rate of

ω

= 2

π f.

MAGNITUDE

+1

0

–1

2

π

PHASE

0

Figure 21. Sine Wave

Knowing that the phase of a sine wave is linear and given a reference interval (clock period), the phase rotation for that period can be determined.

Phase =

ωδ t

Solving for

ω

ω

=

Phase/

δ t = 2

π f

Solving for f and substituting the reference clock frequency for the reference period (1/f

MCLK

=

δ t)

f =

Phase

×

f

MCLK

/2

π

The AD9831 builds the output based on this simple equation.

A simple DDS chip can implement this equation with three major subcircuits.

Numerical Controlled Oscillator + Phase Modulator

This consists of two frequency select registers, a phase accumulator and four phase offset registers. The main component of the

NCO is a 32-bit phase accumulator which assembles the phase component of the output signal. Continuous time signals have a phase range of 0 to 2

π

. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word.

The phase accumulator in the AD9831 is implemented with 32 bits. Therefore, in the AD9831, 2

π

= 2

32

. Likewise, the

Phase

term is scaled into this range of numbers 0 <

Phase < 2

32

– 1.

Making these substitutions into the equation above

f =

Phase

×

f

MCLK

/2

32 where 0 <

Phase < 2

32

With a clock signal of 25 MHz and a phase word of 051EB852 hex

f = 51EB852

×

25 MHz/2

32

= 0.500000000465 MHz

The input to the phase accumulator (i.e., the phase step) can be selected either from the FREQ0 Register or FREQ1 Register and this is controlled by the FSELECT pin. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies.

Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit PHASE Registers. The contents of this register are added to the most significant bits of the

NCO. The AD9831 has four PHASE registers, the resolution of these registers being 2

π

/4096.

Sine Look-Up Table (LUT)

To make the output useful, the signal must be converted from phase information into a sinusoidal value. Since phase information maps directly into amplitude, a ROM LUT converts the phase information into amplitude. To do this, the digital phase information is used to address a sine ROM LUT. Although the

NCO contains a 32-bit phase accumulator, the output of the

NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary as this would require a look-up table of 2

32

entries.

It is necessary only to have sufficient phase resolution in the

LUTs such that the dc error of the output waveform is dominated by the quantization error in the DAC. This requires the look-up table to have two more bits of phase resolution than the

10-bit DAC.

Digital-to-Analog Converter

The AD9831 includes a high impedance current source 10-bit

DAC, capable of driving a wide range of loads at different speeds. Full-scale output current can be adjusted, for optimum power and external load requirements, through the use of a single external resistor (R

SET

).

The DAC is configured for single ended operation. The load resistor can be any value required, as long as the full-scale voltage developed across it does not exceed the voltage compliance range. Since full-scale current is controlled by R

SET

, adjustments to R

SET

can balance changes made to the load resistor.

However, if the DAC full-scale output current is significantly less than 4 mA, the DAC’s linearity may degrade.

–10–

REV. B

DSP and MPU Interfacing

The AD9831 has a parallel interface, with 16 bits of data being loaded during each write cycle.

The frequency or phase registers are loaded by asserting the WR signal. The destination register for the 16 bit data is selected using the address inputs A0, A1 and A2. The phase registers are 12 bits wide so, only the 12 LSBs need to be valid—the

4 MSBs of the 16 bit word do not have to contain valid data.

Data is loaded into the AD9831 by pulsing WR low, the data being latched into the AD9831 on the rising edge of WR. The values of inputs A0, A1 and A2 are also latched into the

AD9831 on the WR rising edge. The appropriate destination register is updated on the next MCLK rising edge. If the WR rising edge coincides with the MCLK rising edge, there is an uncertainty of one MCLK cycle regarding the loading of the destination register—the destination register may be loaded immediately or the destination register may be updated on the next MCLK rising edge. To avoid any uncertainty, the times listed in the specifications should be complied with.

FSELECT, PSEL0 and PSEL1 are sampled on the MCLK rising edge. Again, these inputs should be valid when an

MCLK rising edge occurs as there will be an uncertainty of one

AD9831

MCLK cycle introduced otherwise. When these inputs change value, there will be a pipeline delay before control is transferred to the selected register—there will be a pipeline delay before the analog output is controlled by the selected register. There is a similar delay when a new word is written to a register. PSEL0,

PSEL1, FSELECT and WR have latencies of six MCLK cycles.

The flow chart in Figure 22 shows the operating routine for the

AD9831. When the AD9831 is powered up, the part should be reset using RESET. This will reset the phase accumulator to zero so that the analog output is at midscale. RESET does not reset the phase and frequency registers. These registers will contain invalid data and, therefore, should be set to zero by the user.

The registers to be used should be loaded, the analog output being f

MCLK

/2

32

×

FREG where FREG is the value loaded into the selected frequency register. This signal will be phase shifted by the amount specified in the selected phase register (2

π

/4096

×

PHASEREG where PHASEREG is the value contained in the selected phase register). When FSELECT, PSEL0 and PSEL1 are programmed, there will be a pipeline delay of approximately

6 MCLK cycles before the analog output reacts to the change on these inputs.

RESET

DATA WRITE

FREG<0, 1> = 0

PHASEREG<0, 1, 2, 3> = 0

DATA WRITE

FREG<0> = f

OUT0

/f

MCLK

*2

32

FREG<1> = f

OUT1

/f

MCLK

*2

32

PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3>

SELECT DATA SOURCES

SET FSELECT

SET PSEL0, PSEL1

WAIT 6 MCLK CYCLES

DAC OUTPUT

V

OUT

= V

REFIN

*6.25*R

OUT

/R

SET*

(1 + SIN(2

π

(FREG*f

MCLK

*t/2

32

+ PHASEREG/2

12

)))

CHANGE FSELECT

NO

NO

CHANGE PHASE?

YES

NO

CHANGE F

OUT

?

YES

CHANGE FREG?

CHANGE PHASEREG?

NO

YES

YES

CHANGE PSEL0, PSEL1

Figure 22. Flow Chart for AD9831 Initialization and Operation

REV. B

–11–

AD9831

APPLICATIONS

The AD9831 contains functions which make it suitable for modulation applications. The part can be used to perform simple modulation such as FSK. More complex modulation schemes such as GMSK and QPSK can also be implemented using the AD9831. In an FSK application, the two frequency registers of the AD9831 are loaded with different values; one frequency will represent the space frequency while the other will represent the mark frequency. The digital data stream is fed to the FSELECT pin which will cause the AD9831 to modulate the carrier frequency between the two values.

The AD9831 has four phase registers; this enables the part to perform PSK. With phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount which is related to the bit stream being input to the modulator. The presence of four shift registers eases the interaction needed between the DSP and the AD9831.

The frequency and phase registers can be written to continuously, if required. The maximum update rate equals the frequency of the MCLK. However, if a selected register is loaded with a new word, there will be a delay of 6 MCLK cycles before the analog output will change accordingly.

The AD9831 is also suitable for signal generator applications.

With its low current consumption, the part is suitable for applications in which it can be used as a local oscillator. In addition, the part is fully specified for operation with a +3.3 V

±

10% power supply. Therefore, in portable applications where current consumption is an important issue, the AD9831 is perfect.

Grounding and Layout

The printed circuit board that houses the AD9831 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes which can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD9831 is the only device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD9831. If the AD9831 is in a system where multiple devices require AGND to DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the

AD9831.

Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD9831 to avoid noise coupling. The power supply lines to the AD9831 should use as large a track as is possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side.

Good decoupling is important. The analog and digital supplies to the AD9831 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to

AGND and DGND respectively with 0.1

µ

F ceramic capacitors in parallel with 10

µ

F tantalum capacitors. To achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the

AVDD and DVDD of the AD9831, it is recommended that the system’s AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pins of the AD9831 and AGND and the recommended digital supply decoupling capacitors between the DVDD pins and

DGND.

AD9837

AD9832 AD9833

more information on these parts, visit .

–12–

REV. B

Data Sheet AD9831

OUTLINE DIMENSIONS

0.75

0.60

0.45

1.60

MAX

9.20

9.00 SQ

8.80

1

48

37

36

PIN 1

1.45

1.40

1.35

0.15

0.05

SEATING

PLANE

0.20

0.09

3.5°

0.08

COPLANARITY

12

13

VIEW A

0.50

BSC

LEAD PITCH

TOP VIEW

(PINS DOWN)

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-BBC

Figure 23. 48-Lead Low Profile Quad Flat Package (LQFP)

(ST-48)

Dimensions shown in millimeters

25

24

0.27

0.22

0.17

7.20

7.00 SQ

6.80

ORDERING GUIDE

Model

1

AD9831ASTZ

AD9831ASTZ-REEL

1 Z = RoHS Compliant Part.

Temperature Range

–40°C to +85°C

–40°C to +85°C

Package Description

48-Lead Low Profile Quad Flat Package [LQFP]

48-Lead Low Profile Quad Flat Package [LQFP]

REVISION HISTORY

11/11—Rev. A to Rev. B

Changes to Title and General Description Section ...................... 1

Changed TQFP to LQFP Throughout ............................................ 1

Changes to Grounding and Layout Section ................................. 12

Deleted AD9831 Evaluation Board, Using the AD9831

Evaluation Board, Prototyping Area, XO vs. External Clock, and

Power Supply Sections .................................................................... 13

Package Option

ST-48

ST-48

Deleted Figure 23; Renumbered Sequentially ............................. 13

Updated Outline Dimensions ........................................................ 13

Changes to Ordering Guide ........................................................... 13

Deleted Figure 24 and Component List Section ......................... 14

Rev. B | Page 13 of 16

AD9831

NOTES

Data Sheet

Rev. B | Page 14 of 16

Data Sheet

NOTES

AD9831

Rev. B | Page 15 of 16

AD9831

NOTES

Data Sheet

©2011 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D10373-0-11/11(B)

Rev. B | Page 1

6 of 16

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