- No category
advertisement
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
MSP430FR203x Mixed-Signal Microcontrollers
1 Device Overview
1
1.1
Features
• Embedded Microcontroller
– 16-Bit RISC Architecture up to 16 MHz
– Wide Supply Voltage Range From 1.8 V to
3.6 V
• Optimized Low-Power Modes (at 3 V)
– Active: 126 µA/MHz
– Standby
• LPM3.5 With VLO: 0.4 µA
• Real-Time Clock (RTC) Counter (LPM3.5
With 32768-Hz Crystal): 0.77 µA
– Shutdown (LPM4.5): 15 nA
• Low-Power Ferroelectric RAM (FRAM)
– Up to 15.5KB of Nonvolatile Memory
– Built-In Error Correction Code (ECC)
– Configurable Write Protection
– Unified Memory of Program, Constants, and
Storage
– 10
15
Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
• Intelligent Digital Peripherals
– IR Modulation Logic
– Two 16-Bit Timers With Three Capture/Compare
Registers Each (Timer_A3)
– One 16-Bit Counter-Only RTC Counter
– 16-Bit Cyclic Redundancy Check (CRC)
• Enhanced Serial Communications
– Enhanced USCI A (eUSCI_A) Supports UART,
IrDA, and SPI
– Enhanced USCI B (eUSCI_B) Supports SPI and
I
2
C
• High-Performance Analog
– 10-Channel 10-Bit Analog-to-Digital Converter
(ADC)
• Internal 1.5-V Reference
• Sample-and-Hold 200 ksps
1.2
Applications
• Smoke or Fire Detectors
• Glass Breakage Detectors
• Industrial Sensor Management
• System Supervisor, Low-Power Coprocessors
• Clock System (CS)
– On-Chip 32-kHz RC Oscillator (REFO)
– On-Chip 16-MHz Digitally Controlled Oscillator
(DCO) With Frequency Locked Loop (FLL)
• ±1% Accuracy With On-Chip Reference at
Room Temperature
– On-Chip Very Low-Frequency 10-kHz Oscillator
(VLO)
– On-Chip High-Frequency Modulation Oscillator
(MODOSC)
– External 32-kHz Crystal Oscillator (XT1)
– Programmable MCLK Prescalar of 1 to 128
– SMCLK Derived From MCLK With
Programmable Prescalar of 1, 2, 4, or 8
• General Input/Output and Pin Functionality
– Total 60 I/Os on 64-Pin Package
– 16 Interrupt Pins (P1 and P2) Can Wake up
MCU From LPMs
– All I/Os are Capacitive Touch I/Os
• Development Tools and Software
– Free Professional Development Environments
• Family Members (Also See
)
– MSP430FR2033: 15KB of Program FRAM +
512B of Information FRAM + 2KB of RAM
– MSP430FR2032: 8KB of Program FRAM +
512B of Information FRAM + 1KB of RAM
• Package Options
– 64 Pin: LQFP (PM)
– 56 Pin: TSSOP (G56)
– 48 Pin: TSSOP (G48)
• For Complete Module Descriptions, See the
MSP430FR4xx and MSP430FR2xx Family User's
Guide ( SLAU445 )
• Temperature Sensors or Controllers
• Data Storage, Data Integration
• Human Machine Interface (HMI) Controllers
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
1.3
Description
The TI MSP430™ family of low-power microcontrollers consists of several devices that feature different sets of peripherals targeted for various applications. The architecture, combined with extensive low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The DCO allows the device to wake up from low-power modes to active mode in less than 10 µs.
PART NUMBER
MSP430FR2033IPM
MSP430FR2033IG56
MSP430FR2033IG48
MSP430FR2032IPM
MSP430FR2032IG56
MSP430FR2032IG48
Device Information
(1)
PACKAGE
LQFP (64)
TSSOP (56)
TSSOP (48)
LQFP (64)
TSSOP (56)
TSSOP (48)
BODY SIZE
(2)
10 mm × 10 mm
14.0 mm × 6.1 mm
12.5 mm × 6.1 mm
10 mm × 10 mm
14.0 mm × 6.1 mm
12.5 mm × 6.1 mm
(1) For the most current part, package, and ordering information, see the Package Option Addendum in
, or see the TI website at www.ti.com
.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in
2
Device Overview
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
1.4
Functional Block Diagram
shows the functional block diagram.
XIN XOUT
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
P1.x/P2.x
P3.x/P4.x
P5.x/P6.x
P7.x/P8.x
DVCC
DVSS
RST/NMI
Power
Management
Module
16-MHZ CPU inc.
16 Registers
MAB
MDB
XT1
Clock
System
Control
ADC
Up to 10-ch
Single-end
10-bit
200ksps
FRAM
15KB+512B
8KB+ 512 B
RAM
2KB
1KB
I/O Ports
P1/P2
2×8 IOs
Interrupt
& Wakeup
PA
1×16 IOs
Capacitive Touch I/O
I/O Ports
P3/P4
2×8 IOs
PB
1×16 IOs
I/O Ports
P5/P6
2×8 IOs
PC
1×16 IOs
I/O Ports
P7/P8
1×8 IOs
1×4 IOs
PD
1×12 IOs
EEM
TCK
TMS
TDI/TCLK
TDO
SBWTCK
SBWTDIO
JTAG
SBW
SYS
Watchdog
CRC16
16-bit
Cyclic
Redundancy
Check
TA0
Timer_A
3 CC
Registers
TA1
Timer_A
3 CC
Registers eUSCI_A0
(UART,
IrDA, SPI) eUSCI_B0
(SPI, I2C)
RTC
Counter
16-bit
Real-Time
Clock
LPM3.5 Domain
Figure 1-1. Functional Block Diagram
• The device has one main power pair of DVCC and DVSS that supplies both digital and analog modules. Recommended bypass and decouple capacitors are 4.7 µF to 10 µF and 0.1 µF, respectively, with ±5% accuracy.
• P1 and P2 feature the pin-interrupt function and can wake the MCU from LPM3.5.
• Each Timer_A3 has three CC registers, but only the CCR1 and CCR2 are externally connected. CCR0 registers can only be used for internal period timing and interrupt generation.
• In LPM3.5, the RTC counter can be functional while the remaining peripherals are off.
• Not all I/Os are bonded in TSSOP-56 and TSSOP-48 packages (refer to
). All I/Os can be configured as Capacitive Touch I/Os.
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Device Overview
3
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
1 Device Overview
.........................................
1.1
Features
..............................................
1.2
Applications
...........................................
1.3
Description
............................................
1.4
Functional Block Diagram
............................
2 Revision History
.........................................
3 Device Comparison
.....................................
4 Terminal Configuration and Functions
..............
4.1
Pin Diagrams
.........................................
4.2
Signal Descriptions
...................................
4.3
Pin Multiplexing
.....................................
4.4
Connection of Unused Pins
5 Specifications
.........................
...........................................
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
.........................
........................................
5.3
Recommended Operating Conditions
...............
5.4
Active Mode Supply Current Into V
CC
External Current
Excluding
.....................................
5.5
Active Mode Supply Current Per MHz
..............
5.6
Low-Power Mode LPM0 Supply Currents Into V
CC
Excluding External Current
..........................
5.7
Low-Power Mode LPM3, LPM4 Supply Currents
(Into V
CC
) Excluding External Current
..............
5.8
Low-Power Mode LPMx.5 Supply Currents (Into
V
CC
) Excluding External Current
....................
5.9
Typical Characteristics, Low-Power Mode Supply
Currents
.............................................
5.10
Typical Characteristics - Current Consumption Per
Module
..............................................
Table of Contents
5.11
Thermal Characteristics
.............................
5.12
Timing and Switching Characteristics
6 Detailed Description
...............
...................................
6.1
CPU
.................................................
6.2
Operating Modes
....................................
6.3
Interrupt Vector Addresses
..........................
6.4
Bootstrap Loader (BSL)
.............................
6.5
JTAG Standard Interface
............................
6.6
Spy-Bi-Wire Interface (SBW)
........................
6.7
FRAM
................................................
6.8
Memory Protection
..................................
6.9
Peripherals
..........................................
6.10
Device Descriptors (TLV)
...........................
6.11
Memory
..............................................
6.12
Identification
.........................................
7 Applications, Implementation, and Layout
........
7.1
Device Connection and Layout Fundamentals
......
7.2
Peripheral- and Interface-Specific Design
Information
..........................................
8 Device and Documentation Support
...............
8.1
Device Support
......................................
8.2
Documentation Support
.............................
8.3
Trademarks
..........................................
8.4
Electrostatic Discharge Caution
.....................
8.5
Glossary
.............................................
9 Mechanical Packaging and Orderable
Information
..............................................
9.1
Packaging Information
..............................
2 Revision History
Changes from November 1, 2014 to August 14, 2015 Page
• Corrected "10-BIT ADC CHANNELS" column for MSP430FR2032IPM in
, Device Comparison
• Added T stg
MIN and MAX values
..............
..................................................................................................
• Added
..................................................................................................
• Changed all graphs in
, Typical Characteristics, Low-Power Mode Supply Currents, for new
measurements
• Added V
REF, 1.2V
• Changed f
ADCOSC
......................................................................................................................
parameter to
, PMM, SVS and BOR
...............................................................
• Changed t
STE,LEAD
• Changed t
STE,LEAD
• Changed t
VALID,SO
• Changed t
VALID,SO
MIN value at 2 V from 40 ns to 50 ns
MIN value at 3 V from 24 ns to 45 ns
MAX value at 2 V from 55 ns to 65 ns
MAX value at 3 V from 30 ns to 40 ns
TYP value from 4.5 MHz to 5.0 MHz
......................................................................
......................................................................
......................................................................
......................................................................
........................................................................
• In
, Operating Modes, changed the entry for "Power Consumption at 25°C, 3 V" in AM from
100 µA/MHz to 126 µA/MHz
.......................................................................................................
• In
, Operating Modes, added "with RTC only" to the entry for "Power Consumption at 25°C, 3 V" in
LPM3.5
...............................................................................................................................
• In
, Interrupt Sources, Flags, and Vectors, removed "FRAM access time error" (ACCTEIFG) from the
"System NMI" row
..................................................................................................................
4
Revision History
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
3 Device Comparison
summarizes the features of the available family members.
Table 3-1. Device Comparison
(1) (2)
DEVICE
PROGRAM
FRAM + SRAM
INFORMATION (BYTES)
FRAM (BYTES)
TA0, TA1 eUSCI_A eUSCI_B
10-BIT ADC
CHANNELS
I/O
PACKAGE
TYPE
MSP430FR2033IPM
MSP430FR2033IG56
MSP430FR2033IG48
MSP430FR2032IPM
MSP430FR2032IG56
MSP430FR2032IG48
15360 + 512
15360 + 512
15360 + 512
8192 + 512
8192 + 512
8192 + 512
2048
2048
2048
1024
1024
1024
3 × CCR
3 × CCR
3 × CCR
3 × CCR
3 × CCR
3 × CCR
(3)
(3)
(3)
(3)
(3)
(3)
1
1
1
1
1
1
1
1
1
1
1
1
10
8
8
10
8
8
60
52
44
60
52
44
PM
(LQFP64)
G56
(TSSOP56)
G48
(TSSOP48)
PM
(LQFP64)
G56
(TSSOP56)
G48
(TSSOP48)
(1) For the most current device, package, and ordering information, see the Package Option Addendum in
Section 9 , or see the TI website
at www.ti.com
.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging .
(3) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM outputs.
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Device Comparison
5
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
4 Terminal Configuration and Functions
4.1
Pin Diagrams
shows the 64-pin PM package.
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2/XOUT
P4.1/XIN
DVSS
DVCC
RST/NMI/SBWTDIO
TEST/SBWTCK
P4.0/TA1.1
P8.3/TA1.2
P8.2/TA1CLK
P8.1/ACLK/A9
P8.0/SMCLK/A8
6
7
8
9
10
11
3
4
5
1
2
12
13
14
15
16
43
42
41
40
39
38
37
36
35
34
33
48
47
46
45
44
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
www.ti.com
Figure 4-1. 64-Pin PM (LQFP) Designation (Top View)
6
Terminal Configuration and Functions
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
shows the 56-pin G56 package.
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
P4.2/XOUT
P4.1/XIN
DVSS
DVCC
RST/NMI/SBWTDIO
TEST/SBWTCK
P4.0/TA1.1
P8.3/TA1.2
P8.2/TA1CLK
P1.7/TA0.1/TDO/A7
P1.6/TA0.2/TDI/TCLK/A6
P1.5/TA0CLK/TMS/A5
P7.5
P7.4
P7.3
P7.2
P7.1
P7.0
P4.7
P4.6
P4.5
P4.4
P4.3
P1.3/UCA0STE/A3
P1.2/ UCA0CLK /A2
P1.1/ UCA0RXD/UCA0SOMI /A1/Veref+
P1.0/ UCA0TXD/UCA0SIMO /A0/Veref–
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
3
4
5
1
2
6
7
8
9
10
11
48
47
46
45
44
43
42
41
40
56
55
54
53
52
51
50
49
39
38
37
36
35
34
33
32
31
30
29
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P2.0
P2.1
P2.2
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P2.3
P2.4
P2.5
P2.6
P2.7
P5.0/UCB0STE
P5.1/UCB0CLK
P5.2/UCB0SIMO/UCB0SDA
P5.3/UCB0SOMI/UCB0SCL
P5.4
P5.5
Figure 4-2. 56-Pin DGG (TSSOP) Designation (Top View)
Copyright © 2014–2015, Texas Instruments Incorporated
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
7
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
shows the 48-pin G48 package.
www.ti.com
P3.1
P3.0
P7.3
P7.2
P7.1
P7.0
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2/XOUT
P4.1/XIN
DVSS
DVCC
RST/NMI/SBWTDIO
TEST/SBWTCK
P4.0/TA1.1
P1.7/TA0.1/TDO/A7
P1.6/TA0.2/TDI/TCLK/A6
P1.5/TA0CLK/TMS/A5
P1.4/MCLK/TCK/A4/VREF+
P1.3/UCA0STE/A3
P1.2/UCA0CLK/A2
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P6.0
P6.1
P6.2
P6.3
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P5.0/UCB0STE
P5.1/UCB0CLK
P5.2/UCB0SIMO/UCB0SDA
P5.3/UCB0SOMI/UCB0SCL
P1.0/UCA0TXD/UCA0SIMO/A0/Veref–
P1.1/UCA0RXD/UCA0SOMI/A1/Veref+
Figure 4-3. 48-Pin DGG (TSSOP) Designation (Top View)
8
Terminal Configuration and Functions
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
4.2
Signal Descriptions
describes the signals for all device variants and package options.
P4.7
P4.6
P4.5
P4.4
P4.3
P4.2/XOUT
P4.1/XIN
DVSS
DVCC
NAME
RST/NMI/SBWTDIO
TEST/SBWTCK
P4.0/TA1.1
P8.3/TA1.2
(1)
P8.2/TA1CLK
(1)
P8.1/ACLK/A9
(1)
P8.0/SMCLK/A8
(1)
P1.7/TA0.1/TDO/A7
(2)
TERMINAL
PACKAGE SUFFIX
PM G56 G48
1
2
7
8
7
8
3
4
5
9
10
11
9
10
11
P1.6/TA0.2/TDI/TCLK/A6
(2)
6
7
8
9
10
11
12
13
14
15
16
17
18
12
13
14
15
16
17
18
19
20
21
22
Table 4-1. Signal Descriptions
12
13
14
15
16
17
18
19
20
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DESCRIPTION
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
Output terminal for crystal oscillator
General-purpose I/O
Input terminal for crystal oscillator
Power ground
Power supply
Reset input active low
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
Test Mode pin – selected digital I/O on JTAG pins
Spy-Bi-Wire input clock
General-purpose I/O
Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs
General-purpose I/O
Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs
General-purpose I/O
Timer clock input TACLK for TA1
General-purpose I/O
ACLK output
Analog input A9
General-purpose I/O
SMCLK output
Analog input A8
General-purpose I/O
(2)
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs
Test data output
Analog input A7
General-purpose I/O
(2)
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs
Test data input or test clock input
Analog input A6
(1) Any pin that is not bonded out in a smaller package must be initialized by software after reset to achieve the lowest leakage current.
(2) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to prevent collisions.
Copyright © 2014–2015, Texas Instruments Incorporated
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
9
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
P1.3/UCA0STE/A3
P1.2/UCA0CLK/A2
P1.1/UCA0RXD/UCA0SOMI/
A1/Veref+
P1.0/UCA0TXD/UCA0SIMO/
A0/Veref-
P5.7
(1)
P5.6
(1)
P5.5
(1)
P5.4
(1)
P5.3/UCB0SOMI/UCB0SCL
P5.2/UCB0SIMO/UCB0SDA
P5.1/UCB0CLK
P5.0/UCB0STE
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
NAME
P1.5/TA0CLK/TMS/A5
(2)
Table 4-1. Signal Descriptions (continued)
TERMINAL
PACKAGE SUFFIX
PM G56 G48
I/O DESCRIPTION
General-purpose I/O
(2)
Timer clock input TACLK for TA0
19 23 21 I/O
Test mode select
Analog input A5
General-purpose I/O
(2)
MCLK output
P1.4/MCLK/TCK/A4/VREF+
(2)
20 24 22 I/O Test clock
Analog input A4
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Output of positive reference voltage with ground as reference
General-purpose I/O eUSCI_A0 SPI slave transmit enable
Analog input A3
General-purpose I/O eUSCI_A0 SPI clock input/output
Analog input A2
General-purpose I/O eUSCI_A0 UART receive data eUSCI_A0 SPI slave out/master in
Analog input A1, and ADC positive reference
General-purpose I/O eUSCI_A0 UART transmit data eUSCI_A0 SPI slave in/master out
Analog input A0, and ADC negative reference
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O eUSCI_B0 SPI slave out/master in; eUSCI_B0 I
2
C clock
General-purpose I/O eUSCI_B0 SPI slave in/master out; eUSCI_B0 I
2
C data
General-purpose I/O eUSCI_B0 clock input/output
General-purpose I/O eUSCI_B0 slave transmit enable
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
10
Terminal Configuration and Functions
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
P3.7
P3.6
P3.5
P3.4
P3.3
P2.0
P6.7
(1)
P6.6
(1)
P6.5
(1)
P6.4
(1)
P6.3
P6.2
P6.1
P6.0
P3.2
P3.1
P3.0
P7.7
(1)
P7.6
(1)
P7.5
(1)
P7.4
(1)
P7.3
P7.2
P7.1
P7.0
www.ti.com
NAME
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 4-1. Signal Descriptions (continued)
TERMINAL
PACKAGE SUFFIX
PM G56 G48
40
41
42 38
42
43
44
45
46
47
48
43
44
45
46
49
50
51
52
53
47
48
49
50
51
52
53
39
40
41
42
43
44
45
46
47
54
55
56
48
1
2
62
63
64
59
60
61
54
55
56
57
58
1
2
3
4
5
6
5
6
3
4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
General-purpose I/O
DESCRIPTION
Copyright © 2014–2015, Texas Instruments Incorporated
Terminal Configuration and Functions
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
11
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
4.3
Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the device is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see
.
4.4
Connection of Unused Pins
shows the correct termination of unused pins.
Table 4-2. Connection of Unused Pins
(1)
PIN
Px.0 to Px.7
RST/NMI
TEST
POTENTIAL
Open
DVCC
Open
COMMENT
Set to port function, output direction (PxDIR.n = 1)
47-k Ω pullup or internal pullup selected with 10-nF (or 1.1-nF) pulldown
(2)
This pin always has an internal pulldown enabled.
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection guidelines.
(2) The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers.
12
Terminal Configuration and Functions
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
5 Specifications
5.1
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage applied at DVCC pin to V
Voltage applied to any pin
(2)
SS
MIN
–0.3
–0.3
MAX
4.1
V
CC
+ 0.3
(4.1 Maximum)
UNIT
V
V
Diode current at any device pin
Maximum junction temperature, T
J
Storage temperature, T stg
(3)
–40
±2
85
125 mA
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V
SS
.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
V
(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
VALUE
±1000
±250
UNIT
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance.
5.3
Recommended Operating Conditions
Typical values are specified at V
CC
= 3.3 V and T
A
= 25°C (unless otherwise noted)
V
CC
V
SS
T
A
T
J
C
DVCC
Supply voltage applied at DVCC pin
Supply voltage applied at DVSS pin
Operating free-air temperature
Operating junction temperature
Recommended capacitor at DVCC
(1) (2) (3)
(4)
MIN
1.8
–40
–40
4.7
NOM
0
10
MAX
3.6
85
85
UNIT
V
V
°C
°C
µF f
SYSTEM
Processor frequency (maximum MCLK frequency)
(3) (5)
No FRAM wait states
(NWAITSx = 0)
With FRAM wait states
(NWAITSx = 1)
(6)
0
0 16
8
(7)
MHz f
ACLK f
SMCLK
Maximum ACLK frequency
Maximum SMCLK frequency 16
40
(7) kHz
MHz
(1) Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range.
(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3) The minimum supply voltage is defined by the SVS levels. Refer to the SVS threshold parameters in
.
(4) A capacitor tolerance of ±20% or better is required.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(6) Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed without wait states.
(7) If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to comply with this operating condition.
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Specifications
13
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
5.4
Active Mode Supply Current Into V
CC
Excluding External Current
(1)
PARAMETER
I
AM, FRAM
(0%)
I
AM, FRAM
(100%)
I
AM, RAM
(2)
EXECUTION
MEMORY
FRAM
0% cache hit ratio
FRAM
100% cache hit ratio
RAM
TEST
CONDITIONS
3 V, 25°C
3 V, 85°C
3 V, 25°C
3 V, 85°C
3 V, 25°C
FREQUENCY (f
MCLK
= f
SMCLK
)
1 MHz
0 WAIT STATES
(NWAITSx = 0)
8 MHz
0 WAIT STATES
(NWAITSx = 0)
16 MHz
1 WAIT STATE
(NWAITSx = 1)
TYP
504
516
MAX TYP
2874
2919
MAX TYP
3156
3205
MAX
3700
1298 209
217
231
633
647
809
1056
1074
1450
(1) All inputs are tied to 0 V or to V
CC
. Outputs do not source or sink any current. Characterized with program executing typical data processing.
f
ACLK
= 32786 Hz, f
MCLK
= f
SMCLK
= f
DCO at specified frequency
Program and data entirely reside in FRAM. All execution is from FRAM.
(2) Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.
UNIT
µA
µA
µA
5.5
Active Mode Supply Current Per MHz
V
CC
= 3 V, T
A
= 25°C (unless otherwise noted)
PARAMETER
dI
AM,FRAM
/df
Active mode current consumption per MHz, execution from FRAM, no wait states
(1)
(1) All peripherals are turned on in default settings.
TEST CONDITIONS
((I
AM, 75% cache hit rate
(I
AM, 75% cache hit rate at 8 MHz) – at 1 MHz))
/ 7 MHz
TYP
126
UNIT
µA/MHz
5.6
Low-Power Mode LPM0 Supply Currents Into V
CC
V
CC
= 3 V, T
A
= 25°C (unless otherwise noted)
(1) (2)
Excluding External Current
FREQUENCY (f
SMCLK
)
PARAMETER V
CC
1 MHz
TYP MAX
8 MHz 16 MHz
TYP MAX TYP MAX
I
LPM0
Low-power mode LPM0 supply current
2 V
3 V
158
169
307
318
415
427
(1) All inputs are tied to 0 V or to V
CC
. Outputs do not source or sink any current.
(2) Current for watchdog timer clocked by SMCLK included.
f
ACLK
= 32786 Hz, f
MCLK
= 0 MHz, f
SMCLK at specified frequency.
UNIT
µA
14
Specifications
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
5.7
Low-Power Mode LPM3, LPM4 Supply Currents (Into V
CC
) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
I
LPM3,XT1
I
LPM3,VLO
I
LPM3, RTC
I
LPM4, SVS
I
LPM4
PARAMETER
Low-power mode 3, includes SVS
(2) (3) (4)
Low-power mode 3, VLO, excludes SVS
(5)
Low-power mode 3, RTC, excludes SVS
(6)
Low-power mode 4, includes SVS
Low-power mode 4, excludes SVS
V
CC
3 V
2 V
3 V
2 V
3 V
3 V
2 V
3 V
2 V
–40°C
TYP MAX
1.13
1.06
0.92
0.86
1.08
0.65
0.63
0.51
0.50
25°C 85°C
TYP MAX TYP MAX
1.31
1.21
1.99
3.00
2.94
1.75
1.00
1.00
1.25
2.89
2.75
3.04
0.75
0.73
0.58
0.57
1.88
1.85
1.51
1.49
UNIT
µA
µA
µA
µA
µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current
(2) Not applicable for devices with HF crystal oscillator only.
(3) Characterized with a GOLLEDGE MS1V-TK/I_32.768KHZ crystal with a load capacitance chosen to closely match the required load.
(4) Low-power mode 3, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), f
XT1
= 32768 Hz, f
ACLK
= f
XT1
, f
MCLK
= f
SMCLK
= 0 MHz
(5) Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3), f
XT1
= 0 Hz, f
ACLK
= f
MCLK
= f
SMCLK
= 0 MHz
(6) RTC periodically wakes up every second with external 32768-Hz as source.
5.8
Low-Power Mode LPMx.5 Supply Currents (Into V
CC
) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
I
LPM3.5, XT1
I
LPM4.5, SVS
I
LPM4.5
PARAMETER
Low-power mode 3.5, includes SVS
(1) (2) (3)
(also see
)
Low-power mode 4.5, includes SVS
(4)
Low-power mode 4.5, excludes SVS
(5)
V
CC
3 V
2 V
3 V
2 V
3 V
2 V
–40°C 25°C 85°C
TYP MAX TYP MAX TYP MAX
2.06
0.71
0.66
0.23
0.77
1.25
1.06
0.70
0.95
0.25
0.375
0.32
0.43
0.20
0.010
0.008
0.20
0.015
0.013
0.070
0.24
0.073
0.060
0.140
(1) Not applicable for devices with HF crystal oscillator only.
(2) Characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance chosen to closely match the required load.
(3) Low-power mode 3.5, includes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5), f
XT1
= 32768 Hz, f
ACLK
= f
XT1
, f
MCLK
= f
SMCLK
= 0 MHz
(4) Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5), f
XT1
= 0 Hz, f
ACLK
= f
MCLK
= f
SMCLK
= 0 MHz
(5) Low-power mode 4.5, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
f
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
XT1
= 0 Hz, f
ACLK
= f
MCLK
= f
SMCLK
= 0 MHz
UNIT
µA
µA
µA
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Specifications
15
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
5.9
Typical Characteristics, Low-Power Mode Supply Currents
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Temperature (°C)
LPM3
SVS disabled
DVCC = 3 V
RTC counter on
Figure 5-1. LPM3 Supply Current vs Temperature
3
2.5
2
1.5
1
0.5
0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
Temperature (°C)
LPM3.5
12.5-pF crystal on XT1
DVCC = 3 V
SVS enabled
Figure 5-2. LPM3.5 Supply Current vs Temperature
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
-40 -30 -20 -10 0
LPM4.5
10 20 30 40 50 60 70 80
Temperature (°C)
DVCC = 3 V SVS enabled
Figure 5-3. LPM4.5 Supply Current vs Temperature
16
Specifications
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
5.10 Typical Characteristics - Current Consumption Per Module
TEST CONDITIONS MODULE
Timer_A eUSCI_A eUSCI_A eUSCI_B eUSCI_B
RTC
CRC
UART mode
SPI mode
SPI mode
I
2
C mode, 100 kbaud
From start to end of operation
REFERENCE CLOCK
Module input clock
Module input clock
Module input clock
Module input clock
Module input clock
32 kHz
MCLK
TYP
5
7
5
5
5
85
8.5
UNIT
µA/MHz
µA/MHz
µA/MHz
µA/MHz
µA/MHz nA
µA/MHz
5.11 Thermal Characteristics
θ
JA
θ
JC, (TOP)
θ
JB
Ψ
JB
Ψ
JT
θ
JA
θ
JC, (TOP)
θ
JB
Ψ
JB
Ψ
JT
θ
JA
θ
JC, (TOP)
θ
JB
Ψ
JB
Ψ
JT
PARAMETERS
Junction-to-ambient thermal resistance, still air
(1)
Junction-to-case (top) thermal resistance
(2)
Junction-to-board thermal resistance
(3)
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-ambient thermal resistance, still air(
(1)
Junction-to-case (top) thermal resistance
(2)
Junction-to-board thermal resistance
(3)
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
Junction-to-ambient thermal resistance, still air(
(1)
Junction-to-case (top) thermal resistance
(2)
Junction-to-board thermal resistance
(3)
Junction-to-board thermal characterization parameter
Junction-to-top thermal characterization parameter
LQFP-64 (PM)
TSSOP-56 (DGG56)
TSSOP-48 (DGG48)
VALUE
61.7
25.4
32.7
32.4
2.5
62.4
18.7
31.4
31.1
0.8
68.9
23
35.8
35.3
1.1
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C.W
°C/W
°C/W
°C/W
°C/W
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold place test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold place fixture to control the PCB temperature, as described in JESD51-8.
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Specifications
17
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
5.12 Timing and Switching Characteristics
5.12.1 Power Supply Sequencing
V
Power Cycle Reset
V
SVS+
V
SVS–
SVS Reset BOR Reset
www.ti.com
V
BOR t
BOR
Figure 5-4. Power Cycle, SVS, and BOR Reset Conditions
Table 5-1. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
V
BOR, safe t
BOR, safe
I
SVSH,AM
I
SVSH,LPM
V
SVSH-
V
SVSH+
V
SVSH_hys t
PD,SVSH, AM t
PD,SVSH, LPM
V
REF, 1.2V
SVS
H
SVS
H
SVS
H
PARAMETER
Safe BOR power-down level
Safe BOR reset delay
SVS
H power-up level hysteresis
1.2-V REF voltage
(3)
(2)
SVS
H power-down level
(1)
SVS
H current consumption, active mode
SVS
H current consumption, low-power modes propagation delay, active mode propagation delay, low-power modes
V
V
CC
CC
TEST CONDITIONS
= 3.6 V
= 3.6 V
MIN
0.1
10
1.71
1.76
1.158
TYP
240
1.81
1.88
70
1.200
MAX
1.5
1.87
1.99
nA
V
V mV
10 µs
100
1.242
UNIT
V ms
µA
µs
V
(1) A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.
(2) When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches V
SVSH+
.
(3) This is a characterized result with external 1-mA load to ground from –40°C to +85°C.
t
18
Specifications
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
5.12.2 Reset Timing
Table 5-2. Wake-Up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
V
CC
MIN TYP
t
WAKE-UP FRAM
Additional wake-up time to activate the FRAM in
AM if previously disabled by the FRAM controller or from a LPM if immediate activation is selected for wakeup
(1)
3 V 10
MAX UNIT
µs t
WAKE-UP LPM0
Wake-up time from LPM0 to active mode
(1)
3V
200 ns +
2.5/f
DCO t t
WAKE-UP LPM3 t
WAKE-UP LPM4 t
WAKE-UP LPM3.5
WAKE-UP LPM4.5
Wake-up time from LPM3 to active mode
Wake-up time from LPM4 to active mode
(2)
Wake-up time from LPM3.5 to active mode
(2)
Wake-up time from LPM4.5 to active mode
(2)
SVSHE = 1
SVSHE = 0
3 V
3 V
3 V
3 V
3 V
10
10
350
350
1 t t
WAKE-UP-RESET
RESET
Wake-up time from RST or BOR event to active mode
(2)
Pulse duration required at RST/NMI pin to accept a reset
3 V
3 V 2
1 ms
µs
(1) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first externally observable MCLK clock edge.
(2) The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first instruction of the user program is executed.
µs
µs
µs
µs ms
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Specifications
19
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
5.12.3 Clock Specifications
Table 5-3. XT1 Crystal Oscillator (Low Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1) f
XT1, LF
PARAMETER
XT1 oscillator crystal, low frequency
TEST CONDITIONS
LFXTBYPASS = 0
V
CC
MIN TYP
32768
MAX UNIT
Hz
DC
XT1, LF
XT1 oscillator LF duty cycle f
Measured at MCLK,
LFXT
= 32768 Hz
30% 70% f
XT1,SW
DC
OA
C
XT1, SW
LFXT
L,eff
XT1 oscillator logic-level squarewave input frequency
LFXT oscillator logic-level squarewave input duty cycle
Oscillation allowance for
LF crystals
(4)
Integrated effective load capacitance
(5) f
LFXTBYPASS = 1
LFXTBYPASS = 1
See
(6)
(2) (3)
LFXTBYPASS = 0, LFXTDRIVE = {3},
LFXT
= 32768 Hz, C
L,eff
= 12.5 pF
40%
32768
200
1
60%
Hz k Ω pF t
START,LFXT
Start-up time
(7) f
OSC
= 32768 Hz
LFXTBYPASS = 0, LFXTDRIVE = {3},
T
A
= 25°C, C
L,eff
= 12.5 pF
XTS = 0
(9)
1000 ms f
Fault,LFXT
Oscillator fault frequency
(8)
0 3500 Hz
(1) To improve EMI on the LFXT oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DC
LFXT, SW
(3) Maximum frequency of operation of the entire device cannot be exceeded.
.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, C
L,eff
= 3.7 pF.
• For LFXTDRIVE = {1}, 6 pF ≤ C
L,eff
≤ 9 pF.
• For LFXTDRIVE = {2}, 6 pF ≤ C
L,eff
• For LFXTDRIVE = {3}, 6 pF ≤ C
L,eff
≤ 10 pF.
≤ 12 pF.
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Includes start-up counter of 1024 clock cycles.
(8) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX specification may set the flag. A static condition or stuck at fault condition sets the flag.
(9) Measured with logic-level input frequency but also applies to operation with crystals.
20
Specifications
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 5-4. DCO FLL, Frequency
over recommended operating free-air temperature (unless otherwise noted) f
DCO, FLL
PARAMETER
FLL lock frequency, 16 MHz, 25°C
FLL lock frequency, 16 MHz, –40°C to +85°C
TEST CONDITIONS
Measured at MCLK, Internal trimmed REFO as reference
FLL lock frequency, 16 MHz, –40°C to +85°C
Measured at MCLK, XT1 crystal as reference f
DUTY
Jitter cc
Jitter long t
FLL, lock
Duty cycle
Cycle-to-cycle jitter, 16 MHz
Long-term jitter, 16 MHz
FLL lock time
Measured at MCLK, XT1 crystal as reference
V
CC
3 V
MIN
–1.0%
–2.0%
–0.5%
40%
3 V
TYP MAX UNIT
1.0%
2.0%
0.5%
50% 60%
0.25%
0.022%
120 ms
Table 5-5. REFO
over recommended operating free-air temperature (unless otherwise noted)
I
REFO f
REFO df
REFO
/d
T df
REFO
/ d
VCC f
DC t
START
PARAMETER
REFO oscillator current consumption
REFO calibrated frequency
REFO absolute calibrated tolerance
REFO frequency temperature drift
REFO frequency supply voltage drift
REFO duty cycle
REFO start-up time
TEST CONDITIONS
T
A
= 25°C
Measured at MCLK
–40°C to +85°C
Measured at MCLK
(1)
Measured at MCLK at
25°C
(2)
Measured at MCLK
40% to 60% duty cycle
V
CC
3 V
3 V
1.8 V to 3.6 V –3.5%
3 V
1.8 V to 3.6 V
1.8 V to 3.6 V
MIN
40%
TYP
15
32768
0.01
1
50%
50
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
MAX
3.5%
60%
UNIT
µA
Hz
%/°C
%/V
µs
Table 5-6. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
TEST CONDITIONS V
CC
3 V
MIN TYP MAX UNIT
10 kHz f
VLO df
VLO
/d
T df
VLO
/dV
CC f
VLO,DC
VLO frequency temperature drift
VLO frequency supply voltage drift
Duty cycle
Measured at MCLK
Measured at MCLK
(1)
Measured at MCLK
(2)
Measured at MCLK
3 V
1.8 V to 3.6 V
3 V
0.5
4
50%
%/°C
%/V
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Table 5-7. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
V
CC
MIN TYP MAX UNIT
f
MODOSC f
MODOSC
/dT f
MODOSC
/dV
CC f
MODOSC,DC
MODOSC frequency
MODOSC frequency temperature drift
MODOSC frequency supply voltage drift
Duty cycle
3 V
3 V
1.8 V to 3.6 V
3 V
3.8
4.8
0.102
5.8
1.02
40% 50% 60%
MHz
%/ ℃
%/V
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Specifications
21
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
5.12.4 Digital I/Os
Table 5-8. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
V
V
V
IT+
IT– hys
PARAMETER
Positive-going input threshold voltage
Negative-going input threshold voltage
Input voltage hysteresis (V
IT+
– V
IT–
)
TEST CONDITIONS V
CC
2 V
3 V
2 V
3 V
2 V
3 V
MIN
0.90
1.35
0.50
0.75
0.3
0.4
TYP MAX UNIT
1.50
V
2.25
1.10
V
1.65
0.8
1.2
V
R
Pull
C
I,dig
Pullup or pulldown resistor
Input capacitance, digital only port pins
For pullup: V
IN
= V
SS
For pulldown: V
IN
= V
CC
V
IN
= V
SS or V
CC
20 35
3
50 k Ω pF
C
I,ana
Input capacitance, port pins with shared analog functions
High-impedance leakage current
(1) (2)
V
IN
= V
SS or V
CC
5 pF
I lkg(Px.y)
2 V, 3 V –20 20
(1) The leakage current is measured with V
SS or V
CC applied to the corresponding pins, unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled.
nA
Table 5-9. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
V
OH
V
OL f
Port_CLK t rise,dig t fall,dig
PARAMETER
High-level output voltage
Low-level output voltage
Clock output frequency
Port output rise time, digital only port pins
Port output fall time, digital only port pins
TEST CONDITIONS
I
(OHmax)
= –3 mA
(1)
I
(OHmax)
= –5 mA
(1)
I
(OLmax)
= 3 mA
(1)
I
(OHmax)
= 5 mA
(1)
C
L
= 20 pF
(2)
C
L
= 20 pF
C
L
= 20 pF
V
CC
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
MIN TYP MAX UNIT
1.4
2.0
V
2.4
3.0
0.0
0.0
16
16
0.60
0.60
V
MHz
10
7
10
5 ns ns
(1) The maximum total current, I
(OHmax) specified.
and I
(OLmax)
, for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
(2) The port can output frequencies at least up to the specified limit and might support higher frequencies.
22
Specifications
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
5.12.4.1 Digital I/O Typical Characteristics
25
20
T = 85°C
A
T = 25°C
A
15
10
7.5
T = 85°C
A
T = 25°C
A
5
10
5
2.5
0
0 0.5
1 1.5
2 2.5
Low-Level Output Voltage (V)
Figure 5-5. Typical Low-Level Output Current vs Low-Level
Output Voltage (DVCC = 3 V)
3
0
-5
T = 85°C
A
T = 25°C
A
0
0 0.25
0.5
0.75
1 1.25
1.5
1.75
Low-Level Output Voltage (V)
Figure 5-6. Typical Low-Level Output Current vs Low-Level
Output Voltage (DVCC = 2 V)
2
0
T = 85°C
A
T = 25°C
A -2.5
-10
-5
-15
-7.5
-20
-25
0 0.5
1 1.5
2 2.5
High-Level Output Voltage (V)
Figure 5-7. Typical High-Level Output Current vs High-Level
Output Voltage (DVCC = 3 V)
3
-10
0 0.25
0.5
0.75
1 1.25
1.5
1.75
High-Level Output Voltage (V)
Figure 5-8. Typical High-Level Output Current vs High-Level
Output Voltage (DVCC = 2 V)
2
5.12.5 Timer_A
Table 5-10. Timer_A Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) f
TA
PARAMETER
Timer_A input clock frequency
TEST CONDITIONS
Internal: SMCLK, ACLK
External: TACLK
Duty cycle = 50% ±10%
V
CC
2 V, 3 V
MIN MAX UNIT
16 MHz
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Specifications
23
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
5.12.6 eUSCI
Table 5-11. eUSCI (UART Mode) Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) f eUSCI
PARAMETER
eUSCI input clock frequency
TEST CONDITIONS
Internal: SMCLK, MODCLK
External: UCLK
Duty cycle = 50% ±10%
V
CC
2 V, 3 V
MIN
f
BITCLK
BITCLK clock frequency
(equals baud rate in Mbaud)
2 V, 3 V
MAX UNIT
16 MHz
5 MHz t t
Table 5-12. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
UART receive deglitch time
(1)
TEST CONDITIONS
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
V
CC
2 V, 3 V
TYP UNIT
12
40
68
110 ns
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Table 5-13. eUSCI (SPI Master Mode) Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER CONDITIONS MIN
f eUSCI eUSCI input clock frequency
Internal: SMCLK, MODCLK
Duty cycle = 50% ±10%
MAX UNIT
8 MHz
Table 5-14. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS V
CC
MIN
t t
STE,LEAD
STE,LAG
STE lead time, STE active to clock
STE lag time, Last clock to STE inactive
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
1
1
MAX UNIT
UCxCLK cycles
UCxCLK cycles t t t
SU,MI
HD,MI
VALID,MO
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time
(2)
UCLK edge to SIMO valid,
C
L
= 20 pF
2 V
3 V
2 V
3 V
2 V
3 V
2 V
3 V
45
35
0
0
20
20 ns ns ns t
HD,MO
SIMO output data hold time
(3)
C
L
= 20 pF
0
0 ns
(1) f
UCxCLK
= 1/2t
LO/HI with t
LO/HI
= max(t
VALID,MO(eUSCI)
For the slave parameters t
SU,SI(Slave) and t
+ t
SU,SI(Slave)
VALID,SO(Slave)
, t
SU,MI(eUSCI)
+ t
VALID,SO(Slave)
).
refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing diagrams in
and
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
and
24
Specifications
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
1/f
UCxCLK
CKPL = 0
UCLK
CKPL = 1 t
LOW/HIGH t
LOW/HIGH t
SU,MI t
HD,MI
SOMI t
VALID,MO
SIMO
CKPL = 0
UCLK
CKPL = 1
Figure 5-9. SPI Master Mode, CKPH = 0
1/f
UCxCLK t
LOW/HIGH t
LOW/HIGH t
SU,MI
SOMI t
HD,MI t
VALID,MO
SIMO
Figure 5-10. SPI Master Mode, CKPH = 1
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Specifications
25
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
Table 5-15. eUSCI (SPI Slave Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS
t
STE,LEAD t
STE,LAG t
STE,ACC t
STE,DIS t
SU,SI t
HD,SI t
VALID,SO t
HD,SO
STE lead time, STE active to clock
STE lag time, Last clock to STE inactive
STE access time, STE active to SOMI data out
STE disable time, STE inactive to SOMI high impedance
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time
(2)
SOMI output data hold time
(3)
UCLK edge to SOMI valid,
C
L
= 20 pF
C
L
= 20 pF
3 V
2 V
3 V
2 V
3 V
V
CC
2 V
3 V
2 V
3 V
2 V
2 V
3 V
2 V
3 V
2 V
3 V
MIN
55
45
20
20
12
12
4
4
5
5
MAX UNIT
65
40
40
35
65
40
(1) f
UCxCLK
= 1/2t
LO/HI with t
LO/HI
For the master parameters t
≥ max(t
VALID,MO(Master)
SU,MI(Master) and t
+ t
SU,SI(eUSCI)
VALID,MO(Master)
, t
SU,MI(Master)
+ t
VALID,SO(eUSCI)
).
refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing diagrams in
and
.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
and
.
ns ns ns ns ns ns ns ns
26
Specifications
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
t
STE,LEAD
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
t
STE,LAG
STE
1/f
UCxCLK
UCLK
CKPL = 0
CKPL = 1 t
LOW/HIGH t
LOW/HIGH t
SU,SIMO t
HD,SIMO
SIMO t
ACC t
VALID,SOMI t
DIS
SOMI
STE
UCLK
CKPL = 0
CKPL = 1
Figure 5-11. SPI Slave Mode, CKPH = 0 t
STE,LEAD t
STE,LAG
1/f
UCxCLK t
LOW/HIGH t
LOW/HIGH t
HD,SI t
SU,SI
SIMO t
ACC t
VALID,SO t
DIS
SOMI
Figure 5-12. SPI Slave Mode, CKPH = 1
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Specifications
27
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
Table 5-16. eUSCI (I
2
C Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
f eUSCI
PARAMETER
eUSCI input clock frequency
TEST CONDITIONS
Internal: SMCLK, MODCLK
External: UCLK
Duty cycle = 50% ±10%
V
CC
MIN TYP MAX UNIT
16 MHz f
SCL t
HD,STA t
SU,STA t
HD,DAT t
SU,DAT t
SU,STO t
SP t
TIMEOUT
SCL clock frequency
Hold time (repeated) START
Setup time for a repeated START
Data hold time
Data setup time
Setup time for STOP
Pulse duration of spikes suppressed by input filter
Clock low time-out f
SCL
= 100 kHz f
SCL
> 100 kHz f
SCL
= 100 kHz f
SCL
> 100 kHz f
SCL
= 100 kHz f
SCL
> 100 kHz
UCGLITx = 0
UCGLITx = 1
UCGLITx = 2
UCGLITx = 3
UCCLTOx = 1
UCCLTOx = 2
UCCLTOx = 3
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V, 3 V
50
25
12.5
6.3
0.6
0
250
4.0
0.6
0
4.0
0.6
4.7
27
30
33
400 kHz
600
300
150
75
µs
µs ns ns
µs ns ms
t
HD,STA t
SU,STA t
HD,STA t
BUF
SDA t
LOW t
HIGH t
SP
SCL t
SU,STO t
HD,DAT t
SU,DAT
Figure 5-13. I
2
C Mode Timing
28
Specifications
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
5.12.7 ADC
Table 5-17. ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
DV
CC
V
(Ax)
I
ADC
PARAMETER
ADC supply voltage
Analog input voltage range
Operating supply current into
DVCC terminal, reference current not included, repeatsingle-channel mode
All ADC pins
TEST CONDITIONS
f
ADCCLK
= 5 MHz, ADCON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADCDIV = 0, ADCCONSEQx = 10b
C
I
R
I
Input capacitance
Input MUX ON resistance
Only one terminal Ax can be selected at one time from the pad to the ADC capacitor array, including wiring and pad
DV
CC
= 2 V, 0 V = V
Ax
= DV
CC
V
CC
2 V
3 V
2.2 V
MIN
2.0
0
TYP MAX UNIT
3.6
V
DV
CC
V
185
µA
207
1.6
2.0
pF
2 k Ω
Table 5-18. ADC, 10-Bit Timing Parameters
over operating free-air temperature range (unless otherwise noted) f
ADCCLK
PARAMETER TEST CONDITIONS
For specified performance of ADC linearity parameters f
ADCOSC
Internal ADC oscillator
(MODOSC)
ADCDIV = 0, f
ADCCLK
= f
ADCOSC t
CONVERT t
ADCON t
Sample
Conversion time
Turnon settling time of the ADC
Sampling time
REFON = 0, Internal oscillator,
10 ADCCLK cycles, 10-bit mode, f
ADCOSC
= 4.5 MHz to 5.5 MHz
External f
ADCCLK
ADCSSEL ≠ 0 from ACLK, MCLK, or SMCLK,
The error in a conversion started after t
ADCON than ±0.5 LSB,
Reference and input signal already settled is less
R
S
= 1000 Ω, R
I
= 36000 Ω, C
I
= 3.5 pF,
Approximately eight Tau (t) are required for an error of less than ±0.5 LSB
V
CC
2 V to
3.6 V
2 V to
3.6 V
2 V to
3.6 V
2 V to
3.6 V
2 V
3 V
(1) 12 × ADCDIV × 1/f
ADCCLK
MIN TYP MAX UNIT
0.45
5 5.5
MHz
4.5
5.0
5.5
MHz
2.18
1.5
2.0
(1)
2.67
µs
100 ns
µs
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Specifications
29
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
Table 5-19. ADC, 10-Bit Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS
E
I
E
D
E
O
Integral linearity error (10-bit mode)
Integral linearity error (8-bit mode)
Differential linearity error (10-bit mode)
Differential linearity error (8-bit mode)
Offset error (10-bit mode)
Offset error (8-bit mode)
V
DVCC as reference
V
DVCC as reference
V
DVCC as reference
V
CC
2.4 V to
3.6 V
2 V to
3.6 V
2.4 V to
3.6 V
2 V to
3.6 V
2.4 V to
3.6 V
2 V to
3.6 V
E
G
E
T
V
SENSOR
TC
SENSOR t
SENSOR
(sample)
Gain error (10-bit mode)
Gain error (8-bit mode)
Total unadjusted error (10-bit mode)
Total unadjusted error (8-bit mode)
See
(1)
See
(2)
Sample time required if channel 12 is selected
(3)
V
DVCC as reference
Internal 1.5-V reference
V
DVCC as reference
Internal 1.5-V reference
V
DVCC as reference
Internal 1.5-V reference
V
DVCC as reference
Internal 1.5-V reference
ADCON = 1, INCH = 0Ch, T
A
= 0°C
ADCON = 1, INCH = 0Ch
ADCON = 1, INCH = 0Ch, Error of conversion result ≤ 1 LSB, AM and all
LPM above LPM3
ADCON = 1, INCH = 0Ch, Error of conversion result ≤ 1 LSB, LPM3
2.4 V to
3.6 V
2 V to
3.6 V
2.4 V to
3.6 V
2 V to
3.6 V
3 V
3 V
3 V
3 V
MIN TYP MAX UNIT
–2
–2
–1
–1
–6.5
–6.5
–2.0
–3.0%
–2.0
–3.0%
–2.0
–3.0%
–2.0
–3.0%
30
100
1.013
3.35
2
2
1
1
6.5
6.5
LSB
LSB mV
2.0
LSB
3.0%
2.0
LSB
3.0%
2.0
LSB
3.0%
2.0
LSB
3.0% mV mV/°C
µs
(1) The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in temperature sensor.
(2) The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage levels. The sensor voltage can be computed as V
SENSE
= TC be computed from the calibration values for higher accuracy.
SENSOR
× (Temperature, °C) + V
SENSOR
, where TC
SENSOR and V
SENSOR
(3) The typical equivalent impedance of the sensor is 700 k Ω. The sample time required includes the sensor-on time t
SENSOR(on)
.
can
30
Specifications
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
5.12.8 FRAM
Table 5-20. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Read and write endurance
TEST CONDITIONS
t
Retention
Data retention duration
T
J
= 25°C
T
J
= 70°C
T
J
= 85°C
MIN
10
15
100
40
10
5.12.9 Emulation and Debug
MAX UNIT
cycles years
Table 5-21. JTAG and Spy-Bi-Wire Interface Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) f
SBW t
SBW,Low t
SBW, En t
SBW,Rst f
TCK
R internal
PARAMETER
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse duration
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)
(1)
Spy-Bi-Wire return to normal operation time
TCK input frequency, 4-wire JTAG
(2)
Internal pulldown resistance on TEST
V
CC
2 V, 3 V
2 V, 3 V
2 V, 3 V
2 V
3 V
2 V, 3 V
MIN TYP MAX UNIT
0
0.028
10
15
MHz
µs
15
0
0
20 35
110 µs
100 µs
16
MHz
16
50 k Ω
(1) Tools that access the Spy-Bi-Wire interface must wait for the t
SBW,En first SBWTCK clock edge.
(2) f
TCK time after pulling the TEST/SBWTCK pin high before applying the may be restricted to meet the timing requirements of the module selected.
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Specifications
31
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
6 Detailed Description
6.1
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register
(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.
6.2
Operating Modes
The MSP430 has one active mode and several software selectable low-power modes of operation. An interrupt event can wake up the device from low-power mode LPM0 or LPM3, service the request, and restore back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5 and
LPM4.5 disable the core supply to minimize power consumption.
Maximum System Clock
Power Consumption at 25°C, 3 V
Wake-up time
Wake-up events
Power
Clock
Core
MODE
Regulator
SVS
Brown Out
MCLK
SMCLK
FLL
DCO
MODCLK
REFO
ACLK
XT1CLK
VLOCLK
CPU
FRAM
RAM
Backup Memory
(1)
AM
ACTIVE
MODE
16 MHz
Table 6-1. Operating Modes
LPM0
126 µA/MHz
N/A
N/A
Full
Regulation
On
On
Active
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
On
On
On
On
CPU OFF
16 MHz
20 µA/MHz instant
All
Full
Regulation
On
On
Off
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Off
On
On
On
LPM3
STANDBY
LPM4
OFF
LPM3.5
ONLY RTC
COUNTER
40 kHz 40 kHz
1.2 µA
0
0.6 µA without SVS
10 µs
0.77 µA with
RTC only
150 µs 10 µs
All I/O
RTC Counter,
I/O
Partial Power Partial Power Partial Power
Down Down Down
Optional
On
Optional
On
Optional
On
Off
Off
Off
Off
Off
Optional
Optional
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Optional
Optional
Off
Off
On
On
Off
Off
Off
Off
On
On
Optional
Optional
Off
Off
Off
On
LPM4.5
SHUTDOWN
0
13 nA without SVS
150 µs
I/O
Power Down
Optional
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
(1) Backup memory contains one 32-byte register in the peripheral memory space. Refer to
and
for its memory allocation.
32
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Peripherals
I/O
MODE
Timer0_A3
Timer1_A3
WDT eUSCI_A0 eUSCI_B0
CRC
ADC
RTC Counter
General Digital
Input/Output
Capacitive Touch I/O
Table 6-1. Operating Modes (continued)
AM
ACTIVE
MODE
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
LPM0
CPU OFF
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
LPM3
STANDBY
Optional
Optional
Optional
Off
Off
Off
Optional
Optional
LPM4
OFF
Off
Off
Off
Off
Off
Off
Off
Off
On Optional State Held State Held
Optional Optional Optional Off
LPM3.5
ONLY RTC
COUNTER
Off
Off
Off
Off
Off
Off
Off
State Held
Off
Off
LPM4.5
SHUTDOWN
Off
Off
Off
Off
Off
Off
Off
Off
State Held
Off
6.3
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence
INTERRUPT SOURCE
Table 6-2. Interrupt Sources, Flags, and Vectors
INTERRUPT FLAG
SYSTEM
INTERRUPT
System Reset
Power-up, Brownout, Supply Supervisor
External Reset RST
Watchdog Time-out, Key Violation
FRAM uncorrectable bit error detection
Software POR,
FLL unlock error
SVSHIFG
PMMRSTIFG
WDTIFG
PMMPORIFG, PMMBORIFG
SYSRSTIV
FLLUNLOCKIFG
Reset
System NMI
Vacant Memory Access
JTAG Mailbox
FRAM bit error detection
User NMI
External NMI
Oscillator Fault
Timer0_A3
Timer0_A3
Timer1_A3
Timer1_A3
RTC Counter
Watchdog Timer Interval mode eUSCI_A0 Receive or Transmit
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
NMIIFG
OFIFG
TA0CCR0 CCIFG0
TA0CCR1 CCIFG1, TA0CCR2
CCIFG2, TA0IFG (TA0IV)
TA1CCR0 CCIFG0
TA1CCR1 CCIFG1, TA1CCR2
CCIFG2, TA1IFG (TA1IV)
RTCIFG
WDTIFG
UCTXCPTIFG, UCSTTIFG,
UCRXIFG, UCTXIFG (UART mode)
UCRXIFG, UCTXIFG (SPI mode)
(UCA0IV))
Nonmaskable
Nonmaskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
Maskable
WORD
ADDRESS
FFFEh
FFFCh
FFFAh
FFF8h
FFF6h
FFF4h
FFF2h
FFF0h
FFEEh
FFECh
PRIORITY
63, Highest
62
61
60
59
58
57
56
55
54
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
33
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
Table 6-2. Interrupt Sources, Flags, and Vectors (continued)
INTERRUPT SOURCE INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
eUSCI_B0 Receive or Transmit
ADC
P1
P2
Reserved
Signatures
UCB0RXIFG, UCB0TXIFG (SPI mode)
UCALIFG, UCNACKIFG,
UCSTTIFG, UCSTPIFG,
UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1,
UCRXIFG2, UCTXIFG2,
UCRXIFG3, UCTXIFG3,
UCCNTIFG, UCBIT9IFG (I
2
C mode)
(UCB0IV)
ADCIFG0, ADCINIFG,
ADCLOIFG, ADCHIIFG,
ADCTOVIFG, ADCOVIFG
(ADCIV)
P1IFG.0 to P1IFG.7 (P1IV)
P2IFG.0 to P2IFG.7 (P2IV)
Reserved
BSL Signature 2
BSL Signature 1
JTAG Signature 2
JTAG Signature 1
Maskable
Maskable
Maskable
Maskable
Maskable
FFEAh
FFE8h
FFE6h
FFE4h
FFE2h-FF88h
0FF86h
0FF84h
0FF82h
0FF80h
PRIORITY
53
52
51
50, Lowest
6.4
Bootstrap Loader (BSL)
The BSL enables users to program the FRAM or RAM using a UART serial interface. Access to the device memory through the BSL is protected by an user-defined password. Use of the BSL requires four pins as shown in
Table 6-3 . BSL entry requires a specific entry sequence on the RST/NMISBWTDIO and
TEST/SBWTCK pins. For a complete description of the features of the BSL and its implementation, see the MSP430FR4xx and MSP430FR2xx Bootstrap Loader (BSL) User's Guide ( SLAU610 ).
Table 6-3. BSL Pin Requirements and Functions
DEVICE SIGNAL
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.0
P1.1
VCC
VSS
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
Data receive
Power Supply
Ground Supply
6.5
JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with
MSP430 development tools and device programmers. The JTAG pin requirements are shown in
. For further details on interfacing to development tools and device programmers, see the MSP430
Hardware Tools User's Guide ( SLAU278 ). For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming Via the JTAG Interface ( SLAU320 ).
34
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-4. JTAG Pin Requirements and Function
DEVICE SIGNAL
P1.4/MCLK/TCK/A4/VREF+
P1.5/TA0CLK/TMS/A5
P1.6/TA0.2/TDI/TCLK/A6
P1.7/TA0.1/TDO/A7
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
VSS
DIRECTION
IN
IN
IN
OUT
IN
IN
JTAG FUNCTION
JTAG clock input
JTAG state control
JTAG data input/TCLK input
JTAG data output
Enable JTAG pins
External Reset
Power Supply
Ground Supply
6.6
Spy-Bi-Wire Interface (SBW)
The MSP430 family supports the 2-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with
MSP430 development tools and device programmers.
shows the Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device programmers, refer to the
MSP430 Hardware Tools User's Guide ( SLAU278 ).
Table 6-5. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
VSS
DIRECTION
IN
IN, OUT
SBW FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input/output
Power Supply
Ground Supply
6.7
FRAM
The FRAM can be programmed using the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
• Byte and word access capability
• Programmable wait state generation
• Error correction coding (ECC)
6.8
Memory Protection
The device features memory protection that can restrict user access and enable write protection:
• Securing the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing
JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in-system by the CPU.
• Write protection enabled to prevent unwanted write operation to FRAM contents by setting the control bits in System Configuration register 0. For more detailed information, refer to the SYS chapter in the
MSP430FR4xx and MSP430FR2xx Family User's Guide ( SLAU445 ).
NOTE
The FRAM is protected by default on PUC. To write to FRAM during code execution, the application must first clear the corresponding PFWP or DFWP bit in System Configuration
Register 0 to unprotect the FRAM.
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
35
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
6.9
Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be handled by using all instructions in the memory map. For complete module description, see the
MSP430FR4xx and MSP430FR2xx Family User's Guide ( SLAU445 ).
6.9.1
Power Management Module (PMM) and On-chip Reference Voltages
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR) is implemented to provide the proper internal reset signal to the device during power-on and power-off.
The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is available on the primary supply.
The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.
The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC channel 15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily represent as
by using ADC sampling 1.5-V reference without any external components support.
DVCC = (1023 × 1.5 V) ÷ 1.5-V Reference ADC result (1)
A 1.2-V reference voltage can be buffered and output to P1.4/MCLK/TCK/A4/VREF+, when the ADC channel 4 is selected as the function. For more detailed information, refer to the MSP430FR4xx and
MSP430FR2xx Family User's Guide ( SLAU445 ).
6.9.2
Clock System (CS) and Clock Distribution
The clock system includes a 32-kHz crystal oscillator (XT1), an internal very low-power low-frequency oscillator (VLO), an integrated 32-kHz RC oscillator (REFO), an integrated internal digitally controlled oscillator (DCO) that may use frequency-locked loop (FLL) locking with internal or external 32-kHz reference clock, and on-chip asynchronous high-speed clock (MODOSC). The clock system is designed to target cost-effective designs with minimal external components. A fail-safe mechanism is designed for
XT1. The clock system module offers the following clock signals.
• Main Clock (MCLK): the system clock used by the CPU and all relevant peripherals accessed by the bus. All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8,
16, 32, 64, or 128.
• Sub-Main Clock (SMCLK): the subsystem clock used by the peripheral modules. SMCLK derives from the MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
• Auxiliary Clock (ACLK): this clock is derived from the external XT1 clock or internal REFO clock up to
40 kHz.
All peripherals may have one or several clock sources depending on specific functionality.
shows the clock distribution used in this device.
36
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-6. Clock Distribution
CLOCK
SOURCE
SELECT
BITS
MCLK SMCLK ACLK MODCLK XT1CLK
(1)
VLOCLK EXTERNAL PIN
Frequency
Range
CPU
FRAM
RAM
CRC
I/O
TA0
TA1 eUSCI_A0 eUSCI_B0
WDT
ADC
RTC
N/A
N/A
N/A
N/A
N/A
TASSEL
TASSEL
UCSSEL
UCSSEL
WDTSSEL
ADCSSEL
RTCSS
DC to
16 MHz
Default
Default
Default
Default
Default
DC to
16 MHz
10b
10b
10b or 11b
10b or 11b
00b
11b
01b
DC to
40 kHz
01b
01b
01b
01b
5 MHz ±10%
01b
01b
00b
DC to
40 kHz
10b
10 kHz
±50%
10b
11b
00b (TA0CLK pin)
00b (TA1CLK pin)
00b (UCA0CLK pin)
00b (UCB0CLK pin)
(1) To enable XT1 functionality, configure P4SEL0.1 (XIN) and P4SEL0.2 (XOUT) before configuring the Clock System registers.
6.9.3
General-Purpose Input/Output Port (I/O)
There are up to 60 I/O ports implemented, depending on the package.
• P1, P2, P3, P4, P5, P6, and P7 are full 8-bit ports; P8 has 4 bits implemented.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• Capacitive Touch I/O functionality is supported on all pins.
NOTE
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For details, refer to the Configuration After Reset section in the Digital I/O chapter of the
MSP430FR4xx and MSP430FR2xx Family User's Guide ( SLAU445 )
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
37
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
6.9.4
Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as interval timer and can generate interrupts at selected time intervals.
WDTSSELx
00
01
10
11
Table 6-7. WDT Clocks
NORMAL OPERATION
(WATCHDOG AND INTERVAL TIMER MODE)
SMCLK
ACLK
VLOCLK
VLOCLK
6.9.5
System Module (SYS)
The SYS module handles many of the system functions within the device. These include Power-On Reset
(POR) and Power-Up Clear (PUC) handling, NMI source selection and management, reset interrupt vector generators, bootstrap loader entry mechanisms, and configuration management (device descriptors). SYS also includes a data exchange mechanism through SBW called a JTAG mailbox mail box that can be used in the application.
Table 6-8. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
ADDRESS PRIORITY
SYSRSTIV, System Reset 015Eh
INTERRUPT EVENT
No interrupt pending
Brownout (BOR)
RSTIFG RST/NMI (BOR)
PMMSWBOR software BOR (BOR)
LPMx.5 wakeup (BOR)
Security violation (BOR)
Reserved
SVSHIFG SVSH event (BOR)
Reserved
Reserved
PMMSWPOR software POR (POR)
WDTIFG watchdog time-out (PUC)
WDTPW password violation (PUC)
FRCTLPW password violation (PUC)
Uncorrectable FRAM bit error detection
Peripheral area fetch (PUC)
PMMPW PMM password violation (PUC)
Reserved
FLL unlock (PUC)
Reserved
VALUE
0Ch
0Eh
10h
12h
14h
16h
18h
00h
02h
04h
06h
08h
0Ah
1Ah
1Ch
1Eh
20h
22h
24h
26h to 3Eh
Highest
Lowest
38
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
INTERRUPT VECTOR
REGISTER
SYSSNIV, System NMI
SYSUNIV, User NMI
Table 6-8. System Module Interrupt Vector Registers (continued)
ADDRESS
015Ch
015Ah
INTERRUPT EVENT
No interrupt pending
SVS low-power reset entry
Uncorrectable FRAM bit error detection
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VMAIFG Vacant memory access
JMBINIFG JTAG mailbox input
JMBOUTIFG JTAG mailbox output
Correctable FRAM bit error detection
Reserved
No interrupt pending
NMIFG NMI pin or SVS
H event
OFIFG oscillator fault
Reserved
VALUE
0Ch
0Eh
10h
12h
14h
16h
18h
00h
02h
04h
06h
08h
0Ah
1Ah to 1Eh
00h
02h
04h
06h to 1Eh
PRIORITY
Highest
Lowest
Highest
Lowest
6.9.6
Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data values and can be used for data checking purposes. The CRC generation polynomial is compliant with
CRC-16-CCITT standard of x
16
+ x
12
+ x
5
+ 1.
6.9.7
Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
The eUSCI modules are used for serial data communications. The eUSCI_A module supports either
UART or SPI communications. The eUSCI_B module supports either SPI or I
2
C communications.
Additionally, eUSCI_A supports automatic baud-rate detection and IrDA.
Table 6-9. eUSCI Pin Configurations
eUSCI_A0 eUSCI_B0
PIN
P5.0
P5.1
P5.2
P5.3
PIN
P1.0
P1.1
P1.2
P1.3
UART
TXD
RXD
I
2
C
SDA
SCL
SPI
SIMO
SOMI
SCLK
STE
SPI
STE
SCLK
SIMO
SOMI
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
39
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
6.9.8
Timers (Timer0_A3, Timer1_A3)
The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare registers each. Each timer can support multiple captures or compares, PWM outputs, and interval timing.
Each timer has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. The CCR0 registers on both TA0 and TA1 are not externally connected and can only be used for hardware period timing and interrupt generation. In Up mode, they can be used to set the overflow value of the counter.
PORT PIN
P1.5
P1.7
P1.6
Table 6-10. Timer0_A3 Signal Connections
DEVICE INPUT
SIGNAL
TA0CLK
ACLK (internal)
SMCLK (internal)
From Capacitive
Touch I/O (internal)
MODULE INPUT
NAME
TACLK
ACLK
SMCLK
INCLK
MODULE BLOCK
Timer
MODULE OUTPUT
SIGNAL
N/A
CCI0A
CCI0B
CCR0 TA0
DVSS
DVCC
TA0.1
From RTC (internal)
GND
VCC
CCI1A
CCI1B
CCR1 TA1
DVSS
DVCC
TA0.2
GND
VCC
CCI2A
From Capacitive
Touch I/O (internal)
CCI2B
CCR2 TA2
DEVICE OUTPUT
SIGNAL
Timer1_A3 CCI0B input
TA0.1
Timer1_A3 CCI1B input
TA0.2
Timer1_A3 INCLK
Timer1_A3 CCI2B input,
IR Input
DVSS
DVCC
GND
VCC
40
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
PORT PIN
P8.2
P4.0
P8.3
DEVICE INPUT
SIGNAL
TA1CLK
ACLK (internal)
SMCLK (internal)
Timer0_A3 CCR2B output (internal)
Table 6-11. Timer1_A3 Signal Connections
MODULE INPUT
NAME
TACLK
ACLK
SMCLK
MODULE BLOCK
Timer
MODULE OUTPUT
SIGNAL
N/A
INCLK
CCI0A
Timer0_A3 CCR0B output (internal)
DVSS
DVCC
TA1.1
Timer0_A3 CCR1B output (internal)
DVSS
DVCC
TA1.2
Timer0_A3 CCR2B output (internal)
DVSS
DVCC
CCI0B
GND
VCC
CCI1A
CCI1B
GND
VCC
CCI2A
CCI2B
GND
VCC
CCR0
CCR1
CCR2
TA0
TA1
TA2
DEVICE OUTPUT
SIGNAL
TA1.1
To ADC trigger
TA1.2
IR Input
The interconnection of Timer0_A3 and Timer1_A3 can be used to modulate the eUSCI_A pin of
UCA0TXD/UCA0SIMO in either ASK or FSK mode. This configuration helps an application easily acquire a modulated infrared command for directly driving an external IR diode.
The IR functions are controlled by the following bits in the System Configuration 1 (SYSCFG1) register:
IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSEL (data select), and IRDATA
(data). For more information, refer to the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family
User's Guide ( SLAU445 ).
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
41
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
6.9.9
Real-Time Clock (RTC) Counter
The RTC counter is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, and LPM3.5. The RTC can periodically wake up the CPU from LPM0, LPM3, or LPM3.5 based on timing from a low-power clock source such as the XT1 and VLO clocks. In AM, RTC can be driven by SMCLK to generate highfrequency timing events and interrupts. The RTC overflow events trigger:
• Timer0_A3 CCR1B
• ADC conversion trigger when ADCSHSx bits are set as 01b
6.9.10 10-Bit Analog Digital Converter (ADC)
The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The module implements a 10-bit SAR core, sample select control, reference generator and a conversion result buffer. A window comparator with a lower and upper limit allows CPU independent result monitoring with three window comparator interrupt flags.
The ADC supports 10 external inputs and four internal inputs (see
Table 6-12. ADC Channel Connections
ADCSHSx
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ADC CHANNELS
A0/Veref–
A1/Veref+
A2
A3
A4
(1)
A5
A6
A7
A8
A9
Not used
Not used
On-chip temperature sensor
Reference voltage (1.5 V)
DVSS
DVCC
EXTERNAL PIN OUT
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P8.0
(2)
P8.1
(2)
N/A
N/A
N/A
N/A
N/A
N/A
(1) When A4 is used, the PMM 1.2-V reference voltage can be output to this pin by setting the PMM control register. The 1.2-V voltage can be directly measured by A4 channel.
(2) P8.0 and P8.1 are only available in the LQFP-64 package.
The A/D conversion can be started by software or a hardware trigger.
shows the trigger sources that are available.
Table 6-13. ADC Trigger Signal Connections
BINARY
ADCSHSx
DECIMAL
00
01
0
1
10
11
2
3
TRIGGER SOURCE
ADCSC bit (software trigger)
RTC event
TA1.1B
TA1.2B
42
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
6.9.11 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The EEM on these devices has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
43
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
6.9.12 Input/Output Schematics
6.9.12.1 Port P1 Input/Output With Schmitt Trigger
A0..A7
From ADC A
P1REN.x
P1DIR.x
From Module
DVSS
DVCC
0
1
0
1
P1OUT.x
From Module
P1SEL0.x
0
1
EN
D To module
P1IN.x
P1IE.x
P1 Interrupt
P1IFG.x
P1IES.x
From JTAG
To JTAG
Q
D
S
Edge
Select
Bus
Keeper
P1.0/ UCA0TXD/UCA0SIMO /A0
P1.1/ UCA0RXD/UCA0SOMI /A1
P1.2/ UCA0CLK /A2
P1.3/ UCA0STE /A3
P1.4/ MCLK /TCK/A4/VREF+
P1.5/TA0CLK/TMS/A5
P1.6/TA0.2/TDI/TCLK/A6
P1.7/TA0.1/TDO/A7
Figure 6-1. Port P1 Input/Output With Schmitt Trigger www.ti.com
44
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-14. Port P1 Pin Functions
PIN NAME (P1.x)
P1.0/UCA0TXD/UCA0SIMO/A0
P1.1/UCA0RXD/UCA0SOMI/A1
P1.2/UCA0CLK/A2
P1.3/UCA0STE/A3
P1.4/MCLK/TCK/A4/VREF+
P1.5/TA0CLK/TMS/A5
P1.6/TA0.2/TDI/TCLK/A6
P1.7/TA0.1/TDO/A7
x
7 TA0.1
A7
FUNCTION
P1.0 (I/O)
0 UCA0TXD/UCA0SIMO
A0
P1.1 (I/O)
1 UCA0RXD/UCA0SOMI
A1
P1.2 (I/O)
2 UCA0CLK
A2
P1.3 (I/O)
3 UCA0STE
A3
P1.4 (I/O)
VSS
4 MCLK
A4, VREF+
JTAG TCK
P1.5 (I/O)
TA0CLK
5 VSS
A5
JTAG TMS
P1.6 (I/O)
TA0.CCI2A
6 TA0.2
A6
JTAG TDI/TCLK
P1.7 (I/O)
TA0.CCI1A
JTAG TDO
P1DIR.x
I: 0; O: 1
X
X
I: 0; O: 1
X
X
I: 0; O: 1
X
X
I: 0; O: 1
X
X
I: 0; O: 1
0
1
X
X
I: 0; O: 1
0
1
X
X
I: 0; O: 1
0
1
X
X
I: 0; O: 1
0
1
X
X
CONTROL BITS AND SIGNALS
(1)
P1SEL0.x
ADCPCTLx
(2)
0
1
X
0
0
1
X
1
X
X
0
0
1
1
X
X
0
1
X
X
0
1
X
X
0
1
X
X
0
0
1 (x = 0)
0
0
1 (x = 1)
0
0
1 (x = 2)
0
0
1 (x = 3)
0
0
1 (x = 4)
X
0
0
1 (x = 5)
X
0
0
1 (x = 6)
X
0
0
1 (x = 7)
X
JTAG
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Disabled
Disabled
Disabled
TCK
Disabled
Disabled
Disabled
TMS
Disabled
Disabled
Disabled
TDI/TCLK
Disabled
Disabled
Disabled
TDO
(1) X = don't care
(2) Setting the ADCPCTLx bit in SYSCFG2 register disables both the output driver and the input Schmitt trigger to prevent leakage when analog signals are applied.
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
45
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
6.9.12.2 Port P2 Input/Output With Schmitt Trigger
P2REN.x
P2DIR.x
DVSS
DVCC
0
1
www.ti.com
P2OUT.x
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2IN.x
P2IE.x
P2 Interrupt
P2IFG.x
P2IES.x
Bus
Keeper
PIN NAME (P2.x)
Q
D
S
1
1
Edge
Select
Figure 6-2. Port P2 Input/Output With Schmitt Trigger
Table 6-15. Port P2 Pin Functions
FUNCTION x
0 P2.0 (I/O)
1 P2.1 (I/O)
2 P2.2 (I/O)
3 P2.3 (I/O)
4 P2.4 (I/O)
5 P2.5 (I/O)
6 P2.6 (I/O)
7 P2.7 (I/O)
CONTROL BITS AND
SIGNALS
P2DIR.x
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
46
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
6.9.12.3 Port P3 Input/Output With Schmitt Trigger
P3REN.x
P3DIR.x
DVSS
DVCC
0
1
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
P3OUT.x
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P3IN.x
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
PIN NAME (P3.x)
Bus
Keeper
Figure 6-3. Port P3 Input/Output With Schmitt Trigger
Table 6-16. Port P3 Pin Functions x
0 P3.0 (I/O)
1 P3.1 (I/O)
2 P3.2 (I/O)
3 P3.3 (I/O)
4 P3.4 (I/O)
5 P3.5 (I/O)
6 P3.6 (I/O)
7 P3.7 (I/O)
FUNCTION
CONTROL BITS AND
SIGNALS
P3DIR.x
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
47
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
6.9.12.4 Port P4.0 Input/Output With Schmitt Trigger
P4REN.x
P4DIR.x
From Module
0
1
DVSS
DVCC
0
1
www.ti.com
P4OUT.x
From Module
P4SEL0.x
0
1
EN
D To module
P4IN.x
PIN NAME (P4.x)
P4.0/TA1.1
Bus
Keeper
P4.0/TA1.1
Figure 6-4. Port P4.0 Input/Output With Schmitt Trigger
Table 6-17. Port P4.0 Pin Functions x
P4.0 (I/O)
0 TA1.CCI1A
TA1.1
FUNCTION
CONTROL BITS AND SIGNALS
P4DIR.x
P4SEL0.x
0 I: 0; O: 1
0
1
1
48
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
6.9.12.5 Port P4.1 and P4.2 Input/Output With Schmitt Trigger
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
XIN, XOUT
P4REN.x
P4DIR.x
DVSS
DVCC
P4OUT.x
P4SEL0.x
0
1
P4IN.x
Bus
Keeper
PIN NAME (P4.x)
P4.1/XIN
P4.2/XOUT
(1) X = don't care
P4.1/XIN
P4.2/XOUT
Figure 6-5. Port P4.1 and P4.2 Input/Output With Schmitt Trigger x
Table 6-18. Port P4.1 and P4.2 Pin Functions
1
2
P4.1 (I/O)
XIN
P4.2 (I/O)
XOUT
FUNCTION
CONTROL BITS AND SIGNALS
(1)
P4DIR.x
I: 0; O: 1
P4SEL0.x
0
X
I: 0; O: 1
X
1
0
1
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
49
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
6.9.12.6 Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
P4REN.x
P4DIR.x
DVSS
DVCC
0
1
www.ti.com
P4OUT.x
P4.3
P4.4
P4.5
P4.6
P4.7
P4IN.x
Bus
Keeper
P4.3
P4.4
P4.5
P4.6
P4.7
Figure 6-6. Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
Table 6-19. Port P4.3, P4.4, P4.5, P4.6, and P4.7 Pin Functions
PIN NAME (P4.x) x
3 P4.3 (I/O)
4 P4.4 (I/O)
5 P4.5 (I/O)
6 P4.6 (I/O)
7 P4.7 (I/O)
FUNCTION
CONTROL BITS AND
SIGNALS
P4DIR.x
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
50
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
6.9.12.7 Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
P5REN.x
P5DIR.x
From Module
0
1
DVSS
DVCC
0
1
P5OUT.x
From Module
P5SEL0.x
0
1
P5.0/UCB0STE
P5.1/UCB0CLK
P5.2/UCB0SIMO/UCB0SDA
P5.3/UCB0SOMI/UCB0SCL
EN
D To module
P5IN.x
Bus
Keeper
Figure 6-7. Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
PIN NAME (P5.x)
P5.0/UCB0STE
P5.1/UCB0CLK
P5.2/UCB0SIMO/UCB0SDA
P5.3/UCB0SOMI/UCB0SCL
Table 6-20. Port P5.0, P5.1, P5.2, and P5.3 Pin Functions x
0
1
2
3
P5.0 (I/O)
UCB0STE
P5.1 (I/O)
UCB0CLK
P5.2 (I/O)
UCB0SIMO/UCB0SDA
P5.3 (I/O)
UCB0SOMI/UCB0SCL
FUNCTION
CONTROL BITS AND SIGNALS
P5DIR.x
I: 0; O: 1
P5SEL0.x
0
0
I: 0; O: 1
1
0
0
I: 0; O: 1
0
I: 0; O: 1
0
1
0
1
0
1
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
51
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
6.9.12.8 Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
P5REN.x
P5DIR.x
DVSS
DVCC
0
1
P5OUT.x
www.ti.com
P5.4
P5.5
P5.6
P5.7
P5IN.x
Bus
Keeper
P5.4
P5.5
P5.6
P5.7
Figure 6-8. Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
Table 6-21. Port P5.4, P5.5, P5.6, and P5.7 Pin Functions
PIN NAME (P5.x) x
4 P5.4 (I/O)
5 P5.5 (I/O)
6 P5.6 (I/O)
7 P5.7 (I/O)
FUNCTION
CONTROL BITS AND
SIGNALS
P5DIR.x
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
52
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
6.9.12.9 Port P6.0, P6.1, P6.2, and P6.3 Input/Output With Schmitt Trigger
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
P6REN.x
P6DIR.x
DVSS
DVCC
0
1
P6OUT.x
P6.0
P6.1
P6.2
P6.3
P6IN.x
Bus
Keeper
P6.0
P6.1
P6.2
P6.3
Figure 6-9. Port P6.0, P6.1, P6.2, and P6.3 Input/Output With Schmitt Trigger
Table 6-22. Port P6 Pin Functions
PIN NAME (P6.x) x
0 P6.0 (I/O)
1 P6.1 (I/O)
2 P6.2 (I/O)
3 P6.3 (I/O)
FUNCTION
CONTROL BITS AND
SIGNALS
P6DIR.x
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
53
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
6.9.12.10 Port P6.4, P6.5, P6.6, and P6.7 Input/Output With Schmitt Trigger
P6REN.x
P6DIR.x
DVSS
DVCC
0
1
P6OUT.x
www.ti.com
P6.4
P6.5
P6.6
P6.7
P6IN.x
Bus
Keeper
P6.4
P6.5
P6.6
P6.7
Figure 6-10. Port P6.4, P6.5, P6.6, and P6.7 Input/Output With Schmitt Trigger
Table 6-23. Port P6.4, P6.5, P6.6, and P6.7 Pin Functions
PIN NAME (P6.x) x
4 P6.4 (I/O)
5 P6.5 (I/O)
6 P6.6 (I/O)
7 P6.7 (I/O)
FUNCTION
CONTROL BITS AND
SIGNALS
P6DIR.x
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
54
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
6.9.12.11 Port P7.0, P7.1, P7.2, and P7.3 Input/Output With Schmitt Trigger
P7REN.x
P7DIR.x
DVSS
DVCC
0
1
P7OUT.x
P7.0
P7.1
P7.2
P7.3
P7IN.x
Bus
Keeper
P7.0
P7.1
P7.2
P7.3
Figure 6-11. Port P7.0, P7.1, P7.2, and P7.3 Input/Output With Schmitt Trigger
Table 6-24. Port P7.0, P7.1, P7.2, and P7.3 Pin Functions
PIN NAME (P7.x) x
0 P7.0 (I/O)
1 P7.1 (I/O)
2 P7.2 (I/O)
3 P7.3 (I/O)
FUNCTION
CONTROL BITS AND
SIGNALS
P7DIR.x
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
55
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
6.9.12.12 Port P7.4, P7.5, P7.6, and P7.7 Input/Output With Schmitt Trigger
P7REN.x
P7DIR.x
DVSS
DVCC
0
1
www.ti.com
P7OUT.x
P7.4
P7.5
P7.6
P7.7
P7IN.x
Bus
Keeper
P7.4
P7.5
P7.6
P7.7
Figure 6-12. Port P7.4, P7.5, P7.6, and P7.7 Input/Output With Schmitt Trigger
Table 6-25. Port P7.4, P7.5, P7.6, and P7.7 Pin Functions
PIN NAME (P7.x) x
4 P7.4 (I/O)
5 P7.5 (I/O)
6 P7.6 (I/O)
7 P7.7 (I/O)
FUNCTION
CONTROL BITS AND
SIGNALS
P7DIR.x
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
I: 0; O: 1
56
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
6.9.12.13 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
A8..9
From ADC A
P8REN.x
P8DIR.x
From Module
DVSS
DVCC
0
1
0
1
P8OUT.x
From MCLK, ACLK
P8SEL0.x
0
1
EN
D To module
P8IN.x
Bus
Keeper
P8.0/SMCLK/A8
P8.1/ACLK/A9
Figure 6-13. Port P8.0 and P8.1 Input/Output With Schmitt Trigger
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
57
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
Table 6-26. Port P8.0 and P8.1 Pin Functions
PIN NAME (P8.x)
P8.0/SMCLK/A8
P8.1/ACLK/A9
x
0
1
P8.0 (I/O)
VSS
SMCLK
A8
P8.1 (I/O)
VSS
ACLK
A9
FUNCTION
CONTROL BITS AND SIGNALS
(1)
P8DIR.x
P8SEL0.x
ADCPCTLx
(2)
I: 0; O: 1
0
0 0
1 0
1
X
I: 0; O: 1
0
X
0
1 (x = 8)
0
1 0
1
X X 1 (x = 9)
(1) X = don't care
(2) Setting the ADCPCTLx bit in SYSCFG2 register disables both the output driver and the input Schmitt trigger to prevent leakage when analog signals are applied.
58
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
6.9.12.14 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
P8REN.x
P8DIR.x
From Module
0
1
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
DVSS
DVCC
0
1
P8OUT.x
From Module
P8SEL0.x
0
1
EN
D To module
P8IN.x
Bus
Keeper
PIN NAME (P8.x)
P8.2/TA1CLK
P8.3/TA1.2
P8.2/TA1CLK
P8.3/TA1.2
Figure 6-14. Port P8.2 and P8.3 Input/Output With Schmitt Trigger x
Table 6-27. Port P8.2 and P8.3 Pin Functions
P8.2 (I/O)
2 TA1 CLK
VSS
P8.3 (I/O)
3 TA1.CCI2A
TA1.2
FUNCTION
CONTROL BITS AND SIGNALS
P8DIR.x
P8SEL0.x
I: 0; O: 1
0
0
1
1
0 I: 0; O: 1
0
1
1
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
59
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
6.10 Device Descriptors (TLV)
lists the Device IDs of the MSP430FR203x device variants.
lists the contents of the device descriptor tag-length-value (TLV) structure for MSP430FR203x devices.
Information Block
Die Record
ADC Calibration
DEVICE
MSP430FR2033
MSP430FR2032
Table 6-28. Device IDs
DEVICE ID
1A04h
75h
78h
1A05h
82h
82h
Info length
CRC length
CRC value
(1)
Device ID
Hardware revision
Firmware revision
Die Record Tag
Die Record length
Lot Wafer ID
Die X position
Die Y position
Test Result
ADC Calibration Tag
ADC Calibration Length
ADC Gain Factor
ADC Offset
Table 6-29. Device Descriptors
DESCRIPTION
ADC 1.5-V Reference Temperature 30°C
ADC 1.5-V Reference Temperature 85°C
1A11h
1A12h
1A13h
1A14h
1A15h
1A16h
1A17h
1A18h
1A19h
1A1Ah
1A1Bh
1A1Ch
1A1Dh
ADDRESS
MSP430FR203x
VALUE
1A00h
1A01h
06h
06h
1A02h
1A03h
1A04h
1A05h
1A06h
See per unit per unit
1A07h
1A08h
1A09h
1A0Ah
1A0Bh per unit per unit
08h
0Ah
1A0Ch
1A0Dh
1A0Eh
1A0Fh
1A10h per unit per unit per unit per unit per unit per unit per unit per unit per unit per unit
11h
08h per unit per unit per unit per unit per unit per unit per unit per unit
(1) The CRC value covers the checksum from 1A04h to 1A77h by applying the CRC-CCITT-16 polynomial of x
16
+ x
12
+ x
5
+ 1.
60
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-29. Device Descriptors (continued)
Reference and DCO Calibration
Calibration Tag
Calibration Length
DCO Tap Settings for 16 MHz, Temperature
30°C
(2)
DESCRIPTION
1.5-V Reference Factor
ADDRESS
MSP430FR203x
VALUE
1A1Eh
1A1Fh
1A20h
12h
04h per unit
1A21h
1A22h
1A23h per unit per unit perunit
(2) This value can be directly loaded into DCO bits in CSCTL0 register to get accurate 16-MHz frequency at room temperature, especially when MCU exits from LPM3 and below. TI suggests using a predivider to decrease the frequency, if the temperature drift might result an overshoot beyond 16 MHz.
6.11 Memory
shows the memory organization of the MSP430FR203x devices.
Table 6-30. Memory Organization
Memory (FRAM)
Main: interrupt vectors and signatures
Main: code memory
RAM
Information Memory (FRAM)
Bootstrap loader (BSL) Memory (ROM)
Peripherals
Access
Read/Write
(Optional Write Protect)
Read/Write
Read/Write
(Optional Write Protect)
Read only
Read/Write
(1)
(2)
MSP430FR2033
15KB
FFFFh-FF80h
FFFFh-C400h
2KB
27FFh-2000h
512B
19FFh-1800h
1KB
13FFh-1000h
4KB
0FFFh-0000h
MSP430FR2032
8KB
FFFFh-FF80h
FFFFh-E000h
1KB
23FFh-2000h
512B
19FFh-1800h
1KB
13FFh-1000h
4KB
0FFFh-0000h
(1) The Program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. Refer to the SYS chapter in the MSP430FR4xx
and MSP430FR2xx Family User's Guide ( SLAU445 ) for more details
(2) The Information FRAM can be write protected by setting DFWP bit in SYSCFG0 register. Refer to the SYS chapter in the
MSP430FR4xx and MSP430FR2xx Family User's Guide ( SLAU445 ) for more details
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
61
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
6.11.1 Peripheral File Map
shows the base address and the memory size of the register region for each peripheral, and
through
show all of the available registers for each peripheral and their address offsets.
MODULE NAME
Special Functions (See
PMM (See
SYS (See
CS (See
)
FRAM (See
CRC (See
WDT (See
Port P1, P2 (See
)
Port P3, P4 (See
)
Port P5, P6 (See
)
Port P7, P8 (See
)
Capacitive Touch I/O (See
)
Timer0_A3 (See
)
Timer1_A3 (See
)
RTC (See
) eUSCI_A0 (See
) eUSCI_B0 (See
)
Backup Memory (See
ADC (See
Table 6-31. Peripherals Summary
BASE ADDRESS
0100h
0120h
0140h
0180h
01A0h
01C0h
01CCh
0200h
0220h
0240h
0260h
02E0h
0300h
0340h
03C0h
0500h
0540h
0660h
0700h
0020h
0020h
0010h
0030h
0030h
0010h
0020h
0030h
0020h
0040h
SIZE
0010h
0020h
0030h
0020h
0010h
0008h
0002h
0020h
0020h
62
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-32. Special Function Registers (Base Address: 0100h)
SFR interrupt enable
REGISTER DESCRIPTION
SFR interrupt flag
SFR reset pin control
REGISTER
SFRIE1
SFRIFG1
SFRRPCR
Table 6-33. PMM Registers (Base Address: 0120h)
PMM Control 0
PMM Control 1
PMM Control 2
PMM interrupt flags
PM5 Control 0
REGISTER DESCRIPTION REGISTER
PMMCTL0
PMMCTL1
PMMCTL2
PMMIFG
PM5CTL0
Table 6-34. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTION
System control
Bootstrap loader configuration area
JTAG mailbox control
JTAG mailbox input 0
JTAG mailbox input 1
JTAG mailbox output 0
JTAG mailbox output 1
Bus Error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
System configuration 0
System configuration 1
System configuration 2
REGISTER
SYSCTL
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
SYSSNIV
SYSRSTIV
SYSCFG0
SYSCFG1
SYSCFG2
Table 6-35. CS Registers (Base Address: 0180h)
CS control register 0
CS control register 1
CS control register 2
CS control register 3
CS control register 4
CS control register 5
CS control register 6
CS control register 7
CS control register 8
REGISTER DESCRIPTION REGISTER
CSCTL0
CSCTL1
CSCTL2
CSCTL3
CSCTL4
CSCTL5
CSCTL6
CSCTL7
CSCTL8
FRAM control 0
General control 0
General control 1
Table 6-36. FRAM Registers (Base Address: 01A0h)
REGISTER DESCRIPTION REGISTER
FRCTL0
GCCTL0
GCCTL1
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
OFFSET
00h
02h
04h
OFFSET
00h
02h
04h
0Ah
10h
OFFSET
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
OFFSET
00h
04h
06h
Detailed Description
OFFSET
00h
02h
06h
08h
0Ah
0Ch
0Eh
18h
1Ah
1Ch
1Eh
20h
22h
24h
63
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-37. CRC Registers (Base Address: 01C0h)
REGISTER DESCRIPTION
CRC data input
CRC data input reverse byte
CRC initialization and result
CRC result reverse byte
REGISTER
CRC16DI
CRCDIRB
CRCINIRES
CRCRESR
Table 6-38. WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
WDTCTL
OFFSET
00h
02h
04h
06h
OFFSET
00h
Table 6-39. Port P1, P2 Registers (Base Address: 0200h)
Port P1 input
Port P1 output
REGISTER DESCRIPTION
Port P1 direction
Port P1 pulling register enable
Port P1 selection 0
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
Port P2 output
Port P2 direction
Port P2 pulling register enable
Port P2 selection 0
(1)
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
REGISTER
P1IN
P1OUT
P1DIR
P1REN
P1SEL0
P1IV
P1IES
P1IE
P1IFG
P2IN
P2OUT
P2DIR
P2REN
P2SEL0
P2IV
P2IES
P2IE
P2IFG
OFFSET
00h
02h
04h
06h
0Ah
0Eh
18h
1Ah
1Ch
01h
03h
05h
07h
0Bh
1Eh
19h
1Bh
1Dh
(1) Port P2 selection register does not feature any valid bits. P2SEL0 presents for 16-bit Port A operation with P1SEL0.
Table 6-40. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
Port P3 input
Port P3 output
Port P3 direction
Port P3 pulling register enable
Port P3 selection 0
(1)
Port P4 input
Port P4 output
Port P4 direction
Port P4 pulling register enable
Port P4 selection 0
REGISTER
P3IN
P3OUT
P3DIR
P3REN
P3SEL0
P4IN
P4OUT
P4DIR
P4REN
P4SEL0
(1) Port P3 selection register does not feature any valid bits. P3SEL0 presents for 16-bit Port B operation with P4SEL0.
OFFSET
00h
02h
04h
06h
0Ah
01h
03h
05h
07h
0Bh
www.ti.com
64
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-41. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
Port P5 input
Port P5 output
Port P5 direction
Port P5 pulling register enable
Port P5 selection 0
Port P6 input
Port P6 output
Port P6 direction
Port P6 pulling register enable
Port P6 selection 0
(1)
REGISTER
P5IN
P5OUT
P5DIR
P5REN
P5SEL0
P6IN
P6OUT
P6DIR
P6REN
P6SEL0
(1) Port P6 selection register does not feature any valid bits. P6SEL0 presents for 16-bit Port C operation with P5SEL0.
OFFSET
00h
02h
04h
06h
0Ah
01h
03h
05h
07h
0Bh
Table 6-42. Port P7, P8 Registers (Base Address: 0260h)
Port P7 input
Port P7 output
REGISTER DESCRIPTION
Port P7 direction
Port P7 pulling register enable
Port P7 selection 0
(1)
Port P8 input
Port P8 output
Port P8 direction
Port P8 pulling register enable
Port P8 selection 0
REGISTER
P7IN
P7OUT
P7DIR
P7REN
P7SEL0
P8IN
P8OUT
P8DIR
P8REN
P8SEL0
OFFSET
00h
02h
04h
06h
0Ah
01h
03h
05h
07h
0Bh
(1) Port P7 selection register does not feature any valid bits. P7SEL0 presents for 16-bit Port D operation with P8SEL0.
Table 6-43. Capacitive Touch I/O Registers (Base Address: 02E0h)
REGISTER DESCRIPTION
Capacitive Touch I/O 0 control
REGISTER
CAPTIO0CTL
OFFSET
0Eh
Table 6-44. Timer0_A3 Registers (Base Address: 0300h)
REGISTER DESCRIPTION
TA0 control
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA0 counter register
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TA0 expansion register 0
TA0 interrupt vector
REGISTER
TA0CTL
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0R
TA0CCR0
TA0CCR1
TA0CCR2
TA0EX0
TA0IV
OFFSET
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
65
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-45. Timer1_A3 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
TA1 control
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter register
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TA1 expansion register 0
TA1 interrupt vector
REGISTER
TA1CTL
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
TA1IV
Table 6-46. RTC Registers (Base Address: 03C0h)
RTC control
RTC interrupt vector
RTC modulo
RTC counter
REGISTER DESCRIPTION REGISTER
RTCCTL
RTCIV
RTCMOD
RTCCNT
Table 6-47. eUSCI_A0 Registers (Base Address: 0500h)
REGISTER DESCRIPTION
eUSCI_A control word 0 eUSCI_A control word 1 eUSCI_A control rate 0 eUSCI_A control rate 1 eUSCI_A modulation control eUSCI_A status eUSCI_A receive buffer eUSCI_A transmit buffer eUSCI_A LIN control eUSCI_A IrDA transmit control eUSCI_A IrDA receive control eUSCI_A interrupt enable eUSCI_A interrupt flags eUSCI_A interrupt vector word
REGISTER
UCA0CTLW0
UCA0CTLW1
UCA0BR0
UCA0BR1
UCA0MCTLW
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL lUCA0IRTCTL
IUCA0IRRCTL
UCA0IE
UCA0IFG
UCA0IV
Table 6-48. eUSCI_B0 Registers (Base Address: 0540h)
REGISTER DESCRIPTION
eUSCI_B control word 0 eUSCI_B control word 1 eUSCI_B bit rate 0 eUSCI_B bit rate 1 eUSCI_B status word eUSCI_B byte counter threshold eUSCI_B receive buffer eUSCI_B transmit buffer eUSCI_B I2C own address 0
REGISTER
UCB0CTLW0
UCB0CTLW1
UCB0BR0
UCB0BR1
UCB0STATW
UCB0TBCNT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA0
66
Detailed Description
OFFSET
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
14h
OFFSET
00h
02h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ah
1Ch
1Eh
OFFSET
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
OFFSET
00h
04h
08h
0Ch
www.ti.com
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-48. eUSCI_B0 Registers (Base Address: 0540h) (continued)
REGISTER DESCRIPTION
eUSCI_B I2C own address 1 eUSCI_B I2C own address 2 eUSCI_B I2C own address 3 eUSCI_B receive address eUSCI_B address mask eUSCI_B I2C slave address eUSCI_B interrupt enable eUSCI_B interrupt flags eUSCI_B interrupt vector word
REGISTER
UCB0I2COA1
UCB0I2COA2
UCB0I2COA3
UCB0ADDRX
UCB0ADDMASK
UCB0I2CSA
UCB0IE
UCB0IFG
UCB0IV
OFFSET
16h
18h
1Ah
1Ch
1Eh
20h
2Ah
2Ch
2Eh
Backup Memory 0
Backup Memory 1
Backup Memory 2
Backup Memory 3
Backup Memory 4
Backup Memory 5
Backup Memory 6
Backup Memory 7
Backup Memory 8
Backup Memory 9
Backup Memory 10
Backup Memory 11
Backup Memory 12
Backup Memory 13
Backup Memory 14
Backup Memory 15
Table 6-49. Backup Memory Registers (Base Address: 0660h)
REGISTER DESCRIPTION REGISTER
BAKMEM0
BAKMEM1
BAKMEM2
BAKMEM3
BAKMEM4
BAKMEM5
BAKMEM6
BAKMEM7
BAKMEM8
BAKMEM9
BAKMEM10
BAKMEM11
BAKMEM12
BAKMEM13
BAKMEM14
BAKMEM15
Table 6-50. ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTION
ADC control register 0
ADC control register 1
ADC control register 2
ADC window comparator low threshold
ADC window comparator high threshold
ADC memory control register 0
ADC conversion memory register
ADC interrupt enable
ADC interrupt flags
ADC interrupt vector word
REGISTER
ADCCTL0
ADCCTL1
ADCCTL2
ADCLO
ADCHI
ADCMCTL0
ADCMEM0
ADCIE
ADCIFG
ADCIV
OFFSET
00h
02h
04h
06h
08h
0Ah
12h
1Ah
1Ch
1Eh
OFFSET
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
Detailed Description
67
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
6.12 Identification
6.12.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The device-specific errata sheet describes these markings. For links to the errata sheets for the devices in this data sheet, see
.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For details on this value, see the "Hardware Revision" entries in
6.12.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific errata sheet describes these markings. For links to the errata sheets for the devices in this data sheet, see
.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For details on this value, see the "Device ID" entries in
.
6.12.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in detail in the MSP430 Programming Via the JTAG Interface User's Guide ( SLAU320 ).
68
Detailed Description
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
7 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
7.1
Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430FR413x devices.
These guidelines are to make sure that the device has proper connections for powering, programming, debugging, and optimum analog performance.
7.1.1
Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling capacitor to the DVCC and DVSS pins. Higher-value capacitors may be used but can impact supply rail ramp-up time. Decoupling capacitors must be placed as close as possible to the pins that they decouple
(within a few millimeters).
DVCC
Power Supply
Decoupling
+
DVSS
100 nF
Figure 7-1. Power Supply Decoupling
7.1.2
External Oscillator
This device supports only a low-frequency crystal (32 kHz) on the XIN and XOUT pins. External bypass capacitors for the crystal oscillator pins are required.
It is also possible to apply digital clock signals to the XIN input pin that meet the specifications of the respective oscillator if the appropriate XT1BYPASS mode is selected. In this case, the associated XOUT pin can be used for other purposes. If they are left unused, they must be terminated according to
.
shows a typical connection diagram.
XIN
XOUT
C
L1
C
L2
Figure 7-2. Typical Crystal Connection
See the application report MSP430 32-kHz Crystal Oscillators ( SLAA322 ) for more information on selecting, testing, and designing a crystal oscillator with the MSP430 devices.
Copyright © 2014–2015, Texas Instruments Incorporated
Applications, Implementation, and Layout
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
69
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
7.1.3
JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the connections also support the MSP-GANG production programmers, thus providing an easy way to program prototype boards, if desired.
shows the connections between the 14-pin JTAG connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication.
shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-
FET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an alternate connection (pin 4 instead of pin 2). The VCC-sense feature senses the local VCC present on the target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
and
show a jumper block that supports both scenarios of supplying VCC to the target board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the jumper block. Pins 2 and 4 must not be connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s
Guide ( SLAU278 ).
Important to connect
V
CC
MSP430FRxxx
J1 (see Note A)
J2 (see Note A)
DVCC
R1
47 kW
VCC TOOL
VCC TARGET
TEST
8
10
12
14
2
4
6
JTAG
11
13
7
9
1
3
5
TDO/TDI
TDI
TMS
TCK
GND
RST
RST/NMI/SBWTDIO
TDO/TDI
TDI
TMS
TCK
C1
1 nF
(see Note B)
TEST/SBWTCK
DVSS
A.
If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection J2.
B.
The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-3. Signal Connections for 4-Wire JTAG Communication
70
Applications, Implementation, and Layout
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
Important to connect
J1 (see Note A)
J2 (see Note A)
R1
47 kΩ
(see Note B)
VCC TOOL
VCC TARGET
2
4
6
8
10
12
14
JTAG
1
11
13
7
9
3
5
TDO/TDI
TCK
GND
V
CC
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
DVCC
MSP430FRxxx
RST/NMI/SBWTDIO
C1
1 nF
(see Note B)
TEST/SBWTCK
DVSS
A.
Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or programming adapter.
B.
The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with the device. The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4
Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an external 47-k
Ω pullup resistor to the RST/NMI pin with a 1.1-nF pulldown capacitor. The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.
See the device family user’s guide ( SLAU367 ) for more information on the referenced control registers and bits.
7.1.5
Unused Pins
For details on the connection of unused pins, see
.
Copyright © 2014–2015, Texas Instruments Incorporated
Applications, Implementation, and Layout
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
71
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
7.1.6
General Layout Recommendations
• Proper grounding and short traces for external crystal to reduce parasitic capacitance. See the application report MSP430 32-kHz Crystal Oscillators ( SLAA322 ) for recommended layout guidelines.
• Proper bypass capacitors on DVCC and reference pins, if used.
• Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital switching signals such as PWM or JTAG signals away from the oscillator circuit.
• Refer to the Circuit Board Layout Techniques design guide ( SLOA089 ) for a detailed discussion of
PCB layout considerations. This document is written primarily about op amps, but the guidelines are generally applicable for all mixed-signal applications.
• Proper ESD level protection should be considered to protect the device from unintended high-voltage electrostatic discharge. See the application report MSP430 System-Level ESD Considerations
( SLAA530 ) for guidelines.
7.1.7
Do's and Don'ts
During power up, power down, and device operation, DVCC must not exceed the limits specified in
, Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
7.2
Peripheral- and Interface-Specific Design Information
7.2.1
ADC Peripheral
7.2.1.1
Partial Schematic
DVSS
VREF+/VEREF+
Using an
External
Positive
Reference
+
100 nF
+
VEREF-
Using an
External
Negative
Reference
100 nF
Figure 7-5. ADC Grounding and Noise Considerations
7.2.1.2
Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the ADC. The general guidelines in
combined with the connections shown in
prevent this.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free design using separate analog and digital ground planes with a single-point connection to achieve high accuracy.
72
Applications, Implementation, and Layout
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
shows the recommended decoupling circuit when an external voltage reference is used. The internal reference module has a maximum drive current as described in the sections ADC Pin Enable and
1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide ( SLAU445 ).
The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage enters the device. In this case, the 10μF capacitor is used to buffer the reference pin and filter any lowfrequency ripple. A bypass capacitor of 100 nF is used to filter out any high-frequency noise.
7.2.1.3
Layout Guidelines
Components that are shown in the partial schematic (see
) should be placed as close as possible to the respective device pins to avoid long traces, because they add additional parasitic capacitance, inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM), because the high-frequency switching can be coupled into the analog signal.
Copyright © 2014–2015, Texas Instruments Incorporated
Applications, Implementation, and Layout
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
73
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
8 Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.1.1.1
Getting Started and Next Steps
For an introduction to the MSP430 family of devices and the tools and libraries that are available to help with your development, visit the Getting Started page .
8.1.1.2
Development Tools Support
8.1.1.2.1 Hardware Features
See the Code Composer Studio for MSP430 User's Guide ( SLAU157 ) for details on the available features.
MSP430
ARCHITECTURE
MSP430Xv2
4-WIRE
JTAG
Yes
2-WIRE
JTAG
Yes
BREAK-
POINTS
(N)
3
RANGE
BREAK-
POINTS
Yes
CLOCK STATE TRACE
CONTROL SEQUENCER BUFFER
Yes No No
LPMX.5
DEBUGGING
SUPPORT
No
8.1.1.2.2 Recommended Hardware Options
All MSP430™ microcontrollers are supported by a wide variety of software and hardware development tools. Tools are available from TI and various third parties. See them all at www.ti.com/msp430tools .
8.1.1.2.2.1 Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the
JTAG programmer and debugger included. The following table shows the compatible target boards and the supported packages.
PACKAGE
64-pin LQFP (PM)
TARGET BOARD AND PROGRAMMER BUNDLE
MSP-FET430U64D
TARGET BOARD ONLY
MSP-TS430PM64D
8.1.1.2.2.2 Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP430 devices. These kits feature additional hardware components and connectivity for full system evaluation and prototyping. See www.ti.com/msp430tools for details.
8.1.1.2.2.3 Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third party suppliers. See the full list of available tools at www.ti.com/msp430tools .
8.1.1.2.2.4 Production Programmers
The production programmers expedite loading firmware to devices by programming several devices simultaneously.
PART NUMBER PC PORT PROVIDER
MSP-GANG Serial and USB
FEATURES
Program up to eight devices at a time. Works with PC or as a stand-alone device.
Texas Instruments
74
Device and Documentation Support
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
8.1.1.2.3 Recommended Software Options
8.1.1.2.3.1 Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also available.
This device is supported by Code Composer Studio™ IDE (CCS).
8.1.1.2.3.2 MSP430Ware
MSP430Ware is a collection of code examples, data sheets, and other design resources for all MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSP430Ware also includes a high-level API called MSP430 Driver Library.
This library makes it easy to program MSP430 hardware. MSP430Ware is available as a component of
CCS or as a stand-alone package.
8.1.1.2.3.3 Command-Line Programmer
MSP430 Flasher is an open-source, shell-based interface for programming MSP430 microcontrollers through a FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP430 Flasher can be used to download binary files (.txt or .hex) files directly to the MSP430 microcontroller without the need for an IDE.
8.1.2
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of three prefixes: MSP, PMS, or XMS (for example, MSP430FR2033). TI recommends two of three possible prefix designators for its support tools: MSP and MSPX. These prefixes represent evolutionary stages of product development from engineering prototypes (with XMS for devices and MSPX for tools) through fully qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the electrical specifications of the final device
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed TI internal qualification testing.
MSP – Fully qualified development-support product
XMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PM) and temperature range (for example, T).
provides a legend for reading the complete device name for any family member.
Copyright © 2014–2015, Texas Instruments Incorporated
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
75
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
MSP
430 FR
4
133
I
PM T
Processor Family
430 MCU Platform
Device Type
Series
Feature Set
Optional: Tape and Reel
Packaging
Optional: Temperature Range
www.ti.com
Processor Family
430 MCU Platform
Device Type
Series
Feature Set
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
TI’s 16-Bit Low-Power Microcontroller Platform
Memory Type
FR = FRAM
FRAM 4 Series = Up to 16 MHz with LCD
FRAM 2 Series = Up to 16 MHz without LCD
st nd
1 and 2 Digit – ADC Channels / 16-bit Timers / I/Os
13 = Up to 10 / 3 / Up to 60
rd
3 Digit – FRAM (KB) / SRAM (KB)
3 = 16 / 2
2 = 8 / 1
1 = 4 / 0.5
Optional: Temperature Range
Packaging
Optional: Distribution Format
8.2
Documentation Support
The following documents describe the MSP430FR203x microcontrollers. Copies of these documents are available on the Internet at www.ti.com
.
SLAU445
MSP430FR4xx and MSP430FR2xx Family User's Guide. Detailed description of all modules and peripherals available in this device family.
SLAZ625
MSP430FR2033 Device Erratasheet. Describes the known exceptions to the functional specifications for all silicon revisions of this device.
SLAZ626
MSP430FR2032 Device Erratasheet. Describes the known exceptions to the functional specifications for all silicon revisions of this device.
8.2.1
Related Links
lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.
PARTS
MSP430FR2033
MSP430FR2032
I
C = 0°C to 70°C
– ° °
° http://www.ti.com/packaging
T = Small reel
R = Large reel
No Marking = Tube or Tray
Figure 8-1. Device Nomenclature
PRODUCT FOLDER
Click here
Click here
Table 8-1. Related Links
SAMPLE & BUY
Click here
Click here
TECHNICAL
DOCUMENTS
Click here
Click here
TOOLS &
SOFTWARE
Click here
Click here
SUPPORT &
COMMUNITY
Click here
Click here
76
Device and Documentation Support
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
www.ti.com
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
8.2.2
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use .
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.
8.3
Trademarks
MSP430, Code Composer Studio, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.5
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 2014–2015, Texas Instruments Incorporated
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
77
MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
9 Mechanical Packaging and Orderable Information
9.1
Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
78
Mechanical Packaging and Orderable Information
Copyright © 2014–2015, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
MSP430FR2033 MSP430FR2032
PACKAGE OPTION ADDENDUM
www.ti.com
10-Sep-2015
PACKAGING INFORMATION
Orderable Device
MSP430FR2032IG48
MSP430FR2032IG48R
MSP430FR2032IG56
MSP430FR2032IG56R
MSP430FR2032IPM
MSP430FR2032IPMR
MSP430FR2033IG48
MSP430FR2033IG48R
MSP430FR2033IG56
MSP430FR2033IG56R
Status
(1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Type Package
Drawing
TSSOP
TSSOP
DGG
DGG
Pins Package
48
48
Qty
Eco Plan
(2)
40 Green (RoHS
& no Sb/Br)
2000 Green (RoHS
& no Sb/Br)
TSSOP DGG 56
TSSOP
LQFP
LQFP
DGG
PM
PM
56
64
64
35 Green (RoHS
& no Sb/Br)
2000 Green (RoHS
& no Sb/Br)
160 Green (RoHS
& no Sb/Br)
1000 Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
DGG
48
48
56
56
40 Green (RoHS
& no Sb/Br)
2000 Green (RoHS
& no Sb/Br)
35 Green (RoHS
& no Sb/Br)
2000 Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
MSL Peak Temp
(3)
Level-3-260C-168 HR
Op Temp (°C)
-40 to 85
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
(4/5)
FR2032
FR2032
FR2032
FR2032
FR2032
FR2032
FR2033
FR2033
FR2033
FR2033
MSP430FR2033IPM ACTIVE LQFP PM 64 160 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR -40 to 85 FR2033
MSP430FR2033IPMR ACTIVE LQFP PM 64 1000 Green (RoHS
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
CU NIPDAU Level-3-260C-168 HR
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
-40 to 85 FR2033
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Sep-2015
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
www.ti.com
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
18-Jun-2015
*All dimensions are nominal
Device
MSP430FR2032IG48R
MSP430FR2032IPMR
MSP430FR2033IPMR
Package
Type
Package
Drawing
TSSOP
LQFP
LQFP
DGG
MSP430FR2032IG56R TSSOP DGG
PM
MSP430FR2033IG48R TSSOP DGG
MSP430FR2033IG56R TSSOP DGG
PM
Pins
48
56
64
48
56
64
SPQ
2000
2000
1000
2000
2000
1000
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
24.4
330.0
330.0
24.4
24.4
A0
(mm)
8.6
B0
(mm)
15.8
8.6
15.6
13.0
13.0
330.0
330.0
330.0
24.4
24.4
24.4
8.6
8.6
13.0
15.8
15.6
13.0
K0
(mm)
P1
(mm)
1.8
2.1
12.0
16.0
W
(mm)
Pin1
Quadrant
24.0
1.8
12.0
24.0
2.1
16.0
24.0
1.8
12.0
24.0
1.8
12.0
24.0
24.0
Q1
Q1
Q2
Q1
Q1
Q2
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
18-Jun-2015
*All dimensions are nominal
Device
MSP430FR2032IG48R
MSP430FR2032IG56R
MSP430FR2032IPMR
MSP430FR2033IG48R
MSP430FR2033IG56R
MSP430FR2033IPMR
Package Type Package Drawing Pins
TSSOP
TSSOP
LQFP
TSSOP
TSSOP
LQFP
DGG
DGG
PM
DGG
DGG
PM
48
56
64
48
56
64
SPQ
2000
2000
1000
2000
2000
1000
Length (mm) Width (mm) Height (mm)
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
45.0
45.0
45.0
45.0
45.0
45.0
Pack Materials-Page 2
DGG0056A
A
1
SCALE 1.200
8.3
7.9
TYP
PIN 1 ID
AREA
56
54X 0.5
PACKAGE OUTLINE
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SEATING PLANE
C
0.1 C
14.1
13.9
NOTE 3
2X
13.5
28
B
29
6.2
6.0
1.2 MAX
0.08
C A B
(0.15) TYP
0.25
GAGE PLANE
SEE DETAIL A
0 - 8
0.75
0.50
DETAIL A
TYPICAL
0.15
0.05
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
www.ti.com
DGG0056A
56X (1.5)
1
56X (0.3)
54X (0.5)
(R 0.05
TYP
)
SYMM
EXAMPLE BOARD LAYOUT
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56
SYMM
28
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
29
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
0.05 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
4222167/A 07/2015 www.ti.com
DGG0056A
EXAMPLE STENCIL DESIGN
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
1
56X (0.3)
54X (0.5)
(R 0.05
) TYP
SYMM
56
SYMM
28
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
29
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PM (S-PQFP-G64)
0,50
48
49
0,27
0,17
33
0,08
M
32
MECHANICAL DATA
MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996
PLASTIC QUAD FLATPACK
64
17
0,13 NOM
1 16
7,50 TYP
10,20
SQ
9,80
12,20
11,80
SQ
0,05 MIN
0,25
1,45
1,35
Seating Plane
0,08 1,60 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
D. May also be thermally enhanced plastic with leads connected to the die pads.
0,75
0,45
Gage Plane
0
°
– 7
°
4040152 / C 11/96
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
PLASTIC SMALL-OUTLINE PACKAGE DGG (R-PDSO-G**)
48 PINS SHOWN
48
0,50
0,27
0,17
25
0,08
M
1
A
24
6,20 8,30
6,00 7,90
0,15 NOM
Gage Plane
0
°
– 8
°
0,25
0,75
0,50
1,20 MAX
0,15
0,05
Seating Plane
0,10
DIM
PINS **
A MAX
48
12,60
56 64
14,10 17,10
A MIN 12,40 13,90 16,90
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
4040078 / F 12/97
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Audio
Amplifiers
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
OMAP Applications Processors
Wireless Connectivity www.ti.com/audio amplifier.ti.com
dataconverter.ti.com
www.dlp.com
dsp.ti.com
www.ti.com/clocks interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
Applications
Automotive and Transportation
Communications and Telecom
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
Medical
Security
Space, Avionics and Defense
Video and Imaging www.ti-rfid.com
www.ti.com/omap
TI E2E Community
www.ti.com/wirelessconnectivity www.ti.com/automotive www.ti.com/communications www.ti.com/computers www.ti.com/consumer-apps www.ti.com/energy www.ti.com/industrial www.ti.com/medical www.ti.com/security www.ti.com/space-avionics-defense www.ti.com/video e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
advertisement
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Related manuals
advertisement
Table of contents
- 1 1 Device Overview
- 1 1.1 Features
- 1 1.2 Applications
- 2 1.3 Description
- 3 1.4 Functional Block Diagram
- 4 Table of Contents
- 4 2 Revision History
- 5 3 Device Comparison
- 6 4 Terminal Configuration and Functions
- 6 4.1 Pin Diagrams
- 9 4.2 Signal Descriptions
- 12 4.3 Pin Multiplexing
- 12 4.4 Connection of Unused Pins
- 13 5 Specifications
- 13 5.1 Absolute Maximum Ratings
- 13 5.2 ESD Ratings
- 13 5.3 Recommended Operating Conditions
- 14 5.4 Active Mode Supply Current Into VCC Excluding External Current
- 14 5.5 Active Mode Supply Current Per MHz
- 14 5.6 Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
- 15 5.7 Low-Power Mode LPM3, LPM4 Supply Currents (Into VCC) Excluding External Current
- 15 5.8 Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
- 16 5.9 Typical Characteristics, Low-Power Mode Supply Currents
- 17 5.10 Typical Characteristics - Current Consumption Per Module
- 17 5.11 Thermal Characteristics
- 18 5.12 Timing and Switching Characteristics
- 18 5.12.1 Power Supply Sequencing
- 19 5.12.2 Reset Timing
- 20 5.12.3 Clock Specifications
- 22 5.12.4 Digital I/Os
- 23 5.12.4.1 Digital I/O Typical Characteristics
- 23 5.12.5 Timer_A
- 24 5.12.6 eUSCI
- 29 5.12.7 ADC
- 31 5.12.8 FRAM
- 31 5.12.9 Emulation and Debug
- 32 6 Detailed Description
- 32 6.1 CPU
- 32 6.2 Operating Modes
- 33 6.3 Interrupt Vector Addresses
- 34 6.4 Bootstrap Loader (BSL)
- 34 6.5 JTAG Standard Interface
- 35 6.6 Spy-Bi-Wire Interface (SBW)
- 35 6.7 FRAM
- 35 6.8 Memory Protection
- 36 6.9 Peripherals
- 36 6.9.1 Power Management Module (PMM) and On-chip Reference Voltages
- 36 6.9.2 Clock System (CS) and Clock Distribution
- 37 6.9.3 General-Purpose Input/Output Port (I/O)
- 38 6.9.4 Watchdog Timer (WDT)
- 38 6.9.5 System Module (SYS)
- 39 6.9.6 Cyclic Redundancy Check (CRC)
- 39 6.9.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
- 40 6.9.8 Timers (Timer0_A3, Timer1_A3)
- 42 6.9.9 Real-Time Clock (RTC) Counter
- 42 6.9.10 10-Bit Analog Digital Converter (ADC)
- 43 6.9.11 Embedded Emulation Module (EEM)
- 44 6.9.12 Input/Output Schematics
- 44 6.9.12.1 Port P1 Input/Output With Schmitt Trigger
- 46 6.9.12.2 Port P2 Input/Output With Schmitt Trigger
- 47 6.9.12.3 Port P3 Input/Output With Schmitt Trigger
- 48 6.9.12.4 Port P4.0 Input/Output With Schmitt Trigger
- 49 6.9.12.5 Port P4.1 and P4.2 Input/Output With Schmitt Trigger
- 50 6.9.12.6 Port 4.3, P4.4, P4.5, P4.6, and P4.7 Input/Output With Schmitt Trigger
- 51 6.9.12.7 Port P5.0, P5.1, P5.2, and P5.3 Input/Output With Schmitt Trigger
- 52 6.9.12.8 Port P5.4, P5.5, P5.6, and P5.7 Input/Output With Schmitt Trigger
- 53 6.9.12.9 Port P6.0, P6.1, P6.2, and P6.3 Input/Output With Schmitt Trigger
- 54 6.9.12.10 Port P6.4, P6.5, P6.6, and P6.7 Input/Output With Schmitt Trigger
- 55 6.9.12.11 Port P7.0, P7.1, P7.2, and P7.3 Input/Output With Schmitt Trigger
- 56 6.9.12.12 Port P7.4, P7.5, P7.6, and P7.7 Input/Output With Schmitt Trigger
- 57 6.9.12.13 Port P8.0 and P8.1 Input/Output With Schmitt Trigger
- 59 6.9.12.14 Port P8.2 and P8.3 Input/Output With Schmitt Trigger
- 60 6.10 Device Descriptors (TLV)
- 61 6.11 Memory
- 62 6.11.1 Peripheral File Map
- 68 6.12 Identification
- 68 6.12.1 Revision Identification
- 68 6.12.2 Device Identification
- 68 6.12.3 JTAG Identification
- 69 7 Applications, Implementation, and Layout
- 69 7.1 Device Connection and Layout Fundamentals
- 69 7.1.1 Power Supply Decoupling and Bulk Capacitors
- 69 7.1.2 External Oscillator
- 70 7.1.3 JTAG
- 71 7.1.4 Reset
- 71 7.1.5 Unused Pins
- 72 7.1.6 General Layout Recommendations
- 72 7.1.7 Do's and Don'ts
- 72 7.2 Peripheral- and Interface-Specific Design Information
- 72 7.2.1 ADC Peripheral
- 72 7.2.1.1 Partial Schematic
- 72 7.2.1.2 Design Requirements
- 73 7.2.1.3 Layout Guidelines
- 74 8 Device and Documentation Support
- 74 8.1 Device Support
- 74 8.1.1 Development Support
- 74 8.1.1.1 Getting Started and Next Steps
- 74 8.1.1.2 Development Tools Support
- 75 8.1.2 Device and Development Tool Nomenclature
- 76 8.2 Documentation Support
- 76 8.2.1 Related Links
- 77 8.2.2 Community Resources
- 77 8.3 Trademarks
- 77 8.4 Electrostatic Discharge Caution
- 77 8.5 Glossary
- 78 9 Mechanical Packaging and Orderable Information
- 78 9.1 Packaging Information