Micropower Single-Supply Rail-to-Rail Input/Output Op Amps OP191/OP291/OP491

Micropower Single-Supply Rail-to-Rail Input/Output Op Amps OP191/OP291/OP491

FEATURES

Single-supply operation: 2.7 V to 12 V

Wide input voltage range

Rail-to-rail output swing

Low supply current: 300 μA/amp

Wide bandwidth: 3 MHz

Slew rate: 0.5 V/μs

Low offset voltage: 700 μV

No phase reversal

APPLICATIONS

Industrial process control

Battery-powered instrumentation

Power supply control and protection

Telecommunications

Remote sensors

Low voltage strain gage amplifiers

DAC output amplifiers

GENERAL DESCRIPTION

The OP191, OP291, and OP491 are single, dual, and quad micropower, single-supply, 3 MHz bandwidth amplifiers featuring rail-to-rail inputs and outputs. All are guaranteed to operate from a +3 V single supply as well as ±5 V dual supplies.

Fabricated on Analog Devices CBCMOS process, the OPx91 family has a unique input stage that allows the input voltage to safely extend 10 V beyond either supply without any phase inversion or latch-up. The output voltage swings to within millivolts of the supplies and continues to sink or source current all the way to the supplies.

Applications for these amplifiers include portable telecommunications equipment, power supply control and protection, and interface for transducers with wide output ranges. Sensors requiring a rail-to-rail input amplifier include

Hall effect, piezo electric, and resistive transducers.

Micropower Single-Supply

Rail-to-Rail Input/Output Op Amps

OP191/OP291/OP491

PIN CONFIGURATIONS

NC

1

–INA

2

+INA

3

–V

4

OP191

6

5

8

7

NC

+V

OUTA

NC

NC = NO CONNECT

Figure 1. 8-Lead Narrow-Body SOIC

OUTA

1

–INA

2

+INA

3

–V

4

OP291

6

5

8

7

+V

OUTB

–INB

+INB

Figure 2. 8-Lead Narrow-Body SOIC

OUTA

1

–INA

2

+INA

3

+V

4

+INB

5

–INB

6

OUTB

7

OP491

14

OUTD

13

12

–IND

+IND

11

10

–V

+INC

9

8

–INC

OUTC

Figure 3. 14-Lead Narrow-Body SOIC

OUTA

1

–INA

2

+INA

3

+V

4

+INB

5

–INB

6

OUTB

7

+

-

+ +

+

OP491

-

-

14

13

OUTD

–IND

12

11

+IND

–V

10

+INC

9

8

–INC

OUTC

Figure 4. 14-Lead PDIP

OUTA

1

–INA

2

+INA

3

+V

4

+INB

5

–INB

6

OUTB

7

OP491

14

13

12

11

10

9

8

OUTD

–IND

+IND

–V

+INC

–INC

OUTC

Figure 5. 14-Lead TSSOP

The ability to swing rail-to-rail at both the input and output enables designers to build multistage filters in single-supply systems and to maintain high signal-to-noise ratios.

The OP191/OP291/OP491 are specified over the extended industrial –40°C to +125°C temperature range. The OP191 single and OP291 dual amplifiers are available in 8-lead plastic

SOIC surface-mount packages. The OP491 quad is available in a

14-lead PDIP, a narrow 14-lead SOIC package, and a 14-lead

TSSOP.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

Fax: 781.461.3113 ©1994–2010 Analog Devices, Inc. All rights reserved.

OP191/OP291/OP491

TABLE OF CONTENTS

Features .............................................................................................. 1

 

Applications ....................................................................................... 1

 

Pin Configurations ........................................................................... 1

 

General Description ......................................................................... 1

 

Revision History ............................................................................... 2

 

Specifications ..................................................................................... 3

 

Electrical Specifications ............................................................... 3

 

Absolute Maximum Ratings ............................................................ 7

 

Thermal Resistance ...................................................................... 7

 

ESD Caution .................................................................................. 7

 

Typical Performance Characteristics ............................................. 8

 

Theory of Operation ...................................................................... 17

 

Input Overvoltage Protection ................................................... 18

 

Output Voltage Phase Reversal ................................................. 18

 

REVISION HISTORY

4/10—Rev. D to Rev. E

Changes to Input Voltage Parameter, Table 4 ............................... 7

4/06—Rev. C to Rev. D

Changes to Noise Performance, Voltage Density, Table 1 ........... 3

Changes to Noise Performance, Voltage Density, Table 2 ........... 4

Changes to Noise Performance, Voltage Density, Table 3 ........... 5

Changes to Figure 23 and Figure 24 ............................................. 10

Changes to Figure 42 ...................................................................... 13

Changes to Figure 43 ...................................................................... 14

Changes to Figure 57 ...................................................................... 16

Added Figure 58 .............................................................................. 16

Changed Reference from Figure 47 to Figure 12 ........................ 17

Updated Outline Dimensions ....................................................... 23

Changes to Ordering Guide .......................................................... 24

Overdrive Recovery ................................................................... 18

 

Applications Information .............................................................. 19

 

Single 3 V Supply, Instrumentation Amplifier ....................... 19

 

Single-Supply RTD Amplifier ................................................... 19

 

A 2.5 V Reference from a 3 V Supply ...................................... 20

 

5 V Only, 12-Bit DAC Swings Rail-to-Rail ............................. 20

 

A High-Side Current Monitor .................................................. 20

 

A 3 V, Cold Junction Compensated Thermocouple Amplifier

....................................................................................................... 21

 

Single-Supply, Direct Access Arrangement for Modems ...... 21

 

3 V, 50 Hz/60 Hz Active Notch Filter with False Ground ..... 22

 

Single-Supply, Half-Wave, and Full-Wave Rectifiers ............. 22

 

Outline Dimensions ....................................................................... 23

 

Ordering Guide .......................................................................... 24

 

3/04—Rev. B to Rev. C.

Changes to OP291 SOIC Pin Configuration ................................. 1

11/03—Rev. A to Rev. B.

Edits to General Description ........................................................... 1

Edits to Pin Configuration ............................................................... 1

Changes to Ordering Guide ............................................................. 5

Updated Outline Dimensions ....................................................... 19

12/02—Rev. 0 to Rev. A.

Edits to General Description ........................................................... 1

Edits to Pin Configuration ............................................................... 1

Changes to Ordering Guide ............................................................. 5

Edits to Dice Characteristics ............................................................ 5

Rev. E | Page 2 of 24

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

@ V

S

= 3.0 V, V

CM

= 0.1 V, V

O

= 1.4 V, T

A

= 25°C, unless otherwise noted.

Table 1.

INPUT CHARACTERISTICS

Offset Voltage

OP191G V

OS

OP291G/OP491G

Input Bias Current

V

OS

I

B

I

OS

Input Offset Current

Input Voltage Range

Common-Mode Rejection Ratio

Large Signal Voltage Gain

CMRR

A

VO

Offset Voltage Drift

Bias Current Drift

Offset Current Drift

OUTPUT CHARACTERISTICS

Output Voltage High

Output Voltage Low

Short-Circuit Limit

Open-Loop Impedance

POWER SUPPLY

Power Supply Rejection Ratio

Supply Current/Amplifier

DYNAMIC PERFORMANCE

Slew Rate

Slew Rate

Full-Power Bandwidth

Settling Time

Gain Bandwidth Product

Phase Margin

Channel Separation

NOISE PERFORMANCE

Voltage Noise

Voltage Noise Density

Current Noise Density

I

SY

+SR

–SR

BW

P t

S

GBP

θ

O

CS e n

p-p e n i n

I

SC

Z

OUT

PSRR

∆V

OS

/∆T

∆I

B

/∆T

∆I

OS

/∆T

V

OH

V

OL

V

CM

= 0 V to 2.9 V

R

L

= 10 kΩ, V

O

= 0.3 V to 2.7 V

R

L

= 100 kΩ to GND

−40°C to +125°C

R

L

= 2 kΩ to GND

−40°C to +125°C

R

L

= 100 kΩ to V+

−40°C to +125°C

R

L

= 2 kΩ to V+

−40°C to +125°C

Sink/source

−40°C to +125°C f = 1 MHz, A

V

= 1

V

S

= 2.7 V to 12 V

V

O

= 0 V

R

L

= 10 kΩ

R

L

= 10 kΩ

1% distortion

To 0.01% f = 1 kHz, R

L

= 10 kΩ

0.1 Hz to 10 Hz f = 1 kHz

Rev. E | Page 3 of 24

OP191/OP291/OP491

2.95

2.90

2.8

2.70

±8.75

±6.0

80

0

70

25

1.1

100

20

2.99

2.98

2.9

2.80

4.5

40

±13.50

0.1

90

87

70

50

80

80

30

330

0.4

0.4

1.2

22

3

45

145

±10.5

200

110

110

200

2

30

0.8

10

35

75

130

11

22

3

500

1

μV mV

700 μV

1.25 mV

65

95 nA nA nA nA

V dB dB

V/mV

V/mV

V

V mV mV mV mV mA

V

V

μV/°C pA/°C pA/°C

480

350 mA

Ω dB dB

μA

μA

V/μs

V/μs kHz

μs

MHz

Degrees dB

μV p-p nV/√Hz pA/√Hz

OP191/OP291/OP491

@ V

S

= 5.0 V, V

CM

= 0.1 V, V

O

= 1.4 V, T

A

= 25°C, unless otherwise noted. +5 V specifications are guaranteed by +3 V and ±5 V testing.

Table 2.

INPUT CHARACTERISTICS

Offset Voltage

OP191 V

OS

−40°C 1.0

OP291/OP491

Input Bias Current I

V

B

OS mV

−40°C 1.25 mV

80

30

−40°C

700 μV

65

95 nA nA

Input Offset Current I

OS

Input Voltage Range

Common-Mode Rejection Ratio

Large Signal Voltage Gain

CMRR

A

VO

0.1 11

−40°C 22

0 5

V

CM

= 0 V to 4.9 V 70 93

–40°C

R

L

= 10 kΩ, V

O

= 0.3 V to 4.7 V 25 70

−40°C nA nA

V dB dB

V/mV

V/mV

OUTPUT CHARACTERISTICS

Offset Voltage Drift

Bias Current Drift

Offset Current Drift

Output Voltage High

Output Voltage Low

Short-Circuit Limit

Open-Loop Impedance

POWER SUPPLY

Power Supply Rejection Ratio

Supply Current/Amplifier

DYNAMIC PERFORMANCE

Slew Rate

Slew Rate

Full-Power Bandwidth

Settling Time

Gain Bandwidth Product

Phase Margin

Channel Separation

NOISE PERFORMANCE

Voltage Noise

Voltage Noise Density

Current Noise Density

+SR

–SR

BW

P t

S

GBP

θ

O

CS

I

I

SC

V

OL

∆V

OS

/∆T −40°C ≤ T

A

≤ +125°C

∆I

B

/∆T

∆I

OS

/∆T

V

OH

R

L

= 100 kΩ to GND

−40°C to +125°C

Z

OUT

PSRR

R

R

L

R

L

L

= 2 kΩ to GND

−40°C to +125°C

= 100 kΩ to V+

−40°C to +125°C

= 2 kΩ to V+

−40°C to +125°C

Sink/source

−40°C to +125°C f = 1 MHz, A

V

= 1

SY

4.95

4.90

4.8

4.65

1.1

100

20

4.99

4.98

±8.75 ±13.5

±6.0

4.85

4.75

4.5

40

±10.5

200

10

35

75

μV/°C pA/°C pA/°C

V

V

155 mV

V

V mV mV mV mA mA

Ω

V

S

= 2.7 V to 12 V 80 110

−40°C dB dB

V

O

= 0 V 220 400 μA

−40°C 500 μA

0.4 V/μs R

L

= 10 kΩ

R

L

= 10 kΩ

1% distortion

To 0.01%

0.4

1.2

22

3

V/μs kHz

μs

MHz e i n n e n

p-p f = 1 kHz, R

L

= 10 kΩ

0.1 Hz to 10 Hz f = 1 kHz

45

145

2

42

0.8

Degrees dB

μV p-p nV/√Hz pA/√Hz

Rev. E | Page 4 of 24

@ V

O

= ±5.0 V, –4.9 V ≤ V

CM

≤ +4.9 V, T

A

= +25°C, unless otherwise noted.

Table 3.

OP191/OP291/OP491

OP191 V

OS

OP291/OP491

Input Bias Current I

V

B

OS mV

80

30

700

65

μV

≤ mV nA nA

Input Offset Current I

OS

0.1 11

Input Voltage Range

Common-Mode Rejection Ratio

Large Signal Voltage Gain

Offset Voltage Drift

Bias Current Drift

Offset Current Drift

Output Voltage Swing

Short-Circuit Limit

Open-Loop Impedance

Power Supply Rejection Ratio

Supply Current/Amplifier

Slew Rate

Full-Power Bandwidth

Settling Time

Gain Bandwidth Product

Phase Margin

Channel Separation

Voltage Noise

Voltage Noise Density

Current Noise Density t

I

CMRR

A

VO

∆V

∆I

B

V

O

I

SC

SY

OS

Z

OUT

/∆T

/∆T

∆I

OS

/∆T

R

L f = 1 MHz, A

PSRR V

S

= ±5 V

±SR

BW

S

P

GBP

θ

O

CS

V

R

−40°C to +125°C

R

Sink/source

−40°C to +125°C

V

CM

L

L

O

= ±5 V

= +10 kΩ, V

= 100 kΩ to GND

= 2 kΩ to GND

= 0 V

R

L

= 10 kΩ

1% distortion

To 0.01% f = 1 kHz e n

p-p 0.1 Hz to 10 Hz e n i n f = 1 kHz

V

O

= ±4.7 V

= 1

−5

75

25

±4.93

±4.90

±4.80

±8.75

±6

80

100

70

1.1

100

20

±4.99

±4.98

±4.95

±16.00

±13

200

110

260

0.5

1.2

22

3

45

145

2

42

0.8

+5

420 nA nA

V dB dB

V/mV

μV/°C pA/°C pA/°C

V

V

V

V mA mA

Ω dB dB

μA

μA

V/μs kHz

μs

MHz

Degrees dB

μV p-p nV/√Hz pA/√Hz

Rev. E | Page 5 of 24

OP191/OP291/OP491

INPUT

100

90

OUTPUT

5V

V s

R

L

= ±5V

= 2kΩ

A

V

V

IN

= +1

= 20V p-p

10

0%

5V 200μs

Figure 6. Input and Output with Inputs Overdriven by 5 V

Rev. E | Page 6 of 24

OP191/OP291/OP491

ABSOLUTE MAXIMUM RATINGS

Table 4.

THERMAL RESISTANCE

Parameter Rating

Supply Voltage 16 V

θ

JA

is specified for the worst-case conditions; that is, θ

JA

is

Input Voltage

Differential Input Voltage

GND to (V

S

+ 10 V)

7 V specified for device in socket for PDIP packages; θ

JA

is specified for device soldered in circuit board for TSSOP and SOIC

Output Short-Circuit Duration to GND Indefinite packages.

Storage Temperature Range

Table 5. Thermal Resistance

N, R, RU Packages −65°C to +150°C

Package Type θ

JA

θ

JC

Unit

Operating Temperature Range

OP191G/OP291G/OP491G

Junction Temperature Range

N, R, RU Packages

−40°C to +125°C

−65°C to +150°C

8-Lead SOIC (R)

14-Lead PDIP (N)

14-Lead SOIC (R)

14-Lead TSSOP (RU)

158

76

120

180

43

33

36

35

°C/W

°C/W

°C/W

°C/W

Lead Temperature (Soldering, 60 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted.

Rev. E | Page 7 of 24

OP191/OP291/OP491

TYPICAL PERFORMANCE CHARACTERISTICS

180

160

140

V

S

= 3V

T

A

= 25°C

BASED ON

1200 OP AMPS

120

100

80

60

40

20

0

–0.18

–0.10

–0.02

0.06

INPUT OFFSET VOLTAGE (mV)

0.14

Figure 7. OP291 Input Offset Voltage Distribution, V

S

= 3 V

0.22

120

100

V

S

= 3V

–40°C < T

A

< +125°C

BASED ON 600 OP AMPS

80

60

40

20

0

0 1 2 3 4 5

INPUT OFFSET VOLTAGE (µV/°C)

6

Figure 8. OP291 Input Offset Voltage Drift Distribution, V

S

= 3 V

7

0

V

S

= 3V

–0.02

V

CM

= 0.1V

–0.04

–0.06

V

CM

= 3V

V

CM

= 0V

–0.08

V

CM

= 2.9V

–0.10

–0.12

–0.14

–40 25

TEMPERATURE (°C)

85

Figure 9. Input Offset Voltage vs. Temperature, V

S

= 3 V

125

–1.0

–1.2

–1.4

–1.6

–0.2

–0.4

–0.6

–0.8

40

30

V

CM

= 3V

20

10

V

CM

= 2.9V

0

–10

V

S

= 3V

–20

–30

–40

V

CM

= 0.1V

V

CM

= 0V

–50

–60

–40 25

TEMPERATURE (°C)

85

Figure 10. Input Bias Current vs. Temperature, V

S

= 3 V

0

125

V

S

= 3V

V

CM

= 0.1V

V

CM

= 2.9V

V

CM

= 3V

V

CM

= 0V

–1.8

–40 25

TEMPERATURE (°C)

85

Figure 11. Input Offset Current vs. Temperature, V

S

= 3 V

125

12

6

0

–6

–12

–18

–24

–30

36

30

24

18

V

S

= 3V

–36

0 0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

INPUT COMMON-MODE VOLTAGE (V)

2.7

3.0

Figure 12. Input Bias Current vs. Input Common-Mode Voltage, V

S

= 3 V

Rev. E | Page 8 of 24

3.00

+V

O

@ R

L

= 100kΩ

2.95

2.90

2.85

+V

O

@ R

L

= 2kΩ

2.80

2.75

–40

V

S

= 3V

25

TEMPERATURE (°C)

85

Figure 13. Output Voltage Swing vs. Temperature, V

S

= 3 V

125

160

140

120

100

80

60

40

20

0

–20

–40

100

V

S

T

A

= 3V

= 25°C

800

1k 10k 100k

FREQUENCY (Hz)

1M

Figure 14. Open-Loop Gain and Phase vs. Frequency, V

S

= 3 V

1200

R

V

L

= 100kΩ,

CM

= 2.9V

1000

R

V

L

= 100kΩ,

CM

= 0.1V

90

45

0

–45

10M

–90

600

400

200

V

S

= 3V, V

O

= 0.3V/2.7V

0

–40 25 85

TEMPERATURE (°C)

Figure 15. Open-Loop Gain vs. Temperature, V

S

= 3 V

125

OP191/OP291/OP491

160

140

120

100

80

60

40

20

0

–20

–40

100

50

40

30

20

10

0

–10

–20

–30

–40

V

S

T

A

= 3V

= 25°C

–50

10 100 1k 10k

FREQUENCY (Hz)

100k 1M

Figure 16. Closed-Loop Gain vs. Frequency, V

S

= 3 V

10M

CMRR

V

S

T

A

= 3V

= 25°C

10M 1k 10k 100k

FREQUENCY (Hz)

1M

Figure 17. CMRR vs. Frequency, V

S

= 3 V

90

V

S

= 3V

89

88

87

86

85

84

–40 25 85

TEMPERATURE (°C)

Figure 18. CMRR vs. Temperature, V

S

= 3 V

125

Rev. E | Page 9 of 24

OP191/OP291/OP491

160

140

120

100

80

60

40

20

0

–20

–40

100

–PSRR

+PSRR

±PSRR

V

S

T

A

= 3V

= 25°C

1k 10k 100k

FREQUENCY (Hz)

Figure 19. PSRR vs. Frequency, V

S

= 3 V

1M

113

V

S

= 3V

10M

112

111

110

109

108

107

–40 25 85

TEMPERATURE (°C)

Figure 20. PSRR vs. Temperature, V

S

= 3 V

1.6

V

S

= 3V

1.4

+SR

1.2

1.0

0.8

0.6

0.4

0.2

–SR

0

–40 25

TEMPERATURE (°C)

85

Figure 21. Slew Rate vs. Temperature, V

S

= 3 V

125

125

0.20

0.15

0.10

0.35

V

S

= 3V

0.30

0.25

0.05

–40 25 85

TEMPERATURE (°C)

125

Figure 22. Supply Current vs. Temperature, V

S

= +3 V, +5 V, ±5 V

3.0

2.5

V

IN

= 2.8V p-p

V

S

= 3V

A

V

= +1

R

L

= 100kΩ

2.0

1.5

1.0

0.5

0

100 1k 10k

FREQUENCY (Hz)

100k

Figure 23. Maximum Output Swing vs. Frequency, V

S

= 3 V

1M

1k

100

10

10 100

FREQUENCY (Hz)

1k

Figure 24. Voltage Noise Density, V

S

= 5 V or ±5 V

10k

Rev. E | Page 10 of 24

80

60

40

20

40

30

20

10

70

60

V

T

S

A

= 5V

= 25°C

BASED ON 600

OP AMPS

50

0

–0.50

–0.30

–0.10

0.10

0.30

INPUT OFFSET VOLTAGE (mV)

0.50

Figure 25. OP291 Input Offset Voltage Distribution, V

S

= 5 V

120

100

V

S

= 5V

–40°C < T

A

< +125°C

BASED ON 600 OP AMPS

0

0 1 2 3 4 5

INPUT OFFSET VOLTAGE (µV/°C)

6 7

Figure 26. OP291 Input Offset Voltage Drift Distribution, V

S

= 5 V

0.15

V

S

= 5V

0.10

V

CM

= 0V

0.05

0

–0.05

V

CM

= 5V

–0.10

–40 25 85

TEMPERATURE (°C)

Figure 27. Input Offset Voltage vs. Temperature, V

S

= 5 V

125

OP191/OP291/OP491

40

V

S

= 5V

30

+I

B

–I

B

V

CM

= 5V

0

–10

20

10

0.8

0.6

0.4

1.6

1.4

1.2

1.0

–20

V

CM

= 0V

–30

–40

–40 25

TEMPERATURE (°C)

85

Figure 28. Input Bias Current vs. Temperature, V

S

= 5 V

–I

B

+I

B

125

V

CM

= 0V

V

S

= 5V

0.2

0

V

CM

= 5V

–0.2

–40 25

TEMPERATURE (°C)

85

Figure 29. Input Offset Current vs. Temperature, V

S

= 5 V

125

36

30

24

18

12

6

V

S

= 5V

0

–6

–12

–18

–24

–30

–36

0 1 2 3 4

COMMON-MODE INPUT VOLTAGE (V)

5

Figure 30. Input Bias Current vs. Common-Mode Input Voltage, V

S

= 5 V

Rev. E | Page 11 of 24

OP191/OP291/OP491

5.00

4.95

R

L

= 100kΩ

4.90

4.85

R

L

= 2kΩ

4.80

4.75

4.70

–40

V

S

= 5V

25 85

TEMPERATURE (°C)

Figure 31. Output Voltage Swing vs. Temperature, V

S

= 5 V

125

160

140

120

100

80

60

40

20

0

–20

–40

100

V

S

T

A

= 5V

= 25°C

1k 10k 100k

FREQUENCY (Hz)

1M

Figure 32. Open-Loop Gain and Phase vs. Frequency, V

S

= 5 V

140

V

S

= 5V

120

R

L

= 100kΩ, V

CM

= 5V

90

45

0

–45

10M

–90

100

80

60

R

L

= 100kΩ, V

CM

= 0V

40

R

L

= 2kΩ, V

CM

= 5V

20

R

L

= 2kΩ, V

CM

= 0V

0

–40 25 85

TEMPERATURE (°C)

Figure 33. Open-Loop Gain vs. Temperature, V

S

= 5 V

125

50

40

30

20

10

0

–10

–20

–30

–40

V

S

T

A

= 5V

= 25°C

–50

10 100 1k 10k

FREQUENCY (Hz)

100k 1M

Figure 34. Closed-Loop Gain vs. Frequency, V

S

= 5 V

160

140

120

100

80

60

40

20

0

–20

–40

100

CMRR

V

T

S

A

= 5V

= 25°C

1k 10k 100k

FREQUENCY (Hz)

Figure 35. CMRR vs. Frequency, V

S

= 5V

1M

10M

10M

89

88

87

86

–40

96

95

94

93

92

91

90

V

S

= 5V

25 85

TEMPERATURE (°C)

Figure 36. CMRR vs. Temperature, V

S

= 5 V

125

Rev. E | Page 12 of 24

0.5

0.4

0.3

160

140

120

100

80

60

40

20

0

–20

–40

100

+PSRR

–PSRR

±PSRR

V

S

= 5V

T

A

= 25°C

1k 10k 100k

FREQUENCY (Hz)

Figure 37. PSRR vs. Frequency, V

S

= 5 V

1M

0.6

10M

+SR –SR

0.2

0.1

V

S

= 5V

0

–40 25 85

TEMPERATURE (°C)

Figure 38. OP291 Slew Rate vs. Temperature, V

S

= 5 V

125

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

V

S

= 5V

+SR

–SR

0.05

0

–40

25 85

TEMPERATURE (°C)

Figure 39. OP491 Slew Rate vs. Temperature, V

S

= 5 V

125

OP191/OP291/OP491

14

12

10

8

20

18

16

+I

SC

, V

S

= +3V

+I

SC

, V

S

= ±5V

–I

SC

, V

S

= ±5V

–I

SC

, V

S

= +3V

6

4

–40 25

TEMPERATURE (°C)

85 125

Figure 40. Short-Circuit Current vs. Temperature, V

S

= +3 V, +5 V, ±5 V

80

V

S

= ±5V

70

60

50

40

30

20

10

0

0

10kΩ

1kΩ

A

10kΩ

V

IN

= 10V p-p @ 1kHz

B

500 1000 1500

FREQUENCY (Hz)

2000

Figure 41. Channel Separation, V

S

= ±5 V

V

O

2500

5.0

4.5

4.0

3.5

3.0

V

IN

= 4.8V p-p

V

S

A

R

V

= 5V

= +1

L

= 100kΩ

2.5

2.0

1.5

1.0

0.5

0

100 1k 10k

FREQUENCY (Hz)

100k

Figure 42. Maximum Output Swing vs. Frequency, V

S

= 5 V

1M

Rev. E | Page 13 of 24

OP191/OP291/OP491

10

8

6

4

2

V

IN

V

S

A

R

V

= 9.8V p-p

= ±5V

= +1

L

= 100kΩ

0

100 1k 10k

FREQUENCY (Hz)

100k

Figure 43. Maximum Output Swing vs. Frequency, V

S

= ±5 V

1M

0.15

V

S

= ±5V

0.10

V

CM

= –5V

0.05

0

V

CM

= +5V

–0.05

–0.10

–40 25 85

TEMPERATURE (°C)

Figure 44. Input Offset Voltage vs. Temperature, V

S

= ±5 V

125

50

40

30

20

10

0

V

S

= ±5V

V

CM

= +5V

+I

B

–I

B

–10

–20

–30

V

CM

= –5V

–I

B

–40

+I

B

–50

–40 25

TEMPERATURE (°C)

85

Figure 45. Input Bias Current vs. Temperature, V

S

= ±5 V

125

0.8

0.6

0.4

0.2

0

1.6

1.4

1.2

1.0

V

S

= ±5V

V

CM

= –5V

V

CM

= +5V

–0.2

–40 25

TEMPERATURE (°C)

85

Figure 46. Input Offset Current vs. Temperature, V

S

= ±5 V

125

36

V

S

= ±5V

24

12

0

–12

–24

–36

–5 –4 –3 –2 –1 0 1 2 3

COMMON-MODE INPUT VOLTAGE (V)

4 5

Figure 47. Input Bias Current vs. Common-Mode Voltage, V

S

= ±5 V

5.00

4.95

4.90

4.85

4.80

4.75

0

–4.75

–4.80

–4.85

–4.90

V

S

= ±5V

R

L

= 2kΩ

R

L

= 2kΩ

R

L

= 2kΩ

–4.95

–5.00

–40

R

L

= 2kΩ

25 85

TEMPERATURE (°C)

Figure 48. Output Voltage Swing vs. Temperature, V

S

= ±5 V

125

Rev. E | Page 14 of 24

70

60

V

S

T

A

= ±5V

= 25°C

50

40

30

20

10

0

45

90

135

0

–10

–20

180

225

270

–30

1k 10k 100k

FREQUENCY (Hz)

1M 10M

Figure 49. Open-Loop Gain and Phase vs. Frequency, V

S

= ±5 V

50

40

30

20

10

0

–10

–20

–30

–40

200

V

S

= ±5V

180

160

R

L

= 2kΩ

140

120

100

80

65

40

R

L

= 2kΩ

25

0

–40 25 85

TEMPERATURE (°C)

Figure 50. Open-Loop Gain vs. Temperature, V

S

= ±5 V

125

V

S

T

A

= ±5V

= 25°C

–50

10 100 1k 10k

FREQUENCY (Hz)

100k 1M

Figure 51. Closed-Loop Gain vs. Frequency, V

S

= ±5 V

10M

OP191/OP291/OP491

160

140

120

100

80

60

40

20

0

–20

–40

100

CMRR

V

S

T

A

= ±5V

= 25°C

1k 10k 100k

FREQUENCY (Hz)

1M

Figure 52. CMRR vs. Frequency, V

S

= ±5 V

10M

140

120

100

80

60

40

20

0

–20

–40

100

102

V

S

= ±5V

101

100

99

98

97

96

95

94

93

92

–40 25 85

TEMPERATURE (°C)

Figure 53. CMRR vs. Temperature, V

S

=± 5 V

160

±PSRR

V

S

= ±5V

T

A

= 25°C

–PSRR

+PSRR

125

10M 1k 10k 100k

FREQUENCY (Hz)

1M

Figure 54. PSRR vs. Frequency, V

S

= ±5 V

Rev. E | Page 15 of 24

OP191/OP291/OP491

115

V

S

= ±5V

110

OP291

105

OP491

100

95

0.2

0.1

90

–40 25 85

TEMPERATURE (°C)

Figure 55. OP291/OP491 PSRR vs. Temperature, V

S

= ±5 V

125

0.7

V

S

= ±5V

0.6

+SR

0.5

–SR

0.4

0.3

0

–40 25 85

TEMPERATURE (°C)

Figure 56. Slew Rate vs. Temperature, V

S

= ±5 V

1k

V

S

= 3V

A

V

= +100

100

A

V

= +10

10

A

V

= +1

125

1

0.1

1k 10k 100k

FREQUENCY (Hz)

Figure 57. Output Impedance vs. Frequency

1M 2M

1k

100

10

10 100

FREQUENCY (Hz)

1k

Figure 58. Voltage Noise Density, V

S

= 3 V

100

90

1.00V

10k

INPUT

OUTPUT

10

0%

500mV 2.00µs

V

S

R

L

= 3V

= 200kΩ

100mV

Figure 59. Large Signal Transient Response, V

S

= 3 V

100

90

2.00V

INPUT

OUTPUT

10

0%

1.00V

V

S

R

L

A

V

= ±5V

= 200kΩ

= +1V/V

2.00µs 100mV

Figure 60. Large Signal Transient Response, V

S

= ±5 V

Rev. E | Page 16 of 24

THEORY OF OPERATION

The OP191/OP291/OP491 are single-supply, micropower amplifiers featuring rail-to-rail inputs and outputs. To achieve wide input and output ranges, these amplifiers employ unique

input and output stages. In Figure 61 , the input stage comprises

two differential pairs, a PNP pair and an NPN pair. These two stages do not work in parallel. Instead, only one stage is on for any given input signal level. The PNP stage (Transistor Q1 and

Transistor Q2) is required to ensure that the amplifier remains in the linear region when the input voltage approaches and reaches the negative rail. On the other hand, the NPN stage

(Transistor Q5 and Transistor Q6) is needed for input voltages up to and including the positive rail.

For the majority of the input common-mode range, the PNP

stage is active, as is shown in Figure 12. Notice that the bias

current switches direction at approximately 1.2 V to 1.3 V below the positive rail. At voltages below this, the bias current flows out of the OP291, indicating a PNP input stage. Above this voltage, however, the bias current enters the device, revealing the NPN stage. The actual mechanism within the amplifier for switching between the input stages comprises

Transistor Q3, Transistor Q4, and Transistor Q7. As the input common-mode voltage increases, the emitters of Q1 and Q2 follow that voltage plus a diode drop. Eventually, the emitters of Q1 and Q2 are high enough to turn on Q3, which diverts the

8 μA of tail current away from the PNP input stage, turning it off. Instead, the current is mirrored through Q4 and Q7 to activate the NPN input stage.

OP191/OP291/OP491

Notice that the input stage includes 5 kΩ series resistors and differential diodes, a common practice in bipolar amplifiers to protect the input transistors from large differential voltages.

These diodes turn on whenever the differential voltage exceeds approximately 0.6 V. In this condition, current flows between the input pins, limited only by the two 5 kΩ resistors. This characteristic is important in circuits where the amplifier may be operated open-loop, such as a comparator. Evaluate each circuit carefully to make sure that the increase in current does not affect the performance.

The output stage in OP191 devices uses a PNP and an NPN transistor, as do most output stages; however, Q32 and Q33, the output transistors, are actually connected with their collectors to the output pin to achieve the rail-to-rail output swing. As the output voltage approaches either the positive or negative rail, these transistors begin to saturate. Thus, the final limit on output voltage is the saturation voltage of these transistors, which is about 50 mV. The output stage does have inherent gain arising from the collectors and any external load impedance.

Because of this, the open-loop gain of the amplifier is dependent on the load resistance.

8µA

+IN

5kΩ

Q1 Q2

Q3

Q4

5kΩ

–IN

Q5 Q6

Q8

Q9

Q10 Q12 Q14

Q11 Q13 Q15

Q22 Q26

Q16

Q17

Q20

Q23 Q27

Q30

Q21

Q24 Q28

Q31

10pF

Q32

V

OUT

Q18 Q19 Q25 Q29

Q33

Q7

Figure 61. Simplified Schematic

Rev. E | Page 17 of 24

OP191/OP291/OP491

INPUT OVERVOLTAGE PROTECTION

As with any semiconductor device, whenever the condition exists for the input to exceed either supply voltage, check the input overvoltage characteristic. When an overvoltage occurs, the amplifier could be damaged depending on the voltage level

and the magnitude of the fault current. Figure 62 shows the

characteristics for the OP191 family. This graph was generated with the power supplies at ground and a curve tracer connected to the input. When the input voltage exceeds either supply by more than 0.6 V, internal PN junctions energize, allowing current to flow from the input to the supplies. As described, the

OP291/OP491 do have 5 kΩ resistors in series with each input to help limit the current. Calculating the slope of the current vs. voltage in the graph confirms the 5 kΩ resistor.

I

IN

+2mA

–10V –5V

+1mA

+5V +10V

V

IN

–1mA

–2mA

Figure 62. Input Overvoltage Characteristics

This input current is not inherently damaging to the device as long as it is limited to 5 mA or less. For an input of 10 V over the supply, the current is limited to 1.8 mA. If the voltage is large enough to cause more than 5 mA of current to flow, then an external series resistor should be added. The size of this resistor is calculated by dividing the maximum overvoltage by

5 mA and subtracting the internal 5 kΩ resistor. For example, if the input voltage could reach 100 V, the external resistor should be (100 V/5 mA) − 5 kΩ = 15 kΩ. This resistance should be placed in series with either or both inputs if they are subjected to the overvoltages.

V

IN

20V p-p

OUTPUT VOLTAGE PHASE REVERSAL

Some operational amplifiers designed for single-supply operation exhibit an output voltage phase reversal when their inputs are driven beyond their useful common-mode range.

Typically, for single-supply bipolar op amps, the negative supply determines the lower limit of their common-mode range.

With these devices, external clamping diodes with the anode connected to ground and the cathode to the inputs prevent input signal excursions from exceeding the device’s negative supply (that is, GND), preventing a condition that could cause the output voltage to change phase. JFET input amplifiers can also exhibit phase reversal, and, if so, a series input resistor is usually required to prevent it.

The OP191 is free from reasonable input voltage range restrictions due to its novel input structure. In fact, the input signal can exceed the supply voltage by a significant amount

without causing damage to the device. As shown in Figure 64,

the OP191 family can safely handle a 20 V p-p input signal on

±5 V supplies without exhibiting any sign of output voltage phase reversal or other anomalous behavior. Thus, no external clamping diodes are required.

OVERDRIVE RECOVERY

The overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to its linear region from a saturated condition. This recovery time is important in applications where the amplifier must recover quickly after a large transient event, such as a comparator. The

circuit shown in Figure 63 was used to evaluate the OPx91

overdrive recovery time. The OPx91 takes approximately 8 μs to recover from positive saturation and approximately 6.5 μs to recover from negative saturation.

R1

9kΩ

V

IN

10V STEP

R2

10kΩ

3

+

1/2

OP291

2

1

R3

10kΩ

V

OUT

V

S

= ±5V

Figure 63. Overdrive Recovery Time Test Circuit

5µs 5µs

100

90

+5V

3

2

8

+

1/2

OP291

4

–5V

1

V

OUT

100

90

10

0%

TIME (200µs/DIV)

Figure 64. Output Voltage Phase Reversal Behavior

Rev. E | Page 18 of 24

10

0%

20mV

TIME (200µs/DIV)

20mV

APPLICATIONS INFORMATION

SINGLE 3 V SUPPLY, INSTRUMENTATION

AMPLIFIER

The OP291 low supply current and low voltage operation make it ideal for battery-powered applications, such as the

instrumentation amplifier shown in Figure 65. The circuit uses

the classic two op amp instrumentation amplifier topology, with four resistors to set the gain. The equation is simply that of a

noninverting amplifier, as shown in Figure 65. The two resistors

labeled R1 should be closely matched both to each other and to the two resistors labeled R2 to ensure good common-mode rejection performance. Resistor networks ensure the closest matching as well as matched drifts for good temperature stability. Capacitor C1 is included to limit the bandwidth and, therefore, the noise in sensitive applications. The value of this capacitor should be adjusted depending on the desired closedloop bandwidth of the instrumentation amplifier. The RC combination creates a pole at a frequency equal to 1/(2π ×

R1C1). If AC-CMRR is critical, then a matched capacitor to C1 should be included across the second resistor labeled R1.

+

V

IN

3V

5

6

8

1/2

OP291

4

7

V

OUT

R1

3

2

1/2

OP291

R2

1

R2 R1

V

OUT

= (1 + ) = V

IN

C1

100pF

Figure 65. Single 3 V Supply Instrumentation Amplifier

Because the OP291 accepts rail-to-rail inputs, the input common-mode range includes both ground and the positive supply of 3 V. Furthermore, the rail-to-rail output range ensures the widest signal range possible and maximizes the dynamic range of the system. Also, with its low supply current of

300 μA/device, this circuit consumes a quiescent current of only 600 μA yet still exhibits a gain bandwidth of 3 MHz.

A question may arise about other instrumentation amplifier topologies for single-supply applications. For example, a variation on this topology adds a fifth resistor between the two inverting inputs of the op amps for gain setting. While that topology works well in dual-supply applications, it is inherently inappropriate for single-supply circuits. The same could be said for the traditional three op amp instrumentation amplifier. In both cases, the circuits simply cannot work in single-supply situations unless a false ground between the supplies is created.

OP191/OP291/OP491

SINGLE-SUPPLY RTD AMPLIFIER

The circuit in Figure 66 uses three op amps of the OP491 to

develop a bridge configuration for an RTD amplifier that operates from a single 5 V supply. The circuit takes advantage of the OP491 wide output swing range to generate a high bridge excitation voltage of 3.9 V. In fact, because of the rail-to-rail output swing, this circuit works with supplies as low as 4.0 V.

Amplifier A1 servos the bridge to create a constant excitation current in conjunction with the AD589, a 1.235 V precision reference. The op amp maintains the reference voltage across the parallel combination of the 6.19 kΩ and 2.55 MΩ resistors, which generate a 200 μA current source. This current splits evenly and flows through both halves of the bridge. Thus,

100 μA flows through the RTD to generate an output voltage based on its resistance. A 3-wire RTD is used to balance the line resistance in both 100 Ω legs of the bridge to improve accuracy.

26.7kΩ

200Ω

10 TURNS

26.7kΩ

100Ω

RTD

2.55MΩ

100Ω

6.19kΩ

A1

1/4

OP491

1/4

OP491

A2

365Ω 365Ω

GAIN = 274

5V

1/4

OP491

A3

100kΩ

100kΩ

0.01pF

ALL RESISTORS 1% OR BETTER

V

OUT

AD589

37.4kΩ

5V

Figure 66. Single-Supply RTD Amplifier

Amplifier A2 and Amplifier A3 are configured in the two op

amp instrumentation amplifier topology described in the Single

3 V Supply, Instrumentation Amplifier section. The resistors are

chosen to produce a gain of 274, such that each 1°C increase in temperature results in a 10 mV change in the output voltage, for ease of measurement. A 0.01 μF capacitor is included in parallel with the 100 kΩ resistor on Amplifier A3 to filter out any unwanted noise from this high gain circuit. This particular RC combination creates a pole at 1.6 kHz.

Rev. E | Page 19 of 24

OP191/OP291/OP491

A 2.5 V REFERENCE FROM A 3 V SUPPLY

In many single-supply applications, the need for a 2.5 V reference often arises. Many commercially available monolithic

2.5 V references require a minimum operating supply voltage of

4 V. The problem is exacerbated when the minimum operating

system supply voltage is 3 V. The circuit illustrated in Figure 67

is an example of a 2.5 V reference that operates from a single

3 V supply. The circuit takes advantage of the OP291 rail-to-rail input and output voltage ranges to amplify an AD589 1.235 V output to 2.5 V. The OP291 low TCV

OS

of 1 μV/°C helps maintain an output voltage temperature coefficient of less than

200 ppm/°C. The circuit overall temperature coefficient is dominated by the temperature coefficient of R2 and R3. Lower temperature coefficient resistors are recommended. The entire circuit draws less than 420 μA from a 3 V supply at 25°C.

3V

R1

17.4kΩ

3V

AD589

3 8

1/2

OP291

2

4

1

2.5V

REF

RESISTORS = 1%, 100ppm/°C

POTENTIOMETER = 10 TURN, 100ppm/°C

R3

100kΩ

R2

100kΩ

R1

5kΩ

Figure 67. A 2.5 V Reference that Operates on a Single 3 V Supply

5 V ONLY, 12-BIT DAC SWINGS RAIL-TO-RAIL

The OPx91 family is ideal for use with a CMOS DAC to generate a digitally controlled voltage with a wide output range.

Figure 68 shows the DAC8043 used in conjunction with the

AD589 to generate a voltage output from 0 V to 1.23 V. The

DAC is operated in voltage switching mode, where the reference is connected to the current output, I

OUT

, and the output voltage is taken from the V

REF

pin. This topology is inherently noninverting as opposed to the classic current output mode, which is inverting and, therefore, unsuitable for single supply.

5V

R1

17.8kΩ

1.23V

AD589

3

I

OUT

V

DD

8

DAC8043

R

FB

2

V

REF

1

GND CLK SR1

4 7 6

LD

5

DIGITAL

CONTROL

5V

3 8

1/2

OP291

2

4

1

V

OUT

= –––– (5V)

4096

R3

232Ω

1%

R2

32.4kΩ

1%

R4

100kΩ

1%

Figure 68. 5 V Only, 12-Bit DAC Swings Rail-to-Rail

The OP291 serves two functions. First, it is required to buffer the high output impedance of the DAC V

REF

pin, which is on the order of 10 kΩ. The op amp provides a low impedance output to drive any following circuitry. Second, the op amp amplifies the output signal to provide a rail-to-rail output swing. In this particular case, the gain is set to 4.1 to generate a 5.0 V output when the DAC is at full scale. If other output voltage ranges are needed, such as 0 V to 4.095 V, the gain can easily be adjusted by altering the value of the resistors.

A HIGH-SIDE CURRENT MONITOR

In the design of power supply control circuits, a great deal of design effort is focused on ensuring a pass transistor’s longterm reliability over a wide range of load current conditions.

As a result, monitoring and limiting device power dissipation is of prime importance in these designs. The circuit illustrated

in Figure 69 is an example of a 5 V, single-supply, high-side

current monitor that can be incorporated into the design of a voltage regulator with fold-back current limiting or a high current power supply with crowbar protection. This design uses an OP291 rail-to-rail input voltage range to sense the voltage drop across a 0.1 Ω current shunt. A p-channel MOSFET used as the feedback element in the circuit converts the op amp differential input voltage into a current. This current is then applied to R2 to generate a voltage that is a linear representation of the load current. The transfer equation for the current monitor is given by

Monitor Output

=

R

2

×

R

SENSE

R

1

×

I

L

For the element values shown, the monitor output transfer characteristic is 2.5 V/A.

R

SENSE

0.1Ω

5V

R1

100Ω

I

L

5V

3

8

1/2

OP291

2

4

1

5V

S

M1

3N163

MONITOR

OUTPUT

R2

2.49kΩ

D

G

Figure 69. A High-Side Load Current Monitor

Rev. E | Page 20 of 24

A 3 V, COLD JUNCTION COMPENSATED

THERMOCOUPLE AMPLIFIER

The OP291 low supply operation makes it ideal for 3 V batterypowered applications such as the thermocouple amplifier

shown in Figure 70. The K-type thermocouple terminates in an

isothermal block where the junction ambient temperature is continuously monitored using a simple 1N914 diode. The diode corrects the thermal EMF generated in the junctions by feeding a small voltage, scaled by the 1.5 MΩ and 475 Ω resistors, to the op amp.

To calibrate this circuit, immerse the thermocouple measuring junction in a 0°C ice bath and adjust the 500 Ω potentiometer to 0 V out. Next, immerse the thermocouple in a 250°C temperature bath or oven and adjust the scale adjust potentiometer for an output voltage of 2.50 V. Within this temperature range, the K-type thermocouple is accurate to within ±3°C without linearization.

1.235V

AD589

ISOTHERMAL

BLOCK

1N914

7.15kΩ

1%

10kΩ

3.0V

24.3kΩ

1%

SCALE

ADJUST

1.33MΩ 20kΩ

ALUMEL

AL

1.5MΩ

1%

24.9kΩ

1%

4.99kΩ

1%

2

8

1/2

OP291

V

OUT

CR

CHROMEL

COLD

JUNCTIONS

11.2mV

500Ω

10 TURN

ZERO

ADJUST

3

4

1

0V = 0°C

3V = 300°C

K-TYPE

THERMOCOUPLE

40.7μV/°C

475Ω

1%

2.1kΩ

1%

Figure 70. A 3 V, Cold Junction Compensated Thermocouple Amplifier

SINGLE-SUPPLY, DIRECT ACCESS ARRANGEMENT

FOR MODEMS

An important building block in modems is the telephone line

interface. In the circuit shown in Figure 71, a direct access

arrangement is used to transmit and receive data from the telephone line. Amplifier A1 is the receiving amplifier;

Amplifier A2 and Amplifier A3 are the transmitters. The fourth amplifier, A4, generates a pseudo ground halfway between the supply voltage and ground. This pseudo ground is needed for the ac-coupled bipolar input signals.

OP191/OP291/OP491

The transmit signal, TXA, is inverted by A2 and then reinverted by A3 to provide a differential drive to the transformer, where each amplifier supplies half the drive signal. This is needed because of the smaller swings associated with a single supply as opposed to a dual supply. Amplifier A1 provides some gain for the received signal, and it also removes the transmit signal present at the transformer from the received signal. To do this, the drive signal from A2 is also fed to the noninverting input of

A1 to cancel the transmit signal from the transformer.

390pF

RXA

0.1μF

TXA

0.1μF

20kΩ,1%

37.4kΩ

14

A1

1/4

OP491

13

12

0.0047μF

3.3kΩ

20kΩ,1%

20kΩ,1%

10

A2

1/4

OP491

9

8

37.4kΩ,1%

750pF

20kΩ,1%

20kΩ,1%

475Ω,1%

0.033μF

6

A3

1/4

OP491

5

7

3V OR 5V

5.1V TO 6.2V

ZENER 5

T1

1:1

1

A4

4

1/4

OP491

11

2

3

100kΩ

100kΩ

10μF 0.1μF

Figure 71. Single-Supply, Direct Access Arrangement for Modems

The OP491 bandwidth of 3 MHz and rail-to-rail output swings ensure that it can provide the largest possible drive to the transformer at the frequency of transmission.

Rev. E | Page 21 of 24

OP191/OP291/OP491

3 V, 50 HZ/60 HZ ACTIVE NOTCH FILTER WITH

FALSE GROUND

To process ac signals in a single-supply system, it is often best

to use a false ground biasing scheme. Figure 72 illustrates a

circuit that uses this approach. In this circuit, a false-ground circuit biases an active notch filter used to reject 50 Hz/60 Hz power line interference in portable patient monitoring equipment. Notch filters are quite commonly used to reject power line frequency interference that often obscures low frequency physiological signals, such as heart rates, blood pressure readings, EEGs, and EKGs. This notch filter effectively squelches 60 Hz pickup at a filter Q of 0.75. Substituting

3.16 kΩ resistors for the 2.67 kΩ resistors in the twin-T section

(R1 through R5) configures the active filter to reject 50 Hz interference.

R2

2.67kΩ

V

IN

3V

2

11

1/4

OP491

3

4

A1

1

R1

2.67kΩ

C1

1μF

R3

2.67kΩ

C2

1μF

R4

2.67kΩ

5

6

1/4

OP491

A2

7

V

OUT

R6

100kΩ

C3

2μF

(1μF × 2)

R5

1.33kΩ

(2.67kΩ ÷ 2)

R8

1kΩ

R7

1kΩ

R11

100kΩ

C5

C4

1μF

3V

R9

1MΩ

R10

1MΩ

9

1/4

OP491

10

0.01μF

A3

8

R12

499Ω

C6

1.5V

1μF

Figure 72. A 3 V Single-Supply, 50 Hz/60 Hz Active Notch Filter with False Ground

Amplifier A3 is the heart of the false ground bias circuit.

It buffers the voltage developed by R9 and R10 and is the reference for the active notch filter. Because the OP491 exhibits a rail-to-rail input common-mode range, R9 and R10 are chosen to split the 3 V supply symmetrically. An in-the-loop compensation scheme used around the OP491 allows the op amp to drive C6, a 1 μF capacitor, without oscillation. C6 maintains a low impedance ac ground over the operating frequency range of the filter.

The filter section uses a pair of OP491s in a twin-T configuration whose frequency selectivity is very sensitive to the relative matching of the capacitors and resistors in the twin-T section. Mylar is the material of choice for the capacitors, and the relative matching of the capacitors and resistors determines the pass band symmetry of the filter. Using

1% resistors and 5% capacitors produces satisfactory results.

SINGLE-SUPPLY, HALF-WAVE, AND FULL-WAVE

RECTIFIERS

An OPx91 device configured as a voltage follower operating on a single supply can be used as a simple half-wave rectifier in low frequency (<2 kHz) applications. A full-wave rectifier can be

configured with a pair of OP291s, as illustrated in Figure 73.

The circuit works in the following way. When the input signal is above 0 V, the output of Amplifier A1 follows the input signal.

Because the noninverting input of Amplifier A2 is connected to the output of A1, op amp loop control forces the inverting input of the A2 to the same potential. The result is that both terminals of R1 are equipotential; that is, no current flows. Because there is no current flow in R1, the same condition exists for R2; thus, the output of the circuit tracks the input signal. When the input signal is below 0 V, the output voltage of A1 is forced to 0 V.

This condition now forces A2 to operate as an inverting voltage follower because the noninverting terminal of A2 is also at 0 V.

The output voltage at V

OUT

A is then a full-wave rectified version of the input signal. If needed, a buffered, half-wave rectified version of the input signal is available at V

OUT

B.

R1

100kΩ

R2

100kΩ

V

IN

2V p-p

<2kHz

5V

2

3

8

1/2

OP291

4

A1

1

6

1/2

OP291

5

A2

7

V

OUT

A

FULL-WAVE

RECTIFIED

OUTPUT

V

OUT

B

HALF-WAVE

RECTIFIED

OUTPUT

V

IN

(1V/DIV)

100

90

1V 500mV

V

OUT

A

(0.5V/DIV)

V

OUT

B

(0.5V/DIV)

10

0%

500mV 200μs

TIME (200μs/DIV)

Figure 73. Single-Supply, Half-Wave, and Full-Wave Rectifiers

Using an OP291

Rev. E | Page 22 of 24

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

8

1

5

4

6.20 (0.2441)

5.80 (0.2284)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

SEATING

PLANE

1.27 (0.0500)

BSC

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

45°

1.27 (0.0500)

0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 74. 8-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-8) [S-Suffix]

Dimensions shown in millimeters and (inches)

8.75 (0.3445)

8.55 (0.3366)

4.00 (0.1575)

3.80 (0.1496)

14

1

8

7

6.20 (0.2441)

5.80 (0.2283)

OP191/OP291/OP491

0.25 (0.0098)

0.10 (0.0039)

COPLANARITY

0.10

1.27 (0.0500)

BSC

0.51 (0.0201)

0.31 (0.0122)

1.75 (0.0689)

1.35 (0.0531)

SEATING

PLANE

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0197)

0.25 (0.0098)

45°

1.27 (0.0500)

0.40 (0.0157)

COMPLIANT TO JEDEC STANDARDS MS-012-AB

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 75. 14-Lead Standard Small Outline Package [SOIC_N]

Narrow Body (R-14) [S-Suffix]

Dimensions shown in millimeters and (inches)

5.10

5.00

4.90

14

8

4.50

4.40

4.30

6.40

BSC

1

7

PIN 1

1.05

1.00

0.80

0.15

0.05

COPLANARITY

0.10

0.65 BSC

0.30

0.19

1.20

MAX

SEATING

PLANE

0.20

0.09

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 76. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

Rev. E | Page 23 of 24

0.75

0.60

0.45

ORDERING GUIDE

Model

1

OP191GS

OP191GS-REEL

OP191GS-REEL7

OP191GSZ

OP191GSZ-REEL

OP191GSZ-REEL7

OP291GS

OP291GS-REEL

OP291GS-REEL7

OP291GSZ

OP291GSZ-REEL

OP291GSZ-REEL7

OP491GP

OP491GPZ

OP491GRU-REEL

OP491GRUZ-REEL

OP491GS

OP491GS-REEL

OP491GS-REEL7

OP491GSZ

OP491GSZ-REEL

OP491GSZ-REEL7

1

Z = RoHS Compliant Part.

OP191/OP291/OP491

0.210 (5.33)

MAX

0.150 (3.81)

0.130 (3.30)

0.110 (2.79)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

14

1

0.775 (19.69)

0.750 (19.05)

0.735 (18.67)

8

7

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.100 (2.54)

BSC

0.070 (1.78)

0.050 (1.27)

0.045 (1.14)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.060 (1.52)

MAX

0.015

(0.38)

MIN

SEATING

PLANE

0.015 (0.38)

GAUGE

PLANE

0.005 (0.13)

MIN

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.430 (10.92)

MAX

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 77. 14-Lead Plastic Dual In-Line Package [PDIP]

(N-14)

[P-Suffix]

Dimensions shown in inche s and (millimeters)

Temperature Range

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

Package Description

8-Lead SOIC_N

8-Lead SOIC_N

8-Lead SOIC_N

8-Lead SOIC_N

8-Lead SOIC_N

8-Lead SOIC_N

8-Lead SOIC_N

8-Lead SOIC_N

8-Lead SOIC_N

8-Lead SOIC_N

8-Lead SOIC_N

8-Lead SOIC_N

14-Lead PDIP

14-Lead PDIP

14-Lead TSSOP

14-Lead TSSOP

14-Lead SOIC_N

14-Lead SOIC_N

14-Lead SOIC_N

14-Lead SOIC_N

14-Lead SOIC_N

14-Lead SOIC_N

Package Option

R-8 [S-Suffix]

R-8 [S-Suffix]

R-8 [S-Suffix]

R-8 [S-Suffix]

R-8 [S-Suffix]

R-8 [S-Suffix]

R-8 [S-Suffix]

R-8 [S-Suffix]

R-8 [S-Suffix]

R-8 [S-Suffix]

R-8 [S-Suffix]

R-8 [S-Suffix]

N-14 [P-Suffix]

N-14 [P-Suffix]

RU-14

RU-14

R-14 [S-Suffix]

R-14 [S-Suffix]

R-14 [S-Suffix]

R-14 [S-Suffix]

R-14 [S-Suffix]

R-14 [S-Suffix]

©1994–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D00294-0-4/10(E)

Rev. E | Page 24 of 24

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