DR. SAIBAL MUKHOPADHYAY ASSOCIATE PROFESSOR

DR. SAIBAL MUKHOPADHYAY ASSOCIATE PROFESSOR
DR. SAIBAL MUKHOPADHYAY
ASSOCIATE PROFESSOR
SCHOOL OF ELECTRICAL AND COMPUTER ENGINEERING, GEORGIA TECH
Website: http://www.ece.gatech.edu/research/labs/GREEN/
I.
EARNED DEGREES
PhD (August, 2006)
Electrical & Computer Engineering, Purdue University, West Lafayette, USA
B.E. (June, 2000)
Electronics & Telecommunication Engineering, Jadavpur University, India
II. EMPLOYMENT
July 2012-present
Associate Professor, Electrical & Computer Engineering,
Georgia Institute of Technology, Atlanta, GA
Sept. 2007-June 2012
Assistant Professor, Electrical & Computer Engineering,
Georgia Institute of Technology, Atlanta, GA
Sept. 2006-Sept. 2007
Research Staff Member, High Performance Circuit Design Dept.
IBM T. J. Watson Research Center, Yorktown Heights, NY
Aug. 2001-July 2006
Graduate Teaching and Research Assistant, Electrical & Computer Engineering,
Purdue University, West Lafayette, IN, USA
Summers: 2003, 2004,
and 2005
Technical Co-op, High Performance Circuit Design Dept.
IBM T. J. Watson Research Center, Yorktown Heights, NY
III. HONORS AND AWARDS
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Office of Naval Research (ONR) Young Investigator Award, 2012
ECE Outstanding Junior Faculty Member Award, 2012
Class of 1934 Course Survey Teaching Effectiveness Award, 2012
National Science Foundation CAREER Award, 2011.
IBM Faculty Award, 2010.
IBM Faculty Award, 2009.
Semiconductor Research Corporation (SRC) Inventor Recognition Award, 2008.
SRC Technical Excellence Award as a member of the Purdue Research Team, 2005.
IBM PhD Fellowship Award for 2004-2005.
Best in Session Award at TECHCON 2005.
The Best Paper Award in International Conference on Computer Design 2004.
The Best Student Paper Award in IEEE Nano 2003.
Dr. B. C. Roy Memorial Gold Medal for standing 1st among approx. 600 students in the Faculty of
Engineering & Technology, Jadavpur University, India, 2000.
1/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
IV. RESEARCH EXPERIENCE
The core agenda of my research group is to create a holistic approach to understand and explicitly manage
the interactions between delivery, consumption, and extraction of power to design energy-efficient and
reliable digital and mixed-signal integrated system. We primarily explore circuit level solutions and seek to
exploit their interactions with technology, system, packaging (3D), and algorithm. The target applications
are: (i) ultra-low-power (self-powered) environment adaptive wireless image sensor nodes, (ii)
mobile/embedded systems for multimedia applications, (iii) high-performance many-core processors, and
(iv) low power wireless electroencephalography (EEG).
Current Research Areas

Low-power techniques for digital and wireless mixed-signal systems
 Emerging technologies: Spin-Torque-Transfer RAM, Tunnel FET, FinFET, etc
 Low-power analog circuits and cellular neural network with steep subthreshold devices
 Adaptive digital logic circuits for ultra-low-voltage “zero-margin” operations
 Accuracy-aware µ-architecture for ultra-low-voltage operation
 Memory based computing: a platform for low-power reconfigurable systems
 Cross-layer real-time energy management for wireless image sensors

Power conversion and delivery for digital processors and low-power sensors
 Monolithic converters with line real-time control for optimal system level energy-efficiency
considering energy source, converter, and digital load
 Power regulators for energy harvesting: synchronous and asynchronous boost converters
 Power regulators for processors: hybrid converters, Single-Inductor Multiple-Output converters
 Exploiting emerging packaging technology (2.5D and 3D) for power conversion

Thermal characterization and management for high-performance and mobile systems
 Methods and circuits for post-silicon, on-line, and real-time thermal analysis
 On-demand cooling using thermoelectric devices

Exploring emerging packaging technology for energy-efficiency: heterogeneous 3D integration
 Physical interactions in 3D stack such as tier-to-tier thermal/noise coupling, TSV-device interactions
 Variation tolerant and adaptive 3D systems
 3D heterogeneous integration for: (i) 3D stack of logic and memory, (ii) asymmetric digital
processors with 3D stack of dies with different voltage/frequency; and (ii) 3D for real-time mixedsignal systems with sensors, memory, digital, and RF.
PhD Research
Dissertation: Designing Robust and Low-Leakage VLSI Circuits at the End of Silicon Roadmap: Technology
and Circuit Perspectives

Low-power and variation tolerant Static Random Access Memory
 Modeling and on-chip circuits for variation characterization
 Modeling of failure probability and design of robust (self-repairing) SRAM
 Technology-circuit co-design for SRAM in Fully-depleted SOI and FinFET technologies

Leakage modeling, analysis, and leakage reduction techniques
 Variability-aware modeling of leakage in bulk-CMOS and multi-gate devices
 Circuit techniques to reduce leakage considering subthreshold, gate, and junction leakage
2/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
V. GRANTS AND CONTRACTS
Twenty (20) Research Grants.~$5,720, 000 as PI or Co-PI; ~$3,800,000 is allocated to Mukhopadhyay
Sponsors: National Science Foundation, Office of Naval Research, Semiconductor Research Corporation,
Intel Corp, and IBM Faculty Award
 Current
1. S. Mukhopadhyay (PI), “OROEB: On-line Real-Time Optimal Energy Balancing for Self-Powered
Environment Adaptive Sensor Node,” Office of Naval Research; Fund (including GT Cost-share):
$690,000; Jan. 1, 2013 – Dec. 31, 2016.
2. S. Mukhopadhyay (PI), “CSR:SMALL: Exploiting 3D Integration for Power Management In Embedded
Processors,” National Science Foundation; Fund: $450,000; Aug. 1, 2012 – July 31, 2015
3. S. Mukhopadhyay (PI), “Distributed Power Delivery Architecture for 2D and 3D Integrated Circuits,”
Semiconductor Research Corp, Fund (including IPC cost-share): $255,832; Aug. 1, 2012 – July 31,
2015.
4. S. Yalamanchili (PI) and S. Mukhopadhyay (co-PI), “Exploration of Adaptive 3D Many-core
Architecture,” Semiconductor Research Corp, Fund: $255,000; Aug. 1, 2012 – July 31, 2015; Dr.
Mukhopadhyay’s share ~50%.
5. S. Yalamanchili (PI), M. Bakir (co-PI), S. Mukhopadhyay (co-PI) and Y. Joshi (co-PI); PowerArchitecture-Thermal Co-Design (PATCO) for Exascale Node Architectures, Sandia National Lab; Jan
1, 2012 – Dec. 31, 2015; Fund: $360,000. Dr. Mukhopadhyay’s share ~25%.
6. S. Mukhopadhyay (PI), “CAREER: 3D Heterogeneous Integration for Power Reduction in Embedded
Systems: Application to Wireless Image Sensing and Transport,” National Science Foundation, Fund
(NSF + GT Cost Share): $706,177; Feb. 1, 2011 – Jan. 31, 2016,
7. S. Mukhopadhyay (PI) and S. Lim (co-PI), “Design of 3D Heterogeneous Systems,” Semiconductor
Research Corp, Fund: $420,957; Mar. 1, 2011 – Feb. 28, 2014; Dr. Mukhopadhyay’s share ~50%.
8. S. Mukhopadhyay (PI), “Collaborative Research: Reconfigurable Computing Using 2D Nanoscale
Memory Array For Multimedia Signal Processing,” National Science Foundation, Fund: $174,198; July
1, 2010 – June 30, 2014.
9. S. Kumar (PI, ME) and S. Mukhopadhyay (co-PI), “Collaborative Research: Energy Efficient Thermal
Design of Heterogeneous System with Active Cooling,” National Science Foundation, Fund: $325,744.
Dr. Mukhopadhyay’s share: ~50%; Aug 15, 2010 – Aug. 14, 2013.
10. S. Mukhopadhyay (PI) and S. Yalamanchili (co-PI), “On-Line Coordinated Global Power And Thermal
Management For Many-Core Processors,” Semiconductor Research Corp, Fund: $330,000; Aug. 1,
2010 – July 31, 2013; Dr. Mukhopadhyay’s share ~55%.
11. K. Schwan (PI), H. Kim (co-PI), S. Mukhopadhyay (co-PI), H. Lee (co-PI), Y. Joshi (co-PI), “II-NEW:
GreenIT: Testbeds for Real-time Data Center and Platform Energy and Thermal Management,” National
Science Foundation, Jan. 1, 2010 – Dec. 31, 2013, amount $500,000, Dr. Mukhopadhyay’s share
~$125,000 (probe-station for power/thermal characterization).
12. S. Mukhopadhyay (PI) and W. Wolf (co-PI) “SHF:Small:A Generic Micro-Architecture for AccuracyAware Ultra Low Power Multimedia Processing,” National Science Foundation, Sept. 1, 2009 – Aug.
31, 2012, Fund: $485,638. Dr. Mukhopadhyay’s share ~50%.
13. S. Lim (PI) and S. Mukhopadhyay (co-PI) “SHF:Small:3D Integration of Sub-Threshold Multi-core Coprocessor for Ultra Lower Power Computing,” National Science Foundation, Sept. 15, 2009 – Aug. 31,
2012, Fund: $450,000, Dr. Mukhopadhyay’s share ~50%.
3/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
Industrial Gifts
14. S. Mukhopadhyay (PI), “Designing Many Processing Element Systems in Nanometer Era,” Intel Corp.,
Fund: $36,000 + 3 Dell PCs
15. S. Mukhopadhyay (PI), “3D Integrated Circuits,” Intel Corp, Fund: $25,000.
16. S. Mukhopadhyay (PI), “On-line Thernal Management of Many-Core Processors,” IBM Faculty Award,
2009, Fund: $25,000.
17. S. Mukhopadhyay (PI), “Thermal and Power Analysis and On-Line Management in 3D Systems” IBM
Faculty Award, 2010; Fund: $25,000.
18. S. Mukhopadhyay (PI), 5 Virtex-V FPGA board from Xilinx Corp. thorugh Xilinx University Program
(equivalent value ~ $9995).
 Completed
19. S. Mukhopadhyay (PI) and S. Yalamanchili (co-PI), “A System Driven Approach to Exploit the
Advantage of 3D – a project under IFC research program for "connectivity" in hyper-integrated
electronics,” Marco (Microelectronics Advanced Research Corp), July 1, 2010- Dec. 31, 2012; requested
amount $94,227, received amount $157,227. Dr. Mukhopadhyay’s share ~50%.
20. S. Mukhopadhyay (PI), “Design of Low-Power Wireless Electroencephalography,” SCEEE, July 1, 2010
– June 30, 2011, received amount $38,000.
VI. INDIVIDUAL STUDENT GUIDANCE
Graduated Students

PhD Thesis:
1. Dr. Francesco Barale1, Date of Graduation: Dec. 2010, Thesis Title: Design of Integrated
Frequency Synthesizers and Clock-Data Recovery Circuits for 60GHz Wireless
Communications; Current Affiliation: Silicon Laboratories, Austin, TX, USA
2. Dr. Jeremy Tolbert, Date of Graduation: August 2012, Thesis Title: Energy-Efficient
Digital Design of Reliable, Low-Throughput of Wireless Biomedical Systems; Current
Affiliation: Samsung Electronics, Austin, TX, USA
3. Dr. Subho Chatterjee, Date of Graduation: September 2012, Thesis Title: A Design
Methodology for Robust, Energy-Efficient, Application-Aware Memory Systems; Current
Affiliation: Intel Corp., Hilsboro, OR, USA
4. Dr. Minki Cho, Date of Graduation: September 2012, Thesis Title: Design Methodology To
Characterize And Compensate For Process And Temperature Variation In Digital Systems;
Current Affiliation: Intel Corp., Hilsboro, OR, USA
5. Dr. Kwanyeob Chae, Date of Graduation: August 2013, Thesis Title: Design
Methodologies for Robust Low-Power Digital Systems Under Static and Dynamic
Variations; Current Affiliation: Samsung Electronics, Korea,

MS Thesis:
1. Mr. Nikhil Sathe, Date of Graduation: Aug, 2010; Thesis Title: Thermal Modeling in ManyCore Processors; Current Affiliation: Advanced Micro Devices
2. Mr. Muneeb Zia, Date of Graduation: May, 2013; Thesis Title: SRAM System Design For
Memory Based Computing
3. Mr. Prashant Nair, Date of Graduation: May, 2013; Thesis Title: Designing Low Power
SRAM System Using Energy Compression
4/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
Current PhD Students
No
Student
Expected
Graduation
Topic
1
Amit Trivedi
August 2014
Technology-Circuit Co-design: 3D/FinFET/TFET
2
Denny Lie
August 2014
3D Integration – Image sensor
3
Boris Alexandrov
August 2014
On-demand Cooling with Thermoelectric
4
Wen Yueh
August 2015
3D Integration – High-performance processors
5
Khondker Z. Ahmed
August 2015
Power conversion and power management
6
Sergio Carlo
August 2016
Power conversion and power management
7
Jae Ha Kung
August 2016
Thermal management
8
Monodeep Kar
August 2016
Power conversion and power management
9
Duckhwan Kim
August 2017
3D systems
10
Jong Hwan Ko
August 2017
Low-power design
11
Mohammed F. Amir
August 2017
Low-power design
Student
Expected
Graduation
Topic
1
Krishna Yeleswarapu
May 2013
3D Integration – Interaction of Device and TSVs
2
Swarrnna Parthasarathy
Dec. 2013
Thermoelectrinc devices
Current MS Students
No
Undergraduate Students – Georgia Tech
No
Student
Semester
Topic
1
Anurag Kadasne
Fall 2009 and Spring 2010
Many-core Thermal Management
2
Andrew Burks
Spring 2010
Energy-efficient Wireless EEG system
3
Erik Ronshagen
Fall 2010 and Spring 2011
Thermal Management
4
Samrat Sinharoy
Fall 2012
Low-swing 3D interconnect
5
Chawit Uswachoke
Fall 2012
Low-swing 3D interconnect
6
Daniel Besse
Spring 2013
Tunnel FET
Undergraduate Students – Summer Undergraduate Research Experience (SURE)
No
Student
Semester
Topic
1
Abner Ayalaa
Summer 2010
Wireless Image Transmission: MATLAB Model
2
Erica Nwankwo
Summer 2011
MATLAB based Wireless Channel Simulation
3
Leishla Z Ramos Rivera
Summer 2012
Image Processing-Unit for A Wireless Sensor Node
5/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
VII.
SCHOLARLY ACOMPLISHMENTS
A.
PUBLISHED BOOKS AND PARTS OF BOOKS
1.
Book Chapter: A. Agarwal, S. Mukhopadhyay, C. H. Kim, A. Raychowdhury, and K. Roy, “Leakage
power analysis and reduction for nano-scale circuits,” in System-on-Chip: Next Generation
Electronics, Edited by Bashir M. Al-Hashimi, IET, May 2006, pp. 415-444.
Book Editing: “Low-power Variation-Tolerant Design in Nanometer Silicon” Co-edited by S.
Bhunia and S. Mukhopadhyay, Springer, published Nov. 2010.
2.
B.
REFEREED PUBLICATIONS
*Boldface font is used to identify co-authors who were students being advised by Prof. Mukhopadhyay.
*Citation counts are obtained from Google Scholar search, February. 2013.
Journal Publications

D. Lie, K. Chae, and S. Mukhopadhyay, “Low-Power Image Compression using 3D Integration of
Memory and Signal Processing Units”, submitted to IEEE Transactions on Components, Packaging,
and Manufacturing Technologies (TCPMT).

K. Chae, and S. Mukhopadhyay, “Resilient Pipeline under Supply Noise with Programmable-TimeBorrowing and Delayed-Clock-Gating”, submitted to IEEE Transactions on Circuits and Systems – II
(TCAS-II).

K. Z. Ahmed, and S. Mukhopadhyay, “A wide conversion ratio, extended input 3.5µA Boost Regulator
with 82% Efficiency for Low Voltage Energy Harvesting,” submitted to IEEE Transactions on Power
Electronics. Recommended for publication with mandatory revisions.
 2013
1. M. Cho, C. Kersey, M. P. Gupta, N. Sathe, S. Kumar, S. Yalamanchili, and S. Mukhopadhyay, “Power
Multiplexing for Thermal Field Management in Many Core Processors,” IEEE Transactions on
Components, Packaging, and Manufacturing Technologies (TCPMT), vol. 3, no. 1, January 2013, pp.
94-104.
2. M. Redmond, K. Manickaraj, O. Sullivan, S. Mukhopadhyay, and S. Kumar, “Hotspot Cooling in
Stacked Chips using Thermoelectric Coolers,” IEEE Transactions on Components, Packaging, and
Manufacturing Technologies (TCPMT), vol.3, no.5, May 2013, pp.759-767,
3. W. Yueh, S. Chatterjee, A. Trivedi, and S. Mukhopadhyay, “Performance and Robustness of 3D
Integrated SRAM Considering Tier-to-tier Thermal and Supply Cross-talk,” IEEE Transactions on
Components, Packaging, and Manufacturing Technologies (TCPMT), vol. 3, no.6, June 2013, , pp. 943953.
4. S. Chatterjee, S. Salahuddin, S. Kumar, and S. Mukhopadhyay, “Electro-Thermal Analysis of SpinTorque-Transfer Random Access Memory Arrays,” ACM Journal on Emerging Technologies in
Computing Systems (JETC), Vol. 9, No. 2, May 2013.
5. O. Sullivan, B. Alexandrov, S. Mukhopadhyay, and S. Kumar, “3D Compact Model of Packaged
Thermoelectric Coolers,” ASME Journal of Electronic Packaging (JEP), vol. 135, no. 3, Jun 24, 2013.
6/23
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Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
6. K. Chae, X. Zhao, S. Lim, and S. Mukhopadhyay, “Tier-Adaptive-Body-Biasing: A Post-Silicon Tuning
Method to Minimize Clock Skew Variations in 3D ICs,” accepted for publication in IEEE Transactions
on Components, Packaging, and Manufacturing Technologies (TCPMT). Letter of acceptance received
on December 17, 2012.
7. K. Chae and S. Mukhopadhyay, “A Dynamic Timing Error Prevention Technique with Time Borrowing
and Clock Stretching to Widen Operating Range of Pipelines”, accepted for publication in IEEE
Transaction of Circuits and Systems (TCAS-I).
8. M. Cho, K. Z. Ahmed, W. Song, S. Yalamanchili, and S. Mukhopadhyay, “Methods and Circuits for
Post-Silicon Characterization and Prediction of Transient Thermal Field in Integrated Circuits,” accepted
for publication in IEEE Transactions on Components, Packaging, and Manufacturing Technologies
(TCPMT). Letter of acceptance received on June 17, 2013
9. B. Alexandrov, O. Sullivan, W. Song, S. Yalamanchili, S. Kumar, and S. Mukhopadhyay, “Control
Principles and On-chip Circuits for Active Cooling using Integrated Super Lattice Based Thin-Film
Thermoelectric Devices”, accepted for publication in IEEE Transactions on VLSI Systems (TVLSI).
Letter of acceptance received on July 25, 2013
 2012
10. J. Tolbert, P. Kabali, S. Brar, and S. Mukhopadhyay, “Designing for Accuracy and Energy Efficiency
in Wireless Encephalography Systems,” ACM Journal on Emerging Technologies in Computing Systems
(JETC), vol. 8, no. 1, February 2012, pp. 1-21.
11. M. P. Gupta, M. Cho, S. Mukhopadhyay, and S. Kumar, “Thermal Investigation into Power
Multiplexing for Homogeneous Many-Core Processors,” ASME Journal of Heat Transfer, vol. 134, No.
6, June 2012.
12. S. Chatterjee, S. Salahuddin, S. Kumar, and S. Mukhopadhyay, “Impact of Self-Heating on Reliability
of Spin-Torque-Transfer RAM Cell,” IEEE Transactions on Electron Devices (TED), Vol. 59, No. 3,
March 2012, pp. 791-799.
13. O. Sullivan, M. P. Gupta, S. Mukhopadhyay, and S. Kumar, “Array of Thermoelectric Coolers for On
chip Thermal Management ASME Journal of Electronic Packaging. Vol. 134, no. 2, 2012.
14. X. Zhao, J. R. Tolbert, C. Liu, S. Mukhopadhyay, and S. K. Lim, “Variation-aware Clock Network
Design Methodology for Ultra-Low Voltage (ULV) Circuits”, IEEE Transactions on Computer Aided
Design of Integrated Circuits and Systems (TCAD), vol. 31, no. 8, August 2012, pp. 1222-1234..
15. S. Narasimha, W. Yueh, X. Wang, S. Mukhopadhyay, and S. Bhunia, “Improving IC Security against
Trojan Attacks through Integration of Security Monitors”, IEEE Design and Test of Computers (IEEE
D&T), vol. 29, no. 5, October 2012, pp. 37-46.
16. K. Chae, and S. Mukhopadhyay, “All-Digital Adaptive Clocking to Tolerate Transient Supply Noise in
Low Voltage Operation,” IEEE Transaction on Circuits and Systems-II: Express Briefs (TCAS-II), vol.
59, no. 2, December 2012, pp. 893 - 897.
 2011
17. S. Mukhopadhyay, R. Rao, J.J. Kim, and C. T. Chuang, “SRAM Write-ability Improvement with
Transient Negative Bit-line Voltage,” IEEE Transactions on VLSI Systems (TVLSI), vol. 19, no. 1, Jan.
2011, pp. 24-32.
7/23
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Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
18. M. Cho, J. Schlessman, W. Wolf, and S. Mukhopadhyay, “Reconfigurable SRAM Architecture with
Spatial Voltage Scaling for Low Power Mobile Multimedia Applications,” IEEE Transactions on VLSI
Systems (TVLSI), vol. 19, no. 1, Jan. 2011, pp. 161-165.
19. D. H. Kim, S. Mukhopadhyay, and S. K. Lim, “Fast and Accurate Analytical Modeling of ThroughSilicon-Via Capacitive Coupling,” IEEE Transactions on Components, Packaging, and Manufacturing
Technology (TCPMT), vol. 1, no. 2, Feb. 2011, pp. 168-180.
20. S. Chatterjee, M. Rasquinha, S. Yalamanchili, and S. Mukhopadhyay, “A Scalable Design Methodology
for Energy Minimization of STTRAM: A Circuit and Architecture Perspective,” IEEE Transactions on
VLSI Systems (TVLSI), vol. 19, no. 5, May 2011, pp. 809-817.
21. S. Paul, S. Mukhopadhyay, and S. Bhunia, “Circuit and Architecture Co-design Approach for Hybrid
CMOS-STTRAM non-volatile FPGA,” IEEE Transactions on Nanotechnology (TNANO), vol. 10, no. 3,
May 2011, pp. 385-394.
22. S. Kim, S. Mukhopadhyay, and M. Wolf, “Modeling and Analysis of Image Dependence on Energy
Saving for Error Tolerant Image Processing,” IEEE Transaction on Computer Aided Design (TCAD),
vol. 30, no. 8, Aug. 2011, pp. 1163-1172.
23. A. R. Trivedi and S. Mukhopadhyay, “Through-Oxide-Via Induced Back Gate Effect in 3D Integrated
FDSOI Devices,” IEEE Electron Device Letters (EDL), vol. 32, no. 8, Aug. 2011, pp. 1020-1022.
24. J. R. Tolbert, X. Zhao, S. K. Lim, and S. Mukhopadhyay, “Analysis and Design of Energy and Slew
Aware Subthreshold Clock Systems,” IEEE Transaction on Computer Aided Design (TCAD), vol. 30,
no. 9, Sept. 2011, pp. 1348-1358.
25. M. Gupta, M. Sayer, S. Mukhopadhyay, and S. Kumar, "Ultrathin Thermoelectric Devices For On-Chip
Peltier Cooling", Accepted for publications in IEEE Transactions on Components, Packaging, and
Manufacturing Technologies (TCPMT), vol. 30, no. 9, Sept. 2011, pp. 1395-1405.
26. M. Cho, C. Liu, D. H. Kim, S. K. Lim, and S. Mukhopadhyay, “Pre-bond and Post-bond Test and Signal
Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3D System,”
IEEE Transactions on Components, Packaging and Manufacturing (TCPMT), vol. 1, no. 11, Nov. 2011,
pp. 1718-1727.
27. S. Paul, S. Chatterjee, S. Mukhopadhyay, and S. Bhunia, “Energy-Efficient Reconfigurable Computing
Using a Circuit-Architecture-Software Co-Design Approach,” IEEE Journal on Emerging and Selected
Topics in Circuits and Systems (JETCAS). vol. 1, no. 3, Sept. 2011, pp. 369-380.
28. S. Paul, S. Mukhopadhyay, S. Bhunia, “A Variation-Aware Preferential Design Approach for Memory
Based Reconfigurable Computing,” accepted for publication in IEEE Transactions on VLSI (TVLSI).
Letter of acceptance received on Feb. 26, 2011.
 2010
29. N. N. Mojumder, S. Mukhopadhyay, J. J. Kim, C. T. Chuang, and K. Roy, “Self-Repairing SRAM using
On-Chip Detection and Compensation,” IEEE Transactions on VLSI Systems (TVLSI), vol. 18, no. 1, Jan
2010, pp. 75-84.
30. S. Chatterjee, S. Salahuddin, and S. Mukhopadhyay, “Dual Source-Line-Bias Scheme to Improve Read
Margin and Sensing Accuracy of STTRAM in sub-90nm Nodes,” IEEE Transactions on Circuits and
Systems- II (TCAS-II), vol. 57, no. 3, Mar 2010, pp. 208-212.
8/23
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Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
31. S. Kim, S. Mukhopadhyay, and M. Wolf, “System Level Energy Optimization for Error tolerant Image
Compression,” IEEE Embedded System Letters (ESL), vol. 2, no. 3, Sept. 2010, pp. 81–84.
32. M. Cho, J. Schlessman, H. Mahmoodi, M. Wolf, and S. Mukhopadhyay, “Postsilicon Adaptation for
Low-Power SRAM under Process Variation,” IEEE Design and Test of Computers (D&T), vol. 27, no.
6, Nov.-Dec. 2010, pp. 26–35.
 2009
33. R. Joshi, S. Mukhopadhyay, D. W. Plass, Y. H. Chan, C. T. Chuang, and Y. Tan “Design of sub-90nm
Low power and Variation tolerant PDSOI SRAM cell based on dynamic stability metrics,” IEEE Journal
of Solid State Circuits (JSSC), vol. 44, no. 3, Mar. 2009, pp. 965-976.
34. S. Mukhopadhyay, “A Generic Data-Driven Non-Parametric Framework for Variability Analysis of
Integrated Circuits in Nanometer Technologies,” IEEE Transactions on Computer Aided Design of
Integrated Circuits and Systems (TCAD), vol. 28, no. 7, July 2009, pp. 1038-1046.
 2008
35. S. Mukhopadhyay, K. Kim, and C. T Chuang, “Device Design and Optimization Methodology for
Leakage and Variability Reduction in sub-50nm FD/SOI SRAM,” IEEE Transactions on Electron
Devices (TED), vol. 55, no. 1, Jan. 2008, pp. 152-162. Considered for IEEE Electron Device Society’s
2008 Paul Rappaport Award given to the best paper in IEEE TED – selected as top 1% of all papers
submitted to TED in 2008.
36. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Reduction of Parametric Failures in Sub-100nm SRAM
Array using Body Bias,” IEEE Transactions on Computer Aided Design of Integrated Circuits and
Systems (TCAD), vol. 21, no. 1, Jan. 2008, pp. 174-183 (Top 20 downloaded article in TCAD in 2008).
37. A. Bansal, K. Kim, J. J. Kim, S. Mukhopadhyay, C. T. Chuang, and K. Roy, “Optimal Dual-VT Design
in Sub-100 Nanometer PD/SOI and Double-Gate Technologies,” IEEE Transactions on Electron
Devices (TED), vol. 55, no. 5, May 2008, pp. 1161-1169 .
38. A. Datta, S. Bhunia, J. H. Choi, S. Mukhopadhyay, and K. Roy, “Profit Aware Circuit Design under
Process Variations Considering Speed Binning,” IEEE Transactions on VLSI System (TVLSI), vol. 16,
no. 7, July 2008, pp. 806-815.
39. S. Mukhopadhyay, K. Kim, K. A. Jenkins, C. T. Chuang, and K. Roy, “An On-chip Test Structure and
Digital Measurement Method for Statistical Characterization of Local Random Variability in a Process,”
IEEE Journal of Solid State Circuits (JSSC), vol. 43, no. 9, Sept. 2008, pp. 1951–1963.
 2007
40. A. Bansal, S. Mukhopadhyay, and K. Roy, “Device-optimization Technique for Robust and Low-Power
FinFET SRAM Design in NanoScale Era,” IEEE Transactions on Electron Devices (TED), vol. 54, no.
6, June 2007, pp. 1409-1419.
41. S. Mukhopadhyay, K. Kim, H. Mahmoodi, and K. Roy, “Design of A Process Variation Tolerant SelfRepairing SRAM for Yield Enhancement in Nano-scaled CMOS,” IEEE Journal of Solid-State Circuits
(JSSC), vol. 42, no. 6, June 2007, pp. 1370–1382 (citations 49).
42. S. Mukhopadhyay, K. Kim, J. J. Kim, S. Lo, R. Joshi, C. T. Chuang, and K. Roy, “Modeling and
Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits,”
Microelectronics Journal, vol. 38, no. 8-9, Aug.-Sept. 2007. pp. 931-941.
9/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
 2006
43. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Design of High Performance Sense Amplifier Using
Independent Gate Control in Fully Depleted Double-Gate MOSFET,” IEEE Transactions on VLSI
Systems (TVLSI), vol. 14, no. 2, Mar. 2006, pp. 183-192.
44. A. Agarwal, S. Mukhopadhyay, A. Raychowdhury, K. Roy, and C. H. Kim, “Leakage Power Analysis
and Reduction for Nanoscale Circuits,” IEEE Micro, vol. 26, no. 2, Mar.-Apr. 2006, pp. 68-80 (citations
49).
45. S. Mukhopadhyay, K. Kim, X. Wang, D. J. Frank, P. Oldiges, C. T. Chuang, and K. Roy, “Optimal
Ultra-Thin Body FD/SOI Device Structure using Thin-BOX for sub-50 nm SRAM Design,” IEEE
Electron Device Letters (EDL), vol. 27, no. 4, April 2006, pp. 284-287.
46. S. Mukhopadhyay, S. Bhunia, and K. Roy, “Modeling and Analysis of Loading Effect in Leakage of
Nano-Scaled Bulk-CMOS Logic Circuits,” IEEE Transactions on Computer Aided Design of Integrated
Circuits and Systems (TCAD), vol. 25, no. 8, Aug. 2006, pp. 1486-1495.
47. S. Mukhopadhyay, K. Kim, C. T. Chuang, and K. Roy, “Modeling and Analysis of Leakage Currents in
Double-Gate Technologies,” IEEE Transactions on Computer Aided Design of Integrated Circuits and
Systems (TCAD), vol. 25, no. 10, Oct. 2006, pp. 2052-2061.
48. A. Datta, S. Bhunia, S. Mukhopadhyay, and, K. Roy, “Delay Modeling and Statistical Design of
Pipelined Circuit Under Process Variation,” IEEE Transactions on Computer Aided Design of Integrated
Circuits and Systems (TCAD), vol. 25, no. 11, Nov. 2006, pp. 2427-2436.
 2005
49. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, “Accurate estimation of total leakage in nanometer
scale bulk-CMOS circuits based on device geometry and doping profile,” IEEE Transactions on
Computer Aided Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 3, Feb. 2005, pp. 363381. One of the Top 20 downloaded papers in 2005 in TCAD (citations 63).
50. C. H. Kim, J. J. Kim, S. Mukhopadhyay, and K. Roy, “A Forward Body-Biased Low-Leakage SRAM
Cache: Device and Architecture Considerations,” IEEE Transactions on VLSI Systems (TVLSI), vol. 13,
no. 3, Mar. 2005, pp. 349-357.
51. S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, and K. Roy, “Low-Power Scan Design Using
First Level Supply Gating,” IEEE Transactions on VLSI Systems (TVLSI), vol. 13, no. 3, Mar. 2005, pp.
384- 395 (citations 53).
52. A. Agarwal, S. Mukhopadhyay, C. H. Kim, A. Raychowdhury, and K. Roy, “Leakage Power Analysis
and Reduction: Models, Estimation and Tools,” IEE Proceedings - Computers and Digital Techniques,
vol. 152, no. 3, May 2005, pp. 353-368 (citations 25).
53. A. Agarwal, B. Paul, S. Mukhopadhyay, and K. Roy, “Process Variation in Embedded Memories: Failure
Analysis and Process Tolerant Architecture,” IEEE Journal of Solid State Circuits (JSSC), vol. 40, no. 9,
Sept. 2005, pp. 1804-1814 (citations 100).
54. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “Estimation of Delay Variation Due to Random Dopant
Fluctuations in Nano-scale CMOS Circuits,” IEEE Journal of Solid State Circuits (JSSC), vol. 40, no. 9,
Sept. 2005, pp. 1787-1796 (citations 89).
55. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Modeling of Failure Probability and Statistical Design of
SRAM Array for Yield Enhancement in Nano-Scaled CMOS,” IEEE Transactions on Computer Aided
10/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
Design of Integrated Circuits and Systems (TCAD), vol. 24, no. 12, Dec. 2005, pp. 1859-1880 (citations
223, Top 20 downloaded article in TCAD in 2008, 2009).
 2004
56. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “A circuit-compatible model of ballistic carbon
nanotube field-effect transistors,” IEEE Transactions on Computer Aided Design of Integrated Circuits
and Systems (TCAD), vol. 23, no. 10, Oct. 2004, pp. 1410-1420. One of the Top 20 downloaded papers
in 2004 in TCAD (citations 117).
 2003
57. K. Roy, S. Mukhopadhyay, and H. Mahmoodi, “Leakage current mechanisms and leakage reduction
techniques in deep-submicron CMOS circuits,” Proceeding of IEEE, vol. 91, no. 2, Feb. 2003, pp. 307327 (citations 1060).
58. S. Mukhopadhyay, C. Neau, T. Cakici, A. Agarwal, C. H. Kim, and K. Roy, “Gate leakage reduction for
scaled devices using transistor stacking,” IEEE Transactions on VLSI Systems (TVLSI), vol. 11, no. 4,
Aug. 2003, pp. 716-730 (citations 94).
 2002
59. K. Roy, S. Mukhopadhyay, and H. Mahmoodi, “Leakage Current in Deep-Submicron CMOS Circuits,”
Journal of Circuits, Systems and Computers, vol. 11, no. 6, Dec. 2002, pp. 575-600.
Conference Publications
 2013
1.
W. Yueh, M. Cho and S. Mukhopadhyay, “Perceptual Quality Preserving SRAM Architecture for
Color Motion Pictures” IEEE Design, Automation, and Test in Europe (DATE), 2013.
2.
X. Wang, W. Yueh, S. Mukhopadhyay, D. Basu Roy, D. Mukhopadhyay, S. Narasimhan, Y. Sheng,
and S. Bhunia, “Role of Power Grid in Side Channel Attack and Power-Grid-Aware Secure Design,”
Design Automation Conference (DAC), 2013.
3.
A. Trivedi, S. Carlo, and S. Mukhopadhyay, “Exploring Tunnel-FET for Ultra Low Power Analog
Applications: A Case Study on Operational Transconductance Amplifier,” Design Automation
Conference (DAC), 2013.
4.
S. Carlo, W. Yueh, and S. Mukhopadhyay, “On the Potential of 3D Integration of Inductive DC-DC
Converter for High-Performance Power Delivery,” Design Automation Conference (DAC), 2013.
5.
D. Lie, K. Chae, and S. Mukhopadhyay, “On the Impact of 3D Integration on High-Throughput Sensor
Information Processing: A Case Study with Image Sensing,” NANOARCH, 2013.
6.
K. Z. Ahmed and S. Mukhopadhyay, “A 110nA Synchronous Boost Regulator with Autonomous Bias
Gating for Energy Harvesting,” IEEE Custom Integrated Circuits Conference (CICC), 2013.
7.
M. Wolf and S. Mukhopadhyay, “Physics of Computing as an Introduction to Computer Engineering,”
IEEE Frontiers of Education (FIE), 2013.
11/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
 2012
8.
B. Alexandrov, O. Sullivan, S. Kumar, and S. Mukhopadhyay, “Prospects of Active Cooling with
Integrated Super-Lattice based Thin-Film Thermoelectric Devices for Mitigating Hotspot Challenges in
Microprocessors,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Jan.
2012.
9.
K. Chae and S. Mukhopadhyay, “Tier-Adaptive-Voltage-Scaling (TAVS): A Methodology for PostSilicon Tuning of 3D ICs,” IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2012.
10. S. Chatterjee, M. Cho, R. Rao, and S. Mukhopadhyay, “Impact of Die-to-Die Thermal Coupling on the
Electrical Characteristics of 3D Stacked SRAM Cache,” IEEE Semi-Therm, Feb. 2012.
11. M. Cho, W. Song, S. Yalamanchili, and S. Mukhopadhyay, “Thermal System Identification (TSI): A
Methodology for Post-silicon Characterization and Prediction of the Transient Thermal Field in
Multicore Chips,” IEEE Semi-Therm, Feb. 2012.
12. A. Trivedi and S. Mukhopadhyay, “Self-Adaptive Power Gating with Test Circuit for On-line
Characterization of Energy Inflection Activity,” IEEE VLSI Test Symposium (VTS), April 2012.
13. W. Yueh, S. Chatterjee, A. Trivedi, and S. Mukhopadhyay, “On the Parameteric Failures of SRAM in a
3D-die Stack considering Tier-to-Tier Supply Cross-talk,” IEEE VLSI Test Symposium (VTS), April
2012.
14. W. Song, S. Yalamanchili, S. Mukhopadhyay, and A. Rodrigues, “Instruction-based Energy Estimation
Methodology for Asymmetric Manycore Processor Simulations,” SIMUTools 2012.
15. (Invited) M. Cho, K. Chae, and S. Mukhopadhyay, “Low-Power Design under Variation using Error
Prevention and Error Tolerance,” IEEE Latin American Test Workshop (LATW), April 2012.
16. M. Cho, M. Khellah, K. Chae, K. Ahmed, J. Tschanz, and S. Mukhopadhyay, “Characterization of
Inverse Temperature Dependence in Logic Circuits,” IEEE Custom Integrated Circuits Conference
(CICC), September 2012.
17. A. Trivedi and S. Mukhopadhyay, “Self Adaptive Power-Gating Scheme by On-Line Characterization
of Energy Inflection Activity,” SRC TECHCON, September 2012.
18. K. Chae, X. Zhao, A. R. Trivedi, S. Lim, and S. Mukhopadhyay, “Post-Silicon Tuning Method for
Clock Networks to Minimize Clock Skews in 3D ICs,” SRC TECHCON, September 2012.
 2011
19. J. J. Kim, B. P. Linder, R. M. Rao, T. H. Kim, P. F. Lu, K. A Jenkins, C. H. Kim, A. Bansal, S.
Mukhopadhyay, and C. T. Chuang, “Reliability Monitoring Ring Oscillator Structures for
Isolated/Combined NBTI and PBTI Measurement in High-K Metal Gate Technologies,” International
Reliability Physics Symposium (IRPS), April 2011, pp. 2B.4.1 - 2B.4.4.
20. (INVITED) K. Chae, C. H. Lee, and S. Mukhopadhyay, “Timing error prevention using elastic
clocking,” IEEE International Conference on IC Design and Technology (ICICDT), May 2011, pp. 1-4.
21. X. Zhao, S. Mukhopadhyay, and S. K. Lim, “Variation-Tolerant and Low-Power Clock Network Design
for 3D ICs,” Electronic Components and Technology Conference (ECTC), May-June 2011.
12/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
22. M. P. Gupta, M. Cho, S. Mukhopadhyay, and S. Kumar, “An Investigation into Power Migration Policies
for Many-Core Processors to Manage On-chip Thermal Profile,” to be presented in The ASME 2011
Pacific Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic
Systems, MEMS, and NEMS (InterPACK2011), July 2011.
23. X. Zhao, J. Tolbert, S. Mukhopadhyay, and S. K. Lim, “Variation-aware Clock Network Design
Methodology for Ultra-Low Voltage (ULV) Circuits,” International Symposium on Low-power
Electronic Design (ISLPED), Aug. 2011.
24. K. Chae, M. Rasquinha, S. M. Hasan, S. Yalamanchili, and S. Mukhopadhyay, “Statistical Analysis of
the Effect of Network on Performance of Many-Core Platform with 3D-Stacked DRAM,” SRC
TECHCON, Sept. 2011.
25. M. Cho, W. Song, S. Yalamanchili, and S. Mukhopadhyay, “Modeling of the Thermal Field of ManyCore System using Frequency Domain System Identification,” SRC TECHCON, Sept.2011.
26. W. J. Song, M. Cho, S. Yalamanchili, S. Mukhopadhyay, and A. F. Rodrigues “Energy Introspector:
Simulation Infrastructure for Power, Temperature, and Reliability Modeling in Manycore Processors,”
SRC TECHCON, Sept. 2011.
27. M. Rasquinha, S. M. Hassan, W. Song, K. Chae, M. Cho, S. Mukhopadhyay, and S. Yalamanchili,
“System Impact of 3D Processor-Memory Interconnect: A Limit Study,” SRC TECHCON, Sept. 2011.
28. J. Tolbert and S. Mukhopadhyay, “Modeling and Designing for Energy Efficiency in Wireless EEG
Systems” IEEE Sub-threshold Microelectronics Conference (IEEE SubVt), Sept. 2011.
29. S. Kim, S. Mukhopadhyay, H. Kim, and M. Wolf, “Low Energy Process Variation Tolerant Digital
Image Processing System Design Based On Accuracy-Energy Tradeoffs,” IEEE Workshop in Signal
Processing System (SiPS), Oct. 2011.
30. O. Sullivan, B. Alexandrov, S. Mukhopadhyay, and S. Kumar, “Compact Model of Thermoelectric
Coolers on a Micro-electronic Chip,” to be presented in ASME International Mechanical Engineering
Congress & Exposition (IMECE), Nov. 2011.
31. A. Trivedi, W. Yueh, and S. Mukhopadhyay, “Impact of Through-Silicon-Via Capacitance on High
Frequency Supply Noise in 3D-Stacks,” IEEE Electrical Performance of Electronic Packaging and
Systems (EPEPS), Oct. 2011.
 2010
32. M. Cho, N. Sathe, M. Gupta, S. Kumar, S. Yalamanchili and S. Mukhopadhyay, “Proactive Power
Migration to Reduce Maximum Value and Spatiotemporal Non-uniformity of On-chip Temperature
Distribution in Homogeneous Many-Core Processors,” IEEE Semi-Therm, Feb. 2010, pp. 180-186.
33. M. Cho and S. Mukhopadhyay, “Signal Processing Methods and Hardware-Structure for On-line
Characterization of Thermal Gradients in Many-Core Processors,” IEEE International Symposium in
Quality Electronic Design (ISQED), March 2010. pp. 797-803
34. J. Tolbert, P. Kabali, S. Brar, and S. Mukhopadhyay, “A Low Power System with Adaptive Data
Compression for Wireless Monitoring of Physiological Signals and its Application to Wireless
Electroencephalography,” IEEE International Symposium in Quality Electronic Design, March 2010.
pp. 333-341.
13/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
35. M. P. Gupta, M. H. S. Sayer, S. Mukopadhyay, and S. Kumar, “On-Chip Peltier Cooling Using Current
Pulse,” IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic
Systems (Itherm), June 2010, pp. 1 – 7.
36. M. P. Gupta, M. Cho, S. Mukopadhyay, and S. Kumar, “Thermal Management of Multicore Processors
Using Power Multiplexing,” IEEE Intersociety Conference on Thermal and Thermomechanical
Phenomena in Electronic Systems (Itherm), June 2010, pp. 1-7.
37. M. Rasquinha, D. Choudhary, S. Chatterjee, S. Mukhopadhyay, S. Yalamanachili, “An Energy Efficient
Cache Design Using Spin Torque Transfer (STT) RAM,” International Symposium on Low-Power
Electronic Design (ISLPED), August 2010, pp. 389-394.
38. S. Chatterjee, S. Salahuddin, S. Kumar, and S. Mukhopadhyay, “Analysis of Thermal Behaviors of
Spin-Torque-Transfer RAM: A Simulation Study,” International Symposium on Low-Power Electronic
Design (ISLPED), August 2010, pp. 13-18.
39. K. Chae, S. Mukhopadhyay, C. H. Lee, and J. Laskar, “A Dynamic Timing Control Technique Utilizing
Time Borrowing and Clock Stretching,” IEEE Custom Integrated Circuit Conference (CICC), Sept.
2010, pp. 1-4.
40. M. Cho, N. Sathe, A. Raychowdhury, and S. Mukhopadhyay, “Optimization of Burn-in Test for Manycore Processors Through Adaptive Spatiotemporal Power Migration,” International Test Conference,
Oct. 2010, pp. 1-9.
41. M. Cho, C. Liu, D. H. Kim, S. Lim, and S. Mukhopadhyay, “Design Method and Test Structure to
Characterize and Repair TSV Defect Induced Signal Degradation in 3D System,” IEEE International
Conference on Computer Aided Design (ICCAD), Nov. 2010. pp. 694-697.
42. O. Sullivan, M. Gupta, S. Mukhopadhyay, and S., Kumar, “Thermoelectric coolers for thermal gradient
management on chip,” ASME International Mechanical Engineering Congress & Exposition (IMECE),
Nov. 2010, pp.1-9.
 2009
43. M. Cho, J. Schlessman, W. Wolf, and S. Mukhopadhyay, “Accuracy-Aware SRAM: A Reconfigurable
Low Power SRAM Architecture for Mobile Multimedia Applications,” Asia-Pacific Design Automation
Conference (ASPDAC), Jan. 2009, pp. 823-828.
44. J. Tolbert and S. Mukhopadhyay, “Accurate Buffer Modeling with Slew Propagation in Subthreshold
Circuits,” International Symposium on Quality Electronic Design (ISQED), Mar. 2009, pp. 91-96.
45. D. H. Kim, S. Mukhopadhyay, and S. Lim, “TSV-aware Interconnect Length and Power Prediction for
3D Stacked ICs,” IEEE International Interconnect Technology Conference (IITC), June 2009, pp. 26-28.
46. S. Paul, S. Chatterjee, S. Mukhopadhyay, and S. Bhunia, “Nanoscale Reconfigurable Computing Using
Non-Volatile 2-D STTRAM Array,” International Conference on Nanotechnology (IEEE Nano), July
2009.
47. D. H. Kim, S. Mukhopadhyay, and S. Lim, “Through-Silicon-Via Aware Interconnect Prediction and
Optimization for 3D Stacked ICs,” International Workshop on System Level Interconnect Prediction,
July 2009, pp. 85-92.
48. J. Tolbert, X. Zhao, S. Mukhopadhyay, and S. Lim, “Slew-Aware Clock Tree Design For Reliable
Subthreshold Circuits,” International Symposium on Low-Power Electronic Design (ISLPED), Aug.
2009, pp. 15-20.
14/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
49. S. Kim, S. Mukhopadhyay and W. Wolf, “Experimental analysis of sequence dependence on energy
saving for error tolerant image processing,” International Symposium on Low-Power Electronic Design
(ISLPED), Aug. 2009, pp. 347-350.
50. J. Tolbert, P. Kabali, S. Brar, and S. Mukhopadhyay, “Accuracy Aware Low Power Wireless EEG
Unit with Information Content based Adaptive Data Compression,” Annual International Conference of
the IEEE Engineering in Medicine and Biology Society (EMBS'09), Sept. 2009, pp. 5417-5420.
51. S. Khire and S. Mukhopadhyay, “On improving the algorithmic robustness of a low-power FIR filter,”
IEEE International Conference on Computer Design (ICCD), Oct. 2009, pp. 384-389.
52. S. Chatterjee, S. Salahuddin, S. Kumar, and S. Mukhopadhyay, “Modeling of Self-Heating in STTRAM
and Analysis of its Impact on Reliable Memory Operations,” IEEE Non-Volatile Memory Technology
Symposium (NVMTS), Oct. 2009, pp. 86-89.
53. S. Paul, S. Mukhopadhyay, and S. Bhunia, “A Variation-Aware Preferential Design Approach for
Memory Based Reconfigurable Computing,” International Conference on Computer Aided Design
(ICCAD), Nov. 2009, pp. 180-183.
54. S. Paul, S. Chatterjee, S. Mukhopadhyay, and S. Bhunia, “A Circuit-Software Co-Design Approach for
Improving EDP in Reconfigurable Frameworks,” International Conference on Computer Aided Design
(ICCAD), Nov. 2009, pp. 109-112.
55. S. Chatterjee, M. Rasquinha, S. Yalamanchili, and S. Mukhopadhyay, “A Methodology for Robust,
Energy Efficient Design of Spin-Torque-Transfer RAM Arrays at Scaled Technologies,” International
Conference on Computer Aided Design (ICCAD), Nov. 2009, pp. 474-477.
56. A. Bansal, R. N. Singh, R. N. Kanj, S. Mukhopadhyay, J. F. Lee, E. Acar, A. Singhee, K. Kim, C. T.
Chuang, S. Nassif, F. L. Heng, and K. K. Das, “Yield Estimation of SRAM Circuits using Virtual SRAM
Fab,” International Conference on Computer Aided Design (ICCAD), Nov. 2009, pp. 631-636.
 2008
57. A. Bansal, J. J. Kim, K. Kim, S. Mukhopadhyay, C. T. Chuang, and K. Roy, “Optimal Dual-VT Design
in Sub-100 Nanometer PDSOI and Double-Gate Technologies,” Intl. Conf. on VLSI Design, Jan. 2008,
pp. 125-130.
58. S. Mukhopadhyay, R. Joshi, K. Kim, and C. T. Chuang, “Variability Analysis for Sub-100 nm PD/SOI
Sense-Amplifier,” IEEE Intl. Symp. on Quality Electronic Design (ISQED), Mar 2008, pp. 488-491.
59. N. N. Mojumder, S. Mukhopadhyay, J. J. Kim, C. T. Chuang, and K. Roy, “Design and Analysis of a
Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry,” IEEE VLSI Test Symposium
(VTS), April 2008, pp. 101-106.
60. S. Mukhopadhyay, R. Rao, J. J. Kim, and C. T. Chuang, “Capacitive Coupling Based Transient Negative
Bit-line Voltage (Tran-NBL) Scheme for Improving Write-ability of SRAM Design in Nanometer
Technologies,” IEEE Intl. Symp on Circuits and Systems (ISCAS), May 2008, pp. 384-387.
61. S. Mukhopadhyay, “A Generic Method for Variability Analysis of Nanoscale Circuits,” International
Conference on IC Design & Technology (ICICDT), June 2008, pp. 285-288, (citations in an article in
www.semiconductor.net).
62. J.J. Kim, R. Rao, S. Mukhopadhyay, and C. T. Chuang, “Ring Oscillator Circuit Structures for
Measurement of Isolated NBTI/PBTI Effects,” International Conference on IC Design &
Technology(ICICDT), June 2008, pp. 163-166.
15/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
63. M. Cho, K. Maitra, and S. Mukhopadhyay, “Analysis of the Impact of Interfacial Oxide Thickness
Variation on Metal-Gate High-K Circuits,” Custom Integrated Circuit Conference (CICC), Sept. 2008,
pp. 285-288.
64. A. Bansal, R. Singh, S. Mukhopadhyay, G. Han, F. L. Heng, and C. T. Chuang, “Pre-Si Estimation and
Compensation of SRAM Layout Deficiencies to Achieve Target Performance and Yield,” International
Conference on Computer Design, Oct. 2008, pp. 457-462.
65. S. Paul, S. Mukhopadhyay, and S. Bhunia, “Hybrid CMOS-STTRAM Non-Volatile FPGA: Design
Challenges and Optimization Approaches,” International Conference on Computer Aided Design
(ICCAD), Nov. 2008, pp. 589-592.
 2007
66. S. Bhunia, S. Mukhopadhyay, and K. Roy, “Process Variations and Process-Tolerant Design,” in Proc. of
IEEE International Conference on VLSI Design, 2007, Jan. 2007, pp. 699-704.
67. S. Mukhopadhyay, K. Kim, K. A. Jenkins, C. T. Chuang, and K. Roy, “Statistical Characterization and
On-Chip Measurement Methods for Local Random Variability of a Process Using Sense AmplifierBased Test Structure”, in Tech. Digest of IEEE Intl. Solid State Circuit Conference (ISSCC), Feb. 2007,
pp. 400-401 (citations 42).
68. S. Mukhopadhyay, Q. Chen, K. Roy, “Memories in Scaled Technologies: A Review of Process Induced
Failures, Test Methodologies, and Fault Tolerance,” in Proc. of Design and Diagnostics of Electronic
Circuits and Systems (DDECS), Apr. 2007, pp. 1-6.
69. A. Bansal, K. Kim, J. J. Kim, S. Mukhopadhyay, C. T. Chuang, and K. Roy, “High-Performance Device
Optimization and Dual-VT Technology Options for Double Gate FET,” in Proc. of Intl. Conf. on
Integrated Circuit Design and Technology (ICICDT), May 2007, pp. 1-4.
70. S. Mukhopadhyay, K. Kim, and C. T. Chuang, “Design and analysis of Thin-BOX FD/SOI devices for
low-power and stable SRAM in sub-50nm technologies,” in Proc. of the Intl. Symp. on Low Power
Electronics and Design (ISLPED) Aug. 2007, pp. 20-25.
 2006
71. K. Roy, H. Mahmoodi, S. Mukhopadhyay, H. Ananthan, A. Bansal, and T. Cakici, “Low-Power and
High-Performance Circuit Design using FinFET Devices (INVITED),” in Proc. of Intl. Conf. on VLSI
Design, Jan. 2006, pp. 445-452.
72. A. Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy, “Speed Binning Aware Design Methodology to
Improve Profit under Parameter Variation”, in Proc. of Asia and South Pacific Design Automation Conf.
(ASP-DAC), Jan. 2006, pp. 712-717, nominated for the best paper award.
73. Q. Chen, S. Mukhopadhyay, A. Bansal, and K. Roy, “Circuit-aware device design methodology for
nanometer technologies: A case study for low power SRAM design,” in Proc. of Design, Automation and
Test in Europe (DATE), Mar. 2006, pp. 983-988.
74. S. Mukhopadhyay, K. Kim, H. Mahmoodi, A. Datta, D. Park, and K. Roy, “Self-Repairing SRAM for
Reducing Parametric Failures in Nanoscaled Memory,” in Tech. Digest of Symp. on VLSI Circuits, June
2006, pp. 132-133.
75. S. Ghosh, S. Mukhopadhyay, K. Kim, and K. Roy, “Self-Calibration Technique for Reducing Hold
Failures in Low-Power Nano-scaled SRAM under Process Variation,” in Proc. of Design Automation
Conference (DAC), July 2006, pp. 971-976.
16/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
76. S. Mukhopadhyay, A. Agarwal, Q. Chen, and K. Roy, “SRAMs in Scaled Technologies under Process
Variations: Failure Mechanisms, Test & Variation Tolerant Design (INVITED),” in Proc. of IEEE
Custom Integrated Circuit Conf. (CICC), Sept. 2006, pp. 547-554.
77. S. Gangwal, S. Mukhopadhyay, and K. Roy, “Optimization of Surface Orientation for High-Performance,
Low-Power, and Robust FinFET SRAM,” in Proc. of IEEE Custom Integrated Circuit Conf. (CICC),
Sept. 2006, pp. 433-436.
78. S. Mukhopadhyay, S. Ghosh, K. Kim, and K. Roy, “Low-Power and Process Variation Tolerant
Memories in sub-90nm Technologies (INVITED)”, in Proc. of IEEE Intl. System-On-Chip Conf.
(SOCC), Sept. 2006, pp. 155-159.
 2005
79. S. Mukhopadhyay, S. Bhunia and K. Roy, "Modeling and Analysis of Loading Effect in Leakage of
Nano-Scaled Bulk-CMOS Logic Circuits," in Proc. of Design, Automation, and Test in Europe (DATE),
Mar. 2005, pp. 224-229.
80. A. Datta, S. Bhunia, S. Mukhopadhyay, N. Banerjee, and K. Roy, "Statistical Modeling and Design of
Pipeline under Process Variation to Enhance Yield," in Proc. of Design, Automation, and Test in Europe
(DATE), Mar. 2005, pp. 926-931.
81. S. Mukhopadhyay, K. Kim, J. J. Kim, S.H. Lo, R. Joshi, C. T. Chuang, and K. Roy, “Modeling and
Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits,” in Proc. of
IEEE Intl. Symp. on Quality Electronic Design (ISQED), Mar. 2005, pp. 410-415.
82. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Design of High Performance Sense Amplifier Using
Independent Gate Control in Fully Depleted Double-Gate MOSFET," in Proc. of IEEE Intl. Symp. on
Quality Electronic Design (ISQED), Mar. 2005, pp. 490-495.
83. Q. Chen, S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Process Variation Tolerant Online Current
Monitor for Robust Systems,” in Proc. of IEEE Intl. On-Line Testing Symp. (IOLTS), July 2005, pp. 171176.
84. A. Datta, S. Mukhopadhyay, S. Bhunia, and K. Roy, “Reliability Analysis and Yield Prediction of High
Performance Pipelined Circuit with Respect to Delay Failures in sub-100nm Technology,” in Proc. of
IEEE Intl. On-Line Testing Symp. (IOLTS), July 2005, pp. 275-280.
85. S. Mukhopadhyay, K. Kim, C. T. Chuang, and K. Roy, “Modeling and Analysis of Total Leakage
Currents in Nanoscale Double Gate Circuits,” in Proc. of Intl. Symp. on Low Power Electronics and
Design (ISLPED), Aug. 2005, pp. 8-13.
86. A. Bansal, S. Mukhopadhyay, and K. Roy, “Modeling and Optimization Approach to Robust and LowPower FinFET SRAM Design in NanoScale Era,” in Proc. of IEEE Custom Integrated Circuit Conf.
(CICC), Sept. 2005. pp. 835-838.
87. I. J. Chang, K. Kang, S. Mukhopadhyay, C. H. Kim, and K. Roy, “Fast and Accurate Estimation of NanoScaled SRAM Read Failure Probability using Critical Point Sampling,” in Proc. of IEEE Custom
Integrated Circuit Conf. (CICC), Sept. 2005, pp. 439-442.
17/23
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Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
88. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Analysis and Reduction of Parametric Failures in SRAM
to Enhance Yield in Nano-Scale Memories,” SRC TECHCON, Oct. 2005, Best in Session Award.
89. T. Cakici, H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “Independent Gate Skewed Logic in DoubleGate SOI Technology,” in Proc. of IEEE Intl. SOI Conf., Oct. 2005, pp. 83-84.
90. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “A Feasibility Study of Subthreshold SRAM across
Technology Generations,” in Proc. of IEEE Intl. Conf. on Computer Design (ICCD), Oct. 2005. pp. 417424.
91. K. Roy, H. Mahmoodi, S. Mukhopadhyay, H. Ananthan, A. Bansal, and T. Cakici, “Double-Gate SOI
Devices for Low-Power and High-Performance Applications (INVITED),” in Proc. of Intl. Conf. on
Computer Aided Design (ICCAD), Nov. 2005, pp. 217-224.
92. S. Mukhopadhyay, K. Kang, H. Mahmoodi, and K. Roy, “Reliable and Self-Repairing SRAM in Nanoscale Technologies using Leakage and Delay Monitoring,” in Proc. of Intl. Test Conf. (ITC), Nov. 2005.
93. S. Mukhopadhyay, A. Raychowdhury, H. Mahmoodi, and K. Roy, “Leakage Current based Stabilization
Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM,” in Proc. of
Asian Test Symp. (ATS), Dec. 2005. pp. 176-181.
94. A. Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy, “A statistical approach to area-constrained yield
enhancement for pipelined circuits under parameter variations,” in Proc. of Asian Test Symp. (ATS), Dec.
2005, pp. 170-175.
 2004
95. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “Modeling and Estimation of Leakage in sub-90nm
Devices,” in Proc. of Intl. Conf. on VLSI Design, Jan. 2004, pp. 65-70.
96. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling and Estimation of Failure Probability due to
Parameter Variations in Nano-scale SRAMs for Yield Enhancement," in Tech. Digest of Symp. on VLSI
Circuits, June 2004. pp. 64-67 (citations 67).
97. A. Agarwal, C. H. Kim, S. Mukhopadhyay, and K. Roy, "Leakage in Nano-Scale Technologies:
Mechanisms, Impact and Design Considerations," in Proc. of Design Automation Conf. (DAC), June
2004, pp. 6-11.
98. R. Joshi, S. Mukhopadhyay, D. Plass, Y. Chan, C. T. Chuang, and A. Devgan, "Variability analysis for
Sub-100 nm PD/SOI CMOS SRAM Cell," in Proc. of European Solid State Circuit Conf. (ESSCIRC),
Sept. 2004, pp. 211-214.
99. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, "Estimation of Delay Variations Due to Random-Dopant
Fluctuations in Nano-Scaled CMOS Circuits," in Proc. of IEEE Custom Integrated Circuits Conf.
(CICC), Oct. 2004, pp. 17-20.
100.
H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “High Performance and Low Power Domino Logic
Using Independent Gate Control in Double-Gate SOI MOSFETs,” in Proc. of IEEE Intl. SOI Conf., Oct.
2004, pp. 67-68.
101.
S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, D. Ghosh, and K. Roy, “A Novel Low-Power Scan
Design Technique Using Supply Gating,” in Proc. of IEEE Intl. Conf. on Computer Design (ICCD), Oct.
2004, pp. 60-65, received the Best Paper Award.
102.
S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Statistical Design and Optimization of SRAM Cell
18/23
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Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
for Yield Enhancement," in Proc. of Intl. Conf. on Computer Aided Design (ICCAD), Nov. 2004. pp. 1013 (citations 85).
 2003
103. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, “Leakage Control for Deep Submicron Circuits
(INVITED),” in Proc. of SPIE – vol 5117, VLSI Circuits and Systems, April 2003, pp. 135-146.
104. S. Mukhopadhyay and K. Roy, "Accurate Modeling of Transistor Stacks to Effectively Reduce Total
Standby Leakage in Nano-Scale CMOS Circuits," in Tech. Digest of Symp. of VLSI Circuits, June
2003, pp. 53-56.
105. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, “Accurate Estimation of Total Leakage Current in
Scaled CMOS Logic Circuits Based on Compact Current Modeling,” in Prof. of Design Automation
Conf. (DAC), June 2003, pp. 169-174, nominated for the Best Paper Award (citations 95).
106. S. Mukhopadhyay and K. Roy, “Modeling and Estimation of Total Leakage Current in Nano-scaled
CMOS Devices Considering the Effect of Parameter Variation,” in Proc. of Intl. Symp. on Low Power
Electronics and Design (ISLPED), Aug. 2003, pp. 172-175 (citations 120).
107. C. H. Kim, J. J. Kim, S. Mukhopadhyay, and K. Roy, “A Forward Body-Biased Low-Leakage SRAM
Cache: Device and Architecture Considerations,” in Proc. of Intl. Symp. on Low Power Electronics
and Design (ISLPED), Aug. 2003, pp. 6-9.
108. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “Circuit Compatible Modeling of Carbon Nanotube
FETs in the Ballistic Limit of Performance,” in Proc. of IEEE Conf. on Nanotechnology (IEEE Nano),
Aug. 2003, pp. 343-346, received the Best Student Paper Award.
109. S. Mukhopadhyay, H. Mahmoodi, C. Neau, and K. Roy, “Leakage in Nanometer Scale CMOS Circuits
(INVITED),” in Proc. of Intl. Symp. on VLSI Technology, Systems, and Applications (VLSI-TSA), Oct.
2003, pp. 307-312.
110. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “Modeling of Ballistic Field-effect Transistors for
Efficient Circuit Simulation,” in Proc. of Intl. Conf. on Computer Aided Design (ICCAD), Nov. 2003,
pp. 487-490.
C.
PATENTS
Awarded
1.
S. Mukhopadhyay, H. Mahmoodi, and K. Roy, “Sense Amplifier Circuit,” United States Patent no.
7304903, issued on 12/4/2007.
2.
S. Bhunia, H. Mahmoodi, A. Raychowdhury, S. Mukhopadhyay, and K. Roy, “Low power scan design
and delay fault testing technique using first level supply gating,” United States Patent no. 7319343,
issued on 1/15/2008.
3.
S. Mukhopadhyay, H. Mahmoodi, K. Kim, and K. Roy, “Self Repairing technique in nano-scale SRAM
to reduce parametric failures,”United States Patent no. 7508697, issued on 03/24/2009.
4.
C. T. Chuang, J. J. Kim, T. H. Kim, P. F. Lu, R. Rao, S. Mukhopadhyay, and S. Wang, “Circuits and
Design Structures for Monitoring NBTI (Negative Bias Temperature Instability) Effect and/or PBTI
(Positive Bias Temperature Instability),” United States Patent No. 7642864, issued on, 01/05/2010.
5.
C. T. Chuang, J. J. Kim, and S. Mukhopadhyay, “Circuits and Methods for Characterizing Device
Variation in Electronic Memory Circuits,” United States Patent no. 7673195, issued on 03/02/2010.
19/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
6.
S. Banerjee, D. Chidambarrao, J. Culp, P. Elakkumanan, and S. Mukhopadhyay, “Analyzing multiple
induced systematic and statistical layout dependent effects on circuit performance,” United States Patent
no. 8176444, issued on 03/08/2012.
Pending
1.
C. T. Chuang, J. J. Kim, N. Mojumder, and S. Mukhopadhyay, “Circuits, Methods and Design Structures
for Adaptive Repair of SRAM Arrays,” patent pending, filed on Jan. 24, 2008 by IBM Corporation,
Publication No. 20090190426, Publication Date: 2009-07-30.
2.
C. T. Chuang, F. L. Heng, R. Kanj, K. Kim, J. F. Lee, S. Mukhopadhyay, S. R. Nassif, and R. N. Singh,
“Techniques For Pattern Process Tuning And Design Optimization For Maximizing Process-Sensitive
Circuit Yields,” patent pending, filed on Feb. 1, 2008 by IBM Corporation.
D.
PRESENTATIONS
Tutorial Presentations
1. IEEE International On-Line Testing Symposium, Sesimbra-Lisbon, Portugal, June 24-26, 2009:
“Parameter Variations and Self-Calibration/Self-Repair Solutions in Nanometer Technologies,” by
Saibal Mukhopadhyay, Rahul Rao, Praveen Elakkumanan, and Swarup Bhunia
2. International Test Conference, Austin, TX, USA, Nov 1-6, 2009, “Parameter Variations and SelfCalibration/Self-Repair Solutions in Nanometer Technologies,” by Saibal Mukhopadhyay, Rahul Rao,
Praveen Elakkumanan, and Swarup Bhunia.
3. VLSI Test Symposium, Santa Cruz, CA, USA, April 19-22, 2010, “Parameter Variations and LowPower Design: Test Issues and On-chip Calibration/Repair Solutions,” by Rahul Rao, Saibal
Mukhopadhyay, Praveen Elakkumanan, and Swarup Bhunia.
4. International Test Conference, Austin, TX, USA, Oct 31-Nov 4, 2010, “Parameter Variations and LowPower Design: Test Issues and On-chip Calibration/Repair Solutions,” by Rahul Rao, Saibal
Mukhopadhyay, Praveen Elakkumanan, and Swarup Bhunia.
5. International Conference on VLSI Design, Pune, India, Jan 5-Jan 10, 2013, “Energy-efficient Adaptive
Circuits and Systems,” by Saibal Mukhopadhyay, Swaroop Ghosh, Abhijit Chatterjee, and Sudhakar
Yalamanchili.
6. Design, Automation, and Test in Europe, Grenoble, France, March 18-22, 2013, “Energy-efficient
Adaptive Circuits and Systems,” by Saibal Mukhopadhyay, Arijit Raychowdhury, Abhijit Chatterjee,
and Sudhakar Yalamanchili.
Special Session Organization
7. International Conference on VLSI Design, Pune, India, Jan 5-Jan 10, 2013, “Embedded TutorialEmerging Computing Technologies,” by Saibal Mukhopadhyay
8. International Conference on VLSI Design, Pune, India, Jan 5-Jan 10, 2013, “Embedded Tutorial - Low
Power Computing - Reducing the gap between the Physical and Practical Limits,” by Saibal
Mukhopadhyay, and Sudhakar Yalamanchili.
20/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
Invited Talks/Seminars
9. “Design in Emerging Technologies: Circuit and Technology Perspectives,” Invited Seminar at National
Chiao-Tung University, Hsinchu, Taiwan, Nov. 2008.
10. “Embedded Memory Design in Nanoscale Silicon Technologies,” Invited Seminar at National ChiaoTung University, Hsinchu, Taiwan, Nov. 2008.
11. “Embedded Memory Design in Nanoscale Silicon Technologies,” Invited Seminar at Faraday
Technology Corporation, Hsinchu, Taiwan, Nov. 2008.
12. “Gigascale Reliable Energy-Efficient Many-Core and 3D IC Design in Nanometer Nodes,” Invited
Seminar at Intel Circuit Research Lab, Hillsboro, OR, Oct 2009.
13. “Design Challenges and Solutions in Nanometer Technologies: Embedded Memories and 3D IC,”
Invited Seminar at Portland Technology Development, Intel Corp, Hillsboro, OR, Oct 2009.
14. “Variability Characterization for Narrow-Width Devices and Application to Post-Silicon Repair in
SRAM,” Special Session: Hot Topic: Design Consideration and Silicon Evaluation of On-Chip
Monitors, VLSI Test Symposium, Santa Cruz, CA, April 2010.
15. “Addressing the Thermal Challenges in Many-Core Processors,” Invited Seminar at IBM T. J. Watson
Research Center, Yorktown Heights, NY, Oct 2010.
16. “Addressing the Thermal Challenges in Many-Core Processors,” Invited Seminar at IBM Austin
Research Lab, Austin, TX, Oct 2010.
17. “Energy and Reliability of 3D Integration: Opportunities and Challenges”, Invited Seminar at 3D System
Integration Workshop, Interconnect and Packaging Center, Atlanta, GA, June 2011.
18. “Designing for Energy-Efficiency and Reliability in Future Multi-Core and 3D Systems”, Invited
Seminar at Texas Instruments, Dallas, TX, Nov. 2011.
19. “Low-Power and Temperature-Aware Design of Integrated Circuits”, Invited Seminar at IBM T. J.
Watson Research Center, Yorktown Heights, NY, June. 2012.
20. “Low-Power and Temperature-Aware Design of Integrated Circuits”, Invited Seminar at Intel Labs,
Hillsboro, OR, June. 2012.
21. “Designing for Energy-Efficiency and Reliability in Future Multi-Core and 3D Systems”, Invited
Seminar at Texas Instruments, Dallas, TX, Oct. 2012.
22. “Designing for Energy-Efficiency and Reliability in Future Systems”, Invited Seminar at IBM India Pvt.
Ltd, Bangalore, India, Jan. 2013.
23. “Designing for Energy-Efficiency and Reliability in Future Systems”, Invited Seminar at Qualcomm
Corp., San Diego, CA, Feb. 2013.
VIII.
TEACHING
Key Achievements
 Class of 1934 Course Survey Teaching Effectiveness Award, 2012
 Nominated from ECE for the Georgia Tech "Outstanding Teaching Award (Junior)” in 2013
 Received multiple “Thank-A-Teacher” Certificates
 Average Teaching Effectiveness Score of 4.85 out of 5 over last six (6) years
21/23
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Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech
Publications in Educational Conferences/Journals
 M. Wolf and S. Mukhopadhyay, “Physics of Computing as an Introduction to Computer
Engineering,” IEEE Frontiers of Education (FIE), 2013.
Program Committee of Education Conferences/Journals
 IEEE Frontiers in Education Conference, 2013
 Interdisciplinary Engineering Design Education Conference (IEDEC), 2012, 2013
New Courses: Conceived and Introduced
1. Digital System in Nanometer Nodes (Graduate)
Description: Current VLSI systems designed in sub-90nm silicon technologies have more than 300 million
transistors operating in Gigahertz frequencies. This course discusses the challenges, such as power,
variability, and reliability, etc. associated with designing these VLSI systems. The different principles and
methods explored in both academia and industry to address these challenges are discussed.
2. CAD Methodologies for VLSI Design-for-Manufacturability (Graduate, co-designed with S. Lim)
Course Description: The design for manufacturability (DFM) includes a set of techniques to modify the
design of VLSI circuits in order to make them more manufacturable and improve reliability. This course
focuses on (1) the causes/effects of process variations on device, interconnect, and circuit-level performance,
power, and reliability and (2) various DFM-aware CAD techniques proposed to tackle the problems.
3. Physics of Computation (Undergraduate Core Course for Revised CmpE Curriculum)
Course Description: Motivated by the concepts presented in “Feynman Lectures on Computation”, this new
course will discuss the fundamental requirements in physical implementation of an information processing
system and relate that to principles of semiconductor, circuit theory, electromagnetism, and thermodynamics.
The connections of the above principles to the performance, energy, and robustness of computing system
will be explained to introduce CmpE undergrads to the physics of any computing systems being decoupled
(relatively) from any particular technology. This is an approved new core course for the revised
undergraduate Computer Engineering curricula. Dr. Mukhopadhyay has conceptualized this course and is
spearheading the effort in defining and creating this course in collaboration with several other ECE faculty.
IX. SERVICE
A. PROFESSIONAL CONTRIBUTIONS

Senior Member of the Institute of Electrical and Electronics Engineers (IEEE).

IEEE Society Memberships:
o
IEEE Electron Devices Society, IEEE Circuits and Systems Society, IEEE Components,
Packaging, and Manufacturing Technology Society, and IEEE Solid-State Circuits Society
o
IEEE Council on Electronic Design Automation, IEEE Sensors Council, and IEEE
Nanotechnology Council

Participation in National Science Foundation Proposal Review Panels

Paper Review for Journals
o
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)
o
IEEE Transactions on VLSI Design (TVLSI)
22/23
August 2013
Dr. Saibal Mukhopadhyay, Associate Professor, School of ECE, Georgia Tech

o
IEEE Transactions on Electron Devices (TED)
o
IEEE Transactions on Circuits and Systems (TCAS)
o
IEEE Electron Device Letters (EDL)
o
IEEE Journal of Emerging Topics in Circuits and Systems (JETCAS)
o
IEEE Transactions on Semiconductor Manufacturing (TSM)
o
IEEE Transactions on Component, Packaging, and Manufacturing Technology (TCPMT)
o
ACM Journal of Emerging Technologies in Computing
Member of Technical Program Committee of
o
International Symposium on Quality Electronic Design (ISQED), 2007-2011.
o
International Symposium on Low Power Electronic Design (ISLPED), 2007, 2010-2103
o
International Conference on Computer Aided Design (ICCAD), 2010, 2011, 2012
o
IEEE Intl. Conf. on VLSI Design, 2010, 2011 (Track Chair), 2013 (Track Chair).
o
DAC/ISSCC Student Design Contest (DAC/ISSCC - SDC), 2011
o
IEEE International On-Line Test Symposium (IOLTS), 2009-2013.
o
IEEE Computer Society Annual Symposium on VLSI, 2010, 2011, 2012.
o
IEEE International Workshop on Design for Reliability and Variability (DRVW), 2008, 2009.
B. CAMPUS CONTRIBUTIONS

ECE Graduate Committee – 2008-2009, 2009-2010

ECE Graduate Student Recruiting Committee – 2010-2011, 2011-2012, 2012-2013

CmpE Undergraduate Curriculum Revision Committee – 2010

Physics of Computing Committee – 2010-2011

Member of: Interconnect and Packaging Center (IPC, since 2010), Inteconnect Focus Center (IFC, since
2010), Advanced Center of Embedded Systems (ACES, since 2008).

More than 30 MS Thesis, PhD Proposal, and PhD Defense Committee
23/23
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