NB3H63143G D

NB3H63143G

3.3 V / 2.5 V Programmable

OmniClock Generator

with Single Ended (LVCMOS/LVTTL) and

Differential (LVPECL/LVDS/ HCSL/CML)

Outputs with Individual Output Enable and Individual VDDO

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The NB3H63143G, which is a member of the OmniClock family, is a one−time programmable (OTP), low power PLL−based clock generator that supports any output frequency from 8 kHz to 200 MHz.

The device accepts fundamental mode parallel resonant crystal or a single ended (LVCMOS/LVTTL) reference clock as input. It generates either three single ended (LVCMOS/LVTTL) outputs, or o n e s i n g l e e n d e d o u t p u t a n d o n e d i f f e r e n t i a l

(LVPECL/LVDS/HCSL/CML) output. The output signals can be modulated using the spread spectrum feature of the PLL

(programmable spread spectrum type, deviation and rate) for applications demanding low electromagnetic interference (EMI).

Individual output enable pins OE[2:0] are available to enable/disable the outputs. Individual output voltage pins VDDO[2:0] are available to independently set the output voltage of each output. Up to four different configurations can be written into the device memory. Two selection pins (SEL[1:0]) allow the user to select the configuration to use. Using the PLL bypass mode, it is possible to get a copy of the input clock on any or all of the outputs. The device can be powered down using the Power Down pin (PD#). It is possible to program the internal input crystal load capacitance and the output drive current provided by the device. The device also has automatic gain control

(crystal power limiting) circuitry which avoids the device overdriving the external crystal.

Features

Member of the OmniClock Family of Programmable

Clock Generators

Operating Power Supply: 3.3 V

±10%, 2.5 V ±10%

I/O Standards

Inputs: LVCMOS/LVTTL, Fundamental Mode

Crystal

Outputs: 1.8 V to 3.3 V LVCMOS/LVTTL

Outputs: LVPECL, LVDS, HCSL and CML

3 Programmable Single Ended (LVCMOS/LVTTL)

Outputs from 8 kHz to 200 MHz

1 Programmable Differential Clock Output up to

200 MHz

Input Frequency Range

Crystal: 3 MHz to 50 MHz

Reference Clock: 3 MHz to 200 MHz

Configurable Spread Spectrum Frequency Modulation

Parameters (Type, Deviation, Rate)

Individual Output Enable Pins

Independent Output Voltage Pins

1

QFN16

CASE 485AE

MARKING DIAGRAM

3H631

43Gxx

ALYW

G

G

Y

W

G

3H63143G = Specific Device Code xx = Specific Program Code (Default

A

L

‘00’ for Unprogrammed Part)

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information on page 23 of

this data sheet.

Programmable Internal Crystal Load Capacitors

Programmable Output Drive Current for Single Ended

Outputs

Power Saving Mode through Power Down Pin

Programmable PLL Bypass Mode

Programmable Output Inversion

Programming and Evaluation Kit Available for Field

Programming and Quick Evaluation

Temperature Range −40

°C to 85°C

Packaged in 16−pin QFN

These are Pb−Free Devices

Typical Applications

• eBooks and Media Players

Smart Wearables, Smart Phones, Portable Medical and

Industrial Equipment

Set Top Boxes, Printers, Digital Cameras and

Camcorders

©

Semiconductor Components Industries, LLC, 2016

January, 2016 − Rev. 4

1

Publication Order Number:

NB3H63143G/D

NB3H63143G

PD#

BLOCK DIAGRAM

SEL0 SEL1 VDD

Reference

Clock

XIN/ CLKIN

Crystal

XOUT

Input

Decoder

Clock Buffer/

Crystal

Oscillator And

AGC

Output control

Crystal/Clock Control

Configuration

Memory

Frequency and SS

PLL Block

Phase

Detector

Charge

Pump

VCO

Output

Divider

Output

Divider

Feedback

Divider

Output

Divider

PLL Bypass Mode

CMOS/

DIFF buffer

CMOS/

DIFF buffer

CMOS buffer

GND GNDO

Notes:

1. CLK0 and CLK1 can be configured to be one LVPECL, LVDS, HCSL or CML output, or two single ended LVCMOS/LVTTL outputs.

2. Dotted lines are the programmable control signals to internal IC blocks.

3. OE[2:0], SEL[1:0] have internal pull up resistors. PD# has internal pull down resistor.

Figure 1. Simplified Block Diagram

VDDO0

CLK0

OE0

VDDO1

CLK1

OE1

VDDO2

CLK2

OE2

PIN FUNCTION DESCRIPTION

XIN/CLKIN 1

16 15 14

NB3H63143G

13

12 VDD

XOUT 2 11 VDDO1

GNDO

(EPAD)

PD# 3

GND 4

10 CLK1

9 CLK0

5 6 7 8

Figure 2. Pin Connections (Top View) − QFN16 (with EPAD) www.onsemi.com

2

NB3H63143G

Table 1. PIN DESCRIPTION

Pin No.

1

Pin Name

XIN/CLKIN

4

5, 6, 7

10

11

12

13

2

3

8

9

14

15, 16

EPAD

XOUT

PD#

GND

OE[2:0]

VDDO0

CLK0

CLK1

VDDO1

VDD

CLK2

VDDO2

SEL[1:0]

GNDO

Pin Type

Input

Output

Input

Ground

Input

Power

SE/DIFF Output

SE/DIFF Output

Power

Power

SE Output

Power

Input

Ground

Description

3 MHz to 50 MHz crystal input connection or an external single ended reference input clock between 3 MHz and 200 MHz.

Crystal output. Float this pin when external reference clock is connected at XIN.

Asynchronous LVCMOS/LVTTL input. Active Low Master Reset to disable the device and set outputs Low. Internal pull−down resistor. This pin needs to be pulled

High for normal operation of the chip.

Power supply ground.

2−Level LVCMOS/LVTTL Inputs for Enabling/Disabling output clocks CLK[2:0] respectively. Internal pull−up resistor.

CLK0 Output power supply

VDD

Supports 8 kHz to 200 MHz Single Ended (LVCMOS/LVTTL) signals or Differential

(LVPECL/LVDS/HCSL/CML) signals. Using PLL Bypass mode, the output can also be a copy of the input clock. The single ended output will be LOW and differential outputs will be complementary LOW/HIGH until the PLL has locked and the frequency has stabilized.

Supports 8 kHz to 200 MHz Single Ended (LVCMOS/LVTTL) signals or Differential

(LVPECL/LVDS/HCSL/CML) signals. Using PLL Bypass mode, the output can also be a copy of the input clock. The single ended output will be LOW and differential outputs will be complementary LOW/HIGH until the PLL has locked and the frequency has stabilized.

CLK1 Output power supply

VDD

3.3V / 2.5V power supply.

Supports 8 kHz to 200 MHz Single Ended (LVCMOS/LVTTL) signals. Using PLL

Bypass mode, the output can also be a copy of the input clock. The single ended output will be LOW until the PLL has locked and the frequency has stabilized.

CLK2 Output power supply

VDD

2−Level LVCMOS/LVTTL Inputs for Configuration Selection. Configuration parameters include individual output frequencies, spread spectrum configuration, enable/disable status of each output, output type, internal crystal load capacitance configuration, etc. Configuration can be switched dynamically, but may require the

PLL to re−lock. Internal pull−up resistor.

Power supply ground for Outputs.

Table 2. OUTPUT CONFIGURATION SELECT

FUNCTION TABLE

SEL1

L

L

H

H

SEL0

L

H

L

H

Output Configuration

I

II

III

IV

Table 3. POWER DOWN FUNCTION TABLE

PD#

0

Function

Device Powered Down

1 Device Powered Up

Table 4. OUTPUT ENABLE FUNCTION TABLE

OE[2:0]

0

Function

CLK Disabled

1 CLK Enabled

TYPICAL CRYSTAL PARAMETERS

Crystal: Fundamental Mode Parallel Resonant

Frequency: 3 MHz to 50 MHz

Table 5. MAX CRYSTAL LOAD CAPACITORS

RECOMMENDATION

Crystal Frequency Range

3 MHz − 30 MHz

30 MHz − 50 MHz

Max Cap Value

20 pF

10 pF

Shunt Capacitance (C0): 7 pF (Max)

Equivalent Series Resistance 150

W (Max)

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3

NB3H63143G

FUNCTIONAL DESCRIPTION

The NB3H63143G is a 3.3 V/2.5 V programmable, single ended/differential clock generator, designed to meet the timing requirements for consumer and portable markets. It has a small package size and it requires low power during operation and while in standby. This device provides the ability to configure a number of parameters as detailed in the following section. The One−Time Programmable memory allows programming and storing of up to four configurations in the memory space.

3.3 V/2.5 V VDDO0 VDDO1

R (Optional) R (Optional) R (Optional)

0.1 m

F 0.01 m

F 0.1 m

F 0.01 m

F 0.1 m

F 0.01 m

F

Crystal or

Reference

Clock Input

XIN/CLKIN

VDD VDDO0

VDDO2

VDDO1

R (Optional)

XOUT VDDO2

NB3H63143G

0.1 m

F 0.01 m

F

SEL0

SEL1

CLK2

CLK1

CLK0

Single Ended Clock

Single Ended Clocks or

Differential Clock

LVPECL/LVDS/

HCSL/CML

PD# OE0 OE1 OE2

Figure 3. Power Supply and Output Supply Noise Suppression

Power Supply

Device Supply

The NB3H63143G is designed to work with a 3.3 V/2.5 V

VDD power supply. For VDD operation of 1.8 V, refer to the

NB3V63143G datasheet. In order to suppress power supply noise it is recommended to connect decoupling capacitors of

0.1

mF and 0.01 mF close to the VDD pin as shown in

Figure 3.

Output Power Supply

Each output CLK[2:0] has a separate output power supply

VDDO[2:0] pin to control its output voltage. The output power supply can be as high as VDD. It can be as low as

2.5 V for clock output types LVPECL/CML and as low as

1.8 V if using other clock output types. This feature removes the need for external voltage converters for each of the outputs thus reducing component count, saving board space and facilitating board design. In order to suppress power supply noise it is recommended to connect decoupling capacitors of 0.1

mF and 0.01 mF close to each VDDO pin as

shown in Figure 3.

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NB3H63143G

Clock Input

Input Frequency

The clock input block can be programmed to use a fundamental mode crystal from 3 MHz to 50 MHz or a single ended reference clock source from 3 MHz to

200 MHz. When using output frequency modulation for

EMI reduction, for optimal performance, it is recommended to use crystals with a frequency greater than 6.75 MHz as input. Crystals with ESR values of up to 150

W are supported. While using a crystal as input, it is important to set crystal load capacitor values correctly to achieve good performance.

Programmable Crystal Load Capacitors

The provision of internal programmable crystal load capacitors eliminates the necessity of external load capacitors for standard crystals. The internal load capacitors can be programmed to any value between 4.36 pF and

20.39 pF with a step size of 0.05 pF. Refer to Table 5 for

recommended maximum load capacitor values for stable operation. There are three modes of loading the crystal − with internal chip capacitors only, with external capacitors only or with the both internal and external capacitors. Check with the crystal vendor’s load capacitance specification for setting of the internal load capacitors.

The minimum value of 4.36 pF internal load capacitor need to be considered while selecting external capacitor value. The internal load capacitors will be bypassed when using an external reference clock.

Automatic Gain Control (AGC)

The Automatic Gain Control (AGC) feature adjusts the gain to the input clock based on its signal strength to

Crystal or

Reference

Clock Input maintain a good quality input clock signal level. This feature takes care of low clock swings fed from external reference clocks and ensures proper device operation. It also enables maximum compatibility with crystals from different manufacturers, processes, quality and performance. AGC also takes care of power dissipation in the crystal; avoids overdriving the crystal and thus extending the crystal life. In order to calculate the AGC gain accurately and avoid increasing the jitter on the output clocks, the user needs to provide the crystal load capacitance as well as other crystal parameters like ESR and shunt capacitance (C0).

Programmable Clock Outputs

Output Type and Frequency

The NB3H63143G provides three independent single ended LVCMOS/LVTTL outputs, or one single ended

LVCMOS/LVTTL output and one LVPECL/LVDS/HCSL/

CML differential output. The device supports any single ended output or differential output frequency from 8 kHz up to 200 MHz with or without frequency modulation. All outputs have individual output enable pins (refer to the

Output Enable/Disable section on page 7). It should be

noted that certain combinations of output frequencies and spread spectrum configurations may not be recommended for optimal and stable operation.

For differential clocking, CLK0 and CLK1 can be configured as LVPECL, LVDS, HCSL or CML. While using differential signaling format at the output, it is required to use only VDDO1 as output supply and use only the OE1 pin for the output enable function. (refer to the Application

Schematic in Figure 4). When all 3 outputs are single ended,

VDDO0 and OE0 have normal functionality.

VDDO2

VDD

VDDO2

XIN/CLKIN

XOUT

CLK2

Single Ended Clock

VDDO1

VDD

NB3H63143G

VDDO1

VDDO0

CLK1

CLK0

Differential Clock

LVPECL/LVDS/HCSL/CML

OE2 OE0

PD# OE1

Figure 4. Application Setup for Differential Output Configuration

Programmable Output Drive

The drive strength or output current of each of the

LVCMOS clock outputs is programmable independently.

For each VDDO supply voltage, four distinct levels of

LVCMOS output drive strengths can be selected as mentioned in DC Electrical Characteristics. This feature provides further load drive and signal conditioning as per the application requirement.

PLL BYPASS Mode

PLL Bypass mode can be used to buffer the input clock on any of the outputs or all of the outputs. Any of the clock outputs can be programmed to generate a copy of the input clock.

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NB3H63143G

Output Inversion

All output clocks of the NB3H63143G can be phase inverted relative to each other. This feature can also be used in conjunction with the PLL BYPASS mode.

Spread Spectrum Frequency Modulation

Spread spectrum is a technique using frequency modulation to achieve lower peak electromagnetic interference (EMI). It is an elegant solution compared to techniques of filtering and shielding. The NB3H63143G modulates the output of its PLL in order to “spread” the bandwidth of the synthesized clock, decreasing the peak amplitude at the center frequency and at the frequency’s harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most clock generators. Lowering EMI by increasing a signal’s bandwidth is called ‘spread spectrum modulation’.

Figure 5. Frequency Modulation or Spread Spectrum Clock for EMI Reduction

The outputs of the NB3H63143G can be programmed to have either center spread from

±0.125% to ±3% or down spread from −0.25% to −4%. The programmable step size for spread spectrum deviation is 0.125% for center spread and 0.25% for down spread respectively. Additionally, the frequency modulation rate is also programmable.

Frequency modulation from 30 kHz to 130 kHz can be selected. Spread spectrum, when on, applies to all the outputs of the device but not to output clocks that use the

PLL bypass feature. There exists a tradeoff between the input clock frequency and the desired spread spectrum profile. For certain combinations of input frequency and modulation rate, the device operation could be unstable and should be avoided. For spread spectrum applications, the following limits are recommended:

Fin (Min) = 6.75 MHz

Fmod (range) = 30 kHz to 130 kHz

Fmod (Max) = Fin / 225

For any input frequency selected, the above limits must be observed for a good spread spectrum profile.

For example, the minimum recommended reference frequency for a modulation rate of 30 kHz would be

30 kHz * 225 = 6.75 MHz. For 27 MHz, the maximum recommended modulation rate would be

27 MHz / 225 = 120 kHz

Control Inputs

Configuration Space Selection

The SEL[1:0] pins are used to select one of the pre−programmed configurations statically or dynamically while the device is powered on. These pins are 2−level

LVCMOS/LVTTL. Up to four configurations can be stored in the memory space of the device. Clock outputs can be independently enabled or disabled through the configuration space. To have a given clock output enabled, it must be enabled in both the configuration space and through its respective output enable pin.

The PLL re−locking and stabilization time must be taken into consideration when dynamically changing the

configurations. Table 6 shows an example of four

configurations.

Table 6. EXAMPLE CONFIGURATION SPACE SETTINGS

Configuration

Selection

Input

Frequency

Output

Frequency

I 25 MHz CLK0=100 MHz

CLK1=8 kHz

CLK2=25 MHz

VDD

3.3 V

VDDO

VDDO0=2.5 V

VDDO1=1.8 V

VDDO2=1.8 V

SS%

−0.5%

II 40 MHz CLK0=125 MHz

CLK1=40 MHz

CLK2=10 MHz

3.3 V VDDO0=2.5 V

VDDO1=1.8 V

VDDO2=1.8 V

±

0.25%

III 100 MHz CLK0=100 MHz

CLK1=100 MHz

CLK2=100 MHz

3.3 V VDDO0=2.5 V

VDDO1=1.8 V

VDDO2=1.8 V

No SS

SS Mod

Rate

110 kHz

30 kHz

NA

IV 25 MHz CLK0=100 MHz

CLK1=100 MHz

CLK2=48 MHz

3.3 V VDDO0=NA

VDDO1=2.5 V

VDDO2=3.3 V

−1%

Output

Drive

CLK0=12mA

CLK1=8mA

CLK2=4mA

CLK0=4mA

CLK1=4mA

CLK2=4mA

CLK0=12mA

CLK1=8mA

CLK2=4mA

100 kHz CLK2=16mA

Output

Inversion

CLK0=N

CLK1=N

CLK2=Y

CLK0=N

CLK1=N

CLK2=N

CLK0=N

CLK1=Y

CLK2=Y

Output

Enable

CLK0=Y

CLK1=Y

CLK2=Y

CLK0=Y

CLK1=Y

CLK2=Y

CLK0=Y

CLK1=Y

CLK2=Y

CLK0=NA

CLK1=NA

CLK2=N

CLK0=NA

CLK1=Y

CLK2=Y

PLL

Bypass

CLK0=N

CLK1=N

CLK2=Y

CLK0=N

CLK1=Y

CLK2=N

CLK0=Y

CLK1=Y

CLK2=Y

CLK0=NA

CLK1=N

CLK2=N

Notes

CLK2

Ref clk

CLK1

Ref clk

All Three

Outputs are Ref clks

CLK[1:0] is

Differential

Output

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NB3H63143G

Output Enable/Disable

Output Enable pins (OE[2:0]) are LVCMOS/LVTTL input pins that individually enable or disable the outputs

CLK[2:0] respectively. These inputs only disable the output buffers thus not affecting the rest of the blocks on the device.

When using a differential output, only the OE1 pin must be used to enable/disable the differential output (the OE0 pin will be ignored). The hardware OE pins have an effect only when the respective outputs are enabled in the configuration space. The output disable state can be set to high impedance

(Hi−Z) or Low.

Power Down

Power saving mode can be activated though the power down PD# input pin. This input is an LVCMOS/LVTTL active Low Master Reset that disables the device and sets the outputs Low. By default it has an internal pull−down resistor.

Table 7. ATTRIBUTES

Characteristic

ESD Protection − Human Body Model

Internal Input Default State Pull Up/Down Resistor

Moisture Sensitivity, Indefinite Time Out of Dry Pack

(Note 1)

Flammability Rating − Oxygen Index: 28 to 34

Transistor Count

Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D .

The device functions are disabled by default and when the

PD# pin is pulled high the device functions are activated.

Default Device State

The NB3H63143G parts shipped from

ON Semiconductor are blank, with no inputs/outputs programmed. The parts need to be programmed by the field sales or by a distributor or by the users themselves before they can be used. Programmable clock software downloadable from the ON Semiconductor website can be used along with the programming kit to achieve this purpose. For mass production, parts can be factory programmed with a customer qualified configuration and sourced from ON Semiconductor as a dash part number (Eg.

NB3H63143G−01).

Value

2 kV

50 k

W

MSL1

UL 94 V−0 @ 0.125in

130k

ABSOLUTE MAXIMUM RATINGS

(Note 2)

Symbol

VDD

Parameter

Positive Power Supply with Respect to Ground

Rating

−0.5 to +4.6

Unit

V

V

I

Input Voltage with Respect to Chip Ground −0.5 to VDD + 0.5

V

T

T

A

STG

Operating Ambient Temperature Range (Industrial Grade)

Storage Temperature

−40 to +85

−65 to +150

°

C

°

C

°

C T

SOL q

JA

Max. Soldering Temperature (10 sec)

Thermal Resistance (Junction−to−Ambient) (Note 3)

0 lfpm

500 lfpm

265

32.3

24.22

°

C/W

°

C/W q

JC

T

J

Thermal Resistance (Junction−to−Case)

Junction Temperature

3.6

125

°

C/W

°

C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously.

If stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.

3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). JESD51.7 type board. Back side Copper heat spreader area 100 sqmm, 2 oz

(0.070mm) copper thichness.

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7

NB3H63143G

RECOMMENDED OPERATING CONDITIONS

Symbol

VDD

Parameter

Core Power Supply Voltage

Condition

3.3 V operation

2.5 V operation

Min

2.97

2.25

Typ

3.3

2.5

Max

3.63

2.75

Unit

V

VDDO[2:0]

Output Power Supply Voltage (Note 4)

3.3 V operation

2.5 V operation

1.8 V operation

CL fclkin

Clock output load capacitance for

LVCMOS / LVTTL clock

Crystal Input Frequency

Reference Clock Frequency fout < 100 MHz fout

100 MHz

Fundamental Crystal

Single ended clock input

2.97

2.25

1.7

3.3

2.5

1.8

3.63

2.75

1.9

15

5

50

200

V pF

3

3

MHz

C

X

Xin / Xout pin stray capacitance

(Note 5)

4.5

pF

C

XL

Crystal load capacitance

(Note 6)

10 pF

ESR Crystal ESR 150

W

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.

4. The output power supply voltage VDDO[2:0] must always be less than or equal to core power supply voltage VDD.

5. The Xin/ Xout pin stray capacitance needs to be subtracted from crystal load capacitance (along with PCB and trace capacitance) while selecting appropriate load for the crystal in order to get minimum ppm error.

6. Refer to XTAL parameters supplied by the vendor.

DC ELECTRICAL CHARACTERISTICS

(V

DD

= 3.3 V

±

10%, 2.5 V

±

10%, VDDO[2:0] = 3.3 V

±

10%, 2.5 V

±

10%, 1.8 V

±

0.1V; GND = 0 V, T

A

= −40

°

C to 85

°

C, Note 7)

Symbol Parameter Condition Min Typ Max

I

DD_3.3 V

Power Supply Current for

Core

Configuration Dependent. VDD = 3.3 V,

T

A

= 25

°

C, XIN/CLKIN = 25 MHz

(XTAL), CLK[0:2] = 100 MHz, 16 mA output drive

13

I

DD_2.5 V

13

I

PD

V

IH

V

IL

Zo

R

PUP/PD

Cprog

Cin

Power Supply Current for

Core

Programmable Internal

Crystal Load Capacitance

Configuration Dependent. VDD = 2.5 V,

T

A

= 25

°

C, XIN/CLKIN = 25 MHz

(XTAL), CLK[0:2] = 100 MHz, 12 mA output drive

Power Down Supply Current PD# is Low to Make All Outputs OFF

Input HIGH Voltage Pins XIN, SEL[1:0], OE[2:0]

Input LOW Voltage

Pin PD#

Pins XIN, SEL[1:0], OE[2:0]

Pin PD#

Nominal Output Impedance Configuration Dependent. 12 mA Drive

Internal Pull Up/ Pull Down

Resistor

VDD = 3.3 V

VDD = 2.5 V

Configuration Dependent

Programmable Internal

Crystal Load Capacitance

Resolution

Input Capacitance Pins PD#, SEL[1:0], OE[2:0]

0.65 V

DD

0.85 V

DD

0

0

4.36

22

50

80

0.05

4

20

V

DD

V

DD

0.35 V

DD

0.15 V

DD

20.39

6

Unit

mA mA m

A

V

V

W k

W pF pF

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NB3H63143G

DC ELECTRICAL CHARACTERISTICS

(continued)

(V

DD

= 3.3 V

±

10%, 2.5 V

±

10%, VDDO[2:0] = 3.3 V

±

10%, 2.5 V

±

10%, 1.8 V

±

0.1V; GND = 0 V, T

A

= −40

°

C to 85

°

C, Note 7)

Symbol Parameter Condition Min Typ Max

LVCMOS/LVTTL OUTPUTS

V

OH

Output HIGH Voltage

VDDO = 3.3 V

I

I

I

OH

= 4 mA

I

OH

= 8 mA

OH

= 12 mA

OH

= 16 mA

0.75xVDDO

VDDO = 2.5 V

VDDO = 1.8 V

I

I

I

OH

I

OH

OH

= 2 mA

= 4 mA

= 8 mA

OH

= 12 mA

I

I

OH

I

OH

OH

= 1 mA

= 2 mA

= 4 mA

I

OH

= 8 mA

V

OL

Output LOW Voltage 0.25xVDDO

I

DDO_LVCMOS

LVCMOS Output Supply

Current

VDDO = 3.3 V

VDDO = 2.5 V

I

I

I

OL

= 4 mA

OL

= 8 mA

I

OL

OL

= 12 mA

= 16 mA

I

OL

= 2 mA

I

I

I

OL

= 4 mA

OL

= 8 mA

OL

= 12 mA

VDDO = 1.8 V I

I

OL

= 1 mA

OL

= 2 mA

I

I

OL

= 4 mA

OL

= 8 mA

Configuration Dependent. T

CLK[0:2] = f out

Measured on VDDO = 3.3 V

A

= 25

°

C,

in PLL bypass mode f out

= 33.33 MHz, C

L f out f out

= 100 MHz, C

= 200 MHz, C

Measured on VDDO = 2.5 V

L

L

= 5 pF

= 5 pF

= 5 pF f out

= 33.33 MHz, C

L f out f out

= 100 MHz, C

= 200 MHz, C

Measured on VDDO = 1.8 V

L

L f out

= 33.33 MHz, C

L f out f out

= 100 MHz, C

= 200 MHz, C

L

L

= 5 pF

= 5 pF

= 5 pF

= 5 pF

= 5 pF

= 5 pF

6

16

32

4

12

24

3

8

16

Unit

V

V mA

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9

NB3H63143G

DC ELECTRICAL CHARACTERISTICS

(V

DD

= 3.3 V

±

10%, 2.5 V

±

10%, VDDO[2:0] = 3.3 V

±

10%, 2.5 V

±

10%, 1.8 V

±

0.1 V; GND = 0 V, T

A

= −40

°

C to 85

°

C, Note 19)

Symbol Parameter Condition Min Typ Max

HCSL OUTPUTS (Note 8)

Unit

V

OH_HCSL

Output HIGH Voltage (Note 9)

VDDO = 3.3 V, 2.5 V, 1.8 V

V

OL_HCSL

Output Low Voltage (Note 9)

VDDO = 3.3 V, 2.5 V, 1.8 V

V

CROSS

Crossing Point Voltage (Notes 10 and 11)

VDDO = 3.3 V, 2.5 V

Delta

V cross

Change in Magnitude of V cross

for HCSL Output (Notes 10 and 12)

VDDO = 3.3 V, 2.5 V

I

DDO_HCSL

Measured on VDDO0 = 2.5 V & 3.3 V with f out f out

= 100 MHz, CL = 2 pF

= 200 MHz, CL = 2 pF

LVDS OUTPUTS (Notes 10 and 13)

250

700

0

350

22

450

150 mV mV mV mV mA

V

OD_LVDS

Differential Output Voltage

DeltaV

OD_LVDS

Change in Magnitude of V

OD for Complementary Output States

V

OS_LVDS

Offset Voltage VDDO = 2.5 V / 3.3 V

VDDO = 1.8 V

Change in Magnitude of V

OS for Complementary Output States Delta

V

OS_LVDS

V

OH_LVDS

Output HIGH Voltage (Note 14) VDDO = 2.5 V / 3.3 V

VDDO = 1.8 V

I

V

OL_LVDS

DDO_LVDS

Output LOW Voltage (Note 15)

VDDO = 2.5 V / 3.3 V

VDDO = 1.8 V f f out

= 100 MHz out

= 200 MHz

LVPECL OUTPUTS (Notes 16 and 17)

V

OH_LVPECL

Output HIGH Voltage

I

V

OL_LVPECL

V

SWING

Vcross

DDO_LVPECL

Output LOW Voltage

Peak−to−Peak output voltage swing

Crossover point voltage (Note 17)

250

0

0

900

700

1200

900

1425

1100

1075

800

14

450

25

25

1600

1250 mV mV mV mV mV mV mA

VDDO = 2.5 V

VDDO = 3.3 V

VDDO−1450 VDDO−900

1600

2400

VDDO−825 mV

VDDO = 2.5 V

VDDO = 3.3 V

VDDO−2000 VDDO−1700

800

1600

VDDO−1500 mV

VDDO = 2.5 V

VDDO = 3.3 V

550

270

800 930

380 mV f f out

= 100 MHz out

= 200 MHz

25 mA

CML OUTPUTS (Notes 17 and 18)

V

OH_CML

Output HIGH Voltage mV

V

V

OL_CML

OD_CML

Vcross

Output LOW Voltage

Differential Output Voltage Magnitude

Crossover point voltage (Note 17)

VDDO = 3.3 V

VDDO = 2.5 V

VDDO −60

3240

2440

VDDO−10

3290

2490

VDDO

3300

2500

VDDO = 3.3 V

VDDO = 2.5 V

VDDO −1100

2200

1400

VDDO−800

2500

1700

VDDO − 640

2660

1860

640 780 1000

VDDO = 3.3 V

VDDO = 2.5 V

VDDO−395

VDDO = 3.3 V

VDDO = 2.5 V mV mV

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10

NB3H63143G

DC ELECTRICAL CHARACTERISTICS

(continued)

(V

DD

= 3.3 V

±

10%, 2.5 V

±

10%, VDDO[2:0] = 3.3 V

±

10%, 2.5 V

±

10%, 1.8 V

±

0.1 V; GND = 0 V, T

A

= −40

°

C to 85

°

C, Note 19)

Symbol Parameter Condition Min Typ Max Unit

CML OUTPUTS (Notes 17 and 18)

I

DDO_CML f f out

= 100 MHz out

= 200 MHz

5.0

mA

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm.

7. Measurement taken with single ended clock outputs terminated with test load capacitance of 5 pF and 15 pF and differential clock

terminated with test load of 2 pF. See Figures 6, 7 and 12. Specifications for LVTTL are valid for VDD and VDDO 3.3 V only.

8. Measurement taken with outputs terminated with RS = 0

W

, RL = 50

W

, with test load capacitance of 2 pF. See Figure 8. Guaranteed by

characterization.

9. Measurement taken from single ended waveform.

10. Measured at crossing point where the instantaneous voltage value of the rising edge of CLKx+ equals the falling edge of CLKx−.

11. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement.

12. Defined as the total variation of all crossing voltage of rising CLKx+ and falling CLKx−. This is maximum allowed variance in the VCROSS for any particular system.

13. LVDS outputs require 100

W

receiver termination resistor between differential pair. See Figure 9.

14. VOHmax = VOSmax + 1/2 VODmax.

15. VOLmax = VOSmin − 1/2 VODmax.

16. LVPECL outputs loaded with 50

W

to VDDO1 − 2.0 V for proper operation.

17. Output parameters vary 1:1 with VDDO1.

18. CML outputs loaded with 50

W

to VDDO1 for proper operation.

19. Parameter guaranteed by design verification not tested in production.

AC ELECTRICAL CHARACTERISTICS

±

0.1 V; V

DDO

V

DD

, GND = 0 V, T

A

(V

DD

= 3.3 V

±

10%, 2.5 V

±

10%, VDDO[2:0] = 3.3 V

±

10%, 2.5 V

±

10%, 1.8 V

= −40

°

C to 85

°

C, Notes 19, 20, 23, 24 and 25)

Symbol Parameter Condition Min Typ Max

f out

Single Ended Output

Frequency

0.008

200 f

MOD

Spread Spectrum Modulation

Rate fclkin

6.75 MHz 30 130

SS

SSstep

Percent Spread Spectrum

(deviation from nominal frequency)

Percent Spread Spectrum

Change Step Size

Down Spread

Center Spread

Down Spread Step Size

0

0

0.25

−4

±

3

Center Spread Step Size 0.125

SSC

RED t

PU t

PD t

SEL t

OE1

Spectral Reduction,

3 rd harmonic

Stabilization Time from

Power−up

Stabilization Time from

Power Down

Stabilization Time from

Change of Configuration

Output Enable Time

@SS = −0.5%, f out

= 100 MHz, fclkin = 25 MHz Crystal, RES BW at

30 kHz, All Output Types

V

DD

= 3.3 V, 2.5 V with Frequency

Modulation ON

Time from falling edge on PD pin to

Tri−stated Outputs (Asynchronous)

With Frequency Modulation ON

−10

3.0

3.0

3.0

t

OE2

Eppm

Output Disable Time

Synthesis Error

Time from rising edge on OE pin to valid clock outputs (asynchronous)

Time from falling edge on OE pin to valid clock outputs (asynchronous)

Configuration Dependent

2/f out

(MHz)

2/f out

(MHz)

0

Unit

MHz ms kHz

%

%

%

% dB ms ms m s m s ppm

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11

NB3H63143G

AC ELECTRICAL CHARACTERISTICS

±

0.1 V; V

DDO

V

DD

, GND = 0 V, T

A

(continued)(V

DD

= 3.3 V

±

10%, 2.5 V

±

10%, VDDO[2:0] = 3.3 V

±

10%, 2.5 V

±

10%, 1.8 V

= −40

°

C to 85

°

C, Notes 19, 20, 23, 24 and 25)

Symbol Parameter Condition Min Typ Max Unit

SINGLE ENDED OUTPUTS (V

DD

= 3.3 V

±

10%, 2.5 V

±

10%, VDDO[2:0] = 3.3 V

±

10%, 2.5 V

±

10%, 1.8 V

±

0.1V; V

DDO

V

DD

−40 to 85

°

C) (Notes 19, 20, 23, 24 and 25)

, T

A

= t

JITTER−3.3 V

Period Jitter Peak−to−Peak 25 MHz xtal input, f out

= 100 MHz,

SS off, Configuration Dependent

(Note 25, see Figure 14)

100 ps

Cycle−Cycle Jitter 25 MHz xtal input, f out

= 100 MHz,

SS off, Configuration Dependent

(Note 25, see Figure 14)

100 t

JITTER−2.5 V

Period Jitter Peak−to−Peak

25 MHz xtal input, f out

= 100 MHz,

SS off, Configuration Dependent

(Note 25, see Figure 14)

100 ps t r

/ t t t f 3.3 V r 3.3 V r 2.5 V

Cycle−Cycle Jitter

Rise/Fall Time ns

1

2 t r

/ t t f 2.5 V

DC

Rise/Fall Time

Output Clock Duty Cycle

Measured between 20% to 80% with

15 pF load, f out

V

DD

= V

DDO

= 100 MHz,

= 2.5 V, Max Drive

Min Drive

V

DD

= 3.3 V, 2.5 V; V

DDO

V

DD

Duty Cycle of Ref clock is 50%

PLL Clock

Reference Clock

45

40

1

2

50

50

55

60 ns

%

DIFFERENTIAL OUTPUT (CLK1, CLK0) (V

V

DD

, T

A

DD

= 3.3 V

±

10%, 2.5 V

±

10%, VDDO[2:0] = 3.3 V

±

10%, 2.5 V

±

10%, 1.8 V

±

0.1V; V

= −40 to 85

°

C) (Notes 19, 20, 23, 24 and 25)

DDO t

JITTER−3.3 V

Period Jitter Peak−to−Peak 100 ps

Configuration Dependent. 25 MHz xtal input, f out

= 100 MHz, SS off, CLK2 =

OFF (Note 21, 23 and 25, see

Figure 14)

Cycle−Cycle Jitter 100 t

JITTER−2.5 V

Period Jitter Peak−to−Peak

Configuration Dependent. 25 MHz xtal input, f out

= 100 MHz, SS off, CLK2 =

OFF (Note 22, 23 and 25, see

Figure 14)

Configuration Dependent. 25 MHz xtal input, f out

= 100 MHz, SS off, CLK2 =

OFF (Note 22 and 24, see Figure 9)

100 ps

Cycle−Cycle Jitter 100

Rise Time

Rise Time

25 MHz xtal input, f out

= 100 MHz,

SS off, Configuration Dependent

(Note 25, see Figure 14)

Measured between 20% to 80% with

15 pF load, f out

V

DD

= V

DDO

= 100 MHz,

= 3.3 V, Max Drive

Min Drive

Configuration Dependent. 25 MHz xtal input, f out

= 100 MHz, SS off, CLK2 =

OFF (Note 22, 23 and 25, see

Figure 14)

Measured between 20% to 80%,

V

DD

= 3.3 V

LVPECL

LVDS

HCSL

CML

Measured between 20% to 80%,

V

DD

= 2.5 V

LVPECL

LVDS

HCSL

CML

175

175

100

700

700 ps ps

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12

NB3H63143G

AC ELECTRICAL CHARACTERISTICS

±

0.1 V; V

DDO

V

DD

, GND = 0 V, T

A

(continued)(V

DD

= 3.3 V

±

10%, 2.5 V

±

10%, VDDO[2:0] = 3.3 V

±

10%, 2.5 V

±

10%, 1.8 V

= −40

°

C to 85

°

C, Notes 19, 20, 23, 24 and 25)

Symbol Parameter Condition Min Typ Max Unit

DIFFERENTIAL OUTPUT (CLK1, CLK0) (V

V

DD

, T

A

DD

= 3.3 V

±

10%, 2.5 V

±

10%, VDDO[2:0] = 3.3 V

±

10%, 2.5 V

±

10%, 1.8 V

±

0.1V; V

= −40 to 85

°

C) (Notes 19, 20, 23, 24 and 25)

DDO t f 3.3 V

Fall Time Measured between 20% to 80% with

2 pF load, V

DD

= 3.3 V

LVPECL

LVDS

HCSL

CML

175 700 ps t f 2.5 V

Fall Time Measured between 20% to 80% with

2 pF load, V

DD

= 2.5 V

LVPECL

LVDS

HCSL

CML

175 700 ps t

DC

Output Clock Duty Cycle V

DD

= 3.3 V, 2.5 V;

Duty Cycle of Ref clock is 50%

PLL Clock

Reference Clock

45

40

50

50

55

60

%

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm.

20. Measurement taken from single ended clock terminated with test load capacitance of 5 pF and 15 pF and differential clock terminated with

test load of 2 pF. See Figures 6, 7 and 12.

21. Measurement taken from single ended waveform.

22. Measurement taken from differential waveform.

23. AC performance parameters like jitter change based on the output frequency, spread selection, power supply and loading conditions of the output. For application specific AC performance parameters, please contact ON Semiconductor.

24. Measured at f out

= 100 MHz, No Frequency Modulation, f

Parameter Measurement Test Circuits clkin

= 25 MHz fundamental mode crystal and output termination as described in

25. Period jitter Sampled with 10000 cycles, Cycle−cycle jitter sampled with 1000 cycles. Jitter measurement may vary. Actual jitter is dependent on Input jitter and edge rate, number of active outputs, inputs and output frequencies, supply voltage, temperature, and output load.

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13

NB3H63143G

SCHEMATIC FOR OUTPUT TERMINATION

Figure 6. Typical Termination for Single Ended and Differential Signaling Device Load www.onsemi.com

14

NB3H63143G

PARAMETER MEASUREMENT TEST CIRCUITS

CLKx

LVCMOS/LVTTL

Clock

CL

Hi−Z Probe

Measurement

Equipment

Figure 7. LVCMOS/LVTTL Parameter Measurement

CLK1

HCSL

Clock

CLK0

50

W

2 pF

Hi−Z Probe

50

W

2 pF

Hi−Z Probe

Measurement

Equipment

Figure 8. HCSL Parameter Measurement

CLK1

LVDS

Clock

CLK0

100

W

Hi−Z Probe

Hi−Z Probe

Measurement

Equipment

Figure 9. LVDS Parameter Measurement

CLK1

LVPECL

Clock

CLK0

Hi−Z Probe

Hi−Z Probe

50

W

50

W

VDDO1 − 2 V

Figure 10. LVPECL Parameter Measurement

Measurement

Equipment

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15

NB3H63143G

CLK1

CML

Clock

CLK0

Hi−Z Probe

Hi−Z Probe

50

W

50

W

VDDO1

Figure 11. CML Parameter Measurement

Measurement

Equipment

TIMING MEASUREMENT DEFINITIONS

LVCMOS

Clock Output t

R t

1 t

2 t

DC

= 100 * t

1

/ t

2

VDDO

80% of VDDO

50% of VDDO

20% of VDDO

GND t

F

Figure 12. LVCMOS Measurement for AC Parameters

t

1 t

2 t

DC

= 100 * t

1

/t

2 t

Period

= t

2

80% 80% t

R

Vcross = 50% of output swing

20% 20% t

F

Figure 13. Differential Measurement for AC Parameters

D

Vcross

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16

NB3H63143G

t period−jitter

50% of CLK Swing

Clock

Output t

Ncycle t

(N+1)cycle

Clock

Output

OE

CLK Output

With Hi-Z in disable mode

CLK Output with output

Low in disable mode

PD# t

CTC−jitter

= t

(N+1)cycle

− t

Ncycle (over 1000 cycles)

Figure 14. Period and Cycle−Cycle Jitter Measurement

Toutput disable

Toutput enable

VIH

VIL

ÏÏÏÏÏÏ

High-Z

ÏÏÏÏÏÏ

ÏÏÏÏÏÏ

Tpower-down

Tpower-up

VIH

VIL

50% of CLK Swing

CLK Output

Figure 15. Output Enable/ Disable and Power Down Functions www.onsemi.com

17

NB3H63143G

Crystal Input Interface

APPLICATION GUIDELINES

oscillator interface using a typical parallel resonant fundamental mode crystal. A parallel crystal with loading capacitance CL = 18 pF would use C1 = 32 pF and C2 =

32 pF as nominal values, assuming 4 pF of stray capacitance per line.

C

L

+

(C1

)

Cstray) ń

2; C1

+

C2

The frequency accuracy and duty cycle skew can be fine−tuned by adjusting the C1 and C2 values. For example, increasing the C1 and C2 values will reduce the operational frequency. Note R1 is optional and may be 0

W

.

Output Interface and Terminations

The NB3H63143G consists of a unique Multi Standard

Output Driver to support LVCMOS/LVTTL, LVPECL,

LVDS, HCSL and CML standards. Termination techniques required for each of these standards are different to ensure proper functionality. From the device it is possible to switch off one output driver and turn on another output driver using the SEL[1:0] pins as part of the Configuration Settings. The required termination changes must be considered and taken care of by the system designer.

LVCMOS/LVTTL Interface

LVCMOS/LVTTL output swings rail−to−rail up to

VDDO supply (minimum 1.8 V) and can drive up to 15 pF load at higher drive stengths. The output buffer’s drive is programmable up to four steps, though the drive current will depend on the step setting as well as the VDDO supply

voltage. (See Figure 17 and Table 8). Drive strength must be

configured high for driving higher loads. The slew rate of the clock signal increases with higher output current drive for the same load. The software lets the user choose the load drive current value per LVCMOS/LVTTL output based on the VDDO supply selected.

Figure 16. Crystal Interface Loading

Table 8. LVCMOS/LVTTL DRIVE LEVEL SETTINGS

VDDO Supply

3.3 V

2.5 V

1.8 V

Load Current Setting 3

Max Load Current

16 mA

12 mA

8 mA

Load Current Setting 2

12 mA

8 mA

4 mA

Load Current Setting 1

8 mA

4 mA

2 mA

Load Current Setting 0

Min Load Current

4 mA

2 mA

1 mA

The IDDO current consists of the static current component (varies with drive) and dynamic current component. For any VDDO, the IDDO dynamic current range per LVCMOS output can be approximated by the following:

IDDO

+ f out

* C load

* VDDO

C load

includes the load capacitor connected to the output, the pin capacitor posed by the output pin (typically 5 pF) and the cap load posed by the receiver input pin. C load

= (CL +

C pin

+ C in

)

An optional series resistor Rs can be connected at the output for impedance matching, to limit the overshoots and ringings.

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18

NB3H63143G

VDD

Drive Strength selection

Drive Strength selection

CLKx

Figure 17. Simplified LVCMOS Output Structure

LVDS Interface

Differential signaling like LVDS has inherent advantage of common mode noise rejection and low noise emission, and thus a popular choice for clock distribution in systems.

TIA/EIA−644 or LVDS is a standard differential, point−to−point bus topology that supports fast switching speeds and has the benefit of low power consumption. The driver consists of a low swing differential with constant current of 3.5 mA through the differential pair, and generates switching output voltage across a 100

W

VDDO

Iss terminating resistor (externally connected or internal to the receiver). Power dissipation in LVDS standard ((3.5 mA)

2 x

100

W = 1.2 mW) is thus much lower than other differential signalling standards.

A fan−out LVDS buffer (like ON Semiconductor’s

NB6N1xS and NB6L1xS) can be used as an extension to provide clock signal to multiple LVDS receivers to drive multiple point−to−point links to receiving node.

CLK 1

CLK 0

RT

100

W

+

Vout

_

+

_

Vin

Iss

Figure 18. Simplified LVDS Output Structure with Termination www.onsemi.com

19

NB3H63143G

LVPECL Interface

The LVPECL driver is designed to drive a 50

W transmission line from a constant current differential and a low impedance emitter follower. On the NB3H63143G, this differential standard is supported for VDDO supply voltage of 2.5 V and above. In the system, the clock receiver must be referenced at the same supply voltage as VDDO for reliable functionality. The termination to receiver V

CC

− 2 V

(1.3 V for a 3.3 V VDDO supply, and 0.5 V for a 2.5 V

VDDO

VDDO supply) used in evaluation boards, is rarely used in system boards as it adds another power supply on the system

board. Thus, Thevenin’s equivalent circuit (Figure 20) for this termination or a Y−type termination (Figure 21) is often

used in systems. Termination techniques for LVPECL are detailed in the application note “Termination of ECL

Devices with EF (Emitter Follower) OUTPUT Structure −

AND8020”.

VCC - 2V

CLK1

50

W

CLK0

50

W

Isc

VDDO

NB 3H63143 G

CLK 1

CLK 0

Figure 19. Simplified LVPECL Output Structure with Termination

VCC

R1

R2

R1

R2

System Supply

2.5 V System

3.3 V system

Practical R2

(

W

)

62(5%)

82(5%)

Y−Termination

2.5 V System

3.3 V system

Figure 20. LVPECL Thevenin Termination

VDDO

NB 3H63143G

CLK1

CLK0

50

W

RT

50

W

Figure 21. LVPECL Y−Termaination

Practical R1 (

W

)

240(5%)

130(5%)

RT (

W

)

50

18

The termination should be placed as close to the receiver as possible to avoid unterminated stubs that can cause signal integrity issues.

CML Interface

A CML driver consists of an NMOS open drain constant current differential driving 16 mA current into a 50

W load terminated to the supply voltage at the receiver. This termination resistor can be external or internal to the receiver and needs to be as close as possible to the receiver.

On the NB3H63143G, this differential standard is supported for VDDO supply voltage 2.5 V and above. The termination techniques used for a CML driver are detailed in application note “Termination and Interface of ON Semiconductor ECL

Devices With CML (Current Mode Logic) OUTPUT

Structure − AND8173”

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20

NB3H63143G

50

W

CLK 1

CLK 0

VCC (receiver )

50

W

Isc = 16mA

Figure 22. Simplified CML Output Structure with Termination

HCSL Termination

HCSL is a differential signaling standard commonly used in PCIe systems. The HCSL driver is typical 14.5 mA switched current open source output that needs a 50

W termination resistor to ground near the source, and generates

725 mV of signal swing. A series resistor (10

W to 33 W) is optionally used to achieve impedance matching by limiting overshoot and ringing due to the rapid rise of current from the output driver. The open source driver has high internal impedance; thus a series resistor up to 33

W does not affect the signal integrity. This resistor can be avoided for low

VDDO supply (1.8 V) of operation, unless impedance matching requires it.

14 .5mA

2.6mA

CLK 1

CLK0

50

W

50

W

Figure 23. Simplified HCSL Output Structure with Termination

Field Programming Kit and Software

The NB3H63143G can be programmed by the user using the ‘Clock Cruiser Programmable Clock Kit’. This device uses the 16L daughter card on the hardware kit. To design a new clock, ‘Clock Cruiser Software’ is required to be installed from the ON Semiconductor website. The user manuals for the hardware kit Clock Cruiser Programmable

Clock Kit and Clock Cruiser Software can be found following this link www.onsemi.com

.

Recommendation for Clock Performance

Clock performance is specified in terms of Jitter in the time domain. Details and measurement techniques of

Cycle−cycle jitter, period jitter, TIE jitter and Phase Noise are explained in application note AND8459/D.

In order to have a good clock signal integrity for minimum data errors, it is necessary to reduce the signal reflections.

The reflection coefficient can be zero only when the source impedance equals the load impedance. Reflections are based on signal transition time (slew rate) and due to impedance mismatch. Impedance matching with proper termination is required to reduce the signal reflections. The amplitude of overshoots is due to the difference in impedance and can be minimized by adding a series resistor (Rs) near the output pin. Greater the difference in impedance, greater is the

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21

amplitude of the overshoots and subsequent ripples. The ripple frequency is dependant on the signal travel time from the receiver to the source. Shorter traces results in higher ripple frequency, as the trace gets longer the travel time increases, reducing the ripple frequency. The ripple frequency is independent of signal frequency, and only depends on the trace length and the propogation delay. For eg. On an FR4 PCB with approximately 150 ps/inch of propogation rate on a 2 inch trace, the ripple frequency = 1

/ (150 ps * 2 inch * 5) = 666.6 MHz; [5 = number of times the signal travels, 1 trip to receiver plus 2 additional round trips].

PCB traces should be terminated when trace length >= tr/f

/ (2* tprate); tf/t = rise/ fall time of signal, tprate = propagation rate of trace.

Overshoot

(Positive)

Ñ ÌÌ

Ringing

Overshoot

(Negative)

Ñ ÌÌ

Figure 24. Signal Reflection Components

NB3H63143G

PCB Design Recommendation

For a clean clock signal waveform it is necessary to have a clean power supply for the device. The device must be isolated from system power supply noise. A 0.1 mF and a

2.2 mF decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. No vias should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin and the ground via should be kept as thick and as short as possible.

All the VDD pins should have decoupling capacitors.

Stacked power and ground planes on the PCB should be large. Signal traces should be on the top layer with minimum vias and discontinuities and should not cross the reference planes. The termination components must be placed near the source or the receiver. In an optimum layout all components are on the same side of the board, minimizing vias through other signal layers.

Device Applications

The NB3H63143G is targeted mainly for the Consumer market segment and can be used as per the examples below.

Clock Generator

Consumer applications like a Set top Box, have multiple sub−systems and standard interfaces and require multiple reference clock sources at various locations in the system.

This part can function as a clock generating IC for such applications generating a reference clock for interfaces like

USB, Ethernet, Audio/Video, ADSL, PCI etc.

VDD PD# SEL0 SEL1

Reference

Clock

XIN/ CLKIN

Crystal

XOUT

25MHz

Input

Decoder

Clock Buffer/

Crystal

Oscillator And

AGC

Crystal /Clock Control

Configuration

Memory

Frequency and SS

Output control

Output

Divider

PLL Block

Phase

Detector

Charge

Pump

VCO

Output

Divider

Feedback

Divider

Output

Divider

PLL Bypass Mode

CMOS/

DIFF buffer

CMOS /

DIFF buffer

CMOS buffer

VDDO0

CLK0

OE0

VDDO1

27MHz

CLK1

OE1

VDDO2

48MHz

25MHz

CLK2

OE2

Video

USB

Ethernet

GND GNDO

Figure 25. Application as Clock Generator

Buffer and Logic/Level Translator

The NB3H63143G is useful as a simple CMOS Buffer in

PLL bypass mode. One or more outputs can use the PLL

Bypass mode to generate the buffered outputs. If the PLL is configured to use spread spectrum, all outputs using PLL

Bypass feature will not be subjected to the spread spectrum.

The device can be simultaneously used as logic translator for converting the LVCMOS input clock to LVPECL, LVDS,

HCSL, CML, or LVCMOS (with different output voltage level).

For instance in applications like an LCD monitor, for converting the LVCMOS input clock to LVDS output.

www.onsemi.com

22

NB3H63143G

SEL0 SEL1 VDD PD#

Reference

Clock

XIN/CLKIN

XOUT

LVCMOS

Input

Decoder

Crystal /Clock Control

Configuration

Memory

Frequency and SS

Output control

Output

Divider

Clock Buffer/

Crystal

Oscillator And

AGC

PLL Block

Phase

Detector

Charge

Pump

VCO

Output

Divider

Feedback

Divider

Output

Divider

PLL Bypass Mode

CMOS/

DIFF buffer

CMOS /

DIFF buffer

CMOS buffer

VDDO0

CLK0

OE0

VDDO1

CLK1

OE1

VDDO2

CLK2

OE2

LVDS

LVCMOS

GND GNDO

Figure 26. Application as Level Translator

NOTE: Since the device requirement is VDDO

VDD, LVCMOS signal level cannot be translated to a higher level of LVCMOS voltage.

EMI Attenuator

Spread spectrum through frequency modulation technique enables the reduction of EMI radiated from the high frequency clock signals by spreading the spectral energy to the nearby frequencies. While using frequency modulation, the same selection is applied to all the PLL

VDD PD# SEL0 SEL1 clock outputs (not bypass outputs) even if they are at

different frequencies. In Figure 27, CLK0 uses the PLL and

hence is subjected to the spread spectrum modulation while

CLK1 and CLK2 use the PLL Bypass mode and hence are not subjected to the spread spectrum modulation.

Reference

Clock

XIN/ CLKIN

Crystal

XOUT

12MHz

Input

Decoder

Crystal /Clock Control

Configuration

Memory

Frequency and SS

Output control

Output

Divider

Clock Buffer/

Crystal

Oscillator And

AGC

PLL Block

Phase

Detector

Charge

Pump

VCO

Output

Divider

Feedback

Divider

Output

Divider

PLL Bypass Mode

GND GNDO

CMOS/

DIFF buffer

CMOS /

DIFF buffer

CMOS buffer

Figure 27. Application as EMI Attenuator

VDDO0

CLK0

12MHz +/- 0.375 %

OE0

VDDO1

USB1

CLK1

OE1

VDDO2

12MHz

12MHz

CLK2

OE2

USB2

CPU

ORDERING INFORMATION

Device

NB3H63143G00MNR2G

Case

485AE

Package

QFN−16

(Pb−Free)

Type

Blank Device

Shipping

3000 / Tape & Reel

NB3H63143GxxMNR2G 485AE QFN−16

(Pb−Free)

Factory Pre−programmed

Device

3000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

†Note: Please contact your ON Semiconductor sales representative for availability in tube.

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23

NB3H63143G

PACKAGE DIMENSIONS

PIN 1

LOCATION

0.15 C

0.15 C

0.10 C

0.08 C

NOTE 4

ÇÇ

ÇÇ

D

TOP VIEW

DETAIL B

(A3)

SIDE VIEW

A

B

E

A1

A

QFN16 3x3, 0.5P

CASE 485AE

ISSUE B

L

L1

DETAIL A

ALTERNATE TERMINAL

CONSTRUCTIONS

EXPOSED Cu MOLD CMPD

ÉÉÉ ÉÉ

A3

ÉÉÉ ÉÉÉ

A1

DETAIL B

ALTERNATE

CONSTRUCTIONS

L

ÇÇ ÉÉ

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

5. OUTLINE MEETS JEDEC DIMENSIONS PER

MO−220, VARIATION VEED−6.

MILLIMETERS

D

D2

E

E2 e

K

L

L1

DIM MIN

A

0.80

A1

A3 b

0.00

MAX

1.00

0.05

0.20 REF

0.18

0.30

3.00 BSC

1.25

1.25

0.20

0.30

0.00

1.55

3.00 BSC

1.55

0.50 BSC

−−−

0.50

0.15

C

SEATING

PLANE

D2

16X

L

DETAIL A

5

4

8

9

RECOMMENDED

SOLDERING FOOTPRINT*

3.30

16X

0.65

PACKAGE

OUTLINE

16X K

E2

1

1

12

3.30

0.10 C

0.05 C

16X b

A B

NOTE 3

16 13 e e/2

BOTTOM VIEW

16X

0.30

0.50

PITCH

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: [email protected]

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5817−1050

www.onsemi.com

24

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative

NB3H63143G/D

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