Click here to IC600BF827 PDF for more information.

Click here to IC600BF827 PDF for more information.
SERIES SIX
PROGRAMMABLE
GEK-83545
CONTROLLERS
HIGH SPEED COUNTER
GENERAL DESCRIPTION
The High Speed Counter is an intelligent I/O module and
can be utilized in an I/O rack, or in any of the I/O slots in
a Mode1 60 CPU, to solve a wide variety of position and
velocity measurement/control applications where the frequency of incoming pulses is too high to be handled
directly by the Series Six CPU. Features and Benefits for
this module are summarized in Table 1.
This microprocessor based counter is capable of receiving
count pulses from quadrature encoders, digital
tachometers, and mechanical or transistor switches Input
voltage levels are jumper configurable to accept TTL
Single Ended, TTL Differential, or 10-30 VDC signals.
Four open-collector transistor outputs are provided for
real time response independent of CPU scan time. Each
output can sink up to 250 ma at voltages up to 30V. Individual pull-up resistors are also provided. The module can
accept pulse rates of 50 KHz per channel. The accumulated count is stored as a 24 bit 2’s complement number
giving a counting range of -8,388,607 to + 8,388,607.
A total of 12 software preset registers are supported by
the High Speed Counter module. Four of these presets
control the four real time outputs while the remaining
eight can be used in CPU relay logic. Each preset value
can be individually set by the CPU. It is then continuously
compared to the accumulated count by the modules
microprocessor. The user can determine the sense of the
comparison, selecting between having the output turn on
when the accumulated count is less than (<) or greater
than or equal to> the preset value. User logic in the CPU
can individually set the four real time outputs to be
enabled/disabled, and/or latched/unlatched. Additional
capabilities allow the user to enable/disable counting,
select count direction, reset the accumulated count to a
predetermined value, or dynamically change any of the I2
software preset registers.
Since this intelligent I/O module resides in the Series Six
I/O structure, multiple counter modules can be utilized.
Each counter will use 32 Input and 32 Output addresses by
which the CPU downloads preset and mode select data
and by which position and status data is received.
GEK-83545
High Speed Counter
TABLE 1,
FEATURES AND BENEFITS
FEATURES
2
BENEFITS
Accepts many types of counting input
Quadrature encoder
Digital tachometer
Transistor/photo switch
Mechanical contacts
Provides direct and isolated inputs for multiple types
of field devices
Counting rate to 5OKHz
Xl, X2, X4 count input for quadrature
input to 200KHz
M a x i m u m c o u n t : -8,388,608 t o
+ 8,388,607
Provide high speed pulse input over wide count range,
no need to cascade counters
Four external outputs
Individual preset comparisons can be
<, or >, to accumulated count
Individual enable/latch functions
,500 micro-second response time
Sink 250ma, TTL to 30 VDC
Control multiple field devices, for fast, high speed
application
Eight internal presets for CPU use
Individual preset comparisons can be
<, or > to accumulated count
Functions as programmable limit switch whose bits
can be read by the CPU and used to control logic based
on accumulated count.
Internal/External Signals for
Count enable
Count direction
Count reset
Marker
Home position
Added dimensions for flexible, real world applications
Calculate the number of counts occurring during a
user-defined time period.
Returns counts/timebase (velocity) value for use in
digital speed regulation programs
Continued operation of counter if CPU is placed offline or fails
Maintain accurate position count and control of connected loads
Built-in diagnostics,
information
Detects system faults and alerts CPU logic and operator
indicators and CPU status
I
High Speed Counter
GEK-83545
TABLE 2. SPECIFICATIONS
Dimensions:
Circuit Board
8.15 x 11.0 x 1.20 (inches)
208 x 280 x 31 (mm)l5.0V
Faceplate
12.46 x 1.175 (inches)0.2V
317 x 30 (mm)
Power requirements
5 VDC, l.lA maximum
Supplied by I/O rack power supply
Units of Load = 19
User Supplied
1 o-3ov
TTL
Voltage 5V + 0.20 VDC 10-30V + .5 VDC
Ripple
100mv
Iv
Current
400ma
400ma
Timing Characteristics
Input Pulse Rate: DC to 5OKHz
(square wave)
Input Pulse Rate with filter selected:
DC to 1OOHz (square wave)
M a r k e r P u l s e W i d t h : 5 usec
(minimum)
Response time for outputs l-4 to
incoming pulses: 500 usec (typ)
5 Volt Differential Input Characteristics
Inputs are RS422 compatible
Maximum Input Voltage: +- 15.OV
Common Mode Voltage Range: 3- 7.OV
Threshold Sensitivity: f 0.2V
Input Impedance: 115 ohms (TYP.)
Minimum Input Current: + 3.0ma
l0-30V s i n g l e e n d e d s o u r c e i n p u t
characteristics.
Maximum Input Voltage: 33V
Minimum Turn-On Voltage: 9V
Minimum Input Voltage: -20V
Maximum Turn-off Voltage: 2V
Input Impedance: 3800 ohms (TYP)
Output Characteristics
Outputs are open collector with a common
clamp diode (CLP) provided for optional connection to positive source.
Pull-up resistors provided for outputs.
PUl = 1100 ohm.
PU2, PU3, outputs. PU4 = 4700 ohm
Maximum Supply Voltage: 30 VDC
TTL Single Ended Sink Input Characteristics
Maximum Input Voltage: 5.5V
Minimum Turn-On Voltage: 2.OV
Minimum Input Voltage: -1.5V
Maximum Turn-Off Voltage: 0.8V
Input Impedance: 1000 ohms (TYP)
Minimum Low Level Input Current:
-6.Oma (sinking)
Maximum On-State Voltage Drop:
0.4V for: I 50ma
0.70 for: 1250ma
Maximum Output Current:
250ma continuous
500ma peak for 1 second
Operating Temperature:
0-60°C (at outside of rack)
Storage Temperature: -20° to + 80°C
Humidity: 5-95%
(non-condensing)
Altitude: Up to 10,000 feet above sea level
GEK-83545
High Speed Counter
ITEM
01
02
03
04
05
FUNCTION FOR USER SETTINGS
Faceplate with lens and 36-point connector.
LED for OUT 1; when ON, indicates output 1 is energized.
LED for OUT 2; when ON, indicates output 2 is energized.
LED for count; when blinking, indicates pulses are being received.
LED for Board OK; when ON, Board passed diagnostic test.
ITEM
DIP SWITCH
~_ _-
FUNCTION
-~--
6
SW1 O p e n *
SW2 Open*
SW3 Open*
SW4 Closed
Input A Filter
Input B Filter
Input C Filter
Input D Filter
Switch Open: 100 Hz Filter Disabled
Switch Closed: 100 Hz Filter Enabled
Set to Closed position if input is connected to a device using dry contacts,
or other non-solid state device.
ITEM
__._-
JUMPERS
7
JPl
FUNCTION FOR USER SETTINGS
Run - Normal Use
Factory Test
l-2*
2-3
8
9
JP2
l-2*
If the CPU RESET signal is high, the counter will continue to function,
except outputs 1 thru 4 will be forced off regardless of their previous
state. When the CPU once again becomes operational, the four outputs
will return to their conditional state as determined by the enable/disable
and latch/unlatch bits and the preset comparison state.
2-3
If the CPU RESET signal is high, the counter will continue to function,
and will retain full control over its four outputs.
JP3
Not Used
Not Used
l-2*
2-3
* Factory Setting
FIGURE 2.
6
CONFIGURABLE USER SETTINGS (PART 2 OF 3)
GEK-83545
High Speed Counter
HARDWARE INTERFACE
All external wiring connections to the High Speed counter
module are made via the 36point terminal connector on
the module faceplate. Table 3 details the function of each
terminal point. Please note that all terminals with the
same name (i.e. COM, + 5V, +HV, SHD) are internally
TABLE 3.
connected when the terminal strip is connected to the
printed circuit board, If shielded cable is used, system
earth ground is provided via faceplate to chassis connection and the grounding of the chassis enclosure. For typical wiring diagrams refer to Figure 3 and 4.
TERMINAL WIRING DESCRIPTION
TERMINAL
NUMBER
NAME
FUNCTION
1,2,3
COM
Common ground connection.
4,5,6,7
+5v
User power supply positive connection for 5V operation.
8, 9, 10, 11
+HV
User power supply positive connection for l0-30V operation.
12
CLP
Clamp diode connection. Protects outputs from inductive kick-back from
the load. The CLP terminal should be jumpered to the positive side of
the output power supply.
13
01
14
PUl
Open collector sink output. TTL compatible up to 50ma. Outputs can sink
250 ma. continuous, 500 ma. peak. The maximum supply voltage is 30V.
If the PUl terminal is connected to the positive terminal of the output
suppIy, the output will be pulled up through a 1100 ohm resistor. This
output can drive the Series Six interrupt input board using a 24-30V
power supply.
15
02
16
PU2
17
03
18
PU3
19
04
20
PU4
Open collector sink output. TTL compatible up to 50 ma. Outputs can
sink 250 ma, continuous, 500 ma. peak. The maximum supply voltage is
30V. If the PU4 terminal is connected to the positive terminal of the
output supply, the output will be pulled up through a 4700 ohm pull-up
resistor.
21
AH
These terminals form the IN A input. The settings of JP6 and JP10 determine the input type (see Figure 2).
22
AL+
23
AL-
In the COUNTER mode IN A is used for the incoming square wave
pulses.
24
SHD
In the ENCODER mode this input is used for quad A of the encoder.
Open collector sink output. TTL compatible up to SOma. Outputs can sink
250 ma. continuous, 500 ma. peak. The maximum supply voltage is 30 V.
If the PU2 terminal is connected to the positive terminal of the output
supply, the output wiI1 be pulled up through a 4700 ohm pull-up resistor.
’
/
Open collector sink output. TTL compatible up to 50 ma. Outputs can
sink 250 ma. continuous, 500 ma. peak. The maximum supply voltage is
30V. If the PU3 terminal is connected to the positive terminal of the
output supply, the output will be pulled up through a 4700 ohm pull-up
resistor.
I
11
GEK-83545
High Speed Counter
TABL E
3.
TER M I N A L
WIRING
DESC RIPTION
(CONTINUED)
TERMINAL
NUMBER
NAME
FUNCTION
25
BH
These terminals form the IN B input. The settings of JP7 and JPl 1 determine the input type (see Figure 2).
26
BL+
27
BL-
28
SHD
In the COUNTER mode these terminals are used for the count direction
control. With no signal applied the count direction is UP. If the direction
is to be controlled via software, the input should be disabled, or not
connected. Up.Down is controlled in software by bit 10 of the Discrete
command (see Figure 9).
In the ENCODER mode this input is used for quad B of the shaft encoder.
29
CH
30
CL+
31
CL-
32
SHD
These terminals form the IN C input. The settings of JP8 and JP12 determine the input type (see Figure 2).
In the COUNTER mode these terminals are used as a counter enable
control. With no signal applied the counter is ENABLED. If the counter
enable is to be controlled by software command, IN C should be
disabled, or not connected. Enable/Disable is controlled in software by
Bit 9 of the Discrete Command (see Figure 9).
In the ENCODER mode this input is used for the marker pulse of the
shaft encoder. If there is no marker present then no connection should be
made to this input
33
DH
34
DL+
35
DL-
36
SHD
These terminals form the IN D input. The settings of JP9 and JP13 determine the input type (see Figure 2).
In the COUNTER mode the IN D input is used to reset the counter. The
reset function forces the accumulated count to the Lower Count Limit.
The reset condition will exist as long as the IN D signal is asserted. With
no signal applied the counter is NOT RESET. The count can also be reset
by software command. IN D should be disabled or not connected if software control is used. Reset is controlled in software by Bit 19 of the Discrete Command (see Figure 9).
In the ENCODER mode the IN D input is used to establish
position. When the HOME command is active and the IN D limit
is asserted, the next marker pulse will cause the accumulated count
set to the home position value. After the marker occurs, incoming
will be counted, and will represent an offset from HOME position.
12
home
switch
to be
pulses
GEK-83545
High Speed Counter
GENERAL DESCRIPTION OF OPERATION
The intelligent High Speed Counter module receives cornmand data from the Series Six CPU logic program and returns count and status data to the CPU. These data transfers requires 32 input and 32 output points. There are also
four input circuits and four output circuits for connection
to field devices. Refer to Table 3 for a full description of
each.
In the Encoder mode the inputs have the following
meanings:
INA
INB
INC
The High Speed Counter card has two basic modes of operation (counter or encoder) which are selectable by
means of a jumper. The functions of the inputs depends
on the mode of operation selected.
In the Counter mode the inputs are defined as follows:
INA
INB
INC
IND
Pulse Input: connected to the pulses to
be counted.
Direction Input: controls the direction of
counting.
Enable/Disable Input: used to enable or
disable counting.
sets the Accumulate
Reset Input:
register to the Lower Count Limit and
inhibits counting while active.
IND
Quad A Input: connected to channel A
of the quadrature encoder.
Quad B Input: connected to channel B of
the quadrature encoder.
Marker Input: connected to the marker
channel of the encoder.
Limit Switch Input: used to establish
True Home Position.
Each input is provided with a selectable filtering network.
When the filter is selected, the frequency response of the
input is limited to 1OOHz (square wave). The filter is normally used for debouncing mechanical contacts.
When the ENCODER mode is selected, one of three
counting rates: Xl, X2, or X4 can be jumper selected by
the user. When the COUNTER mode is selected, the
jumper must be placed in the Xl position. Figure 8 shows
the effect of this jumper selection for when quadrature
encoders are used.
1
INA
I
INB *
I
I
I
Xl
PC-96-84-01 69
TIME __+c
FIGURE 8.
Ref. PC-S6-84-0189
QUADRATURE PULSE COUNTING
13
GEK-83545
High Speed Counter
The module contains an 8 bit counter which is read by the
counter software and used to maintain a 24 bit Accumulate register. The counting range of this register is
-8,388,608 to +8,388,607. Negative values are kept as 2’s
complement. The user can define the upper and lower
counting limits anywhere within this range (the Upper
Count Limit minus the Lower Count Limit must be greater than 128). When counting up, the Accumulate register
will be set to the Lower Count Limit after reaching the
Upper Count Limit plus one. When counting down, the
Accumulate register will be set to the Upper Count Limit
when reaching the Lower Count Limit minus one.
The four outputs are open collector transistors which can
provide TTL compatible levels. Individual pull-up resistors are provided to allow outputs to drive TTL or CMOS
logic without the use of external resistors. When used in
the open collector configuration, the outputs can sink 250
ma. of current and can accept up to 3OV. The output circuitry is optically isolated and detailed in Figure 7.
TABLE 4.
Accumulate
<, 2
Preset
3<<
3
7
The state of each of the four outputs is determined by a
combination of five factors:
1.
2.
3.
4.
5.
Preset/Accumulate Relationship ( < , 2)
Comparison Sense (Command # 35)
Disable/ Enable (Discrete Command)
Unlatch/Latch (Discrete Command)
Previous State of Output
How these factors control an output is shown in Table 4.
NOTE
Once an output has been turned on
through the conditions described in
Table 4, it can be latched on using discrete commands 15-18 (Refer to
Figure 9). Once an output is latched
on it will remain on regardless of
changes in the Disable/Enable or
Preset Comparison function. The
output will not be turned off until it is
unlatched, and the conditions in Table
4 are appropriate.
OUTPUT STATE TABLE
Comparison
Sense
(CMMD # 35)
Preset*
Comparison
Function
Disable/
Enable
output
State
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
1
0
1
0
0
0
1
1
0
0
1
0
Result of Preset Comparison is determined by the comparison sense (Command # 35), and the
Preset/Accumulate relationship (<, 3).
14
GEK-83545
High Speed Counter
When configured for open collector operation, outputs
can be paralleled. In conjunction with the preset compare
and enable/disable functions, custom ON/OFF switching
patterns can be established. It should be noted that the
counter does not monitor the state of the outputs.
Therefore, if a failure in that circuitry should occur, the
CPU delete “system” will not be aware of it.
In addition to the four outputs, the counter module provides eight programmable Internal Preset registers. CPU
logic can download preset limits which are then compared
to the accumulated count with the resultant state (true or
false) returned to the CPU.
Because the counter is an intelligent module, it is capable
of continued operation regardless of the operating state of
the CPU. This feature is selectable via a jumper and is conditioned upon the module being previously downloaded
with preset data from the CPU and the I/O rack and external power supplies being operational.
An external user-furnished power supply is required to
support the delete “field” isolated Input and Output logic.
The power supply may be 5 VDC or l0-30 VDC. If this, or
the rack power supply should lose power, the module
must be reloaded from the CPU. An appropriate status bit
will be set.
CPU INTERFACE
Communications between the High Speed Counter
module and the Central Processor Unit (CPU) is accomplished via 32 consecutive input and output bits. (I/O address selection is discussed under Installation.) Command
and preset data is transferred from the CPU to the counter
module, while board status, output status, accumulated
count, or counts/time-base is returned from the counter
to the CPU. A two way data transfer will occur with every
CPU I/O scan.
Since data is only transferred between the CPU and the
counter in the I/O scan, the user needs to consider carefully the use of the Suspend I/O instruction. The counter will
continue operation without communication to the CPU
when the I/O is suspended, but it will not be able to apprise the CPU of its status. In similar context, use of the
DO I/O instruction, which could poll the counter too
frequently, would tend to cause the module to respond
slowly to the degree that it may miss a pulse. To prevent
this, a minimum of 6 msec should elapse between I/O
scans that use the I/O addresses of the counter.
High Speed Counter
GEK-83545
DATA SENT FROM SERIES SIX CPU
The first 8 bits or the first byte of data transferred from
the CPU to the counter is referred to as the Command
Byte (CB), while the remaining 24 bits or 3 bytes are
referred to as the Command Data Bytes. This data uses 32
bits of the CPU output table.
COMMAND BYTE
CB
I
1 ST BYTE
1
Information contained in the Command Data Bytes is interpreted by the counter based upon the Command
Number contained in the Command Byte.
+---S
W E E P
LOGIC
I +-SWEEP~++SWEEP~+
l/O
If the CPU issues a command in Sweep 1 that requires a specific type of data to be returned, that
data will be returned in Sweep 2, and be available
for logic solutions in Sweep 3.
If a command is issued that does not request return
data, the previously requested data will continue to
be returned.
LOGIC
I/O
LOGIC
I/O
- A CPU SUSPEND I/O function will stop all communications to the counter module while allowing
it to continue in full operation.
-
A CPU DO I/O function, which addresses a specific
counter, can be used to download system
parameters. However, communications with the
counter must not occur more often than every 6
milliseconds.
If a command generates an error, that Error Code
will be returned in the next I/O sweep. Subsequent
sweeps will return data that was previously
requested.
16
Ref.
PC-S6-84-0190
PC-S&84-0191
High Speed Counter
GEK-83545
COMMAND BYTE (CB)
The Command Byte contains a Command Number that is
used to set up the operational characteristics of the High
Speed Counter. CPU logic selects the Command Number
to be executed in the counter module and places that
number in the Command Byte. One command is executed
per I/O scan. Once card set up is complete, the Command
Number is usually set to zero. The Command Data Bytes
contain the information necessary to complete the execution of the command specified. Table 5 contains a list of
all the commands along with a detailed description.
TABLE 5, COMMAND NUMBER
COMMAND
DECIMAL
VALUE
NUMBER
HEX
VALUE
lDEFINITION OF COMMAND
0
00
DISCRETE COMMANDS - Interpret data bits (9-32) as discrete commands as
detailed in Figure 9.
1
01
RESET CARD - Accumulated count and preset register are set to zero; outputs
are turned off and board returned to initial default conditions, diagnostic tests are
run, if tests are passed, the heartbeat will toggle and the Power-Up Bit of the Status
Byte will be set; all commands except the Reset Card command will be ignored
until this Power-Up Bit is cleared by Command 6. If the diagnostic tests fail an
error code will be returned on the next I/O scan and the Board OK LED is turned
off.
2
02
CONTINUE - This is a null command and the counter will continue to operate in
the previously commanded mode. When used, this command improves counter
processing time.
3
03
RETURN DISCRETE COMMAND - Return data bits (9-32) of Last Discrete
Command (CB =0) sent as detailed in Figure 11.
4
04
HOME POSITION - Used only in encoder mode. (Refer to Figure 13.) Data bytes
will contain value of Home Position location, all outputs are disabled and
unlatched, the Home Position Bit in the returned Status Byte is cleared and incoming count pulses are ignored, On first Marker Pulse (Input C) after Home Limit
Switch signal (Input D) is received: Home Position value is loaded into accumulate
register, incoming pulses will ADD/SUBTRACT from accumulate register to
track offset from Home Position, Home Position bit (SB=5) is set, and outputs
remain disabled. If, in Encoder Mode, Home Position Value is outside the Upper
or Lower Count Limit, or if another command is issued while the Home Command Bit is set, an error code will be returned. This command is active until Home
Position is found or Abort Home Position (CB=5) or Reset Card (CB= 1) is
issued.
5
05
ABORT HOME POSITION COMMAND - Used only in Encoder Mode; cancels
Command 4; count pulses are again accepted while outputs are held disabled. Outputs must be re-enabled via the Discrete Command (CB =O). Since Home Position
was not established and counting was disabled, the Accumulate Register value
should be used with caution. If not in the Counter Mode or if the Home Position
(Command 4) is not active, an error code will be returned.
6
06
CLEAR POWER-UP BIT - Sets Bit 2 of Status Byte to zero; this bit must equal
zero for the counter module to accept any command other than Reset Card
(CB= 1); bit will be set on power-up, external power supply failure, or after Reset
Card command is issued.
7
thru
15
07
thru
OF
Reserved for future use.
17
GEK-83545
High Speed Counter
TABLE 5.
COMMAND
NUM BER
(CONTINUED)
-r
COMMANL
DECIMAL
VALUE
NUMBER
HEX
VALUE
DEFINITION OF COMMAND
16
10
LOAD OUTPUT 1 PRESET REGISTER from Command Data Bytes
17
11
LOAD OUTPUT 2 PRESET REGISTER from Command Data Bytes
18
12
LOAD OUTPUT 3 PRESET REGISTER from Command Data Bytes
19
13
LOAD OUTPUT 4 PRESET REGISTER from Command Data Bytes
20
14
LOAD INTERNAL PRESET REGISTER 1 from Command Data Bytes
21
15
LOAD INTERNAL PRESET REGISTER 2 from Command Data Bytes
22
16
LOAD INTERNAL PRESET REGISTER 3 from Command Data Bytes
23
17
LOAD INTERNAL PRESET REGISTER 4 from Command Data Bytes
24
18
LOAD INTERNAL PRESET REGISTER 5 from Command Data Bytes
25
19
LOAD INTERNAL PRESET REGISTER 6 from Command Data Bytes
26
1A
LOAD INTERNAL PRESET REGISTER 7 from Command Data Bytes
27
1B
LOAD INTERNAL PRESET REGISTER 8 from Command Data Bytes
If Preset Value is above the Upper Count Limit or below the Lower Count Limit,
an error code will be returned and, the command will not be executed. Counter operation remains unchanged. Default value upon power-up is zero.
18
GEK-83545
High Speed Counter
TABLE 5.
COMMANC
DECIMAL
VALUE
NUMBER
HEX
VALUE
COMMAND
NUM BERS (CONTINUED)
lDEFINITION OF COMMAND
28
thru
31
1C
thru
1F
Reserved for future use.
32
20
LOAD ACCUMULATE REGISTER from Command Data Bytes-If new Accumulate Value is above the Upper Count Limit or below the Lower Count Limit, an
error code will be returned and, the command will not be executed. Counter operation remains unchanged, Default value upon power-up is zero.
33
21
LOAD UPPER COUNT LIMIT from Command Data Bytes-If Upper Count
Limit minus the Lower Count Limit is less than 128, an error code will be returned
and, the command will not be executed. Counter operation remains unchanged.
Default value upon power-up is 8,388,607 or 7FFFFF(HEX).
34
22
LOAD LOWER COUNT LIMIT from Command Data Bytes-If Upper Count
Limit minus the Lower Count Limit is less than 128, an error code will be returned
and, the command will not be executed. Counter operation remains unchanged.
Default value upon power-up is zero. Lower count limit is -8,388,608
or 800000
( HEX ).
35
23
LOAD PRESET COMPARISON SENSE - Interpret Command Data Bytes (bits
9-32) as detailed in Figure 10.
36
24
LOAD TIME BASE from Command Data Bytes- Sets time base in milliseconds
for measurement of count pulses/ time base for use in velocity feedback. If time
base is set outside of range 1 to 65,535 (milliseconds), an error code will be returned and, the command will not be executed. Counter operation remains
unchanged.
37
thru
47
25
thru
2F
Reserved for future use.
19
GEK-83545
High Speed Counter
TABLE 5.
COMMANL
DECIMAL
VALUE
20
NUMBER
HEX
VALUE
COMMAND NUMBERS (CONTINUED)
lDEFINITION OF COMMAND
48
49
50
51
52
53
54
55
56
57
58
59
30
31
32
33
34
35
36
37
38
39
3A
3B
RETURN
RETURN
RETURN
RETURN
RETURN
RETURN
RETURN
RETURN
RETURN
RETURN
RETURN
RETURN
OUTPUT 1 PRESET REGISTER
OUTPUT 2 PRESET REGISTER
OUTPUT 3 PRESET REGISTER
OUTPUT 4 PRESET REGISTER
INTERNAL PRESET REGISTER 1
INTERNAL PRESET REGISTER 2
INTERNAL PRESET REGISTER 3
INTERNAL PRESET REGISTER 4
INTERNAL PRESET REGISTER 5
INTERNAL PRESET REGISTER 6
INTERNAL PRESET REGISTER 7
INTERNAL PRESET REGISTER 8
60
thru
63
3c
thru
3F
Reserved for Future Use
64
40
RETURN ACCUMULATE REGISTER (CB = 32)
65
41
RETURN UPPER COUNT LIMIT (CB=33)
66
42
RETURN LOWER COUNT LIMIT (CB=34)
67
43
RETURN PRESET COMPARISON SENSE (CB=35)
68
44
RETURN TIME BASE (CB=36)
69
thru
255
45
thru
7F
Reserved for future use
High Speed Counter
GEK-83545
ACCUMULATED
<, 3
PRESET
COUNT
COMPARISON
SENSE
PRESET
COMPARlSON
FUNCTION
<
3
OFF (0)
OFF (0)
FALSE (0)
TRUE (1)
<
3
ON (1)
ON (1)
T R U E (1)
FALSE (0)
NOTE (Continued)
In the case of outputs, the output will be turned on when the Preset Comparison function is
true if it has been enabled (Refer to Table 4, and Figure 9). When the Preset Comparison
function is no longer true, the output will be turned off, unless it has been latched (Refer to
Figure 9).
The state of all Preset Comparison functions (FALSE = 0, TRUE = 11, can be returned to
CPU User Logic by giving the module discrete command # 21, return state of Preset Comparison functions (Refer to Figures 9, and 11).
Figure 10.
PRESET
COMPARISON
SENSE
(Continued)
23
High Speed Counter
GEK-83545
DATA RETURNED TO SERIES SIX CPU
The first 8 bits, or the first byte of data, transferred to the
CPU from the counter is referred to as the Status Byte,
while the remaining 24 bits or 3 bytes are referred to as
l-f-
R ETU R N
DATA
the Returned Data Bytes. This data uses 32 bits of the
CPU Input Table.
BYTES
k---
RDB
4TH
BYTE
3RD BYTE
STATUS BYTE ----d
SB
2ND BYTE
p-F?q p27mT-g
Information contained in the Returned Data Bytes is that
data which was requested via the Command Number contained in the Command Byte issued during the previous
I/O scan. The previously requested data type will be returned every I/O scan unless a new type of return data is
requested. Default returned data on power-up is the accumulated count value.
STATUS BYTE
8
7
6
5
4
1
3
2
Bit 4 - COUNTING ENABLED: This bit, when set to a
one (1) by the counter module, indicates that the counter
is enabled. The Count Enable command (CB=0, bit 9)
must be set to one (1) to enable counting. To Disable
counting, set bit 9 to zero (O), or in the Count Mode,
apply a signal to Input C.
1
1st BYTE
The Status Byte (SB) contains information pertaining to
the current operating status of the High Speed Counter.
This byte is updated and returned to the CPU every I/O
scan. Definition of the Status Byte bits is as follows.
Bit 1 - HEARTBEAT: This bit indicates if the board is
functional. It is toggled every time an I/O scan occurs
except during power-up diagnostics, Any failures of counter diagnostics will stop the heartbeat.
Bit 2 - POWER-UP: This bit is set by the module to a one
(1) whenever rack or external power is applied, either for
the first time or following a power dip. On power-up, the
counter will run its diagnostic tests and reset all internal
data registers to their default values.
A Reset Card Command (CB= 1) from the CPU will also
cause diagnostics to be executed and the Power-Up bit to
be set.
All commands (except Reset Card) will be ignored until
this bit is reset to zero (0) by the Clear Power-up Bit
Command (CB = 6).
Bit 3 - EXTERNAL POWER SUPPLY STATUS: This bit
is set to a one (1) whenever the external (user) power
supply is below 4.5V. When external power fails, the
Power-Up bit is set and the counter will run its diagnostic
tests and reset all data registers to their default values.
24
All commands (except Reset Card) will be ignored until
the Power-Up bit is reset to a zero (0) by the Clear Powerup Bit Command (CB = 6).
Bit 5 - HOME/DIRECTION: In the Encoder Mode this
bit indicates that Home Position has been established,
and is set to a one (1) when any of the following events
occur:
a.
After the Home Command (CB=4) is
issued, and the first Marker Pulse is received after the Home Limit Switch is
reached. Refer to Figure 14.
b.
A load Accumulate command (CB=32) is
issued.
C.
A Reset Accumulate to Lower Count
Limit (CB=O, bit 19) is issued.
This bit is reset to zero (0) on Power-up, Reset Command
(CB-O), or Home Command (CB=4).
In the Counter Mode this bit indicates the direction
count (0 = up, (1 = down). Direction is a function
Input B or the Up/Down Count command (CB=0,
10). Count direction is Up unless a signal is applied
Input B or CB=0, bit 10 is set to a one (1).
of
of
bit
to
Bits 6, 7, 8 - Returned Data Type: Interpretation of these
bits indicates the type of data being returned to the CPU
in the Return Data Bytes 2, 3, and 4. If an error code is
returned, the command that caused the error is ignored,
and count operation remains unchanged. (Refer to Table
6)
High Speed Counter
GEK-83545
TABLE 6.
F
Bit 6
0
0
0
I
1
0
1
1
0
1
0
RETURNED DATA TYPE
1
i
-
Data Returned
Accumulated Count (default on power-up)
Counts/Time base
Comparison States for Presets (see Figure 12)
Returned Data as requested in previous I/O scan
from commands 3,48-59, 65-68
Error Code (see Figure 13)
Future Use
Future Use
Future Use
25
GEK-83545
High Speed Counter
ERROR CODES
When the Status Byte bits 6, 7, 8 indicate an error code is
present (refer to Table 6), a binary number will be returned in the 2nd Byte indicating the particular Error
Code. If a command generates an error, that command
will be ignored and an Error Code will be present in the
Return Data Bytes of the next I/O scan. Subsequent
sweeps will return the previously requested data. Counter
operation remains unchanged from its current operating
mode whenever an error code is sensed. The data contained in the 3rd and 4th bytes is indeterminate. The
Error Codes are as follows.
HIGH SPEED COUNTER ERROR CODES
DECIMAL
VALUE
1
HEX
VALUE
1
DESCRIPTION OF ERROR
Invalid Home Position value - The valid Home Position value should be:
= Home Position < = UCL
LCL <
LCL = Lower Count Limit
UCL = Upper Count Limit
The command was not executed.
2
2
Invalid Home Command - While in Home Position mode no commands are
accepted. This error code will be generated if another Home command is issued
before Home position is achieved.
3
3
Invalid Home Command - Home command was issued while in counter mode.
4
4
Invalid Abort Home Command - Abort Home command was not executed because card is not in Home Position Mode, or Home position has already been
established.
5
5
Invalid Abort Home Command - Abort Home command was issued while in
counter mode.
6
6
Invalid Command Number - Command does not exist.
7- 10
I-A
Invalid Output (l-4) Preset Value - Valid preset values are:
LCL < =
Output (l-4) Preset < = UCL
The command was not executed.
FIGURE 12. ERROR CODES
27
GEK-83545
High Speed Counter
DECIMAL
VALUE
HEX
VALUE
11-18
B-12
DESCRIPTION OF ERROR
Invalid Internal Preset (l-8) Value - Internal Preset Value must lie between lower
count limit and upper count limit,
LCL d Internal Preset d UCL
The command was not executed.
19
13
Invalid Accumulate Value - Valid Accumulate values are:
LCL <
= Accumulate < = U C L
The command was not executed.
20
14
Invalid Upper Count Limit - Upper Count Limit minus Lower Count Limit should
be greater than or equal to 128. The command was not executed.
21
15
Invalid Lower Count Limit - Upper Count Limit minus Lower Count Limit should
be greater than or equal to 127. The command was not executed.
22
16
Invalid Time Base Value - Valid Time Base values are:
1< = Time Base < = 65535
23
17
Invalid Command; Power-up Bit Set - When the power-up bit (bit 2 of the Status
Byte) is set, the only commands the card will respond to are the Clear Power-up
Bit command and the Reset Card command. The command was not executed.
24
18
Diagnostic Failure* - Internal RAM test failed. After error is sent heartbeat will
die. Cycle power to reset this bit,
25
19
Diagnostic Failure* - External RAM failed. After error is sent heartbeat will die.
Cycle power to reset this bit.
26
1A
Diagnostic Failure* - EPROM test failed. After error is sent heartbeat will die.
Must re-cycle power.
27
1B
External Power Supply Failure - External power supply has gone out of tolerance.
Card will go through power-up sequence, and all default conditions will be
restored.
* If the High Speed Counter fails to pass its self-diagnostic tests, reseat the module
in the I/O rack and check power supplies. If the module does not respond properly
replace it and return the failed unit to G.E. for repairs or call our Service Number
804-978-5747.
FIGURE 12.
28
ERROR CODES (CONTINUED)
High Speed Counter
GEK-83545
HOME POSITION
LOCATION
IC VALUE LOADED AND
COUNTING RESUMED
1
COUNTS 4
Pc~sE-a4.0192
t
ROLL
1 . Set counter in Home Position Mode
Data Bytes will contain the numeric
Home Position Location. Counter
turned off and incoming count pulses
(CB=4). The
value of the
outputs are
are ignored.
2 . Advance guage towards the home position.
3 . When the Home Limit Switch is tripped, a signal is
received at Input D.
FIGURE 13.
Ref. PC-S&84-0192
I
I
:
CONVEYOR
The next Marker Pulse (Input C) from the Encoder C )
nals the True Home Position.
4 . The numeric value of the Home Position Location
is now loaded into the Accumulate Register and
counting resumed to track offset from the True
Home Position. The outputs remain disabled and
must be re-enabled by the CPU program.
HOME POSITION APPLICATION
29
GEK-83545
High Speed Counter
DATA DOWNLOAD USING THE REGISTER TABLE
INTRODUCTION
Since the High Speed Counter Module is capable of counting high frequency input pulses it can be used in applications involving quadrature encoders and high speed digital
tachometers and photosensors. The applications include
cam s w i t c h simulations, velocity measurement
applications, and position tracking applications. However,
before the HSC can be utilized in any application the
Series Six CPU must tell the counter via command data
how and when to react to the incoming pulses.
The following pages will present a method of downloading
command data to the High Speed Counter card through
the 32 consecutive input and output points that the
module occupies in a Series 6 system. The data download
routine is imbedded in a Demonstration program that
uses a Series 6 with an Extended Instruction Set, 1024
registers, and an I/O Simulator Unit with a BCD display,
16 toggle switch inputs and 16 LED outputs.
With the Demonstration Program the user can enter commands into a command table. The command table is
set-up within the Register Table of the CPU. The user
TABLE 7.
simply types the commands into the Register Table using
a Program Development Terminal (PDT) or a
WorkMaster. The program will step through the Register
Table transferring the commands one by one from the
table to the HSC.
In the Series Six system the I/O simulator uses input and
output addresses 1 through 32. The High Speed Counter
card is addressed at I/O points 33 through 64. Table 7 lists
all of the Inputs, Outputs and Register address references
that are used in the Demonstration Program.
OPERATION
The Demonstration Program is divided into two sections:
the Main Body and a Subroutine. The Main Body contains
the logic that performs the power up sequence required to
enable the counter. The Subroutine does the actual loading of the Command Data to the HSC module. Figures 14
and 15 illustrate the operation of the Main Body and the
Subroutine, respectively, in block diagram form. The
function of each logic block with the corresponding rung
numbers is described below.
INPUT/OUTPUT AND REGISTER ALLOCATION CHART
Reference
30
Description
01 to 16
33 to 64
l/O Simulator
High Speed Counter Module
01 to016
033 to 064
0201
0202
0203
0204
0205
0206 to 0230
0231,0232
0233
0234
I/O Simulator
High Speed Counter Module
Clear Power Up Bit
Initiate Register Download
Register Download In Progress
Register Download Complete
Command Byte Equals Zero
Detects Zero Data Byte Commands
Detects End of Register Table
Update Simulator LED Outputs
Indicates CB = 0 For Single Command Load
R12toR14
R15, R16
R17 to R20
R21
R22
R23
R24
Scratch Registers
Stores Counts Per Time Base
Scratch Registers
Stores Command Byte Data
Scratch Register
Storage For 3rd Data Byte
Pointer For Commands In the Register Table
R25 to R64
R65
Table of HSC Commands
Command Byte For Single Command Load
R66, R67
Data Bytes For Single Command Load
R74, R75
Return Data Bytes
GEK-83545
High Speed Counter
MAIN BODY OF PROGRAM
(Refer to Figure 14)
Clear Power Up:
Bit
This block sends CB = 6 to the HSC. The counter will only accept Command 1
(Reset Module) and Command 6 (Clear Power Up Bit) while the Power Up Bit is
set.
Rung Numbers: 24,25
Load Discrete:
Set Up Data
The HSC outputs (in the default state) after power up are disabled. Also after
power up the counter is disabled; meaning the HSC will ignore any incoming
pulses. Here the Command Byte is set to zero (Discrete Commands) to enable the
outputs and the counter.
Rung Numbers: 2 - 7
Initiate:
Register Load
This block contains the logic that initializes the register pointer to rest
at the first register in the Register Table. Also a latch is set up that controls the operation of the Subroutine. While Command Data is being downloaded the latch is
energized: if the last register in the table has been loaded the latch de-energizes,
which terminates Subroutine execution.
Rung Numbers: 24,26, 28
Last Register:
Loaded
Here a check is performed to determine if the last register in the table has been
loaded. As long as the register pointer has not reached the end of the table commands are downloaded to the HSC.
Rung Numbers: 27
HSC Count/Outputs:
Enabled and
Download Complete
If the above check is true all commands in the table have been downloaded and the
counter module will be enabled.
Rung Numbers: 28
Execute:
Subroutine
The Subroutine is executed one time to download a single corn mand from Register
Table to the High Speed card.
Rung Numbers: 29,43 - 80
31
GEK-83545
High Speed Counter
SUBROUTINE
(Refer to Figure I.51
Read Command:
Read the Command Byte from the register in the Register Table upon which the
register pointer resides. Store the Command Byte in a buffer register. (Increment
the pointer.)
Rung Numbers: 44
Last Register:
This block performs a check to determine if the previously read command resides
in the last register in the Register Table.
Rung Numbers: 44
‘0’ D.B.:
Command Detected
Here a check is performed to determine whether or not the command requires
Data Bytes.
Rung Numbers: 45 - 68
‘0’ Register:
Value
Clear 1st and:
2nd D.B.
If a zero Data Byte Command is detected clear the data byte buffer registers.
Rung Numbers: 70
Clear 3rd D.B.
Read 1st and:
2nd D.B.
(Increment Pointer.)
Read 3rd D.B.:
Read the 3rd Data Byte and store it in a buffer register.
Rung N u mbers: 72
Load Command:
Byte
Load the Command Byte from the storage register to the Output Table.
Rung N u.mbers: 73
Load 1st and:
2nd D.B.
Move the 1st and 2nd Data Bytes from the buffer storage register to the Output
Table.
Rung Numbers: 73
Load 3rd D.B.:
Move the 3rd Data Byte from its buffer register to the Output Table.
Rung Numbers: 73
33
GEK-83545
High Speed Counter
ENTERING
COMMAND
DATA
The High Speed Counter commands are entered into a
table that consists of a block of registers located in the
CPU Register Table. In the Demonstration Program the
first register in the table is R25 and the last register is R64.
Each command will occupy either one or three registers
depending upon the command. Commands that require
no Data Bytes use one register: commands that require
data use 3 registers.
TABLE 8.
For the Command Byte, the command number is entered
as a single precision decimal number into the Register
Table. The Data Bytes, if required, are entered as a
double precision number into the next two registers in
the table. The Figure 17 below illustrates how the commands would appear in the Register Table on a PDT.
CPU REGISTER TABLE
REGISTER 0025
00000 00000 00000 00000 00000
- 0000009999 00034 +0000009999
00000
00033
0017
0025
00000
00000
00000
+OOOOOOlOOO
00036
00064
0033
00000
00000
00000
00000 00000
00000
00000
0042
0024
0032
00000
00000
00000
00000
0040
0048
00000
00000
The above illustration shows four commands. Command
33 (Load Upper Count Limit) resides in R25. Located in
R26 and R27 are the Data Bytes (+ 9999) associated with
CB = 33. R28 contains the command to "Load the Lower
Count Limit" of the HSC (CB = 34). The data for this
command is located in R29 and R30 (-9999). R33 contains
a value of 64. CB = 64 (Return Accumulate Register)
does not require any Data Bytes, so the next command in
the table is located in R34.
NOTE
Command 64 could also have been entered into R31, and CB = 36 could
have been placed in R32. If Command
36 had been placed in R32 the Data
Bytes would be entered into R33 and
R34.
I/O
SIMULATOR
The I/O Simulator is used to activate the inputs that download the data to the HSC, latch the HSC outputs, load a
single command and reset the counter module. The
Series 6 CPU uses outputs on the simulator to display the
count or error codes, and provide diagnostic information
with the LED indicator lights. Figure 16 and Tables 7 and
8 give the simulator I/O functions.
The BCD display will display the accumulate count value
of the High Speed Counter by default. If the HSC module
generates an error code, the error code will be displayed.
TABLE 9. SIMULATOR INPUTS
Toggle Switch #
Function
11
Reset the High Speed Counter Module. Send CB =
1.
12
Clear the Power Up Bit and Download the Command Table to the HSC.
13
Abort the Home Search, Send CB = 5.
14
Reset the Accumulate Count Register to its Lower
Limit.
1.5 through 18
Latch/Unlatch HSC outputs 1 through 4.
19
Return Preset Comparison States.
110
Return the Counts per Time Base and Store the
number of counts in R15 and 16.
111
Load the single command located in R65, R66, and
R67. (R65 contains the Command Byte and R66
and R67 contains the Data Bytes.
35
GEK-83545
High Speed Counter
SIMULATOR
OUTPUTS
TABLE 10 SIMULATOR OUTPUTS
Function
LED Light #
36
01
Counting is Enabled
02
The Power Up Bit has been cleared and the commands have been downloaded.
03
Energized when the external power supply is out of
tolerance.
04
Turns on when an error condition exists.
0 5 through 0 8
Indicates the HSC Preset Comparison States when
switch 19 is “on“.
08
Energized when number on BCD display is
negative.
113 through 016
Reflects the HSC Outputs Preset Comparison
Senses as determined by CB = 35.
017 through 032
Simulator LED Display.
GEK-83545
High Speed Counter
ORDERING INFORMATION
Equipment
Catalog Number
Circuit Board without Faceplate
Faceplate
Circuit Board with Faceplate
IC600YB827A
IC600FP827A
IC600BF827A
CATALOG NUMBER REVISION SUFFIX
The equipment listed above having the catalog numbers shown and the same equipment
having a higher alpha suffix is designed for listing by UL for use as auxiliary control devices.
The equipment is a direct replacement for equipment having the same catalog number but a
lower alpha suffix.
The UL symbol on the nameplate means the product is listed by Underwriters Laboratories Inc. (UL Standard No. 508, Industrial Control Equipment, subsection Electronic
Power Conversion Equipment.)
For further information, contact your local GE Fanuc sales office.
GE FANUC AUTOMATION NORTH AMERICA, INC., CHARLOTTESVILLE, VIRGINIA
FEBRUARY, 1985
64
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement