UPD78098B Subseries User's Manual

UPD78098B Subseries User's Manual
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Notice
1.
2.
3.
4.
5.
6.
7.
All information included in this document is current as of the date this document is issued. Such information, however, is
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“Standard”:
8.
9.
10.
11.
12.
Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
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User’s Manual
µPD78098B Subseries
8-Bit Single-Chip Microcontrollers
µPD78095B
µPD78096B
µPD78098B
µPD78P098B
Document No. U12761EJ2V0UM00 (2nd edition)
Date Published December 2001 N CP(K)
©
Printed in Japan
1997
[MEMO]
2
User’s Manual U12761EJ2V0UM
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
FIP, IEBus, and QTOP are trademarks of NEC Corporation.
MS-DOS, Windows, Windows NT are either registered trademarks or trademarks of Microsoft Corporation
in the United States and/or other countries.
PC/AT and PC DOS are trademarks of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
Ethernet is a trademark of XEROX Corporation.
TRON stands for The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
User’s Manual U12761EJ2V0UM
3
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of September, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
4
User’s Manual U12761EJ2V0UM
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-3067-5800
Fax: 01-3067-5899
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829
J01.2
User’s Manual U12761EJ2V0UM
5
Major Revisions in This Edition (1/2)
Pages
Throughout
Description
Change of ordering numbers
µPD78095BGC-×××-3B9 → µPD78095BGC-×××-8BT
µPD78096BGC-×××-3B9 → µPD78096BGC-×××-8BT
µPD78098BGC-×××-3B9 → µPD78098BGC-×××-8BT
µPD78P098BGC-3B9 → µPD78P098BGC-8BT
p.53
Addition of Caution in 2.2.9 P120 to P127 (Port 12)
p.55, 56
Addition of recommended connection (I/O circuit) at output in Table 2-1 Pin I/O Circuit Types
p.79
Addition of Caution in Table 3-3 IEBus Register List
p.125
Modification of Figure 5-7 Format of Clock Select Register 1
p.143
Modification of Caution 2 in Table 6-4 INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger
Valid Edge
p.152
Change of Caution in Figure 6-8 Format of External Interrupt Mode Register 0
p.161
Change of Figure 6-19 Timing of Pulse Width Measurement Operation by Free-Running
Counter and One Capture Register (with Both Edges Specified)
p.163
Addition of Figure 6-21 CR01 Capture Operation with Rising Edge Specified
p.163
Change of Figure 6-22 Timing of Pulse Width Measurement Operation by Free-Running
Counter (with Both Edges Specified)
p.165
Change of Figure 6-24 Timing of Pulse Width Measurement Operation by Free-Running
Counter and Two Capture Registers (with Rising Edge Specified)
p.166
Change of Figure 6-26 Timing of Pulse Width Measurement Operation by Restart
(with Rising Edge Specified)
p.170
Change of TI00 pin input to count clock in Figure 6-31 Square-Wave Output Operation Timing
p.171
Addition of Note and modification of Caution in 6.5.7 One-shot pulse output operation (1)
One-shot pulse output using software trigger
p.171
Modification of (a) 16-bit timer mode control register 0 (TMC0) and Caution in Figure 6-32
Control Register Setting for One-Shot Pulse Output Operation Using Software Trigger
p.172
Change of setting value of TMC0 in Figure 6-33 Timing of One-Shot Pulse Output Operation
Using Software Trigger
p.173
Addition of Note in 6.5.7 One-shot pulse output operation (2) One-shot pulse output using
external trigger
p.173
Modification of Caution in Figure 6-34 Control Register Settings for One-Shot Pulse Output
Operation Using External Trigger
pp.175 to 177
Deletion of following items in 6.6 Cautions for 16-Bit Timer/Event Counter 0
(2) 16-bit compare register setting (when in clear & start mode entered on match between
TM0 and CR00)
(3) Operation after compare register change during timer count operation
(4) Capture register data retention timing
(6) Re-trigger of one-shot pulse
(a) One-shot pulse output using software
(b) One-shot pulse output using external trigger
(7) Operation of OVF0 flag
(a) OVF0 flag setting
6
User’s Manual U12761EJ2V0UM
Major Revisions in This Edition (2/2)
Pages
pp.176 to 178
Description
Addition of following items in 6.6 Cautions for 16-Bit Timer/Event Counter 0
(6) Re-trigger of one-shot pulse
(c) One-shot pulse output function
(7) Operation of OVF0 flag
(b) OVF0 flag clear
(8) Conflict operation
(9) Timer operation
(10) Capture operation
(11) Compare operation
(12) Edge detection
p.207
Change of Caution in Figure 8-2 Format of Timer Clock Select Register 2
p.210
Addition of Figure 8-4 Operation Timing of Watch Timer/Interval Timer
p.215
Modification of Figure 9-2 Format of Timer Clock Select Register 2
p.226
Modification of Figure 11-2 Format of Timer Clock Select Register 2
p.235
Addition of Caution in Figure 12-5 Format of A/D Current Cut Select Register
pp.241 to 242
Addition of 12.5 How to Read the A/D Converter Characteristics Table
p.245
Modification of (4) Pins ANI0/P10 to ANI7/P17 and (5) AVREF0 pin input impedance in 12.6
Cautions for A/D Converter
p.247
Addition of (9) A/D conversion result register (ADCR) read operation and (10) Timing at
which A/D conversion result is undefined in 12.6 Cautions for A/D Converter
p.382
Modification of Example of preventive measures in 16.4.4 Restrictions in UART mode
p.390
Addition of Remark in 18.2 Interrupt Source and Configuration
p.395
Addition of Caution 3 in Figure 18-2 Format of Interrupt Request Flag Register
p.398
Change of Caution in Figure 18-5 Format of External Interrupt Mode Register 0
p.427
Addition of 19.4 Example of Connection with Memory
p.437
Addition of Caution in 20.3 IEBus Controller Configuration
p.443
Addition of Note in Figure 20-16 Command Register Format (for Option Setting)
p.444
Addition of Notes in Figure 20-17 Format of Master Communication Control Register
p.446
Addition of description and Note 2 and Caution in Figure 20-19 Format of Status Register 2
pp.529 to 509
Modification of APPENDIX A DEVELOPMENT TOOLS and APPENDIX B EMBEDDED
SOFTWARE
The mark
shows major revised points.
User’s Manual U12761EJ2V0UM
7
PREFACE
Target Readers
This manual is intended for user engineers who wish to understand the functions of
the µPD78098B Subseries to design and develop its application systems and
programs.
The target products are as follows:
µPD78098B Subseries: µPD78095B, 78096B, 78098B, 78P098B
Purpose
This manual is intended to give users an understanding of the functions described
in the Organization below.
The µPD78098B Subseries manual is separated into two parts: this manual and the
Organization
instruction version (common to the 78K/0 Series).
µPD78098B Subseries
78K/0 Series
User’s Manual
User’s Manual
(This manual)
Instructions
Pin functions
CPU functions
Internal block functions
Instruction set
Interrupts
Explanation of each instruction
Other on-chip peripheral functions
How to Read This Manual
It is assumed that the readers of this manual have general knowledge in the fields
of electrical engineering, logic circuits, and microcontrollers.
To know the functional differences from the µPD78098 Subseries:
→ Refer to 1.9 Differences Between µPD78098 Subseries and µPD78098B
Subseries.
To understand the functions in general:
→ Read this manual in the order of the contents.
To know the µPD78098B Subseries instruction functions in detail:
→ Refer to the 78K/0 Series Instruction User's Manual (U12326E)
How to interpret the register format:
→ For a circled bit number, the bit name is defined as a reserved word in
RA78K0, and is already defined in the header file named sfrbit.h in the CC78K0.
To learn the function of a register whose register name is known:
→ Refer to APPENDIX C REGISTER INDEX.
To know the electrical specifications of the µPD78098B Subseries:
→ Refer to the separately available data sheet.
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representation:
××× (overscore over pin or signal name)
Note:
Footnote for item marked with Note in the text.
Caution:
Information requiring particular attention
Remarks:
Supplementary information
Numeral representation:
Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H
8
User’s Manual U12761EJ2V0UM
Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Documents Related to Devices
Document Name
Document No.
µPD78095B, 78096B, 78098B Data Sheet
U12735E
µPD78P098B Data Sheet
U12777E
µPD78098B Subseries User’s Manual
This manual
78K/0 Series Instructions User’s Manual
U12326E
78K/0 Series Basic (III) Application Note
U10182E
Documents Related to Software Development Tools (User’s Manuals)
Document Name
RA78K0 Assembler Package
Document No.
Operation
U14445E
Language
U14446E
Structured Assembly Language
U11789E
Operation
U14297E
Language
U14298E
SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later
WindowsTM Based
Operation
U14611E
SM78K Series System Simulator Ver. 2.10 or Later
External Part User Open Interface Specification
U15006E
ID78K0-NS Integrated Debugger Ver. 2.00 or Later
Operation
U14379E
Reference
U11539E
Guide
U11649E
Fundamentals
U11537E
Installation
U11536E
CC78K0 C Compiler
Windows Based
ID78K0 Integrated Debugger Windows Based
RX78K0 Real-Time OS
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
User’s Manual U12761EJ2V0UM
9
Documents Related to Hardware Development Tools (User’s Manuals)
Document Name
Document No.
IE-78K0-NS In-Circuit Emulator
U13731E
IE-78K0-NS-A In-Circuit Emulator
U14889E
IE-78098-NS-EM4 Emulation Board
To be prepared
Documents Related to PROM Writing (User’s Manuals)
Document Name
Document No.
PG-1500 PROM Programmer
U11940E
PC-9800 series (MS-DOSTM) Based
PG-1500 Controller
TM
IBM PC series (PC DOS ) Based
EEU-1291
U10540E
Other Related Documents
Document Name
Document No.
SEMICONDUCTOR SELECTION GUIDE - Products & Packages -
X13769E
Semiconductor Device Mounting Technology Manual
C10535E
Quality Grades on NEC Semiconductor Devices
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the
latest version of each document for designing.
10
User’s Manual U12761EJ2V0UM
CONTENTS
CHAPTER 1 OUTLINE .......................................................................................................................... 32
1.1
Features .................................................................................................................................. 32
1.2
Applications ........................................................................................................................... 33
1.3
Ordering Information ............................................................................................................ 33
1.4
Pin Configuration (Top View) ............................................................................................... 34
1.5
78K/0 Series Lineup .............................................................................................................. 37
1.6
Block Diagram ....................................................................................................................... 39
1.7
Outline of Function ............................................................................................................... 40
1.8
Mask Options ........................................................................................................................ 43
1.9
Differences Between µPD78098 Subseries and µPD78098B Subseries .......................... 43
CHAPTER 2 PIN FUNCTIONS ............................................................................................................ 44
2.1
2.2
Pin Function List ................................................................................................................... 44
2.1.1
Normal operating mode ............................................................................................................
44
2.1.2
PROM programming mode (PROM versions only) ...................................................................
47
Description of Pin Functions ............................................................................................... 48
2.2.1
P00 to P07 (Port 0) ...................................................................................................................
48
2.2.2
P10 to P17 (Port 1) ...................................................................................................................
49
2.2.3
P20 to P27 (Port 2) ...................................................................................................................
49
2.2.4
P30 to P37 (Port 3) ...................................................................................................................
50
2.2.5
P40 to P47 (Port 4) ...................................................................................................................
51
2.2.6
P50 to P57 (Port 5) ...................................................................................................................
51
2.2.7
P60 to P67 (Port 6) ...................................................................................................................
51
2.2.8
P70 to P72 (Port 7) ...................................................................................................................
52
2.2.9
P120 to P127 (Port 12) .............................................................................................................
52
2.2.10
P130 and P131 (Port 13) ..........................................................................................................
53
2.2.11
AVREF0 .......................................................................................................................................
53
2.2.12
AVREF1 ...........................................................................................................................................................................................................
53
2.2.13
AVDD ..........................................................................................................................................
53
2.2.14
AVSS ..........................................................................................................................................
53
2.2.15
RESET ......................................................................................................................................
53
2.2.16
X1 and X2 .................................................................................................................................
53
2.2.17
XT1 and XT2 ............................................................................................................................
54
2.2.18
VDD ............................................................................................................................................
54
2.2.19
VSS ............................................................................................................................................
54
2.2.20
VPP (PROM versions only) ........................................................................................................
54
2.2.21
IC (Mask ROM version only) .....................................................................................................
54
User’s Manual U12761EJ2V0UM
11
2.3
Pin I/O Circuits and Recommended Connection of Unused Pins .................................... 55
CHAPTER 3 CPU ARCHITECTURE .................................................................................................... 59
3.1
3.2
3.3
3.4
Memory Space ....................................................................................................................... 59
3.1.1
Internal program memory space ...............................................................................................
63
3.1.2
Internal data memory space .....................................................................................................
65
3.1.3
Special-Function Register (SFR) area ......................................................................................
65
3.1.4
External memory space ............................................................................................................
65
3.1.5
IEBus register space ................................................................................................................
65
3.1.6
Data memory addressing .........................................................................................................
66
Processor Registers ............................................................................................................. 70
3.2.1
Control registers .......................................................................................................................
70
3.2.2
General-purpose registers ........................................................................................................
73
3.2.3
Special-Function Register (SFR) ..............................................................................................
74
3.2.4
IEBus registers .........................................................................................................................
78
Instruction Address Addressing ......................................................................................... 80
3.3.1
Relative addressing ..................................................................................................................
80
3.3.2
Immediate addressing ..............................................................................................................
81
3.3.3
Table indirect addressing ..........................................................................................................
82
3.3.4
Register addressing ..................................................................................................................
83
Operand Address Addressing ............................................................................................. 84
3.4.1
Implied addressing ...................................................................................................................
84
3.4.2
Register addressing ..................................................................................................................
85
3.4.3
Direct addressing ......................................................................................................................
86
3.4.4
Short direct addressing .............................................................................................................
87
3.4.5
Special-Function Register (SFR) addressing ...........................................................................
88
3.4.6
Register indirect addressing .....................................................................................................
89
3.4.7
Based addressing .....................................................................................................................
90
3.4.8
Based indexed addressing .......................................................................................................
91
3.4.9
Stack addressing ......................................................................................................................
91
CHAPTER 4 PORT FUNCTIONS ........................................................................................................ 92
12
4.1
Port Functions ....................................................................................................................... 92
4.2
Port Configuration ................................................................................................................ 95
4.2.1
Port 0 ........................................................................................................................................
95
4.2.2
Port 1 ........................................................................................................................................
97
4.2.3
Port 2 ........................................................................................................................................
98
4.2.4
Port 3 ........................................................................................................................................ 100
4.2.5
Port 4 ........................................................................................................................................ 101
4.2.6
Port 5 ........................................................................................................................................ 102
4.2.7
Port 6 ........................................................................................................................................ 103
User’s Manual U12761EJ2V0UM
4.2.8
Port 7 ........................................................................................................................................ 105
4.2.9
Port 12 ...................................................................................................................................... 107
4.2.10
Port 13 ...................................................................................................................................... 110
4.3
Registers Controlling Port Function ................................................................................... 111
4.4
Port Operations ..................................................................................................................... 117
4.5
4.4.1
Writing to I/O port ...................................................................................................................... 117
4.4.2
Reading from I/O port ............................................................................................................... 117
4.4.3
Operations on I/O port .............................................................................................................. 118
Selection of Mask Option ..................................................................................................... 118
CHAPTER 5 CLOCK GENERATOR .................................................................................................... 119
5.1
Clock Generator Functions .................................................................................................. 119
5.2
Clock Generator Configuration ........................................................................................... 119
5.3
Registers Controlling Clock Generator .............................................................................. 122
5.4
System Clock Oscillator ....................................................................................................... 128
5.5
5.6
5.4.1
Main system clock oscillator ..................................................................................................... 128
5.4.2
Subsystem clock oscillator ....................................................................................................... 129
5.4.3
Divider ....................................................................................................................................... 131
5.4.4
When subsystem clocks not used ............................................................................................ 131
Clock Generator Operations ................................................................................................ 132
5.5.1
Main system clock operations .................................................................................................. 133
5.5.2
Subsystem clock operations ..................................................................................................... 134
Changing System Clock and CPU Clock Settings ............................................................. 135
5.6.1
Time required for switchover between system clock and CPU clock ....................................... 135
5.6.2
System clock and CPU clock switching procedure ................................................................... 137
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0 .............................................................................. 138
6.1
Outline of Internal Timer of µPD78098B Subseries ........................................................... 138
6.2
Functions of 16-Bit Timer/Event Counter 0 ........................................................................ 139
6.3
Configuration of 16-Bit Timer/Event Counter 0 .................................................................. 141
6.4
Registers Controlling 16-Bit Timer/Event Counter 0 ......................................................... 144
6.5
Operations of 16-Bit Timer/Event Counter 0 ...................................................................... 154
6.6
6.5.1
Interval timer operations ........................................................................................................... 154
6.5.2
PWM output operations ............................................................................................................ 156
6.5.3
PPG output operations ............................................................................................................. 159
6.5.4
Pulse width measurement operations ...................................................................................... 160
6.5.5
External event counter operation .............................................................................................. 167
6.5.6
Square-wave output operation ................................................................................................. 169
6.5.7
One-shot pulse output operation ............................................................................................. 171
Cautions for 16-Bit Timer/Event Counter 0 ........................................................................ 175
User’s Manual U12761EJ2V0UM
13
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 1 AND 2 .................................................................. 179
7.1
Functions of 8-Bit Timer/Event Counters 1 and 2 .............................................................. 179
7.1.1
8-bit timer/event counter mode ................................................................................................ 179
7.1.2
16-bit timer/event counter mode ............................................................................................... 182
7.2
Configuration of 8-Bit Timer/Event Counters 1 and 2 ....................................................... 184
7.3
Registers Controlling 8-Bit Timer/Event Counters 1 and 2 ............................................... 188
7.4
Operations of 8-Bit Timer/Event Counters 1 and 2 ............................................................ 193
7.5
7.4.1
8-bit timer/event counter mode ................................................................................................. 193
7.4.2
16-bit timer/event counter mode ............................................................................................... 198
Cautions for 8-Bit Timer/Event Counters 1 and 2 .............................................................. 202
CHAPTER 8 WATCH TIMER ............................................................................................................... 204
8.1
Watch Timer Functions ........................................................................................................ 204
8.2
Watch Timer Configuration .................................................................................................. 205
8.3
Registers Controlling Watch Timer ..................................................................................... 205
8.4
Watch Timer Operations ....................................................................................................... 209
8.4.1
Watch timer operation ............................................................................................................... 209
8.4.2
Interval timer operation ............................................................................................................. 209
CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 211
9.1
Watchdog Timer Functions .................................................................................................. 211
9.2
Watchdog Timer Configuration ........................................................................................... 213
9.3
Registers Controlling Watchdog Timer .............................................................................. 214
9.4
Watchdog Timer Operations ................................................................................................ 217
9.4.1
Watchdog timer operation ......................................................................................................... 217
9.4.2
Interval timer operation ............................................................................................................. 218
CHAPTER 10 CLOCK OUTPUT CONTROLLER .................................................................................. 219
10.1 Functions of Clock Output Controller ................................................................................. 219
10.2 Configuration of Clock Output Controller .......................................................................... 220
10.3 Registers Controlling Clock Output Function .................................................................... 221
CHAPTER 11 BUZZER OUTPUT CONTROLLER ................................................................................ 224
11.1 Functions of Buzzer Output Controller ............................................................................... 224
11.2 Configuration of Buzzer Output Controller ........................................................................ 224
11.3 Registers Controlling Buzzer Output Function .................................................................. 225
14
User’s Manual U12761EJ2V0UM
CHAPTER 12 A/D CONVERTER ........................................................................................................... 228
12.1 A/D Converter Functions ...................................................................................................... 228
12.2 A/D Converter Configuration ............................................................................................... 228
12.3 Registers Controlling A/D Converter .................................................................................. 231
12.4 A/D Converter Operation ...................................................................................................... 236
12.4.1
Basic operation of A/D converter .............................................................................................. 236
12.4.2
Input voltage and conversion results ........................................................................................ 238
12.4.3
A/D converter operating mode .................................................................................................. 239
12.5 How to Read the A/D Converter Characteristics Table...................................................... 241
12.6 Cautions for A/D Converter .................................................................................................. 243
CHAPTER 13 D/A CONVERTER ........................................................................................................... 248
13.1 D/A Converter Functions ...................................................................................................... 248
13.2 D/A Converter Configuration ............................................................................................... 249
13.3 Registers Controlling D/A Converter .................................................................................. 251
13.4 Operations of D/A Converter ............................................................................................... 252
13.5 Cautions for D/A Converter .................................................................................................. 253
CHAPTER 14 SERIAL INTERFACE CHANNEL 0 ................................................................................ 254
14.1 Functions of Serial Interface Channel 0 ............................................................................. 254
14.2 Configuration of Serial Interface Channel 0 ....................................................................... 256
14.3 Registers Controlling Serial Interface Channel 0 .............................................................. 260
14.4 Operations of Serial Interface Channel 0 ............................................................................ 267
14.4.1
Operation stop mode ................................................................................................................ 267
14.4.2
3-wire serial I/O mode operation .............................................................................................. 268
14.4.3
SBI mode operation .................................................................................................................. 273
14.4.4
2-wire serial I/O mode operation .............................................................................................. 299
14.4.5
SCK0/P27 pin output manipulation ........................................................................................... 304
CHAPTER 15 SERIAL INTERFACE CHANNEL 1 ................................................................................ 305
15.1 Functions of Serial Interface Channel 1 ............................................................................. 305
15.2 Configuration of Serial Interface Channel 1 ....................................................................... 306
15.3 Registers Controlling Serial Interface Channel 1 .............................................................. 309
15.4 Operations of Serial Interface Channel 1 ............................................................................ 315
15.4.1
Operation stop mode ................................................................................................................ 315
15.4.2
3-wire serial I/O mode operation .............................................................................................. 316
15.4.3
3-wire serial I/O mode operation with automatic transmit/receive function .............................. 319
User’s Manual U12761EJ2V0UM
15
CHAPTER 16 SERIAL INTERFACE CHANNEL 2 ................................................................................ 346
16.1 Functions of Serial Interface Channel 2 ............................................................................. 346
16.2 Configuration of Serial Interface Channel 2 ....................................................................... 347
16.3 Registers Controlling Serial Interface Channel 2 .............................................................. 351
16.4 Operation of Serial Interface Channel 2 .............................................................................. 359
16.4.1
Operation stop mode ................................................................................................................ 359
16.4.2
Asynchronous serial interface (UART) mode ........................................................................... 361
16.4.3
3-wire serial I/O mode .............................................................................................................. 374
16.4.4
Restrictions in UART mode ...................................................................................................... 381
CHAPTER 17 REAL-TIME OUTPUT PORT .......................................................................................... 384
17.1 Functions of Real-Time Output Port ................................................................................... 384
17.2 Configuration of Real-Time Output Port ............................................................................. 385
17.3 Registers Controlling Real-Time Output Port .................................................................... 387
CHAPTER 18 INTERRUPT AND TEST FUNCTIONS ........................................................................... 389
18.1 Interrupt Function Types ...................................................................................................... 389
18.2 Interrupt Sources and Configuration .................................................................................. 390
18.3 Registers Controlling Interrupt Function ........................................................................... 394
18.4 Interrupt Servicing Operations ............................................................................................ 403
18.4.1
Non-maskable interrupt request acknowledge operation ......................................................... 403
18.4.2
Maskable interrupt request acknowledgement operation ......................................................... 406
18.4.3
Software interrupt request acknowledgement operation .......................................................... 409
18.4.4
Multiple interrupt servicing ........................................................................................................ 409
18.4.5
Interrupt request pending ......................................................................................................... 413
18.5 Test Functions ....................................................................................................................... 414
18.5.1
Registers controlling the test function ....................................................................................... 414
18.5.2
Test input signal acknowledge operation .................................................................................. 416
CHAPTER 19 EXTERNAL DEVICE EXPANSION FUNCTION ............................................................. 417
19.1 External Device Expansion Function ................................................................................. 417
19.2 Registers Controlling External Device Expansion Function ............................................ 420
19.3 External Device Expansion Function Timing ..................................................................... 422
19.4 Example of Connection with Memory .................................................................................. 427
CHAPTER 20 IEBus CONTROLLER .................................................................................................... 428
20.1 IEBus Controller Function .................................................................................................... 428
16
20.1.1
IEBus communication protocol ................................................................................................. 428
20.1.2
Determining bus mastership (arbitration) ................................................................................. 429
User’s Manual U12761EJ2V0UM
20.1.3
Communication mode ............................................................................................................... 429
20.1.4
Communication address ........................................................................................................... 430
20.1.5
Broadcast communication ........................................................................................................ 430
20.2 Transmission System of IEBus ........................................................................................... 430
20.2.1
Transmit signal format of IEBus ................................................................................................ 430
20.2.2
Bit format .................................................................................................................................. 435
20.2.3
Transmit data ............................................................................................................................ 435
20.3 IEBus Controller Configuration ........................................................................................... 437
20.4 Registers Controlling IEBus Controller .............................................................................. 439
20.5 Communication Operation by IEBus ................................................................................... 453
20.5.1
Start bit output .......................................................................................................................... 453
20.5.2
Broadcast bit output .................................................................................................................. 453
20.5.3
Master address output .............................................................................................................. 453
20.5.4
Slave address output ................................................................................................................ 454
20.5.5
Control bit output ...................................................................................................................... 454
20.5.6
Lock function ............................................................................................................................ 455
20.5.7
Message length bit output ........................................................................................................ 455
20.5.8
Data bit output .......................................................................................................................... 456
20.5.9
Timing chart .............................................................................................................................. 456
20.6 Communication Procedure of IEBus .................................................................................. 460
20.6.1
Initialization ............................................................................................................................... 460
20.6.2
Master transmission procedure ................................................................................................ 461
CHAPTER 21 STANDBY FUNCTION ................................................................................................... 462
21.1 Standby Function and Configuration .................................................................................. 462
21.1.1 Standby function ......................................................................................................................... 462
21.1.2 Register controlling standby function .......................................................................................... 463
21.2 Standby Function Operations .............................................................................................. 464
21.2.1 HALT mode ................................................................................................................................. 464
21.2.2 STOP mode ................................................................................................................................ 466
CHAPTER 22 RESET FUNCTION ......................................................................................................... 470
22.1 Reset Function ...................................................................................................................... 470
CHAPTER 23 µPD78P098B .................................................................................................................. 475
23.1 Memory Size Switching Register ......................................................................................... 476
23.2 Internal Expansion RAM Size Switching Register .............................................................. 477
23.3 PROM Programming ............................................................................................................. 478
23.3.1 Operating modes ........................................................................................................................ 478
23.3.2 PROM write procedure ............................................................................................................... 480
User’s Manual U12761EJ2V0UM
17
23.3.3 PROM reading procedure ........................................................................................................... 484
23.4 Screening of One-Time PROM Versions .............................................................................. 484
CHAPTER 24 INSTRUCTION SET ....................................................................................................... 485
24.1 Conventions ........................................................................................................................... 485
24.1.1 Operand identifiers and description methods ............................................................................. 485
24.1.2 Description of “operation” column ............................................................................................... 486
24.1.3 Description of “flag operation” column ........................................................................................ 486
24.2 Operation List ........................................................................................................................ 487
24.3 Instructions Listed by Addressing Type ............................................................................. 495
APPENDIX A DEVELOPMENT TOOLS ................................................................................................ 499
A.1 Software Package ................................................................................................................... 501
A.2 Language Processing Software ............................................................................................ 501
A.3 PROM Programming Tools ..................................................................................................... 503
A.3.1 Hardware ...................................................................................................................................... 503
A.3.2 Software ....................................................................................................................................... 503
A.4 Debugging Tools ..................................................................................................................... 504
A.4.1 Hardware ...................................................................................................................................... 504
A.4.2 Software ....................................................................................................................................... 505
APPENDIX B EMBEDDED SOFTWARE .............................................................................................. 509
APPENDIX C REGISTER INDEX ......................................................................................................... 510
C.1 Register Index ......................................................................................................................... 510
C.2 Register Index (Symbol) ......................................................................................................... 514
APPENDIX D REVISION HISTORY ................................................................................................... 517
18
User’s Manual U12761EJ2V0UM
LIST OF FIGURES (1/9)
Figure No.
Title
Page
2-1
Pin I/O Circuits ...................................................................................................................................
57
3-1
Memory Map (µPD78095B) ................................................................................................................
59
3-2
Memory Map (µPD78096B) ................................................................................................................
60
3-3
Memory Map (µPD78098B) ................................................................................................................
61
3-4
Memory Map (µPD78P098B) .............................................................................................................
62
3-5
Data Memory Addressing (µPD78095B) ............................................................................................
66
3-6
Data Memory Addressing (µPD78096B) ............................................................................................
67
3-7
Data Memory Addressing (µPD78098B) ............................................................................................
68
3-8
Data Memory Addressing (µPD78P098B) ..........................................................................................
69
3-9
Program Counter Configuration .........................................................................................................
70
3-10
Program Status Word Configuration ..................................................................................................
70
3-11
Stack Pointer Configuration ................................................................................................................
72
3-12
Data to Be Saved to Stack Memory ...................................................................................................
72
3-13
Data to Be Restored from Stack Memory ...........................................................................................
72
3-14
General-Purpose Register Configuration ...........................................................................................
73
4-1
Port Types ..........................................................................................................................................
92
4-2
Block Diagram of P00 and P07 ..........................................................................................................
96
4-3
Block Diagram of P01 to P06 .............................................................................................................
96
4-4
Block Diagram of P10 to P17 .............................................................................................................
97
4-5
Block Diagram of P20, P21, P23 to P26 ............................................................................................
98
4-6
Block Diagram of P22 and P27 ..........................................................................................................
99
4-7
Block Diagram of P30 to P37 ............................................................................................................. 100
4-8
Block Diagram of P40 to P47 ............................................................................................................. 101
4-9
Block Diagram of Falling Edge Detector ............................................................................................ 101
4-10
Block Diagram of P50 to P57 ............................................................................................................. 102
4-11
Block Diagram of P60 to P63 ............................................................................................................. 104
4-12
Block Diagram of P64 to P67 ............................................................................................................. 104
4-13
Block Diagram of P70 ......................................................................................................................... 105
4-14
Block Diagram of P71 and P72 .......................................................................................................... 106
4-15
Block Diagram of P120 to P123, P126, and P127 ............................................................................. 107
4-16
Block Diagram of P124 ....................................................................................................................... 108
4-17
Block Diagram of P125 ....................................................................................................................... 109
4-18
Block Diagram of P130 and P131 ...................................................................................................... 110
4-19
Format of Port Mode Registers .......................................................................................................... 113
4-20
Format of Pull-Up Resistor Option Registers ..................................................................................... 114
4-21
Format of Memory Expansion Mode Register .................................................................................... 115
User’s Manual U12761EJ2V0UM
19
LIST OF FIGURES (2/9)
Figure No.
Title
Page
4-22
Format of Key Return Mode Register ................................................................................................. 116
5-1
Block Diagram of Clock Generator ..................................................................................................... 120
5-2
Configuration of Dividers 1 and 2 ....................................................................................................... 121
5-3
Subsystem Clock Feedback Resistor ................................................................................................. 122
5-4
Format of Processor Clock Control Register ...................................................................................... 123
5-5
Format of Oscillation Mode Selection Register .................................................................................. 124
5-6
Main System Clock Waveform When Writing to OSMS ..................................................................... 124
5-7
Format of Clock Select Register 1 ...................................................................................................... 125
5-8
Format of Clock Select Register 2 ...................................................................................................... 125
5-9
External Circuit of Main System Clock Oscillator ............................................................................... 128
5-10
External Circuit of Subsystem Clock Oscillator .................................................................................. 129
5-11
Examples of Oscillators with Incorrect Connection ............................................................................ 129
5-12
Main System Clock Stop Function ..................................................................................................... 133
5-13
System Clock and CPU Clock Switching ........................................................................................... 137
6-1
Block Diagram of 16-Bit Timer/Event Counter 0 ................................................................................. 141
6-2
Block Diagram of 16-Bit Timer/Event Counter 0 Output Controller .................................................... 142
6-3
Format of Timer Clock Select Register 0 ............................................................................................ 145
6-4
Format of 16-Bit Timer Mode Control Register 0 ................................................................................ 147
6-5
Format of Capture/Compare Control Register 0 ................................................................................ 148
6-6
Format of 16-Bit Timer Output Control Register 0 .............................................................................. 150
6-7
Format of Port Mode Register 3 ......................................................................................................... 151
6-8
Format of External Interrupt Mode Register 0 .................................................................................... 152
6-9
Format of Sampling Clock Select Register ......................................................................................... 153
6-10
Control Register Settings for Interval Timer Operation ....................................................................... 154
6-11
Interval Timer Configuration Diagram ................................................................................................ 155
6-12
Interval Timer Operation Timing ......................................................................................................... 155
6-13
Control Register Settings for PWM Output Operation ........................................................................ 157
6-14
Example of D/A Converter Configuration with PWM Output .............................................................. 158
6-15
TV Tuner Application Circuit Example ............................................................................................... 158
6-16
Control Register Settings for PPG Output Operation ......................................................................... 159
6-17
Control Register Settings for Pulse Width Measurement Operation by
Free-Running Counter and One Capture Register ............................................................................. 160
6-18
Configuration Diagram of Pulse Width Measurement Operation by
Free-Running Counter ........................................................................................................................ 161
6-19
Timing of Pulse Width Measurement Operation by Free-Running Counter
and One Capture Register (with Both Edges Specified) .................................................................... 161
20
User’s Manual U12761EJ2V0UM
LIST OF FIGURES (3/9)
Figure No.
6-20
Title
Page
Control Register Settings for Two Pulse Width Measurements Operation by
Free-Running Counter ........................................................................................................................ 162
6-21
CR01 Capture Operation with Rising Edge Specified ........................................................................ 163
6-22
Timing of Pulse Width Measurement Operation by
Free-Running Counter (with Both Edges Specified) .......................................................................... 163
6-23
Control Register Settings for Pulse Width Measurement Operation by
Free-Running Counter and Two Capture Registers ........................................................................... 164
6-24
Timing of Pulse Width Measurement Operation by Free-Running
Counter and Two Capture Registers (with Rising Edge Specified) .................................................... 165
6-25
Control Register Settings for Pulse Width Measurement Operation by Restart ................................. 166
6-26
Timing of Pulse Width Measurement Operation by Restart (with Rising Edge Specified) ................. 166
6-27
Control Register Settings in External Event Counter Mode ............................................................... 167
6-28
Configuration of External Event Counter ............................................................................................ 168
6-29
External Event Counter Operation Timing (with Rising Edge Specified) ............................................ 168
6-30
Control Register Settings in Square-Wave Output Mode ................................................................... 169
6-31
Square-Wave Output Operation Timing ............................................................................................. 170
6-32
Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger .................. 171
6-33
Timing of One-Shot Pulse Output Operation Using Software Trigger ................................................ 172
6-34
Control Register Settings for One-Shot Pulse Output Operation Using External Trigger ................... 173
6-35
Timing of One-Shot Pulse Output Operation Using
External Trigger (With Rising Edge Specified) ................................................................................... 174
6-36
16-Bit Timer Counter 0 Start Timing ................................................................................................... 175
6-37
Timing After Change of Compare Register During Timer Count Operation ........................................ 175
6-38
Capture Register Data Retention Timing ............................................................................................ 176
6-39
Operation Timing of OVF0 Flag .......................................................................................................... 177
7-1
Block Diagram of 8-Bit Timer/Event Counters 1 and 2 ....................................................................... 185
7-2
Block Diagram of 8-Bit Timer/Event Counter Output Controller 1 ...................................................... 186
7-3
Block Diagram of 8-Bit Timer/Event Counter Output Controller 2 ..................................................... 186
7-4
Format of Timer Clock Select Register 1 ............................................................................................ 189
7-5
Format of 8-Bit Timer Mode Control Register 1 .................................................................................. 190
7-6
Format of 8-Bit Timer Output Control Register 1 ................................................................................ 191
7-7
Format of Port Mode Register 3 ......................................................................................................... 192
7-8
Interval Timer Operation Timing ......................................................................................................... 193
7-9
External Event Counter Operation Timing (with Rising Edge Specified) ............................................ 196
7-10
Square-Wave Output Operation Timing ............................................................................................. 197
7-11
Interval Timer Operation Timing ......................................................................................................... 198
7-12
External Event Counter Operation Timing (with Rising Edge Specified) ............................................ 200
User’s Manual U12761EJ2V0UM
21
LIST OF FIGURES (4/9)
Figure No.
Title
Page
7-13
Square-Wave Output Operation Timing ............................................................................................. 201
7-14
8-Bit Timer Registers 1 and 2 Start Timing ......................................................................................... 202
7-15
Event Counter Operation Timing ........................................................................................................ 202
7-16
Timing After Change of Compare Register During Timer Count Operation ........................................ 203
8-1
Watch Timer Block Diagram ............................................................................................................... 206
8-2
Format of Timer Clock Select Register 2 ............................................................................................ 207
8-3
Format of Watch Timer Mode Control Register 2 ............................................................................... 208
8-4
Operation Timing of Watch Timer/Interval Timer ................................................................................ 210
9-1
Watchdog Timer Block Diagram ......................................................................................................... 213
9-2
Format of Timer Clock Select Register 2 ............................................................................................ 215
9-3
Format of Watchdog Timer Mode Register ......................................................................................... 216
10-1
Remote Controlled Output Application Example ................................................................................ 219
10-2
Block Diagram of Clock Output Controller .......................................................................................... 220
10-3
Format of Timer Clock Select Register 0 ............................................................................................ 222
10-4
Format of Port Mode Register 3 ......................................................................................................... 223
11-1
Block Diagram of Buzzer Output Controller ....................................................................................... 224
11-2
Format of Timer Clock Select Register 2 ............................................................................................ 226
11-3
Format of Port Mode Register 3 ......................................................................................................... 227
12-1
A/D Converter Block Diagram ............................................................................................................ 229
12-2
Format of A/D Converter Mode Register ............................................................................................ 232
12-3
Format of A/D Converter Input Select Register .................................................................................. 233
12-4
Format of External Interrupt Mode Register 1 .................................................................................... 234
12-5
Format of A/D Current Cut Select Register ........................................................................................ 235
12-6
Function of A/D Current Cut Select Register ...................................................................................... 235
12-7
A/D Converter Basic Operation .......................................................................................................... 237
12-8
Relationship Between Analog Input Voltage and A/D Conversion Result .......................................... 238
12-9
A/D Conversion by Hardware Start .................................................................................................... 239
12-10
A/D Conversion by Software Start ...................................................................................................... 240
12-11
Overall Error ....................................................................................................................................... 241
12-12
Quantization Error .............................................................................................................................. 241
12-13
Example of Method of Reducing Current Consumption in Standby Mode (Using Port) ..................... 243
12-14
Example of Reducing Power Consumption in Standby Mode
(Using A/D Current Cut Select Register) ............................................................................................ 244
22
User’s Manual U12761EJ2V0UM
LIST OF FIGURES (5/9)
Figure No.
Title
Page
12-15
Analog Input Pin Processing .............................................................................................................. 245
12-16
A/D Conversion End Interrupt Generation Timing .............................................................................. 246
12-17
AVDD Pin Connection .......................................................................................................................... 246
12-18
Timing of Reading Conversion Result (When Conversion Result Is Undefined) ................................ 247
12-19
Timing of Reading Conversion Result (When Conversion Result Is Normal) .................................... 247
13-1
D/A Converter Block Diagram ............................................................................................................ 249
13-2
Format of D/A Converter Mode Register ............................................................................................ 251
13-3
Example of Buffer Amplifier Insertion ................................................................................................ 253
14-1
Serial Bus Interface (SBI) System Configuration Example ................................................................ 255
14-2
Block Diagram of Serial Interface Channel 0 ..................................................................................... 257
14-3
Format of Timer Clock Select Register 3 ............................................................................................ 261
14-4
Format of Serial Operating Mode Register 0 ...................................................................................... 262
14-5
Format of Serial Bus Interface Control Register ................................................................................. 264
14-6
Format of Interrupt Timing Specification Register .............................................................................. 266
14-7
Timing in 3-Wire Serial I/O Mode ....................................................................................................... 271
14-8
RELT and CMDT Operations .............................................................................................................. 271
14-9
Transfer Bit Order Switching Circuit ................................................................................................... 272
14-10
Example of Serial Bus Configuration with SBI ................................................................................... 273
14-11
SBI Transfer Timing ............................................................................................................................ 275
14-12
Bus Release Signal ............................................................................................................................ 276
14-13
Command Signal ................................................................................................................................ 276
14-14
Address .............................................................................................................................................. 277
14-15
Slave Selection with Address ............................................................................................................. 277
14-16
Command ........................................................................................................................................... 278
14-17
Data .................................................................................................................................................... 278
14-18
Acknowledge Signal ........................................................................................................................... 279
14-19
BUSY and READY Signals ................................................................................................................. 280
14-20
RELT, CMDT, RELD, and CMDD Operations (Master) ...................................................................... 285
14-21
RELD and CMDD Operations (Slave) ................................................................................................ 285
14-22
ACKT Operation ................................................................................................................................. 286
14-23
ACKE Operations ............................................................................................................................... 287
14-24
ACKD Operations ............................................................................................................................... 288
14-25
BSYE Operation ................................................................................................................................. 288
14-26
Pin Configuration ................................................................................................................................ 291
14-27
Address Transmission from Master Device to Slave Device (WUP = 1) ............................................ 293
14-28
Command Transmission from Master Device to Slave Device .......................................................... 294
User’s Manual U12761EJ2V0UM
23
LIST OF FIGURES (6/9)
Figure No.
Title
Page
14-29
Data Transmission from Master Device to Slave Device ................................................................... 295
14-30
Data Transmission from Slave Device to Master Device ................................................................... 296
14-31
Serial Bus Configuration Example Using 2-Wire Serial I/O Mode ...................................................... 299
14-32
2-Wire Serial I/O Mode Timing ........................................................................................................... 302
14-33
RELT and CMDT Operations .............................................................................................................. 303
14-34
SCK0/P27 Pin Configuration .............................................................................................................. 304
15-1
Block Diagram of Serial Interface Channel 1 ..................................................................................... 307
15-2
Format of Timer Clock Select Register 3 ............................................................................................ 310
15-3
Format of Serial Operation Mode Register 1 ...................................................................................... 311
15-4
Format of Automatic Data Transmit/Receive Control Register ........................................................... 312
15-5
Format of Automatic Data Transmit/Receive Interval Specification Register ..................................... 313
15-6
Timing in 3-Wire Serial I/O Mode ....................................................................................................... 317
15-7
Transfer Bit Order Switching Circuit ................................................................................................... 318
15-8
Timing in Basic Transmission/Reception Mode Operation ................................................................. 325
15-9
Basic Transmission/Reception Mode Flowchart ................................................................................. 326
15-10
Buffer RAM Operation in 6-Byte Transmission/Reception
(in Basic Transmit/Receive Mode) ...................................................................................................... 327
15-11
Basic Transmission Mode Operation Timing ...................................................................................... 329
15-12
Basic Transmission Mode Flowchart .................................................................................................. 330
15-13
Buffer RAM Operation in 6-Byte Transmission (in Basic Transmission Mode) .................................. 331
15-14
Repeat Transmission Mode Operation Timing ................................................................................... 333
15-15
Repeat Transmission Mode Flowchart ............................................................................................... 334
15-16
Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode) ................................ 335
15-17
Automatic Transmission/Reception Suspension and Restart ............................................................. 337
15-18
System Configuration When Busy Control Option Is Used ................................................................ 338
15-19
Operation Timing When Using Busy Control Option (BUSY0 = 0) ..................................................... 339
15-20
Busy Signal and Wait Cancel (When BUSY0 = 0) ............................................................................. 340
15-21
Operation Timing When Using Busy & Strobe Control Option (BUSY0 = 0) ...................................... 341
15-22
Operation Timing of Bit Slippage Detection Function Using Busy Signal ........................................... 342
15-23
Automatic Data Transmit/Receive Interval ......................................................................................... 343
15-24
Operation Timing with Automatic Data Transmit/Receive Function Performed by
Internal Clock ..................................................................................................................................... 344
24
16-1
Block Diagram of Serial Interface Channel 2 .................................................................................... 348
16-2
Block Diagram of Baud Rate Generator ............................................................................................. 349
16-3
Format of Serial Operating Mode Register 2 ...................................................................................... 351
16-4
Format of Asynchronous Serial Interface Mode Register ................................................................... 352
User’s Manual U12761EJ2V0UM
LIST OF FIGURES (7/9)
Figure No.
Title
Page
16-5
Format of Asynchronous Serial Interface Status Register .................................................................. 354
16-6
Format of Baud Rate Generator Control Register .............................................................................. 355
16-7
Format of Asynchronous Serial Interface Transmit/Receive Data ...................................................... 368
16-8
Asynchronous Serial Interface Transmission Completion Interrupt Request
Generation Timing .............................................................................................................................. 370
16-9
Asynchronous Serial Interface Reception Completion Interrupt Request
Generation Timing .............................................................................................................................. 371
16-10
Receive Error Timing .......................................................................................................................... 372
16-11
Status of Receive Buffer Register (RXB) and Generation of
Interrupt Request (INTSR) When Reception Is Stopped .................................................................... 373
16-12
3-Wire Serial I/O Mode Timing ........................................................................................................... 379
16-13
Transfer Bit Order Switching Circuit ................................................................................................... 380
16-14
Receive Completion Interrupt Request Generation Timing (When ISRM = 1) ................................... 381
16-15
Disabling Reading Receive Buffer Register ....................................................................................... 382
17-1
Block Diagram of Real-Time Output Port ........................................................................................... 385
17-2
Configuration of Real-Time Output Buffer Register ............................................................................ 386
17-3
Format of Port Mode Register 12 ....................................................................................................... 387
17-4
Format of Real-Time Output Port Mode Register ............................................................................... 387
17-5
Format of Real-Time Output Port Control Register ............................................................................ 388
18-1
Basic Configuration of Interrupt Function ........................................................................................... 392
18-2
Format of Interrupt Request Flag Register ......................................................................................... 395
18-3
Format of Interrupt Mask Flag Register .............................................................................................. 396
18-4
Format of Priority Specification Flag Register .................................................................................... 397
18-5
Format of External Interrupt Mode Register 0 .................................................................................... 398
18-6
Format of External Interrupt Mode Register 1 .................................................................................... 399
18-7
Format of Sampling Clock Select Register ......................................................................................... 400
18-8
Noise Eliminator I/O Timing (Rising Edge Detection) ......................................................................... 401
18-9
Configuration of Program Status Word .............................................................................................. 402
18-10
Non-Maskable Interrupt Request Occurrence and Acknowledgement Flowchart .............................. 404
18-11
Non-Maskable Interrupt Request Acknowledgement Timing .............................................................. 404
18-12
Non-Maskable Interrupt Request Acknowledgement Operation ........................................................ 405
18-13
Interrupt Request Acknowledgement Processing Algorithm ............................................................... 407
18-14
Interrupt Request Acknowledgement Timing (Minimum Time) ........................................................... 408
18-15
Interrupt Request Acknowledgement Timing (Maximum Time) .......................................................... 408
18-16
Example of Multiple Interrupts ............................................................................................................ 411
18-17
Interrupt Request Hold ....................................................................................................................... 413
User’s Manual U12761EJ2V0UM
25
LIST OF FIGURES (8/9)
Figure No.
26
Title
Page
18-18
Basic Configuration of Test Function .................................................................................................. 414
18-19
Format of Interrupt Request Flag Register 1L .................................................................................... 415
18-20
Format of Interrupt Mask Flag Register 1L ......................................................................................... 415
18-21
Format of Key Return Mode Register ................................................................................................. 416
19-1
Memory Map When Using External Device Expansion Function ....................................................... 418
19-2
Format of Memory Expansion Mode Register .................................................................................... 420
19-3
Format of Memory Size Switching Register ....................................................................................... 421
19-4
Instruction Fetch from External Memory ............................................................................................ 423
19-5
External Memory Read Timing ........................................................................................................... 424
19-6
External Memory Write Timing ........................................................................................................... 425
19-7
External Memory Read Modify Write Timing ...................................................................................... 426
19-8
Connection Example of µPD78095B and Memory ............................................................................. 427
20-1
Transmit Signal Format of IEBus ........................................................................................................ 430
20-2
Configuration of Master Address Field ............................................................................................... 432
20-3
Configuration of Slave Address Field ................................................................................................. 432
20-4
Configuration of Control Field ............................................................................................................. 433
20-5
Configuration of Message Length Field .............................................................................................. 434
20-6
Configuration of Data Field ................................................................................................................. 434
20-7
Bit Format of IEBus ............................................................................................................................ 435
20-8
Bit Configuration of Slave Status ........................................................................................................ 435
20-9
Configuration of Lock Address ........................................................................................................... 436
20-10
TBF Setting Format ............................................................................................................................ 437
20-11
RBF Setting Format ............................................................................................................................ 438
20-12
Format of Clock Select Register 1 ...................................................................................................... 439
20-13
Format of IEBus Controller Mode Register ........................................................................................ 440
20-14
Control Register Format ..................................................................................................................... 441
20-15
Command Register Format (When Used for Control) ........................................................................ 442
20-16
Command Register Format (for Option Setting) ................................................................................. 443
20-17
Format of Master Communication Control Register ........................................................................... 444
20-18
Format of Status Register 1 ............................................................................................................... 445
20-19
Format of Status Register 2 ............................................................................................................... 446
20-20
Format of Return Code Register ........................................................................................................ 447
20-21
Format of Unit Address Registers 1 and 2 ......................................................................................... 450
20-22
Format of Slave Address Registers 1 and 2 ....................................................................................... 451
20-23
Format of Broadcast Destination Address Registers 1 and 2 ............................................................. 451
20-24
Format of Lock Address Registers 1 and 2 ........................................................................................ 452
User’s Manual U12761EJ2V0UM
LIST OF FIGURES (9/9)
Figure No.
20-25
Title
Page
Operation Example of Individual Communication
(Master Transmission - Slave Reception) .......................................................................................... 457
20-26
Operation Example of Individual Communication
(Master Reception - Slave Transmission) .......................................................................................... 458
20-27
Operation Example of Broadcast Communication
(Master Transmission - Slave Reception) .......................................................................................... 459
21-1
Format of Oscillation Stabilization Time Select Register .................................................................... 463
21-2
Releasing HALT Mode by Interrupt Request Generation ................................................................... 465
21-3
Releasing HALT Mode by RESET Input ............................................................................................. 466
21-4
Releasing STOP Mode by Interrupt Request Generation .................................................................. 468
21-5
Releasing STOP Mode by RESET Input ............................................................................................ 469
22-1
Block Diagram of Reset Function ....................................................................................................... 470
22-2
Timing of Reset by RESET Input ........................................................................................................ 471
22-3
Timing of Reset due to Watchdog Timer Overflow ............................................................................. 471
22-4
Timing of Reset by RESET Input in STOP Mode ............................................................................... 471
23-1
Format of Memory Size Switching Register ....................................................................................... 476
23-2
Format of Internal Expansion RAM Size Switching Register ............................................................. 477
23-3
Page Program Mode Flowchart .......................................................................................................... 480
23-4
Page Program Mode Timing ............................................................................................................... 481
23-5
Byte Program Mode Flowchart ........................................................................................................... 482
23-6
Byte Program Mode Timing ................................................................................................................ 483
23-7
PROM Read Timing ........................................................................................................................... 484
A-1
Development Tool Configuration ........................................................................................................ 500
A-2
EV-9200GC-80 Drawing (For Reference Only) .................................................................................. 507
A-3
EV-9200GC-80 Footprint (For Reference Only) ................................................................................. 508
User’s Manual U12761EJ2V0UM
27
LIST OF TABLES (1/4)
Table No.
Title
Page
1-1
Mask Options of Mask ROM Versions ................................................................................................
43
1-2
Differences Between µPD78098 Subseries and µPD78098B Subseries ...........................................
43
2-1
Pin I/O Circuit Types ...........................................................................................................................
55
3-1
Vector Table ........................................................................................................................................
64
3-2
Special-Function Register List ............................................................................................................
75
3-3
IEBus Register List .............................................................................................................................
79
4-1
Port Functions ....................................................................................................................................
93
4-2
Port Configuration ..............................................................................................................................
95
4-3
Pull-up Resistor of Port 6 ................................................................................................................... 103
4-4
Port Mode Register and Output Latch Setting When Using Alternate Functions ............................... 112
4-5
Comparison Between Mask ROM Version and PROM Version ......................................................... 118
5-1
Clock Generator Configuration ........................................................................................................... 119
5-2
Relationship Between Setting of Divider 1 and Main System Clock Frequency ................................ 126
5-3
CPU Clock (fCPU) List .......................................................................................................................... 127
5-4
Maximum Time Required for CPU Clock Switchover ......................................................................... 136
6-1
Interval Time of 16-Bit Timer/Event Counter 0 ................................................................................... 139
6-2
Square-Wave Output Range of 16-Bit Timer/Event Counter 0 ........................................................... 140
6-3
Configuration of 16-Bit Timer/Event Counter 0 ................................................................................... 141
6-4
INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge ................................................... 143
6-5
Interval Time of 16-Bit Timer/Event Counter 0 ................................................................................... 156
6-6
Square-Wave Output Range of 16-Bit Timer/Event Counter 0 ........................................................... 170
7-1
Interval Time of 8-Bit Timer/Event Counters 1 and 2 .......................................................................... 180
7-2
Square-Wave Output Range of 8-Bit Timer/Event Counters 1 and 2 ................................................. 181
7-3
Interval Time When 8-Bit Timer/Event Counters 1 and 2
Are Used as 16-Bit Timer/Event Counter ........................................................................................... 182
7-4
Square-Wave Output Ranges When 8-Bit Timer/Event
Counters 1 and 2 Are Used as 16-Bit Timer/Event Counter ............................................................... 183
28
7-5
Configuration of 8-Bit Timer/Event Counters 1 and 2 ......................................................................... 184
7-6
Interval Time of 8-Bit Timer/Event Counter 1 ..................................................................................... 194
7-7
Interval Time of 8-Bit Timer/Event Counter 2 ..................................................................................... 195
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LIST OF TABLES (2/4)
Table No.
Title
Page
7-8
Square-Wave Output Range of 8-Bit Timer/Event Counters 1 and 2 ................................................. 197
7-9
Interval Times When 2-Channel 8-Bit Timer/Event Counters
Are Used as 16-Bit Timer/Event Counter ........................................................................................... 199
7-10
Square-Wave Output Range When 2-Channel 8-Bit Timer/Event Counters
Are Used as 16-Bit Timer/Event Counter ........................................................................................... 201
8-1
Interval Timer Interval Time ................................................................................................................ 204
8-2
Watch Timer Configuration ................................................................................................................. 205
8-3
Interval Timer Interval Time ................................................................................................................ 209
9-1
Watchdog Timer Program Loop Detection Time ................................................................................. 211
9-2
Interval Time ....................................................................................................................................... 212
9-3
Watchdog Timer Configuration ........................................................................................................... 213
9-4
Watchdog Timer Program Loop Detection Time ................................................................................. 217
9-5
Interval Timer Interval Time ................................................................................................................ 218
10-1
Clock Output Controller Configuration ................................................................................................ 220
11-1
Buzzer Output Controller Configuration ............................................................................................. 224
12-1
A/D Converter Configuration .............................................................................................................. 228
13-1
D/A Converter Configuration .............................................................................................................. 249
14-1
Configuration of Serial Interface Channel 0 ....................................................................................... 256
14-2
Signals in SBI Mode ........................................................................................................................... 289
15-1
Configuration of Serial Interface Channel 1 ....................................................................................... 306
15-2
Interval Timing Through CPU Processing (When Internal Clock Is Operating) .................................. 344
15-3
Interval Timing Through CPU Processing (When External Clock Is Operating) ................................. 345
16-1
Configuration of Serial Interface Channel 2 ....................................................................................... 347
16-2
Operating Mode Settings of Serial Interface Channel 2 ..................................................................... 353
16-3
Relationship Between Main System Clock and Baud Rate ................................................................ 357
16-4
Relationship Between ASCK Pin Input Frequency and Baud Rate
(When BRGC Is Set to 00H) .............................................................................................................. 358
User’s Manual U12761EJ2V0UM
29
LIST OF TABLES (3/4)
Table No.
Title
Page
16-5
Relationship Between Main System Clock and Baud Rate ................................................................ 366
16-6
Relationship Between ASCK Pin Input Frequency and Baud Rate
(When BRGC Is Set to 00H) .............................................................................................................. 367
16-7
Receive Error Causes ........................................................................................................................ 372
17-1
Configuration of Real-Time Output Port ............................................................................................. 385
17-2
Operation in Real-Time Output Buffer Register Manipulation ............................................................ 386
17-3
Real-Time Output Port Operating Mode and Output Trigger .............................................................. 388
18-1
Interrupt Source List ........................................................................................................................... 390
18-2
Various Flags Corresponding to Interrupt Request Sources .............................................................. 394
18-3
Times from Maskable Interrupt Request Generation to Interrupt Servicing ....................................... 406
18-4
Interrupt Request Enabled as Multiple Interrupts During Interrupt Servicing ..................................... 410
18-5
Test Input Factors ............................................................................................................................... 414
18-6
Flags Corresponding to Test Input Signals ......................................................................................... 414
19-1
Pin Functions in External Memory Expansion Mode .......................................................................... 417
19-2
State of Ports 4 to 6 Pins in External Memory Expansion Mode ........................................................ 417
19-3
Values After Memory Size Switching Register Is Reset ..................................................................... 421
20-1
Transmission Rate in Each Communication Mode and Maximum Number
of Transmit Bytes ................................................................................................................................ 429
30
20-2
Contents of Control Bits ..................................................................................................................... 433
20-3
Message Length Bit and Number of Bytes of Transmit Data ............................................................. 434
20-4
Meaning of Slave Status .................................................................................................................... 436
20-5
IEBus Controller Configuration ........................................................................................................... 437
20-6
Control Bits That Can Be Specified for Locked Slave Unit ................................................................. 455
21-1
HALT Mode Operating Status ............................................................................................................. 464
21-2
Operation After HALT Mode Release ................................................................................................. 466
21-3
STOP Mode Operating Status ............................................................................................................ 467
21-4
Operation After STOP Mode Release ................................................................................................ 469
22-1
Hardware Status After Reset .............................................................................................................. 472
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LIST OF TABLES (4/4)
Table No.
Title
Page
23-1
Differences Between µPD78P098B and Mask ROM Versions ........................................................... 475
23-2
Examples of Memory Size Switching Register Settings ..................................................................... 476
23-3
Values Set to Internal Expansion RAM Size Switching Register ........................................................ 477
23-4
PROM Programming Operating Modes ............................................................................................. 478
24-1
Operand Identifiers and Description Methods .................................................................................... 485
User’s Manual U12761EJ2V0UM
31
CHAPTER 1
OUTLINE
CHAPTER 1 OUTLINE
1.1 Features
Lower EMI (Electro-Magnetic Interference) noise than that of existing µPD78098 Subseries products
On-chip high-capacity ROM and RAM
Type
Part Number
Program Memory
(ROM)
µPD78095B
40 KB
µPD78096B
48 KB
µPD78098B
60 KB
µPD78P098B
Notes
60
Data Memory
Internal High-Speed RAM
1,024 bytes
Buffer RAM
32 bytes
Internal Expansion RAM
None
2,048 bytes
KBNote 1
2,048 bytes Note 2
1. The capacity of the internal PROM can be changed by means of the internal memory size switching
register (IMS).
2. The capacity of the internal high-speed RAM can be changed by means of the internal expansion RAM
size switching register (IXS).
External memory expansion space: 64 KB
Minimum instruction execution time changeable from high speed (0.5 µs: @ 6.0 MHz operation with main system
clock) to ultra-low speed (122 µs: @ 32.768 kHz operation with subsystem clock)
Instruction set suited to system control
• Bit manipulation possible in all address spaces
• Multiply and divide instructions
I/O ports: 69 (4 N-ch open-drain ports)
IEBusTM controller
• Effective transfer rate: 3.9 kbps/17 kbps/26 kbps
• Supply voltage: VDD = 4.5 to 5.5 V
8-bit resolution A/D converter: 8 channels
8-bit resolution D/A converter: 2 channels
Serial interface: 3 channels
• 3-wire serial I/O/SBI/2-wire serial I/O mode:
1 channel
• 3-wire serial I/O mode (automatic transmit/receive function):
1 channel
• 3-wire serial I/O/UART mode:
1 channel
Timer: 5 channels
• 16-bit timer/event counter:
1 channel
• 8-bit timer/event counter:
2 channels
• Watch timer:
1 channel
• Watchdog timer:
1 channel
Vectored interrupt sources:
23
Two test inputs
Two types of on-chip clock oscillators (main system clock and subsystem clock)
Supply voltage: VDD = 2.7 to 5.5 V
32
User’s Manual U12761EJ2V0UM
CHAPTER 1
OUTLINE
1.2 Applications
Car audio systems, CD changers, etc.
1.3 Ordering Information
Part Number
Package
Internal ROM
µPD78095BGC-×××-8BT
80-pin plastic QFP (14 × 14)
Mask ROM
µPD78096BGC-×××-8BT
80-pin plastic QFP (14 × 14)
Mask ROM
µPD78098BGC-×××-8BT
80-pin plastic QFP (14 × 14)
Mask ROM
µPD78P098BGC-8BT
80-pin plastic QFP (14 × 14)
One-time PROM
Remark
××× indicates ROM code suffix.
User’s Manual U12761EJ2V0UM
33
CHAPTER 1
OUTLINE
1.4 Pin Configuration (Top View)
(1) Normal operating mode
80-pin plastic QFP (14 × 14)
µPD78095BGC-×××-8BT, 78096BGC-×××-8BT, 78098BGC-×××-8BT
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AVREF0
AVDD
XT1/P07
XT2
IC (VPP)
X1
X2
VDD
P06/INTP6
P05/INTP5
P04/INTP4
P03/INTP3
P02/INTP2
P01/INTP1/TI01
P00/INTP0/TI00
µPD78P098BGC-8BT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
1
59
2
58
3
57
4
56
5
55
6
54
7
53
8
52
9
51
10
50
11
49
12
48
13
47
14
46
15
45
16
44
17
43
18
42
19
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
RESET
P127/RTP7
P126/RTP6
P125/RTP5/RX
P124/RTP4/TX
P123/RTP3
P122/RTP2
P121/RTP1
P120/RTP0
P37
P36/BUZ
P35/PCL
P34/TI2
P33/TI1
P32/TO2
P31/TO1
P30/TO0
P67/ASTB
P66/WAIT
P65/WR
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
VSS
P56/A14
P57/A15
P60
P61
P62
P63
P64/RD
P15/ANI5
P16/ANI6
P17/ANI7
AVSS
P130/ANO0
P131/ANO1
AVREF1
P70/SI2/RxD
P71/SO2/TxD
P72/SCK2/ASCK
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0
P26/SO0/SB1
P27/SCK0
P40/AD0
P41/AD1
Cautions 1. Connect the IC (Internally Connected) pin directly to VSS.
2. The AVDD pin supplies power to the A/D converter and ports. In an application where the
noise generated from the internal circuitry of the microcontroller must be reduced,
connect this pin to a separate power supply with the same potential as VDD.
3. The AVSS pin is used as the ground of the A/D converter, D/A converter, and ports. In
an application where the noise generated from the internal circuitry of the microcontroller
must be reduced, connect this pin to a ground line separated from VSS.
Remark
34
The pin connection in parentheses applies to the µPD78P098B.
User’s Manual U12761EJ2V0UM
CHAPTER 1
OUTLINE
Pin Identification
A8 to A15:
Address bus
PCL:
Programmable clock
AD0 to AD7:
Address/data bus
RD:
Read strobe
ANI0 to ANI7:
Analog input
RESET:
Reset
ANO0, ANO1:
Analog output
RTP0 to RTP7:
Real-time output port
ASCK:
Asynchronous serial clock
RX:
Receive data (IEBus controller)
ASTB:
Address strobe
RxD:
Receive data
AVDD:
Analog power supply
SB0, SB1:
Serial bus
AVREF0, AVREF1:
Analog reference voltage
SCK0 to SCK2:
Serial clock
AVSS:
Analog ground
SI0 to SI2:
Serial input
BUSY:
Busy
SO0 to SO2:
Serial output
BUZ:
Buzzer clock
STB:
Strobe
IC:
Internally connected
TI00, TI01:
Timer input
INTP0 to INTP6:
Interrupt from peripherals
TI1, TI2:
Timer input
P00 to P07:
Port 0
TO0 to TO2:
Timer output
P10 to P17:
Port 1
TX:
Transmit data (IEBus controller)
P20 to P27:
Port 2
TxD:
Transmit data
P30 to P37:
Port 3
VDD:
Power supply
P40 to P47:
Port 4
VPP:
Programming power supply
P50 to P57:
Port 5
VSS:
Ground
P60 to P67:
Port 6
WAIT:
Wait
P70 to P72:
Port 7
WR:
Write strobe
P120 to P127:
Port 12
X1, X2:
Crystal (main system clock)
P130, P131:
Port 13
XT1, XT2:
Crystal (subsystem clock)
User’s Manual U12761EJ2V0UM
35
CHAPTER 1
OUTLINE
(2) PROM programming mode
80-pin plastic QFP (14 × 14)
VDD
(L)
Cautions 1. (L):
2. VSS:
PGM
(L)
A9
(L)
A2
A3
A4
A5
A6
A7
A8
A16
A10
A11
A12
A13
VSS
A14
A15
A0
A1
RESET
(L)
D7
D6
D5
D4
D3
D2
D1
D0
(L)
CE
OE
VSS
(L)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
1
59
2
58
3
57
4
56
5
55
6
54
7
53
8
52
9
51
10
50
11
49
12
48
13
47
14
46
15
45
16
44
17
43
18
42
19
41
20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
(L)
(L)
VSS
VDD
(L)
Open
VPP
(L)
Open
VDD
(L)
µPD78P098BGC-8BT
Connect individually to VSS via a pull-down resistor.
Connect to the ground.
3. RESET: Set to the low level.
4. Open:
36
Do not connect anything.
A0 to A16:
Address bus
RESET:
Reset
CE:
Chip enable
VDD:
Power supply
D0 to D7:
Data bus
VPP:
Programming power supply
OE:
Output enable
VSS:
Ground
PGM:
Program
User’s Manual U12761EJ2V0UM
CHAPTER 1
OUTLINE
1.5 78K/0 Series Lineup
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
100-pin
100-pin
100-pin
µ PD78075B
µ PD78078
µ PD78070A
100-pin
80-pin
80-pin
µ PD780058
µ PD78058F
80-pin
µPD78054
µPD780065
64-pin
µ PD780078
64-pin
64-pin
64-pin
µ PD780034A
µ PD780024A
µPD78014H
64-pin
42-/44-pin
µPD78018F
µ PD78083
64-pin
µPD780988
80-pin
EMI-noise reduced version of the µPD78078
µPD78078Y
µPD78054 with added timer and enhanced external interface
µ PD78070AY
ROMless version of the µ PD78078
µ PD78078Y with enhanced serial I/O and limited functions
µ PD780018AY
µ PD780058Y
µ PD78058FY
µ PD78054 with enhanced serial I/O
EMI-noise reduced version of the µ PD78054
µPD78018F with added UART and D/A converter and enhanced I/O
µPD780024A with increased RAM capacity.
µPD780034A with added timer and enhanced serial I/O
µ PD780078Y
µ PD780034AY µ PD780024A with enhanced A/D converter
µ PD780024AY µ PD78018F with enhanced serial I/O
EMI-noise reduced version of the µPD78018F
µ PD78054Y
µ PD78018FY
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
Inverter control
On-chip inverter controller and UART. EMI-noise reduced.
VFD drive
78K/0
Series
100-pin
µ PD780208
µ PD78044F with enhanced I/O and VFD C/D. Display output total: 53
80-pin
For panel control. On-chip VFD and C/D. Display output total: 53
80-pin
µ PD780232
µPD78044H
80-pin
µPD78044F
Basic subseries for VFD drive. Display output total: 34
µ PD78044F with added N-ch open-drain I/O. Display output total: 34
LCD drive
120-pin
µ PD780338
120-pin
µ PD780328
µPD780318
µ PD780308
µPD78064B
µPD78064
120-pin
100-pin
100-pin
100-pin
µ PD780308 with enhanced display function and timer. Segment signal output: 40 pins max.
µ PD780308 with enhanced display function and timer. Segment signal output: 32 pins max.
µ PD780308 with enhanced display function and timer. Segment signal output: 24 pins max.
µPD780308Y
µ PD78064 with enhanced SIO, and increased ROM, RAM capacity
EMI-noise reduced version of the µ PD78064
µ PD78064Y
Basic subseries for LCD drive, on-chip UART
Bus interface supported
100-pin
80-pin
µ PD780948
µ PD78098B
On-chip CAN controller
µPD78054 with added IEBusTM controller.
80-pin
µPD780702Y
On-chip IEBus controller
80-pin
µPD780703Y
µPD780833Y
On-chip CAN controller
80-pin
64-pin
µPD780816
On-chip controller compliant with J1850 (Class 2)
Specialized for CAN controller function
Meter control
100-pin
µPD780958
For industrial meter control
80-pin
µPD780852
µPD780828B
On-chip automobile meter controller/driver
For automobile meter driver. On-chip CAN controller
80-pin
Remark
VFD (Vacuum Fluorescent Display) is referred to as FIPTM (Fluorescent Indicator Panel) in some
documents, but the functions of the two are the same.
User’s Manual U12761EJ2V0UM
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CHAPTER 1
OUTLINE
The major functional differences between the subseries are shown below.
Function
Subseries Name
ROM
Capacity
(Bytes)
Timer
8-Bit 16-Bit Watch WDT
µPD78075B 32 K to 40 K 4 ch
Control
µPD78078
µPD78070A
8-Bit 10-Bit 8-Bit
1 ch
1 ch
1 ch
A/D
A/D
8 ch
–
Serial Interface
I/O
VDD External
MIN.
Expansion
Value
88
1.8 V
61
2.7 V
D/A
2 ch 3 ch (UART: 1 ch)
48 K to 60 K
–
µPD780058 24 K to 60 K 2 ch
3 ch (time-division UART: 1 ch)
68
1.8 V
µPD78058F 48 K to 60 K
3 ch (UART: 1 ch)
69
2.7 V
µPD78054
√
16 K to 60 K
2.0 V
µPD780065 40 K to 48 K
–
µPD780078 48 K to 60 K
2 ch
µPD780034A 8 K to 32 K
1 ch
–
µPD780024A
8 ch
8 ch
4 ch (UART: 1 ch)
60
2.7 V
3 ch (UART: 2 ch)
52
1.8 V
3 ch (UART: 1 ch)
51
2 ch
53
1 ch (UART: 1 ch)
33
–
µPD78014H
µPD78018F 8 K to 60 K
µPD78083
8 K to 16 K
–
Inverter
control
µPD780988 16 K to 60 K 3 ch Note
VFD
drive
µPD780208 32 K to 60 K 2 ch
–
–
1 ch
–
8 ch
–
3 ch (UART: 2 ch)
47
4.0 V
√
1 ch
1 ch
1 ch
8 ch
–
–
2 ch
74
2.7 V
–
µPD780232 16 K to 24 K 3 ch
–
–
4 ch
40
4.5 V
µPD78044H 32 K to 48 K 2 ch
1 ch
1 ch
8 ch
68
2.7 V
54
1.8 V
1 ch
µPD78044F 16 K to 40 K
LCD
drive
µPD780338 48 K to 60 K 3 ch
2 ch
2 ch
1 ch
1 ch
–
10 ch 1 ch 2 ch (UART: 1 ch)
µPD780328
62
µPD780318
70
µPD780308 48 K to 60 K 2 ch
1 ch
8 ch
–
–
µPD78064B 32 K
µPD78064
57
2.0 V
79
4.0 V
√
69
2.7 V
–
2 ch (UART: 1 ch)
2 ch
1 ch
1 ch
8 ch
–
1 ch
–
3 ch (UART: 1 ch)
2 ch
µPD780816 32 K to 60 K
2 ch
Meter
control
µPD780958 48 K to 60 K 4 ch
2 ch
–
1 ch
–
Dash
board
control
µPD780852 32 K to 40 K 3 ch
1 ch
1 ch
1 ch
5 ch
12 ch
–
2 ch (UART: 1 ch)
46
4.0 V
–
–
2 ch (UART: 1 ch)
69
2.2 V
–
–
–
3 ch (UART: 1 ch)
56
4.0 V
–
µPD780828B 32 K to 60 K
59
16-bit timer: 2 channels
10-bit timer: 1 channel
38
3 ch (time-division UART: 1 ch)
–
16 K to 32 K
Bus
µPD780948 60 K
2 ch
interface
supported µPD78098B 40 K to 60 K
Note
–
User’s Manual U12761EJ2V0UM
CHAPTER 1
OUTLINE
1.6 Block Diagram
TO0/P30
TI00/INTP0/P00
TI01/INTP1/P01
16-bit timer/
event counter
TO1/P31
TI1/P33
8-bit timer/
event counter 1
TO2/P32
TI2/P34
8-bit timer/
event counter 2
Watchdog timer
Port 0
P00
P01 to P06
P07
Port 1
P10 to P17
Port 2
P20 to P27
Port 3
P30 to P37
Port 4
P40 to P47
Port 5
P50 to P57
Port 6
P60 to P67
Port 7
P70 to P72
Port 12
P120 to P127
Port 13
P130, P131
External
access
AD0/P40 to
AD7/P47
A8/P50 to
A15/P57
RD/P64
WR/P65
WAIT/P66
ASTB/P67
System
control
RESET
X1
X2
XT1/P07
XT2
Watch timer
SI0/SB0/P25
SO0/SB1/P26
SCK0/P27
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
Serial
interface 0
78K/0
CPU
core
ROM
Serial
interface 1
SI2/RxD/P70
SO2/TxD/P71
SCK2/ASCK/P72
Serial
interface 2
ANI0/P10 to
ANI7/P17
AVDD
AVSS
AVREF0
A/D
converter
ANO0/P130,
ANO1/P131
AVSS
AVREF1
D/A
converter
RAM
INTP0/P00 to
INTP6/P06
Interrupt
control
RTP0/P120 to
RTP7/P127
Realtime
output port
TX/P124/RTP4
RX/P125/RTP5
IEBus
controller
BUZ/P36
Buzzer output
PCL/P35
Clock output
control
VDD
VSS
IC
(VPP)
Remarks 1. The internal ROM and RAM capacities vary depending on the product.
2. The pin connection in parentheses applies to the µPD78P098B.
User’s Manual U12761EJ2V0UM
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CHAPTER 1
OUTLINE
1.7 Outline of Functions
µPD78095B
Part Number
µPD78096B
µPD78098B
µPD78P098B
Item
Internal
memory
ROM
Mask ROM
40 KB
High-speed RAM
1,024 bytes
Buffer RAM
32 bytes
Expansion RAM
None
PROM
48 KB
Memory space
64 KB
General-purpose registers
8 bits × 8 × 4 banks
Minimum
instruction
With main system clock selected
execution time With subsystem clock selected
Instruction set
60 KB
60 KBNote 1
2,048 bytes
2,048 bytesNote 2
0.5 µs/1.0 µs/2.0 µs/4.0 µs/8.0 µs/16.0 µs (@ 6.0 MHz)
122 µs (@ 32.768 kHz)
• 16-bit operation
• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)
• Bit manipulate (set, reset, test, and Boolean operation)
• BCD adjust, etc.
I/O ports
• Total:
• CMOS input:
• CMOS I/O:
69
2
63
• N-ch open-drain I/O: 4
A/D converter
8-bit resolution × 8 channels
D/A converter
8-bit resolution × 2 channels
Serial interface
• 3-wire serial I/O/SBI/2-wire serial I/O mode selection possible: 1 channel
• 3-wire serial I/O mode (Max. 32-byte on-chip automatic transmit/receive): 1
channel
• 3-wire serial I/O/UART mode selectable: 1 channel
Timers
•
•
•
•
Timer output
Three outputs: (14-bit PWM output enable: 1)
Clock output
15.6 kHz, 31.3 kHz, 62.5 kHz, 125 kHz, 250 kHz, 500 kHz, 1.0 MHz,
2.0 MHz, 4.0 MHz (@ 6.0 MHz with main system clock)
32.768 kHz (@ 32.768 kHz with subsystem clock)
Buzzer output
977 Hz, 1.95 kHz, 3.9 kHz, 7.8 kHz (@ 6.0 MHz with main system clock)
Notes
16-bit timer/event counter:
8-bit timer/event counter:
Watch timer:
Watchdog timer:
1
2
1
1
channel
channels
channel
channel
1. The capacity of the internal PROM can be changed using the memory switching register (IMS).
2. The capacity of the internal expansion RAM can be changed using the internal expansion RAM size
switching register (IXS).
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User’s Manual U12761EJ2V0UM
CHAPTER 1
OUTLINE
µPD78095B
Part Number
µPD78096B
µPD78098B
µPD78P098B
Item
Vectored
interrupt
sources
Maskable
Internal: 14
External: 7
Non-maskable
Internal: 1
Software
1
Test inputs
Internal: 1
External: 1
Supply voltage
VDD = 2.7 to 5.5 V
Operating ambient temperature
TA = –40 to +85°C
Package
80-pin plastic QFP (14 × 14)
An overview of the timer/event counter is shown below (for details, refer to CHAPTER 6 16-BIT TIMER/EVENT
COUNTER 0, CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 1 AND 2, CHAPTER 8 WATCH TIMER, or
CHAPTER 9 WATCHDOG TIMER).
16-Bit Timer/
8-Bit Timer/Event
Event Counter 0
Counters 1 and 2
Watch Timer
Watchdog Timer
2 channels Note 3
2 channels
1 channel Note 1
1 channel Note 2
External event counter
√
√
—
—
Timer output
√
√
—
—
PWM output
√
—
—
—
Pulse width measurement
√
—
—
—
Square-wave output
√
√
—
—
One-shot pulse output
√
—
—
—
Interrupt request
√
√
√
√
Test input
—
—
√
—
Operating Interval timer
mode
Function
Notes
1. The watch timer can perform both watch timer and interval timer functions at the same time.
2. The watchdog timer can perform either the watchdog timer function or the interval timer function.
3. When capture/compare registers (CR00, CR01) are specified as compare registers.
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CHAPTER 1
OUTLINE
An overview of serial interfaces is shown below (refer to CHAPTER 14 SERIAL INTERFACE CHANNEL 0 for
details of serial interface 0, CHAPTER 15 SERIAL INTERFACE CHANNEL 1 for details of serial interface channel
1, and CHAPTER 16 SERIAL INTERFACE CHANNEL 2 for details of the serial interface channel 2).
Serial Transfer Mode
3-wire serial I/O
Channel 0
fXX/22,
fXX/23,
Channel 1
fXX/22,
fXX/23,
Channel 2
Clock selection
fXX/2,
fXX/24, fXX/25, fXX/26,
fXX/27, fXX/28, external
clock, TO2 output
fXX/2,
fXX/24, fXX/25, fXX/26,
fXX/27, fXX/28, external
clock, TO2 output
External clock, baud
rate generator output
Transfer method
MSB/LSB switchable as
the start bit
MSB/LSB switchable as
the start bit
Automatic transmit/
receive function
MSB/LSB switchable as
the start bit
Transfer end flag
Serial transfer end
interrupt request flag
(CSIIF0)
Serial transfer end
interrupt request flag
(CSIIF1)
Serial transfer end
interrupt request flag
(SRIF)
Use possible
None
None
SBI (serial bus interface)
2-wire serial I/O
UART
(Asynchronous serial interface)
42
None
User’s Manual U12761EJ2V0UM
Use possible
CHAPTER 1
OUTLINE
1.8 Mask Options
The mask ROM versions (µPD78095B, 78096B, 78098B) provide pull-up resistor mask options which allow users
to specify whether to connect a pull-up resistor to a specific port pin when the user places an order for device
production. Using this mask option when pull-up resistors are required reduces the number of components to add
to the device, resulting in board space saving.
The mask options provided in the µPD78098B Subseries are shown in Table 1-1.
Table 1-1. Mask Options of Mask ROM Versions
Pin Names
Mask Options
P60 to P63
Pull-up resistor connection can be specified in 1-bit units.
1.9 Differences Between µPD78098 Subseries and µPD78098B Subseries
The µPD78098B Subseries has a higher EMI noise immunity than the existing µPD78098 Subseries. Table 12 shows the differences between the µPD78098 Subseries and µPD78098B Subseries. Aside from these differences,
the µPD78098 Subseries has the same functions as the µPD78098B Subseries.
Table 1-2. Differences Between µ PD78098 Subseries and µPD78098B Subseries
µPD78098 Subseries
Part Number
µPD78098B Subseries
Item
EMI noise immunity
None
Provided
ROM capacity of mask ROM version
32 to 60 KB
40 to 60 KB
User’s Manual U12761EJ2V0UM
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CHAPTER 2
PIN FUNCTION
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
2.1.1 Normal operating mode
(1) Port pins (1/2)
Pin Name
P00
P01
I/O
Function
After Reset Alternate Function
Input
Port 0.
Input only
Input
INTP0/TI00
I/O
8-bit I/O port.
Input/output mode can be specified
in 1-bit units.
Input
INTP1/TI01
P02
INTP2
If used as an input port, use of an
P03
INTP3
on-chip pull-up resistor can be
specified by a software setting.
P04
INTP4
P05
INTP5
P06
INTP6
P07 Note 1
Input
P10 to P17 I/O
P20
I/O
P21
P22
P23
Input only
Input
XT1
Port 1.
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, use of an on-chip pull-up resistor can be
specified by a software setting Note 2.
Input
ANI0 to ANI7
Port 2.
Input
SI1
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, use of an on-chip pull-up resistor can be
SO1
specified by a software setting.
STB
SCK1
P24
BUSY
P25
SI0/SB0
P26
SO0/SB1
P27
SCK0
P30
P31
P32
P33
I/O
Port 3.
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, use of an on-chip pull-up resistor can be
specified by a software setting.
Input
TO0
TO1
TO2
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
Notes
—
1. When the P07/XT1 pin is used as an input port, set bit 6 (FRC) of the processor clock control register
(PCC) to 1 (do not use the feedback resistor incorporated in the subsystem clock oscillator).
2. When pins P10/ANI0 to P17/ANI7 are used as analog inputs of the A/D converter, the on-chip pullup resistor is automatically disabled.
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PIN FUNCTION
(1) Port pins (2/2)
Pin Name
I/O
P40 to P47 I/O
Function
Port 4.
8-bit I/O port.
Input/output mode can be specified in 8-bit units.
If used as an input port, use of an on-chip pull-up resistor can be
specified by a software setting.
After Reset
Alternate Function
Input
AD0 to AD7
A8 to A15
Test input flag (KRIF) is set to 1 by falling edge detection.
P50 to P57 I/O
Port 5.
8-bit I/O port.
LED can be driven directly.
Input/output mode can be specified in 1-bit units.
If used as an input port, use of an on-chip pull-up resistor can be specified
by a software setting.
Input
P60
Port 6.
8-bit I/O port.
N-ch open-drain I/O port.
On-chip pull-up resistor can be
Input
Input/output mode can be
specified by mask option.
specified in 1-bit units.
P63
(Mask ROM version only).
LEDs can be driven directly.
P64
If used as an input port, use of an
RD
P65
on-chip pull-up resistor can be
specified by a software setting.
WR
I/O
P61
P62
—
P66
WAIT
P67
ASTB
P70
I/O
P71
P72
P120 to P123 I/O
P124
P125
Input
Port 12.
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
Input
P130 to P131 I/O
Port 13.
2-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as anu port, use of an on-chip pull-up resistor can be specified
by a software setting.
SI2/RxD
SO2/TxD
SCK2/ASCK
RTP0 to RTP3
RTP4/TX
RTP5/RX
If used as an input port, use of an on-chip pull-up resistor can be
specified by a software setting.
P126, P127
Caution
Port 7.
3-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, use of an on-chip pull-up resistor can be specified
by a software setting.
RTP6, RTP7
Input
ANO0 to ANO1
Do not manipulate pins that have alternate functions as port pins as follows during an A/D
conversion operation; otherwise, the specification of the total error during A/D conversion may
not be satisfied.
<1> Rewriting the output latch of a pin when the pin is used as a port
<2> Changing the output level of a pin even when the pin is not being used as a port
User’s Manual U12761EJ2V0UM
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CHAPTER 2
PIN FUNCTION
(2) Non-port pins (1/2)
Pin Name
INTP0
I/O
Input
Function
External interrupt request input for which the valid edge (rising
After Reset Alternate Function
Input
edge, falling edge, or both rising and falling edges) can be specified.
INTP1
P00/TI00
P01/TI01
INTP2
P02
INTP3
P03
INTP4
P04
INTP5
P05
INTP6
P06
SI0
Input
Serial interface serial data input
Input
P25/SB0
SI1
P20
SI2
P70/RxD
SO0
Output
Serial interface serial data output
Input
P26/SB1
SO1
P21
SO2
P71/TxD
SB0
I/O
Serial interface serial data input/output
Input
SB1
SCK0
P25/SI0
P26/SO0
I/O
Serial interface serial clock input/output
Input
P27
SCK1
P22
SCK2
P72/ASCK
STB
Output
Serial interface automatic transmit/receive strobe output
Input
P23
BUSY
Input
Serial interface automatic transmit/receive busy input
Input
P24
RxD
Input
Asynchronous serial interface serial data input
Input
P70/SI2
TxD
Output
Asynchronous serial interface serial data output
Input
P71/SO2
ASCK
Input
Asynchronous serial interface serial clock input
Input
P72/SCK2
TI00
Input
External count clock input to 16-bit timer/event counter 0
Input
P00/INTP0
TI01
Capture trigger signal input to capture register (CR00)
P01/INTP1
TI1
External count clock input to 8-bit timer/event counter 1
P33
TI2
External count clock input to 8-bit timer/event counter 2
P34
TO0
Output
16-bit timer/event counter 0 output (also used for 14-bit PWM output)
Input
P30
TO1
8-bit timer/event counter 1 output
P31
TO2
8-bit timer/event counter 2 output
P32
PCL
Output
Clock output (for main system clock and subsystem clock trimming)
Input
P35
BUZ
Output
Buzzer output
Input
P36
Real-time output port that outputs data in synchronization with a trigger
Input
P120 to P123
RTP0 to RTP3 Output
RTP4
P124/TX
RTP5
P125/RX
RTP6, RTP7
P126, P127
TX
Output
Data output of IEBus controller
Input
P124/RTP4
RX
Input
Data input of IEBus controller
Input
P125/RTP5
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CHAPTER 2
PIN FUNCTION
(2) Non-port pins (2/2)
Pin Name
I/O
Function
After Reset Alternate Function
AD0 to AD7
I/O
Lower address/data bus when expanding external memory
Input
P40 to P47
A8 to A15
Output
Higher address bus when expanding external memory
Input
P50 to P57
RD
Output
Strobe signal output for read operation from external memory
Input
P64
WR
Strobe signal output for write operation to external memory
P65
WAIT
Input
Wait insertion when accessing external memory
Input
P66
ASTB
Output
Strobe output that externally latches address information output to ports
4, 5 to access external memory
Input
P67
ANI0 to ANI7
Input
A/D converter analog input
Input
P10 to P17
ANO0, ANO1
Output
D/A converter analog output
Input
P130, P131
AVREF0
Input
A/D converter reference voltage input
—
—
AVREF1
Input
D/A converter reference voltage input
—
—
AVDD
—
A/D converter analog power supply (also functions as port power supply)
—
—
AVSS
—
A/D converter, D/A converter ground potential (also functions as port ground)
—
—
RESET
Input
System reset input
—
—
X1
Input
Crystal connection for main system clock oscillation
—
—
X2
—
—
—
XT1
Input
XT2
—
VDD
—
VPP
Crystal connection for subsystem clock oscillation
Input
P07
—
—
Positive power supply (except ports and analog block)
—
—
—
High-voltage application for program write/verify. Connect directly to
VSS in normal operating mode.
—
—
VSS
—
Ground potential (except ports and analog block)
—
—
IC
—
Internal connection. Connect directly to VSS.
—
—
Cautions 1. The AVDD pin supplies power to the A/D converter and ports. In an application where the noise
generated from the internal circuitry of the microcontroller must be reduced, connect this
pin to a separate power supply with the same potential as VDD.
2. The AVSS pin is used as the ground of the A/D converter, D/A converter, and ports. In an
application where the noise generated from the internal circuitry of the microcontroller must
be reduced, connect this pin to a ground line separate from VSS.
2.1.2 PROM programming mode (PROM versions only)
Pin Name
I/O
Function
RESET
Input
PROM programming mode setting.
When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the RESET pin,
the PROM programming mode is set.
VPP
Input
High-voltage application for PROM programming mode setting and program write/verify.
A0 to A16
Input
Address bus
D0 to D7
I/O
Data bus
CE
Input
PROM enable input/program pulse input
OE
Input
Read strobe input to PROM
PGM
Input
Program/program inhibit input in PROM programming mode
VDD
—
Positive power supply
VSS
—
Ground potential
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2.2 Description of Pin Functions
2.2.1 P00 to P07 (Port 0)
P00 to P07 function as an 8-bit I/O port. Besides serving as I/O port pins, these pins also function as external
interrupt request inputs, an external count clock input to the timer, a capture trigger signal input, and crystal connection
for subsystem oscillation.
The following operating modes can be specified in 1-bit units.
(1) Port mode
P00 and P07 function as input-only port pins and P01 to P06 function as I/O port pins.
P01 to P06 can be set to input or output in 1-bit units using port mode register 0 (PM0). When used as input
port pins, on-chip pull-up resistors can be connected by setting pull-up resistor option register L (PUOL).
(2) Control mode
P00 and P07 function as external interrupt request inputs, an external count clock input to the timer, and crystal
connection for subsystem clock oscillation.
(a) INTP0 to INTP6
INTP0 to INTP6 are external interrupt request input pins for which the valid edge (rising edge, falling edge,
or both rising and falling edges) can be specified. INTP0 and INTP1 become 16-bit timer/event counter
0 capture trigger signal input pins by valid edge input.
(b) TI00
Pin at which the external count clock is input to 16-bit timer/event counter 0.
(c) TI01
Pin at which the capture trigger signal is input to the capture register (CR00) of 16-bit timer/event counter
0.
(d) XT1
Crystal connection pin for subsystem clock oscillation.
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2.2.2 P10 to P17 (Port 1)
P10 to P17 function as an 8-bit I/O port. Besides serving as I/O port pins, these pins also function as A/D converter
analog inputs.
The following operating modes can be specified in 1-bit units.
(1) Port mode
P10 to P17 function as an 8-bit I/O port.
P10 to P17 can be set to input or output in 1-bit units using port mode register 1 (PM1). When used as input
port pins, on-chip pull-up resistors can be connected by setting pull-up resistor option register L (PUOL).
(2) Control mode
P10 to P17 function as A/D converter analog input pins (ANI0 to ANI7). On-chip pull-up resistors are
automatically disabled when these pins are specified for analog input.
2.2.3 P20 to P27 (Port 2)
P20 to P27 function as an 8-bit I/O port. Besides serving as I/O port pins, these pins also function as data input/
output to/from the serial interface, clock input/output, automatic transmit/receive busy input, and strobe output.
The following operating modes can be specified in 1-bit units.
(1) Port mode
P20 to P27 function as an 8-bit I/O port.
P20 to P27 can be set to input or output in 1-bit units using port mode register 2 (PM2). When used as input
port pins, on-chip pull-up resistors can be connected by setting pull-up resistor option register L (PUOL).
(2) Control mode
P20 to P27 function as data input/output to/from the serial interface, clock input/output, automatic transmit/
receive busy input, and strobe output.
(a) SI0, SI1, SO0, SO1
Serial interface serial data I/O pins.
(b) SCK0 and SCK1
Serial interface serial clock I/O pins.
(c) SB0 and SB1
NEC standard serial bus interface I/O pins.
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(d) BUSY
Serial interface automatic transmit/receive busy input pin
(e) STB
Serial interface automatic transmit/receive strobe output pin
Caution
When this port is used for the serial interface, the I/O and output latches must be set
according to the required function. For the setting, refer to Figure 14-4 Format of Serial
Operation Mode Register 0 and Figure 15-3 Format of Serial Operation Mode Register
1.
2.2.4 P30 to P37 (Port 3)
P30 to P37 function as an 8-bit I/O port. Beside serving as I/O port pins, these pins function as timer input/output,
clock output and buzzer output.
The following operating modes can be specified in 1-bit units.
(1) Port mode
P30 to P37 function as an 8-bit I/O port.
P30 to P37 can be set to input or output in 1-bit units using port mode register 3 (PM3). When used as input
port pins, on-chip pull-up resistors can be connected by setting pull-up resistor option register L (PUOL).
(2) Control mode
P30 to P37 function as timer input/output, clock output, and buzzer output.
(a) TI1 and TI2
Pins at which the external count clock is input to 8-bit timer/event counters 1 and 2.
(b) TO0 to TO2
Timer output pins.
(c) PCL
Clock output pin.
(d) BUZ
Buzzer output pin.
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2.2.5 P40 to P47 (Port 4)
P40 to P47 function as an 8-bit I/O port. Besides serving as I/O port pins, these pins also function as an address/
data bus.
The test input flag (KRIF) can be set to 1 by detecting the falling edge.
The following operating mode can be specified in 8-bit units.
(1) Port mode
P40 to P47 function as an 8-bit I/O port.
P40 to P47 can be set to input or output in 8-bit units using the memory expansion mode register (MM). When
used as input port pins, on-chip pull-up resistors can be connected by setting pull-up resistor option register
L (PUOL).
(2) Control mode
P40 to P47 function as lower address/data bus pins (AD0 to AD7) in external memory expansion mode. When
these pins are used as an address/data bus, on-chip pull-up resistors are automatically disabled.
2.2.6 P50 to P57 (Port 5)
P50 to P57 function as an 8-bit I/O port. Besides serving as I/O port pins, these pins also function as an address
bus.
Port 5 can drive LEDs directly.
The following operating modes can be specified in 1-bit units.
(1) Port mode
P50 to P57 function as an 8-bit I/O port.
P50 to P57 can be set to input or output in 1-bit units using port mode register 5 (PM5). When used as input
port pins, on-chip pull-up resistors can be connected by setting pull-up resistor option register L (PUOL).
(2) Control mode
P50 to P57 function as higher address bus pins (A8 to A15) in external memory expansion mode. When these
pins are used as an address bus, on-chip pull-up resistors are automatically disabled.
2.2.7 P60 to P67 (Port 6)
P60 to P67 function as an 8-bit I/O port. Besides serving as I/O port pins, these pins are also used for control
in external memory expansion mode. P60 to P63 can drive LEDs directly.
The following operating modes can be specified in 1-bit units.
(1) Port mode
P60 to P67 function as an 8-bit I/O ports.
P60 to P67 can be set to input or output in 1-bit units using port mode register 6 (PM6).
P60 to P63 are N-ch open drain outputs. In mask ROM versions, pull-up resistors can be connected using
a mask option.
When P64 to P67 are used as input ports, on-chip pull-up resistors can be connected by setting pull-up resistor
option register L (PUOL).
(2) Control mode
P60 to P67 function as control signal output pins (RD, WR, WAIT, ASTB) in external memory expansion mode.
When a pin is used as a control signal output, its on-chip pull-up resistor is automatically disabled.
Caution When external wait is not used in external memory expansion mode, P66 can be used as an
I/O port.
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2.2.8 P70 to P72 (Port 7)
P70 to P72 function as a 3-bit I/O port. Besides serving as I/O port pins, these pins also function as serial interface
data I/O and clock I/O.
The following operating modes can be specified in 1-bit units.
(1) Port mode
P70 to P72 function as a 3-bit I/O port.
P70 to P72 can be set to input or output in 1-bit units using port mode register 7 (PM7). When used as input
port pins, on-chip pull-up resistors can be connected by setting pull-up resistor option register L (PUOL).
(2) Control mode
P70 to P72 function as serial interface data I/O and clock I/O.
(a) SI2, SO2
Serial interface serial data I/O pins.
(b) SCK2
Serial interface serial clock I/O pin.
(c) RxD, TxD
Asynchronous serial interface serial data I/O pins.
(d) ASCK
Asynchronous serial interface serial clock I/O pin.
Caution When this port is used for the serial interface, the I/O and output latches must be set
according to the required function.
For the setting, see the operation mode setting list in Table 16-2 Serial Interface Channel 2.
2.2.9 P120 to P127 (Port 12)
P120 to P127 function as an 8-bit I/O port. Besides serving as I/O port pins, these pins also function as a realtime output port.
In addition, P124 and P125 are also used to input/output data to/from the IEBus controller.
The following operating modes can be specified in 1-bit units.
(1) Port mode
P120 to P127 function as an 8-bit I/O port.
P120 to P127 can be set to input or output in 1-bit units using port mode register 12 (PM12). When used as
input port pins, on-chip pull-up resistors can be connected by setting pull-up resistor option register H (PUOH).
(2) Control mode
(a) Real-time output port function (RTP0 to RTP7)
P120 to P127 function as a real-time output port that outputs data in synchronization with a trigger.
(b) IEBus controller function (P124 and P125 only: TX and RX)
P124 and P125 are used to input/output data to/from the IEBus controller. In this case, the on-chip pullup resistor of each pin is not used.
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Caution When using P124 and P125 for the IEBus controller, access these pins using an 8-bit
manipulation instruction.
2.2.10 P130 and P131 (Port 13)
P130 and P131 function as a 2-bit I/O port. Besides serving as I/O port pins, these pins are also used for D/A
converter analog output.
The following operating modes can be specified in 1-bit units.
(1) Port mode
P130 and P131 function as a 2-bit I/O port.
P130 and P131 can be set to input or output in 1-bit units using port mode register 13 (PM13). When used
as input port pins, on-chip pull-up resistors can be connected by setting pull-up resistor option register H
(PUOH).
(2) Control mode
P130 and P131 allow D/A converter analog output (ANO0 and ANO1).
Caution When only one of the D/A converter channels is used with AVREF1< VDD, the other pins that
are not used as analog outputs must be set as follows.
•
Set the PM13×
× bit of port mode register 13 (PM13) to 1 (input mode) and connect the
pin to VSS.
•
× bit of port mode register 13 (PM13) to 0 (output mode) and the output latch
Set the PM13×
to 0, to output a low level from the pin.
2.2.11 AVREF0
A/D converter reference voltage input pin.
When the A/D converter is not used, connect this pin to VSS.
2.2.12 AVREF1
D/A converter reference voltage input pin.
When the D/A converter is not used, connect this pin to VDD.
2.2.13 AVDD
This is the analog power supply pin of the A/D converter. It also supplies power to the ports. Always use the same
potential as that of the V DD pin even when A/D converter is not used.
2.2.14 AVSS
This is the ground voltage pin of A/D converter and D/A converter. It is also used as the ground pin of the ports.
Always use the same potential as that of the VSS pin even when A/D converter or D/A converter is not used.
2.2.15 RESET
This is a low-level active system reset input pin.
2.2.16 X1 and X2
Crystal resonator connection pins for main system clock oscillation. For external clock supply, input the signal
to X1 and inverted signal to X2.
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2.2.17 XT1 and XT2
Crystal resonator connection pins for subsystem clock oscillation.
For external clock supply, input the signal to XT1 and inverted signal to XT2.
2.2.18 VDD
Positive power supply pin (except ports and analog block).
2.2.19 VSS
Ground potential pin (except ports and analog block).
2.2.20 VPP (PROM versions only)
High-voltage application pin for PROM programming mode setting and program write/verify. Connect directly to
VSS in the normal operating mode.
2.2.21 IC (mask ROM versions only)
The IC (Internally Connected) pin is provided to set the test mode to check the µPD78098B Subseries at delivery.
Connect it directly to VSS with the shortest possible wire in the normal operating mode.
When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins
is too long or an external noise is input to the IC pin, the user program may not run normally.
Connect the IC pin to the VSS pin directly.
VSS IC
As short as possible
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2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the pin I/O circuit types and the recommended connections for unused pins.
Refer to Figure 2-1 for the I/O circuit configuration of each type.
Table 2-1. Pin I/O Circuit Types (1/2)
Pin Name
I/O
Circuit Type
I/O
P00/INTP0/TI00
2
Input
P01/INTP1/TI01
8-D
I/O
Recommended Connection of Unused Pins
Connect to VSS.
Input: Connect independently to VSS via a
P02/INTP2
resistor.
P03/INTP3
Output: Leave open.
P04/INTP4
P05/INTP5
P06/INTP6
P07/XT1
P10/ANI0 to P17/ANI7
16
Input
11-C
I/O
P20/SI1
8-D
P21/SO1
5-J
P22/SCK1
8-D
P23/STB
5-J
P24/BUSY
8-D
P25/SI0/SB0
10-C
Connect to VDD or VSS.
Input: Connect independently to VDD or
VSS via a resistor.
Output: Leave open.
P26/SO0/SB1
P27/SCK0
P30/TO0
5-J
P31/TO1
P32/TO2
P33/TI1
8-D
P34/TI2
P35/PCL
5-J
P36/BUZ
P37
P40/AD0 to P47/AD7
5-O
Input: Connect independently to VDD via a
resistor.
Output: Leave open.
P50/A8 to P57/A15
5-J
Input: Connect independently to VDD or VSS
via a resistor.
Output: Leave open.
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Table 2-1. Pin I/O Circuit Types (2/2)
Pin Name
I/O
Circuit Type
P60 to P63 (mask ROM version)
13-I
P60 to P63 (PROM version)
13-H
P64/RD
I/O
Recommended Connection of Unused Pins
I/O
Input: Connect independently to VDD via a resistor.
Output: Leave open.
5-J
Input: Connect independently to VDD or
P65/WR
VSS via a resistor.
P66/WAIT
Output: Leave open.
P67/ASTB
P70/SI2/RxD
8-D
P71/SO2/TxD
5-J
P72/SCK2/ASCK
8-D
P120/RTP0 to P123/RTP3
5-J
P124/RTP4/TX
P125/RTP5/RX
P126/RTP6, P127/RTP7
P130/ANO0, P131/ANO1
12-B
Input: Connect independently to VSS via a resistor.
Output: Leave open.
RESET
2
Input
XT2
16
—
AVREF0
—
—
Leave open.
Connect to VSS.
AVREF1
Connect to VDD.
AVDD
Connect this pin to a separate power
supply with the same potential as VDD.
AVSS
Connect this pin to a separate ground with
the same potential as VSS.
IC (mask ROM version)
Connect directly to VSS.
VPP (PROM version)
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Figure 2-1. Pin I/O Circuits (1/2)
Type 2
Type 8-D
AVDD
Pullup
enable
P-ch
IN
AVDD
Data
P-ch
IN/OUT
Schmitt-triggered input with
hysteresis characteristics
Output
disable
N-ch
AVSS
Type 5-J
Type 10-C
AVDD
Pullup
enable
AVDD
Pullup
enable
P-ch
P-ch
AVDD
Data
AVDD
P-ch
Data
P-ch
IN/OUT
Output
disable
IN/OUT
Open drain
Output disable
N-ch
N-ch
AVSS
AVSS
Input
enable
AVDD
Type 5-O
Pullup
enable
P-ch
P-ch
AVDD
Data
P-ch
IN/OUT
P-ch
Output
disable
IN/OUT
Output
disable
AVDD
Pullup
enable
AVDD
Data
Type 11-C
Comparator
+
–
N-ch
AVSS
N-ch
P-ch
AVSS
AVSS N-ch
VREF (Threshold voltage)
Input
enable
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Figure 2-1. Pin I/O Circuits (2/2)
Type 12-B
Type 13-I
AVDD
Pullup
enable
AVDD
Mask
Option
P-ch
IN/OUT
AVDD
Data
Data
Output disable
P-ch
N-ch
AVSS
IN/OUT
Output
disable
AVDD
N-ch
AVSS
Input
enable
P-ch
RD
P-ch
Analog output
voltage
Medium breakdown
input buffer
N-ch
AVSS
Type 13-H
Type 16
Feedback
cut-off
IN/OUT
Data
Output disable
N-ch
P-ch
AVSS
AVDD
RD
P-ch
Medium breakdown
input buffer
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CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
The µPD78098B Subseries can access a 64 KB memory space. Figures 3-1 to 3-4 show the memory maps.
Figure 3-1. Memory Map (µPD78095B)
FFFFH
Special-Function
Registers (SFRs)
256 × 8 bits
FF00H
FEFFH General-purpose Registers
32 × 8 bits
FEE0H
FEDFH
Internal High-speed RAM
1,024 × 8 bits
FB00H
FAFFH
Reserved
FAE0H
FADFH
FAC0H
FABFH
Buffer RAM
32 × 8 bits
Reserved
Data memory
space
F900H
F8FFH
F8E0H
F8DFH
F000H
EFFFH
9FFFH
IEBus Register
32 × 8 bits
Reserved
Program Area
1000H
0FFFH
CALLF Entry Area
External Memory
20,480 × 8 bits
0800H
07FFH
Program Area
Program
memory
space
0080H
007FH
A000H
9FFFH
CALLT Table Area
Internal ROM
40,960 × 8 bits
0040H
003FH
Vector Table Area
0000H
0000H
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Figure 3-2. Memory Map (µPD78096B)
FFFFH
Special-Function
Registers (SFRs)
256 × 8 bits
FF00H
FEFFH General-Purpose Registers
32 × 8 bits
FEE0H
FEDFH
Internal High-speed RAM
1,024 × 8 bits
FB00H
FAFFH
Reserved
FAE0H
FADFH
FAC0H
FABFH
Buffer RAM
32 × 8 bits
Reserved
Data memory
space
F900H
F8FFH
F8E0H
F8DFH
F000H
EFFFH
BFFFH
IEBus Register
32 × 8 bits
Reserved
Program Area
1000H
0FFFH
CALLF Entry Area
External Memory
12,288 × 8 bits
0800H
07FFH
Program Area
Program
memory
space
0080H
007FH
C000H
BFFFH
CALLT Table Area
Internal ROM
49,152 × 8 bits
0040H
003FH
Vector Table Area
0000H
0000H
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Figure 3-3. Memory Map (µPD78098B)
FFFFH
Special-Function
Registers (SFRs)
256 × 8 bits
FF00H
FEFFH General-Purpose Registers
32 × 8 bits
FEE0H
FEDFH
Internal High-speed RAM
1,024 × 8 bits
FB00H
FAFFH
Reserved
FAE0H
FADFH
FAC0H
FABFH
Buffer RAM
32 × 8 bits
Reserved
F900H
F8FFH
Data memory
space
F8E0H
F8DFH
F800H
F7FFH
EFFFH
IEBus Register
32 × 8 bits
1000H
0FFFH
Reserved
CALLF Entry Area
Internal
Expansion RAM
2,048 × 8 bits
Program Area
CALLT Table Area
Note
Internal ROM
61,440 × 8 bits
0040H
003FH
Vector Table Area
0000H
Note
0800H
07FFH
0080H
007FH
F000H
EFFFH
Program
memory
space
Program Area
0000H
If the internal ROM capacity is 60 KB, the external device expansion function cannot be used. When
the internal ROM capacity is set to 56 KB or less by using the memory size switching register (IMS),
the last address of the internal ROM through to address EFFFH can be used as an external memory.
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Figure 3-4. Memory Map (µPD78P098B)
FFFFH
Special-Function
Registers (SFRs)
256 × 8 bits
FF00H
FEFFH General-Purpose Registers
32 × 8 bits
FEE0H
FEDFH
Internal High-speed RAM
1,024 × 8 bits
FB00H
FAFFH
Reserved
FAE0H
FADFH
FAC0H
FABFH
Buffer RAM
32 × 8 bits
Reserved
F900H
F8FFH
Data memory
space
F8E0H
F8DFH
F800H
F7FFH
EFFFH
IEBus Register
32 × 8 bits
1000H
0FFFH
Reserved
CALLF Entry Area
Internal
Expansion RAM
2,048 × 8 bits
0800H
07FFH
Program Area
0080H
007FH
F000H
EFFFH
Program
memory
space
Program Area
CALLT Table Area
Note
Internal PROM
61,440 × 8 bits
0040H
003FH
Vector Table Area
0000H
0000H
Note
If the internal PROM capacity is 60 KB, the external device expansion function cannot be used.
When the internal PROM capacity is set to 56 KB or less by using the memory size switching register
(IMS), the last address of the internal PROM through to address EFFFH can be used as an external
memory.
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3.1.1 Internal program memory space
The µPD78098B Subseries has various sizes of internal ROM or PROM as shown below.
The internal program memory space stores programs and table data. Normally, they are addressed using the
program counter (PC).
Internal ROM
Part Number
µPD78095B
Type
Mask ROM
Capacity
40,960 × 8 bits
µPD78096B
49,152 × 8 bits
µPD78098B
61,440 × 8 bits
µPD78P098B
PROM
61,440 × 8 bits
The internal program memory is divided into the following three areas.
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(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. Program start addresses for branch
upon RESET input or interrupt request generation are stored in the vector table area. Of a 16-bit address,
the lower 8 bits are stored at even addresses and higher 8 bits are stored at odd addresses.
Table 3-1. Vector Table
Vector Table Address
Interrupt Source
0000H
RESET input
0004H
INTWDT
0006H
INTP0
0008H
INTP1
000AH
INTP2
000CH
INTP3
000EH
INTP4
0010H
INTP5
0012H
INTP6
0014H
INTCSI0
0016H
INTCSI1
0018H
INTSER
001AH
INTSR/INTCSI2
001CH
INTST
001EH
INTTM3
0020H
INTTM00
0022H
INTTM01
0024H
INTTM1
0026H
INTTM2
0028H
INTAD
002AH
INTIE
003EH
BRK
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) CALLF instruction entry area
The area of 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
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3.1.2 Internal data memory space
The µPD78098B Subseries units incorporate the following RAMs.
(1) Internal high-speed RAM
High-speed memory of the following configuration is incorporated:
1,024 × 8 bits from FB00H to FEFFH
In this area, four banks of general-purpose registers, each bank consisting of eight 8-bit registers, are allocated
in the 32-byte area FEE0H to FEFFH.
The internal high-speed RAM can also be used as a stack memory.
(2) Buffer RAM
Buffer RAM is allocated to the 32-byte area from FAC0H to FADFH. The buffer RAM is used to store transmit/
receive data of serial interface channel 1 (in 3-wire serial I/O mode with automatic transfer/receive function).
If the 3-wire serial I/O mode with automatic transfer/receive function is not used, the buffer RAM can also be
used as normal RAM.
(3) Internal expansion RAM (µPD78098B, 78P098B only)
Internal expansion RAM is allocated to the 2,048-byte area from F000H to F7FFH.
3.1.3 Special-Function Register (SFR) area
On-chip peripheral hardware special-function registers (SFRs) are allocated in the area FF00H to FFFFH. (Refer
to Table 3-2. Special-Function Register List in 3.2.3 Special-Function Registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
3.1.4 External memory space
The external memory space is accessible by setting the memory expansion mode register (MM). External memory
space can store program and table data, etc. and be allocated for peripheral devices.
3.1.5 IEBus register space
IEBus registers are allocated in the area F8E0H to F8FFH.
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3.1.6 Data memory addressing
The method to specify the address of the instruction to be executed next, or the address of a register or memory
to be manipulated when an instruction is executed is called addressing.
The address of the instruction to be executed next is addressed by the program counter PC (for details, refer to
3.3 Instruction Address Addressing).
To address the memory that is manipulated when an instruction is executed, the µPD78098B Subseries is provided
with many addressing modes to allow high operability. At addresses corresponding to data memory area (FB00H
to FFFFH) especially, specific addressing modes corresponding to the particular function of an area, such as the
special-function registers or general-purpose registers, are available. Figures 3-5 to 3-8 show the data memory
addressing modes. For details of each addressing, refer to 3.4 Operand Address Addressing.
Figure 3-5. Data Memory Addressing (µPD78095B)
FFFFH
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
Special-Function
Registers (SFRs)
256 × 8 bits
General-Purpose Registers
32 × 8 bits
SFR Addressing
Register Addressing
Short Direct
Addressing
Internal High-speed RAM
1,024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
Reserved
FAE0H
FADFH
Buffer RAM
32 × 8 bits
Direct Addressing
Reserved
Based Addressing
Register Indirect
Addressing
FAC0H
FABFH
F900H
F8FFH
Based Indexed
Addressing
IEBus Register
32 × 8 bits
F8E0H
F8DFH
Reserved
F000H
EFFFH
External Memory
20,480 × 8 bits
A000H
9FFFH
Internal ROM
40,960 × 8 bits
0000H
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Figure 3-6. Data Memory Addressing (µPD78096B)
FFFFH
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
Special-Function
Registers (SFRs)
256 × 8 bits
General-Purpose Registers
32 × 8 bits
SFR Addressing
Register Addressing
Short Direct
Addressing
Internal High-speed RAM
1,024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
Reserved
FAE0H
FADFH
Buffer RAM
32 × 8 bits
Direct Addressing
Reserved
Based Addressing
Register Indirect
Addressing
FAC0H
FABFH
F900H
F8FFH
Based Indexed
Addressing
IEBus Register
32 × 8 bits
F8E0H
F8DFH
Reserved
F000H
EFFFH
External Memory
12,288 × 8 bits
C000H
BFFFH
Internal ROM
49,152 × 8 bits
0000H
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Figure 3-7. Data Memory Addressing (µPD78098B)
FFFFH
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
Special-Function
Registers (SFRs)
256 × 8 bits
General-Purpose Registers
32 × 8 bits
SFR Addressing
Register Addressing
Short Direct
Addressing
Internal High-speed RAM
1,024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
Reserved
FAE0H
FADFH
Direct Addressing
Buffer RAM
32 × 8 bits
Register Indirect
Addressing
FAC0H
FABFH
Reserved
Based Addressing
F900H
F8FFH
Based Indexed
Addressing
IEBus Register
32 × 8 bits
F8E0H
F8DFH
Reserved
F000H
EFFFH
Internal Expansion RAM
2,048 × 8 bits
F000H
EFFFH
Note
Internal ROM
61,440 × 8 bits
0000H
Note
If the internal ROM capacity is 60 KB, the external device expansion function cannot be used. When
the internal ROM capacity is set to 56 KB or less by using the memory size switching register (IMS),
the last address of the internal ROM through to address EFFFH can be used as an external memory.
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Figure 3-8. Data Memory Addressing (µPD78P098B)
FFFFH
FF20H
FF1FH
FF00H
FEFFH
FEE0H
FEDFH
Special-Function
Registers (SFRs)
256 × 8 bits
General-Purpose Registers
32 × 8 bits
SFR Addressing
Register Addressing
Short Direct
Addressing
Internal High-speed RAM
1,024 × 8 bits
FE20H
FE1FH
FB00H
FAFFH
Reserved
FAE0H
FADFH
Buffer RAM
32 × 8 bits
Direct Addressing
Register Indirect
Addressing
FAC0H
FABFH
Reserved
Based Addressing
F900H
F8FFH
F8E0H
F8DFH
Based Indexed
Addressing
IEBus Register
32 × 8 bits
Reserved
F000H
EFFFH
Internal Expansion RAM
2,048× 8 bits
F000H
EFFFH
Internal PROM Note
61,440× 8 bits
0000H
Note
If the internal PROM capacity is 60 KB, the external device expansion function cannot be used.
When the internal PROM capacity is set to 56 KB or less by using the memory size switching register
(IMS), the last address of the internal PROM through to address EFFFH can be used as an external
memory.
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3.2 Processor Registers
The µPD78098B Subseries units incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist
of a program counter (PC), a program status word (PSW) and a stack pointer (SP).
(1) Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction
to be fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the program counter to the reset vector table values at addresses 0000H and 0001H.
Figure 3-9. Program Counter Configuration
15
PC
0
PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags that are set/reset by instruction
execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically reset upon execution of the RETB, RETI and POP PSW instructions.
RESET input sets the PSW to 02H.
Figure 3-10. Program Status Word Configuration
7
PSW
70
IE
0
Z
RBS1
AC
RBS0
0
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(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledgement operations of the CPU.
When IE = 0, all interrupts except the non-maskable interrupt are disabled (DI status).
When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupts is controlled
with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority
specification flag.
The interrupt enable flag is reset to 0 when the DI instruction is executed or when an interrupt request
is acknowledged, and set to 1 when the EI instruction is executed.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (to 1). It is reset (to 0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags used to select one of the four register banks.
Two-bit information indicating the register bank selected by SEL RBn instruction execution is stored in
these flags.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (to 1). It is reset (to 0)
in all other cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, the
vectored interrupt request whose priority is specified by the priority specify flag registers (PR0L, PR0H,
and PR1L) (refer to 18.3 (3) Priority specify flag registers (PR0L, PR0H, and PR1L)) to be low is
disabled. Whether the interrupt request is actually acknowledged is controlled by the status of the interrupt
enable flag (IE).
(f) Carry flag (CY)
This flag stores an overflow or underflow generated by add/subtract instruction execution. It stores the
shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation
instruction execution.
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(3) Stack pointer (SP)
This is a 16-bit register that holds the start address of the memory stack area. Only the internal high-speed
RAM area (FB00H to FEFFH) can be set as the stack area.
Figure 3-11. Stack Pointer Configuration
15
SP
0
SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from
the stack memory.
Each stack operation saves/resets data as shown in Figures 3-12 and 3-13.
Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before
instruction execution.
Figure 3-12. Data to Be Saved to Stack Memory
PUSH rp Instruction
Interrupt and
BRK Instructions
CALL, CALLF, and
CALLT Instructions
SP
SP
SP _ 2
SP
SP _ 2
SP _ 3
SP _ 3
PC7 to PC0
SP _ 2
Register Pair Lower
SP _ 2
PC7 to PC0
SP _ 2
PC15 to PC8
SP _ 1
Register Pair Upper
SP _ 1
PC15 to PC8
SP _ 1
PSW
SP
SP
SP
Figure 3-13. Data to Be Restored from Stack Memory
POP rp Instruction
SP
RETI and RETB
Instructions
RET Instruction
SP
Register Pair Lower
SP
PC7 to PC0
SP
PC7 to PC0
SP + 1
Register Pair Upper
SP + 1
PC15 to PC8
SP + 1
PC15 to PC8
SP + 2
PSW
SP + 2
SP
SP + 2
SP
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3.2.2 General-purpose registers
General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The
general-purpose registers consist of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and
H).
In addition to use as an 8-bit register, two 8-bit registers can also be used in pairs as a 16-bit register (AX, BC,
DE, and HL).
These registers can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because
of the 4-register bank configuration, an efficient program can be created by switching between a register for normal
processing and a register for interrupts for each bank.
Figure 3-14. General-Purpose Register Configuration
(a) Absolute Name
16-Bit Processing
8-Bit Processing
FEFFH
R7
BANK0
RP3
R6
FEF8H
FEF7H
R5
BANK1
RP2
R4
FEE0H
FEEFH
R3
RP1
BANK2
R2
FEE8H
FEE7H
R1
RP0
BANK3
R0
FEE0H
15
0
7
0
(b) Function Name
16-Bit Processing
8-Bit Processing
FEFFH
H
BANK0
HL
L
FEF8H
FEF7H
D
BANK1
DE
E
FEF0H
FEEFH
B
BC
BANK2
C
FEE8H
FEE7H
A
AX
BANK3
X
FEE0H
15
0
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0
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3.2.3 Special-Function Register (SFR)
Unlike a general-purpose register, each special-function register has a special function.
The special-function registers are allocated in the area FF00H to FFFFH.
Special-function registers can be manipulated like general-purpose registers, by operation, transfer and bit
manipulation instructions. The manipulatable bit unit, 1, 8, or 16, depends on the special-function register type.
The manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).
When addressing an address, describe an even address.
Table 3-2 lists the special-function registers. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special-function register. These symbols are reserved words in the RA78K0
and defined by header file sfrbit.h in the CC78K0, and can be used as the operands of instructions when the
RA78K0, ID78K0, and SD78K0 are used.
• R/W
Indicates whether the corresponding special-function register can be read or written.
R/W: Read/write enabled
R:
Read only
W:
Write only
• Manipulatable bit units
√ indicates the bit unit (1, 8 or 16 bits) in which the register can be manipulated. — indicates that the register
cannot be manipulated in the indicated bit unit.
• After reset
Indicates the status of each register upon RESET input.
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Table 3-2. Special-Function Register List (1/3)
Manipulatable Bit Unit
Address
Special-Function Register (SFR) Name
Symbol
R/W
After Reset
1 Bit
8 Bits
16 Bits
√
√
—
P1
√
√
—
Port2
P2
√
√
—
FF03H
Port3
P3
√
√
—
FF04H
Port4
P4
√
√
—
FF05H
Port5
P5
√
√
—
FF06H
Port6
P6
√
√
—
FF07H
Port7
P7
√
√
—
FF0CH
Port12
P12
√ Note
√
—
FF0DH
Port13
P13
√
√
—
FF10H
FF11H
Capture/compare register 00
CR00
—
—
√
FF12H
FF13H
Capture/compare register 01
CR01
—
—
√
FF14H
FF15H
16-bit timer counter 0
TM0
R
—
—
√
0000H
FF16H
Compare register 10
CR10
R/W
—
√
—
Undefined
FF17H
Compare register 20
CR20
—
√
—
FF18H
8-bit timer counter 1
—
√
√
00H
FF19H
8-bit timer counter 2
—
√
FF1AH
Serial I/O shift register 0
SIO0
—
√
—
Undefined
FF1BH
Serial I/O shift register 1
SIO1
—
√
—
FF1FH
A/D conversion result register
ADCR
R
—
√
—
FF20H
Port mode register 0
PM0
R/W
√
√
—
FF21H
Port mode register 1
PM1
√
√
—
FF22H
Port mode register 2
PM2
√
√
—
FF23H
Port mode register 3
PM3
√
√
—
FF25H
Port mode register 5
PM5
√
√
—
FF26H
Port mode register 6
PM6
√
√
—
FF27H
Port mode register 7
PM7
√
√
—
FF2CH
Port mode register 12
PM12
√
√
—
FF2DH
Port mode register 13
PM13
√
√
—
FF30H
Real-time output buffer register L
RTBL
—
√
—
FF31H
Real-time output buffer register H
RTBH
—
√
—
FF34H
Real-time output port mode register
RTPM
√
√
—
FF36H
Real-time output port control register
RTPC
√
√
—
FF00H
Port0
P0
FF01H
Port1
FF02H
Note
TMS
TM1
R/W
R
TM2
R/W
00H
Undefined
00H
Undefined
FFH
00H
Do not manipulate this port in 1-bit units when the IEBus controller is used.
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Table 3-2. Special-Function Register List (2/3)
Manipulatable Bit Unit
Address
Special-Function Register (SFR) Name
Symbol
R/W
After Reset
1 Bit
8 Bits
16 Bits
√
√
—
TCL1
—
√
—
Timer clock select register 2
TCL2
—
√
—
FF43H
Timer clock select register 3
TCL3
—
√
—
88H
FF47H
Sampling clock select register
SCS
—
√
—
00H
FF48H
16-bit timer mode control register 0
TMC0
√
√
—
FF49H
8-bit timer mode control register 1
TMC1
√
√
—
FF4AH
Watch timer mode control register 2
TMC2
√
√
—
FF4CH
Capture/compare control register 0
CRC0
√
√
—
FF4EH
16-bit timer output control register 0
TOC0
√
√
—
FF4FH
8-bit timer output control register 1
TOC1
√
√
—
FF60H
Serial operating mode register 0
CSIM0
√
√
—
FF61H
Serial bus interface control register
SBIC
√
√
—
FF62H
Slave address register
SVA
—
√
—
Undefined
FF63H
Interrupt timing specify register
SINT
√
√
—
00H
FF68H
Serial operating mode register 1
CSIM1
√
√
—
FF69H
Automatic data transmit/receive control register
ADTC
√
√
—
FF6AH
Automatic data transmit/receive address pointer
ADTP
—
√
—
FF6BH
Automatic data transmit/receive interval specify register
ADTI
√
√
—
FF70H
Asynchronous serial interface mode register
ASIM
√
√
—
FF71H
Asynchronous serial interface status register
ASIS
R
√
√
—
FF72H
Serial operating mode register 2
CSIM2
R/W
√
√
—
FF73H
Baud rate generator control register
—
√
—
FF74H
Transmit shift register
TXS
—
√
—
FFH
Receive buffer register
RXB
FF80H
A/D converter mode register
ADM
√
√
—
01H
FF84H
A/D converter input select register
ADIS
—
√
—
00H
FF90H
D/A conversion value set register 0
DACS0
—
√
—
FF91H
D/A conversion value set register 1
DACS1
—
√
—
FF98H
D/A converter mode register
DAM
√
√
—
FF40H
Timer clock select register 0
TCL0
FF41H
Timer clock select register 1
FF42H
76
R/W
BRGC
SIO2
W
0000H
04H
R
R/W
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Table 3-2. Special-Function Register List (3/3)
Manipulatable Bit Unit
Address
Special-Function Register (SFR) Name
Symbol
R/W
After Reset
1 Bit
8 Bits
16 Bits
√
√
—
Undefine
IF0L
√
√
√
00H
IF0H
√
√
√
√
—
MK0L
√
√
√
MK0H
√
√
√
√
—
PR0L
√
√
√
PR0H
√
√
PR1L
√
√
—
External interrupt mode register 0
INTM0
—
√
—
FFEDH
External interrupt mode register 1
INTM1
—
√
—
FFF0H
Memory size switching register
IMS
—
√
—
Note2
FFF2H
Oscillation mode selection register
OSMS
W
—
√
—
00H
FFF3H
Pull-up resistor option register H
PUOH
R/W
√
√
—
FFF4H
Internal expansion RAM size
switching registerNote 3
IXS
W
—
√
—
08HNote 4
FFF6H
Key return mode register
KRM
R/W
√
√
—
02H
FFF7H
Pull-up resistor option register L
PUOL
√
√
—
00H
FFF8H
Memory expansion mode register
MM
√
√
—
10H
FFF9H
Watchdog timer mode register
WDTM
√
√
—
00H
FFFAH
Oscillation stabilization time select register
OSTS
—
√
—
04H
FFFBH
Processor clock control register
PCC
√
√
—
FFD0H to
FFDFH
External access areaNote 1
FFE0H
Interrupt request flag register 0L
FFE1H
Interrupt request flag register 0H
FFE2H
Interrupt request flag register 1L
FFE4H
Interrupt mask flag register 0L
FFE5H
Interrupt mask flag register 0H
FFE6H
Interrupt mask flag register 1L
FFE8H
Priority order specify flag register 0L
FFE9H
Priority order specify flag register 0H
FFEAH
Priority order specify flag register 1L
FFECH
Notes
R/W
IF0
IF1L
MK0
MK1L
PR0
FFH
00H
1. The external access area cannot be accessed by SFR addressing. Access the area with direct
addressing.
2. The value after reset depends on the product.
µPD78095B: CAH, µPD78096B: CCH, µPD78098B: CFH, µPD78P098B: CFH
Do not set a value other than the value after reset to IMS when a mask ROM version is used, except
when the external device expansion function is used with the µPD78098B.
3. This register is provided only in the µPD78098B and 78P098B.
4. Do not set a value other than the value after reset to IXS when a mask ROM version is used.
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3.2.4 IEBus registers
The IEBus registers are mainly used to control the IEBus controller.
These registers are allocated in the area F8E0H to F8FFH.
They can be manipulated by an operation instruction and transfer instruction.
The manipulatable bit unit, 8 or 16, depends on the IEBus register setting.
The manipulation bit unit can be specified as follows.
• 8-bit manipulation
This manipulation can be specified by an address.
• 16-bit manipulation
This manipulation can be specified by an even address.
Caution The IEBus registers cannot be read or written in 1-bit units. To write 1-bit data to a register, use
an 8-bit transfer instruction after adding another 7-bit data to the 1-bit data. To reference (read)
1 bit of the register, read an 8-bit value to the A register, and then execute a bit manipulation
instruction to the A register.
Table 3-3 lists the IEBus registers. The meanings of items in this table are as follows.
• Symbol
These symbols indicate the IEBus register.
• R/W
Indicates whether the corresponding IEBus register can be read or written.
R/W: Read/write enabled
R:
Read only
W:
Write only
• Manipulatable bit units
√ indicates the bit unit (8 or 16 bits) in which the register can be manipulated.
cannot be manipulated in the indicated bit unit.
• After reset
Indicates the status of each register upon RESET input.
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 indicates that the register
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Table 3-3. IEBus Register List
Address
IEBus Register Name
Symbol
R/W
R/W
Manipulatable Bit Unit
8 Bits
16 Bits
√
√
After Reset
F8E0H
Clock select register 1
IECL1 IECL
F8E1H
Clock select register 2
IECL2
√
F8E2H
A/D current cut select register
IEAD
√
—
F8E3H
IEBus controller mode register
IECM
√
—
F8F0H
Control register
CTR
√
—
F8F1H
Command register
CMR
F8F0H
Status register 1
STR1
F8F1H
Status register 2
STR2
F8F2H
Unit address register 1
UAR1
F8F3H
Unit address register 2
UAR2
F8F2H
Number of receive data register 1
RDR1 RDR
F8F3H
Number of receive data register 2
RDR2
F8F4H
Slave address register 1
SAR1
F8F5H
Slave address register 2
SAR2
F8F4H
Lock address register 1
LOR1
F8F5H
Lock address register 2
LOR2
F8F6H
Master communication control register
MCR
F8F6H
Broadcast destination address resister 1
DAR1
F8F7H
Broadcast destination address register 2
DAR2
F8F8H
Return code register
RCR
R
√
—
4FH
F8FEH
Transmit buffer register
TBF
W
√
—
Undefined
Receive buffer register
RBF
R
√
—
W
√
STR
R
√
W
√
×××00×01B
00H
√
√
UAR
00H
01011×××B
02H
√
Undefined
√
00H
√
Undefined
√
Undefined
√
R
√
√
SAR
W
√
√
LOR
R
√
√
DAR
0000××××B
W
√
—
R
√
√
Undefined
√
Caution The registers listed in Table 3-3 are not registered in the device file.
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3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents. The contents of the PC are normally
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed. When a branch instruction is executed, the branch destination information is
set to the PC and branched by the following addressing. (For details of instructions, refer to 78K/0 Instruction User's
Manual (U12326E).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the
start address of the following instruction is transferred to the program counter (PC) and branched. The
displacement value is treated as signed two's complement data (–128 to +127) and bit 7 becomes a sign bit.
In the relative addressing mode, execution branches in a relative range of –128 to +127 from the first address
of the next instruction.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
0
... PC indicates the start address
of the instruction
after the BR instruction.
PC
+
15
8
α
7
0
6
S
jdisp8
15
0
PC
When S = 0, all bits of α are 0.
When S = 1, all bits of α are 1.
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3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
The CALL !addr16 and BR !addr16 instructions can branch in the entire memory space. The CALLF !addr11
instruction branches to an area of addresses 0800H through 0FFFH.
[Illustration]
In the case of CALL !addr16 and BR !addr16 instructions
7
0
CALL or BR
Low Addr.
High Addr.
15
8 7
0
PC
In the case of CALLF !addr11 instruction
7 6
4
3
fa10–8
0
CALLF
fa7–0
15
PC
0
11 10
0
0
0
8 7
0
1
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3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the
immediate data of an operation code are transferred to the program counter (PC) and branched.
Table indirect addressing is performed when the CALLT [addr5] instruction is executed. This instruction
references an address stored in the memory table at addresses 40H through 7FH, and can branch in the entire
memory space.
[Illustration]
7
Operation Code
6
1
5
1
1
ta4–0
1
15
Effective Address
0
7
0
0
0
0
0
0
Memory (Table)
0
8
7
6
0
0
1
5
1 0
0
0
Low Addr.
High Addr.
Effective Address+1
15
8
7
PC
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3.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
rp
0
7
A
15
0
X
8
7
0
PC
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3.4 Operand Address Addressing
The following methods are available to specify the register and memory (addressing) to undergo manipulation
during instruction execution.
3.4.1 Implied addressing
[Function]
The register that functions as an accumulator (A and AX) in the general-purpose register is automatically
(implicitly) addressed.
Of the µPD78098B Subseries instruction words, the following instructions employ implied addressing.
Instruction
Register to Be Specified by Implied Addressing
MULU
A register for multiplicand and AX register for product storage
DIVUW
AX register for dividend and quotient storage
ADJBA/ADJBS
A register for storage of numeric values that become decimal correction targets
ROR4/ROL4
A register for storage of digit data that undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format is
necessary.
[Description example]
In the case of MULU X
With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,
the A and AX registers are specified by implied addressing.
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3.4.2 Register addressing
[Function]
This addressing accesses a general-purpose register as an operand. The general-purpose register accessed
is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an
instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
[Operand format]
Identifier
Description
r
X, A, C, B, E, D, L, H
rp
AX, BC, DE, HL
'r' and 'rp' can be described with function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) as well as absolute
names (R0 to R7 and RP0 to RP3).
[Description example]
MOV A, C; when selecting C register as r
Operation code
0 1 1 0 0 0 1 0
Register specify code
INCW DE; when selecting DE register pair as rp
Operation code
1 0 0 0 0 1 0 0
Register specify code
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3.4.3 Direct addressing
[Function]
This addressing directly addresses the memory indicated by the immediate data in an instruction word.
[Operand format]
Identifier
Description
addr16
Label or 16-bit immediate data
[Description example]
MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code
1 0 0 0 1 1 1 0
OP code
0 0 0 0 0 0 0 0
00H
1 1 1 1 1 1 1 0
FEH
[Illustration]
7
0
OP code
saddr16 (low)
saddr16 (high)
Memory
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3.4.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
The fixed space to which this address is applied is a 256-byte space of addresses FE20H through FF1FH. Internal
high-speed RAM and special-function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH,
respectively.
The SFR area (FF00H through FF1FH) to which short direct addressing is applied is a part of the entire SFR
area. Ports frequently accessed by the program, and the compare registers and capture registers of timer/event
counters are mapped to this area. These SFRs can be manipulated with a short byte length and a few clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH,
bit 8 is set to 1. Refer to [Illustration] on next page.
[Operand format]
Identifier
Description
saddr
Label of FE20H to FF1FH immediate data
saddrp
Label of FE20H to FF1FH immediate data (even address only)
[Description example]
MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H
Operation code
0 0 0 1 0 0 0 1
OP code
0 0 1 1 0 0 0 0
30H (saddr-offset)
0 1 0 1 0 0 0 0
50H (immediate data)
[Illustration]
7
0
OP code
saddr-offset
Short Direct Memory
15
Effective Address
1
8 7
1
1
1
1
1
1
0
α
When 8-bit immediate data is 20H to FFH, α = 0
When 8-bit immediate data is 00H to 1FH, α = 1
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3.4.5 Special-Function Register (SFR) addressing
[Function]
A memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs
mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier
Description
sfr
Special-function register name
sfrp
16-bit manipulatable special-function register name (even address only)
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code
1 1 1 1 0 1 1 0
OP code
0 0 1 0 0 0 0 0
20H (sfr-offset)
[Illustration]
7
0
OP code
sfr-offset
SFR
15
Effective Address
88
1
8 7
1
1
1
1
1
1
1
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3.4.6 Register indirect addressing
[Function]
This addressing addresses the memory with the contents of a register pair specified as an operand. The register
pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code
in an instruction code. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
—
Description
[DE], [HL]
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
Operation code
1 0 0 0 0 1 0 1
[Illustration]
16
DE
8 7
0
E
D
7
Memory
0
Memory address specified
by register pair DE
Contents of addressed
memory are transferred.
7
0
A
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3.4.7 Based addressing
[Function]
This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair
which is used as a base register and by using the result of the addition. The HL register pair to be accessed
is in the register bank specified by the register bank select flags (RBS0 and RBS1). Addition is performed by
expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing
can be carried out for all the memory spaces.
[Operand format]
Identifier
—
Description
[HL + byte]
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code
1 0 1 0 1 1 1 0
0 0 0 1 0 0 0 0
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3.4.8 Based indexed addressing
[Function]
This addressing addresses the memory by adding the contents of the HL register, which is used as a base register,
to the contents of the B or C register specified in the instruction word, and by using the result of the addition.
The HL, B, and C registers to be accessed are registers in the register bank specified by the register bank select
flags (RBS0 and RBS1). The addition is performed by extending the contents of the B or C register to 16 bits
as a positive number. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory
spaces.
[Operand format]
Identifier
—
Description
[HL + B], [HL + C]
[Description example]
In the case of MOV A, [HL + B]
Operation code
1 0 1 0 1 0 1 1
3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN
instructions are executed or the register is saved/reset upon generation of an interrupt request.
Stack addressing can address the internal high-speed RAM area only.
[Description example]
In the case of PUSH DE
Operation code
1 0 1 1 0 1 0 1
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CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
The µPD78098B Subseries units incorporate two input ports and sixty-seven I/O ports. Figure 4-1 shows the port
configuration. Every port can be manipulated in 1-bit and 8-bit units and can carry out a variety of control operations.
Besides port functions, the ports can also serve as on-chip hardware I/O pins.
Figure 4-1. Port Types
P50
P00
Port 0
Port 5
P57
P07
P60
P10
Port 1
Port 6
P67
P17
P70
P20
Port 7
P72
Port 2
P120
P27
P30
Port 12
P127
Port 3
P130
Port 13
P131
P37
P40 to P47
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Table 4-1. Port Functions (1/2)
Pin Name
P00
P01
Function
Port 0.
8-bit I/O port.
Input only
INTP0/TI00
Input/output mode can be specified
INTP1/TI01
in 1-bit units.
P02
If used as an input port, use of an on-chip
pull-up resistor can be specified by a
software setting.
P03
P04
Alternate Function
INTP2
INTP3
INTP4
P05
INTP5
P06
INTP6
P07
P10 to P17
P20
P21
P22
P23
Input only
Port 1.
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, use of an on-chip pull-up resistor can be specified by a software setting.
Port 2.
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, use of an on-chip pull-up resistor can be specified by a software
setting.
XT1
ANI0 to ANI7
SI1
SO1
SCK1
STB
P24
BUSY
P25
SI0/SB0
P26
SO0/SB1
P27
SCK0
P30
Port 3.
TO0
P31
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, use of an on-chip pull-up resistor can be specified by a software
TO1
setting.
TI1
P32
P33
TO2
P34
TI2
P35
PCL
P36
BUZ
P37
—
P40 to P47
Port 4.
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, use of an on-chip pull-up resistor can be specified by a software setting.
Test input flag (KRIF) is set to 1 by falling edge detection.
AD0 to AD7
P50 to P57
Port 5.
8-bit I/O port.
LEDs can be driven directly.
Input/output mode can be specified in 1-bit units.
If used as an input port, use of an on-chip pull-up resistor can be specified by a software setting.
A8 to A15
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Table 4-1. Port Functions (2/2)
Pin Name
Function
P60
Port 6.
N-ch open-drain I/O port.
P61
8-bit I/O port.
Use of an on-chip pull-up resistor can be
Input/output mode can be specified
specified by a mask option. (Mask ROM
in 1-bit units.
P63
versions only).
LEDs can be driven directly.
P64
If used as an input port, use of an on-chip
P62
pull-up register can be specified by a
P65
Alternate Function
—
RD
WR
software setting.
P66
WAIT
P67
ASTB
P70
P71
P72
P120 to P123
P124
P125
Port 7.
3-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, use of an on-chip pull-up resistor can be specified by a software setting.
Port 12.
SO2/TxD
SCK2/ASCK
RTP0 to RTP3
8-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, use of an on-chip pull-up resistor can be specified by a software setting.
P126, P127
RTP4/TX
RTP5/RX
RTP6, RTP7
P130 and P131 Port 13.
2-bit I/O port.
Input/output mode can be specified in 1-bit units.
If used as an input port, use of an on-chip pull-up resistor can be specified by a software setting.
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4.2 Port Configuration
A port consists of the following hardware.
Table 4-2. Port Configuration
Item
Configuration
Control registers
Port mode register (PMm: m = 0 to 3, 5 to 10, 12, 13)
Pull-up resistor option register (PUOH, PUOL)
Memory expansion mode register (MM) Note
Key return mode register (KRM)
Port
Total: 69 ports (input × 2, I/O × 67)
Pull-up resistors
• Mask ROM version
Total: 67 (software specifiable: 63, mask option: 4)
• PROM version
Total: 63
Note
MM specifies port 4 input/output.
4.2.1 Port 0
Port 0 is an 8-bit I/O port with an output latch. P01 to P06 can be set input or output mode in 1-bit units using
port mode register 0 (PM0). P00 and P07 are input-only pins. When P01 to P06 are used as input pins, an on-chip
pull-up resistor can be connected in 6-bit units by setting pull-up resistor option register L (PUOL).
Alternate functions include external interrupt request input, external count clock input to the timer and crystal
connection for subsystem clock oscillation.
RESET input sets port 0 to input mode.
Figures 4-2 and 4-3 show block diagrams of port 0.
Caution Because port 0 also serves as an external interrupt request input, when the port function output
mode is specified and the output level is changed, the interrupt request flag is set. Thus, when
the output mode is used, set the interrupt mask flag to 1.
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Internal Bus
Figure 4-2. Block Diagram of P00 and P07
RD
P00/INTP0/TI00,
P07/XT1
Figure 4-3. Block Diagram of P01 to P06
AVDD
WRPUO
PUO0
P-ch
RD
Internal Bus
Selector
WRPORT
P01/INTP1/TI01.
P02/INTP2
Output Latch
(P01 to P06)
P06/INTP6
WRPM
PM01 to PM06
PUO: Pull-up resistor option register
PM:
Port mode register
RD:
Port 0 read signal
WR: Port 0 write signal
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4.2.2 Port 1
Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to input or output mode in 1-bit units using port
mode register 1 (PM1). When P10 to P17 are used as input pins, an on-chip pull-up resistor can be connected in
8-bit units by setting pull-up resistor option register L (PUOL).
Alternate functions include A/D converter analog input.
RESET input sets port 1 to input mode.
Figure 4-4 shows a block diagram of port 1.
Caution A pull-up resistor cannot be used for pins used as A/D converter analog inputs.
Figure 4-4. Block Diagram of P10 to P17
AVDD
WRPUO
PUO1
P-ch
RD
Internal Bus
Selector
WRPORT
P10/ANI0,
Output Latch
(P10 to P17)
P17/ANI7
WRPM
PM10 to PM17
PUO: Pull-up resistor option register
PM:
Port mode register
RD:
Port 1 read signal
WR: Port 1 write signal
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4.2.3 Port 2
Port 2 is an 8-bit I/O port with an output latch. P20 to P27 can be set to input or output mode in 1-bit units using
port mode register 2 (PM2). When P20 to P27 are used as input pins, an on-chip pull-up resistor can be connected
in 8-bit units by setting pull-up resistor option register L (PUOL).
Alternate functions include serial interface data I/O, clock I/O, automatic transmit/receive busy input, and strobe
output.
RESET input sets port 2 to input mode.
Figures 4-5 and 4-6 show a block diagram of port 2.
Cautions 1.
When used for the serial interface, set the I/O and output latch according to the required
function. For the setting method, refer to Figure 14-4 Format of Serial Operating Mode
Register 0 and Figure 15-3 Format of Serial Operating Mode Register 1.
2.
When reading the pin state in SBI mode, set the PM2n bit of PM2 to 1 (n = 5, 6) (refer to the
description in (10) Judging busy state of slave in 14.4.3 SBI Mode Operation).
Figure 4-5. Block Diagram of P20, P21, P23 to P26
AVDD
WRPUO
PUO2
P-ch
RD
Internal Bus
Selector
WRPORT
P20/SI1,
P21/SO1,
P23/STB,
P24/BUSY,
P25/SI0/SB0,
P26/SO0/SB1
Output Latch
(P20, P21, P23 to P26)
WRPM
PM20, PM21
PM23 to PM26
Alternate Function
PUO: Pull-up resistor option register
PM:
Port mode register
RD:
Port 2 read signal
WR: Port 2 write signal
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Figure 4-6. Block Diagram of P22 and P27
AVDD
WRPUO
PUO2
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P22, P27)
P22/SCK1,
P27/SCK0
WRPM
PM22, PM27
Alternate Function
PUO: Pull-up resistor option register
PM:
Port mode register
RD:
Port 2 read signal
WR: Port 2 write signal
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4.2.4 Port 3
Port 3 is an 8-bit I/O port with an output latch. P30 to P37 can be set to input or output mode in 1-bit units using
port mode register 3 (PM3). When P30 to P37 are used as input pins, an on-chip pull-up resistor can be connected
in 8-bit units by setting pull-up resistor option register L (PUOL).
Alternate functions include timer I/O, clock output and buzzer output.
RESET input sets port 3 to input mode.
Figure 4-7 shows a block diagram of port 3.
Figure 4-7. Block Diagram of P30 to P37
AVDD
WRPUO
PUO3
P-ch
RD
Internal Bus
Selector
WRPORT
P30/TO0
Output Latch
(P30 to P37)
P32/TO2,
P33/TI1,
P34/TI2,
P35/PCL,
P36/BUZ,
P37
WRPM
PM30 to PM37
Alternate Function
PUO: Pull-up resistor option register
PM:
Port mode register
RD:
Port 3 read signal
WR: Port 3 write signal
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4.2.5 Port 4
Port 4 is an 8-bit I/O port with an output latch. P40 to P47 can be set to input or output mode in 8-bit units using
the memory expansion mode register (MM). When P40 to P47 are used as input pins, an on-chip pull-up resistor
can be connected in 8-bit units by setting pull-up resistor option register L (PUOL).
The test input flag (KRIF) can be set to 1 by falling edge detection.
Alternate functions include operation as an address/data bus in external memory expansion mode.
RESET input sets port 4 to input mode.
Figures 4-8 and 4-9 show a block diagram of port 4 and the falling edge detector, respectively.
Figure 4-8. Block Diagram of P40 to P47
AVDD
WRPUO
PUO4
P-ch
RD
Internal Bus
Selector
WRPORT
P40/AD0
Output Latch
(P40 to P47)
P47/AD7
WRMM
MM
PUO: Pull-up resistor option register
MM: Memory expansion mode register
RD:
Port 4 read signal
WR: Port 4 write signal
Figure 4-9. Block Diagram of Falling Edge Detector
P40
P41
P42
P43
Falling Edge
Detector
KRIF Set Signal
KRMK
Standby Release
Signal
P44
P45
P46
P47
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4.2.6 Port 5
Port 5 is an 8-bit I/O port with an output latch. P50 to P57 can be set to input or output mode in 1-bit units using
port mode register 5 (PM5). When P50 to P57 are used as input pins, an on-chip pull-up resistor can be connected
in 8-bit units by setting pull-up resistor option register L (PUOL).
Port 5 can drive LEDs directly.
Alternate functions include operation as an address bus in external memory expansion mode.
RESET input sets port 5 to input mode.
Figure 4-10 shows a block diagram of port 5.
Figure 4-10. Block Diagram of P50 to P57
AVDD
WRPUO
PUO5
P-ch
RD
Internal Bus
Selector
WRPORT
P50/A8
Output Latch
(P50 to P57)
P57/A15
WRPM
PM50 to PM57
PUO: Pull-up resistor option register
PM:
Port mode register
RD:
Port 5 read signal
WR: Port 5 write signal
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4.2.7 Port 6
Port 6 is an 8-bit I/O port with an output latch. P60 to P67 can be set to input or output mode in 1-bit units using
port mode register 6 (PM6).
This port has functions related to pull-up resistors as shown below. These functions depend on whether the higher
4 bits or lower 4 bits of the port are used, and whether the mask ROM model or PROM model is used.
Table 4-3. Pull-up Resistor of Port 6
Higher 4 Bits (P64 to P67)
Mask ROM
version
On-chip pull-up resistor can be connected in 4-bit
units by PUO6
PROM version
Lower 4 bits (P60 to P63)
Pull-up resistor can be connected in 1-bit units by
mask option
Pull-up resistor is not connected
PUO6: Bit 6 of pull-up resistor option register L (PUOL)
P60 to P63 can drive LEDs directly.
Alternate functions include control signal output in external memory expansion mode.
RESET input sets port 6 to input mode.
Figures 4-11 and 4-12 show block diagrams of port 6.
Cautions 1. When external wait is not used in external memory expansion mode, P66 can be used as an
I/O port.
2. The value of the low-level input leakage current flowing to the P60 through P63 pins differs
depending on the following conditions.
[Mask ROM version]
• When pull-up resistor is connected: Always –3 µA (MAX.)
• When pull-up resistor is not connected
·
For the duration of 1.5 clocks (no wait) when an instruction to read port 6 (P6) and
port mode register 6 (PM6) is executed: –200 µA (MAX.)
·
–3 µA (MAX.)
Other than above:
[PROM version]
• For the duration of 1.5 clocks (no wait) when an instruction to read port 6 (P6) and
port mode register 6 (PM6) is executed:
• Other than above:
–200 µA (MAX.)
–3 µA (MAX.)
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Figure 4-11. Block Diagram of P60 to P63
AVDD
RD
Mask Option Resistor
Mask ROM versions
only. PROM versions
have no pull-up resistor.
Internal Bus
Selector
WRPORT
Output Latch
(P60 to P63)
P60 to P63
WRPM
PM60 to PM63
PM: Port mode register
RD: Port 6 read signal
WR: Port 6 write signal
Figure 4-12. Block Diagram of P64 to P67
AVDD
WRPUO
PUO6
P-ch
RD
Internal Bus
Selector
WRPORT
P64/RD,
P65/WR,
P66/WAIT,
P67/ASTB
Output Latch
(P64 to P67)
WRPM
PM64 to PM67
PUO: Pull-up resistor option register
PM:
Port mode register
RD:
Port 6 read signal
WR: Port 6 write signal
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4.2.8 Port 7
This is a 3-bit I/O port with an output latch. P70 to P72 can be set to input or output mode in 1-bit units using port
mode register 7 (PM7). When P70 to P72 are used as input pins, an on-chip pull-up resistor can be connected in
3-bit units by setting pull-up resistor option register L (PUOL).
Alternate functions include serial interface channel 2 data I/O and clock I/O.
RESET input sets port 7 to input mode.
Figures 4-13 and 4-14 show block diagrams of port 7.
Caution When used for the serial interface, set the I/O and output latch according to the required function.
For the setting method, refer to Table 16-2 Operating Mode Setting of Serial Interface Channel
2.
Figure 4-13. Block Diagram of P70
AVDD
WRPUO
PUO7
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P70)
P70/SI2/RxD
WRPM
PM70
PUO: Pull-up resistor option register
PM:
Port mode register
RD:
Port 7 read signal
WR: Port 7 write signal
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Figure 4-14. Block Diagram of P71 and P72
AVDD
WRPUO
PUO7
P-ch
RD
Internal Bus
Selector
WRPORT
Output Latch
(P71 and P72)
P71/SO2/TxD,
P72/SCK2/ASCK
WRPM
PM71, PM72
Alternate Function
PUO: Pull-up resistor option register
PM:
Port mode register
RD:
Port 7 read signal
WR: Port 7 write signal
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4.2.9 Port 12
This is an 8-bit I/O port with an output latch. P120 to P127 can be set to input or output mode in 1-bit units using
port mode register 12 (PM12). When P120 to P127 are used as input pins, an on-chip pull-up resistor can be connected
in 8-bit units by setting pull-up resistor option register H (PUOH).
Alternate functions include real-time output and data I/O for the IEBus controller.
RESET input sets port 12 to input mode.
Figures 4-15 to 4-17 show block diagrams of port 12.
Caution The following read-modify-write instructions cannot be used to manipulate port 12 when the
IEBus controller is used.
SET1
P12X
CLR1
P12X
BTCLR
P12X
OR
P12, #byte
XOR
P12, #byte
AND
P12, #byte
Instructions to manipulate any bit of port 12
Figure 4-15. Block Diagram of P120 to P123, P126, and P127
AVDD
WRPUO
PUO12
P-ch
RD
Internal Bus
Selector
WRPORT
P120/RTP0
Output Latch
(P120 to P123,
P126, P127)
P123/RTP3,
P126/RTP6,
P127/RTP7
WRPM
PM120 to PM123,
PM126, PM127
PUO: Pull-up resistor option register
PM:
Port mode register
RD:
Port 12 read signal
WR: Port 12 write signal
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Figure 4-16. Block Diagram of P124
AVDD
WRPUO
PUO12
P-ch
RD
Selector
WRPORT
Internal Bus
Output Latch
(P124)
P124/RTP4/TX
WRPM
PM124
WRIECM
Note
IECM0
WRIECM
IECM1
Output data of IEBus
controller (TX)
PUO: Pull-up resistor option register
PM:
Port mode register
IECM: IEBus controller mode register
RD:
Port 12 read signal
WR:
Port 12 write signal
Note
The in-circuit emulator cannot emulate the function that automatically disconnects the
on-chip pull-up resistors when IECM = 0.
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Figure 4-17. Block Diagram of P125
AVDD
WRPUO
PUO12
P-ch
RD
Selector
WRPORT
Internal Bus
Output Latch
(P125)
P125/RTP5/RX
WRPM
PM125
WRIECM
Note
IECM0
WRIECM
IECM1
Input data of IEBus
controller (RX)
PUO: Pull-up resistor option register
PM:
Port mode register
IECM: IEBus controller mode register
RD:
Port 12 read signal
WR:
Port 12 write signal
Note
The in-circuit emulator cannot emulate the function that automatically disconnects the
on-chip pull-up resistors when IECM = 0.
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4.2.10 Port 13
This is a 2-bit I/O port with an output latch. P130 and P131 can be set to input or output mode in 1-bit units using
port mode register 13 (PM13). When P130 and P131 are used as input pins, an on-chip pull-up resistor can be
connected in 2-bit units by setting pull-up resistor option register H (PUOH).
Alternate functions include D/A converter analog output.
RESET input sets port 13 to input mode.
Figure 4-18 shows a block diagram of port 13.
Caution When only one of the D/A converter channels is used with AVREF1< VDD, the other pins that
are not used as analog outputs must be set as follows.
•
Set the PM13 bit of port mode register 13 (PM13) to 1 (input mode) and connect the
•
Set the PM13x bit of port mode register 13 (PM13) to 0 (output mode) and the output latch
pin to VSS.
to 0, to output a low level from the pin.
Figure 4-18. Block Diagram of P130 and P131
AVDD
WRPUO
PUO13
P-ch
RD
Internal Bus
Selector
WRPORT
P130/ANO0,
P131/ANO1
Output Latch
(P130 and P131)
WRPM
PM130, PM131
PUO: Pull-up resistor option register
PM:
Port mode register
RD:
Port 13 read signal
WR: Port 13 write signal
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4.3 Registers Controlling Port Function
The following four types of registers control the ports.
• Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13)
• Pull-up resistor option registers (PUOH, PUOL)
• Memory expansion mode register (MM)
• Key return mode register (KRM)
(1) Port mode registers (PM0 to PM3, PM5 to PM7, PM12, PM13)
These registers are used to set the port to input/output in 1-bit units.
PM0 to PM3, PM5 to PM7, PM12, and PM13 are independently set with a 1-bit or 8-bit memory manipulation
instruction
RESET input sets these registers to FFH.
When port pins are used as alternate-function pins, set the port mode register and output latch according to
Table 4-4.
Cautions 1. Pins P00 and P07 are input-only pins.
2. As port 0 has an alternate function as an external interrupt request input, when the port
function output mode is specified and the output level is changed, the interrupt request
flag is set. When the output mode is used, therefore, the interrupt mask flag should be
set to 1 beforehand.
3. The memory expansion mode register (MM) specifies the input/output mode of P40 to
P47.
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Table 4-4. Port Mode Register and Output Latch Settings When Using Alternate Functions
Pin Name
Alternate Functions
Name
PM××
P××
Pin Name
Alternate Functions
I/O
Name
PM××
P××
I/O
INTP0
Input
1 (Fixed)
None
P50 to P57
A8 to A15
Output
×Note 2
TI00
Input
1 (Fixed)
None
P64
RD
Output
×Note 2
INTP1
Input
1
×
P65
WR
Output
×Note 2
TI01
Input
1
×
P66
WAIT
Input
×Note 2
P02 to P06
INTP2 to INTP6
Input
1
×
P67
ASTB
Output
×Note 2
P07Note 1
XT1
Input
1 (Fixed)
None
Input
1
×
Output
0
0
Input
1
×
0
P00
P01
P10 to P17Note 1 ANI0 to ANI7
P30 to P32
TO0 to TO2
P33, P34
TI1, TI2
P35
PCL
Output
0
P36
BUZ
Output
0
P40 to P47
Notes
AD0 to AD7
I/O
0
×Note 2
P120 to P123 RTP0 to RTP3
Output
0
Desired value
P124
RTP4
Output
0
Desired value
TX
Output
1
0
RTP5
Output
0
Desired value
Input
1
×
RTP6, RTP7
Output
0
Desired value
ANO0, ANO1
Output
1
0
P125
RX
P126, P127
P130,
P131Note 1
1. If these ports are read when these pins are used in the alternate function mode, undefined values are
read.
2. When the P40 to P47 pins, P50 to P57 pins, and P64 to P67 pins are used as alternate functions,
set the function using the memory expansion mode register (MM).
Cautions 1. When not using external wait in the external memory expansion mode, the P66 pin can be
used as an I/O port.
2. When port 2 and port 7 are used for the serial interface, the I/O latch or output latch must
be set according to the required function. For the setting method, see Figure 14-4 Format
of Serial Operation Mode Register 0, Figure 15-3 Format of Serial Operation Mode
Register 1, and Table 16-2 Operating Mode Settings of Serial Interface Channel 2.
Remarks ×:
don’t care
PM××: port mode register
P××:
112
port output latch
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PORT FUNCTIONS
Figure 4-19. Format of Port Mode Registers
Symbol
7
PM0
1
6
5
4
3
2
1
PM06 PM05 PM04 PM03 PM02 PM01
0
Address
After
Reset
R/W
1
FF20H
FFH
R/W
PM1
PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
FF21H
FFH
R/W
PM2
PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20
FF22H
FFH
R/W
PM3
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
FF23H
FFH
R/W
PM5
PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50
FF25H
FFH
R/W
PM6
PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60
FF26H
FFH
R/W
PM72 PM71 PM70
FF27H
FFH
R/W
PM12 PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120
FF2CH
FFH
R/W
PM13
FF2DH
FFH
R/W
PM7
1
1
PMmn
1
1
1
1
1
1
1
1
1
PM131 PM130
Pmn Pin Input/Output Mode Selection (m = 0 to 3, 5 to 7, 12, 13: n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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(2) Pull-up resistor option registers (PUOH, PUOL)
These registers are used to set whether to use an on-chip pull-up resistor at each port or not. A pull-up resistor
is internally used at bits that are set to the input mode at a port where on-chip pull-up resistor use has been
specified with PUOH or PUOL. No on-chip pull-up resistors can be used for bits set to the output mode or
bits used as an analog input pin, irrespective of the PUOH or PUOL setting.
PUOH and PUOL are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Cautions 1. The P00 and P07 pins do not incorporate a pull-up resistor.
2. When ports 1, 4, 5, and the P64 to P67 pins are used as alternate-function pins, an onchip pull-up resistor cannot be used even if the PUOm bit of PUOH or PUOL (m = 1, 4
to 6) is set to 1.
3. Pins P60 to P63 can be connected to a pull-up resistor by mask option only in mask ROM
versions.
Figure 4-20. Format of Pull-Up Resistor Option Registers
Symbol
7
6
PUOH
0
0
7
6
PUOL
4
PUO13 PUO12
5
4
3
2
1
0
Address
After
Reset
R/W
0
0
0
0
FFF3H
00H
R/W
3
2
1
0
FFF7H
00H
R/W
PUO7 PUO6 PUO5 PUO4 PUO3 PUO2 PUO1 PUO0
PUOm
Caution
114
5
Pm On-Chip Pull-Up Resistor Selection (m = 0 to 7, 12, 13)
0
On-chip pull-up resistor not used
1
On-chip pull-up resistor used
Bits 0 to 3, 6, and 7 of PUOH should be set to 0.
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PORT FUNCTIONS
(3) Memory expansion mode register (MM)
This register is used to set port 4 to input/output.
MM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 10H.
Caution If the 2/3 divider (in divider 1) of the clock generator is used when the main system clock
is generated, the external device expansion function cannot be used.
Figure 4-21. Format of Memory Expansion Mode Register
Symbol
7
6
5
4
3
2
1
0
Address
After
Reset
R/W
MM
0
0
PW1
PW0
0
MM2
MM1
MM0
FFF8H
10H
R/W
Wait Control
PW1 PW0
0
0
No wait
0
1
Wait (one wait state insertion)
1
0
Setting prohibited
1
1
Wait control by external wait pin
MM2 MM1
0
0
MM0
Single-chip/Memory
Expansion Mode
Selection
0
Single-chip mode
0
0
1
0
1
1
256-byte
mode
1
0
0
4 KB
mode
1
0
1
Memory
expansion
mode
P40 to P47, P50 to P57, P64 to P67 Pin State
P40 to P47 P50 to P53
Input
Port
mode Output
1
1
Other than above
Note
P56, P57
P64 to P67
Port mode
Port mode
P64 = RD
Port mode
P65 = WR
AD0 to AD7
16 KB
mode
P66 = WAIT
Port mode
A8 to A11
P67 = ASTB
A12, A13
Note
1
P54, P55
Full
address
mode
A14, A15
Setting prohibited
The full address mode allows external expansion for all areas of the 64 KB address space, except
the internal ROM, RAM, SFR, and use-prohibited areas.
Remarks 1. P60 to P63 enter the port mode in both the single-chip and memory expansion mode.
2. Besides setting port 4 input/output, MM also sets the wait count and external expansion area.
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(4) Key return mode register (KRM)
This register sets enabling/disabling of standby function release by a key return signal (falling edge detection
of port 4).
KRM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets KRM to 02H.
Figure 4-22. Format of Key Return Mode Register
Symbol
7
6
5
4
3
2
KRM
0
0
0
0
0
0
1
0
KRMK KRIF
Address
After
Reset
R/W
FFF6H
02H
R/W
Standby Mode Control by Key Return Signal
KRMK
0
Standby mode release enabled
1
Standby mode release disabled
Key Return Signal Detection Flag
KRIF
0
Not detected
1
Detected (falling edge detection of port 4)
Caution When falling edge detection of port 4 is used, KRIF should be cleared to 0 (it is not cleared
to 0 automatically).
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4.4 Port Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
4.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from
the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status
does not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated,
the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output
pins, the output latch contents for pins specified as input are undefined except for the
manipulated bit.
4.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
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4.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output
latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
(2) Input mode
The output latch contents are undefined, but since the output buffer is off, the pin status does not change.
Caution In the case of a 1-bit memory manipulation instruction, although a single bit is manipulated
the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output
pins, the output latch contents for pins specified as input are undefined, even for bits other
than the manipulated bit.
4.5 Selection of Mask Option
The following mask option is provided in mask ROM versions. PROM versions have no mask options.
Table 4-5. Comparison Between Mask ROM Version and PROM Version
Pin Name
Mask option for pins P60 to P63
118
Mask ROM Version
On-chip pull-up resistors selectable in 1-bit units
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PROM Version
No on-chip pull-up resistor
CHAPTER 5
CLOCK GENERATOR
CHAPTER 5 CLOCK GENERATOR
5.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two
system clock oscillators are available.
(1) Main system clock oscillator
This circuit oscillates at frequencies of 1 to 6.29 MHz. Oscillation can be stopped by executing the STOP
instruction or setting the processor clock control register (PCC).
(2) Subsystem clock oscillator
The circuit oscillates at a frequency of 32.768 kHz. Oscillation cannot be stopped. If the subsystem clock
oscillator is not used, not using the internal feedback resistance can be set by the processor clock control
register (PCC). This enables a decrease in the power consumption in the STOP mode.
5.2 Clock Generator Configuration
The clock generator consists of the following hardware.
Table 5-1. Clock Generator Configuration
Item
Configuration
Control registers
Processor clock control register (PCC)
Oscillation mode selection register (OSMS)
Oscillator
Main system clock oscillator
Subsystem clock oscillator
Clock select registers 1 and 2 (IECL1 and IECL2)
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120
Figure 5-1. Block Diagram of Clock Generator
FRC
XT1/P07
XT2
Subsystem fXT
Clock
Oscillator
IECL11
Watch Timer,
Clock Output
Function
Note
Clock to IEBus
Controller
Divider 2
Prescaler
1/2
Note
X1
Divider 1
Prescaler
fXX
fXX
22
fXX
23
fXX
24
Standby
Controller
3
Wait
Controller
To INTP0
Sampling Clock
STOP
IECL20
Clock Select
Register 2
IECL11 IECL10
Clock Select
Register 1
MCS
Oscillation Mode
Selection Register
Internal Bus
Note
For the configuration of dividers 1 and 2, refer to Figure 5-2.
MCC
FRC
CLS
CSS PCC2 PCC1 PCC0
Processor Clock Control Register
CPU Clock (fCPU)
CLOCK GENERATOR
Selector
fXX
2
fXT
2
CHAPTER 5
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X2
Main System
Clock
fX
Oscillator
Clock to Peripheral
Hardware
Figure 5-2. Configuration of Dividers 1 and 2
Divider 1
IECL20
IECL10
MCS
Selector
1/2 divider
Main System Clock
Oscillation Frequency (fX)
IECL11
Operating Clock of IEBus Controller (fS)
CLOCK GENERATOR
Divider 2
Main System Clock
Frequency (fXX)
CHAPTER 5
User’s Manual U12761EJ2V0UM
Selector
1/2 divider
Selector
2/3 divider
Selector
1/3 divider
Main System Clock
Oscillation Frequency (fX)
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CLOCK GENERATOR
5.3 Registers Controlling Clock Generator
The clock generator is controlled by the following four registers.
• Processor clock control register (PCC)
• Oscillation mode selection register (OSMS)
• Clock select registers 1 and 2 (IECL1 and IECL2)
(1) Processor clock control register (PCC)
The PCC selects CPU clock and sets the ratio of division, main system clock oscillator operation/stop and
whether to use the subsystem clock oscillator internal feedback resistor.
The PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the PCC to 04H.
Caution When stopping the main system clock by using the STOP instruction or by setting bit 7 (MCC)
of PCC to 1, be sure to set bit 0 (STREQ) of the control register (CTR) to 1 and confirm that
the IEBus controller has entered the standby status. To confirm the standby status, read
bit 1 (STM) of status register 2 (STR2).
Figure 5-3. Subsystem Clock Feedback Resistor
FRC
P-ch
Feedback Resistor
XT1
122
XT2
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CLOCK GENERATOR
Figure 5-4. Format of Processor Clock Control Register
Symbol
7
6
5
4
3
PCC
MCC
FRC
CLS
CSS
0
R/W
MCC
R/W
R
R/W
2
1
0
PCC2 PCC1 PCC0
Oscillation possible
1
Oscillation stopped
R/W
FFFBH
04H
R/WNote 1
Notes 2, 3
Subsystem Clock Feedback Resistor Selection
FRC
0
Internal feedback resistor used
1
Internal feedback resistor not used
CPU Clock Status
CLS
0
Main system clock
1
Subsystem clock
CSS PCC2 PCC1 PCC0
1
After
Reset
Main System Clock Oscillation Control
0
0
Address
0
0
0
CPU CIock (fCPU) Selection
fXX
0
0
1
fXX/2
0
1
0
fXX/2
0
1
1
fXX/23
1
0
0
fXX/24
0
0
0
fXT/2 (122 µ s)
0
0
1
0
1
0
0
1
1
1
0
0
Other than above
2
Setting prohibited
Notes 1. Bit 5 is a read-only bit.
2. When the CPU is operating on the subsystem clock, MCC should be used to stop the main
system clock oscillation. The STOP instruction should not be used.
3. Do not set MCC when an external clock is input. This is because the X2 pin is pulled up to
VDD.
Caution Bit 3 must be set to 0.
Remarks 1. fXX: Main system clock frequency
2. fXT: Subsystem clock oscillation frequency
3. Figures in parentheses indicate the minimum instruction execution time: when operating at
fXT = 32.768 kHz: 2fCPU.
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(2) Oscillation mode selection register (OSMS)
This register specifies whether the 1/2 divider in divider 1 is used.
Eight types of main system clock frequencies (fXX) can be selected by using these registers in combination
with clock select registers 1 and 2 (IECL1 and IECL2).
OSMS is set with an 8-bit memory manipulation instruction.
RESET input clears OSMS to 00H.
Figure 5-5. Format of Oscillation Mode Selection Register
Symbol
7
6
5
4
3
2
1
0
Address
After
Reset
R/W
OSMS
0
0
0
0
0
0
0
MCS
FFF2H
00H
W
Main System Clock Divider Control
MCS
0
Divider used
1
Divider not used
Caution Writing to OSMS should be performed only immediately after reset signal release and before
peripheral hardware operation starts. As shown in Figure 5-6 below, writing data (including
the same data as previously) to OSMS causes the main system clock cycle to be delayed by
up to 2/fx during the write operation. Therefore, in peripheral hardware that operates with
the main system clock, writing this register at a timing other than the above causes a
temporary error in the count clock cycle of the timer, etc. In addition, because the oscillation
mode is changed by this register, the clock for peripheral hardware as well as that for the
CPU is switched.
Figure 5-6. Main System Clock Waveform When Writing to OSMS
Write to OSMS
(MCS
0)
Max. 2/fX
fXX
Operating at fXX = fX/2 (MCS = 0)
Remarks fxx: Main system clock frequency
fx: Main system clock oscillation frequency
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CLOCK GENERATOR
(3) Clock select registers 1 and 2 (IECL1 and IECL2)
These registers specify whether the 1/3 divider and 2/3 divider in divider 1 is used and whether the 1/2 divider
in divider 2 is used.
Eight types of main system clock frequencies can be selected by using these registers in combination with
the oscillation mode selection register (OSMS (refer to Tables 5-2 and 5-3).
IECL1 and IECL2 are set with an 8-bit memory manipulation instruction. When IECL1 and IECL2 are used
in combination as a 16-bit register, they can be set with a 16-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figure 5-7. Format of Clock Select Register 1
Symbol
7
6
5
4
3
2
IECL1
0
0
0
0
0
0
1
0
IECL1 IECL2
Address
After
Reset
R/W
F8E0H
00H
R/W
Main System Clock Divider Control (Divider 2)
IECL11
0
1/2 divider in divider 2 used
1
1/2 divider in divider 2 not used
Main System Clock Divider Control (Divider 1)
IECL10
0
2/3 divider in divider 1 not used
1
2/3 divider in divider 1 used
Caution Bits 2 to 7 must be set to 0.
Figure 5-8. Format of Clock Select Register 2
Symbol
7
6
5
4
3
2
1
0
Address
After
Reset
R/W
IECL2
0
0
0
0
0
0
0
IECL20
F8E1H
00H
R/W
Main System Clock Divider Control (Divider 1)
IECL20
0
1/3 divider in divider 1 not used
1
1/3 divider in divider 1 used
Caution Bits 1 to 7 must be set to 0.
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Table 5-2. Relationship Between Setting of Divider 1 and Main System Clock Frequency
MCS
IECL20
IECL10
0
0
0
fX/2
0
1
fX/3
1
0
fX/6
1
1
fX/9
0
0
fX
0
1
2fX/3
1
0
fX/3 (2fX/6)
1
1
2fX/9
1
MCS:
Main System Clock Frequency (fXX)
Bit 0 of oscillation mode selection register (OSMS)
IECL20: Bit 0 of clock select register 2 (IECL2)
IECL10: Bit 0 of clock select register 1 (IECL1)
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Table 5-3. CPU Clock (fCPU) List
CSS
0
0
0
0
0
1
1
CPU Clock (fCPU) Selection
PCC2 PCC1 PCC0
0
0
1
1
0
0
1
0
1
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
Other than above
MCS
0
0
0
0
1
1
1
1
IECL20
0
0
1
1
0
0
1
1
IECL10
0
1
0
1
0
1
0
1
f xx
f xx/2
f xx/22
f xx/23
f xx/24
fx/2
(2fx/3)/2
(fx/3)/2
(2fx/9)/2
fx
2fx/3
fx/3
2fx/9
(0.67 µs)
(1.00 µs)
(2.00 µs)
(3.00 µs)
(Setting prohibited)
(0.50 µs)
(1.00 µs)
(1.50 µs)
fx/22
(2fx/3)/22
(fx/3)/22
(2fx/9)/22
fx/2
(2fx/3)/2
(fx/3)/2
(2fx/9)/2
(1.33 µs)
(2.00 µs)
(4.00 µs)
(6.00 µs)
(0.67 µs)
(1.00 µs)
(2.00 µs)
(3.00 µs)
fx/23
(2fx/3)/23
(fx/3)/23
(2fx/9)/23
fx/22
(2fx/3)/22
(fx/3)/22
(2fx/9)/22
(2.67 µs)
(4.00 µs)
(8.00 µs)
(12.0 µs)
(1.33 µs)
(2.00 µs)
(4.00 µs)
(6.00 µs)
fx/24
(2fx/3)/24
(fx/3)/24
(2fx/9)/24
fx/23
(2fx/3)/23
(fx/3)/23
(2fx/9)/23
(5.33 µs)
(8.00 µs)
(16.0 µs)
(24.0 µs)
(2.67 µs)
(4.00 µs)
(8.00 µs)
(12.0 µs)
fx/25
(2fx/3)/25
(fx/3)/25
(2fx/9)/25
fx/24
(2fx/3)/24
(fx/3)/24
(2fx/9)/24
(10.7 µs)
(16.0 µs)
(32.0 µs)
(48.0 µs)
(5.33 µs)
(8.00 µs)
(16.0 µs)
(24.0 µs)
f XT/2 (122 µs)
Setting prohibited
Remarks 1. fX:
Main system clock oscillation frequency
2. fXX:
Main system clock frequency
3. fXT:
Subsystem clock oscillation frequency
4. Figures in parentheses indicate the minimum instruction execution time when operating at fX = 6.0
MHz or fXT = 32.768 kHz: 2 fCPU.
Caution The guaranteed operating voltage differs depending on the CPU clock selected. For details, refer
to the data sheet of each product.
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5.4 System Clock Oscillator
5.4.1 Main system clock oscillator
The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 6.0 MHz)
connected to the X1 and X2 pins.
External clocks can be input to the main system clock oscillator. In this case, input the clock signal to the X1 pin
and the inverted clock signal to the X2 pin.
Figure 5-9 shows an external circuit of the main system clock oscillator.
Figure 5-9. External Circuit of Main System Clock Oscillator
(a) Crystal and ceramic oscillation
(b) External clock
X2
X2
External
Clock
µ PD74HCU04
X1
IC
X1
Crystal
or
Ceramic Resonator
Caution Do not execute the STOP instruction or set MCC (bit 7 of processor clock control register (PCC))
to 1 if an external clock is input. Otherwise, the operation of the main system clock will be stopped
and the X2 pin will be pulled up to VDD.
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5.4.2 Subsystem clock oscillator
The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1
and XT2 pins.
External clocks can be input to the main system clock oscillator. In this case, input the clock signal to the XT1
pin and the inverted clock signal to the XT2 pin.
Figure 5-10 shows an external circuit of the subsystem clock oscillator.
Figure 5-10. External Circuit of Subsystem Clock Oscillator
(a) Crystal oscillation
(b) External clock
IC
32.768
kHz
XT2
XT2
External
Clock
XT1
XT1
µ PD74HCU04
Cautions 1. When using the main system clock oscillator and subsystem clock oscillator, wire as follows
in the broken-line area in Figures 5-9 and 5-10 to avoid an adverse effect from wiring
capacitance.
•
Minimize the wiring length.
•
Do not cross the wiring with other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
•
Make the ground point of the oscillator capacitor the same potential as VSS. Do not ground
•
Do not fetch signals from the oscillator.
the capacitor to a ground pattern through which a high current is flows.
Take special note of the fact that the subsystem clock oscillator is a circuit with low-level
amplification so that current consumption is maintained at low levels.
Figure 5-11 shows examples of incorrectly connected oscillators.
Figure 5-11. Examples of Oscillators with Incorrect Connection (1/2)
(a) Wiring of connection circuits is too long
(b) Signal lines cross each other
PORTn
(n = 0 to 7, 12, 13)
X2
Remark
X1
IC
X2
X1
IC
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively, and insert resistors
in series on the side of XT2.
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Figure 5-11. Examples of Oscillators with Incorrect Connection (2/2)
(c) High fluctuating current is too near a
signal line
(d) Current flows through the grounding line
of the oscillator (potential at points A, B,
and C fluctuate)
AVDD
Pnm
X2
X1
IC
X2
X1
IC
High
Current
A
B
C
High
Current
(e) Signals are fetched
X2
Remark
X1
IC
When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively, and insert resistors
in series on the XT2 side.
Cautions 2. If XT2 and X1 are wired in parallel, the cross-talk noise of X1 may synergize with XT2,
resulting in malfunction. To prevent this from occurring, it is recommended to wire XT2
and X1 so that they are not in parallel, and to connect the IC pin between XT2 and X1 directly
to VSS.
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5.4.3 Divider
The divider divides the main system clock oscillator output (fXX) and generates various clocks.
5.4.4 When subsystem clocks not used
If it is not necessary to use the subsystem clock for low power consumption or watch operations, connect the
XT1 and XT2 pins as follows.
XT1: Connect to VDD
XT2: Leave open
In this state, however, some current may leak via the internal feedback resistor of the subsystem clock oscillator
when the main system clock stops. To suppress the leakage current, disconnect the above internal feedback resistor
by using the bit 6 (FRC) of the processor clock control register (PCC). In this case also, connect the XT1 and XT2
pins as described above.
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5.5 Clock Generator Operations
The clock generator generates the following various types of clocks and controls the CPU operating mode
including the standby mode.
• Main system clock
• Subsystem clock
• CPU clock
fXX
fXT
fCPU
• Clock to peripheral hardware
The following clock generator functions and operations are determined by the processor clock control register
(PCC), the oscillation mode selection register (OSMS), and clock select registers 1 and 2 (IECL1 and IECL2).
(a) Upon generation of the RESET signal, the lowest speed mode of the main system clock (10.7 µs when operated
at 6.0 MHz) is selected (PCC = 04H, OSMS = 00H, IECL1 = 00H, IECL2 = 00H). Main system clock oscillation
stops while a low level is being applied to the RESET pin.
(b) With the main system clock selected, one of the 40 CPU clock steps (19 types) can be selected by setting
PCC, OSMS, IECL1, and IECL2.
(c) With the main system clock selected, two standby modes, STOP and HALT, are available. In a system where
the subsystem clock is not used, the current consumption in the STOP mode can be further reduced by
specifying not to use the feedback resistor using bit 6 (FRC) of PCC.
(d) PCC can be used to select the subsystem clock and to operate the system at a low current consumption (122
µs when operated at 32.768 kHz).
(e) With the subsystem clock selected, main system clock oscillation can be stopped using PCC. The HALT mode
can be used, but the STOP mode cannot. (Subsystem clock oscillation cannot be stopped.)
(f)
The main system clock is divided and supplied to the peripheral hardware. The subsystem clock is supplied
to the 16-bit timer/event counter, the watch timer, and clock output functions only. Thus, the 16-bit timer/event
counter (when selecting watch timer output for count clock operating with subsystem clock), the watch function,
and the clock output function can also be continued in the standby state. However, since all other peripheral
hardware operate with the main system clock, the peripheral hardware also stops if the main system clock
is stopped. (Except the external clock input operation.)
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5.5.1 Main system clock operations
When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to
0), the following operations are carried out by PCC settings.
(a) Because the operation-guaranteed instruction execution speed depends on the power supply voltage, the
minimum instruction execution time can be changed by bits 0 to 2 (PCC0 to PCC2) of PCC.
(b) If bit 7 (MCC) of PCC is set to 1 when operated with the main system clock, the main system clock oscillation
does not stop. When bit 4 (CSS) of PCC is set to 1 and the operation is switched to subsystem clock operation
(CLS = 1) after that, the main system clock oscillation stops (see Figure 5-12).
Figure 5-12. Main System Clock Stop Function (1/2)
(a) Operation when MCC is set after setting CSS with main system clock operation
MCC
CSS
CLS
Main System Clock Oscillation
Subsystem Clock Oscillation
CPU Clock
(b) Operation when MCC is set with main system clock operation
MCC
L
CSS
L
CLS
Oscillation does not stop.
Main System Clock Oscillation
Subsystem Clock Oscillation
CPU Clock
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Figure 5-12. Main System Clock Stop Function (2/2)
(c) Operation when CSS is set after setting MCC with main system clock operation
MCC
CSS
CLS
Main System Clock Oscillation
Subsystem Clock Oscillation
CPU Clock
5.5.2 Subsystem clock operations
When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1),
the following operations are carried out.
(a) The minimum instruction execution time remains constant (122 µs when operated at 32.768 kHz) irrespective
of bits 0 to 2 (PCC0 to PCC2) of PCC.
(b) Watchdog timer counting stops.
Caution Do not execute the STOP instruction while the subsystem clock is in operation.
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5.6 Changing System Clock and CPU Clock Settings
5.6.1 Time required for switchover between system clock and CPU clock
The system clock and CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS)
of the processor clock control register (PCC).
The actual switchover operation is not performed directly after writing to PCC; operation continues on the preswitchover clock for several instructions (see Table 5-4).
Determination as to whether the system is operating on the main system clock or the subsystem clock can be made
using bit 5 (CLS) of the PCC register.
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136
Table 5-4. Maximum Time Required for CPU Clock Switchover
Set Values Before
Switchover
Set Values After Switchover
CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0 CSS PCC2 PCC1 PCC0
CSS
PCC2 PCC1 PCC0
0
0
0
0
0
0
1
0
0
0
0
0
1
16 instructions
8 instructions
0
0
1
0
0
0
1
1
0
1
0
0
16 instructions
16 instructions
16 instructions
8 instructions
8 instructions
8 instructions
1
×
×
×
fX/2fXT instruction
(62 instructions)
fX/4fXT instruction
(31 instructions)
1
0
4 instructions
4 instructions
4 instructions
4 instructions
fX/8fXT instruction
(16 instructions)
0
1
1
2 instructions
2 instructions
2 instructions
2 instructions
fX/16fXT instruction
(8 instructions)
1
0
0
1 instruction
1 instruction
1 instruction
fX/32fXT instruction
1 instruction
(4 instructions)
1
×
×
×
1 instruction
1 instruction
1 instruction
1 instruction
1 instruction
Remarks 1. One instruction is executed in the minimum instruction execution time with the pre-switchover CPU clock.
2. Figures in parentheses apply to operation with fX = 4.0 MHz or fXT = 32.768 kHz.
Caution Selection of the CPU clock division (PCC0 to PCC2) and switchover from the main system clock to the
subsystem clock (changing CSS from 0 to 1) should not be performed simultaneously.
Simultaneous setting is possible, however, for selection of the CPU clock division (PCC0 to PCC2) and
switchover from the subsystem clock to the main system clock (changing CSS from 1 to 0).
CLOCK GENERATOR
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5.6.2 System clock and CPU clock switching procedure
This section describes the procedure for switching between the system clock and CPU clock.
Figure 5-13. System Clock and CPU Clock Switching
VDD
RESET
Interrupt
Request
Signal
System Clock
CPU Clock
fXX
fXX
Minimum Maximum Speed
Speed
Operation
Operation
Wait (21.8 ms: 6.0 MHz)
fXT
Subsystem Clock
Operation
fXX
High-Speed
Operation
Internal Reset Operation
(1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released
by setting the RESET signal to high level, the main system clock starts oscillating. At this time, the oscillation
stabilization time (217/fX) is secured automatically.
After that, the CPU starts executing the instruction at the minimum speed of the main system clock (10.7 µs when
operated at 6.0 MHz).
(2) After the lapse of a sufficient time for the VDD voltage to increase to enable operation at maximum speed, the
processor clock control register (PCC), oscillation mode selection register (OSMS), and clock select registers
1 and 2 (IECL1 and IECL2) are rewritten and maximum-speed operation is carried out.
(3) When a decrease in the VDD voltage is detected by an interrupt request signal, the main system clock is
switched to the subsystem clock (which must be in an oscillation stable state).
(4) When restoration of the VDD voltage reset is detected by an interrupt request signal, bit 7 (MCC) of PCC is
set to 0 and oscillation of the main system clock is started. After the time required for oscillation to stabilize
has elapsed, the PCC, OSMS, IECL1, and IECL2 registers are rewritten and maximum-speed operation is
resumed.
Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait
until the oscillation stabilization has been secured by the program before switching back to the
main system clock.
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16-BIT TIMER/EVENT COUNTER 0
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 0
6.1 Outline of Internal Timer of µPD78098B Subseries
This chapter explains the 16-bit timer/event counter. Before that, the timers incorporated in the µPD78098B
Subseries, and their related functions are outlined below.
(1) 16-bit timer/event counter 0 (TM0)
16-bit timer/event counter 0 can be used as an interval timer, for PWM output and pulse width measurement
(infrared remote control receive function), as an external event counter, and for square-wave output of any
frequency or one-shot pulse output.
(2) 8-bit timer/event counters 1 and 2 (TM1 and TM2)
8-bit timer/event counters 1 and 2 can be used as an interval timer and an external event counter and to output
square waves of any selected frequency. Two 8-bit timer/event counters can be used as one 16-bit timer/
event counter (See CHAPTER 7 8-BIT TIMER/EVENT COUNTER).
(3) Watch timer (TM3)
This timer can be used to simultaneously set a flag every 0.5 sec. and generate interrupt requests at preset
time intervals (See CHAPTER 8 WATCH TIMER).
(4) Watchdog timer (WDTM)
WDTM can perform a watchdog timer function or generate non-maskable interrupt requests, maskable
interrupt requests and RESET at preset time intervals (See CHAPTER 9 WATCHDOG TIMER).
(5) Clock output controller
This circuit supplies the divided main system clock and the subsystem clock to other devices (See CHAPTER
10 CLOCK OUTPUT CONTROLLER).
(6) Buzzer output controller
This circuit outputs the buzzer frequency obtained by dividing the main system clock (See CHAPTER 11
BUZZER OUTPUT CONTROLLER).
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16-BIT TIMER/EVENT COUNTER 0
6.2 Functions of 16-Bit Timer/Event Counter 0
16-bit timer/event counter 0 has the following functions.
• Interval timer
• PWM output
• Pulse width measurement
• External event counter
• Square-wave output
• One-shot pulse output
PWM output and pulse width measurement can be used at the same time.
(1) Interval timer
16-bit timer/event counter 0 generates interrupt requests at a preset time interval.
Table 6-1. Interval Time of 16-Bit Timer/Event Counter 0
Minimum Interval Time
Maximum Interval Time
Resolution
2 × TI00 input cycle
216 × TI00 input cycle
TI00 input edge cycle
1/fXX
(250 ns)
215 × 1/fXX
(8.19 ms)
1/2fXX
(125 ns)
2 × 1/fXX
(500 ns)
216 × 1/fXX
(16.4 ms)
1/fXX
(250 ns)
22 × 1/fXX
(1.0 µs)
217 × 1/fXX
(32.8 ms)
2 × 1/fXX
(500 ns)
23 × 1/fXX
(2.0 µs)
218 × 1/fXX
(65.5 ms)
22 × 1/fXX
(1.0 µs)
2 × watch timer output cycle
216 × watch timer output cycle
Watch timer output edge cycle
Remarks 1. fXX: Main system clock frequency
2. Values in parentheses apply to operation with fXX = 4.0 MHz
(2) PWM output
16-bit timer/event counter 0 can generate 14-bit resolution PWM output.
(3) Pulse width measurement
16-bit timer/event counter 0 can measure the pulse width of an externally input signal.
(4) External event counter
16-bit timer/event counter 0 can measure the number of pulses of an externally input signal.
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16-BIT TIMER/EVENT COUNTER 0
(5) Square-wave output
16-bit timer/event counter 0 can output a square wave of any selected frequency.
Table 6-2. Square-Wave Output Range of 16-Bit Timer/Event Counter 0
Minimum Pulse Width
2 × TI00 input cycle
Maximum Pulse Width
216
× TI00 input cycle
Resolution
TI00 input edge cycle
1/fXX
(250 ns)
215
× 1/fXX
(8.19 ms)
1/2fXX
(125 ns)
2 × 1/fXX
(500 ns)
216 × 1/fXX
(16.4 ms)
1/fXX
(250 ns)
22 × 1/fXX
(1.0 µs)
217 × 1/fXX
(32.8 ms)
2 × 1/fXX
(500 ns)
23 × 1/fXX
(2.0 µs)
218 × 1/fXX
(65.5 ms)
22 × 1/fXX
(1.0 µs)
2 × watch timer output cycle
216 × watch timer output cycle
Watch timer output edge cycle
Remarks 1. fXX: Main system clock frequency
2. Values in parentheses apply to operation with fXX = 4.0 MHz
(6) One-shot pulse output
16-bit timer/event counter 0 can output a one-shot pulse for which any output pulse width can be set.
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16-BIT TIMER/EVENT COUNTER 0
6.3 Configuration of 16-Bit Timer/Event Counter 0
16-bit timer/event counter 0 consists of the following hardware.
Table 6-3. Configuration of 16-Bit Timer/Event Counter 0
Item
Note
Configuration
Timer counter
16 bits × 1 (TM0)
Register
Capture/compare register: 16 bits × 2 (CR00, CR01)
Timer outputs
1 (TO0)
Control registers
Timer clock select register 0 (TCL0)
16-bit timer mode control register 0 (TMC0)
Capture/compare control register 0 (CRC0)
16-bit timer output control register 0 (TOC0)
Port mode register 3 (PM3)
External interrupt mode register 0 (INTM0)
Sampling clock select register (SCS) Note
Refer to Figure 18-1 Basic Configuration of Interrupt Function.
Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 0
Internal Bus
Capture/Compare
Control Register 0
CRC02 CRC01 CRC00
Selector
INTP1
TI01/
P01/INTP1
16-Bit Capture/Compare
Control Register 00 (CR00)
PWM Pulse
Output
Controller
Match
TI00/P00/
INTP0
Selector
INTTM3
2f XX
f XX
f XX/2
f XX/22
INTTM00
Note 2
TMC01 to TMC03
16-Bit Timer Counter 0 (TM0)
Clear
Clear Circuit
Note 1
TMC01 to TMC03
Match
3
TCL06 TCL05 TCL04
TO0/P30
2
INTTM01
3
Timer Clock
Selection
Register 0
16-Bit Timer/Event
Counter 0 Output
Controller
16-Bit Capture/Compare
Control Register 01 (CR01)
INTP0
TMC03 TMC02 TMC01 OVF0
OSPT OSPE TOC04 LVS0 LVR0 TOC01TOE0
16-Bit Timer Mode
Control Register 0 (TMC0)
CRC02
16-Bit Timer Output
Control Register 0 (TOC0)
Internal Bus
Notes 1. Edge detector
2. The configuration of the 16-bit timer/event counter 0 output controller is shown in Figure 6-2.
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16-BIT TIMER/EVENT COUNTER 0
Figure 6-2. Block Diagram of 16-Bit Timer/Event Counter 0 Output Controller
PWM Pulse
Output
Controller
Level
Inversion
CRC00
INTTM00
Edge
Detector
TI00/P00/
INTP0
INV
S
One-Shot Pulse
Output Controller
Selector
Selector
CRC02
INTTM01
Q
TO0/P30
R
3
2
ES11 ES10
External Interrupt
Mode Register 0
(INTM0)
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0
16-Bit Timer Output
Control Register 0
(TOC0)
TMC03 TMC02 TMC01
16-Bit Timer Mode
Control Register 0
(TMC0)
Internal Bus
Remark
142
The circuitry enclosed by the broken lines is the output controller.
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P30 Output
Latch
PM30
Port Mode
Register 3
CHAPTER 6
16-BIT TIMER/EVENT COUNTER 0
(1) Capture/compare register 00 (CR00)
CR00 is a 16-bit register with the functions of both a capture register and a compare register. Whether it is
used as a capture register or as a compare register is set by bit 0 (CRC00) of capture/compare control register
0 (CRC0).
When CR00 is used as a compare register, the value set in CR00 is constantly compared with the 16-bit timer
register (TM0) count value, and an interrupt request (INTTM00) is generated if they match. It can also be
used as the register that holds the interval time when TM0 is set to interval timer operation, and as the register
that sets the pulse width when TM0 is set to PWM output operation.
When CR00 is used as a capture register, it is possible to select the valid edge of the INTP0/TI00 pin or the
INTP1/TI01 pin as the capture trigger. The INTP0/TI00 or INTP1/TI01 valid edge is set by means of external
interrupt mode register 0 (INTM0).
If CR00 is specified as a capture register and the capture trigger is specified to be the valid edge of the INTP0/
TI00 pin, the situation is as shown in the following table.
Table 6-4. INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge
ES11
ES10
INTP0/TI00 Pin Valid Edge
CR00 Capture Trigger Valid Edge
0
0
Falling edge
Rising edge
0
1
Rising edge
Falling edge
1
0
1
1
Setting prohibited
Both rising and falling edges
No capture operation
CR00 is set with a 16-bit memory manipulation instruction.
After RESET input, the value of CR00 is undefined.
Cautions 1. Set the data of PWM (14 bits) to the higher 14 bits of CR00. At this time, clear the lower
2 bits to 00.
2. In the clear & start mode entered on a match between TM0 and CR00, set a value other
than 0000H to CR00. When the event counter function is used, therefore, one pulse
cannot be counted.
3. If the new value of CR00 is less than the value of 16-bit timer counter 0 (TM0), TM0
continues counting, overflows, and then starts counting again from 0. If the new value
of CR00 is less than the old value, the timer must be restarted after changing the value
of CR00.
(2) Capture/compare register 01 (CR01)
CR01 is a 16-bit register with the functions of both a capture register and a compare register. Whether it is
used as a capture register or a compare register is set by bit 2 (CRC02) of capture/compare control register
0.
When CR01 is used as a compare register, the value set in CR01 is constantly compared with the 16-bit timer
counter 0 (TM0) count value, and an interrupt request (INTTM01) is generated if they match.
When CR01 is used as a capture register, it is possible to select the valid edge of the INTP0/TI00 pin as the
capture trigger. The INTP0/TI00 valid edge is set by means of external interrupt mode register 0 (INTM0).
CR01 is set with a 16-bit memory manipulation instruction.
After RESET input, the value of CR01 is undefined.
Caution If the valid edge of the TI00/P00 pin is input while CR01 is being read, CR01 does not perform
the capture operation and retains the current data. However, the interrupt request flag (PIF0)
is set.
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(3) 16-bit timer counter 0 (TM0)
TM0 is a 16-bit register that counts the count pulses.
TM0 is read with a 16-bit memory manipulation instruction. When TM0 is read, capture/compare register 01
(CR01) should first be set as a capture register.
RESET input clears TM0 to 0000H.
Caution The value of TM0 is read via CR01, so the previously set value of CR01 will be lost.
6.4 Registers Controlling 16-Bit Timer/Event Counter 0
The following seven registers are used to control 16-bit timer/event counter 0.
• Timer clock select register 0 (TCL0)
• 16-bit timer mode control register 0 (TMC0)
• Capture/compare control register 0 (CRC0)
• 16-bit timer output control register 0 (TOC0)
• Port mode register 3 (PM3)
• External interrupt mode register 0 (INTM0)
• Sampling clock select register (SCS)
(1) Timer clock select register 0 (TCL0)
This register is used to set the count clock of 16-bit timer counter 0 (TM0).
TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TCL0 to 00H.
Remark
TCL0 has the function of setting the PCL output clock in addition to that of setting the count clock
of 16-bit timer counter 0 (TM0).
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Figure 6-3. Format of Timer Clock Select Register 0
Symbol
7
6
5
4
3
2
1
0
TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00
0
Output disabled
1
Output enabled
0
0
0
TI00 (Valid edge specifiable)
0
0
1
2fXX Note
0
1
0
fXX
0
1
1
fXX/2 (2.0 MHz)
1
0
0
fXX/2 (1.0 MHz)
1
1
1
Watch timer output (INTTM3)
Other than above
00H
R/W
2
Setting prohibited
PCL Output Clock Selection
0
0
0
0
fXT
(32.768 kHz)
0
1
0
1
fXX
(4.0 MHz)
0
1
1
0
fXX/2
(2.0 MHz)
0
1
1
1
fXX/2
0
0
0
2
(1.0 MHz)
3
(500 kHz)
4
(250 kHz)
5
(125 kHz)
6
(62.5 kHz)
7
(31.3 kHz)
fXX/2
1
0
0
1
fXX/2
1
0
1
0
fXX/2
0
1
1
0
Other than above
Note
FF40H
(4.0 MHz)
TCL03 TCL02 TCL01 TCL00
1
R/W
16-Bit Timer Counter 0 (TM0) Count Clock Selection
TCL06 TCL05 TCL04
1
After Reset
PCL Output Control
CLOE
1
Address
1
0
fXX/2
fXX/2
Setting prohibited
Setting prohibited when fXX > 2.5 MHz
Cautions 1. The TI00/INTP0 pin valid edge is set by external interrupt mode register 0 (INTM0), and
the sampling clock frequency is selected by the sampling clock select register (SCS).
2. When enabling PCL output, set TCL00 to TCL03, then set CLOE to 1 with a 1-bit memory
manipulation instruction.
3. To read the count value when TI00 has been specified as the TM0 count clock, the value
should be read from TM0, not from 16-bit capture/compare register 01 (CR01).
4. When rewriting TCL0 to other data, first stop the timer operation.
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Remarks 1. fXX:
16-BIT TIMER/EVENT COUNTER 0
Main system clock frequency
2. fXT:
Subsystem clock oscillation frequency
3. TI00:
16-bit timer/event counter 0 input pin
4. TM0:
16-bit timer counter 0
5. Figures in parentheses apply to operation with fXX = 4.0 MHz or fXT = 32.768 kHz.
(2) 16-bit timer mode control register 0 (TMC0)
This register sets the 16-bit timer operating mode, the 16-bit timer counter 0 (TM0) clear mode and output
timing, and detects an overflow.
TMC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC0 to 00H.
Caution 16-bit timer counter 0 (TM0) starts operation at the moment TMC01 to TMC03 are set to values
other than 0, 0, 0 (operation stop mode). Set TMC01 to TMC03 to 0, 0, 0 to stop the operation.
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Figure 6-4. Format of 16-Bit Timer Mode Control Register 0
Symbol
7
6
5
4
TMC0
0
0
0
0
3
2
1
Operating Mode/
Clear Mode Selection
TMC03 TMC02 TMC01
0
TMC03 TMC02 TMC01 OVF0
Address
After Reset
R/W
FF48H
00H
R/W
TO0 Output Timing Selection
Interrupt Generation
0
0
0
Operation stopped
(TM0 cleared to 0)
No change
Not Generated
0
0
1
PWM mode
(free running)
PWM pulse output
0
1
0
Free-running mode
Match between TM0 and
CR00 or match between
TM0 and CR01
Generated on match
between TM0 and CR00,
and match between TM0
and CR01
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Match between TM0 and
CR00, match between
TM0 and CR01 or TI00
valid edge
Clear & start on TI00
valid edge
Match between TM0 and
CR00 or match between
TM0 and CR01
Match between TM0 and
CR00, match between
TM0 and CR01 or TI00
valid edge
Clear & start on match
between TM0 and CR00
OVF0
Match between TM0 and
CR00 or match between
TM0 and CR01
Match between TM0 and
CR00, match between
TM0 and CR01 or TI00
valid edge
16-Bit Timer Counter 0 (TM0) Overflow Detection
0
Overflow not detected
1
Overflow detected
Cautions 1. Switch the clear mode and the T00 output timing after stopping the timer operation
(by setting TMC01 to TMC03 to 0, 0, 0).
2. Set the valid edge of the TI00/INTP0 pin using external interrupt mode register 0
(INTM0) and select the sampling clock frequency using the sampling clock select
register (SCS).
3. When using the PWM mode, set the PWM mode and then set data to CR00.
4. If clear & start mode entered on a match between TM0 and CR00 is selected, when the
set value of CR00 is FFFFH and the TM0 value changes from FFFFH to 0000H, the OVF0
flag is set to 1.
Remarks 1. TO0: 16-bit timer/event counter 0 output pin
2. TI00: 16-bit timer/event counter 0 input pin
3. TM0: 16-bit timer counter 0
4. CR00: Compare register 00
5. CR01: Compare register 01
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(3) Capture/compare control register 0 (CRC0)
This register controls the operation of the capture/compare registers (CR00, CR01).
CRC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CRC0 to 04H.
Figure 6-5. Format of Capture/Compare Control Register 0
Symbol
7
6
5
4
3
CRC0
0
0
0
0
0
2
1
0
CRC02 CRC01 CRC00
CRC02
Address
After Reset
R/W
FF4CH
04H
R/W
CR01 Operating Mode Selection
0
Operates as compare register
1
Operates as capture register
CRC01
CR00 Capture Trigger Selection
0
Captures on valid edge of TI01
1
Captures on valid edge of TI00
CRC00
CR00 Operating Mode Selection
0
Operates as compare register
1
Operates as capture register
Cautions 1. Timer operation must be stopped before setting CRC0.
2. When clear & start mode entered on a match between TM0 and CR00 is selected by
16-bit timer mode control register 0, CR00 should not be specified as a capture register.
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(4) 16-bit timer output control register 0 (TOC0)
This register controls the operation of the 16-bit timer/event counter 0 output controller. It sets/resets the RS type flip-flop (LV0), sets the active level in PWM mode, enables/disables inversion in modes other than PWM
mode, enables/disables 16-bit timer/event counter 0 timer output, enables/disables the one-shot pulse output
operation, and sets the output trigger for a one-shop pulse by software.
TOC0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TOC0 to 00H.
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Figure 6-6. Format of 16-Bit Timer Output Control Register 0
Symbol
7
TOC0
0
6
5
4
3
2
1
0
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0
OSPT
Address
After Reset
R/W
FF4EH
00H
R/W
Control of One-Shot Pulse Output Trigger by Software
0
One-shot pulse trigger not used
1
One-shot pulse trigger used
OSPE
One-Shot Pulse Output Control
0
Continuous pulse output
1
One-shot pulse output
TOC04
Timer Output F/F Control by Match of CR01 and TM0
0
Inversion operation disabled
1
Inversion operation enabled
LVS0 LVR0
16-Bit Timer/Event Counter 0 Timer Output F/F Status Setting
0
0
No change
0
1
Timer output F/F reset (to 0)
1
0
Timer output F/F set (to 1)
1
1
Setting prohibited
TOC04
In PWM Mode
In Other Modes
Active Level Selection
Timer Output F/F Control by Match of CR00 and TM0
0
Active high
Inversion operation disabled
1
Active low
Inversion operation enabled
TOE0
16-Bit Timer/Event Counter Output Control
0
Output disabled (port mode)
1
Output enabled
Cautions 1. Timer operation must be stopped before setting TOC0 (except OSPT).
2. If LVS0 and LVR0 are read after data is set, they will be 0.
3. OSPT is cleared automatically after data setting, and will therefore be 0 if read.
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(5) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P30/TO0 pin for timer output, set PM30 and the output latch of P30 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 6-7. Format of Port Mode Register 3
Symbol
7
6
5
4
3
2
1
0
PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n
Address
After Reset
R/W
FF23H
FFH
R/W
P3n Pin I/O Mode Selection (n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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(6) External interrupt mode register 0 (INTM0)
This register is used to set the valid edges of INTP0 to INTP2.
INTM0 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM0 value to 00H.
Figure 6-8. Format of External Interrupt Mode Register 0
Symbol
7
6
5
4
3
INTM0 ES31 ES30 ES21 ES20 ES11
2
1
0
Address
After Reset
R/W
ES10
0
0
FFECH
00H
R/W
ES31 ES30
INTP2 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES21 ES20
INTP1 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES11 ES10
INTP0 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
Caution When using the INTP0/TI00/P00 pin as timer input (TI00), be sure to set the valid edge after
setting bits 1 to 3 (TMC01 to TMC03) of 16-bit timer mode control register 0 (TMC0) to 0, 0,
0 to stop the operation of 16-bit timer counter 0.
Note that when using the INTP0/TI00/P00 pin as external interrupt input (INTP0), the valid
edge can be set during operation of 16-bit timer counter 0.
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(7) Sampling clock select register (SCS)
This register sets the clock to undergo clock sampling of the valid edges input to INTP0. When remote
controlled reception is carried out using INTP0, digital noise is removed by the sampling clock.
SCS is set with an 8-bit memory manipulation instruction.
RESET input clears SCS to 00H.
Figure 6-9. Format of Sampling Clock Select Register
Symbol
7
6
5
4
3
2
SCS
0
0
0
0
0
0
1
0
SCS1 SCS0
Address
After Reset
R/W
FF47H
00H
R/W
INTP0 Sampling Clock Selection
SCS1 SCS0
0
0
fXX/2
N
0
1
fXX/2
7
(31.3 kHz)
(125.0 kHz)
(62.5 kHz)
1
0
fXX/2
5
1
1
fXX/2
6
Caution fXX/2N is the clock supplied to the CPU, and fXX/25, fXX/26, and fXX/27 are the clocks supplied
to peripheral hardware. The fXX/2N clock is stopped in HALT mode.
Remarks 1. N:
Value set to bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC)
(N = 0 to 4)
2. fXX:
Main system clock frequency
3. Figures in parentheses apply to operation with fXX = 4.0 MHz.
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6.5 Operations of 16-Bit Timer/Event Counter 0
6.5.1 Interval timer operations
Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in
Figure 6-10 allows operation as an interval timer. Interrupt requests are generated repeatedly using the count value
set in 16-bit capture/compare register 00 (CR00) beforehand as the interval.
When the count value of 16-bit timer counter 0 (TM0) matches the value set to CR00, counting continues with the
TM0 value cleared to 0 and the interrupt request signal (INTTM00) is generated.
The count clock of 16-bit timer/event counter 0 can be selected with bits 4 to 6 (TCL04 to TCL06) of timer clock
select register 0 (TCL0).
For the operation when the value of the compare register is changed during timer/counter operation, refer to 6.6
Cautions for 16-Bit Timer/Event Counter 0 (3).
Figure 6-10. Control Register Settings for Interval Timer Operation
(a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
1
0/1
0
Clear & start on match of TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0/1
0/1
0
CR00 is set as compare register
Remark 0/1:
Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See
the description of the respective control registers for details.
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Figure 6-11. Interval Timer Configuration Diagram
16-Bit Capture/Compare Register 00 (CR00)
INTTM00
2fXX
fXX
fXX/2
2
fXX/2
TI00/P00/INTP0
Selector
INTTM3
OVF0
16-Bit Timer Counter 0 (TM0)
Clear Circuit
Figure 6-12. Interval Timer Operation Timing
t
Count Clock
TM0 Count Value
0000
0001
Count Start
CR00
N
N
0000 0001
Clear
N
0000 0001
N
Clear
N
N
N
INTTM00
Interrupt Request
Acknowledgement
Interrupt Request
Acknowledgement
TO0
Interval Time
Remark
Interval Time
Interval Time
Interval time = (N + 1) × t
N = 0001H to FFFFH
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Table 6-5. Interval Time of 16-Bit Timer/Event Counter 0
TCL06
TCL05
TCL04
Minimum Interval Time
Maximum Interval Time
Resolution
0
0
0
2 × TI00 input cycle
216 × TI00 input cycle
TI00 input edge cycle
0
0
1
1/fXX
(250 ns)
215 × 1/fXX
(8.19 ms)
1/2fXX
(125 ns)
0
1
0
2 × 1/fXX
(500 ns)
216 × 1/fXX
(16.4 ms)
1/fXX
(250 ns)
0
1
1
22 × 1/fXX
(1.0 µs)
217 × 1/fXX
(32.8 ms)
2 × 1/fXX
(500 ns)
1
0
0
23 × 1/fXX
(2.0 µs)
218 × 1/fXX
(65.5 ms)
22 × 1/fXX
(1.0 µs)
1
1
1
2 × watch timer output cycle
216 × watch timer output cycle
Watch timer output edge cycle
Other than above
Setting prohibited
Remarks 1. fXX: Main system clock frequency
2. TCL04 to TCL06: Bits 4 to 6 of timer clock select register 0 (TCL0)
3. Figures in parentheses apply to operation with fXX = 4.0 MHz
6.5.2 PWM output operations
Setting 16-bit timer mode control register 0 (TMC0), capture/compare control register 0 (CRC0), and 16-bit timer
output control register 0 (TOC0) as shown in Figure 6-13 allows operation as PWM output. Pulses with the duty ratio
determined by the value set in 16-bit capture/compare register 00 (CR00) beforehand are output from the TO0/P30
pin.
Set the active level width of the PWM pulse to the higher 14 bits of CR00. Select the active level with bit 1 (TOC01)
of 16-bit timer output control register 0 (TOC0).
This PWM pulse has a 14-bit resolution. The pulse can be converted to an analog voltage by integrating it with
an external low-pass filter (LPF). The PWM pulse is formed by a combination of the basic cycle determined by 28/
Φ and the sub-cycle determined by 214/Φ so that the time constant of the external LPF can be shortened. The count
clock Φ can be selected with bits 4 to 6 (TCL04 to TCL06) of timer clock select register 0 (TCL0).
PWM output enable/disable can be selected with bit 0 (TOE0) of TOC0.
Cautions 1. The PWM operation mode should be selected before setting CR00.
2. Be sure to write 0 to bits 0 and 1 of CR00.
3. Do not select the PWM operation mode for external clock input from the TI00/P00/INTP0 pin.
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Figure 6-13. Control Register Settings for PWM Output Operation
(a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
0
0
1
0
PWM mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0/1
0/1
0
CR00 set as compare register
(c) 16-bit timer output control register 0 (TOC0)
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0
TOC0
0
×
×
×
×
×
0/1
1
TO0 output enabled
Specifies active level
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with PWM output.
See the description of the respective control registers for details.
×:
Don't care
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By integrating 14-bit resolution PWM pulses with an external low-pass filter, the pulses can be converted to an
analog voltage and used for electronic tuning and D/A converter applications, etc.
The analog output voltage (VAN) used for D/A conversion with the configuration shown in Figure 6-14 is as follows.
VAN = VREF ×
Capture/compare register 00 (CR00) value
216
VREF: External switching circuit reference voltage
Figure 6-14. Example of D/A Converter Configuration with PWM Output
µ PD78098B
VREF
PWM
Signal
TO0/P30
Switching Circuit
Analog Output (VAN)
Low-Pass Filter
Figure 6-15 shows an example in which PWM output is converted to an analog voltage and used in a voltage
synthesizer type TV tuner.
Figure 6-15. TV Tuner Application Circuit Example
+110 V
µ PD78098B
22 kΩ
47 kΩ
47 kΩ
47 kΩ
100 pF
TO0/P30
8.2 kΩ
2SC
2352
0.22 µ F
0.22 µ F
µ PC574J
0.22 µ F
Electronic
Tuner
8.2 kΩ
VSS
158
GND
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6.5.3 PPG output operations
Setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in
Figure 6-16 allows operation as PPG (Programmable Pulse Generator) output.
In the PPG output operation, square waves are output from the TO0/P30 pin with the pulse width and the cycle
that correspond to the count values set beforehand in 16-bit capture/compare register 01 (CR01) and in 16-bit capture/
compare register 00 (CR00), respectively.
Figure 6-16. Control Register Settings for PPG Output Operation
(a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
1
0
0
Clear & start on match of TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0
x
0
CR00 set as compare register
CR01 set as compare register
(c) 16-bit timer output control register 0 (TOC0)
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0
TOC0
0
0
0
1
0/1
0/1
1
1
TO0 output enabled
Inversion of output on match of TM0 and CR00
Specified TO0 output F/F initial value
Inversion of output on match of TM0 and CR01
One-shot pulse output disabled
Caution Values in the following range should be set in CR00 and CR01.
0000H ≤ CR01 < CR00 ≤ FFFFH
Remark
×: Don't care
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6.5.4 Pulse width measurement operations
It is possible to measure the pulse width of the signals input to the TI00/P00 pin and TI01/P01 pin using
16-bit timer counter 0 (TM0).
There are two measurement methods: measuring with TM0 used in free-running mode, and measuring by
restarting the timer in synchronization with the edge of the signal input to the TI00/P00 pin.
(1) Pulse width measurement with free-running counter and one capture register
When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-17),
and the edge specified by external interrupt mode register 0 (INTM0) is input to the TI00/P00 pin, the value
of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTP0)
is set.
Any of three edge specifications can be selected —rising, falling, or both edges— by means of bits 2 and 3
(ES10 and ES11) of INTM0.
For valid edge detection, sampling is performed at the interval selected by the sampling clock select register
(SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise
with a short pulse width.
Figure 6-17. Control Register Settings for Pulse Width Measurement Operation by
Free-Running Counter and One Capture Register
(a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
1
0/1
0
CR00 set as compare register
CR01 set as capture register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 6-18. Configuration Diagram of Pulse Width Measurement Operation by Free-Running Counter
INTTM3
Selector
2fXX
fXX
fXX/2
16-Bit Timer Counter 0 (TM0)
OVF0
2
fXX/2
16-Bit Capture/Compare
Register 01 (CR01)
TI00/P00/INTP00
INTP0
Internal Bus
Figure 6-19. Timing of Pulse Width Measurement Operation by Free-Running Counter
and One Capture Register (with Both Edges Specified)
t
Count Clock
TM0 Count
Value
TI00 Pin
Input
Value Loaded
to CR01
0000H 0001H
D0
D0 + 1
D0
D1
D1 + 1
FFFFH 0000H
D1
D2
D3
D2
D3
INTP0
OVF0
(D1 – D0) × t
(10000H – D1 + D2) × t
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(2) Measurement of two pulse widths with free-running counter
When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-20),
it is possible to simultaneously measure the pulse widths of the two signals input to the TI00/P00 and TI01/
P01 pins.
When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is
input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an
external interrupt request signal (INTP0) is set.
Also, when the edge specified by bits 4 and 5 (ES20 and ES21) of INTM0 is input to the TI01/P01 pin, the
value of TM0 is taken into 16-bit capture/compare register 00 (CR00) and an external interrupt request signal
(INTP1) is set.
Any of three edge specifications can be selected —rising, falling, or both edges— as the valid edges for the
TI00/P00 pin and the TI01/P01 pin by means of bits 2 and 3 (ES10 and ES11) and bits 4 and 5 (ES20 and
ES21) of INTM0, respectively.
For TI00/P00 pin valid edge detection, sampling is performed at the interval selected by the sampling clock
select register (SCS), and a capture operation is only performed when a valid level is detected twice, thus
eliminating noise with a short pulse width.
Figure 6-20. Control Register Settings for Two Pulse Width Measurement Operation by Free-Running Counter
(a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
1
0
1
CR00 set as capture register
Captured in CR00 on valid edge of TI01/P01 pin
CR01 set as capture register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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The following figure illustrates the operation of the capture register when the capture trigger is input.
Figure 6-21. CR01 Capture Operation with Rising Edge Specified
Count Clock
TM0
n–3
n–2
n–1
n
n+1
TI00
Rising Edge
Detection
CR01
n
INTP0
Figure 6-22. Timing of Pulse Width Measurement Operation by Free-Running Counter
(with Both Edges Specified)
t
Count Clock
TM0 Count
Value
0000H 0001H
D0
D0 + 1
D1 D1 + 1
FFFFH 0000H
D2
D2 + 1 D2 + 2
D3
TI00 Pin
Input
Value Loaded
to CR01
D0
D1
D2
INTP0
TI01 Pin Input
Value Loaded
to CR00
D1
D2 + 1
INTP1
OVF0
(D1 – D0) × t
(10000H – D1 + D2) × t
(D3 – D2) × t
(10000H – D1 + (D2 + 1) × t
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(3) Pulse width measurement with free-running counter and two capture registers
When 16-bit timer counter 0 (TM0) is operated in free-running mode (see register settings in Figure 6-22),
it is possible to measure the pulse width of the signal input to the TI00/P00 pin.
When the edge specified by bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0) is
input to the TI00/P00 pin, the value of TM0 is taken into 16-bit capture/compare register 01 (CR01) and an
external interrupt request signal (INTP0) is set.
Also, when the inverse edge to that of the capture operation to CR01 is input, the value of TM0 is taken into
16-bit capture/compare register 00 (CR00).
Either of two edge specifications can be selected —rising or falling— as the valid edges for the TI00/P00 pin
by means of bits 2 and 3 (ES10 and ES11) of INTM0.
For TI00/P00 pin valid edge detection, sampling is performed at the interval selected by the sampling clock
select register (SCS), and a capture operation is only performed when a valid level is detected twice, thus
eliminating noise with a short pulse width.
Caution If the valid edge of TI00/P00 is specified to be both the rising and falling edge, 16-bit capture/
compare register 00 (CR00) cannot perform the capture operation.
Figure 6-23. Control Register Settings for Pulse Width Measurement Operation by
Free-Running Counter and Two Capture Registers
(a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
1
1
1
CR00 set as capture register
Captured in CR00 on invalid edge of
TI00/P00 pin
CR01 set as capture register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 6-24. Timing of Pulse Width Measurement Operation by Free-Running
Counter and Two Capture Registers (with Rising Edge Specified)
t
Count Clock
TMn Count
Value
0000H 0001H
D0
D0 + 1
D1
D1 + 1
FFFFH 0000H
D2
D2 + 1
D3
TI00 Pin Input
Value Loaded
to CR01
D2
D0
Value Loaded
to CR00
D1
D3
INTP0
OVF0
(D1 – D0) × t
(10000H – D1 + D2) × t
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(4) Pulse width measurement by restart
When input of a valid edge to the TI00/P00 pin is detected, the count value of 16-bit timer counter 0 (TM0)
is taken into 16-bit capture/compare register 01 (CR01), and then the pulse width of the signal input to the
TI00/P00 pin is measured by clearing TM0 and restarting the count (see register settings in Figure 6-24).
The edge specification can be selected from two types, rising and falling edges, by means of bits 2 and 3 (ES10
and ES11) of external interrupt mode register 0 (INTM0).
In valid edge detection, sampling is performed at the interval selected by the sampling clock select register
(SCS), and a capture operation is only performed when a valid level is detected twice, thus eliminating noise
with a short pulse width.
Caution If the valid edge of TI00/P00 is specified to be both the rising and falling edge, 16-bit capture/
compare register 00 (CR00) cannot perform the capture operation.
Figure 6-25. Control Register Settings for Pulse Width Measurement Operation by Restart
(a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
0
0/1
0
Clear & start with valid edge of TI00/P00 pin
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
1
1
1
CR00 set as capture register
Captured in CR00 on invalid
edge of TI00/P00 pin
CR01 set as capture register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
Figure 6-26. Timing of Pulse Width Measurement Operation by
Restart (with Rising Edge Specified)
t
Count Clock
TM0 Count
Value
0000H
0001H
D0
0000H 0001H
D1
D2
0000H
TI00 Pin Input
Value Loaded to
CR01
D2
D0
Value Loaded to
CR00
D1
INTP0
(D1 + 1) × t
(D2 + 1) × t
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6.5.5 External event counter operation
The external event counter counts the number of external clock pulses input to the TI00/P00 pin using 16-bit timer
counter 0 (TM0).
TM0 is incremented each time the valid edge specified by external interrupt mode register 0 (INTM0) is input.
When the TM0 count value matches the 16-bit capture/compare register 00 (CR00) value, TM0 is cleared to 0 and
the interrupt request signal (INTTM00) is generated.
Set a value other than 0000H to CR00 (a 1-pulse count operation cannot be performed).
The rising edge, falling edge, or both edges can be selected with bits 2 and 3 (ES10 and ES11) of INTM0.
In valid edge detection, sampling is performed at the interval selected by the sampling clock select register (SCS),
and a capture operation is only performed when a valid level is detected twice, thus eliminating noise with a short
pulse width.
Figure 6-27. Control Register Settings in External Event Counter Mode
(a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
1
0/1
0
Clear & start on match of TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0/1
0/1
0
CR00 set as compare register
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event
counter. See the description of the respective control registers for details.
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Figure 6-28. Configuration of External Event Counter
16-Bit Capture/Compare
Register 00 (CR00)
INTTM00
Clear
OVF0
16-Bit Timer Counter 0 (TM0)
TI00 Valid Edge
INTP0
16-Bit Capture/Compare
Register 01 (CR01)
Internal Bus
Figure 6-29. External Event Counter Operation Timing (with Rising Edge Specified)
TI00 Pin Input
TM0 Count Value
CR00
0000
0001 0002 0003
0004
0005
N–1
N
0000 0001 0002 0003
N
INTTM0
Caution When reading the external event counter count value, TM0 should be read.
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6.5.6 Square-wave output operation
16-bit timer/event counter 0 outputs a square wave of any selected frequency at intervals of the count value preset
to 16-bit capture/compare register 00 (CR00).
The TO0/P30 pin output status is reversed at intervals of the count value preset to CR00 by setting bit 0 (TOE0)
and bit 1 (TOC01) of 16-bit timer output control register 0 (TOC0) to 1. This enables a square wave of any selected
frequency to be output.
Figure 6-30. Control Register Settings in Square-Wave Output Mode
(a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
1
0/1
0
Clear & start on match of TM0 and CR00
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0/1
0/1
0
CR00 set as compare register
(c) 16-bit timer output control register 0 (TOC0)
OSPT OSPE TOC04 LVS0
TOC0
0
0
0
0
0/1
LVR0 TOC01 TOE0
0/1
1
1
TO0 output enabled
Inversion of output on match of TM0 and CR00
Specified TO0 output F/F initial value
No inversion of output on match of TM0 and CR01
One-shot pulse output disabled
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output.
See the description of the respective control registers for details.
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Figure 6-31. Square-Wave Output Operation Timing
Count Clock
TM0 Count Value
0000
0001
CR00
0002
N–1
N
0000
0001
0002
N–1
N
0000
N
INTTM0
TO0 Pin Output
Table 6-6. Square-Wave Output Range of 16-Bit Timer/Event Counter 0
Minimum Pulse Width
Maximum Pulse Width
Resolution
2 × TI00 input cycle
216 × TI00 input cycle
TI00 input edge cycle
1/fXX
215 × 1/fXX
1/2fXX
(250 ns)
(8.19 ms)
(125 ns)
2 × 1/fXX
(500 ns)
216 × 1/fXX
(16.4 ms)
1/fXX
(250 ns)
22 × 1/fXX
(1.0 µs)
217 × 1/fXX
(32.8 ms)
2 × 1/fXX
(500 ns)
23 × 1/fXX
(2.0 µs)
218 × 1/fXX
(65.5 ms)
22 × 1/fXX
(1.0 µs)
2 × watch timer output cycle
216 × watch timer output cycle
Watch timer output edge cycle
Remarks 1. fXX: Main system clock frequency
2. Values in parentheses apply to operation with fXX = 4.0 MHz
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6.5.7 One-shot pulse output operation
It is possible to output one-shot pulses synchronized with a software trigger or an external trigger (TI00/P00 pin
input).
(1) One-shot pulse output using software trigger
If 16-bit timer mode control register 0 (TMC0), capture/compare control register 0 (CRC0), and the 16-bit timer
output control register 0 (TOC0) are set as shown in Figure 6-31, and bit 6 (OSPT) of TOC0 is set to 1 by
software, a one-shot pulse is output from the TO0/P30 pin.
By setting OSPT to 1, 16-bit timer/event counter 0 is cleared and started, and output is activated by the count
value (N) set beforehand in 16-bit capture/compare register 01 (CR01). Thereafter, output is inactivated by
the count value (M) set beforehand in 16-bit capture/compare register 00 (CR00)Note.
TM0 continues to operate after a one-shot pulse is output. To stop TM0, 00H must be set to TMC0.
Note
This example assumes that N < M. When N > M, output is activated by CR00 and inactivated by
CR01.
Caution When outputting a one-shot pulse, do not set OSPT to 1. When outputting a one-shot pulse
again, execute after the current one-shot pulse output is complete.
Figure 6-32. Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger
(a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
0
1
0/1
0
Free-running mode
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0
0/1
0
CR00 set as compare register
CR01 set as compare register
(c) 16-bit timer output control register 0 (TOC0)
OSPT OSPE TOC04 LVS0
TOC0
0
0
1
1
0/1
LVR0 TOC01 TOE0
0/1
1
1
TO0 output enabled
Inversion of output on match of TM0 and CR00
Specified TO0 output F/F initial value
Inversion of output on match of TM0 and CR01
One-shot pulse output mode
Set 1 in case of output
Caution Do not set CR00 and CR01 to 0000H.
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output.
See the description of the respective control registers for details.
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Figure 6-33. Timing of One-Shot Pulse Output Operation Using Software Trigger
Set 04H to TMC0
(TM0 count start)
Count Clock
TM0 Count Value
0000
0001
N
N+1
0000
N–1
N
M–1
M
0000 0001 0002
CR01 Set Value
N
N
N
N
CR00 Set Value
M
M
M
M
OSPT
INTTM01
INTTM00
TO0 Pin Output
Caution 16-bit timer counter 0 starts operation at the moment TMC01 to TMC03 are set to values other
than 0, 0, 0 (operation stop mode).
Remark
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(2) One-shot pulse output using external trigger
If 16-bit timer mode control register 0 (TMC0), capture/compare control register 0 (CRC0), and 16-bit timer
output control register 0 (TOC0) are set as shown in Figure 6-33, a one-shot pulse is output from the TO0/
P30 pin with the TI00/P00 valid edge as an external trigger.
Any of three edge specifications can be selected —rising, falling, or both edges— as the valid edges for the
TI00/P00 pin by means of bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0).
When a valid edge is input to the TI00/P00 pin, 16-bit timer/event counter 0 is cleared and started, and output
is activated by the count values set beforehand in 16-bit capture/compare register 01 (CR01). Thereafter,
output is inactivated by the count value set beforehand in 16-bit capture/compare register 00 (CR00)Note.
Note
This example assumes that N < M. When N > M, output is activated by CR00 and inactivated by CR01.
Caution When outputting one-shot pulses, the external trigger is ignored if generated again.
Figure 6-34. Control Register Settings for One-Shot Pulse Output Operation Using External Trigger
(a) 16-bit timer mode control register 0 (TMC0)
TMC03 TMC02 TMC01 OVF0
TMC0
0
0
0
0
1
0
0
0
Clear & start with valid edge of TI00/P00 pin
(b) Capture/compare control register 0 (CRC0)
CRC02 CRC01 CRC00
CRC0
0
0
0
0
0
0
0/1
0
CR00 set as compare register
CR01 set as compare register
(c) 16-bit timer output control register 0 (TOC0)
OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0
TOC0
0
0
1
1
0/1
0/1
1
1
TO0 Output Enabled
Inversion of output on match of TM0 and CR00
Specified TO0 output F/F initial value
Inversion of output on match of TM0 and CR01
One-shot pulse output mode
Caution Do not set CR00 and CR01 to 0000H.
Remark
0/1: Setting 0 or 1 allows another function to be used simultaneously with one-shot pulse output.
See the description of the respective control registers for details.
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Figure 6-35. Timing of One-Shot Pulse Output Operation Using
External Trigger (With Rising Edge Specified)
Set 08H to TMC0
(TM0 count start)
Count Clock
TM0 Count Value
0000
0001
0000
N
N+1
N+2
M–2 M–1
M
M+1 M+2 M+3
CR01 Set Value
N
N
N
N
CR00 Set Value
M
M
M
M
TI00 Pin Input
INTTM01
INTTM00
TO0 Pin Output
Caution 16-bit timer counter 0 starts operation at the moment TMC01 to TMC03 are set to values other
than 0, 0, 0 (operation stop mode).
Remark
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6.6 Cautions for 16-Bit Timer/Event Counter 0
(1) Timer start errors
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 16-bit timer counter 0 (TM0) is started asynchronously to the count pulse.
Figure 6-36. 16-Bit Timer Counter 0 Start Timing
Count Pulse
TM0 Count Value
0000H
0001H
0002H
0003H
0004H
Timer Start
(2) 16-bit compare register setting (when in the clear & start mode entered on a match between TM0 and
CR00)
Set 16-bit capture/compare register 00 (CR00) to a value other than 0000H (when using the 16-bit capture/
compare register as event counter, a one-pulse count operation cannot be carried out).
(3) Operation after compare register is changed during timer count operation
If the value after 16-bit capture/compare register 00 (CR00) is changed is smaller than that of 16-bit timer
counter 0 (TM0), TM0 continues counting, overflows and then restarts counting from 0. Thus, if the value (M)
after CR00 changes is smaller than that (N) before the change, it is necessary to reset and restart the timer
after changing CR00.
Figure 6-37. Timing After Change of Compare Register During Timer Count Operation
Count Pulse
CR00
TM0 Count Value
Remark
M
N
X–1
X
FFFFH
0000H
0001H
0002H
N>X>M
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(4) Capture register data retention timings
If the valid edge of the TI00/P00 pin is input while 16-bit capture/compare register 01 (CR01) is being read,
CR01 holds the data without carrying out a capture operation. However, the interrupt request signal (INTP0)
is set upon detection of the valid edge.
Figure 6-38. Capture Register Data Retention Timing
Count Pulse
TM0 Count Value
N
N+1
N + 2
M
M+1
M+2
Edge Input
INTP0
Capture Read Signal
CR01 Interrupt Value
X
N+1
Capture operation
A capture operation is performed
but not guaranteed.
(5) Valid edge setting
Set the valid edge of the TI00/P00/INTP0 pin after setting bits 1 to 3 (TMC01 to TMC03) of 16-bit timer mode
control register 0 (TMC0) to 0, 0 and 0, respectively, and then stopping timer operation. The valid edge is
set with bits 2 and 3 (ES10 and ES11) of external interrupt mode register 0 (INTM0).
(6) Re-trigger of one-shot pulse
(a) One-shot pulse output using software
When outputting a one-shot pulse, do not set OSPT to 1. When outputting a one-shot pulse again, output
it after the current one-shot pulse is complete.
(b) One-shot pulse output using external trigger
When outputting one-shot pulses, the counter clears and starts and outputs a one-shot pulse again if the
external trigger is generated.
(c) One-shot pulse output function
When one-shot pulse output is used with a software trigger, do not change the level of the TI00 pin or
its alternate-function port pin.
Since the external trigger is valid even in this case, the timer clears and starts at the level of the TI00
pin or its alternate-function pin, and the pulse is output at an unintended timing.
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(7) Operation of OVF0 flag
(a) OVF0 flag setting
The OVF0 flag is set to 1 in the following case.
When one of clear & start mode on match between TM0 and CR00, clear & start mode on TI00 valid edge,
or free-running mode is selected.
↓
CR00 is set to FFFFH.
↓
TM0 is counted up from FFFFH to 0000H.
Figure 6-39. Operation Timing of OVF0 Flag
Count Pulse
CR00
FFFFH
TM0
FFFEH
FFFFH
0000H
0001H
OVF0
INTTM00
(b) OVF0 flag clear
Even if the OVF00 flag is cleared before the next count clock (before TM00 becomes 0001H) after the
occurrence of a TM00 overflow, the OVF0 flag is reset newly and clearing is disabled.
(8) Contending operations
<1> The contending operation between the read time of 16-bit timer capture/compare register (CR00/CR01)
and capture trigger input (CR00/CR01 used as capture/register)
Capture/trigger input is prior to the other. The data read from CR00/CR01 is not defined.
<2> The match timing of contending operation between the write period of 16-bit timer capture/compare register
(CR00/CR01) and 16-bit timer counter 0 (TM0) (CR00/CR01 used as a compare register)
The match discriminant is not performed normally. Do not write any data to CR00/CR01 near the match
timing.
(9) Timer operation
<1> Even if the 16-bit timer counter 0 (TM0) is read, the value is not captured by 16-bit timer capture/compare
register 01 (CR01).
<2> Regardless of the CPU’s operation mode, when the timer stops, the input signals to pins TI00/TI01 are
not acknowledged.
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<3> One-shot pulse output operates normally only the free-running mode. In the clear & start mode by TM0
and CR00 match, no overflow occurs, and therefore one-shot pulse output is not possible.
(10) Capture operation
<1> If TI00 is specified as the valid edge of the sampling clock, a capture operation by the capture register
specified as the trigger for TI00 is not possible.
<2> If both the rising and falling edges are selected as the valid edges of TI00, a capture is not performed.
<3> To ensure the reliability of the capture operation, the capture trigger requires a pulse two times longer than
the sampling clock selected by the sampling clock select register (SCS).
<4> The capture operation is performed at the fall of the sampling clock. An interrupt request input (INTTM00),
however, is generated at the rise of the next sampling clock.
(11) Compare operation
<1> When the 16-bit timer capture/compare register (CR00/CR01) is overwritten during timer operation, a match
interrupt may be generated or the clear operation may not be performed normally if that value is close to
or larger than the timer value.
<2> The capture operation may not be performed for CR00/CR01 set in compare mode even if a capture trigger
has been input.
(12) Edge detection
If the TI00 or TI01 pin is high level immediately after system reset and the rising edge or both the rising and
falling edges are specified as the valid edge for the TI00 or TI01 pin to enable 16-bit timer counter 0 (TM0)
operation, a rising edge is detected immediately after the operation is enabled. Be careful when pulling up
the TI00 or TI01 pin. However, the rising edge is not detected at restart after the operation has been stopped
once.
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CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 1 AND 2
7.1 Functions of 8-Bit Timer/Event Counters 1 and 2
Two modes are available for 8-bit timer/event counters 1 and 2. One is a mode for two-channel 8-bit timer/event
counters to be used separately (the 8-bit timer/event counter mode) and the other is a mode for the two-channel 8bit timer/event counters to be used as a 16-bit timer/event counter (the 16-bit timer/event counter mode).
7.1.1 8-bit timer/event counter mode
The 8-bit timer/event counters 1 and 2 have the following functions.
• Interval timer
• External event counter
• Square-wave output
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(1) 8-bit interval timer
Interrupt requests are generated at the preset time intervals.
Table 7-1. Interval Time of 8-Bit Timer/Event Counters 1 and 2
Minimum Interval Time
Maximum Interval Time
Resolution
2 × 1/fXX
(500 ns)
29
× 1/fXX
(128.0 µs)
2 × 1/fXX
(500 ns)
22 × 1/fXX
(1.0 µs)
210 × 1/fXX
(256.0 µs)
22 × 1/fXX
(1.0 µs)
23 × 1/fXX
(2.0 µs)
211 × 1/fXX
(512.0 µs)
23 × 1/fXX
(2.0 µs)
24 × 1/fXX
(4.0 µs)
212 × 1/fXX
(1.02 ms)
24 × 1/fXX
(4.0 µs)
25 × 1/fXX
(8.0 µs)
213 × 1/fXX
(2.05 ms)
25 × 1/fXX
(8.0 µs)
26 × 1/fXX
(16.0 µs)
214 × 1/fXX
(4.10 ms)
26 × 1/fXX
(16.0 µs)
27 × 1/fXX
(32.0 µs)
215 × 1/fXX
(8.19 ms)
27 × 1/fXX
(32.0 µs)
28 × 1/fXX
(64.0 µs)
216 × 1/fXX
(16.4 ms)
28 × 1/fXX
(64.0 µs)
29 × 1/fXX
(128.0 µs)
217 × 1/fXX
(32.8 ms)
29 × 1/fXX
(128.0 µs)
211 × 1/fXX
(512.0 µs)
219 × 1/fXX
(131.1 ms)
211 × 1/fXX
(512.0 µs)
Remarks 1. fXX: Main system clock frequency
2. Values in parentheses apply to operation with fXX = 4.0 MHz.
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(2) External event counter
The number of pulses of an externally input signal can be measured.
(3) Square-wave output
A square wave of any selected frequency can be output.
Table 7-2. Square-Wave Output Range of 8-Bit Timer/Event Counters 1 and 2
Minimum Pulse Width
Maximum Pulse Width
Resolution
2 × 1/fXX
(500 ns)
29 × 1/fXX
(128.0 µs)
2 × 1/fXX
(500 ns)
22 × 1/fXX
(1.0 µs)
210 × 1/fXX
(256.0 µs)
22 × 1/fXX
(1.0 µs)
23 × 1/fXX
(2.0 µs)
211 × 1/fXX
(512.0 µs)
23 × 1/fXX
(2.0 µs)
24 × 1/fXX
(4.0 µs)
212 × 1/fXX
24 × 1/fXX
(1.02 ms)
(4.0 µs)
25 × 1/fXX
(8.0 µs)
213 × 1/fXX
(2.05 ms)
25 × 1/fXX
(8.0 µs)
26 × 1/fXX
(16.0 µs)
214 × 1/fXX
(4.10 ms)
26 × 1/fXX
(16.0 µs)
27 × 1/fXX
(32.0 µs)
215 × 1/fXX
(8.19 ms)
27 × 1/fXX
(32.0 µs)
28 × 1/fXX
(64.0 µs)
216 × 1/fXX
(16.4 ms)
28 × 1/fXX
(64.0 µs)
29 × 1/fXX
(128.0 µs)
217 × 1/fXX
(32.8 ms)
29 × 1/fXX
(128.0 µs)
211 × 1/fXX
(512.0 µs)
219 × 1/fXX
(131.1 ms)
211 × 1/fXX
(512.0 µs)
Remarks 1. fXX: Main system clock frequency
2. Values in parentheses apply to operation with fXX = 4.0 MHz.
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7.1.2 16-bit timer/event counter mode
(1) 16-bit interval timer
Interrupt requests can be generated at the preset time intervals.
Table 7-3. Interval Time When 8-Bit Timer/Event Counters 1 and 2
Are Used as 16-Bit Timer/Event Counter
Minimum Interval Time
Maximum Interval Time
Resolution
2 × 1/fXX
(500 ns)
217 × 1/fXX
(32.8 ms)
2 × 1/fXX
(500 ns)
22 × 1/fXX
(1.0 µs)
218 × 1/fXX
(65.5 ms)
22 × 1/fXX
(1.0 µs)
23 × 1/fXX
(2.0 µs)
219 × 1/fXX
(131.1 ms)
23 × 1/fXX
(2.0 µs)
24 × 1/fXX
(4.0 µs)
220 × 1/fXX
24 × 1/fXX
(262.1 ms)
(4.0 µs)
25 × 1/fXX
(8.0 µs)
221 × 1/fXX
(524.3 ms)
25 × 1/fXX
(8.0 µs)
26 × 1/fXX
(16.0 µs)
222 × 1/fXX
(1.0 s)
26 × 1/fXX
(16.0 µs)
27 × 1/fXX
(32.0 µs)
223 × 1/fXX
(2.1 s)
27 × 1/fXX
(32.0 µs)
28 × 1/fXX
(64.0 µs)
224 × 1/fXX
(4.2 s)
28 × 1/fXX
(64.0 µs)
29 × 1/fXX
(128.0 µs)
225 × 1/fXX
(8.4 s)
29 × 1/fXX
(128.0 µs)
211 × 1/fXX
(512.0 µs)
227 × 1/fXX
(33.6 s)
211 × 1/fXX
(512.0 µs)
Remarks 1. fXX: Main system clock frequency
2. Values in parentheses apply to operation with fXX = 4.0 MHz.
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(2) External event counter
The number of pulses of an externally input signal can be measured.
(3) Square-wave output
A square wave of any selected frequency can be output.
Table 7-4. Square-Wave Output Ranges When 8-Bit Timer/Event
Counters 1 and 2 Are Used as 16-Bit Timer/Event Counter
Minimum Pulse Width
Maximum Pulse Width
Resolution
2 × 1/fXX
(500 ns)
217
× 1/fXX
(32.8 ms)
2 × 1/fXX
(500 ns)
22 × 1/fXX
(1.0 µs)
218 × 1/fXX
(65.5 ms)
22 × 1/fXX
(1.0 µs)
23 × 1/fXX
(2.0 µs)
219 × 1/fXX
(131.1 ms)
23 × 1/fXX
(2.0 µs)
24 × 1/fXX
(4.0 µs)
220 × 1/fXX
(262.1 ms)
24 × 1/fXX
(4.0 µs)
25 × 1/fXX
(8.0 µs)
221 × 1/fXX
(524.3 ms)
25 × 1/fXX
(8.0 µs)
26 × 1/fXX
(16.0 µs)
222 × 1/fXX
(1.0 s)
26 × 1/fXX
(16.0 µs)
27 × 1/fXX
(32.0 µs)
223 × 1/fXX
(2.1 s)
27 × 1/fXX
(32.0 µs)
28 × 1/fXX
(64.0 µs)
224 × 1/fXX
(4.2 s)
28 × 1/fXX
(64.0 µs)
29 × 1/fXX
(128.0 µs)
225 × 1/fXX
(8.4 s)
29 × 1/fXX
(128.0 µs)
211 × 1/fXX
(512.0 µs)
227 × 1/fXX
(33.6 s)
211 × 1/fXX
(512.0 µs)
Remarks 1. fXX: Main system clock frequency
2. Values in parentheses apply to operation with fXX = 4.0 MHz.
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7.2 Configuration of 8-Bit Timer/Event Counters 1 and 2
8-bit timer/event counters 1 and 2 consist of the following hardware.
Table 7-5. Configuration of 8-Bit Timer/Event Counters 1 and 2
Item
Configuration
Timer counter
8 bits × 2 (TM1, TM2)
Register
Compare register: 8 bits × 2 (CR10, CR20)
Timer outputs
2 (TO1, TO2)
Control registers
Timer clock select register 1 (TCL1)
8-bit timer mode control register 1 (TMC1)
8-bit timer output control register 1 (TOC1)
Port mode register 3 (PM3) Note
Note Refer to Figure 4-7 Block Diagram of P30 to P37.
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Figure 7-1. Block Diagram of 8-Bit Timer/Event Counters 1 and 2
Internal Bus
INTTM1
Selector
8-Bit Compare
Register (CR20)
8-Bit Compare
Register (CR10)
Match
11
f XX/2
8-Bit Timer
Counter 1 (TM1)
Note
TO2/P32
4
TI1/P33
Clear
Selector
9
f XX/2 to fXX/2
Selector
Match
8-Bit Timer/
Event Counter
Output
Controller 2
8-Bit Timer
Counter 2 (TM2)
4
INTTM2
Clear
11
f XX/2
Selector
Selector
9
f XX/2 to fXX/2
TI2/P34
Note
8-Bit Timer/
Event Counter
Output Controller
4
TO1/P31
4
TCL TCL TCL TCL TCL TCL TCL TCL
17 16 15 14 13 12 11 10
Timer Clock
Select Register 1
(TCL1)
TMC12 TCE2
TCE1
8-Bit Timer Mode
Control Register
(TMC1)
LVS2 LVR2 TOC TOE2 LVS1 LVR1 TOC TOE1
15
11
8-Bit Timer Output
Control Register (TOC1)
Internal Bus
Note
Refer to Figures 7-2 and 7-3 for details of 8-bit timer/event counter output controllers 1 and 2, respectively.
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Figure 7-2. Block Diagram of 8-Bit Timer/Event Counter Output Controller 1
Level F/F
(LV1)
LVR1
R
LVS1
S
Q
TOC11
TO1/P31
P31
Output Latch
INV
PM31
INTTM1
TOE1
Remark
The section in the broken lines is the output control circuit.
Figure 7-3. Block Diagram of 8-Bit Timer/Event Counter Output Controller 2
Level F/F
(LV2)
fSCK
LVR2
R
Q
LVS2
TOC15
TO2/P32
S
P32
Output Latch
INV
INTTM2
TOE2
Remarks 1. The section in the broken lines is the output controller.
2. fSCK: Serial clock frequency
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(1) Compare registers 10 and 20 (CR10, CR20)
These are 8-bit registers used to compare the value set to CR10 to the 8-bit timer counter 1 (TM1) count value,
and the value set to CR20 to the 8-bit timer counter 2 (TM2) count value, and, if they match, generate an
interrupt request (INTTM1 and INTTM2, respectively).
CR10 and CR20 are set with an 8-bit memory manipulation instruction. They cannot be set with a 16-bit
memory manipulation instruction. When the compare register is used as an 8-bit timer/event counter, a value
between 00H and FFH can be set. When the compare register is used as a 16-bit timer/event counter, a value
between 0000H and FFFFH values can be set.
RESET input makes CR10 and CR20 undefined.
Caution When using the compare register as 16-bit timer/event counter, be sure to set data after
stopping the timer operation.
(2) 8-bit timer counters 1 and 2 (TM1, TM2)
These are 8-bit registers used to count count pulses.
When TM1 and TM2 are used in the 8-bit timer × 2-channel mode, they are read with an 8-bit memory
manipulation instruction. When TM1 and TM2 are used in the 16-bit timer × 1-channel mode, the 16-bit timer
(TMS) is read with a 16-bit memory manipulation instruction.
RESET input clears TM1 and TM2 to 00H.
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7.3 Registers Controlling 8-Bit Timer/Event Counters 1 and 2
The following four registers are used to control 8-bit timer/event counters 1 and 2.
• Timer clock select register 1 (TCL1)
• 8-bit timer mode control register 1 (TMC1)
• 8-bit timer output control register 1 (TOC1)
• Port mode register 3 (PM3)
(1) Timer clock select register 1 (TCL1)
This register sets the count clock of 8-bit timer counters 1 and 2 (TM1, TM2).
TCL1 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL1 to 00H.
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Figure 7-4. Format of Timer Clock Select Register 1
Symbol
7
6
5
4
3
2
1
0
TCL1 TCL17 TCL16 TCL15 TCL14 TCL13 TCL12 TCL11 TCL10
TCL17 TCL16 TCL15 TCL14
0
0
0
TI2 falling edge
0
0
0
1
TI2 rising edge
0
1
1
0
fXX/2
(1.0 MHz)
3
(500 kHz)
4
(250 kHz)
5
(125 kHz)
6
(62.5 kHz)
7
(31.3 kHz)
8
(15.6 kHz)
9
(7.8 kHz)
11
(2.0 kHz)
1
1
1
fXX/2
1
0
0
0
fXX/2
1
0
0
1
1
0
fXX/2
fXX/2
1
0
1
1
fXX/2
1
1
0
0
fXX/2
1
1
1
1
1
1
0
1
1
1
0
1
Other than above
fXX/2
fXX/2
fXX/2
FF41H
00H
R/W
Setting prohibited
8-Bit Timer Counter 1 Count Clock Selection
TCL13 TCL12 TCL11 TCL10
0
0
0
0
TI1 falling edge
0
0
0
1
TI1 rising edge
0
1
1
0
fXX/2 (2.0 MHz)
0
1
1
1
fXX/2 (1.0 MHz)
1
0
0
0
fXX/2 (500 kHz)
1
0
0
1
fXX/2 (250 kHz)
1
0
1
0
fXX/2 (125 kHz)
1
0
1
1
fXX/2 (62.5 kHz)
1
1
0
0
fXX/2 (31.3 kHz)
1
1
0
1
fXX/2 (15.6 kHz)
1
1
1
0
fXX/2 (7.8 kHz)
1
1
1
1
fXX/2 (2.0 kHz)
Other than above
R/W
(2.0 MHz)
2
0
0
After Reset
8-Bit Timer Counter 2 Count Clock Selection
0
1
Address
2
3
4
5
6
7
8
9
11
Setting prohibited
Caution When rewriting TCL1 to other data, stop the timer operation beforehand.
Remarks 1.
2.
3.
4.
fXX: Main system clock frequency
TI1: 8-bit timer event/counter 1 input pin
TI2: 8-bit timer event/counter 2 input pin
Figures in parentheses apply to operation with fXX = 4.0 MHz
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(2) 8-bit timer mode control register 1 (TMC1)
This register enables/stops operation of 8-bit timer counters 1 and 2 (TM1, TM2) and sets the operating mode.
TMC1 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TMC1 to 00H.
Figure 7-5. Format of 8-Bit Timer Mode Control Register 1
Symbol
7
6
5
4
3
TMC1
0
0
0
0
0
2
1
0
TMC12 TCE2 TCE1
TMC12
Address
After Reset
R/W
FF49H
00H
R/W
Operating Mode Selection
0
8-bit timer counter × 2-channel mode (TM1, TM2)
1
16-bit timer counter × 1-channel mode (TMS)
TCE2
8-Bit Timer Counter 2 Operation Control
0
Operation stopped (TM2 is cleared to 0)
1
Operation enabled
TCE1
8-Bit Timer Counter 1 Operation Control
0
Operation stopped (TM1 is cleared to 0)
1
Operation enabled
Cautions 1. Switch the operating mode after stopping the timer operation.
2. When used as 16-bit timer/event counter, TCE1 should be used for operation enable/stop.
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(3) 8-bit timer output control register 1 (TOC1)
This register controls operation of 8-bit timer/event counter output controllers 1 and 2.
TOC1 sets/resets the R-S flip-flops (LV1 and LV2) and enables/disables inversion and 8-bit timer output of
8-bit timer registers 1 and 2.
TOC1 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TOC1 to 00H.
Figure 7-6. Format of 8-Bit Timer Output Control Register 1
Symbol
7
6
5
4
3
2
1
0
TOC1 LVS2 LVR2 TOC15 TOE2 LVS1 LVR1 TOC11 TOE1
LVS2 LVR2
Address
After Reset
R/W
FF4FH
00H
R/W
8-Bit Timer/Event Counter 2 Timer Output F/F Status Set
0
0
Unchanged
0
1
Timer output F/F is reset (to 0)
1
0
Timer output F/F is set (to 1)
1
1
Setting prohibited
TOC15
8-Bit Timer/Event Counter 2 Timer Output F/F Control
0
Inverted operation disabled
1
Inverted operation enabled
TOE2
8-Bit Timer/Event Counter 2 Output Control
0
Output disabled (port mode)
1
Output enabled
LVS1 LVR1
8-Bit Timer/Event Counter 1 Timer Output F/F Status Set
0
0
Unchanged
0
1
Timer output F/F is reset (to 0)
1
0
Timer output F/F is set (to 1)
1
1
Setting prohibited
TOC11
8-Bit Timer/Event Counter 1 Timer Output F/F Control
0
Inverted operation disabled
1
Inverted operation enabled
TOE1
8-Bit Timer/Event Counter 1 Output Control
0
Output disabled (port mode)
1
Output enabled
Cautions 1. Be sure to set TOC1 after stopping timer operation.
2. LVS1, LVS2, LVR1, and LVR2 are 0 when read after data is set to them.
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(4) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P31/TO1 and P32/TO2 pins for timer output, set PM31, PM32, and the output latches of P31
and P32 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 7-7. Format of Port Mode Register 3
Symbol
PM3
7
6
5
4
3
PM3n
192
2
1
0
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
Address
After Reset
R/W
FF23H
FFH
R/W
P3n Pin I/O Mode Selection (n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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8-BIT TIMER/EVENT COUNTERS 1 AND 2
7.4 Operations of 8-Bit Timer/Event Counters 1 and 2
7.4.1 8-bit timer/event counter mode
(1) Interval timer operations
8-bit timer/event counters 1 and 2 operate as interval timers that generate interrupt requests repeatedly at
intervals of the count value preset to 8-bit compare registers 10 and 20 (CR10 and CR20).
When the count values of 8-bit timer counters 1 and 2 (TM1 and TM2) match the values set to CR10 and CR20,
counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signals (INTTM1 and
INTTM2) are generated.
The count clock of TM1 can be selected with bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1).
The count clock of TM2 can be selected with bits 4 to 7 (TCL14 to TCL17) of timer clock select register 1 (TCL1).
For the operation when the value of the compare register is changed during a timer count operation, refer to
7.5 Cautions for 8-Bit Timer/Event Counters 1 and 2 (3).
Figure 7-8. Interval Timer Operation Timing
t
Count Clock
TM1 Count Value
00
01
Count Start
CR10
N
N
00
01
Clear
N
00
01
N
Clear
N
N
N
INTTM1
Interrupt Request Acknowledge Interrupt Request Acknowledge
TO1
Interval Time
Remark
Interval Time
Interval Time
Interval time = (N + 1) × t: N = 00H to FFH
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Table 7-6. Interval Time of 8-Bit Timer/Event Counter 1
TCL13 TCL12 TCL11 TCL10
Minimum Interval Time
Maximum Interval Time
Resolution
0
0
0
0
TI1 input cycle
28 × TI1 input cycle
TI1 input edge cycle
0
0
0
1
TI1 input cycle
28 × TI1 input cycle
TI1 input edge cycle
0
1
1
0
2 × 1/fXX
(500 ns)
29 × 1/fXX
(128.0 µs)
2 × 1/fXX
(500 ns)
0
1
1
1
22 × 1/fXX
(1.0 µs)
210 × 1/fXX
(256.0 µs)
22 × 1/fXX
(1.0 µs)
1
0
0
0
23 × 1/fXX
(2.0 µs)
211 × 1/fXX
(512.0 µs)
23 × 1/fXX
(2.0 µs)
1
0
0
1
24 × 1/fXX
(4.0 µs)
212 × 1/fXX
(1.02 ms)
24 × 1/fXX
(4.0 µs)
1
0
1
0
25 × 1/fXX
(8.0 µs)
213 × 1/fXX
(2.05 ms)
25 × 1/fXX
(8.0 µs)
1
0
1
1
26 × 1/fXX
(16.0 µs)
214 × 1/fXX
(4.10 ms)
26 × 1/fXX
(16.0 µs)
1
1
0
0
27 × 1/fXX
(32.0 µs)
215 × 1/fXX
(8.19 ms)
27 × 1/fXX
(32.0 µs)
1
1
0
1
28 × 1/fXX
(64.0 µs)
216 × 1/fXX
(16.4 ms)
28 × 1/fXX
(64.0 µs)
1
1
1
0
29 × 1/fXX
(128.0 µs)
217 × 1/fXX
(32.8 ms)
29 × 1/fXX
(128.0 µs)
1
1
1
1
211 × 1/fXX
(512.0 µs)
219 × 1/fXX
(131.1 ms)
211 × 1/fXX
(512.0 µs)
Other than above
Setting prohibited
Remarks 1. fXX: Main system clock frequency
2. TCL10 to TCL13: Bits 0 to 3 of timer clock select register 1 (TCL1)
3. Values in parentheses apply to operation with fXX = 4.0 MHz.
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Table 7-7. Interval Time of 8-Bit Timer/Event Counter 2
TCL17 TCL16 TCL15 TCL14
Minimum Interval Time
Maximum Interval Time
Resolution
0
0
0
0
TI2 input cycle
28 × TI2 input cycle
TI2 input edge cycle
0
0
0
1
TI2 input cycle
28 × TI2 input cycle
TI2 input edge cycle
0
1
1
0
2 × 1/fXX
(500 ns)
29 × 1/fXX
(128.0 µs)
2 × 1/fXX
(500 ns)
0
1
1
1
22 × 1/fXX
(1.0 µs)
210 × 1/fXX
(256.0 µs)
22 × 1/fXX
(1.0 µs)
1
0
0
0
23 × 1/fXX
(2.0 µs)
211 × 1/fXX
(512.0 µs)
23 × 1/fXX
(2.0 µs)
1
0
0
1
24 × 1/fXX
(4.0 µs)
212 × 1/fXX
(1.02 ms)
24 × 1/fXX
(4.0 µs)
1
0
1
0
25 × 1/fXX
(8.0 µs)
213 × 1/fXX
(2.05 ms)
25 × 1/fXX
(8.0 µs)
1
0
1
1
26 × 1/fXX
(16.0 µs)
214 × 1/fXX
(4.10 ms)
26 × 1/fXX
(16.0 µs)
1
1
0
0
27 × 1/fXX
(32.0 µs)
215 × 1/fXX
(8.19 ms)
27 × 1/fXX
(32.0 µs)
1
1
0
1
28 × 1/fXX
(64.0 µs)
216 × 1/fXX
(16.4 ms)
28 × 1/fXX
(64.0 µs)
1
1
1
0
29 × 1/fXX
(128.0 µs)
217 × 1/fXX
(32.8 ms)
29 × 1/fXX
(128.0 µs)
1
1
1
1
211 × 1/fXX
(512.0 µs)
219 × 1/fXX
(131.1 ms)
211 × 1/fXX
(512.0 µs)
Other than above
Setting prohibited
Remarks 1. fXX: Main system clock frequency
2. TCL14 to TCL17: Bits 4 to 7 of timer clock select register 1 (TCL1)
3. Values in parentheses apply to operation with fXX = 4.0 MHz
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(2) External event counter operation
The external event counter counts the number of external clock pulses to be input to the TI1/P33 and TI2/
P34 pins using 8-bit timer counters 1 and 2 (TM1 and TM2).
TM1 and TM2 are incremented each time the valid edge specified by timer clock select register 1 (TCL1) is
input. Either the rising or falling edge can be selected.
When the TM1 and TM2 counted values match the values of 8-bit compare registers 10 and 20 (CR10 and
CR20), TM1 and TM2 are cleared to 0 and the interrupt request signals (INTTM1 and INTTM2) are generated.
Figure 7-9. External Event Counter Operation Timing (with Rising Edge Specified)
TI1 Pin Input
TM1 Count Value
00
01
CR10
02
03
04
05
N–1
N
INTTM1
Remark
196
N = 00H to FFH
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00
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02
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8-BIT TIMER/EVENT COUNTERS 1 AND 2
(3) Square-wave output operation
The 8-bit timer/event counters 1 and 2 output square waves of any selected frequency at intervals of the value
preset to 8-bit compare registers 10 and 20 (CR10 and CR20).
The TO1/P31 or TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 or CR20
by setting bit 0 (TOE1) or bit 4 (TOE2) of 8-bit timer output control register 1 (TOC1) to 1. This enables a
square wave of any selected frequency to be output.
Table 7-8. Square-Wave Output Range of 8-Bit Timer/Event Counters 1 and 2
Minimum Pulse Width
Maximum Pulse Width
Resolution
2 × 1/fXX
(500 ns)
29
× 1/fXX
(128.0 µs)
2 × 1/fXX
(500 ns)
22 × 1/fXX
(1.0 µs)
210 × 1/fXX
(256.0 µs)
22 × 1/fXX
(1.0 µs)
23 × 1/fXX
(2.0 µs)
211 × 1/fXX
(512.0 µs)
23 × 1/fXX
(2.0 µs)
24 × 1/fXX
(4.0 µs)
212 × 1/fXX
(1.02 ms)
24 × 1/fXX
(4.0 µs)
25 × 1/fXX
(8.0 µs)
213 × 1/fXX
(2.05 ms)
25 × 1/fXX
(8.0 µs)
26 × 1/fXX
(16.0 µs)
214 × 1/fXX
(4.10 ms)
26 × 1/fXX
(16.0 µs)
27 × 1/fXX
(32.0 µs)
215 × 1/fXX
(8.19 ms)
27 × 1/fXX
(32.0 µs)
28 × 1/fXX
(64.0 µs)
216 × 1/fXX
(16.4 ms)
28 × 1/fXX
(64.0 µs)
29 × 1/fXX
(128.0 µs)
217 × 1/fXX
(32.8 ms)
29 × 1/fXX
(128.0 µs)
211 × 1/fXX
(512.0 µs)
219 × 1/fXX
(131.1 ms)
211 × 1/fXX
(512.0 µs)
Remarks 1. fXX: Main system clock frequency
2. Values in parentheses apply to operation with fXX = 4.0 MHz.
Figure 7-10. Square-Wave Output Operation Timing
Count Clock
TM1 Count Value
00
01
02
N–1
N
00
01
02
N–1
N
00
Count start
CR10
N
N
TO1 Note
Note
The initial value of TO1 output can be set with bits 2 and 3 (LVR1 and LVS1) of 8-bit timer output control
register 1 (TOC1).
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8-BIT TIMER/EVENT COUNTERS 1 AND 2
7.4.2 16-bit timer/event counter mode
When bit 2 (TMC12) of 8-bit timer mode control register 1 (TMC1) is set to 1, the 16-bit timer/event counter mode
is set.
In this mode, the count clock is selected with bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1).
The overflow signal of 8-bit timer/event counter 1 (TM1) is used as the count clock of 8-bit timer/event counter 2 (TM2).
Count operation enable/disable in this mode is selected with bit 0 (TCE1) of TMC1.
(1) Interval timer operations
8-bit timer/event counters 1 and 2 operate as an interval timers that generates interrupt requests repeatedly
at intervals of the count value preset to the 2-channel 8-bit compare registers (CR10 and CR20). When setting
a count value, set the value of the higher 8 bits to CR20 and the value of the lower 8 bits to CR10. For the
count values (interval times) that can be set, refer to Table 7-9.
When the 8-bit timer counter 1 (TM1) and CR10 values match and the 8-bit timer counter 2 (TM2) and CR20
values match, counting continues with the TM1 and TM2 values cleared to 0 and the interrupt request signal
(INTTM2) is generated. For the operation timing of the interval timer, refer to Figure 7-11.
The count clock can be selected with bits 0 to 3 (TCL10 to TCL13) of timer clock select register 1 (TCL1).
The overflow signal of TM1 is used as the count clock of TM2.
Figure 7-11. Interval Timer Operation Timing
t
Count Clock
TMS (TM1, TM2) Count Value
0000
0001
N
Count Start
CR10, CR20
N
0000 0001
N
0000 0001
Clear
Clear
N
N
N
N
INTTM2
Interrupt Request Acknowledge Interrupt Request Acknowledge
TO2
Interval Time
Remark
Interval Time
Interval Time
Interval time = (N + 1) × t: N = 0000H to FFFFH
Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the
CR10 value, an interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event
counter output controller 1 is inverted. Thus, when using 8-bit timer/event counters 1 and
2 as a 16-bit interval timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1
acknowledgment.
When reading the 16-bit timer counter (TMS) count value, use a 16-bit memory manipulation
instruction.
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8-BIT TIMER/EVENT COUNTERS 1 AND 2
Table 7-9. Interval Times When 2-Channel 8-Bit Timer/Event Counters
Are Used as 16-Bit Timer/Event Counter
TCL13 TCL12 TCL11 TCL10
0
0
0
0
0
0
Minimum Interval Time
Maximum Interval Time
Resolution
TI1 input cycle
28
× TI1 input cycle
TI1 input edge cycle
1
TI1 input cycle
28
× TI1 input cycle
TI1 input edge cycle
0
0
1
1
0
2 × 1/fXX
(500 ns)
217
× 1/fXX
(32.8 ms)
2 × 1/fXX
(500 ns)
0
1
1
1
22 × 1/fXX
(1.0 µs)
218 × 1/fXX
(65.5 ms)
22 × 1/fXX
(1.0 µs)
1
0
0
0
23 × 1/fXX
(2.0 µs)
219 × 1/fXX
(131.1 ms)
23 × 1/fXX
(2.0 µs)
1
0
0
1
24 × 1/fXX
(4.0 µs)
220 × 1/fXX
(262.1 ms)
24 × 1/fXX
(4.0 µs)
1
0
1
0
25 × 1/fXX
(8.0 µs)
221 × 1/fXX
(524.3 ms)
25 × 1/fXX
(8.0 µs)
1
0
1
1
26 × 1/fXX
(16.0 µs)
222 × 1/fXX
(1.0 s)
26 × 1/fXX
(16.0 µs)
1
1
0
0
27 × 1/fXX
(32.0 µs)
223 × 1/fXX
(2.1 s)
27 × 1/fXX
(32.0 µs)
1
1
0
1
28 × 1/fXX
(64.0 µs)
224 × 1/fXX
(4.2 s)
28 × 1/fXX
(64.0 µs)
1
1
1
0
29 × 1/fXX
(128.0 µs)
225 × 1/fXX
(8.4 s)
29 × 1/fXX
(128.0 µs)
1
1
1
1
211 × 1/fXX
(512.0 µs)
227 × 1/fXX
(33.6 s)
211 × 1/fXX
(512.0 µs)
Other than above
Setting prohibited
Remarks 1. fXX: Main system clock frequency
2. TCL10 to TCL13: Bits 0 to 3 of timer clock select register 1 (TCL1)
3. Values in parentheses apply to operation with fXX = 4.0 MHz.
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8-BIT TIMER/EVENT COUNTERS 1 AND 2
(2) External event counter operations
The external event counter counts the number of external clock pulses to be input to the TI1/P33 pin using
2-channel 8-bit timer registers 1 and 2 (TM1 and TM2).
TM1 and TM2 are incremented each time the valid edge specified by timer clock select register 1 (TCL1) is
input. Either the rising or falling edge can be selected.
When the TM1 and TM2 count values match the values of 8-bit compare registers 10 and 20 (CR10 and CR20),
TM1 and TM2 are cleared to 0 and the interrupt request signal (INTTM2) is generated.
Figure 7-12. External Event Counter Operation Timing (with Rising Edge Specified)
TI1 Pin Input
TM1, TM2 Count Value
N–1
0000 0001 0002 0003 0004 0005
N
0000 0001 0002 0003
N
CR10, CR20
INTTM2
Caution Even if the 16-bit timer/event counter mode is used, when the TM1 count value matches the
CR10 value, an interrupt request (INTTM1) is generated and the F/F of 8-bit timer/event
counter output controller 1 is inverted. Thus, when using 8-bit timer/event counters 1 and
2 as a 16-bit interval timer, set the INTTM1 mask flag TMMK1 to 1 to disable INTTM1
acknowledgment.
When reading the 16-bit timer counter counter (TMS) count value, use a 16-bit memory
manipulation instruction.
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8-BIT TIMER/EVENT COUNTERS 1 AND 2
(3) Square-wave output operation
8-bit timer/event counters 1 and 2 output square waves of any selected frequency at intervals of the value
preset to 8-bit compare registers 10 and 20 (CR10 and CR20). To set a count value, set the value of the higher
8 bits to CR20, and the value of the lower 8 bits to CR10.
The TO2/P32 pin output status is reversed at intervals of the count value preset to CR10 and CR20 by setting
bit 4 (TOE2) of 8-bit timer output control register 1 (TOC1) to 1. This enables a square wave of any selected
frequency to be output.
Table 7-10. Square-Wave Output Range When 2-Channel 8-Bit Timer/Event Counters
Are Used as 16-Bit Timer/Event Counter
Minimum Pulse Width
Maximum Pulse Width
Resolution
2 × 1/fXX
(500 ns)
217
× 1/fXX
(32.8 ms)
2 × 1/fXX
(500 ns)
22 × 1/fXX
(1.0 µs)
218 × 1/fXX
(65.5 ms)
22 × 1/fXX
(1.0 µs)
23 × 1/fXX
(2.0 µs)
219 × 1/fXX
(131.1 ms)
23 × 1/fXX
(2.0 µs)
24 × 1/fXX
(4.0 µs)
220 × 1/fXX
(262.1 ms)
24 × 1/fXX
(4.0 µs)
25 × 1/fXX
(8.0 µs)
221 × 1/fXX
(524.3 ms)
25 × 1/fXX
(8.0 µs)
26 × 1/fXX
(16.0 µs)
222 × 1/fXX
(1.0 s)
26 × 1/fXX
(16.0 µs)
27 × 1/fXX
(32.0 µs)
223 × 1/fXX
(2.1 s)
27 × 1/fXX
(32.0 µs)
28 × 1/fXX
(64.0 µs)
224 × 1/fXX
(4.2 s)
28 × 1/fXX
(64.0 µs)
29 × 1/fXX
(128.0 µs)
225 × 1/fXX
(8.4 s)
29 × 1/fXX
(128.0 µs)
211 × 1/fXX
(512.0 µs)
227 × 1/fXX
(33.6 s)
211 × 1/fXX
(512.0 µs)
Remarks 1. fXX: Main system clock frequency
2. Values in parentheses apply to operation with fXX = 4.0 MHz.
Figure 7-13. Square-Wave Output Operation Timing
Count Clock
TM1
00H
TM2
00H
N N+1
01H
CR10
N
CR20
M
TO2
FFH 00H
FFH 00H
01H
02H
FFH 00H 01H
M–1 M
N 00H 01H
00H
Interval Time
Count Start
Level Reverse
Counter Clear
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8-BIT TIMER/EVENT COUNTERS 1 AND 2
7.5 Cautions for 8-Bit Timer/Event Counters 1 and 2
(1) Timer start errors
An error of up to one clock may occur in the time required for a match signal to be generated after timer start.
This is because 8-bit timer counters 1 and 2 (TM1 and TM2) are started asynchronously to the count pulse.
Figure 7-14. 8-Bit Timer Registers 1 and 2 Start Timing
Count Pulse
TM1, TM2 Count Value
00H
01H
02H
03H
04H
Timer Start
(2) Settings of 8-bit compare registers 10 and 20
8-bit compare registers 10 and 20 (CR10 and CR20) can be set to 00H.
Thus, when these 8-bit compare registers are used as event counters, a one-pulse count operation can be
carried out.
When the 8-bit compare registers are used as 16-bit timer/event counter, write data to CR10 and CR20 after
setting bit 0 (TCE1) of 8-bit timer mode control register 1 to 0 and stopping the timer operation.
Figure 7-15. Event Counter Operation Timing
TI1, TI2, Input
CR10, CR20
TM1, TM2 Count Value
00H
00H
00H
TO1, TO2
Interrupt Request Flag
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8-BIT TIMER/EVENT COUNTERS 1 AND 2
(3) Operation after compare register is changed during timer count operation
If the values after 8-bit compare registers 10 and 20 (CR10 and CR20) are changed are smaller than those
of 8-bit timer counters 1 and 2 (TM1 and TM2), TM1 and TM2 continue counting, overflow and then restart
counting from 0. Thus, if the value (M) after CR10 and CR20 change is smaller than value (N) before the
change, it is necessary to restart the timer after changing CR10 and CR20.
Figure 7-16. Timing After Change of Compare Register During Timer Count Operation
Count Pulse
CR10, CR20
N
TM1, TM2 Count Value
X–1
Remark
N>X>M
M
X
FFH
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01H
02H
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WATCH TIMER
CHAPTER 8 WATCH TIMER
8.1 Watch Timer Functions
The watch timer has the following functions.
• Watch timer
• Interval timer
The watch timer and the interval timer can be used simultaneously.
(1) Watch timer
When the 32.768 kHz subsystem clock is used, a flag (WTIF) is set at 0.5-second or 0.25-second intervals.
When the 4.19 MHz (standard: 4.194304 MHz) main system clock is used, a flag (WTIF) is set at 0.5-second
or 0.25-second intervals.
Caution 0.5-second intervals cannot be generated with the 6.0 MHz main system clock. Switch to
the 32.768 kHz subsystem clock to generate 0.5-second intervals.
(2) Interval timer
Interrupt requests (INTTM3) are generated at the preset time interval.
Table 8-1. Interval Timer Interval Time
Interval Time
When Operated at
fXX = 4.0 MHz
When Operated at
fXT = 32.768 kHz
24 × 1/fW
512 µs
488 µs
25
× 1/fW
1.02 ms
977 µs
26
× 1/fW
2.05 ms
1.95 ms
27
× 1/fW
4.10 ms
3.91 ms
28
× 1/fW
8.19 ms
7.81 ms
29
× 1/fW
16.4 ms
15.6 ms
Remarks 1. fXX: Main system clock frequency
2. fXT: Subsystem clock oscillation frequency
3. fW:
204
Watch timer clock frequency (fXX/27 or fXT)
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WATCH TIMER
8.2 Watch Timer Configuration
The watch timer consists of the following hardware.
Table 8-2. Watch Timer Configuration
Item
Configuration
Counter
5 bits × 1
Control registers
Timer clock select register 2 (TCL2)
Watch timer mode control register 2 (TMC2)
8.3 Registers Controlling Watch Timer
The following two registers are used to control the watch timer.
• Timer clock select register 2 (TCL2)
• Watch timer mode control register 2 (TMC2)
(1) Timer clock select register 2 (TCL2) (Refer to Figure 8-2.)
This register sets the watch timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Remark
Besides setting the watch timer count clock, TCL2 sets the watchdog timer count clock and buzzer
output frequency.
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Figure 8-1. Watch Timer Block Diagram
9-Bit Prescaler
fW fW fW
24 25 26
fW fW
27 28
5-Bit Counter
Clear
fW
29
fW
213
Selector
f XT
fW
fW
214
Selector
f XX /2
Clear
Selector
7
Selector
TMC21
INTTM3
To 16-Bit Timer/
Event Counter 0
3
TCL24
TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20
Watch Timer Mode
Control Register 2 (TMC 2)
Timer Clock
Select Register 2 (TCL2)
Internal Bus
206
INTWT
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WATCH TIMER
Figure 8-2. Format of Timer Clock Select Register 2
Symbol
7
5
6
4
TCL2 TCL27 TCL26 TCL25 TCL24
3
0
2
1
0
TCL22 TCL21 TCL20
Address
FF42H
After
Reset
00H
R/W
R/W
Buzzer Output Frequency Selection
(Refer to Figure 11-2 Format of Timer Clock Select Register 2)
TCL27 TCL26 TCL25
TCL24
Watch Timer Count Clock Selection
0
f XX /27
(31.3 kHz)
1
f XT
(32.768 kHz)
Watchdog Timer Count Clock Selection
(Refer to Figure 9-2 Format of Timer Clock Select Register 2)
TCL22 TCL21 TCL20
Cautions 1. Be sure to stop operation of the watch timer or buzzer to be changed before rewriting
TCL2 (operation stop is not necessary when rewriting the same data).
The operation is stopped by the following methods.
• Buzzer output: Input 0 to bit 7 of TCL2 (TCL27)
• Watch timer: Input 0 to bit 2 (TMC22) of watch timer mode control register 2 (TMC2)
2. Changing the count clock (rewriting TCL20 to TCL22) after watchdog timer operation
has started is prohibited.
Remarks 1. fXX:
Main system clock frequency
2. fXT:
Subsystem clock oscillation frequency
3. ×:
Don't care
4. Figures in parentheses apply to operation with fXX = 4.0 MHz or fXT = 32.768 kHz.
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(2) Watch timer mode control register 2 (TMC2)
This register sets the watch timer operating mode, watch flag set time and prescaler interval time and enables/
disables prescaler and 5-bit counter operations. TMC2 is set with a 1-bit or 8-bit memory manipulation
instruction.
RESET input clears TMC2 to 00H.
Figure 8-3. Format of Watch Timer Mode Control Register 2
Symbol
7
TMC2
0
6
5
4
3
2
1
0
TMC26 TMC25 TMC24 TMC23 TMC22 TMC21 TMC20
Address
FF4AH
After
Reset
00H
R/W
R/W
Prescaler Interval Time Selection
TMC26 TMC25 TMC24
f XT = 32.768 kHz Operation
0
0
0
24/f W (488 µ s)
0
0
1
25/f W (977 µ s)
0
1
0
26/f W (1.95 ms)
0
1
1
27/f W (3.91 ms)
1
0
0
28/f W (7.81 ms)
1
0
1
29/f W (15.6 ms)
Other than above
Setting prohibited
Watch Flag Set Time Selection
TMC23
f XT = 32.768 kHz Operation
0
214/f W (0.5 sec)
1
213/f W (0.25 sec)
TMC22
5-Bit Counter Operation Control
0
Clear after operation stop
1
Operation enabled
Prescaler Operation Control
TMC21
0
Clear after operation stop
1
Operation enabled
TMC20
Watch Operating Mode Selection
0
Normal operating mode (flag set at f W /214 )
1
Fast-forward operating mode (flag set at f W /25)
Caution When the watch timer is used, the prescaler should not be cleared frequently.
Remarks 1. fW:
208
Watch timer clock frequency (fXX/27 or fXT)
2. fXX:
Main system clock frequency
3. fXT:
Subsystem clock oscillation frequency
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WATCH TIMER
8.4 Watch Timer Operations
8.4.1 Watch timer operation
When the 32.768 kHz subsystem clock is used, the timer operates as a watch timer with a 0.5-second or 0.25second interval.
The watch timer sets the test input flag (WTIF) to 1 at a constant time interval. The standby state (STOP mode/
HALT mode) can be cleared by setting WTIF to 1.
When bit 2 (TMC22) of watch timer mode control register 2 (TMC2) is set to 0, the 5-bit counter is cleared and
the count operation stops.
When the watch timer is operating simultaneously with the interval timer, a zero-second start can be achieved by
setting TMC22 to 0 (maximum error: 32.8 ms when operated at fXX = 4.0 MHz).
8.4.2 Interval timer operation
The watch timer operates as interval timer that generates interrupt requests repeatedly at an interval of a preset
count value.
The interval time can be selected with bits 4 to 6 (TMC24 to TMC26) of watch timer mode control register 2.
Table 8-3. Interval Timer Interval Time
TMC26
TMC25
TMC24
Interval Time
When Operated at
fXX = 4.0 MHz
When Operated at
fXT = 32.768 kHz
0
0
0
24 × 1/fW
512 µs
488 µs
1
25
× 1/fW
1.02 ms
977 µs
0
26
× 1/fW
2.05 ms
1.95 ms
1
27
× 1/fW
4.10 ms
3.91 ms
0
28
× 1/fW
8.19 ms
7.81 ms
1
29
× 1/fW
16.4 ms
15.6 ms
0
0
0
1
1
0
1
1
0
0
Other than above
Remarks 1. fXX:
Setting prohibited
Main system clock frequency
2. fXT:
Subsystem clock oscillation frequency
3. fW:
Watch timer clock frequency (fXX/27 or fXT)
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Figure 8-4. Operation Timing of Watch Timer/Interval Timer
5-Bit Counter
0H
Overflow
Start
Overflow
Count Clock
fXX/27 or fXT
Watch Timer
Interrupt INTWT
Interval Timer
Interrupt INTTM3
Interrupt Time of Watch Timer
(214/fW or 213/fW sec.)
Interval Time
(T)
Interrupt Time of Watch Timer
(214/fW or 213/fW sec.)
T
n×T
Remark fxx:
n×T
Main system clock frequency
fXT:
Subsystem clock frequency
f W:
Watch timer clock frequency
n:
Number of interval timer operations
Caution If the 5-bit counter is enabled by watch timer mode control register 2 (TMC2) (by setting bit 2
(TMC22) of TMC2 to 1), the time from this setting to the occurrence of the first interrupt request
(INTTM3) is not exactly the value set by bit 3 (TMC23) of TMC2. This is because the 5-bit counter
is late by one output cycle of the 9-bit prescaler in starting counting. The second INTTM3 signal
and those that follow are generated at exactly the set time.
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CHAPTER 9
WATCHDOG TIMER
CHAPTER 9 WATCHDOG TIMER
9.1 Watchdog Timer Functions
The watchdog timer has the following functions.
• Watchdog timer
• Interval timer
Caution Select the watchdog timer mode or the interval timer mode using the watchdog timer mode
register (WDTM) (the watchdog timer and interval timer cannot be used at the same time).
(1) Watchdog timer mode
In this mode, an inadvertent program loop is detected. Upon detection of a program loop, a non-maskable
interrupt request or RESET can be generated.
Table 9-1. Watchdog Timer Program Loop Detection Time
Program Loop Detection Time
211 × 1/fXX (512 µs)
212 × 1/fXX (1.02 ms)
213 × 1/fXX (2.05 ms)
214 × 1/fXX (4.10 ms)
215 × 1/fXX (8.19 ms)
216 × 1/fXX (16.4 ms)
217 × 1/fXX (32.8 ms)
219 × 1/fXX (131.1 ms)
Remarks 1. fXX: Main system clock frequency
2. Figures in parentheses apply to operation with fXX = 4.0 MHz.
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(2) Interval timer mode
Interrupt requests are generated at the preset time intervals.
Table 9-2. Interval Time
Interval Time
211
× 1/fXX (512 µs)
212
× 1/fXX (1.02 ms)
213
× 1/fXX (2.05 ms)
214
× 1/fXX (4.10 ms)
215
× 1/fXX (8.19 ms)
216
× 1/fXX (16.4 ms)
217
× 1/fXX (32.8 ms)
219 × 1/fXX (131.1 ms)
Remarks 1. fXX: Main system clock frequency
2. Figures in parentheses apply to operation with fXX = 4.0 MHz.
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WATCHDOG TIMER
9.2 Watchdog Timer Configuration
The watchdog timer consists of the following hardware.
Table 9-3. Watchdog Timer Configuration
Item
Configuration
Control registers
Timer clock select register 2 (TCL2)
Watchdog timer mode control register (WDTM)
Figure 9-1. Watchdog Timer Block Diagram
Internal Bus
Prescaler
TMMK4
f XX f XX f XX f XX f XX f XX f XX
24 25 26 27 28 29 211
RUN
TMIF4
Selector
f XX /23
8-Bit Counter
Controller
INTWDT
Maskable
Interrupt
Request
RESET
INTWDT
Non-Maskable
Interrupt
Request
3
TCL22 TCL21 TCL20
RUN WDTM4 WDTM3
Timer Clock Select Register 2 (TCL 2)
Watchdog Timer Mode Register (WDTM)
Internal Bus
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WATCHDOG TIMER
9.3 Registers Controlling Watchdog Timer
The following two registers are used to control the watchdog timer.
• Timer clock select register 2 (TCL2)
• Watchdog timer mode register (WDTM)
(1) Timer clock select register 2 (TCL2)
This register sets the watchdog timer count clock.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Remark
Besides setting the watchdog timer count clock, TCL2 sets the watch timer count clock and buzzer
output frequency.
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Figure 9-2. Format of Timer Clock Select Register 2
Symbol
7
6
5
4
3
TCL2 TCL27 TCL26 TCL25 TCL24
0
2
TCL22 TCL21 TCL20
3
(500 kHz)
0
0
0
f XX /2
0
0
1
f XX /24
(250 kHz)
0
f XX /2
5
(125 kHz)
6
(62.5 kHz)
1
0
1
1
f XX /2
1
0
0
f XX /27
(31.3 kHz)
1
f XX /2
8
(15.6 kHz)
f XX /2
9
(7.8 kHz)
f XX /2
11
(2.0 kHz)
1
FF42H
After
Reset
00H
R/W
R/W
Watchdog Timer Count Clock Selection
TCL22 TCL21 TCL20
1
Address
Watch Timer Count Clock Selection
(Refer to Figure 8-2 Format of Timer Clock Select Register 2)
TCL24
1
0
Buzzer Output Frequency Selection
(Refer to Figure 11-2 Format of Timer Clock Select Register 2)
TCL27 TCL26 TCL25
0
1
0
1
1
0
1
Cautions 1. Be sure to stop operation of the watch timer or buzzer to be changed before rewriting
TCL2 (operation stop is not necessary when rewriting the same data).
The operation is stopped by the following methods.
• Buzzer output: Input 0 to bit 7 of TCL2 (TCL27)
• Watch timer: Input 0 to bit 2 (TMC22) of watch timer mode control register 2 (TMC2)
2. Changing the count clock (rewriting TCL20 to TCL22) after watchdog timer operation
has started is prohibited.
Remarks 1. fXX:
Main system clock frequency
2. fXT:
Subsystem clock oscillation frequency
3. ×:
Don't care
4. Figures in parentheses apply to operation with fXX = 4.0 MHz or fXT = 32.768 kHz.
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(2) Watchdog timer mode register (WDTM)
This register sets the watchdog timer operating mode and enables/disables counting.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears WDTM to 00H.
Figure 9-3. Format of Watchdog Timer Mode Register
Symbol
7
WDTM RUN
6
5
0
0
4
3
WDTM4 WDTM3
2
1
0
Address
0
0
0
FFF9H
After
Reset
00H
R/W
R/W
Watchdog Timer Operation Selection Note 1
RUN
0
Count stopped
1
Counter is cleared and counting starts.
WDTM4WDTM3
Watchdog Timer Operation Mode Selection Note 2
0
×
Interval timer mode (maskable interrupt occurs upon generation of an overflow) Note 3
1
0
Watchdog timer mode 1 (non-maskable interrupt occurs upon generation of an overflow)
1
0
Watchdog timer mode 2 (reset operation is activated upon generation of an overflow)
Notes 1. Once set to 1, RUN cannot be cleared to 0 by software.
Thus, once counting starts, it can only be stopped by RESET input.
2. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software.
3. The watchdog timer starts operating as an interval timer as soon as RUN has been set to 1.
Cautions 1. When 1 is set in RUN so that the watchdog timer is cleared, the actual overflow time is
up to 0.5% shorter than the time set by timer clock select register 2 (TCL2).
2. To use watchdog timer modes 1 and 2, make sure that the interrupt request flag (TMIF4)
is 0, and then set WDTM4 to 1.
If WDTM4 is set to 1 when TMIF4 is 1, a non-maskable interrupt request occurs, regardless
of the contents of WDTM3.
Remark
216
×: Don’t care
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WATCHDOG TIMER
9.4 Watchdog Timer Operations
9.4.1 Watchdog timer operation
When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated
to detect any inadvertent program loop.
The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to
2 (TCL20 to TCL22) of timer clock select register 2 (TCL2).
The watchdog timer is started by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN
to 1 within the set overrun detection time interval. The watchdog timer can be cleared and counting is started by setting
RUN to 1. If RUN is not set to 1 and the inadvertent program loop detection time has elapsed, a system reset or
non-maskable interrupt request is generated according to the value of WDTM bit 3 (WDTM3).
By setting RUN to 1, the watchdog timer can be cleared.
The watchdog timer continues operating in the HALT mode but stops in the STOP mode. Thus, set RUN to 1 before
the STOP mode is set to clear the watchdog timer and then execute the STOP instruction.
Cautions 1. The actual overrun detection time may be shorter than the set time by a maximum of
0.5%.
2. When the subsystem clock is selected for the CPU clock, the watchdog timer count operation
is stopped.
Table 9-4. Watchdog Timer Program Loop Detection Time
TCL22
TCL21
TCL20
Program Loop Detection Time
0
0
0
211 × 1/fXX (512 µs)
0
0
1
212 × 1/fXX (1.02 ms)
0
1
0
213 × 1/fXX (2.05 ms)
0
1
1
214 × 1/fXX (4.10 ms)
1
0
0
215 × 1/fXX (8.19 ms)
1
0
1
216 × 1/fXX (16.4 ms)
1
1
0
217 × 1/fXX (32.8 ms)
1
1
1
219 × 1/fXX (131.1 ms)
Remarks 1. fXX: Main system clock frequency
2. TCL20 to TCL22: Bits 0 to 2 of timer clock select register 2 (TCL2)
3. Figures in parentheses apply to operation with fXX = 4.0 MHz.
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9.4.2 Interval timer operation
The watchdog timer operates as an interval timer that generates interrupt requests repeatedly at an interval of the
preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0.
The count clock (interval time) can be selected by the bits 0 to 2 (TCL20 to TCL22) of timer clock select register
2 (TCL2). By setting the bit 7 (RUN) of WDTM to 1, the watchdog timer starts operating as an interval timer.
When the watchdog timer is operated as interval timer, the interrupt mask flag (TMMK4) and priority specify flag
(TMPR4) are validated and the maskable interrupt request (INTWDT) can be generated. Among maskable interrupt
requests, the INTWDT default has the highest priority.
The interval timer continues operating in the HALT mode but stops in STOP mode. Thus, set bit 7 (RUN) of WDTM
to 1 before the STOP mode is set to clear the interval timer and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval
timer mode is not set unless RESET is input.
2. The interval time just after being set by WDTM may be shorter than the set time by a maximum
of 0.5%.
3. When the subsystem clock is selected for the CPU clock, the watchdog timer count operation
is stopped.
Table 9-5. Interval Timer Interval Time
TCL22
0
0
0
0
1
1
TCL21
0
0
1
1
0
0
TCL20
Interval Time
0
211
× 1/fXX
(512 µs)
1
212
× 1/fXX
(1.02 ms)
0
213
× 1/fXX
(2.05 ms)
1
214
× 1/fXX
(4.10 ms)
0
215
× 1/fXX
(8.19 ms)
1
216
× 1/fXX
(16.4 ms)
× 1/fXX
(32.8 ms)
1
1
0
217
1
1
1
219 × 1/fXX
(131.1 ms)
Remarks 1. fXX: Main system clock frequency
2. TCL20 to TCL22: Bits 0 to 2 of timer clock select register 2 (TCL2)
3. Figures in parentheses apply to operation with fXX = 4.0 MHz.
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CHAPTER 10
CLOCK OUTPUT CONTROLLER
CHAPTER 10 CLOCK OUTPUT CONTROLLER
10.1 Functions of Clock Output Controller
The clock output controller is used for carrier output during remote controlled transmission and clock output for
supply to peripheral LSIs. The clocks selected by timer clock select register 0 (TCL0) is output from the PCL/P35
pin.
Follow the procedure below to output clock pulses.
(1) Select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (TCL00 to TCL03)
of TCL0.
(2) Set the P35 output latch to 0.
(3) Set bit 5 (PM35) of port mode register 3 (PM3) to 0 (set to output mode).
(4) Set bit 7 (CLOE) of timer clock select register 0 (TCL0) to 1.
Caution Clock output cannot be used when the P35 output latch is set to 1.
Remark
When clock output enable/disable is switched, the clock output controller does not output pulses with
narrow widths (see the portions marked with * in Figure 10-1).
Figure 10-1. Remote Controlled Output Application Example
CLOE
*
*
PCL/P35 Pin Output
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10.2 Configuration of Clock Output Controller
The clock output controller consists of the following hardware.
Table 10-1. Clock Output Controller Configuration
Item
Control register
Configuration
Timer clock select register 0 (TCL0)
Port mode register 3 (PM3)
Figure 10-2. Block Diagram of Clock Output Controller
f XX
f XX /2
f XX /23
f XX /24
f XX /25
Selector
f XX /22
Synchronizing
Circuit
PCL /P35
f XX /26
f XX /27
f XT
4
P35
Output Latch
CLOE TCL03 TCL02 TCL01 TCL00
Timer Clock Select Register 0
(TCL0)
Internal Bus
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PM35
Port Mode Register 3 (PM3)
CHAPTER 10
CLOCK OUTPUT CONTROLLER
10.3 Registers Controlling Clock Output Function
The following two registers are used to control the clock output function.
• Timer clock select register 0 (TCL0)
• Port mode register 3 (PM3)
(1) Timer clock select register 0 (TCL0)
This register sets the PCL output clock.
TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears TCL0 to 00H.
Remark
Besides setting the PCL output clock, TCL0 sets the 16-bit timer register count clock.
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Figure 10-3. Format of Timer Clock Select Register 0
7
Symbol
6
5
4
3
2
1
0
TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00
CLOE
FF40H
After
Reset
00H
R/W
R/W
PCL Output Control
0
Output disabled
1
Output enabled
16-Bit Timer Register Count Clock Selection
TCL06 TCL05 TCL04
0
0
0
TI00 (Valid edge specifiable)
0
0
1
2f XX Note
0
1
0
f XX
0
1
1
f XX /2
(4.0 MHz)
(2.0 MHz)
2
1
0
0
f XX /2
1
1
1
Watch timer output (INTTM3)
Other than above
(1.0 MHz)
Setting prohibited
TCL03 TCL02 TCL01 TCL00
PCL Output Clock Selection
0
0
0
0
f XT
(32.768 kHz)
0
1
0
1
f XX
(4.0 MHz)
0
1
1
0
f XX /2
(2.0 MHz)
2
0
1
1
1
f XX /2
1
0
0
0
f XX /23 (500 kHz)
1
0
0
1
f XX /24 (250 kHz)
1
0
1
0
f XX /25 (125 kHz)
1
0
1
1
f XX /26 (62.5 kHz)
1
1
0
0
f XX /27 (31.3 kHz)
Other than above
Note
Address
(1.0 MHz)
Setting prohibited
Setting prohibited when fXX > 2.5 MHz
Cautions 1. The TI00/P00/INTP0 pin valid edge is set by external interrupt mode register 0 (INTM0),
and the sampling clock frequency is selected by the sampling clock select register
(SCS).
2. When enabling PCL output, set TCL00 to TCL03, then set CLOE to 1 with a 1-bit memory
manipulation instruction.
3. To read the count value when TI00 has been specified as the TM0 count clock, the value
should be read from TM0, not from 16-bit capture/compare register 01 (CR01).
4. When rewriting TCL0 to other data, stop the clock operation beforehand.
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Remarks 1. fXX:
CLOCK OUTPUT CONTROLLER
Main system clock frequency
2. fXT:
Subsystem clock oscillation frequency
3. TI00:
16-bit timer/event counter input pin
4. TM0:
16-bit timer register
5. Figures in parentheses apply to operation with fXX = 4.0 MHz or fXT = 32.768 kHz.
(2) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P35/PCL pin for the clock output function, set PM35 and the output latch of P35 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 10-4. Format of Port Mode Register 3
Symbol
PM3
7
6
5
4
3
2
1
0
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n
Address
After
Reset
R/W
FF23H
FFH
R/W
P3n Pin Input/Output Mode Selection (n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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CHAPTER 11
BUZZER OUTPUT CONTROLLER
CHAPTER 11 BUZZER OUTPUT CONTROLLER
11.1 Functions of Buzzer Output Controller
The buzzer output controller outputs square waves with a frequency of 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz. The
buzzer frequency selected using timer clock select register 2 (TCL2) is output from the BUZ/P36 pin.
Follow the procedure below to output the buzzer frequency.
(1) Select the buzzer output frequency with bits 5 to 7 (TCL25 to TCL27) of TCL2.
(2) Set the P36 output latch to 0.
(3) Set bit 6 (PM36) of port mode register 3 (PM3) to 0 (set to output mode).
Caution Buzzer output cannot be used when the P36 output latch is set to 1.
11.2 Configuration of Buzzer Output Controller
The buzzer output controller consists of the following hardware.
Table 11-1. Buzzer Output Controller Configuration
Item
Configuration
Control registers
Timer clock select register 2 (TCL2)
Port mode register 3 (PM3)
Figure 11-1. Block Diagram of Buzzer Output Controller
Selector
f XX /29
f XX /210
f XX /211
BUZ/P36
3
TCL27 TCL26 TCL25
P36
Output Latch
Port Mode Register 3 (PM3)
Timer Clock Select Register 2 (TCL2)
Internal Bus
224
PM36
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BUZZER OUTPUT CONTROLLER
11.3 Registers Controlling Buzzer Output Function
The following two registers are used to control the buzzer output function.
• Timer clock select register 2 (TCL2)
• Port mode register 3 (PM3)
(1) Timer clock select register 2 (TCL2)
This register sets the buzzer output frequency.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input clears TCL2 to 00H.
Remark
Besides setting the buzzer output frequency, TCL2 sets the watch timer count clock and the
watchdog timer count clock.
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Figure 11-2. Format of Timer Clock Select Register 2
Symbol
7
6
5
4
TCL2 TCL27 TCL26 TCL25 TCL24
3
0
2
1
0
TCL22 TCL21 TCL20
TCL27 TCL26 TCL25
Address
FF42H
After
Reset
00H
R/W
R/W
Buzzer Output Frequency Selection
0
×
×
Buzzer output disable
1
0
0
f XX /29
1
0
1
f XX /210 (3.9 kHz)
1
1
0
f XX /211 (1.95 kHz)
1
1
1
Setting prohibited
(7.8 kHz)
Watch Timer Count Clock Selection
Refer to Figure 8-2 Format of Timer Clock Select Register 2
TCL24
TCL22 TCL21 TCL20
Watchdog Timer Count Clock Selection
Refer to Figure 9-2 Format of Timer Clock Select Register 2
Cautions 1. Be sure to stop operation of the watch timer or buzzer to be changed before rewriting
TCL2 (operation stop is not necessary when rewriting the same data).
The operation is stopped by the following methods.
• Buzzer output: Input 0 to bit 7 of TCL2 (TCL27)
• Watch timer: Input 0 to bit 2 (TMC22) of watch timer mode control register 2 (TMC2)
2. Changing the count clock (rewriting TCL20 to TCL22) after watchdog timer operation
has started is prohibited.
Remarks 1. fXX:
Main system clock frequency
2. fXT:
Subsystem clock oscillation frequency
3. ×:
Don't care
4. Figures in parentheses apply to operation with fXX = 4.0 MHz or fXT = 32.768 kHz.
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(2) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P36/BUZ pin for buzzer output function, set PM36 and the output latch of P36 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 11-3. Format of Port Mode Register 3
Symbol
PM3
7
6
5
4
3
2
1
0
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
PM3n
Address
After
Reset
R/W
FF23H
FFH
R/W
P3n Pin Input/Output Mode Selection (n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
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CHAPTER 12
A/D CONVERTER
CHAPTER 12 A/D CONVERTER
12.1 A/D Converter Functions
The A/D converter converts an analog input into a digital value and consists of 8 channels (ANI0 to ANI7) with
8-bit resolution.
The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D
conversion result register (ADCR).
A/D conversion can be started in the following two ways.
(1) Hardware start
Conversion is started by trigger input (INTP3).
(2) Software start
Conversion is started by setting the A/D converter mode register (ADM).
One channel of analog input is selected from ANI0 to ANI7 and A/D conversion is executed. In the case of a
hardware start, A/D conversion stops when an A/D conversion operation ends, and an interrupt request (INTAD) is
generated. In the case of a software start, the A/D conversion operation is repeated. Each time an A/D conversion
operation ends, an interrupt request (INTAD) is generated.
Caution Do not manipulate pins that have alternate functions as ports as follows during A/D conversion;
otherwise, the specification of the overall error during A/D conversion may not be satisfied.
<1> Rewriting the output latch of a pin when the pin is used as a port
<2> Changing the output level of a pin even when the pin is not used as a port
12.2 A/D Converter Configuration
The A/D converter consists of the following hardware.
Table 12-1. A/D Converter Configuration
Item
Configuration
Analog input
8 channels (ANI0 to ANI7)
Control registers
A/D converter mode register (ADM)
A/D converter input select register (ADIS)
External interrupt mode register 1 (INTM1)
A/D current cut select register (IEAD)
Registers
Successive approximation register (SAR)
A/D conversion result register (ADCR)
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A/D CONVERTER
Figure 12-1. A/D Converter Block Diagram
Internal Bus
Internal Bus
A/D Current Cut
Select Register (IEAD)
A/ D Converter Input Select Register (ADIS)
Series Resistor String
IEAD0
ADIS3 ADIS2 ADIS1 ADIS0
AVDD
Note 2
Sample & Hold Circuit
AVSS
Voltage
Comparator
Tap Selector
Note 1
Selector
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
Selector
4
Connection
Control
AVREF0
Successive
Approximation
Register (SAR)
AVSS
3
ADM1 to ADM3
Edge
Detector
INTP3/P03
Controller
INTAD
INTP3
ES40, ES41 Note 3
3
Trigger Enable
CS TRG FR1 FR0 ADM3 ADM2 ADM1 HSC
A/ D Conversion
Result Register
(ADCR)
A/D Converter Mode Register (ADM)
Internal Bus
Notes 1. Selector to select the number of channels to be used for analog input.
2. Selector to select the channel for A/D conversion.
3. Bits 0 and 1 of external interrupt mode register 1 (INTM1)
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A/D CONVERTER
(1) Successive approximation register (SAR)
This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from
the series resistor string and holds the result from the most significant bit (MSB).
When up to the least significant bit (LSB) is held (end of A/D conversion), the SAR contents are transferred
to the A/D conversion result register.
(2) A/D conversion result register (ADCR)
This register holds the A/D conversion result. Each time A/D conversion ends, the conversion result is loaded
from the successive approximation register.
ADCR is read with an 8-bit memory manipulation instruction.
RESET input makes ADCR undefined.
(3) Sample & hold circuit
The sample & hold circuit samples each analog input signal sequentially applied from the input circuit and
transmits it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/
D conversion.
(4) Voltage comparator
The voltage comparator compares the analog input to the series resistor string output voltage.
(5) Series resistor string
The series resistor string is connected between AVREF0 and AVSS, and generates a voltage to be compared
to the analog input.
(6) ANI0 to ANI7 pins
These are 8-channel analog input pins used to input the analog signals to undergo A/D conversion to the A/
D converter.
Pins other than those selected as analog input by the A/D converter input select register (ADIS) can be used
as I/O ports.
Cautions 1. Use the ANI0 to ANI7 input voltages within the specified range. If a voltage higher than
AVREF0 or lower than AVSS is applied (even if within the absolute maximum ratings), the
converted value of the corresponding channel becomes undefined and may adversely
affect the converted values of other channels.
2. The analog input pins (ANI0 to ANI7) also function as I/O port (port 1) pins. When A/D
conversion is performed with any of pins ANI0 to ANI7 selected, be sure not to execute
an instruction that inputs data to port 1 while conversion is in progress, as this may
reduce the conversion resolution.
Also, if digital pulses are applied to a pin adjacent to the pin undergoing A/D conversion,
the expected A/D conversion value may not be obtained due to coupling noise. Therefore,
avoid applying pulses to pins adjacent to the pin undergoing A/D conversion.
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(7) AVREF0 pin
This pin inputs the A/D converter reference voltage.
It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AVREF0
and AVSS.
The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AVREF0
pin to AVSS level in standby mode.
Caution A series resistor string of approximately 10 kΩ is connected between the AVREF0 pin and AVSS
pin. Therefore, if the output impedance of the reference voltage supply is high, this will result
in series connection to the series resistor string between AVREF0 pin and the AVSS pin,
resulting in a large reference voltage error.
(8) AVSS pin
This is the GND potential pin of the A/D converter. Keep it at the same potential as the VSS pin when not using
the A/D converter.
(9) AVDD pin
This is the A/D converter analog power supply pin. Keep it at the same potential as the VSS pin when not using
the A/D converter.
12.3 Registers Controlling A/D Converter
The following four registers are used to control the A/D converter.
• A/D converter mode register (ADM)
• A/D converter input select register (ADIS)
• External interrupt mode register 1 (INTM1)
• A/D current cut select register (IEAD)
(1) A/D converter mode register (ADM)
This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and
external trigger.
ADM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ADM to 01H.
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Figure 12-2. Format of A/D Converter Mode Register
Symbol
7
6
5
ADM
CS
TRG
FR1
4
3
2
1
0
FR0 ADM3 ADM2 ADM1 HSC
CS
Address
FF80H
After
Reset
01H
R/W
R/W
A/D Conversion Operation Control
0
Operation stop
1
Operation start
TRG
External Trigger Selection
0
No external trigger (software start)
1
Conversion started by external trigger (hardware start)
FR1
FR0
HSC
0
0
1
80/f XX (20.0 µ s)
0
1
1
40/f XX (setting prohibited Note 2)
1
0
0
50/f XX (setting prohibited
1
0
1
100/f XX (25.0 µ s)
Other than above
A/D Conversion Time Selection
Note 2
Note 1
)
Setting prohibited
ADM3 ADM2 ADM1
Analog Input Channel Selection
0
0
0
ANI0
0
0
1
ANI1
0
1
0
ANI2
0
1
1
ANI3
1
0
0
ANI4
1
0
1
ANI5
1
1
0
ANI6
1
1
1
ANI7
Notes 1. Set so that the A/D conversion time is 19.1 µs or more.
2. Setting prohibited because A/D conversion time is less than 19.1 µs.
Cautions 1. The following sequence is recommended to reduce the power consumption of the
A/D converter when the standby function is used: Clear bit 7 (CS) to 0 first to stop
the A/D conversion operation, and then execute the HALT or STOP instruction.
2. When restarting the stopped A/D conversion operation, start the A/D conversion
operation after clearing the interrupt request flag (ADIF) to 0.
Remarks 1. fXX: Main system clock frequency
2. Figures in parentheses apply to operation with fXX = 4.0 MHz.
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(2) A/D converter input select register (ADIS)
This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels
or ports. Pins other than those selected as analog input can be used as I/O ports.
ADIS is set with an 8-bit memory manipulation instruction.
RESET input clears ADIS to 00H.
Cautions 1. Set the analog input channel in the following order.
(1) Set the number of analog input channels with ADIS.
(2) Using the A/D converter mode register (ADM), select one channel to undergo A/D
conversion from among the channels set for analog input with ADIS.
2. No on-chip pull-up resistor can be used for the channels set to analog input with ADIS,
irrespective of the value of bit 1 (PUO1) of pull-up resistor option register L (PUOL).
Figure 12-3. Format of A/D Converter Input Select Register
Symbol
7
6
5
4
ADIS
0
0
0
0
3
2
1
0
ADIS3 ADIS2 ADIS1 ADIS0
ADIS3 ADIS2 ADIS1 ADIS0
Address
After
Reset
R/W
FF84H
00H
R/W
Selection of Analog Input Channel Number
0
0
0
0
No analog input channel (P10 to P17)
0
0
0
1
1 channel (ANI0, P11 to P17)
0
0
1
0
2 channel (ANI0, ANI1, P12 to P17)
0
0
1
1
3 channel (ANI0 to ANI2, P13 to P17)
0
1
0
0
4 channel (ANI0 to ANI3, P14 to P17)
0
1
0
1
5 channel (ANI0 to ANI4, P15 to P17)
0
1
1
0
6 channel (ANI0 to ANI5, P16, P17)
0
1
1
1
7 channel (ANI0 to ANI6, P17)
1
0
0
0
8 channel (ANI0 to ANI7)
Other than above
Setting prohibited
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(3) External interrupt mode register 1 (INTM1)
This register sets the valid edge of INTP3 to INTP6.
INTM1 is set with an 8-bit memory manipulation instruction.
RESET input clears INTM1 to 00H.
Figure 12-4. Format of External Interrupt Mode Register 1
Symbol
7
6
5
4
3
2
1
0
INTM1 ES71 ES70 ES61 ES60 ES51 ES50 ES41 ES40
ES71 ES70
After
Reset
R/W
FFEDH
00H
R/W
INTP6 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES61 ES60
INTP5 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES51 ES50
INTP4 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES41 ES40
234
Address
INTP3 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
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(4) A/D current cut select register (IEAD)
This register specifies whether AVDD and AVREF0 are connected.
.
In a system where a high accuracy is not required and where AVDD =
. AV REF0 , the AVREF0 pin is left open and
AVDD and AVREF0 are connected normally. In the standby mode, these pins are disconnected from each other.
In this way, the power consumption in the standby mode can be reduced.
IEAD is set with an 8-bit memory manipulation instruction.
RESET input clears IEAD to 00H.
Figure 12-5. Format of A/D Current Cut Select Register
Symbol
7
6
5
4
3
2
1
0
Address
After
Reset
R/W
IEAD
0
0
0
0
0
0
0
IEAD0
F8E2H
00H
R/W
IEAD0
Control of Connection Between AVDD and AVREF0
0
AVDD and AVREF0 disconnected
1
AVDD and AVREF0 connected
Figure 12-6. Function of A/D Current Cut Select Register
AVDD
AVDD
Connection
Control
AVDD ≠ AVREF0 or
where accuracy is required
Power consumption can be
reduced via connection/
disconnection control by IEAD0.
AVREF0
AVREF0
(open)
AVSS
AVSS
AVDD = AVREF0 and
where accuracy is not required
Caution The A/D current cut select register of this product is not registered in the device file.
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12.4 A/D Converter Operation
12.4.1 Basic operation of A/D converter
(1) Set the number of analog input channels using the A/D converter input select register (ADIS).
(2) From among the analog input channels set using ADIS, select one channel for A/D conversion using A/D
converter mode register (ADM).
(3) Sample the voltage input to the selected analog input channel using the sample & hold circuit.
(4) Sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit
holds the input analog voltage until the end of A/D conversion.
(5) Bit 7 of the successive approximation register (SAR) is set and the tap selector sets the series resistor string
voltage tap to (1/2) AVREF0.
(6) The voltage difference between the series resistor string voltage tap and analog input is compared by the
voltage comparator. If the analog input is greater than (1/2) AVREF0, the MSB of SAR remains set. If the input
is smaller than (1/2) AVREF0, the MSB is reset.
(7) Next, bit 6 of SAR is automatically set and the operation proceeds to the next comparison. In this case, the
series resistor string voltage tap is selected according to the preset value of bit 7 as described below.
• Bit 7 = 1: (3/4) AVREF0
• Bit 7 = 0: (1/4) AVREF0
The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated using the result as
follows.
• Analog input voltage ≥ Voltage tap: Bit 6 = 1
• Analog input voltage < Voltage tap: Bit 6 = 0
(8) Comparison continues in this way up to bit 0 of SAR.
(9) Upon completion of the comparison of 8 bits, the valid digital result that remains in SAR is transferred to and
latched in the A/D conversion result register (ADCR).
At the same time, the A/D conversion termination interrupt request (INTAD) can also be generated.
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Figure 12-7. A/D Converter Basic Operation
Conversion
Time
Sampling Time
A/D Converter
Operation
Sampling
SAR
Undefined
A /D Conversion
80H
C0H
or
40H
Conversion
Result
Conversion
Result
ADCR
INTAD
A/D conversion operations are performed continuously until bit 7 (CS) of ADM is reset (to 0) by software.
If a write to ADM is performed during an A/D conversion operation, the conversion operation is initialized, and if
the CS bit is set (to 1), conversion starts again from the beginning.
RESET input makes ADCR undefined.
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12.4.2 Input voltage and conversion results
The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D
conversion result (the value stored in the A/D conversion result register (ADCR)) is shown by the following expression.
VIN
ADCR = INT (
× 256 + 0.5)
AVREF0
or
AVREF0
(ADCR – 0.5) × AVREF0 ≤ VIN < (ADCR + 0.5) ×
256
256
Where,
INT( ):
Function that returns the integer part of the value in parentheses.
VIN:
Analog input voltage
AVREF0:
AVREF0 pin voltage
ADCR:
Value of A/D conversion result register (ADCR)
Figure 12-8 shows the relationship between the analog input voltage and the A/D conversion result.
Figure 12-8. Relationship Between Analog Input Voltage and A/D Conversion Result
255
254
A/D Conversion
Result
(ADCR)
253
3
2
1
0
1
1
3
2
5
3
512 256 512 256 512 256
507 254 509 255 511
512 256 512 256 512
Input Voltage/AVREF0
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12.4.3 A/D converter operating mode
One analog input channel is selected from among ANI0 to ANI7 with the A/D converter input select register (ADIS)
and A/D converter mode register (ADM) and A/D conversion is started.
A/D conversion can be started in the following two ways.
• Hardware start: Conversion is started by trigger input (INTP3).
• Software start: Conversion is started by setting ADM.
The A/D conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal
(INTAD) is generated simultaneously.
(1) A/D conversion by hardware start
When bit 6 (TRG) and bit 7 (CS) of the A/D converter mode register (ADM) are set to 1, the A/D conversion
standby state is set. When the external trigger signal (INTP3) is input, A/D conversion starts on the voltage
applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM.
At the end of A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR) and
the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started and ends,
another operation is not started until a new external trigger signal is input.
If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D
conversion operation and waits for a new external trigger signal to be input. When the external trigger input
signal is reinput, A/D conversion is carried out from the beginning.
If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops
immediately.
Figure 12-9. A/D Conversion by Hardware Start
INTP3
ADM Rewrite
CS = 1, TRG = 1
ADM Rewrite
CS = 1, TRG = 1
A /D Conversion
Standby
State
ADCR
ANIn
ANIn
ANIn
Standby
State
ANIn
ANIn
Standby
State
ANIn
ANIm
ANIm
ANIm
ANIm
ANIm
INTAD
Remarks 1. n = 0, 1, ..., 7
2. m = 0, 1, ..., 7
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(2) A/D conversion operation by software start
When bit 6 (TRG) and bit 7 (CS) of the A/D converter mode register (ADM) are set to 0 and 1, respectively,
the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to
ADM3) of ADM.
At the end of A/D conversion, the conversion result is stored in the A/D conversion result register (ADCR) and
the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started and ends,
the next A/D conversion operation starts immediately. The A/D conversion operation continues repeatedly
until new data is written to ADM.
If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D
conversion operation and starts A/D conversion on the newly written data.
If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops
immediately.
Figure 12-10. A/D Conversion by Software Start
Conversion Start
CS = 1, TRG = 0
A /D Conversion
ANIn
ADM Rewrite
CS = 1, TRG = 0
ANIn
ANIn
ANIm
ADM Rewrite
CS = 0, TRG = 0
ANIm
Conversion suspended
Conversion results are
not stored
ADCR
ANIn
ANIn
INTAD
Remarks 1. n = 0, 1, ..., 7
2. m = 0, 1, ..., 7
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ANIm
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12.5 How to Read the A/D Converter Characteristics Table
Here the special terms unique to A/D converters are explained.
(1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input
voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect
to the full scale is expressed by %FSR (Full Scale Range).
When the resolution is 8 bits,
1LSB = 1/28 = 1/256
= 0.4%FSR
Accuracy is not related to resolution, but is determined by overall error.
(2) Overall error
This shows the maximum error value between the actual measured value and the theoretical value.
Zero-scale offset, full-scale offset, integral linearity error, differential linearity error and errors which are
combinations of these express the overall error.
Note that the quantization error is not included in overall error in the characteristics table.
(3) Quantization error
When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter,
an analog input voltages in a range of ±1/2LSB are converted to the same digital code, so a quantization error
cannot be avoided.
Note that the quatization error is not included in the overall error, zero-scale offset, full-scale offset, integral
linearity error, and differential linearity error in the characteristics table.
Figure 12-11. Overall Error
Figure 12-12. Quantization Error
1……1
1……1
Overall
Error
Digital Output
Digital Output
Ideal Line
1/2LSB
Quantization Error
1/2LSB
0……0
0……0
AVREF0
0
Analog Input
AVREF0
0
Analog Input
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(4) Conversion time
This expresses the time from when the analog input voltage was applied to when the digital output was
obtained.
Sampling time is included in the conversion time in the characteristics table.
(5) Sampling time
This is the time the analog switch is turned on for the analog voltage to be sampled by the sample and hold
circuit.
Sampling
Time
242
Conversion Time
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12.6 Cautions for A/D Converter
(1) Power consumption in standby mode
The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode or in
HALT mode with the subsystem clock. As a current still flows through the AVREF0 pin at this time, this current
must be cut in order to minimize the overall system power consumption. The power consumption can be
reduced in the standby mode as follows:
(a) Using port
Figure 12-13 shows an example of reducing the power consumption in the standby mode by using a port.
In this example, the power consumption can be reduced if a low level is output to the output port in the
standby mode. However, because the voltage of AVREF0 is not accurate, the converted value is not
accurate and can only be used for relative comparison.
Figure 12-13. Example of Method of Reducing Current Consumption in Standby Mode (Using Port)
VDD
Output Port
µ PD78098B
AVREF0
.
AVREF0 =. VDD
Series Resistor String
AVSS
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(b) Using A/D current cut select register (IEAD)
Figure 12-14 shows an example of using the A/D current cut select register (IEAD).
.
In a system where a high accuracy is not required and where AVDD =. AVREF0, the AVREF0 pin is left open
and AVDD and AVREF0 are connected normally (IEAD = 00H). In the standby mode, these pins are
disconnected from each other (IEAD = 01H). In this way, the power consumption in the standby mode
can be reduced.
However, the conversion accuracy is lower than when a voltage is applied to the AVREF0 pin because the
characteristics of the internal switch are reflected.
Figure 12-14. Example of Reducing Power Consumption in Standby Mode
(Using A/D Current Cut Select Register)
Power consumption can be
reduced via connection/
disconnection control by
IEAD0.
AVDD
.
AVDD =. AVREF0
AVREF0
(open)
Connection
Control
µ PD78098B
AVSS
(2) Input range of ANI0 to ANI7
The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage above
AVREF0 or below AVSS is input (even if within the absolute maximum rating range), the conversion value for
that channel will be undefined. The conversion values of the other channels may also be affected.
(3) Noise countermeasures
In order to maintain 8-bit resolution, attention must be paid to noise on the AVREF0 and ANI0 to ANI7 pins.
Since the effect increases in proportion to the output impedance of the analog input source, it is recommended
that a capacitor be connected externally as shown in Figure 12-15 in order to reduce noise.
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Figure 12-15. Analog Input Pin Processing
If there is possibility that noise whose
level is AVREF0 or higher or AVSS or lower may enter,
clamp with a diode with a small VF (0.3 V or less).
Reference
Voltage Input
AVREF0
ANI0 to ANI7
VDD
C = 100 to 1000 pF
VDD
AVDD
AVSS
VSS
Note
To reduce EMI noise, supply separate voltages to VDD and AVDD, and separately ground VSS and AVSS.
(4) ANI0/P10 to ANI7/P17 pins
The analog input pins ANI0 to ANI7 also function as I/O port (port 1) pins. When A/D conversion is performed
with any of pins ANI0 to ANI7 selected, be sure not to execute an instruction that inputs data to port 1 while
conversion is in progress, as this may reduce the conversion resolution.
Also, if digital pulses are applied to other analog input pins undergoing A/D conversion, the expected A/D
conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to other
analog input pins undergoing A/D conversion.
(5) AVREF0 pin input impedance
A series resistor string of approximately 10 kΩ is connected between the AVREF0 pin and the AVSS pin.
Therefore, if the output impedance of the reference voltage supply is high, this will result in series connection
to the series resistor string between the AVREF0 pin and the AVSS pin, resulting in a large reference voltage
error.
(6) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed.
Caution is therefore required since, if an analog input pin is changed during A/D conversion, the A/D conversion
result and ADIF for the pre-change analog input may be set just before ADM is rewritten. At this time, when
ADIF is read immediately after ADM is rewritten, ADIF may be set despite the fact that A/D conversion for
the post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before resumption of A/D conversion.
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Figure 12-16. A/D Conversion End Interrupt Generation Timing
ADM Rewrite
(Start of ANIm Conversion)
ADM Rewrite
(Start of ANIn Conversion)
A /D Conversion
ANIn
ANIn
ANIm
ANIn
ADCR
ADIF is set but ANIm
conversion has not ended
ANIn
ANIm
ANIm
ANIm
INTAD
Remarks 1. n = 0, 1, ..., 7
2. m = 0, 1, ..., 7
(7) AVDD pin
The AVDD pin is the analog circuit power supply pin, and supplies power to the input circuits of ANI0/P10 to
ANI7/P17.
Therefore, be sure to apply the voltage at the same level as VDD as shown in Figure 12-17 even in an application
where the power supply is switched to the backup power supply.
Figure 12-17. AVDD Pin Connection
AVREF0
Note
VDD
Main
Power
Supply
AVDD
Capacitor
for Backup
AVSS
VSS
Note
To reduce EMI noise, supply separate voltages to VDD and AVDD, and separately ground VSS and AVSS.
(8) Manipulating ports during A/D converter operation
Do not manipulate pins that have alternate function as ports (refer to (1) Port pins in 2.1.1 Normal operating
mode pins) as follows during A/D conversion; otherwise, the specification of the overall error during A/D
conversion may not be satisfied.
<1> Rewriting the output latch of a pin when the pin is used as a port
<2> Changing the output level of a pin even when the pin is not used as a port
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(9) A/D conversion result register (ADCR) read operation
When the A/D converter mode register (ADM) and A/D converter input select register (ADIS) are written, the
contents of ADCR may become undefined. Read the conversion result following conversion completion before
writing to ADM and ADIS. Using a timing other than the above may cause an incorrect conversion result to
be read.
(10) Timing at which A/D conversion result is undefined
The A/D conversion value may be undefined if the timing of completion of A/D conversion and the timing of
stopping the A/D conversion conflict with each other. Therefore, read the the A/D conversion result during
the A/D conversion operation. To read the conversion result after stopping the A/D conversion operation, be
sure to stop the A/D conversion before the next conversion ends.
Figures 12-18 and 12-19 show the timing of reading the conversion result.
Figure 12-18. Timing of Reading Conversion Result (When Conversion Result Is Undefined)
A/D conversion completes.
ADCR
A/D conversion completes.
Normal Conversion Result
Undefined Value
INTAD
ADCS
Normal conversion result is read.
A/D conversion
is stopped.
Undefined value
is read.
Figure 12-19. Timing of Reading Conversion Result (When Conversion Result Is Normal)
A/D conversion completes
ADCR
Normal Conversion Result
INTAD
CS
A/D conversion is stopped.
Normal conversion
result is read.
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D/A CONVERTER
CHAPTER 13 D/A CONVERTER
13.1 D/A Converter Functions
The D/A converter converts a digital input into an analog value and is a two-channel 8-bit resolution voltage-outputtype converter.
The conversion method used is the R-2R resistor ladder method.
Start A/D conversion by setting the DACE0 and DACE1 of the D/A converter mode register (DAM).
There are two types of modes for the D/A converter, as follows.
(1) Normal mode
Outputs an analog voltage signal immediately after the D/A conversion.
(2) Real-time output mode
Outputs an analog voltage signal synchronously with the output trigger after the D/A conversion.
Since a sine wave can be generated in this mode, it is useful for an MSK modem for cordless telephone sets.
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13.2 D/A Converter Configuration
The D/A converter consists of the following hardware.
Table 13-1. D/A Converter Configuration
Item
Configuration
Registers
D/A conversion value set register 0 (DACS0)
D/A conversion value set register 1 (DACS1)
Control register
D/A converter mode register (DAM)
Figure 13-1. D/A Converter Block Diagram
Internal Bus
D/A Conversion Value
Set Register 1
(DACS1)
DACS1 Write
INTTM2
DACS0 Write
D/A Conversion Value
Set Register 0
(DACS0)
INTTM1
2R
ANO1/P131
AVREF1
2R
R
2R
R
Selector
AVSS
2R
2R
ANO0/P130
2R
R
2R
R
Selector
2R
DAM5 DAM4 DACE1 DACE0
D/A Converter Mode Register (DAM)
Internal Bus
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(1) D/A conversion value set registers 0 and 1 (DACS0, DACS1)
DACS0 and DACS1 are registers that set the values used to determine the analog voltage to be output to
the ANO0 and ANO1 pins, respectively.
DACS0 and DACS1 are set with an 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
The analog voltage output to the ANO0 and ANO1 pins is determined by the following expression.
ANOn output voltage = AVREF1 ×
where,
DACSn
256
n = 0, 1
Cautions 1. In the real-time output mode, when data that is set in DACS0 and DACS1 is read before
an output trigger is generated, the previous data is read rather than the set data.
2. In the real-time output mode, data should be set to DACS0 and DACS1 after an output
trigger and before the next output trigger.
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13.3 Register Controlling D/A Converter
The D/A converter mode register (DAM) controls the D/A converter. This register sets D/A converter operation
enable/stop.
The DAM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 13-2. Format of D/A Converter Mode Register
Symbol
7
6
DAM
0
0
5
4
DAM5 DAM4
3
2
0
0
DAM5
1
0
DACE1 DACE0
Address
After
Reset
R/W
FF98H
00H
R/W
Operating Mode of D/A Converter Channel 1
0
Normal mode
1
Real-time output mode
DAM4
Operating Mode of D/A Converter Channel 0
0
Normal mode
1
Real-time output mode
DACE1
Control of D/A Converter Channel 1
0
D/A conversion stop
1
D/A conversion enable
DACE0
Control of D/A Converter Channel 0
0
D/A conversion stop
1
D/A conversion enable
Cautions 1. When using the D/A converter, alternate-function port pins should be set to the input mode,
and pull-up resistors should be disconnected.
2. Always set bits 2, 3, 6, and 7 to 0.
3. When D/A conversion is stopped, the output state is high-impedance.
4. The output triggers are INTTM1 and INTTM2 for channel 0 and channel 1, respectively, in the
real-time output mode.
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13.4 Operations of D/A Converter
(1) Select the channel 0 operating mode and channel 1 operating mode using DAM4 and DAM5, respectively,
of the D/A converter mode register (DAM).
(2) Set the data corresponding to the analog voltages output to the ANO0/P130 and ANO1/P131 pins to
D/A conversion value setting registers 0 and 1 (DACS0 and DACS1), respectively.
(3) D/A conversion of channel 0 or channel 1 can be started by setting DACE0 or DACE1 of DAM, respectively.
(4) In the normal mode, the analog voltage signals are output to the ANO0/P130 and ANO1/P131 pins immediately
after the D/A conversion. In the real-time output mode, the analog voltage signals are output synchronously
with the output triggers.
(5) In the normal mode, the analog voltage signals to be output are held until new data is set in DACS0 and DACS1.
In the real-time output mode, new data is set in DACS0 and DACS1 and then held until the next trigger is
generated.
Caution Set DACE0 and DACE1 after setting data in DACS0 and DACS1.
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D/A CONVERTER
Cautions for D/A Converter
(1) Output impedance of D/A converter
Because the output impedance of the D/A converter is high, use of current flowing from the ANOn pin (n =
0, 1) is prohibited. If the input impedance of the load for the converter is low, insert a buffer amplifier between
the load and the ANOn pin. In addition, wiring from the ANOn pin to the buffer amplifier or the load should
be as short as possible (because of high output impedance). If the wiring seems to be long, implement
measures to shorten the wiring, such as designing a ground pattern around those lines.
Figure 13-3. Example of Buffer Amplifier Insertion
(a) Inverting amplifier
C
µPD78098B
R2
R1
ANOn
• The input impedance of the buffer amplifier is R1.
(b) Voltage-follower
µPD78098B
R
ANOn
R1
C
• The input impedance of the buffer amplifier is R1.
• If R1 is not connected, the output becomes
undefined when RESET is low.
(2) Output voltage of D/A converter
Because the output voltage of the converter changes in steps, in general, use the D/A converter output signals
by connecting a low-pass filter.
(3) AVREF1 pin
When only either one of the D/A converter channels is used with AVREF1 < VDD, the other pins that are not
used as analog outputs must be set as follows:
•
Set the PM13x bit of port mode register 13 (PM13) to 1 (input mode) and connect the pin to VSS.
•
Set the PM13x bit of port mode register 13 (PM13) to 0 (output mode) and the output latch to 0, to output
a low level from the pin.
In addition, if the D/A converter is not used, connect the AVREF1 pin to VDD.
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CHAPTER 14 SERIAL INTERFACE CHANNEL 0
14.1 Functions of Serial Interface Channel 0
Serial interface channel 0 employs the following four modes.
• Operation stop mode
• 3-wire serial I/O mode
• SBI (serial bus interface) mode
• 2-wire serial I/O mode
Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while serial interface
channel 0 is enabled. Change the operating mode after stopping the serial operation.
(1) Operation stop mode
This mode is used when serial transfer is not carried out to reduce power consumption.
(2) 3-wire serial I/O mode (MSB-/LSB-first selectable)
This mode is used for 8-bit data transfer using three lines, one each for the serial clock (SCK0), serial output
(SO0) and serial input (SI0). This mode enables simultaneous transmission/reception and therefore reduces
the data transfer processing time.
The start bit of 8-bit data to be serially transferred is switchable between the MSB and LSB, so that devices
can be connected regardless of their start bit recognition.
This mode should be used when connecting with peripheral I/O devices or display controllers that incorporate
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series.
(3) SBI (serial bus interface) mode (MSB-first)
This mode is used for 8-bit data transfer with two or more devices using two lines: the serial clock (SCK0)
and serial data bus (SB0 or SB1).
The SBI mode conforms to the NEC serial bus format, and transmits or receives three types of transfer data:
“addresses”, “commands”, and “data”.
• Address:
Data to select the target device for serial communication
• Command: Data to give an instruction to the target device
• Data:
Data actually transferred
Actually, the master device outputs an “address” to the serial bus to select one of the slave devices with which
the master device is to communicate. After that, “commands” and “data” are transmitted or received between
the master and slave devices (this is the serial transfer). The receiver can automatically identify the received
data as an “address”, “command”, or “data” by hardware.
This function enables the I/O ports to be used effectively and the application program serial interface control
portions to be simplified.
In this mode, the wakeup function for handshake and the output function of the acknowledge and busy signals
can also be used.
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(4) 2-wire serial I/O mode (MSB-first)
This mode is used for 8-bit data transfer using two lines: the serial clock (SCK0) and serial data bus (SB0
or SB1).
This mode makes it possible to cope with any one of the possible data transfer formats by controlling the SCK0
level and the SB0 or SB1 output level. Thus, the handshake line previously necessary for connection of two
or more devices can be removed, resulting in an increase in the number of available I/O ports.
Figure 14-1. Serial Bus Interface (SBI) System Configuration Example
AVDD
Master CPU
Slave CPU1
SCK0
SCK0
SB0
SB0
Slave CPU2
SCK0
SB0
Slave CPUn
SCK0
SB0
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14.2 Configuration of Serial Interface Channel 0
Serial interface channel 0 consists of the following hardware.
Table 14-1. Configuration of Serial Interface Channel 0
Item
Configuration
Registers
Serial I/O shift register 0 (SIO0)
Slave address register (SVA)
Control registers
Timer clock select register 3 (TCL3)
Serial operating mode register 0 (CSIM0)
Serial bus interface control register (SBIC)
Interrupt timing specification register (SINT)
Port mode register 2 (PM2) Note
Note
Refer to Figure 4-5 Block Diagram of P20, P21, P23 to P26 and Figure 4-6 Block
Diagram of P22 and P27.
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Figure 14-2. Block Diagram of Serial Interface Channel 0
Internal Bus
Serial Operating Mode Register 0
(CSIM0)
CSIE0 COI WUP
Serial Bus Interface
Control Register (SBIC)
CSIM CSIM CSIM CSIM CSIM
04
03
02
01
00
Slave Address
Register (SVA)
BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
SVAM
Match
Controller
SI0/SB0/
P25
Selector
P25
Output Latch
PM25
Output
Control
CLR SET
D
Q
Serial I/O Shift
Register 0 (SIO0)
Busy/
Acknowledge
Output Circuit
Selector
SO0/SB1/
P26
PM26
Bus Release/
Command/
Acknowledge
Detector
Output
Control
CLD
ACKD
CMDD
RELD
WUP
Interrupt
Request
Signal
Generator
P26 Output Latch
Serial Clock
Counter
SCK0/
P27
INTCSI0
TO2
PM27
Output
Control
Serial Clock
Controller
Selector
Selector
CSIM00
CSIM01
CSIM00
CSIM01
f xx/2 to f xx/28
4
P27
Output Latch
CLD
SIC
SVAM
TCL33 TCL32 TCL31 TCL30
Interrupt Timing
Specify Register
(SINT)
Timer Clock
Select
Register 3 (TCL3)
Internal Bus
Remark
Output Control performs selection between CMOS output and N-ch open-drain output.
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(1) Serial I/O shift register 0 (SIO0)
This is an 8-bit register used to carry out parallel/serial conversion and to carry out serial transmission/
reception (shift operation) in synchronization with the serial clock.
SIO0 is set with an 8-bit memory manipulation instruction.
When bit 7 (CSIE0) of serial operating mode register 0 (CSIM0) is 1, writing data to SIO0 starts a serial
operation.
In transmission, data written to SIO0 is output to the serial output (SO0) or serial data bus (SB0/SB1). In
reception, data is read from the serial input (SI0) or SB0/SB1 to SIO0.
Note that if a bus is driven in the SBI mode or 2-wire serial I/O mode, the bus pin must serve for both input
and output. Thus, in the case of a device for reception, write FFH to SIO0 in advance (except when address
reception is carried out by setting bit 5 (WUP) of CSIM0 to 1).
In the SBI mode, the busy state can be cleared by writing data to SIO0. In this case, bit 7 (BSYE) of the serial
bus interface control register (SBIC) is not cleared to 0.
RESET input makes SIO0 undefined.
(2) Slave address register (SVA)
This is an 8-bit register used to set the slave address value for connection of a slave device to the serial bus.
SVA is set with an 8-bit memory manipulation instruction. This register is not used in the 3-wire serial I/O
mode.
The master device outputs a slave address for selection of a particular slave device to the connected slave
device. These two data (the slave address output from the master device and the SVA value) are compared
with an address comparator. If they match, the slave device has been selected. In that case, bit 6 (COI) of
serial operating mode register 0 (CSIM0) becomes 1.
Address comparison can also be executed on the LSB-masked higher 7-bit data by setting bit 4 (SVAM) of
the interrupt timing specification register (SINT) to 1.
If no match is detected in address reception, bit 2 (RELD) of the serial bus interface control register (SBIC)
is cleared to 0. In the SBI mode, the wakeup function can be used by setting bit 5 (WUP) of CSIM0 to 1. In
this case, the interrupt request signal (INTCSI0) is generated only when the slave address output by the master
matches the value of SVA, and it can be learned by this interrupt request that the master requests
communication. If bit 5 (SIC) of the interrupt timing specification register (SINT) is set to 1, the wakeup function
cannot be used even if WUP is set to 1 (an interrupt request signal is generated when a bus release is detected).
To use the wakeup function, clear SIC to 0.
Further, an error can be detected by using SVA when the device transmits data as the master or slave device
in the SBI or 2-wire serial I/O mode.
RESET input makes SVA undefined.
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(3) SO0 latch
This latch holds the SI0/SB0/P25 and SO0/SB1/P26 pin levels. It can be directly controlled by software. In
the SBI mode, this latch is set upon termination of the 8th serial clock.
(4) Serial clock counter
This counter counts the serial clocks to be output and input during transmission/reception and to check whether
8-bit data has been transmitted/received.
(5) Serial clock controller
This circuit controls the serial clock supply to serial I/O shift register 0 (SIO0). When the internal system clock
is used, the circuit also controls clock output to the SCK0/P27 pin.
(6) Interrupt request signal generator
This circuit controls interrupt request signal generation. It generates an interrupt request signal in the following
cases.
• In the 3-wire serial I/O mode and 2-wire serial I/O mode
This circuit generates an interrupt request signal every eight serial clocks.
• In the SBI mode
When WUP is 0 ........... Generates an interrupt request signal every eight serial clocks.
When WUP is 1 ........... Generates an interrupt request signal when the serial I/O shift register 0 (SIO0)
value matches the slave address register (SVA) value after address reception.
Remark WUP is the wakeup function specification bit. It is bit 5 of serial operating mode register 0 (CSIM0).
To use the wakeup function (WUP = 1), clear bit 5 (SIC) of the interrupt timing specification register
(SINT) to 0.
(7) Busy/acknowledge output circuit and bus release/command/acknowledge detector
These two circuits output and detect various control signals in the SBI mode.
These do not operate in the 3-wire serial I/O mode and 2-wire serial I/O mode.
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14.3 Registers Controlling Serial Interface Channel 0
The following four registers are used to control serial interface channel 0.
• Timer clock select register 3 (TCL3)
• Serial operating mode register 0 (CSIM0)
• Serial bus interface control register (SBIC)
• Interrupt timing specify register (SINT)
(1) Timer clock select register 3 (TCL3)
This register sets the serial clock of serial interface channel 0.
TCL3 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL3 to 88H.
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Figure 14-3. Format of Timer Clock Select Register 3
Symbol
7
6
5
4
3
2
1
0
TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30
TCL37 TCL36 TCL35 TCL34
1
1
0
fXX/2 Note
0
1
1
1
fXX/22
(1.0 MHz)
1
0
0
0
fXX/23
(500 kHz)
1
0
0
1
fXX/24
(250 kHz)
1
0
1
0
fXX/2
(125 kHz)
1
0
1
1
fXX/26
(62.5 kHz)
1
1
0
0
fXX/27
(31.3 kHz)
1
1
0
1
fXX/2
(15.6 kHz)
5
8
FF43H
88H
R/W
Serial Interface Channel 0 Serial Clock Selection
Note
0
1
1
0
fXX/2
0
1
1
1
fXX/22
(1.0 MHz)
1
0
0
0
fXX/23
(500 kHz)
1
0
0
1
fXX/24
(250 kHz)
1
0
1
0
fXX/25
(125 kHz)
1
0
1
1
fXX/26
(62.5 kHz)
1
1
0
0
fXX/27
(31.3 kHz)
1
1
0
1
fXX/2
(15.6 kHz)
Note
R/W
Setting prohibited
TCL33 TCL32 TCL31 TCL30
Other than above
After Reset
Serial Interface Channel 1 Serial Clock Selection
0
Other than above
Address
8
Setting prohibited
This can only be set when the main system clock frequency is 5.0 MHz or less.
Caution When rewriting TCL3 to other data, stop the serial transfer operation beforehand.
Remarks 1. fXX:
Main system clock frequency
2. Figures in parentheses apply to operation with fXX = 4.0 MHz.
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(2) Serial operating mode register 0 (CSIM0)
This register sets serial interface channel 0 serial clock, operating mode, operation enable/stop, wakeup
function and displays the address comparator match signal.
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Caution Do not change the operating mode (3-wire serial I/O, 2-wire serial I/O, or SBI) while serial
interface channel 0 is enabled. To change the operating mode, first stop the serial operation.
Figure 14-4. Format of Serial Operating Mode Register 0 (1/2)
Symbol
7
6
CSIM0 CSIE0 COI
R/W
R
R/W
5
WUP
4
3
2
1
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIE0
Address
After Reset
FF60H
R/W
00H
R/W Note 1
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enabled
COI
Slave Address Comparison Result Flag Note 2
0
Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data
1
Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
WUP
Wakeup Function Control
Note 3
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after bus release (when CMDD = RELD = 1)
matches the slave address register (SVA) data in SBI mode
Notes 1. Bit 6 (COI) is a read-only bit.
2. When CSIE0 = 0, COI becomes 0.
3. Clear bit 5 (SIC) of the interrupt timing specification register (SINT) to 0 when using the wakeup
function (WUP = 1).
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Figure 14-4. Format of Serial Operating Mode Register 0 (2/2)
R/W
CSIM CSIM CSIM
PM25 P25 PM26 P26 PM27 P27
04
03
×
0
02
Operating
Mode
Note 1 Note 1
0
1
1
×
0
0
0
1
3-wire serial
l/O mode
Start Bit
SIO/SB0/P25
Pin Function
SO0/SB1/P26
Pin Function
SCK0/P27
Pin Function
SI0 Note 1
(Input)
SO0
(CMOS output)
SCK0
(CMOS I/O)
P25
(CMOS I/O)
SB1
(N-ch
open-drain I/O)
MSB
LSB
Note 2 Note 2
×
0
1
×
0
0
0
1
SBI mode
0
Note 2 Note 2
0
1
0
SCK0
(CMOS I/O)
MSB
×
×
0
1
SB0
(N-ch
open-drain I/O)
P26
(CMOS I/O)
0
0
0
1
P25
(CMOS I/O)
SB1
(N-ch
open-drain I/O)
Note 2 Note 2
×
0
1
×
2-wire serial
l/O mode
1
Note 2 Note 2
0
1
R/W
0
×
×
0
MSB
SB0
(N-ch
open-drain I/O)
1
SCK0
(N-ch
open-drain I/O)
P26
(CMOS I/O)
Serial Interface Channel 0 Clock Selection
CSIM01 CSIM00
0
×
Input clock to SCK0 pin from off-chip
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
Notes 1. Can be used as P25 (CMOS I/O) when used only for transmission.
2. Can be used freely as port function.
Remark
×:
Don’t care
PM××: Port mode register
P××:
Port output latch
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(3) Serial bus interface control register (SBIC)
This register sets the serial bus interface operation and displays statuses.
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Figure 14-5. Format of Serial Bus Interface Control Register (1/2)
Symbol
7
6
5
4
3
2
1
0
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
FF61H
00H
R/W
R/W
Note 1
Synchronizing Busy Signal Output Control
0
Disables busy signal which is output in synchronization with the falling edge of SCK0 clock just after
execution of the instruction that clears this bit to 0.
1
Outputs busy signal at the falling edge of SCK0 clock following the acknowledge signal.
ACKD
Acknowledge Detection
Set Conditions (ACKD = 1)
Clear Conditions (ACKD = 0)
• Falling edge of SCK0 immediately after the busy
mode is released while executing the transfer
start instruction
• When CSIE0 = 0
• When RESET input is applied
R/W
After Reset
Note 2
BSYE
R
Address
ACKE
0
1
• When acknowledge signal (ACK) is detected at the
rising edge of SCK0 clock after completion of
transfer
Acknowledge Signal Output Control
Acknowledge signal automatic output disable (output with ACKT enable)
Before completion of
transfer
Acknowledge signal is output in synchronization with the falling edge of the 9th
SCK0 clock (automatically output when ACKE = 1).
After completion of
transfer
Acknowledge signal is output in synchronization with the falling edge of
SCK0 just after execution of the instruction that sets this bit to 1
(automatically output when ACKE = 1).
However, not automatically cleared to 0 after acknowledge signal output.
Notes 1. Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
2. The busy mode can be cancelled by start of serial interface transfer. However, the BSYE flag
is not cleared to 0.
Remark
264
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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Figure 14-5. Format of Serial Bus Interface Control Register (2/2)
R/W
ACKT
Acknowledge signal is output in synchronization with the falling edge of the SCK0 clock just after execution
of the instruction that sets this bit to 1, and after acknowledge signal output, is automatically cleared to 0.
Used as ACKE = 0. Also cleared to 0 upon start of serial interface transfer or when CSIE0 = 0.
R CMDD
Command Detection
Set Conditions (CMDD = 1)
Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When bus release signal (REL) is detected
• When CSIE0 = 0
• When RESET input is applied
R
RELD
Bus Release Detection
Clear Conditions (RELD = 0)
Set Conditions (RELD = 1)
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in
address reception
• When CSIE0 = 0
• When RESET input is applied
R/W
• When command signal (CMD) is detected
• When bus release signal (REL) is detected
CMDT
Used for command signal output.
When CMDT = 1, SO Iatch is cleared to (0). After SO latch clearance, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
RELT
Used for bus release signal output.
When RELT = 1, SO Iatch is set to 1. After SO latch setting, automatically cleared to 0.
Also cleared to 0 when CSIE0 = 0.
R/W
Remarks 1.
Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when they are read after data has been
set.
2.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(4) Interrupt timing specification register (SINT)
This register sets the bus release interrupt and address mask functions and displays the SCK0 pin level status.
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Figure 14-6. Format of Interrupt Timing Specification Register
Symbol
7
6
SINT
0
CLD
R
R/W
R/W
5
4
SIC SVAM
3
2
1
0
Address
0
0
0
0
FF63H
CLD
After Reset
00H
R/W Note 1
SCK0 Pin Level Note 2
0
Low level
1
High level
SIC
INTCSI0 Interrupt Source SelectionNote 3
0
CSIIF0 is set upon termination of serial interface channel 0 transfer
1
CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer
SVAM
SVA Bit to be Used as Slave Address
0
Bits 0 to 7
1
Bits 1 to 7
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
3. When using the wakeup function in the SBI mode, set SIC to 0.
Caution Be sure to set bits 0 to 3 to 0.
Remark
266
R/W
SVA:
Slave address register
CSIIF0:
Interrupt request flag corresponding to INTCSI0
CSIE0:
Bit 7 of serial operating mode register 0 (CSIM0)
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14.4 Operations of Serial Interface Channel 0
The following four operating modes are available for serial interface channel 0.
• Operation stop mode
• 3-wire serial I/O mode
• SBI mode
• 2-wire serial I/O mode
14.4.1 Operation stop mode
Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. Serial
I/O shift register 0 (SIO0) does not carry out shift operations either and thus it can be used as ordinary 8-bit register.
In the operation stop mode, the P25/SI0/SB0, P26/SO0/SB1 and P27/SCK0 pins can be used as ordinary I/O ports.
(1) Register setting
The operation stop mode is set with serial operating mode register 0 (CSIM0).
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Symbol
7
6
CSIM0 CSIE0 COI
R/W
5
WUP
4
3
2
1
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIE0
Address
FF60H
After Reset
00H
R/W
R/W
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enabled
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14.4.2 3-wire serial I/O mode operation
The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers that incorporate
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series.
Communication is carried out with three lines: a serial clock (SCK0), serial output (SO0), and serial input (SI0).
(1) Register setting
The 3-wire serial I/O mode is set with serial operating mode register 0 (CSIM0) and serial bus interface control
register (SBIC).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
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Symbol
7
6
5
CSIM0 CSIE0 COI
R/W
R/W
R/W
4
WUP
3
SERIAL INTERFACE CHANNEL 0
2
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIE0
Address
After Reset
FF60H
00H
R/W
R/W Note 1
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enabled
WUP
Wakeup Function Control
Note 2
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after bus release
(when CMDD = RELD = 1) matches the slave address register (SVA) data in SBI mode
CSIM CSIM CSIM
PM25 P25 PM26 P26 PM27 P27
04
0
R/W
1
03
×
02
0
Operation
Mode
Note 3 Note 3
1
1
×
0
0
0
1
3-wire serial
l/O mode
Start Bit
MSB
LSB
SIO/SB0/P25
Pin Function
Note 3
SI0
(Input)
1
0
SBI mode (see 14.4.3 SBI mode operation)
1
1
2-wire serial I/O mode (see 14.4.4 2-wire serial I/O mode operation)
SO0/SB1/P26
Pin Function
SCK0/P27
Pin Function
SO0
(CMOS output)
SCK0
(CMOS I/O)
Serial Interface Channel 0 Clock Selection
CSIM01 CSIM00
0
×
Input clock to SCK0 pin from off-chip
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
Notes 1. Bit 6 (COI) is a read-only bit.
2. Be sure to set WUP to 0 when the 3-wire serial I/O mode is selected.
3. Can be used as P25 (CMOS input/output) when used only for transmission.
Remark
×:
Don’t care
PM××: Port mode register
P××:
Port output latch
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(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Symbol
7
6
5
4
3
2
1
0
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
Address
FF61H
00H
R/W
R/W
R/W
CMDT
When CMDT = 1, the SO Iatch is cleared to 0. After SO latch clearance, CMDT is automatically cleared to 0.
It is also cleared to 0 when CSIE0 = 0.
R/W
RELT
When RELT = 1, the SO Iatch is set to 1. After SO Iatch setting, RELT is automatically cleared to 0.
It is also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
270
After Reset
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(2) Communication operation
The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception
is carried out in 1-bit units in synchronization with the serial clock.
Shift operations of serial I/O shift register 0 (SIO0) are carried out at the falling edge of the serial clock (SCK0).
The transmitted data is held in the SO0 latch and is output from the SO0 pin. The received data input to the
SI0 pin is latched in SIO0 at the rising edge of SCK0.
Upon termination of 8-bit transfer, SIO0 operation stops automatically and the interrupt request flag (CSIIF0)
is set.
Figure 14-7. Timing in 3-Wire Serial I/O Mode
SCK0
1
2
3
4
5
6
7
8
SI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIIF0
End of Transfer
Transfer Starts at Falling Edge of SCK0
The SO0 pin is a CMOS output pin and outputs the current SO0 latch status. Thus, the SO0 pin output status
can be manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC).
However, do not carry out this manipulation during serial transfer.
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27
output latch (refer to 14.4.5 SCK0/P27 pin output manipulation).
(3) Other signals
Figure 14-8 shows the RELT and CMDT operations.
Figure 14-8. RELT and CMDT Operations
SO0 Latch
RELT
CMDT
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(4) MSB/LSB start bit switching
In the 3-wire serial I/O mode, transfer can be selected to start from the MSB or LSB.
Figure 14-9 shows the configuration of serial I/O shift register 0 (SIO0) and the internal bus. As shown in the
figure, the MSB/LSB can be read/written in reverse.
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM02) of serial operating mode register 0
(CSIM0).
Figure 14-9. Transfer Bit Order Switching Circuit
7
6
Internal Bus
1
0
LSB-first
MSB-first
Read/Write Gate
Read/Write Gate
SO0 Latch
SI0
Shift Register 0 (SIO0)
D
Q
SO0
SCK0
Start-bit switching is realized by switching the bit order for a data write to SIO0. The SIO0 shift order remains
unchanged.
Thus, switch the MSB/LSB start bit before writing data to the shift register.
(5) Transfer start
Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
• Serial interface channel 0 operation control bit (CSIE0) = 1.
• Internal serial clock is stopped or SCK0 is high level after 8-bit serial transfer.
Caution If CSIE0 is set to 1 after data is written to SIO0, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
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14.4.3 SBI mode operation
SBI (Serial Bus Interface) is a high-speed serial interface that complies with the NEC serial bus format.
SBI uses a single master device and employs the clocked serial I/O format with the addition of a bus configuration
function. This function enables devices to communicate using only two lines. Thus, when configuring a serial bus
with two or more microcontrollers and peripheral ICs, the number of ports to be used and the number of wires on
the board can be decreased.
The master device outputs three kinds of data to slave devices on the serial data bus: “addresses” to select a device
to be communicated with, “commands” to instruct the selected device, and the “data” that is actually required.
The slave device can identify the received data as an “address”, “command”, or “data”, by hardware. An application
program that controls serial interface channel 0 can be simplified by using this function.
The SBI function is incorporated into various devices including the 75X/XL Series and 78K Series.
Figure 14-10 shows a serial bus configuration example when a CPU having a serial interface compliant with SBI
and peripheral ICs are used.
In SBI, the SB0 (SB1) serial data bus pin is an open-drain output pin and therefore the serial data bus line behaves
in the same way as the wired-OR configuration. In addition, a pull-up resistor must be connected to the serial data
bus line.
When the SBI mode is used, refer to (11) SBI mode cautions (d) described later.
Figure 14-10. Example of Serial Bus Configuration with SBI
AVDD
Serial Clock
SCK0
SCK0
Slave CPU
SB0 (SB1)
Address 1
SCK0
Slave CPU
SB0 (SB1)
Address 2
Master CPU
Serial Data Bus
SB0 (SB1)
•
•
•
•
•
•
SCK0
Slave IC
SB0 (SB1)
Address N
Caution When exchanging the master CPU/slave CPU, a pull-up resistor is necessary for the serial clock
line (SCK0) as well because serial clock line (SCK0) input/output switching is carried out
asynchronously between the master and slave CPUs.
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(1) SBI functions
In the conventional serial I/O format, when a serial bus is configured by connecting two or more devices, many
ports and wiring are necessary to provide the chip select signals to identify commands and data, and to judge
the busy state, because only the data transfer function is available. If these operations are to be controlled
by software, the software must be heavily loaded.
In SBI, a serial bus can be configured with two signal lines: a serial clock SCK0 and serial data bus SB0 (SB1).
Thus, use of SBI leads to a reduction in the number of microcontroller ports, and wiring and wiring redundancies
on the board.
The SBI functions are described below.
(a) Address/command/data identification function
Serial data is identified as addresses, commands, or data.
(b) Chip select function by address transmission
The master executes slave chip selection by address transmission.
(c) Wakeup function
The slave can easily judge address reception (chip select judgment) with the wakeup function (which can
be set/reset by software).
When the wakeup function is set, the interrupt request signal (INTCSI0) is generated upon reception of
a match address.
Thus, when communication is executed with two or more devices, the CPU except the selected slave
devices can operate regardless of serial communications under execution.
(d) Acknowledge signal (ACK) control function
The acknowledge signal to check serial data reception is controlled.
(e) Busy signal (BUSY) control function
The busy signal to report the slave busy state is controlled.
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(2) SBI definition
The SBI serial data format and the signals to be used are defined as follows.
Serial data to be transferred with SBI consists of three kinds of data: “address”, “command”, and “data”.
Figure 14-11 shows the address, command, and data transfer timing.
Figure 14-11. SBI Transfer Timing
Address Transfer
SCK0
8
SB0 (SB1)
A7
Command Transfer
Bus Release
Signal
9
A0
ACK
BUSY
Address
Command Signal
SCK0
SB0 (SB1)
9
C7
C0 ACK
BUSY
READY
BUSY
READY
Command
Data Transfer
SCK0
SB0 (SB1)
8
D7
9
D0 ACK
Data
Remark
The broken lines indicate the READY status.
The bus release signal and the command signal are output by the master device. BUSY is output by the slave
device. ACK can be output by either the master or slave device (normally output by the receiver of 8-bit data).
Serial clocks continue to be output by the master device from 8-bit data transfer start to BUSY reset.
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(a) Bus release signal (REL)
The bus release signal is a signal that is output when the SB0 (SB1) line changes from low level to high
level while the SCK0 line is high level (without serial clock output).
This signal is output by the master device.
Figure 14-12. Bus Release Signal
SCK0
"H"
SB0 (SB1)
The bus release signal indicates that the master device is going to transmit an address to the slave device.
The slave device incorporates hardware to detect the bus release signal.
Caution The transition of the SB0 (SB1) line from low to high when the SCK0 line is high is
recognized as a bus release signal. If the transition timing of the bus is shifted due to
the influence of board capacitance, the transmitted data may be judged as a bus release
signal. Exercise care in wiring so that noise is not superimposed on the signal lines.
(b) Command signal (CMD)
The command signal is a signal that is output when the SB0 (SB1) line changes from high level to low
level while the SCK0 line is high level (without serial clock output). This signal is output by the master
device.
Figure 14-13. Command Signal
SCK0
"H"
SB0 (SB1)
The command signal indicates that the master is going to transmit a command to the slave (however,
the command signal following the bus release signal indicates that an address is being transmitted).
The slave device incorporates hardware to detect the command signal.
Caution The transition of the SB0 (SB1) line from high to low when the SCK0 line is high is
recognized as a command signal. If the transition timing of the bus is shifted due to the
influence of board capacitance, transmitted data may be judged as a command signal.
Exercise care in wiring so that noise is not superimposed on the signal lines.
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(c) Address
An address is 8-bit data that the master device outputs to the slave device connected to the bus line in
order to select a particular slave device.
Figure 14-14. Address
1
SCK0
A7
SB0 (SB1)
2
A6
3
A5
4
A4
5
A3
6
A2
7
A1
8
A0
Address
Bus Release
Signal
Command Signal
8-bit data following bus release and command signals is defined as an “address”. In the slave device,
this condition is detected by hardware and whether or not 8-bit data matches its own specification number
(slave address) is checked by hardware. If the 8-bit data matches the slave address, the slave device
has been selected. After that, communication with the master device continues until a release instruction
is received from the master device.
Figure 14-15. Slave Selection with Address
Master
Slave 2
address transmission
Slave 1
Not selected
Slave 2
Selected
Slave 3
Not selected
Slave 4
Not selected
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(d) Command and data
The master device transmits commands to, and transmits/receives data to/from the slave device selected
by address transmission.
Figure 14-16. Command
SCK0
1
SB0 (SB1)
C7
2
C6
3
C5
4
5
C4
C3
6
7
8
C2
C1
C0
6
7
8
Command
Command Signal
Figure 14-17. Data
SCK0
1
SB0 (SB1)
D7
2
D6
3
D5
4
5
D4
D3
D2
D1
D0
Data
8-bit data following a command signal is defined as “command” data. 8-bit data without command signal
is defined as “data”. Command and data operation procedures can be determined by the user according
to the communication specifications.
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(e) Acknowledge signal (ACK)
The acknowledge signal is used to check serial data reception between the transmitter and receiver.
Figure 14-18. Acknowledge Signal
[When output in synchronization with 11th SCK0 clock]
SCK0
8
9
SB0 (SB1)
10
11
ACK
[When output in synchronization with 9th SCK0 clock]
SCK0
8
SB0 (SB1)
Remark
9
ACK
The broken lines indicate the READY status.
The acknowledge signal is a one-shot pulse generated at the falling edge of SCK0 after 8-bit data transfer.
It can be positioned anywhere and can be synchronized with any SCK0 clock.
After 8-bit data transmission, the transmitter checks whether the receiver has returned the acknowledge
signal. If the acknowledge signal is not returned for the preset period of time after data transmission,
it can be judged that data reception has not been carried out correctly.
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(f) Busy signal (BUSY) and ready signal (READY)
The BUSY signal is used to report to the master device that the slave device is not ready for data
transmission/reception.
The READY signal is intended to report to the master device that the slave device is ready for data
transmission/reception.
Figure 14-19. BUSY and READY Signals
SCK0
8
SB0 (SB1)
9
ACK
BUSY
READY
In SBI, the slave device notifies the master device of the busy state by setting the SB0 (SB1) line to low
level.
BUSY signal output follows acknowledge signal output from the master or slave device. It is set/reset
at the falling edge of SCK0. When the BUSY signal is reset, the master device automatically terminates
the output of the SCK0 serial clock.
When the BUSY signal is reset and the READY signal is set, the master device can start the next transfer.
Caution In the SBI mode, the BUSY signal is output until the next serial clock (SCK0) falls after
a command that resets the BUSY signal has been issued. If WUP is set to 1 during this
period by mistake, the BUSY signal is not reset. Therefore, be sure to confirm that the
SB0 (SB1) pin has gone high after resetting the BUSY signal, by setting WUP to 1.
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(3) Register setting
The SBI mode is set with serial operating mode register 0 (CSIM0), the serial bus interface control register
(SBIC), and the interrupt timing specify register (SINT).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Symbol
7
6
5
CSIM0 CSIE0 COI
R/W
R
R/W
R/W
4
WUP
3
2
1
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIE0
Address
After Reset
FF60H
00H
R/W
R/W Note 1
Serial Interface Channel 0 Operation Control
0
Operation stopped
1
Operation enabled
COI
Slave Address Comparison Result Flag Note 2
0
Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data
1
Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
WUP
Wakeup Function Control
Note 3
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after bus release
(when CMDD = RELD = 1) matches the slave address register (SVA) data in SBI mode
CSIM CSIM CSIM
PM25 P25 PM26 P26 PM27 P27
Operation
Mode
Start Bit
SI0/SB0/P25
Pin Function
04
03
02
0
×
3-wire serial I/O mode (see 14.4.2 3-wire serial I/O mode operation)
Note 4 Note 4
0
1
×
×
0
0
0
P25
(CMOS I/O)
1
SBI mode
0
SO0/SB1/P26
Pin Function
SB1
(N-ch
open-drain I/O)
MSB
Note 4 Note 4
1
1
R/W
1
0
0
×
×
0
SB0
(N-ch
open-drain I/O)
1
SCK0/P27
Pin Function
SCK0
(CMOS I/O)
P26
(CMOS I/O)
2-wire serial I/O mode (see 14.4.4 2-wire serial I/O mode operation)
Serial Interface Channel 0 Clock Selection
CSIM01 CSIM00
0
×
Input clock to SCK0 pin from off-chip
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
Notes 1. Bit 6 (COI) is a read-only bit.
2. COI is 0 when CSIE0 = 0.
3. Set bit 5 (SIC) of the interrupt timing specify register (SINT) to 1 when using the wakeup
function (WUP = 1).
4. These pins can be used freely as port pins.
Remark
×:
Don’t care
PM××: Port mode register
P××:
Port output latch
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(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Symbol
7
6
5
4
3
2
1
0
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
FF61H
00H
R/W
R/W
Note 1
Synchronizing Busy Signal Output Control
0
Disables busy signal which is output in synchronization with the falling edge of the SCK0 clock just after
execution of the instruction that clears this bit to 0.
1
Outputs busy signal at the falling edge of the SCK0 clock following the acknowledge signal.
ACKD
Acknowledge Detection
Set Conditions (ACKD = 1)
Clear Conditions (ACKD = 0)
• SCK0 falls immediately after the busy mode is
released during the transfer start instruction execution.
• When CSIE0 = 0
• When RESET input is applied
R/W
After Reset
Note 2
BSYE
R
Address
ACKE
0
• When acknowledge signal (ACK) is detected at the
rising edge of SCK0 clock after completion of
transfer
Acknowledge Signal Output Control
Acknowledge signal automatic output disable (output with ACKT enable)
Before completion of
transfer
Acknowledge signal is output in synchronization with the falling edge of the 9th SCK0
clock (automatically output when ACKE = 1).
After completion of
transfer
Acknowledge signal is output in synchronization with falling edge of the SCK0 clock
just after execution of the instruction that sets this bit to 1
(automatically output when ACKE = 1).
However, not automatically cleared to 0 after acknowledge signal output.
1
(Cont'd)
Notes 1. Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
2. The busy mode can be cleared by start of serial interface transfer. However, the BSYE flag
is not cleared to 0.
Remark
282
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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R/W
ACKT
SERIAL INTERFACE CHANNEL 0
Acknowledge signal is output in synchronization with the falling edge of the SCK0 clock just after execution
of the instruction that sets this bit to 1 and, after acknowledge signal output, is automatically cleared (to 0).
Used as ACKE = 0. Also cleared (to 0) upon start of serial interface transfer or when CSIE0 = 0.
R CMDD
Command Detection
Set Conditions (CMDD = 1)
Clear Conditions (CMDD = 0)
• When transfer start instruction is executed
• When bus release signal (REL) is detected
• When CSIE0 = 0
• When RESET input is applied
R
RELD
• When command signal (CMD) is detected
Bus Release Detection
Clear Conditions (RELD = 0)
Set Conditions (RELD = 1)
• When transfer start instruction is executed
• If SIO0 and SVA values do not match in address
reception
• When CSIE0 = 0
• When RESET input is applied
R/W
• When bus release signal (REL) is detected
CMDT
Used for command signal output.
When CMDT = 1, SO Iatch is cleared (to 0). After SO latch clearance, automatically cleared (to 0).
Also cleared to 0 when CSIE0 = 0.
RELT
Used for bus release signal output.
When RELT = 1, SO Iatch is set (to 1). After SO latch setting, automatically cleared (to 0).
Also cleared to 0 when CSIE0 = 0.
R/W
Remarks 1. Bits 0, 1, and 4 (RELT, CMDT, and ACKT) are 0 when read after data setting.
2. CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(c) Interrupt timing specify register (SINT)
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Symbol
7
6
SINT
0
CLD
R
R/W
R/W
5
4
SIC SVAM
3
2
1
0
Address
0
0
0
0
FF63H
CLD
After Reset
00H
R/W Note 1
SCK0 Pin Level Note 2
0
Low level
1
High level
INTCSI0 Interrupt Source Selection Note 3
SIC
0
CSIIF0 is set upon termination of serial interface channel 0 transfer
1
CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer
SVAM
SVA Bit to Be Used as Slave Address
0
Bits 0 to 7
1
Bits 1 to 7
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
3. When using wakeup function in the SBI mode, set SIC to 0.
Caution Be sure to set bits 0 to 3 to 0.
Remark
SVA:
Slave address register
CSIIF0: Interrupt request flag corresponding to INTCSI0
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(4) Various signals
Figures 14-20 to 14-25 show various signal and flag operations in SBI. Table 14-3 lists the signals in SBI.
Figure 14-20. RELT, CMDT, RELD, and CMDD Operations (Master)
Slave Address Write to SIO0
(Transfer Start Instruction)
SIO0
SCK0
SB0 (SB1)
RELT
CMDT
RELD
CMDD
Figure 14-21. RELD and CMDD Operations (Slave)
Write FFH to SIO0
(Transfer Start Instruction)
Transfer Start Instruction
A7
SIO0
A6
SCK0
1
2
SB0 (SB1)
A7
A6
A1
7
A0
8
9
READY
A1
Slave Address
A0
ACK
When Addresses Match
RELD
When Addresses do not Match
CMDD
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Figure 14-22. ACKT Operation
SCK0
SB0 (SB1)
6
7
D2
8
D1
9
D0
ACK
ACKT
If the ACKT is set
during this period
Caution Do not set ACKT before completion of transfer.
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ACK signal is output for
a period of one clock
just after setting
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SERIAL INTERFACE CHANNEL 0
Figure 14-23. ACKE Operations
(a) When ACKE = 1 upon completion of transfer
2
1
SCK0
D7
SB0 (SB1)
7
D6
D2
8
D1
9
D0
ACK signal is output
at 9th clock
ACK
ACKE
When ACKE = 1 at this point
(b) When set after completion of transfer
SCK0
SB0 (SB1)
6
8
7
D2
D1
9
D0
ACK
ACK signal is output for
a period of one clock
just after setting
ACKE
If the ACKE is set during this period and it is
still 1 at the falling edge of the next SCK0
(c) When ACKE = 0 upon completion of transfer
1
SCK0
2
D7
SB0 (SB1)
7
D6
D2
8
D1
9
ACK signal is not output
D0
ACKE
When ACKE = 0 at this point
(d) When “ACKE = 1” period is short
SCK0
SB0 (SB1)
D2
D1
ACK signal is not output
D0
ACKE
If the ACKE is set and then cleared during this
period and it is still 0 at the falling edge of SCK0
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Figure 14-24. ACKD Operations
(a) When ACK signal is output at 9th SCK0 clock
Transfer Start
Instruction
SIO0
Transfer Start
7
6
SCK0
8
D1
D2
SB0 (SB1)
9
D0
ACK
ACKD
(b) When ACK signal is output after 9th SCK0 clock
Transfer Start
Instruction
SIO0
Transfer Start
6
SCK0
7
D2
SB0 (SB1)
8
9
ACK
D0
D1
ACKD
(c) Clear timing when transfer start is instructed in BUSY
Transfer Start
Instruction
SIO0
SCK0
6
7
D2
SB0 (SB1)
8
D1
9
D0
BUSY
ACK
D7
D6
ACKD
Figure 14-25. BSYE Operation
SCK0
SB0 (SB1)
7
6
D2
8
D1
9
D0
ACK
BUSY
BSYE
When BSYE = 1 at this point
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If the BSYE is reset during this period and
it is still 0 at the falling edge of SCK0
Table 14-2. Signals in SBI Mode (1/2)
Signal Name
Bus release
signal
(REL)
Output
Device
Master
Busy signal
(BUSY)
Master
Master/
slave
Slave
SB0 (SB1) falling edge
when SCK0 = 1
CMD signal is output
to indicate that
transmit data is an
address.
• CMDT set
• CMDD set
i) Transmit data is an
address after REL
signal output.
ii) REL signal is not
output and transmit data is an
command.
1 ACKE = 1
2 ACKT set
• ACKD set
Completion of
reception
• RELT set
Low-level signal to be
output to SB0 (SB1) during
one-clock period of SCK0
after completion of serial
reception
[Synchronous BUSY signal]
Low-level signal to be
output to SB0 (SB1)
following Acknowledge
signal
"H"
SB0 (SB1)
[Synchronous BUSY output]
Slave
High-level signal to be
output to SB0 (SB1) before
serial transfer start and
after completion of serial
transfer
—
Serial receive disable
because of processing
—
Serial receive enable
9
SCK0
• BSYE = 1
ACK
SB0 (SB1)
D0
SB0 (SB1)
D0
BUSY
READY
ACK
Ready signal
(READY)
• RELD set
• CMDD clear
"H"
SCK0
Meaning of Signal
BUSY
READY
1 BSYE = 0
2 Execution of
instruction for
data write to
SIO0
(transfer start
instruction)
SERIAL INTERFACE CHANNEL 0
signal
(ACK)
SCK0
Effect on Flag
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User’s Manual U12761EJ2V0UM
Acknowledge
SB0 (SB1) rising edge
when SCK0 = 1
Output
Condition
Timing Chart
SB0 (SB1)
Command
signal
(CMD)
Definition
289
290
Table 14-2. Signals in SBI Mode (2/2)
Signal Name
Serial clock
(SCK0)
Definition
Master
Synchronous clock to
output address/command/
data, ACK signal, synchroSCK0
nous BUSY signal, etc.
Address/command/data are
SB0 (SB1)
transferred with the first
eight synchronous clocks.
Master
8-bit data to be transferred
in synchronization with
SCK0 after output of REL
and CMD signals
1
(C7 to C0)
Data
(D7 to D0)
Master
Master/
slave
8-bit data to be transferred
in synchronization with
SCK0 without output of
REL and CMD signals
7
8
9
10
1
2
7
8
1
2
7
8
1
2
7
8
SB0 (SB1)
CMD
SCK0
SB0 (SB1)
Effect on Flag
Meaning of Signal
Timing of signal
output to serial data
bus
Address value of
When CSIE0 = 1,
slave device on the
execution of
instruction for
CSIIF0 set (rising serial bus
data write to
edge of 9th clock
SIO0 (serial
of SCK0) Note 1
transfer start
instruction) Note 2
Instructions and
messages to the
slave device
CMD
SCK0
SB0 (SB1)
Numeric values to be
processed with slave
or master device
Notes 1. When WUP = 0, CSIIF0 is set at the rising edge of the 9th clock of SCK0.
When WUP = 1, an address is received. Only when the address matches the slave address register (SVA) value, CSIIF0 is set (if the address does not
match the value of SVA, RELD is cleared).
2. In the BUSY state, transfer starts after the READY state is set.
SERIAL INTERFACE CHANNEL 0
Commands
2
SCK0
REL
8-bit data to be transferred
in synchronization with
SCK0 after output of only
CMD signal without REL
signal output
Output
Condition
Timing Chart
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User’s Manual U12761EJ2V0UM
Address
(A7 to A0)
Output
Device
CHAPTER 14
SERIAL INTERFACE CHANNEL 0
(5) Pin configuration
The serial clock pin SCK0 and serial data bus pin SB0 (SB1) have the following configurations.
(a) SCK0 ............ Serial clock I/O pin
1
Master ... CMOS and push-pull output
2
Slave ...... Schmitt input
(b) SB0 (SB1) .... Serial data I/O alternate-function pin
Both master and slave devices have an N-ch open-drain output and a Schmitt input.
Because the serial data bus line has an N-ch open-drain output, an external pull-up resistor is necessary.
Figure 14-26. Pin Configuration
Slave Device
Master Device
(Clock Output)
SCK0
SCK0
Clock Output
Clock Input
Serial Clock
(Clock Input)
AVDD
N-ch Open-Drain
SB0 (SB1)
RL
SB0 (SB1)
N-ch Open-Drain
Serial Data Bus
SO0
AVSS
SO0
AVSS
SI0
SI0
Caution Because the N-ch open-drain output pin must go into a high-impedance state during data
reception, write FFH to serial I/O shift register 0 (SIO0) in advance. The N-ch open-drain
output can go into a high-impedance state at any time during transfer. However, when the
wakeup function specification bit (WUP) = 1, the N-ch open-drain output always goes into
a high-impedance state. Thus, it is not necessary to write FFH to SIO0 before reception.
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(6) Address match detection method
In the SBI mode, the master transmits a slave address to select a specific slave device.
A match of the addresses can be automatically detected by hardware. CSIIF0 is set only when the slave
address transmitted by the master matches the address set to SVA when the wakeup function specification
bit (WUP) = 1.
If bit 5 (SIC) of the interrupt timing specification register (SINT) is set, the wakeup function cannot be used
even if WUP is set (an interrupt request signal is generated when bus release is detected). To use the wakeup function, clear SIC to 0.
Cautions 1. Slave selection/non-selection is detected by a match of the slave address received after
bus release (RELD = 1).
For this match detection, the match interrupt (INTCSI0) of the address to be generated
with WUP = 1 is normally used. Thus, execute selection/non-selection detection by slave
address when WUP = 1.
2. When detecting selection/non-selection without the use of interrupt with WUP = 0, do so
by means of transmission/reception of the command preset by program instead of using
the address match detection method.
(7) Error detection
In the SBI mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination device, that
is, serial I/O shift register 0 (SIO0). Thus, transmit errors can be detected in the following ways.
(a) Method of comparing SIO0 data before and after transmission
In this case, if the two data differ, a transmit error is judged to have occurred.
(b) Method of using the slave address register (SVA)
Transmit data is set to both SIO0 and SVA and transmitted. After termination of transmission, the COI
bit (match signal coming from the address comparator) of serial operating mode register 0 (CSIM0) is
tested. If “1”, normal transmission is judged to have been carried out. If “0”, a transmit error is judged
to have occurred.
(8) Communication operation
In the SBI mode, the master device normally selects one slave device as the communication target from among
two or more devices by outputting an “address” to the serial bus.
After the communication target device has been determined, commands and data are transmitted/received
and serial communication is realized between the master and slave devices.
Figures 14-27 to 14-30 show data communication timing charts.
Shift operations of serial I/O shift register 0 (SIO0) are carried out at the falling edge of the serial clock (SCK0).
Transmit data is latched into the SO0 latch and is output with the MSB set as the start bit from the SB0/P25
or SB1/P26 pin. Receive data input to the SB0 (or SB1) pin at the rising edge of SCK0 is latched into SIO0.
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Figure 14-27. Address Transmission from Master Device to Slave Device (WUP = 1)
Master Device Processing (Transmitter)
Program Processing
CMDT
Set
RELT
Set
CMDT
Set
Write
to SIO0
Interrupt Servicing
(Preparation for the Next Serial Transfer)
Hardware Operation
Serial Transmission
INTCSI0
ACKD
SCK0
Generation
Set
Stop
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Transfer Line
1
SB0 (SB1) Pin
A7
2
A6
3
4
A5
5
A4
A3
6
A2
7
A1
8
9
A0
ACK
READY
BUSY
Address
Slave Device Processing (Receiver)
ACKT
Set
BUSY
INTCSI0
ACK BUSY
BUSY
Generation
Output Output
Clear
Program Processing
Hardware Operation
WUP←0
CMDD CMDD CMDD
Set
Clear
Set
RELD
Set
Serial Reception
(When SVA = SIO0)
Clear
SERIAL INTERFACE CHANNEL 0
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SCK0 Pin
293
294
Figure 14-28. Command Transmission from Master Device to Slave Device
Master Device Processing (Transmitter)
Program Processing
CMDT
Set
Write
to SIO0
Interrupt Servicing
(Preparation for the Next Serial Transfer)
Hardware Operation
Serial Transmission
INTCSI0
ACKD
SCK0
Generation
Set
Stop
CHAPTER 14
Transfer Line
1
SB0 (SB1) Pin
C7
2
C6
3
4
C5
5
C4
C3
6
C2
7
C1
8
9
C0
ACK
BUSY
Command
Slave Device Processing (Receiver)
SIO0
Read
Program Processing
Hardware Operation
CMDD
Set
Serial Reception
Command ACKT
analysis
Set
BUSY
Clear
INTCSI0
ACK BUSY
Generation
Output
Output
BUSY
Clear
READY
SERIAL INTERFACE CHANNEL 0
User’s Manual U12761EJ2V0UM
SCK0 Pin
Figure 14-29. Data Transmission from Master Device to Slave Device
Master Device Processing (Transmitter)
Program Processing
Write
to SIO0
Interrupt Servicing
(Preparation for the Next Serial Transfer)
Hardware Operation
Serial Transmission
INTCSI0
ACKD
SCK0
Generation
Set
Stop
CHAPTER 14
Transfer Line
SB0 (SB1) Pin
1
D7
2
D6
3
4
D5
D4
5
D3
6
D2
7
D1
8
9
D0
ACK
BUSY
Data
Slave Device Processing (Receiver)
SIO0
Read
Program Processing
Hardware Operation
Serial Reception
ACKT
Set
BUSY
Clear
INTCSI0
ACK BUSY
Generation
Output
Output
BUSY
Clear
READY
SERIAL INTERFACE CHANNEL 0
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SCK0 Pin
295
296
Figure 14-30. Data Transmission from Slave Device to Master Device
Master Device Processing (Receiver)
SIO0
Read
FFH Write
to SIO0
Program Processing
SCK0
Hardware Operation
Serial Reception
Stop
ACKT FFH Write
Set
INTCSI0
ACK
Generation
Output
to SIO0
Receive data processing
Serial
Reception
CHAPTER 14
Transfer Line
SB0 (SB1) Pin
1
BUSY
READY
D7
2
D6
3
4
D5
D4
5
D3
6
D2
7
D1
8
9
1
D0
ACK
BUSY
READY
Data
Slave Device processing (Transmitter)
Program Processing
Write
to SIO0
Hardware Operation
BUSY
Clear
Write
to SIO0
Serial Transmission
INTCSI0
ACKD
Generation
Set
BUSY
Output
BUSY
Clear
2
D7
D6
SERIAL INTERFACE CHANNEL 0
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SCK0 Pin
CHAPTER 14
SERIAL INTERFACE CHANNEL 0
(9) Transfer start
Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
• Serial interface channel 0 operation control bit (CSIE0) = 1
• Internal serial clock is stopped or SCK0 is high level after 8-bit serial transfer.
Cautions 1. If CSIE0 is set to 1 after data is written to SIO0, transfer does not start.
2. Because the N-ch open-drain output must go into a high-impedance state during data
reception, write FFH to SIO0 in advance.
However, when the wakeup function specification bit (WUP) = 1, the N-ch open-drain
output always goes into a high-impedance state. Thus, it is not necessary to write FFH
to SIO0 before reception.
3. If data is written to SIO0 when the slave is busy, the data is not lost.
When the busy state is cleared and SB0 (or SB1) input is set to high level (READY),
transfer starts.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
For the pin to be used for data I/O (SB0 or SB1), be sure to carry out the following settings before serial transfer
of the 1st byte after RESET input.
<1> Set the P25 and P26 output latches to 1.
<2> Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1.
<3> Reset the P25 and P26 output latches from 1 to 0.
(10) Judging busy state of slave
When the device is in the master mode, follow the procedure below to judge whether slave device is in the
busy state or not.
<1> Detect acknowledge signal (ACK) or interrupt request signal generation.
<2> Set port mode register PM25 (or PM26) of the SB0/P25 (or SB1/P26) pin to the input mode.
<3> Read out the pin state (when the pin level is high, the READY state is set).
After the detection of the READY state, set the port mode register to 0 and return to the output mode.
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(11) SBI mode cautions
(a) Slave selection/non-selection is detected by match detection of the slave address received after bus
release (RELD = 1).
For this match detection, the match interrupt (INTCSI0) of the address to be generated with WUP = 1
is normally used. Thus, execute selection/non-selection detection by slave address when WUP = 1.
(b) When detecting selection/non-selection without the use of interrupt with WUP = 0, do so by means of
transmission/reception of the command preset by program instead of using the address match detection
method.
(c) In the SBI mode, the BUSY signal is output until the next serial clock (SCK0) falls after a command that
resets the BUSY signal has been issued. If WUP is set to 1 during this period by mistake, the BUSY signal
is not reset. Therefore, be sure to confirm that the SB0 (SB1) pin has gone high after resetting the BUSY
signal, by setting WUP to 1.
(d) For pins that are to be used for data I/O, be sure to carry out the following settings before serial transfer
of the 1st byte after RESET input.
<1> Set the P25 and P26 output latches to 1.
<2> Set bit 0 (RELT) of the serial bus interface control register (SBIC) to 1.
<3> Reset the P25 and P26 output latches from 1 to 0.
(e) The transition of the SB0 (SB1) line from low to high or from high to low when the SCK0 line is high is
recognized as a bus release signal or a command signal, respectively. If the transition timing of the bus
is shifted due to the influence of board capacitance, transmitted data may be judged as a bus release
signal (or a command signal). Exercise care in wiring so that noise is not superimposed on the signal
lines.
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14.4.4 2-wire serial I/O mode operation
The 2-wire serial I/O mode can handle any communication format by program.
Communication is basically carried out with two lines: a serial clock (SCK0) and serial data input/output (SB0 or
SB1).
Figure 14-31. Serial Bus Configuration Example Using 2-Wire Serial I/O Mode
AVDD
AVDD
Master
Slave
SCK0
SCK0
SB0 (SB1)
SB0 (SB1)
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(1) Register setting
The 2-wire serial I/O mode is set with serial operating mode register 0 (CSIM0), the serial bus interface control
register (SBIC), and the interrupt timing specify register (SINT).
(a) Serial operating mode register 0 (CSIM0)
CSIM0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM0 to 00H.
Symbol
7
6
5
CSIM0 CSIE0 COI
R/W
R
R/W
R/W
4
WUP
3
2
1
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIE0
Address
After Reset
FF60H
00H
0
Operation stopped
1
Operation enabled
COI
Note 1
Slave Address Comparison Result Flag Note 2
0
Slave address register (SVA) not equal to serial I/O shift register 0 (SIO0) data
1
Slave address register (SVA) equal to serial I/O shift register 0 (SIO0) data
Wake-up Function Control Note 3
WUP
0
Interrupt request signal generation with each serial transfer in any mode
1
Interrupt request signal generation when the address received after bus release
(when CMDD = RELD = 1) matches the slave address register (SVA) data in SBI mode
CSIM CSIM CSIM
02
Operation
Mode
Start Bit
SIO/SB0/P25
Pin Function
04
03
0
×
3-wire serial I/O mode (see 14.4.2 3-wire serial I/O mode operation)
1
0
SBI mode (see 14.4.3 SBI mode operation)
Note 4 Note 4
0
1
×
×
1
0
0
0
1
2-wire serial
l/O mode
Note 4 Note 4
1
0
0
×
×
0
1
SB1
(N-ch
open-drain I/O)
SB0
(N-ch
open-drain I/O)
P26
(CMOS I/O)
MSB
Serial Interface Channel 0 Clock Selection
CSIM01 CSIM00
0
×
Input clock to SCK0 pin from off-chip
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 0 to 3 of timer clock select register 3 (TCL3)
2. When CSIE0 = 0, COI becomes 0.
3. Be sure to set WUP to 0 in 2-wire serial I/O mode.
4. Can be used freely as port function.
Remark
SO0/SB1/P26
Pin Function
P25
(CMOS I/O)
Notes 1. Bit 6 (COI) is a read-only bit.
×:
Don’t care
PM××: Port mode register
P××:
300
R/W
Serial Interface Channel 0 Operation Control
PM25 P25 PM26 P26 PM27 P27
R/W
R/W
Port output latch
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SCK0/P27
Pin Function
SCK0
(N-ch
open-drain I/O)
CHAPTER 14
SERIAL INTERFACE CHANNEL 0
(b) Serial bus interface control register (SBIC)
SBIC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SBIC to 00H.
Symbol
7
6
5
4
3
2
1
0
SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT
R/W
R/W
Address
After Reset
R/W
FF61H
00H
R/W
CMDT
When CMDT = 1, the SO Iatch is cleared to 0. After SO latch clearance, CMDT is automatically cleared to 0.
It is also cleared to 0 when CSIE0 = 0.
RELT
When RELT = 1, the SO Iatch is set to 1. After SO Iatch setting, RELT is automatically cleared to 0.
It is also cleared to 0 when CSIE0 = 0.
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
(c) Interrupt timing specification register (SINT)
SINT is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears SINT to 00H.
Symbol
7
6
5
4
3
2
1
0
Address
SINT
0
CLD
SIC
SVAM
0
0
0
0
FF63H
R
R/W
CLD
SCK0 Pin Level
0
Low level
1
High level
SIC
After Reset
00H
R/W
R/W Note 1
Note 2
INTCSI0 Interrupt Source Selection
0
CSIIF0 is set upon termination of serial interface channel 0 transfer
1
CSIIF0 is set upon bus release detection or termination of serial interface channel 0 transfer
Notes 1. Bit 6 (CLD) is a read-only bit.
2. When CSIE0 = 0, CLD becomes 0.
Caution Be sure to set bits 0 to 3 to 0.
Remark
CSIIF0: Interrupt request flag corresponding to INTCSI0
CSIE0: Bit 7 of serial operating mode register 0 (CSIM0)
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(2) Communication operation
The 2-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception
is carried out in 1-bit units in synchronization with the serial clock.
Shift operations of serial I/O shift register 0 (SIO0) are carried out in synchronization with the falling edge of
the serial clock (SCK0). The transmit data is held in the SO0 latch and is output from the SB0/P25 (or SB1/
P26) pin on an MSB-first basis. The receive data input from the SB0 (or SB1) pin is latched into SIO0 at the
rising edge of SCK0.
Upon termination of 8-bit transfer, the SIO0 operation stops automatically and the interrupt request flag
(CSIIF0) is set.
Figure 14-32. 2-Wire Serial I/O Mode Timing
SCK0
1
SB0 (SB1)
2
D7
3
D6
4
D5
5
D4
6
D3
7
D2
8
D1
D0
CSIIF0
End of Transfer
Transfer Start at the Falling Edge of SCK0
The SB0 (or SB1) pin specified for the serial data bus is an N-ch open-drain I/O and thus it must be externally
connected via a pull-up resistor. Because this pin must go into a high-impedance state during data reception,
write FFH to SIO0 in advance.
The SB0 (or SB1) pin generates the SO0 latch status and thus the SB0 (or SB1) pin output status can be
manipulated by setting bit 0 (RELT) and bit 1 (CMDT) of the serial bus interface control register (SBIC).
However, do not carry out this manipulation during serial transfer.
Control the SCK0 pin output level in the output mode (internal system clock mode) by manipulating the P27
output latch (refer to 14.4.5 SCK0/P27 pin output manipulation).
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(3) Other signals
Figure 14-33 shows RELT and CMDT operations.
Figure 14-33. RELT and CMDT Operations
SO0 Latch
RELT
CMDT
(4) Transfer start
Serial transfer is started by setting transfer data to serial I/O shift register 0 (SIO0) when the following two
conditions are satisfied.
• Serial interface channel 0 operation control bit (CSIE0) = 1
• Internal serial clock is stopped or SCK0 is at high level after 8-bit serial transfer.
Cautions 1. If CSIE0 is set to 1 after data is written to SIO0, transfer does not start.
2. Because the N-ch open-drain output must go into a high-impedance state during data
reception, write FFH to SIO0 in advance.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF0)
is set.
(5) Error detection
In the 2-wire serial I/O mode, the serial bus SB0 (SB1) status being transmitted is fetched into the destination
device, that is, serial I/O shift register 0 (SIO0). Thus, transmit error can be detected in the following ways.
(a) Method of comparing SIO0 data before and after transmission
In this case, if the two data differ, a transmit error is judged to have occurred.
(b) Method of using the slave address register (SVA)
Transmit data is set to both SIO0 and SVA and is transmitted. After termination of transmission, the COI
bit (match signal coming from the address comparator) of serial operating mode register 0 (CSIM0) is
tested. If “1”, normal transmission is judged to have been carried out. If “0”, a transmit error is judged
to have occurred.
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SERIAL INTERFACE CHANNEL 0
14.4.5 SCK0/P27 pin output manipulation
Because the SCK0/P27 pin incorporates an output latch, static output is also possible by software in addition to
normal serial clock output.
P27 output latch manipulation enables any value of SCK0 to be set by software. (SI0/SB0 and SO0/SB1 pin to
be controlled with the RELT and CMDT bits of the serial bus interface control register (SBIC).)
The SCK0/P27 pin output manipulation procedure is described below.
1
Set serial operating mode register 0 (CSIM0) (SCK0 pin enabled for serial operation in the output mode). Set
SCK0 = 1 with serial transfer suspended.
2
Manipulate the P27 output latch with a bit manipulation instruction.
Figure 14-34. SCK0/P27 Pin Configuration
Manipulated by bit
manipulation instruction
SCK0/P27
To Internal
Circuit
P27 Output
Latch
SCK0 (1 while transfer is stopped)
From Serial Clock
Controller
When CSIE0 = 1
and
CSIM01 and CSIM00 are 1 and 0, or 1 and 1.
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CHAPTER 15 SERIAL INTERFACE CHANNEL 1
15.1 Functions of Serial Interface Channel 1
Serial interface channel 1 employs the following three modes.
• Operation stop mode
• 3-wire serial I/O mode
• 3-wire serial I/O mode with automatic transmit/receive function
(1) Operation stop mode
This mode is used when serial transfer is not carried out to reduce power consumption.
(2) 3-wire serial I/O mode (MSB-/LSB-first switchable)
This mode is used for 8-bit data transfer using three lines, one each for the serial clock (SCK1), serial output
(SO1), and serial input (SI1).
The 3-wire serial I/O mode enables simultaneous transmission/reception and so decreases the data transfer
processing time.
Since the start bit of 8-bit data to undergo serial transfer is switchable between MSB and LSB, connection
is enabled with either start bit device.
The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers that incorporate
a conventional synchronous clocked serial interface such as the 75X/XL, 78K and 17K Series.
(3) 3-wire serial I/O mode with automatic transmit/receive function (MSB-/LSB-first switchable)
This mode has the some functions as the mode in (2) 3-wire serial I/O mode but with an automatic transmit/
receive function added.
The automatic transmit/receive function is used to transmit/receive data with a maximum of 32 bytes. This
function enables the hardware to transmit/receive data to/from the OSD (On Screen Display) device and a
device with built-in display controller/driver independently of the CPU, thus alleviating the software load.
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15.2 Configuration of Serial Interface Channel 1
Serial interface channel 1 consists of the following hardware.
Table 15-1. Configuration of Serial Interface Channel 1
Item
Configuration
Register
Serial I/O shift register 1 (SIO1)
Automatic data transmit/receive address pointer (ADTP)
Control register
Timer clock select register 3 (TCL3)
Serial operating mode register 1 (CSIM1)
Automatic data transmit/receive control register (ADTC)
Automatic data transmit/receive interval specification register (ADTI)
Port mode register 2 (PM2) Note
Note
Refer to Figure 4-5 Block Diagram of P20, P21, P23 to P26 and Figure 4-6 Block Diagram of P22
and P27.
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Figure 15-1. Block Diagram of Serial Interface Channel 1
Internal Bus
Automatic Data
Transmit/Receive
Address Pointer
(ADTP)
Buffer RAM
Internal Bus
Automatic Data
Transmit/Receive Interval
Specify Register (ADTI)
ATE
DIR
DIR
ADTI ADTI ADTI ADTI ADTI ADTI
7
4
3
2
1
0
Serial I/O
Shift Register 1
(SIO1)
SI1/
P20
RE
ARLD ERCE ERR
TRF STRB BUSY BUSY
1
0
PM23
CSIE1 DIR ATE CSIM CSIM
11 10
TRF
ADTI0-ADTI4
Match
PM21
SO1/
P21
Serial Operating
Mode Register 1
(CSIM1)
Automatic Data
Transmit/Receive
Control Register (ADTC)
Selector
P21 Output
Latch
STB/
P23
BUSY/
P24
5-Bit Counter
Handshake
ARLD
Selector
Serial Clock
Counter
SCK1/
P22
INTCSI1
SIOI write
Clear
Selector
Selector
R
Q
TO2
f xx/2 to f xx/2 8
4
S
PM22
TCL TCL TCL TCL
37 36 35 34
P22 Output Latch
Timer Clock
Select Register 3 (TCL3)
Internal Bus
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(1) Serial I/O shift register 1 (SIO1)
This is an 8-bit register used to carry out parallel/serial conversion and serial transmission/reception (shift
operation) in synchronization with the serial clock.
SIO1 is set with an 8-bit memory manipulation instruction.
When the value in bit 7 (CSIE1) of serial operating mode register 1 (CSIM1) is 1, writing data to SIO1 starts
a serial operation.
In transmission, data written to SIO1 is output to the serial output (SO1). In reception, data is read from the
serial input (SI1) to SIO1.
RESET input makes SIO1 undefined.
Caution Do not write data to SIO1 while the automatic transmit/receive function is activated.
(2) Automatic data transmit/receive address pointer (ADTP)
This register stores value of (the number of transmit data bytes – 1) while the automatic transmit/receive
function is activated. As data is transferred/received, it is automatically decremented.
ADTP is set with an 8-bit memory manipulation instruction. The higher 3 bits must be set to 0.
RESET input clears ADTP to 00H.
Caution Do not write data to ADTP while the automatic transmit/receive function is activated.
(3) Serial clock counter
This counter counts the serial clocks to be output and input during transmission/reception to check whether
8-bit data has been transmitted/received.
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15.3 Registers Controlling Serial Interface Channel 1
The following four registers are used to control serial interface channel 1.
•
Timer clock select register 3 (TCL3)
•
Serial operating mode register 1 (CSIM1)
•
Automatic data transmit/receive control register (ADTC)
•
Automatic data transmit/receive interval specification register (ADTI)
(1) Timer clock select register 3 (TCL3)
This register sets the serial clock of serial interface channel 1.
TCL3 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL3 to 88H.
Remark
Besides setting the serial clock of serial interface channel 1, TCL3 sets the serial clock of serial
interface channel 0.
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Figure 15-2. Format of Timer Clock Select Register 3
Symbol
7
6
5
4
3
2
1
0
TCL3 TCL37 TCL36 TCL35 TCL34 TCL33 TCL32 TCL31 TCL30
TCL37 TCL36 TCL35 TCL34
Note
FF43H
After Reset
88H
R/W
R/W
Serial Interface Channel 1 Serial Clock Selection
0
1
1
0
fXX/2 Note
0
1
1
1
fXX/22
(1.0 MHz)
1
0
0
0
fXX/23
(500 kHz)
1
0
0
1
fXX/24
(250 kHz)
1
0
1
0
fXX/25
(125 kHz)
1
0
1
1
fXX/26
(62.5 kHz)
1
1
0
0
fXX/27
(31.3 kHz)
1
1
0
1
fXX/28
(15.6 kHz)
Other than above
Address
Setting prohibited
This can only be set when the main system clock frequency is 5.0 MHz or less.
Caution When rewriting other data to TCL3 , stop the serial transfer operation beforehand.
Remarks 1. fXX:
Main system clock frequency
2. Figures in parentheses apply to operation with fXX = 4.0 MHz
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(2) Serial operating mode register 1 (CSIM1)
This register sets the serial interface channel 1 serial clock, operating mode, operation enable/stop and
automatic transmit/receive operation enable/stop.
CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM1 to 00H.
Figure 15-3. Format of Serial Operation Mode Register 1
Symbol
7
6
CSIM1 CSIE1 DIR
5
4
3
2
ATE
0
0
0
CSIE1 CSIM11 PM20 P20 PM21 P21 PM22 P22
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
×
0
×
×
×
×
0
×
×
1
×
Note 2 Note 2
1
1
×
0
DIR
0
CSIM11 CSIM10
MSB
1
LSB
FF68H
After Reset
00H
1 Operation
Operation Control
Operation
Clear
stopped
R/W
SCK1/P22
Function
Function
Pin Function
P20
(CMOS I/O)
P21
(CMOS I/O)
P22
(CMOS I/O)
Count
operation
SI1 Note 2
(input)
SO1 (CMOS
output)
SCK1
(CMOS
output)
1
SI1 Pin Function
SI1/P20
(Input)
ATE
R/W
SCK1
(Input)
Start Bit
0
Address
Shift Register Serial Clock Counter SI1/P20 Pin SO1/P21 Pin
Operation
enabled
0
0
1
1
SO1 Pin Function
SO1
(CMOS output)
Serial Interface Channel 1 Operating Mode Selection
0
3-wire serial I/O mode
1
3-wire serial I/O mode with automatic transmit/receive function
Serial Interface Channel 1 Clock Selection
CSIM11 CSIM10
0
×
Clock externally input to SCK1 pin Note 3
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3)
Notes 1. Can be used freely as port function.
2. Can be used as P20 (CMOS I/O) when only transmission is performed (clear bit 7 (RE) of ADTC to 0).
3. If the external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY1) and bit 2 (STRB)
of the automatic data transmit/receive control register (ADTC) to 0, 0.
Remark
×:
Don't care
PMXX: Port mode register
PXX:
Port output latch
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(3) Automatic data transmit/receive control register (ADTC)
This register sets automatic receive enable/disable, the operating mode, strobe output enable/disable, busy
input enable/disable, error check enable/disable and displays automatic transmit/receive execution and error
detection.
ADTC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADTC to 00H.
Figure 15-4. Format of Automatic Data Transmit/Receive Control Register
Symbol
ADTC
R/W
7
RE
6
5
4
ARLD ERCE ERR
3
0
Address
After Reset
FF69H
R/W
00H
R/W Note 1
Receive Control of Automatic Transmit/Receive Function
0
Receive disabled
1
Receive enabled
Operating Mode Selection of Automatic Transmit/Receive Function
0
Single operating mode
1
Repetitive operating mode
R/W ERCE
R
1
TRF STRB BUSY1 BUSY0
RE
R/W ARLD
R
2
Error Check Control of Automatic Transmit/Receive Function
0
Error check disabled
1
Error check enabled (only when BUSY1 = 1)
ERR
Error Detection of Automatic Transmit/Receive Function
0
No error (this bit is set to 0 when data is written to SIO1)
1
Error occurred
TRF
Status of Automatic Transmit/Receive Function Note 2
0
Detection of termination of automatic transmission/reception (this bit is set to 0 upon suspension of automatic
transmission/reception or when ARLD = 0)
1
During automatic transmission/reception
(this bit is set to 1 when data is written to SIO1)
R/W STRB
Strobe Output Control
0
Strobe output disable
1
Strobe output enable
R/W BUSY1 BUSY0
Busy Input Control
0
×
Not using busy input
1
0
Busy input enabled (active high)
1
1
Busy input enabled (active low)
Notes 1. Bits 3 and 4 (TRF and ERR) are read-only bits.
2. Judge the termination of automatic transmission and reception by TRF, not by CSIIF1 (interrupt request
flag).
Caution When an external clock input is selected by setting bit 1 (CSIM11) of serial operating mode
register 1 (CSIM1) to 0, set STRB and BUSY1 of ADTC to 0, 0.
Remark
312
×: Don't care
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(4) Automatic data transmit/receive interval specification register (ADTI)
This register sets the automatic data transmit/receive function data transfer interval.
ADTI is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADTI to 00H.
Figure 15-5. Format of Automatic Data Transmit/Receive Interval Specification Register (1/2)
Symbol
7
ADTI ADTI7
6
5
0
0
4
3
2
1
0
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
ADTI7
Address
After Reset
FF6BH
00H
R/W
R/W
Data Transfer Interval Control
0
No control of interval by ADTINote 1
1
Control of interval by ADTI (ADTI0 to ADTI4)
Data Transfer Interval Specification (fXX = 4.0 MHz Operation)
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Minimum Note 2
MaximumNote 2
0
0
0
0
0
23.0 µ s + 0.5/fSCK
25.0 µs + 1.5/fSCK
0
0
0
0
1
39.0 µ s + 0.5/fSCK
41.0 µs + 1.5/fSCK
0
0
0
1
0
55.0 µ s + 0.5/fSCK
57.0 µs + 1.5/fSCK
0
0
0
1
1
71.0 µ s + 0.5/fSCK
73.0 µs + 1.5/fSCK
0
0
1
0
0
87.0 µ s + 0.5/fSCK
89.0 µs + 1.5/fSCK
0
0
1
0
1
103.0 µ s + 0.5/fSCK
105.0 µs + 1.5/fSCK
0
0
1
1
0
119.0 µ s + 0.5/fSCK
121.0 µs + 1.5/fSCK
0
0
1
1
1
135.0 µ s + 0.5/fSCK
137.0 µs + 1.5/fSCK
0
1
0
0
0
151.0 µ s + 0.5/fSCK
153.0 µs + 1.5/fSCK
0
1
0
0
1
167.0 µ s + 0.5/fSCK
169.0 µs + 1.5/fSCK
0
1
0
1
0
183.0 µ s + 0.5/fSCK
185.0 µs + 1.5/fSCK
0
1
0
1
1
199.0 µ s + 0.5/fSCK
201.0 µs + 1.5/fSCK
0
1
1
0
0
215.0 µ s + 0.5/fSCK
217.0 µs + 1.5/fSCK
0
1
1
0
1
231.0 µ s + 0.5/fSCK
233.0 µs + 1.5/fSCK
0
1
1
1
0
247.0 µ s + 0.5/fSCK
249.0 µs + 1.5/fSCK
0
1
1
1
1
263.0 µ s + 0.5/fSCK
265.0 µs + 1.5/fSCK
Notes 1. The interval is dependent only on CPU processing.
2. The data transfer interval includes an error. The data transfer minimum and maximum intervals are
found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if the minimum value
calculated by the following expression is smaller than 2/fSCK, the minimum interval time is 2/fSCK.
Minimum = (n+1) ×
Cautions 1.
26
fXX
+
28
fXX
+ 0.5
fSCK
Maximum = (n+1) ×
26
fXX
+
36 + 1.5
fXX
fSCK
Do not write ADTI during operation of the automatic data transmit/receive function.
2.
Bits 5 and 6 must be set to zero.
3.
If the auto transmit/receive data transmission interval time is controlled using ADTI, busy
control becomes invalid (see 15.4.3 (4) (a) Busy control option).
Remarks 1. fXX:
Main system clock frequency
2. fSCK: Serial clock frequency
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Figure 15-5. Format of Automatic Data Transmit/Receive Interval Specification Register (2/2)
Symbol
7
ADTI ADTI7
6
5
0
0
4
3
2
1
Address
0
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
FF6BH
After Reset
00H
R/W
R/W
Data Transfer Interval Specification (fXX = 4.0 MHz Operation)
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Minimum Note
Maximum Note
1
0
0
0
0
279.0 µs + 0.5/fSCK
281.0 µs + 1.5/fSCK
1
0
0
0
1
295.0 µs + 0.5/fSCK
297.0 µs + 1.5/fSCK
1
0
0
1
0
311.0 µs + 0.5/fSCK
313.0 µs + 1.5/fSCK
1
0
0
1
1
327.0 µs + 0.5/fSCK
329.0 µs + 1.5/fSCK
1
0
1
0
0
343.0 µs + 0.5/fSCK
345.0 µs + 1.5/fSCK
1
0
1
0
1
359.0 µs + 0.5/fSCK
361.0 µs + 1.5/fSCK
1
0
1
1
0
375.0 µs + 0.5/fSCK
377.0 µs + 1.5/fSCK
1
0
1
1
1
391.0 µs + 0.5/fSCK
393.0 µs + 1.5/fSCK
1
1
0
0
0
407.0 µs + 0.5/fSCK
409.0 µs + 1.5/fSCK
1
1
0
0
1
423.0 µs + 0.5/fSCK
425.0 µs + 1.5/fSCK
1
1
0
1
0
439.0 µs + 0.5/fSCK
441.0 µs + 1.5/fSCK
1
1
0
1
1
455.0 µs + 0.5/fSCK
457.0 µs + 1.5/fSCK
1
1
1
0
0
471.0 µs + 0.5/fSCK
473.0 µs + 1.5/fSCK
1
1
1
0
1
487.0 µs + 0.5/fSCK
489.0 µs + 1.5/fSCK
1
1
1
1
0
503.0 µs + 0.5/fSCK
505.0 µs + 1.5/fSCK
1
1
1
1
1
519.0 µs + 0.5/fSCK
521.0 µs + 1.5/fSCK
Note
The data transfer interval includes an error. The data transfer minimum and maximum intervals
are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if the
minimum value calculated by the following expression is smaller than 2/fSCK, the minimum interval
time is 2/fSCK.
Minimum = (n+1) ×
26
fXX
+
28
fXX
+ 0.5
fSCK
Maximum = (n+1) ×
26
fXX
+
36
fXX
+ 1.5
fSCK
Cautions 1. Do not write ADTI during operation of the automatic data transmit/receive function.
2. Bits 5 and 6 must be set to 0.
3. If the auto transmit/receive data transmission interval time is controlled using ADTI,
busy control becomes invalid (see 15.4.3 (4) (a) Busy control option).
Remarks 1. fXX: Main system clock frequency
2. fSCK: Serial clock frequency
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15.4 Operations of Serial Interface Channel 1
The following three operating modes are available for serial interface channel 1.
• Operation stop mode
• 3-wire serial I/O mode
• 3-wire serial I/O mode with automatic transmit/receive function
15.4.1 Operation stop mode
Serial transfer is not carried out in the operation stop mode. Thus, power consumption can be reduced. Serial
I/O shift register 1 (SIO1) does not carry out shift operations either, and thus it can be used as an ordinary 8-bit register.
In the operation stop mode, the P20/SI1, P21/SO1, P22/SCK1, P23/STB and P24/BUSY pins can be used as
ordinary I/O ports.
(1) Register setting
The operation stop mode is set with serial operating mode register 1 (CSIM1).
CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM1 to 00H.
Symbol
7
6
CSIM1 CSIE1 DIR
5
4
3
2
ATE
0
0
0
CSIE1 CSIM11 PM20 P20 PM21 P21 PM22 P22
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
×
×
0
×
×
×
0
×
×
1
×
Note 2 Note 2
1
1
×
0
0
0
CSIM11 CSIM10
Address
FF68H
After Reset
00H
R/W
R/W
Shift Register Serial Clock Counter SI1/P20 Pin SO1/P21 Pin SCK1/P22
1 Operation Operation Control
Function
Function
Pin Function
Operation
stop
Clear
P20
(CMOS I/O)
P21
(CMOS I/O)
P22
(CMOS I/O)
SCK1
(Input)
Operation
enable
0
1
1
Count
operation
SI1Note 2
(Input)
SO1 (CMOS
output)
SCK1
(CMOS
output)
1
Notes 1. Can be used freely as port function.
2. Can be used as P20 (CMOS I/O) when only transmission is performed (clear bit 7 (RE) of the
automatic data transmit/receive control register (ADTC) to 0).
Remark
×:
Don't care
PMXX: Port mode register
PXX:
Port output latch
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15.4.2 3-wire serial I/O mode operation
The 3-wire serial I/O mode is valid for connection of peripheral I/O units and display controllers that incorporate
a conventional synchronous clocked serial interface as is the case with the 75X/XL, 78K, and 17K Series.
Communication is carried out with three lines: a serial clock (SCK1), serial output (SO1), and serial input (SI1).
(1) Register setting
The 3-wire serial I/O mode is set with serial operating mode register 1 (CSIM1).
CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM1 to 00H.
Symbol
7
6
CSIM1 CSIE1 DIR
5
4
3
2
ATE
0
0
0
CSIE1 CSIM11 PM20 P20 PM21 P21 PM22 P22
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
×
×
×
0
×
×
0
×
×
1
×
Note 2 Note 2
1
×
1
0
DIR
MSB
1
LSB
ATE
Address
FF68H
After Reset
00H
R/W
R/W
Shift Register Serial Clock Counter SI1/P20 Pin SO1/P21 Pin SCK1/P22
1 Operation Operation Control
Function
Function
Pin Function
Operation
stop
Clear
P20
(CMOS I/O)
P21
(CMOS I/O)
P22
(CMOS I/O)
SCK1
(Input)
Count
operation
SI1 Note 2
(input)
SO1 (CMOS
output)
SCK1
(CMOS
output)
1
Start Bit
0
0
CSIM11 CSIM10
Operation
enable
0
0
1
1
SI1 Pin Function
SI1/P20
(Input)
SO1 Pin Function
SO1
(CMOS output)
Serial Interface Channel 1 Operating Mode Selection
0
3-wire serial I/O mode
1
3-wire serial I/O mode with automatic transmit/receive function
Notes 1. Can be used freely as port function.
2. Can be used as P20 (CMOS I/O) when only transmission is performed (clear bit 7 (RE) of ADTC to 0).
Remark
×:
Don't care
PMXX: Port mode register
PXX:
316
Port output latch
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Serial Interface Channel 1 Clock Selection
CSIM11 CSIM10
Note
SERIAL INTERFACE CHANNEL 1
0
×
External clock input to SCK1 pin Note
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3)
If external clock input has been selected by setting CSIM11 to 0, set bit 1 (BUSY1) and bit 2 (STRB) of
the automatic data transmit/receive control register (ADTC) to 0, 0.
Remark
×: Don't care
(2) Communication operation
The 3-wire serial I/O mode is used for data transmission/reception in 8-bit units. Data transmission/reception
is carried out in 1-bit units in synchronization with the serial clock.
Shift operations of serial I/O shift register 1 (SIO1) are carried out at the falling edge of the serial clock (SCK1).
The transmitted data is held in the SO1 latch and is output from the SO1 pin. The received data input to the
SI1 pin is latched in SIO1 at the rising edge of SCK1.
Upon termination of 8-bit transfer, SIO1 operation stops automatically and the interrupt request flag (CSIIF1)
is set.
Figure 15-6. Timing in 3-Wire Serial I/O Mode
SCK1
1
2
3
4
5
6
7
8
SI1
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO1
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
CSIIF1
End of Transfer
Transfer Start at Falling Edge of SCK1
SIO1 Write
Caution The SO1 pin becomes low level by SIO1 write.
(3) MSB/LSB start bit switching
In the 3-wire serial I/O mode, transfer can be selected to start from the MSB or LSB.
Figure 15-7 shows the configuration of serial I/O shift register 1 (SIO1) and the internal bus. As shown in the
figure, the MSB/LSB can be read/written in reverse.
MSB/LSB switching as the start bit can be specified with bit 6 (DIR) of serial operating mode register 1 (CSIM1).
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Figure 15-7. Transfer Bit Order Switching Circuit
7
6
Internal Bus
1
0
LSB-first
MSB-first
Read/Write Gate
Read/Write Gate
SO1 Latch
SI1
Serial I/O Shift Register 1 (SIO1)
D
Q
SO1
SCK1
Start-bit switching is realized by switching the bit order for a data write to SIO1. The SIO1 shift order remains
unchanged. Thus, switching between MSB-first and LSB-first must be performed before writing data to the
shift register.
(4) Transfer start
Serial transfer is started by setting transfer data to serial I/O shift register 1 (SIO1) when the following two
conditions are satisfied.
•
Serial interface channel 1 operation control bit (CSIE1) = 1
•
Internal serial clock is stopped or SCK1 is high level after 8-bit serial transfer.
Caution If CSIE1 is set to 1 after data is written to SIO1, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (CSIIF1)
is set.
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15.4.3 3-wire serial I/O mode operation with automatic transmit/receive function
This 3-wire serial I/O mode is used for transmission/reception of a maximum of 32 bytes of data without the use
of software. Once transfer is started, the data prestored in the RAM can be transmitted in the set number of bytes,
and data can be received and stored in the RAM in the set number of bytes.
Handshake signals (STB and BUSY) are supported by hardware to transmit/receive data continuously. An OSD
(On Screen Display) LSI and peripheral LSI including LCD controller/driver can be connected without difficulty.
(1) Register setting
The 3-wire serial I/O mode with automatic transmit/receive function is set with serial operating mode register
1 (CSIM1), the automatic data transmit/receive control register (ADTC) and the automatic data transmit/
receive interval specify register (ADTI).
(a) Serial operating mode register 1 (CSIM1)
CSIM1 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM1 to 00H.
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Symbol
7
6
CSIM1 CSIE1 DIR
5
4
3
2
ATE
0
0
0
CSIE1 CSIM11 PM20 P20 PM21 P21 PM22 P22
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
0
×
×
×
×
×
0
×
×
1
×
Note 2 Note 2
1
1
×
0
1
0
DIR
0
1
0
SERIAL INTERFACE CHANNEL 1
1
0
CSIM11 CSIM10
Address
FF68H
After Reset
00H
R/W
R/W
Shift Register Serial Clock Counter SI1/P20 Pin SO1/P21 Pin
1 Operation
Operation Control
Operation
SCK1/P22
Function
Function
Pin Function
Clear
P20
(CMOS I/O)
P21
(CMOS I/O)
P22
(CMOS I/O)
Operation
Count
enabled
operation
SI1
(input)
stopped
SCK1
(Input)
Note 2
SO1 (CMOS
output)
SCK1
(CMOS
output)
1
Start Bit
SI1 Pin Function
SO1 Pin Function
MSB
SI1/P20
SO1
LSB
(Input)
(CMOS output)
Serial Interface Channel 1 Operating Mode Selection
ATE
0
3-wire serial I/O mode
1
3-wire serial I/O mode with automatic transmit/receive function
Serial Interface Channel 1 Clock Selection
CSIM11 CSIM10
0
×
Clock externally input to SCK1 pin Note 3
1
0
8-bit timer register 2 (TM2) output
1
1
Clock specified with bits 4 to 7 of timer clock select register 3 (TCL3)
Notes 1. Can be used freely as port function.
2. Can be used as P20 (CMOS I/O) when only transmission is performed (clear bit 7 (RE) of ADTC
to 0).
3. If the external clock input has been selected with CSIM11 set to 0, set bit 1 (BUSY 1) and bit
2 (STRB) of the automatic data transmit/receive control register (ADTC) to 0, 0.
Remark
×:
Don't care
PMXX: Port mode register
PXX:
320
Port output latch
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(b) Automatic data transmit/receive control register (ADTC)
ADTC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADTC to 00H.
Symbol
7
ADTC
RE
R/W
6
5
4
ARLD ERCE ERR
3
0
Address
After Reset
FF69H
R/W
00H
R/W Note 1
Receive Control of Automatic Transmit/Receive Function
0
Receive disabled
1
Receive enabled
R/W ARLD
Operating Mode Selection of Automatic Transmit/Receive Function
0
Single operating mode
1
Repetitive operating mode
R/W ERCE
Error Check Control of Automatic Transmit/Receive Function
0
Error check disabled
1
Error check enabled (only when BUSY1 = 1)
ERR
R
1
TRF STRB BUSY1 BUSY0
RE
R
2
Error Detection of Automatic Transmit/Receive Function
0
No error (this bit is set to 0 when data is written to SIO1)
1
Error occurred
TRF
Status of Automatic Transmit/Receive Function Note 2
0
Detection of termination of automatic transmission/reception (this bit is set to 0 upon suspension of automatic
transmission/reception or when ARLD = 0)
1
During automatic transmission/reception
(this bit is set to 1 when data is written to SIO1)
R/W STRB
Strobe Output Control
0
Strobe output disabled
1
Strobe output enabled
R/W BUSY1 BUSY0
Busy Input Control
0
×
Not using busy input
1
0
Busy input enabled (active high)
1
1
Busy input enabled (active low)
Notes 1. Bits 3 and 4 (TRF and ERR) are read-only bits.
2. Judge the termination of automatic transmit and receive by TRF, not by CSIIF1 (interrupt request flag).
Caution When external clock input is selected by setting bit 1 (CSIM11) of serial operating mode register
1 (CSIM1) to 0, set STRB and BUSY1 of ADTC to 0, 0. Handshake control cannot be executed
when an external clock is input.
Remark
×: Don't care
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(c) Automatic data transmit/receive interval specification register (ADTI)
This register sets the automatic data transmit/receive function data transfer interval.
ADTI is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ADTI to 00H.
Symbol
7
ADTI ADTI7
6
5
0
0
4
3
2
1
0
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
ADTI7
Address
After Reset
FF6BH
00H
R/W
R/W
Data Transfer Interval Control
0
No control of interval by ADTI
1
Control of interval by ADTI (ADTI0 to ADTI4)
Note 1
Data Transfer Interval Specification (fXX = 4.0 MHz Operation)
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
MaximumNote 2
Minimum Note 2
0
0
0
0
0
23.0 µ s + 0.5/fSCK
25.0 µs + 1.5/fSCK
0
0
0
0
1
39.0 µ s + 0.5/fSCK
41.0 µs + 1.5/fSCK
0
0
0
1
0
55.0 µ s + 0.5/fSCK
57.0 µs + 1.5/fSCK
0
0
0
1
1
71.0 µ s + 0.5/fSCK
73.0 µs + 1.5/fSCK
0
0
1
0
0
87.0 µ s + 0.5/fSCK
89.0 µs + 1.5/fSCK
0
0
1
0
1
103.0 µ s + 0.5/fSCK
105.0 µs + 1.5/fSCK
0
0
1
1
0
119.0 µ s + 0.5/fSCK
121.0 µs + 1.5/fSCK
0
0
1
1
1
135.0 µ s + 0.5/fSCK
137.0 µs + 1.5/fSCK
0
1
0
0
0
151.0 µ s + 0.5/fSCK
153.0 µs + 1.5/fSCK
0
1
0
0
1
167.0 µ s + 0.5/fSCK
169.0 µs + 1.5/fSCK
0
1
0
1
0
183.0 µ s + 0.5/fSCK
185.0 µs + 1.5/fSCK
0
1
0
1
1
199.0 µ s + 0.5/fSCK
201.0 µs + 1.5/fSCK
0
1
1
0
0
215.0 µ s + 0.5/fSCK
217.0 µs + 1.5/fSCK
0
1
1
0
1
231.0 µ s + 0.5/fSCK
233.0 µs + 1.5/fSCK
0
1
1
1
0
247.0 µ s + 0.5/fSCK
249.0 µs + 1.5/fSCK
0
1
1
1
1
263.0 µ s + 0.5/fSCK
265.0 µs + 1.5/fSCK
Notes 1. The interval is dependent only on CPU processing.
2. The data transfer interval includes an error. The data transfer minimum and maximum
intervals are found from the following expressions (n: Value set in ADTI0 to ADTI4).
However, if the minimum value calculated by the following expression is smaller than 2/
fSCK, the minimum interval time is 2/fSCK.
Minimum = (n+1) ×
26
fXX
+ 28
fXX
+ 0.5
fSCK
Maximum = (n+1) ×
26 + 36
fXX
fXX
+ 1.5
fSCK
Cautions 1. Do not write ADTI during operation of the automatic data transmit/receive function.
2. Bits 5 and 6 must be set to 0.
3. If the auto transmit/receive data transmission interval time is controlled using ADTI,
busy control becomes invalid (see 15.4.3 (4) (a) Busy control option).
Remarks 1. fXX: Main system clock frequency
2. fSCK: Serial clock frequency
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Symbol
7
ADTI ADTI7
6
5
0
0
4
3
2
SERIAL INTERFACE CHANNEL 1
1
Address
0
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
FF6BH
After Reset
00H
R/W
R/W
Data Transfer Interval Specification (fXX = 4.0 MHz Operation)
ADTI4 ADTI3 ADTI2 ADTI1 ADTI0
Minimum Note
Maximum Note
1
0
0
0
0
279.0 µs + 0.5/fSCK
281.0 µs + 1.5/fSCK
1
0
0
0
1
295.0 µs + 0.5/fSCK
297.0 µs + 1.5/fSCK
1
0
0
1
0
311.0 µs + 0.5/fSCK
313.0 µs + 1.5/fSCK
1
0
0
1
1
327.0 µs + 0.5/fSCK
329.0 µs + 1.5/fSCK
1
0
1
0
0
343.0 µs + 0.5/fSCK
345.0 µs + 1.5/fSCK
1
0
1
0
1
359.0 µs + 0.5/fSCK
361.0 µs + 1.5/fSCK
1
0
1
1
0
375.0 µs + 0.5/fSCK
377.0 µs + 1.5/fSCK
1
0
1
1
1
391.0 µs + 0.5/fSCK
393.0 µs + 1.5/fSCK
1
1
0
0
0
407.0 µs + 0.5/fSCK
409.0 µs + 1.5/fSCK
1
1
0
0
1
423.0 µs + 0.5/fSCK
425.0 µs + 1.5/fSCK
1
1
0
1
0
439.0 µs + 0.5/fSCK
441.0 µs + 1.5/fSCK
1
1
0
1
1
455.0 µs + 0.5/fSCK
457.0 µs + 1.5/fSCK
1
1
1
0
0
471.0 µs + 0.5/fSCK
473.0 µs + 1.5/fSCK
1
1
1
0
1
487.0 µs + 0.5/fSCK
489.0 µs + 1.5/fSCK
1
1
1
1
0
503.0 µs + 0.5/fSCK
505.0 µs + 1.5/fSCK
1
1
1
1
1
519.0 µs + 0.5/fSCK
521.0 µs + 1.5/fSCK
Note
The data transfer interval includes an error. The data transfer minimum and maximum intervals
are found from the following expressions (n: Value set in ADTI0 to ADTI4). However, if the
minimum value calculated by the following expression is smaller than 2/fSCK, the minimum interval
time is 2/fSCK.
Minimum = (n+1) ×
26
fXX
+ 28
fXX
+ 0.5
fSCK
Maximum = (n+1) ×
26
fXX
+ 36
fXX
+ 1.5
fSCK
Cautions 1. Do not write ADTI during operation of the automatic data transmit/receive function.
2. Bits 5 and 6 must be set to zero.
3. If the auto transmit/receive data transmission interval time is controlled using ADTI,
busy control becomes invalid (see 15.4.3 (4) (a) Busy control option).
Remarks 1. fXX: Main system clock frequency
2. fSCK: Serial clock frequency
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(2) Automatic transmit/receive data setting
(a) Transmit data setting
<1>
Write transmit data from the least significant address of buffer RAM, FAC0H, (up to FADFH (max.)).
The transmit data should be in order from higher address to lower address.
<2>
Set the automatic data transmit/receive address pointer (ADTP) to the value obtained by
subtracting 1 from the number of transmit data bytes.
(b) Automatic transmit/receive mode setting
<1>
Set CSIE1 and ATE of serial operating mode register 1 (CSIM1) to 1.
<2>
Set RE of the automatic data transmit/receive control register (ADTC) to 1.
<3>
Set a data transmit/receive interval in the automatic data transmit/receive interval specify register
(ADTI).
<4>
Write any value to the serial I/O shift register 1 (SIO1) (transfer start trigger).
Caution Writing any value to SIO1 orders the start of an automatic transmit/receive operation;
the written value has no meaning.
The following operations are automatically carried out when (a) and (b) are carried out.
• After the buffer RAM data specified with ADTP is transferred to SIO1, transmission is carried
out (start of automatic transmission/reception).
• The received data is written to the buffer RAM address specified with ADTP.
• ADTP is decremented and the next data transmission/reception is carried out.
Data
transmission/reception continues until the ADTP decremented output becomes 00H and
data at address FAC0H is output (end of automatic transmission/reception).
• When automatic transmission/reception is terminated, TRF is cleared to 0.
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(3) Communication operation
(a) Basic transmission/reception mode
This transmission/reception mode is the same as the 3-wire serial I/O mode in which a specified number
of data are transmitted/received in 8-bit units.
Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7
(CSIE1) of serial operation mode register 1 (CSIM1) is set to 1.
When the final byte has been sent, an interrupt request flag (CSIIF1) is set. However, judge the termination
of automatic transmit/recieve, not by CSIIF1 (interrupt request flag) but by bit 3 (TRF) of the automatic
data transmit/receive control register (ADTC).
If busy control and strobe control are not executed, the P23/STB and P24/BUSY pins can be used as
normal I/O ports.
Figure 15-8 shows the basic transmission/reception mode operation timing, and Figure 15-9 shows the
operation flowchart. Figure 15-10 shows the operation of the buffer RAM when 6 bytes of data are
transmitted or received.
Figure 15-8. Timing in Basic Transmission/Reception Mode Operation
Interval
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSIIF1
TRF
Cautions 1. Because, in the basic transmission/reception mode, the automatic transmit/receive
function writes/reads data to/from the buffer RAM after 1-byte transmission/reception, an interval is inserted until the next transmission/reception. As the buffer RAM
write/read is performed at the same time as CPU processing, the maximum interval
is dependent upon CPU processing and the value of the automatic data transmit/
receive interval specification register (ADTI) (see (5) "Automatic data transmit/
receive interval").
2. When TRF is cleared, the SO1 pin becomes low level.
Remark
CSIIF1: Interrupt request flag
TRF:
Bit 3 of automatic data transmit/receive control register (ADTC)
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Figure 15-9. Basic Transmission/Reception Mode Flowchart
Start
Write transmit data
in buffer RAM
Set ADTP to the value (pointer
value) obtained by subtracting 1
from the number of transmit
data bytes
Software Execution
Set the transmission/reception
operation interval time in ADTI
Write any data to SIO1
(Start trigger)
Write transmit data from
buffer RAM to SIO1
Transmission/reception
operation
Decrement pointer value
Hardware Execution
Write receive data from
SIO1 to buffer RAM
Pointer value = 0
No
Yes
TRF = 0
No
Software Execution
Yes
End
ADTP: Automatic data transmit/receive address pointer
326
ADTI:
Automatic data transmit/receive interval specify register
SIO1:
Serial I/O shift register 1
TRF:
Bit 3 of automatic data transmit/receive control register (ADTC)
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In 6-byte transmission/reception (ARLD = 0, RE = 1) in the basic transmit/receive mode, buffer RAM operates as
follows.
(i)
Before transmission/reception (see Figure 15-10 (a))
After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not
transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission
of the first byte is completed, receive data 1 (R1) is transferred from SIO1 to the buffer RAM, and
the automatic data transmit/receive address pointer (ADTP) is decremented. Then transmit data 2
(T2) is transferred from the buffer RAM to SIO1.
(ii) 4th byte transmission/reception point (see Figure 15-10 (b))
Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred from
the buffer RAM to SIO1. When transmission of the fourth byte is completed, receive data 4 (R4) is
transferred from SIO1 to the buffer RAM, and ADTP is decremented.
(iii) Completion of transmission/reception (see Figure 15-10 (c))
When transmission of the sixth byte is completed, receive data 6 (R6) is transferred from SIO1 to
the buffer RAM, and the interrupt request flag (CSIIF1) is set (INTCSI1 generation).
Figure 15-10. Buffer RAM Operation in 6-Byte Transmission/Reception
(in Basic Transmission/Reception Mode) (1/2)
(a) Before transmission/reception
FADFH
FAC5H
Transmit data 1 (T1)
Receive data 1 (R1)
SIO1
5
ADTP
0
CSIIF1
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
–1
Transmit data 5 (T5)
FAC0H
Transmit data 6 (T6)
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Figure 15-10. Buffer RAM Operation in 6-Byte Transmission/Reception
(in Basic Transmission/Reception Mode) (2/2)
(b) 4th byte transmission/reception
FADFH
FAC5H
Receive data 1 (R1)
Receive data 4 (R4)
SIO1
2
ADTP
0
CSIIF1
Receive data 2 (R2)
Receive data 3 (R3)
Transmit data 4 (T4)
–1
Transmit data 5 (T5)
FAC0H
Transmit data 6 (T6)
(c) Completion of transmission/reception
FADFH
FAC5H
Receive data 1 (R1)
SIO1
Receive data 2 (R2)
Receive data 3 (R3)
0
ADTP
1
CSIIF1
Receive data 4 (R4)
Receive data 5 (R5)
FAC0H
328
Receive data 6 (R6)
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(b) Basic transmission mode
In this mode, 8-bit unit data is transmitted the specified number of times.
Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7
(CSIE1) of serial operation mode register 1 (CSIM1) is set to 1.
When the final byte has been sent, an interrupt request flag (CSIIF1) is set. However, judge the termination
of automatic transmit/receive by bit 3 (TRF) of the automatic data transmit/receive control register (ADTC),
not by CSIIF1 (interrupt request flag).
If a receive operation, busy control and strobe control are not executed, the P20/SI1, P23/STB and P24/
BUSY pins can be used as normal I/O ports.
Figure 15-11 shows the basic transmission mode operation timing, and Figure 15-12 shows the operation
flowchart. Figure 15-13 shows the operation of the buffer RAM when 6 bytes of data are transmitted or
received.
Figure 15-11. Basic Transmission Mode Operation Timing
Interval
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSIIF1
TRF
Cautions 1. Because, in the basic transmission mode, the automatic transmit/receive function
reads data from the buffer RAM after 1-byte transmission, an interval is inserted until
the next transmission. As the buffer RAM read is performed at the same time as CPU
processing, the maximum interval is dependent upon CPU processing and the value
of the automatic data transmit/receive interval specification register (ADTI) (see (5)
"Automatic data transmit/receive interval").
2. When TRF is cleared, the SO1 pin becomes low level.
Remark
CSIIF1: Interrupt request flag
TRF:
Bit 3 of the automatic data transmit/receive control register (ADTC)
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Figure 15-12. Basic Transmission Mode Flowchart
Start
Write transmit data
in buffer RAM
Set ADTP to the value (pointer
value) obtained by subtracting 1
from the number of transmit
data bytes
Software Execution
Set the transmission/reception
operation interval time in ADTI
Write any data to SIO1
(Start trigger)
Write transmit data from
buffer RAM to SIO1
Decrement pointer value
Transmission operation
Hardware Execution
Pointer value = 0
No
Yes
TRF = 0
No
Software Execution
Yes
End
ADTP: Automatic data transmit/receive address pointer
330
ADTI:
Automatic data transmit/receive interval specify register
SIO1:
Serial I/O shift register 1
TRF:
Bit 3 of automatic data transmit/receive control register (ADTC)
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In 6-byte transmission (ARLD = 0, RE = 0) in basic transmit mode, buffer RAM operates as follows.
(i)
Before transmission (see Figure 15-13 (a))
After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not
transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission
of the first byte is completed, the automatic data transmit/receive address pointer (ADTP) is
decremented. Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1.
(ii) 4th byte transmission point (see Figure 15-13 (b))
Transmission of the third byte is completed, and transmit data 4 (T4) is transferred from the buffer
RAM to SIO1. When transmission of the fourth byte is completed, ADTP is decremented.
(iii) Completion of transmission (see Figure 15-13 (c))
When transmission of the sixth byte is completed, the interrupt request flag (CSIIF1) is set (INTCSI1
generation).
Figure 15-13. Buffer RAM Operation in 6-Byte Transmission
(in Basic Transmission Mode) (1/2)
(a) Before transmission
FADFH
FAC5H
Transmit data 1 (T1)
SIO1
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
5
ADTP
0
CSIIF1
–1
Transmit data 5 (T5)
FAC0H
Transmit data 6 (T6)
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Figure 15-13. Buffer RAM Operation in 6-Byte Transmission
(in Basic Transmission Mode) (2/2)
(b) 4th byte transmission point
FADFH
FAC5H
Transmit data 1 (T1)
SIO1
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
2
ADTP
0
CSIIF1
–1
Transmit data 5 (T5)
FAC0H
Transmit data 6 (T6)
(c) Completion of transmission
FADFH
FAC5H
Transmit data 1 (T1)
SIO1
Transmit data 2 (T2)
Transmit data 3 (T3)
0
ADTP
1
CSIIF1
Transmit data 4 (T4)
Transmit data 5 (T5)
FAC0H
332
Transmit data 6 (T6)
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(c) Repeat transmission mode
In this mode, data stored in the buffer RAM is transmitted repeatedly.
Serial transmission is started by writing the desired data to serial I/O shift register 1 (SIO1) when bit 7
(CSIE1) of serial operation mode register 1 (CSIM1) is set to 1.
Unlike the case of the basic transmission mode, an interrupt request flag (CSIIF1) is not set after sending
the final byte (FAC0H address data), but the automatic data transmit/receive address pointer (ADTP) is
reset to the value it was at when transmission was started and the contents of the buffer RAM are resent.
If a reception operation, busy control and strobe control are not performed, the P20/SI1, P23/STB and
P24/BUSY pins can be used as ordinary I/O ports.
The repeat transmission mode operation timing is shown in Figure 15-14, and the operation flowchart in
Figure 15-15. Figure 15-16 shows the operation of the buffer RAM when 6 bytes of data are transmitted
in the repeat transmission mode.
Figure 15-14. Repeat Transmission Mode Operation Timing
Interval
Interval
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5
Caution Since, in the repeat transmission mode, a read is performed on the buffer RAM after the
transmission of one byte, the interval is included in the period up to the next transmission.
As the buffer RAM read is performed at the same time as CPU processing, the maximum
interval is dependent upon the CPU operation and the value of the automatic data
transmit/receive interval specify register (ADTI) (see (5) "Automatic data transmit/
receive interval").
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Figure 15-15. Repeat Transmission Mode Flowchart
Start
Write transmit data
in buffer RAM
Set ADTP to the value (pointer
value) obtained by subtracting 1
from the number of transmit
data bytes
Software Execution
Set the transmission/reception
operation interval time in ADTI
Write any data to SIO1
(Start trigger)
Write transmit data from
buffer RAM to SIO1
Decrement pointer value
Transmission operation
Hardware Execution
Pointer value = 0
No
Yes
Reset ADTP
ADTP: Automatic data transmit/receive address pointer
334
ADTI:
Automatic data transmit/receive interval specify register
SIO1:
Serial I/O shift register 1
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In 6-byte transmission (ARLD = 1, RE = 0) in repeat transmit mode, buffer RAM operates as follows.
(i)
Before transmission (See Figure 15-16 (a))
After any data has been written to serial I/O shift register 1 (SIO1) (start trigger: this data is not
transferred), transmit data 1 (T1) is transferred from the buffer RAM to SIO1. When transmission
of the first byte is completed, the automatic data transmit/receive address pointer (ADTP) is
decremented. Then transmit data 2 (T2) is transferred from the buffer RAM to SIO1.
(ii) Upon completion of transmission of 6 bytes (See Figure 15-16 (b))
Even when transmission of the 6th byte is completed, the interrupt request flag (CSIIF1) is not set.
The initial pointer value is reset in ADTP.
(iii) 7th byte transmission point (See Figure 15-16 (c))
Transmit data 1 (T1) is transferred from the buffer RAM to SIO1 again. When transmission of the
first byte is completed, ADTP is decremented. Then transmit data 2 (T2) is transferred from the buffer
RAM to SIO1.
Figure 15-16. Buffer RAM Operation in 6-Byte Transmission
(in Repeat Transmission Mode) (1/2)
(a) Before transmission
FADFH
FAC5H
Transmit data 1 (T1)
SIO1
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
5
ADTP
0
CSIIF1
–1
Transmit data 5 (T5)
FAC0H
Transmit data 6 (T6)
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Figure 15-16. Buffer RAM Operation in 6-Byte Transmission
(in Repeat Transmission Mode) (2/2)
(b) Upon completion of transmission of 6 bytes
FADFH
FAC5H
Transmit data 1 (T1)
SIO1
Transmit data 2 (T2)
Transmit data 3 (T3)
0
ADTP
0
CSIIF1
Transmit data 4 (T4)
Transmit data 5 (T5)
FAC0H
Transmit data 6 (T6)
(c) 7th byte transmission point
FADFH
FAC5H
Transmit data 1 (T1)
SIO1
Transmit data 2 (T2)
Transmit data 3 (T3)
Transmit data 4 (T4)
5
ADTP
0
CSIIF1
–1
Transmit data 5 (T5)
FAC0H
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Transmit data 6 (T6)
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(d) Automatic transmission/reception suspension and restart
Automatic transmission/reception can be temporarily suspended by setting bit 7 (CSIE1) of serial
operating mode register 1 (CSIM1) to 0.
Note, however, that transmission/reception is suspended upon completion of 8-bit data transfer, not in
the middle.
When suspended, bit 3 (TRF) of the automatic data transmit/receive control register (ADTC) is set to 0
after transfer of the 8th bit, and all the port pins functioning alternately as the serial interface pins (P20/
SI1, P21/SO1, P22/SCK1, P23/STB and P24/BUSY) are set to the port mode.
To restart automatic transmit/receive, set CSIE1 to 1 and write the desired value in serial I/O shift register
1 (SIO1). The remaining data can be transmitted in this way.
Cautions 1. If the HALT instruction is executed during automatic transmission/reception, transfer
is suspended and the HALT mode is set even if 8-bit data transfer is not complete.
When the HALT mode is cleared, automatic transmission/reception is restarted from
the point it was suspended.
2. When suspending automatic transmission/reception, do not change the operating
mode to 3-wire serial I/O mode while TRF = 1.
Figure 15-17. Automatic Transmission/Reception Suspension and Restart
CSIE1 = 0 (Suspended Command)
Suspend
Restart Command
CSIE1 = 1, Write to SIO1
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSIE1: Bit 7 of serial operation mode register 1 (CSIM1)
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(4) Synchronization Control
Busy control and strobe control are functions for synchronizing transmission and reception between the master
device and slave device.
By using these functions, it is possible to detect bit slippage during transmission and reception.
(a) Busy control option
Busy control is a function by which serial transmission by the master device is made to wait due to the
output of a busy signal from the slave device to the master device, which then maintains the wait state
while that busy signal is active.
The conditions shown below are necessary to use the busy control option.
• Bit 5 (ATE) of serial operation mode register 1 (CSIM1) is set at (1).
• Bit 1 (BUSY1) of the automatic data transmit/receive control register (ADTC) is set (1).
The system configuration between the master device and slave device in cases where the busy control
option is used is shown in Figure 15-18.
Figure 15-18. System Configuration When Busy Control Option Is Used
Master Device
(µPD78098B Subseries)
SCK1
SO1
SI1
Slave Device
SCK1
SO1
SI1
BUSY
The master device inputs the busy signal output by the slave device to the BUSY/P24 pin. The master
device samples the input busy signal in synchronization with the fall of the serial clock. Even if the busy
signal becomes active during transmission or reception of 8 bit data, the wait does not apply. If the busy
signal becomes active at the rise of the serial clock 2 clock cycles after transmission or reception of 8
bit data ends, the busy input first becomes effective at that point, and thereafter, transmission or reception
of data waits during the period that the busy signal is active.
The busy signal’s active level is set by bit 0 (BUSY0) of ADTC.
BUSY0 = 0: Active high
BUSY0 = 1: Active low
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Note that when using the busy control option, the internal clock must be selected for the serial clock. The
busy signal cannot be controlled with an external clock.
The operation timing when the busy control option is used is shown in Figure 15-19.
Caution Busy control cannot be used at the same time as interval timing control using the
automatic data transmit/receive interval instruction register (ADIT). If both are used
simultaneously, busy control becomes invalid.
Figure 15-19. Operation Timing When Using Busy Control Option (BUSY0 = 0)
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
BUSY
Wait
CSIIF1
Busy Input Clear
Busy Input Valid
TRF
Caution When TRF is cleared, the SO1 pin becomes low level.
Remark
CSIIF1: Interrupt request flag
TRF:
Bit 3 of the automatic data transmit/receive control register (ADTC)
If the busy signal becomes inactive, the wait is canceled. If the sampled busy signal is inactive,
transmission or reception of the next 8 bit data begins from the fall of the next serial clock cycle.
Furthermore, the busy signal is asynchronous with the serial clock, so even if the slave side inactivates
the busy signal, it takes nearly 1 clock cycle at the most until it is sampled again. Also, it takes another
0.5 clock cycles after sampling until data transmission resumes.
Therefore, in order to definitely cancel a wait state, it is necessary for the slave side to keep the busy
signal inactive for at least 1.5 clock cycles.
Figure 15-20 shows the timing of the busy signal and wait cancel. In this figure, an example of a case
where the busy signal becomes active when transmission or reception starts is shown.
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Figure 15-20. Busy Signal and Wait Cancel (When BUSY0 = 0)
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
BUSY
(Active High)
1.5 clocks (min.)
In the case where the busy
signal becomes inactive
directly when sampled
Wait
BUSY Input Cancel
BUSY Input Effective
(b) Busy & strobe control option
Strobe control is a function for synchronizing the transmission and reception of data between a master
device and slave device. When transmission or reception of 8 bit data ends, the strobe signal is output
by the master device from the STB/P23 pin. In this way, the slave device can know the timing of the end
of data transmission of the master device. Therefore, even if there is noise in the serial clock and bit
slippage occurs, synchronization is maintained and bit slippage has no effect on transmission of the next
byte.
The conditions shown below are necessary to use the strobe control option.
• Bit 5 (ATE) of serial operation mode register 1 (CSIM1) is set (1).
• Bit 2 (STRB) of the automatic data transmit/receive control register (ADTC) is set (1).
Normally, busy control and strobe control are used simultaneously as handshake signals. In this case,
together with output of the strobe signal from the STB/P23 pin, the BUSY/P24 pin can be sampled and
transmission or reception can wait while the busy signal is being input.
If strobe control is not carried out, the P23/STB pin can be used as a normal I/O port.
The operation timing when busy and strobe control are used is shown in Figure 15-21.
Furthermore, if strobe control is used, the interrupt request flag (CSIIF1), set when transmission or
reception ends, is set after the strobe signal is output.
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Figure 15-21. Operation Timing When Using Busy & Strobe Control Option (BUSY0 = 0)
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
STB
BUSY
CSIIF1
Busy Input Clear
Busy Input Valid
TRF
Caution When TRF is cleared, the SO1 pin becomes low level.
Remark
CSIIF1: Interrupt request flag
TRF:
Bit 3 of the automatic data transmit/receive control register (ADTC)
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(c) Bit slippage detection function using busy signal
During an automatic transmit/receive operation, noise occurs in the serial clock signal output by the master
device and bit slippage may occur in the serial clock on the slave device side. At this time, if the strobe
control option is not used, this bit slippage will have an effect on transmission of the next byte. In such
cases, the busy control option can be used on the master device side and, by checking the busy signal
during transmission, bit slippage can be detected.
Bit slippage detection using the busy signal is accomplished as follows.
The slave side outputs a busy signal after the serial clock rises on the 8th cycle of data transmission or
reception (at this time, if application of the wait state by the busy signal is not desired, the busy signal
is made inactive within 2 clock cycles).
The master device side samples the busy signal in synchronization with the fall of the serial clock. If no
bit slippage has occurred, the busy signal will be inactive in the sampling of 8 clock cycles. If the busy
signal is found to be active in sampling, it is regarded as an occurrence of bit slippage and error processing
is executed (bit 4 (ERR) of the automatic data transmit/receive control register (ADTC) is set (1)).
The operation timing of the bit slippage detection function using the busy signal is shown in Figure 1522.
Figure 15-22. Operation Timing of Bit Slippage Detection Function Using Busy Signal
(When BUSY0 = 1)
SCK1
(Master Side)
Bit Slippage Due to Noise
SCK1
(Slave Side)
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7
D7 D6 D5 D4 D3 D2 D1
D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7
D7 D6 D5 D4 D3 D2 D1
D0
BUSY
CSIIF1
CSIE1
ERR
No Busy Detection
CSIIF1: Interrupt request flag
CSIE1: Bit 7 of serial operation mode register 1 (CSIM1)
ERR:
342
Bit 4 of the automatic data transmit/receive control register (ADTC)
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Request Generation
Error Detection
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(5) Automatic transmit/receive interval time
When using the automatic transmit/receive function, the read/write operations from/to the buffer RAM are
performed after transmitting/receiving one byte. Therefore, an interval is inserted before the next transmit/
receive.
Since the read/write operations from/to the buffer RAM are performed in parallel with the CPU processing when
using the automatic transmit/receive function by the internal clock, the interval depends on the value set in
the automatic transmit/receive interval specification register (ADTI) and the CPU processing at the rising edge
of the eighth serial clock. Whether it depends on the ADTI or not can be selected by setting of bit 7 (ADTI7)
of AOTI. When it is set to 0, the interval depends only on the CPU processing. When it is set to 1, the interval
depends on the contents of the ADTI or CPU processing, whichever is greater.
When the automatic transmit/receive function is used by an external clock, it must be selected so that the
interval is longer than the value indicated by paragraph (b).
Figure 15-23. Automatic Data Transmit/Receive Interval
Interval
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SI1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
CSIIF1
CSIIF1: Interrupt request flag
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(a) When the automatic transmit/receive function is used by the internal clock
If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is set (1), the internal clock operates.
If the automatic transmit/receive function is operated by the internal clock, the interval timing by CPU
processing is as follows.
When bit 7 (ADTI7) of the automatic data transmit/receive interval specification register (ADTI) is set to
0, the interval depends on the CPU processing. When ADTI7 is set to 1, it depends on the contents of
the ADTI or CPU processing, whichever is greater.
Refer to Figure 15-5, “Format of Automatic Data Transmit/Receive Interval Specification Register” for the
intervals set by ADTI.
Table 15-2. Interval Timing Through CPU Processing (When Internal Clock Is Operating)
CPU Processing
Interval Time
When using multiplication instruction
Max. (2.5TSCK, 13TCPU)
When using division instruction
Max. (2.5TSCK, 20TCPU)
External access 1 wait mode
Max. (2.5TSCK, 9TCPU)
Other than above
Max. (2.5TSCK, 7TCPU)
TSCK:
1/fSCK
fSCK:
Serial clock frequency
TCPU:
1/fCPU
fCPU:
CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC),
the oscillation mode selection register (OSMS) and the clock select registers (IECL1,
IECL2))
MAX. (a, b): a or b, whichever is greater
Figure 15-24. Operation Timing with Automatic Data Transmit/Receive Function Performed by
Internal Clock
fX
TCPU
f CPU
TSCK
Interval
SCK1
SO1
D7
D6
D5
D4
D3
D2
D1
D0
SI1
D7
D6
D5
D4
D3
D2
D1
D0
f X:
Main system clock oscillation frequency
fCPU:
CPU clock (set by bit 0 to bit 2 (PCC0 to PCC2) of the processor clock control register (PCC),
the oscillation mode select register (OSMS), and the clock select register (IECL1, IECL2).
TCPU:
344
1/fCPU
TSCK:
1/fSCK
fSCK:
Serial clock frequency
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(b) When the automatic transmit/receive function is used by an external clock
If bit 1 (CSIM11) of serial operation mode register 1 (CSIM1) is cleared to 0, external clock operation is
set.
When the automatic transmit/receive function is used by an external clock, it must be selected so that
the interval is longer than the values shown below.
Table 15-3. Interval Timing Through CPU Processing (When External Clock Is Operating)
CPU Processing
Interval Time
When using multiplication instruction
13TCPU
When using division instruction
20TCPU
External access 1 wait mode
9TCPU
Other than above
7TCPU
TCPU:
1/fCPU
fCPU:
CPU clock (set by the bits 0 to 2 (PCC0 to PCC2) of the processor clock control register
(PCC), the oscillation mode selection register (OSMS), and the clock select registers
(IECL1, IECL2))
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CHAPTER 16 SERIAL INTERFACE CHANNEL 2
16.1 Functions of Serial Interface Channel 2
Serial interface channel 2 has the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial transfer is not carried out to reduce power consumption.
(2) Asynchronous serial interface (UART) mode
In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is
possible.
A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud
rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.
The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator.
(3) 3-wire serial I/O mode (MSB-first/LSB-first switchable)
In this mode, 8-bit data transfer is performed using three lines: the serial clock (SCK2), and serial data lines
(SI2, SO2).
In the 3-wire serial I/O mode, simultaneous transmission and reception is possible, increasing the data transfer
processing speed.
Either the MSB or LSB can be specified as the start bit for an 8-bit data serial transfer, allowing connection
to devices using either as the start bit.
The 3-wire serial I/O mode is useful for connection to peripheral I/Os and display controllers, etc., which
incorporate a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, and
17K Series.
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16.2 Configuration of Serial Interface Channel 2
Serial interface channel 2 consists of the following hardware.
Table 16-1. Configuration of Serial Interface Channel 2
Item
Configuration
Registers
Transmit shift register (TXS)
Receive shift register (RXS)
Receive buffer register (RXB)
Control registers
Serial operating mode register 2 (CSIM2)
Asynchronous serial interface mode register (ASIM)
Asynchronous serial interface status register (ASIS)
Baud rate generator control register (BRGC)
Port mode register 7 (PM7) Note
Note
Refer to Figure 4-13 Block Diagram of P70 and Figure 4-14 Block Diagram of P71 and
P72.
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Figure 16-1. Block Diagram of Serial Interface Channel 2
Internal Bus
Receive Buffer
Register
(RXB/SIO2)
Asynchronous
Serial Interface
Status Register (ASIS)
Direction
FE OVE
Controller
PE
Asynchronous
Serial Interface
Mode Register
(ASIM)
TXE RXE PS1 PS0 CL
SL ISRM SCK
Transmit Shift
Register
(TXS/SIO2)
Direction
Controller
Receive Shift
Register (RXS)
RxD/SI2/
P70
TxD/SO2/
P71
PM71
Reception
Control
Circuit
PM72
INTSER
INTSR/INTCSI2
Transmission
Control
Circuit
SCK Output
Controller
INTST
ISRM
ASCK/
SCK2/P72
Note
Baud Rate Generator
CSIE2
TXE
RXE
CSIE2
CSIM CSCK
22
SCK
CSCK
Baud Rate Generator
Control Register (BRGC)
Internal Bus
348
4
MDL3 MDL2 MDL1 MDL0 TPS3 TPS2 TPS1 TPS0
Serial Operating
Mode Register 2
(CSIM2)
Note
4
f xx to fxx/210
See Figure 16-2 for the baud rate generator configuration.
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Figure 16-2. Block Diagram of Baud Rate Generator
CSIE2
TXE
1/2
Selector
5-Bit
Counter
Selector
Transmit
Clock
Selector
Start Bit
Sampling Clock
Match
ASCK/SCK2/P72
Selector
4
MDL0 to MDL3
f xx to fxx/210
TPS0 to TPS3
SCK
CSCK
Receive
Clock
Selector
Decoder
4
Match
1/2
5-Bit
Counter
4
RXE
Start Bit Detection
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
Baud Rate Generator
Control Register (BRGC)
Internal Bus
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(1) Transmit shift register (TXS)
This register is used to set the transmit data. The data written in TXS is transmitted as serial data.
If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data.
Writing data to TXS starts the transmit operation.
TXS is written to with an 8-bit memory manipulation instruction. It cannot be read.
RESET input sets TXS to FFH.
Caution TXS must not be written to during a transmit operation. TXS and the receive buffer register
(RXB) are allocated to the same address, and when a read is performed, the value of RXB
is read.
(2) Receive shift register (RXS)
This register is used to convert serial data input to the RxD pin to parallel data. When one byte of data is
received, the receive data is transferred to the receive buffer register (RXB).
RXS cannot be directly manipulated by a program.
(3) Receive buffer register (RXB)
This register holds receive data. Each time one byte of data is received, new receive data is transferred from
the receive shift register (RXS).
If the data length is specified as 7 bits, the receive data is transferred to bits 0 to 6 of RXB, and the MSB of
RXB is always set to 0.
RXB is read with an 8-bit memory manipulation instruction. It cannot be written to.
RESET input sets RXB to FFH.
Caution RXB and the transmit shift register (TXS) are allocated to the same address, and when a write
is performed, the value is written to TXS.
(4) Transmission controller
This circuit performs transmit operation control such as the addition of a start bit, parity bit and stop bit to data
written in the transmit shift register (TXS) in accordance with the contents set in the asynchronous serial
interface mode register (ASIM).
(5) Reception controller
This circuit controls receive operations in accordance with the contents set in the asynchronous serial interface
mode register (ASIM). It performs error checks for parity errors, etc., during a receive operation, and if an
error is detected, sets a value in the asynchronous serial interface status register (ASIS) in accordance with
the error contents.
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16.3 Registers Controlling Serial Interface Channel 2
Serial interface channel 2 is controlled by the following four registers.
• Serial operating mode register 2 (CSIM2)
• Asynchronous serial interface mode register (ASIM)
• Asynchronous serial interface status register (ASIS)
• Baud rate generator control register (BRGC)
(1) Serial operating mode register 2 (CSIM2)
This register is set when serial interface channel 2 is used in the 3-wire serial I/O mode.
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM2 to 00H.
Figure 16-3. Format of Serial Operating Mode Register 2
Symbol
7
CSIM2 CSIE2
6
5
4
3
0
0
0
0
CSIE2
2
1
CSIM
CSCK
22
Address
0
FF72H
After Reset
R/W
00H
R/W
Operation Control in 3-Wire Serial I/O Mode
0
Operation stopped
1
Operation enabled
First Bit Specification
CSIM22
0
MSB
1
LSB
CSCK
0
Clock Selection in 3-Wire Serial I/O Mode
0
Input clock from off-chip to SCK2 pin
1
Dedicated baud rate generator output
Cautions 1. Ensure that bit 0 and bits 3 to 6 are set to 0.
2. When UART mode is selected, CSIM2 should be set to 00H.
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(2) Asynchronous serial interface mode register (ASIM)
This register is set when serial interface channel 2 is used in the asynchronous serial interface mode.
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM to 00H.
Figure 16-4. Format of Asynchronous Serial Interface Mode Register
Symbol
ASIM
7
6
5
4
3
2
1
TXE
RXE
PS1
PS0
CL
SL
Address
0
ISRM SCK
TXE
After Reset
FF70H
00H
R/W
Transmit Operation Control
0
Transmit operation stopped
1
Transmit operation enabled
RXE
Receive Operation Control
0
Receive operation stopped
1
Receive operation enabled
PS1
PS0
0
0
No Parity
0
1
0 parity always added in transmission
No parity test in reception (parity error not generated)
1
0
Odd parity
1
1
Even parity
Parity Bit Specification
CL
Character Length Specification
0
7 bits
1
8 bits
SL
Transmit Data Stop Bit Length Specification
0
1 bit
1
2 bits
ISRM
Control of Reception Completion Interrupt in Case of Error Generation
0
Reception completion interrupt generated in case of error generation
1
Reception completion interrupt not generated in case of error generation
SCK
Clock Selection in Asynchronous Serial Interface Mode
0
Input clock from off-chip to ASCK pin
1
Dedicated baud rate generator output
Note
R/W
Note
When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as
an I/O port.
Cautions 1. When the 3-wire serial I/O mode is selected, ASIM should be set to 00H.
2. The serial transmit/receive operation must be stopped before changing the operating
mode.
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Table 16-2. Operating Mode Settings of Serial Interface Channel 2
(1) Operation stop mode
PM70 P70 PM71 P71 PM72 P72 Start Shift P70/SI2
P71/SO2 P72/SCK2
Bit
Clock /RxD Pin /TxD Pin /ASCK Pin
TXE RXE SCK CSIE2 CSIM22 CSCK
Functions Functions Functions
ASIM
0
CSIM2
x
0
0
x
x
x
Note1
x
Note1
x
Note1
x
Note1
x
Note1
x
Note1
—
—
Other than above
P70
P71
P72
Setting prohibited
(2) 3-wire serial I/O mode
PM70 P70 PM71 P71 PM72 P72 Start Shift P70/SI2
P71/SO2 P72/SCK2
Bit
Clock /RxD Pin /TxD Pin /ASCK Pin
TXE RXE SCK CSIE2 CSIM22 CSCK
Functions Functions Functions
ASIM
0
CSIM2
0
0
1
1
0
1
Note2
Note2
1
x
MSB External
clock
1
0
1
Internal
clock
0
1
x
LSB External
clock
1
0
1
Internal
clock
0
1
x
0
1
Other than above
SI2
Note2
SO2
(CMOS
output)
SCK2 input
SCK2 output
SI2
Note2
SO2
(CMOS
output)
SCK2 input
SCK2 output
Setting prohibited
(3) Asynchronous serial interface mode
ASIM
CSIM2
PM70 P70 PM71 P71 PM72 P72 Start Shift P70/SI2
P71/SO2 P72/SCK2
Bit
Clock /RxD Pin /TxD Pin /ASCK Pin
TXE RXE SCK CSIE2 CSIM22 CSCK
Functions Functions Functions
1
0
0
0
0
0
x
Note1
x
Note1
0
1
1
0
0
0
0
1
x
x
Note1
x Note1
1
0
1
x
x Note1 x Note1
1
1
x
x Note1 x Note1
1
0
1
0
0
0
1
x
0
1
1
x
x Note1 x Note1
1
Other than above
LSB External
clock
P70
TxD
ASCK input
(CMOS
output)
P72
RxD
P71
Internal
clock
External
clock
Internal
clock
ASCK input
P72
TxD
ASCK input
(CMOS
output)
P72
External
clock
Internal
clock
Setting prohibited
Notes 1. Can be used freely as port function.
2. Can be used as P70 (CMOS I/O) when only transmission is performed.
Remark
×:
Don't care
PMXX: Port mode register
PXX:
Port output latch
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(3) Asynchronous serial interface status register (ASIS)
This is a register that displays the type of error when a receive error is generated in the asynchronous serial
interface mode.
ASIS is read with an 8-bit memory manipulation instruction.
In 3-wire serial I/O mode, the contents of ASIS are undefined.
RESET input clears ASIS to 00H.
Figure 16-5. Format of Asynchronous Serial Interface Status Register
Symbol
7
6
5
4
3
2
1
0
ASIS
0
0
0
0
0
PE
FE
OVE
PE
Address
After Reset
FF71H
00H
R/W
R
Parity Error Flag
0
Parity error not generated
1
Parity error generated (when parity specification during transmission and receive data parity do not match)
FE
Framing Error Flag
0
Framing error not generated
1
Framing error generated Note 1 (when stop bit is not detected)
OVE
Overrun Error Flag
0
Overrun error not generated
1
Overrun error generated Note 2
(when next receive operation is completed before data is read from receive buffer register)
Notes 1. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial interface
mode register (ASIM), only single stop bit detection is performed during reception.
2. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors
will continue to be generated until RXB is read.
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(4) Baud rate generator control register (BRGC)
This register sets the serial clock for serial interface channel 2.
BRGC is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC to 00H.
Figure 16-6. Format of Baud Rate Generator Control Register (1/2)
Symbol
BRGC
7
6
5
4
3
2
1
0
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
TPS3 TPS2 TPS1 TPS0
Address
FF73H
After Reset
00H
R/W
R/W
Selects Source Clock of 5-Bit Counter
n
0
0
0
0
fXX/210 (3.91 kHz)
11
0
1
0
1
fXX
(4.0 MHz)
1
0
1
1
0
fXX/2
(2.0 MHz)
2
0
1
1
1
fXX/22
(1.0 MHz)
3
1
0
0
0
fXX/23
(500 kHz)
4
4
1
0
0
1
fXX/2
(250 kHz)
5
1
0
1
0
fXX/25
(125 kHz)
6
1
0
1
1
fXX/26
(62.5 kHz)
7
7
1
1
0
0
fXX/2
(31.3 kHz)
8
1
1
0
1
fXX/28
(15.6 kHz)
9
1
1
1
0
fXX/29
(7.81 kHz)
10
Other than above
Remarks 1. fXX:
2. n:
Setting prohibited
Main system clock frequency
Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
3. Figures in parentheses apply to operation with fXX = 4.0 MHz
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Figure 16-6. Format of Baud Rate Generator Control Register (2/2)
MDL3 MDL2 MDL1 MDL0
Baud Rate Generator Input Clock Selection
k
0
0
0
0
fSCK/16
0
0
0
0
1
fSCK/17
1
0
0
1
0
fSCK/18
2
0
0
1
1
fSCK/19
3
0
1
0
0
fSCK/20
4
0
1
0
1
fSCK/21
5
0
1
1
0
fSCK/22
6
0
1
1
1
fSCK/23
7
1
0
0
0
fSCK/24
8
1
0
0
1
fSCK/25
9
1
0
1
0
fSCK/26
10
1
0
1
1
fSCK/27
11
1
1
0
0
fSCK/28
12
1
1
0
1
fSCK/29
13
1
1
1
0
fSCK/30
14
1
1
1
1
fSCK
Note
—
Note
Can only be used in 3-wire serial I/O mode.
Caution When a write is performed to BRGC during a communication operation, baud rate generator
output is disrupted and communication cannot be performed normally.
Therefore, BRGC must not be written to during a communication operation.
Remarks 1. fSCK:
2. k:
356
5-bit counter source clock
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
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The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal
scaled from the clock input from the ASCK pin.
(a) Generation of baud rate transmit/receive clock by means of main system clock
The transmit/receive clock is generated by scaling the main system clock. The baud rate generated from
the main system clock is obtained from the following expression.
[Baud rate] =
where,
fXX
2n
× (k + 16)
fXX:
[Hz]
Main system clock frequency (fx or fx/2)
n:
Value set in TPS0 to TPS3
k:
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
Table 16-3. Relationship Between Main System Clock and Baud Rate
Baud Rate (bps)
fXX = 4.0 MHz
BRGC Set Value
Error (%)
75
0AH
0.16
110
02H
–1.36
150
EAH
0.16
300
DAH
0.16
600
CAH
0.16
1,200
BAH
0.16
2,400
AAH
0.16
4,800
9AH
0.16
9,600
8AH
0.16
19,200
7AH
0.16
31,250
70H
0
38,400
6AH
0.16
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(b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin
The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate
generated from the clock input from the ASCK pin is obtained with the following expression.
fASCK
[Baud rate] =
2 × (k + 16)
[Hz]
fASCK:
Frequency of clock input to ASCK pin
k:
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
Table 16-4. Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H)
358
Baud Rate (bps)
ASCK Pin Input Frequency
75
2.4 kHz
110
3.52 kHz
150
4.8 kHz
300
9.6 kHz
600
19.2 kHz
1,200
38.4 kHz
2,400
76.8 kHz
4,800
153.6 kHz
9,600
307.2 kHz
19,200
614.4 kHz
31,250
1,000.0 kHz
38,400
1,228.8 kHz
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16.4 Operation of Serial Interface Channel 2
Serial interface channel 2 has the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
16.4.1 Operation stop mode
In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced.
In the operation stop mode, the P70/SI2/RxD, P71/SO2/TxD and P72/SCK2/ASCK pins can be used as normal
I/O ports.
(1) Register setting
Operation stop mode settings are performed using serial operating mode register 2 (CSIM2) and the
asynchronous serial interface mode register (ASIM).
(a) Serial operating mode register 2 (CSIM2)
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM2 to 00H.
Symbol
7
CSIM2 CSIE2
6
0
5
0
4
0
CSIE2
3
0
2
1
CSIM CSCK
22
0
Address
0
FF72H
After Reset
00H
R/W
R/W
Operation Control in 3-Wire Serial I/O Mode
0
Operation stopped
1
Operation enabled
Caution Ensure that bits 0 and 3 to 6 are set to 0.
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(b) Asynchronous serial interface mode register (ASIM)
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM to 00H.
Symbol
ASIM
7
6
5
4
3
2
TXE
RXE
PS1
PS0
CL
SL
TXE
0
ISRM SCK
Address
After Reset
FF70H
Transmit Operation Control
0
Transmit operation stopped
1
Transmit operation enabled
RXE
360
1
Receive Operation Control
0
Receive operation stopped
1
Receive operation enabled
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R/W
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SERIAL INTERFACE CHANNEL 2
16.4.2 Asynchronous serial interface (UART) mode
In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible.
A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates.
In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.
The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator.
(1) Register setting
UART mode settings are performed using serial operating mode register 2 (CSIM2), the asynchronous serial
interface mode register (ASIM), the asynchronous serial interface status register (ASIS), and the baud rate
generator control register (BRGC).
(a) Serial operating mode register 2 (CSIM2)
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM2 to 00H.
When the UART mode is selected, CSIM2 should be set to 00H.
Symbol
7
CSIM2 CSIE2
6
5
4
3
0
0
0
0
CSIE2
2
1
CSIM
CSCK
22
Address
0
FF72H
After Reset
00H
R/W
R/W
Operation Control in 3-Wire Serial I/O Mode
0
Operation stopped
1
Operation enabled
First Bit Specification
CSIM22
0
MSB
1
LSB
CSCK
0
Clock Selection in 3-Wire Serial I/O Mode
0
Input clock from off-chip to SCK2 pin
1
Dedicated baud rate generator output
Caution Ensure that bit 0 and bits 3 to 6 are set to 0.
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(b) Asynchronous serial interface mode register (ASIM)
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM to 00H.
Symbol
ASIM
7
6
5
4
3
2
TXE
RXE
PS1
PS0
CL
SL
1
Address
0
ISRM SCK
TXE
FF70H
After Reset
00H
R/W
R/W
Transmit Operation Control
0
Transmit operation stopped
1
Transmit operation enabled
RXE
Receive Operation Control
0
Receive operation stopped
1
Receive operation enabled
Parity Bit Specification
PS1
PS0
0
0
No Parity
0
1
0 parity always added in transmission
No parity test in reception (parity error not generated)
1
0
Odd parity
1
1
Even parity
CL
Character Length Specification
0
7 bits
1
8 bits
SL
Transmit Data Stop Bit Length Specification
0
1 bit
1
2 bits
ISRM
Control of Reception Completion Interrupt in Case of Error Generation
0
Reception completion interrupt generated in case of error generation
1
Reception completion interrupt not generated in case of error generation
SCK
Clock Selection in Asynchronous Serial Interface Mode
0
Input clock from off-chip to ASCK pin
1
Dedicated baud rate generator output
Note
Note
When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used
as an I/O port.
Caution The serial transmit/receive operation must be stopped before changing the operating
mode.
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(c) Asynchronous serial interface status register (ASIS)
ASIS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIS to 00H.
Symbol
7
6
5
4
3
2
1
0
ASIS
0
0
0
0
0
PE
FE
OVE
PE
Address
After Reset
FF71H
00H
R/W
R
Parity Error Flag
0
Parity error not generated
1
Parity error generated (when parity specification during transmission and receive data parity do not match)
FE
Framing Error Flag
0
Framing error not generated
1
Framing error generated Note 1
(when stop bit is not detected)
OVE
Overrun Error Flag
0
Overrun error not generated
1
Overrun error generated Note 2
(when next receive operation is completed before data from receive buffer register is read)
Notes 1. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial
interface mode register (ASIM), only single stop bit detection is performed during reception.
2. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun
errors will continue to be generated until RXB is read.
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(d) Baud rate generator control register (BRGC)
BRGC is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC to 00H.
Symbol
BRGC
7
6
5
4
3
2
1
0
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
TPS3 TPS2 TPS1 TPS0
Address
FF73H
After Reset
00H
R/W
R/W
Selects Source Clock of 5-Bit Counter
n
0
0
0
0
fXX/210 (3.91 kHz)
11
0
1
0
1
fXX
(4.0 MHz)
1
0
1
1
0
fXX/2
(2.0 MHz)
2
0
1
1
1
fXX/22
(1.0 MHz)
3
0
fXX/2
3
(500 kHz)
4
4
(250 kHz)
5
1
0
0
1
0
0
1
fXX/2
1
0
1
0
fXX/25
(125 kHz)
6
1
fXX/2
6
(62.5 kHz)
7
7
(31.3 kHz)
8
1
0
1
1
1
0
0
fXX/2
1
1
0
1
fXX/28
(15.6 kHz)
9
0
9
(7.81 kHz)
10
1
1
1
Other than above
fXX/2
Setting prohibited
(Cont’d)
Remarks 1. fXX:
2. n:
Main system clock frequency
Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
3. Figures in parentheses apply to operation with fXX = 4.0 MHz.
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MDL3 MDL2 MDL1 MDL0
SERIAL INTERFACE CHANNEL 2
Baud Rate Generator Input Clock Selection
k
0
0
0
0
fSCK/16
0
0
0
0
1
fSCK/17
1
0
0
1
0
fSCK/18
2
0
0
1
1
fSCK/19
3
0
1
0
0
fSCK/20
4
0
1
0
1
fSCK/21
5
0
1
1
0
fSCK/22
6
0
1
1
1
fSCK/23
7
1
0
0
0
fSCK/24
8
1
0
0
1
fSCK/25
9
1
0
1
0
fSCK/26
10
1
0
1
1
fSCK/27
11
1
1
0
0
fSCK/28
12
1
1
0
1
fSCK/29
13
1
1
1
0
fSCK/30
14
Caution When a write is performed to BRGC during a communication operation, baud rate
generator output is disrupted and communication cannot be performed normally.
Therefore, BRGC must not be written to during a communication operation.
Remark
fSCK:
5-bit counter source clock
k:
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
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The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or
a signal scaled from the clock input from the ASCK pin.
(i)
Generation of baud rate transmit/receive clock by means of main system clock
The transmit/receive clock is generated by scaling the main system clock. The baud rate generated
from the main system clock is obtained with the following expression.
[Baud rate] =
where,
fXX
2n × (k + 16)
[Hz]
fXX:
Main system clock frequency (fx or fx/2)
n:
Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
k:
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
Table 16-5. Relationship Between Main System Clock and Baud Rate
Baud Rate (bps)
366
fXX = 4.0 MHz
BRGC Set Value
Error (%)
75
0AH
0.16
110
02H
–1.36
150
EAH
0.16
300
DAH
0.16
600
CAH
0.16
1,200
BAH
0.16
2,400
AAH
0.16
4,800
9AH
0.16
9,600
8AH
0.16
19,200
7AH
0.16
31,250
70H
0
38,400
6AH
0.16
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(ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin
The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate
generated from the clock input from the ASCK pin is obtained with the following expression.
[Baud rate] =
where,
fASCK
2 × (k + 16)
[Hz]
fASCK: Frequency of clock input to ASCK pin
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
k:
Table 16-6. Relationship Between ASCK Pin Input Frequency and Baud Rate (When BRGC Is Set to 00H)
Baud Rate (bps)
ASCK Pin Input Frequency
75
2.4 kHz
110
3.52 kHz
150
4.8 kHz
300
9.6 kHz
600
19.2 kHz
1,200
38.4 kHz
2,400
76.8 kHz
4,800
153.6 kHz
9,600
307.2 kHz
19,200
614.4 kHz
31,250
1,000.0 kHz
38,400
1,228.8 kHz
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(2) Communication operation
(a) Data format
The transmit/receive data format is as shown in Figure 16-7.
Figure 16-7. Format of Asynchronous Serial Interface Transmit/Receive Data
One Data Frame
Start
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop Bit
Character Bit
One data frame consists of the following bits:
• Start bit ...................
1 bit
• Character bits .........
7 bits/8 bits
• Parity bits ................
Even parity/odd parity/0 parity/no parity
• Stop bit(s) ...............
1 bit/2 bits
The specification of character bit length, parity selection, and specification of stop bit length for each data
frame is carried out with the asynchronous serial interface mode register (ASIM).
When 7 bits is selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in
transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is
always "0".
The serial transfer rate is selected by means of ASIM and the baud rate generator control register (BRGC).
If a serial data receive error is generated, the receive error contents can be determined by reading the
status of the asynchronous serial interface status register (ASIS).
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(b) Parity types and operation
The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity
bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd
number) error can be detected. With 0 parity and no parity, an error cannot be detected.
(i)
Even parity
• Transmission
The number of bits with a value of “1”, including the parity bit, in the transmit data is controlled to
be even.
The value of the parity bit is as follows:
Number of bits with a value of “1” in transmit data is odd: 1
Number of bits with a value of “1” in transmit data is even: 0
• Reception
The number of bits with a value of “1”, including the parity bit, in the receive data is counted. If
it is odd, a parity error occurs.
(ii) Odd parity
• Transmission
Conversely to the situation with even parity, the number of bits with a value of “1”, including the
parity bit, in the transmit data is controlled to be odd. The value of the parity bit is as follows:
Number of bits with a value of “1” in transmit data is odd: 0
Number of bits with a value of “1” in transmit data is even: 1
• Reception
The number of bits with a value of “1”, including the parity bit, in the receive data is counted. If
it is even, a parity error occurs.
(iii) 0 Parity
When transmitting, the parity bit is set to "0" irrespective of the transmit data.
At reception, a parity bit check is not performed. Therefore, a parity error is not generated, irrespective
of whether the parity bit is set to "0" or "1".
(iv) No parity
A parity bit is not added to the transmit data. At reception, data is received assuming that there is
no parity bit. Since there is no parity bit, a parity error is not generated.
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SERIAL INTERFACE CHANNEL 2
(c) Transmission
A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit,
parity bit and stop bit(s) are added automatically.
When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when
the transmit shift register (TXS) is empty, a transmission completion interrupt request (INTST) is
generated.
Figure 16-8. Asynchronous Serial Interface Transmission Completion Interrupt Request Generation Timing
(a) Stop bit length: 1
STOP
TxD (Output)
D0
D1
D2
D6
D7
Parity
D7
Parity
START
INTST
(b) Stop bit length: 2
TxD (Output)
D0
D1
D2
D6
STOP
START
INTST
Caution Rewriting of the asynchronous serial interface mode register (ASIM) should not be
performed during a transmit operation. If rewriting of the ASIM register is performed
during transmission, subsequent transmit operations may not be possible (the normal
state is restored by RESET input).
It is possible to determine whether transmission is in progress by software by using a
transmission completion interrupt request (INTST) or the interrupt request flag (STIF)
set by the INTST.
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(d) Reception
When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (to 1), a receive
operation is enabled and sampling of the RxD pin input is performed.
RxD pin input sampling is performed using the serial clock specified by ASIM.
When the RxD pin input becomes low, the 5-bit counter of the baud rate generator (refer to Figure 162) starts counting, and at the time when half the time determined by the specified baud rate has passed,
the data sampling start timing signal is output. If the RxD pin input sampled again as a result of this start
timing signal is low, it is identified as a start bit, the 5-bit counter is initialized and starts counting, and
data sampling is performed. When character data, a parity bit and one stop bit are detected after the
start bit, reception of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to the receive
buffer register (RXB), and a reception completion interrupt request (INTSR) is generated.
If an error is generated, the receive data in which the error was generated is still transferred to RXB. If
bit 1 (ISRM) of ASIM is cleared (to 0) on occurrence of the error, INTSR is generated. If the ISRM bit
is set (to 1), INTSR is not generated.
If the RXE bit is reset (to 0) during the receive operation, the receive operation is stopped immediately.
In this case, the contents of RXB and ASIS are not changed, and INTSR and INTSER are not generated.
Figure 16-9. Asynchronous Serial Interface Reception Completion Interrupt Request Generation Timing
STOP
RxD (Input)
D0
D1
D2
D6
D7
Parity
START
INTSR
Caution The receive buffer register (RXB) must be read even if a receive error is generated. If
RXB is not read, an overrun error will be generated when the next data is received, and
the receive error state will continue indefinitely.
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(e) Receive errors
Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error.
The data reception result error flag is set in the asynchronous serial interface status register (ASIS) and
a receive error interrupt request (INTSER) is generated. The receive error interrupt occurs earlier than
the receive completion interrupt (INTSR). Receive error causes are shown in Table 16-7.
It is possible to determine what kind of error was generated during reception by reading the contents of
ASIS in the reception error interrupt servicing (INTSER) (see Figures 16-9 and 16-10).
The contents of ASIS are reset (to 0) by reading the receive buffer register (RXB) or receiving the next
data (if there is an error in the next data, the corresponding error flag is set).
Table 16-7. Receive Error Causes
Receive Errors
Cause
Parity error
Transmission-time parity specification and reception data parity do not match
Framing error
Stop bit not detected
Overrun error
Reception of next data is completed before data is read from receive register buffer
Figure 16-10. Receive Error Timing
STOP
D0
RxD (Input)
D1
D2
D6
D7
Parity
START
INTSR Note
INTSER (when framing/
overrun error occurs)
INTSER (when parity
error occurs)
Note
INTSR is not generated if a receive error is generated while bit 1 (ISRM) of the asynchronous serial
interface mode register (ASIM) is set (to 1).
Cautions 1. The contents of ASIS are reset (to 0) by reading the receive buffer register (RXB) or
receiving the next data. To ascertain the error contents, ASIS must be read before
reading RXB.
2. The receive buffer register (RXB) must be read even if a receive error is generated.
If RXB is not read, an overrun error will be generated when the next data is received,
and the receive error state will continue indefinitely.
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(3) UART mode cautions
(a) When the transmission under execution has been stopped by clearing bit 7 (TXE) of the asynchronous
serial interface mode register (ASIM) to 0, be sure to set the transmit shift register (TXS) to FFH, then
set TXE to 1 before executing the next transmission.
(b) When the reception under execution has been stopped by clearing bit 6 (RXE) of the asynchronous serial
interface mode register (ASIM) to 0, the status of the receive buffer register (RXB) and whether the receive
completion interrupt request (INTSR) occurs differ depending on the timing of stopping the reception.
Figure 16-11 shows the timing.
Figure 16-11. Status of Receive Buffer Register (RXB) and Generation of
Interrupt Request (INTSR) When Reception Is Stopped
RxD Pin
Parity
RXB
INTSR
<1>
<3>
<2>
When RXE is set to 0 at a time indicated by <1>, RXB holds the previous data and does not generate INTSR.
When RXE is set to 0 at a time indicated by <2>, RXB renews the data and does not generate INTSR.
When RXE is set to 0 at a time indicated by <3>, RXB renews the data and generates INTSR.
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16.4.3 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate
a conventional synchronous clocked serial interface, such as the 75X/XL Series, 78K Series, and 17K Series.
Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2).
(1) Register setting
3-wire serial I/O mode settings are performed using serial operating mode register 2 (CSIM2), the asynchronous serial interface mode register (ASIM), and the baud rate generator control register (BRGC).
(a) Serial operating mode register 2 (CSIM2)
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears CSIM2 to 00H.
Symbol
7
CSIM2 CSIE2
6
0
5
0
4
0
CSIE2
3
0
2
1
CSIM
CSCK
22
Address
0
FF72H
Operation stopped
1
Operation enabled
00H
First Bit Specification
CSIM22
0
MSB
1
LSB
Clock Selection in 3-Wire Serial I/O Mode
0
Input clock from off-chip to SCK2 pin
1
Dedicated baud rate generator output
Caution Ensure that bit 0 and bits 3 to 6 are set to 0.
374
After Reset
Operation Control in 3-Wire Serial I/O Mode
0
CSCK
0
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CHAPTER 16
SERIAL INTERFACE CHANNEL 2
(b) Asynchronous serial interface mode register (ASIM)
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears ASIM to 00H.
When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.
Symbol
ASIM
7
6
5
4
3
2
TXE
RXE
PS1
PS0
CL
SL
1
Address
0
ISRM SCK
TXE
FF70H
00H
Transmit operation stopped
1
Transmit operation enabled
RXE
R/W
Receive Operation Control
0
Receive operation stopped
1
Receive operation enabled
PS1
PS0
0
0
No Parity
0
1
0 parity always added in transmission
No parity test in reception (parity error not generated)
1
0
Odd parity
1
1
Even parity
Parity Bit Specification
CL
Character Length Specification
0
7 bits
1
8 bits
SL
Transmit Data Stop Bit Length Specification
0
1 bit
1
2 bits
Control of Receive Completion Interrupt in Case of Error Generation
0
Receive completion interrupt generated in case of error generation
1
Receive completion interrupt not generated in case of error generation
SCK
R/W
Transmit Operation Control
0
ISRM
After Reset
Clock Selection in Asynchronous Serial Interface Mode
0
Input clock from off-chip to ASCK pin
1
Dedicated baud rate generator output
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(c) Baud rate generator control register (BRGC)
BRGC is set with an 8-bit memory manipulation instruction.
RESET input clears BRGC to 00H.
Symbol
BRGC
7
6
5
4
3
2
1
0
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
TPS3 TPS2 TPS1 TPS0
Address
FF73H
After Reset
00H
R/W
R/W
Selects Source Clock of 5-bit Counter
10
n
0
0
0
0
fXX/2
(3.91 kHz)
11
0
1
0
1
fXX
(4.0 MHz)
1
0
1
1
0
fXX/2
0
1
1
1
(2.0 MHz)
2
2
(1.0 MHz)
3
3
fXX/2
1
0
0
0
fXX/2
(500 kHz)
4
1
0
0
1
fXX/24
(250 kHz)
5
0
5
(125 kHz)
6
6
1
0
1
fXX/2
1
0
1
1
fXX/2
(62.5 kHz)
7
1
1
0
0
fXX/27
(31.3 kHz)
8
1
1
0
1
fXX/28
(15.6 kHz)
9
0
9
(7.81 kHz)
10
1
1
1
Other than above
fXX/2
Setting prohibited
(Cont’d)
Remarks 1. fXX: Main system clock frequency
2. n:
Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
3. Figures in parentheses apply to operation with fXX = 4.0 MHz.
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MDL3 MDL2 MDL1 MDL0
SERIAL INTERFACE CHANNEL 2
Baud Rate Generator Input Clock Selection
k
0
0
0
0
fSCK/16
0
0
0
0
1
fSCK/17
1
0
0
1
0
fSCK/18
2
0
0
1
1
fSCK/19
3
0
1
0
0
fSCK/20
4
0
1
0
1
fSCK/21
5
0
1
1
0
fSCK/22
6
0
1
1
1
fSCK/23
7
1
0
0
0
fSCK/24
8
1
0
0
1
fSCK/25
9
1
0
1
0
fSCK/26
10
1
0
1
1
fSCK/27
11
1
1
0
0
fSCK/28
12
1
1
0
1
fSCK/29
13
1
1
1
0
fSCK/30
14
1
1
1
1
fSCK
—
Caution When a write is performed to BRGC during a communication operation, baud rate
generator output is disrupted and communication cannot be performed normally.
Therefore, BRGC must not be written to during a communication operation.
Remark
fSCK:
5-bit counter source clock
k:
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
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When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below.
BRGC Setting is not required if an external serial clock is used.
(i) When the baud rate generator is not used:
Select a serial clock frequency with TPS0 to TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1.
The serial clock frequency becomes half the source clock frequency of the 5-bit counter.
(ii) When the baud rate generator is used:
Select the serial clock frequency with TPS0 to TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1.
The serial clock frequency is calculated by the following formula:
fXX
Serial clock frequency =
[Hz]
n
2 × (k + 16)
Remarks 1. fXX:
378
Main system clock frequency
2. n:
Value set in TPS0 to TPS3 (1 ≤ n ≤ 11)
3. k:
Value set in MDL0 to MDL3 (0 ≤ k ≤ 14)
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(2) Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/
received bit by bit in synchronization with the serial clock.
Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in
synchronization with the fall of the serial clock SCK2. Then transmit data is held in the SO2 latch and output
from the SO2 pin. Also, receive data input to the SI2 pin is latched in the receive buffer register (RXB/SIO2)
on the rise of SCK2.
At the end of an 8-bit transfer, the operation of the TXS/SIO2 or RXS stops automatically, and the interrupt
request flag (SRIF) is set.
Figure 16-12. 3-Wire Serial I/O Mode Timing
SCK2
SI2
SO2
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
SRIF
End of Transfer
Transfer Start at Falling Edge of SCK2
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(3) MSB/LSB switching as the start bit
In the 3-wire serial I/O mode, transfer can be selected to start from the MSB or LSB.
Figure 16-13 shows the configuration of the transmit shift register (TXS/SIO2) and internal bus. As shown
in the figure, the MSB/LSB can be read/written in reverse.
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM22) of serial operating mode register 2
(CSIM2).
Figure 16-13. Transfer Bit Order Switching Circuit
7
6
Internal Bus
1
0
LSB-first
MSB-first
Read/Write Gate
Read/Write Gate
SO2 Latch
SI2
Transmit Shift Register (TXS/SIO2)
D
Q
SO2
SCK2
Start bit switching is realized by switching the bit order for data written to SIO2. The SIO2 shift order remains
unchanged.
Thus, switch the MSB/LSB start bit before writing data to the shift register.
(4) Transfer start
Serial transfer is started by setting transfer data to the transmit shift register (TXS/SIO2) when the following
two conditions are satisfied.
• Serial interface channel 2 operation control bit (CSIE2) =1
• Internal serial clock is stopped or SCK2 is a high level after 8-bit serial transfer.
Caution If CSIE2 is set to "1" after data is written to TXS/SIO2, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (SRIF) is
set.
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16.4.4 Restrictions in UART mode
In the UART mode, the receive completion interrupt (INTSR) occurs a certain time after the receive error interrupt
(INTSER) occurred and was cleared. Consequently, the following phenomenon may take place.
• Description
If bit 1 (ISRM) of the asynchronous serial interface mode register (ASIM) is set to 1, the receive completion
interrupt (INTSR) does not occur when a receive error occurs. If the receive buffer register (RXB) is read at
certain timing (“a” in Figure 16-14) while the receive error interrupt (INTSER) is being serviced, the internal error
flag is cleared to 0. Therefore, it is judged that the receive error does not occur, and INTSR, which must not
occur, occurs. This is illustrated in Figure 16-14.
Figure 16-14. Receive Completion Interrupt Request Generation Timing (When ISRM = 1)
fSCK
INTSER (When framing/
overrun error occurs)
a
Error Flag
(Internal flag)
Cleared when
RXB is read
INTSR
Interrupt Processing
Routine of CPU
RXB is read
Remark
It is judged that receive error does not
occur, and INTSR occurs.
ISRM: Bit 1 of asynchronous serial interface mode register (ASIM)
fSCK:
Source clock of 5-bit counter of baud rate generator
RXB:
Receive buffer register
To prevent this phenomenon, take the following measures.
• Preventive measures
• In case of framing error or overrun error
Disable reading the receive buffer register (RXB) for a certain period (T2 in Figure 16-15) after the receive
error interrupt (INTSER) has occurred.
• In case of parity error
Disable reading the receive buffer register (RXB) for a certain period (T1 + T2 in Figure 16-15) after the receive
error interrupt (INTSER) has occurred.
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Figure 16-15. Disabling Reading Receive Buffer Register
RxD (Input)
D0
D1
D2
D6
D7
Parity
STOP
START
INTSR
INTSER
(When framing/overrun
error occurs)
INTSER
(When parity error occurs)
T1
T2
T1: Time of one data of baud rate selected by baud rate generator control register (BRGC) (1/baud rate)
T2: Time of two clocks of source clock (fSCK) of 5-bit counter selected by BRGC
• Example of preventive measure
Here is an example of a preventive measure.
[Condition]
fXX = 4.0 MHz
Baud rate generator control register (BRGC) = AAH (baud rate: 2400 bps)
TCY = 0.5 µs (tCY = 0.25 µs)
1
T1 =
= 416.7 µs
2400
1
T2 =
× 2 = 16 µs
125
T1 + T2
tCY
382
= 1,731 (clock)
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[Example]
Main Processing
UART Receive Error
Interrupt (INTSER) Processing
EI
INTSER occurs
Seven CPU Clocks (MIN.)
(Time from generation of
interrupt request to processing)
Instructions of
1,731 CPU clocks
(MIN.) are
necessary.
MOV A, RXB
RETI
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REAL-TIME OUTPUT PORT
CHAPTER 17 REAL-TIME OUTPUT PORT
17.1 Functions of Real-Time Output Port
Data set previously in the real-time output buffer register can be transferred to the output latch by hardware
concurrently with the generation of a timer interrupt request or external interrupt request, then output externally. This
is called the real-time output function. The pins that output data externally are called real-time output ports.
By using a real-time output, a signal which has no jitter can be output. This port is therefore suitable for control
of stepper motors, etc.
Port mode/real-time output port mode can be specified in 1-bit units.
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REAL-TIME OUTPUT PORT
17.2 Configuration of Real-Time Output Port
The real-time output port consists of the following hardware.
Table 17-1. Configuration of Real-Time Output Port
Item
Configuration
Register
Real-time output buffer register (RTBL, RTBH)
Control registers
Port mode register 12 (PM12)
Real-time output port mode register (RTPM)
Real-time output port control register (RTPC)
Figure 17-1. Block Diagram of Real-Time Output Port
Internal Bus
Real-Time Output
Port Control
Register (RTPC)
BYTE
EXTR
INTP2
INTTM1
INTTM2
Output Trigger
Controller
Port Mode
Register 12
(PM12)
Real-Time Output
Buffer Register
Higher 4 Bits
(RTBH)
Real-Time Output
Buffer Register
Lower 4 Bits
(RTBL)
Real-Time Output port
Mode Register (RTPM)
Output Latch
P127
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(1) Real-time output buffer register (RTBL, RTBH)
RTBL and RTBH are mapped to individual addresses in the special-function register (SFR) area as shown
in Figure 17-2.
When specifying 4 bits × 2 channels as the operating mode, data is set individually in RTBL and RTBH.
When specifying 8 bits × 1 channel as the operating mode, data is set to both RTBL and RTBH by writing 8bit data to either RTBL or RTBH.
Table 17-2 shows operations during manipulation of RTBL and RTBH.
Figure 17-2. Configuration of Real-Time Output Buffer Register
Higher
4 Bits
Lower
4 Bits
FF30H
FF31H
RTBL
RTBH
Table 17-2. Operation in Real-Time Output Buffer Register Manipulation
Operating Mode
In Read Note 1
Register to Be
In Write Note 2
Manipulated
Higher 4 Bits
Lower 4 Bits
Higher 4 Bits
Lower 4 Bits
RTBL
RTBH
RTBL
Invalid
RTBL
RTBH
RTBH
RTBL
RTBH
Invalid
RTBL
RTBH
RTBL
RTBH
RTBL
RTBH
RTBH
RTBL
RTBH
RTBL
4 Bits × 2 channels
8 Bits × 1 channel
Notes 1. Only the bits set in the real-time output port mode can be read. When a bit set in the port mode
is read, 0 is read.
2. After setting data in the real-time output port, output data should be set in RTBL and RTBH by the
time a real-time output trigger is generated.
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17.3 Registers Controlling Real-Time Output Port
The following three registers control the real-time output port.
• Port mode register 12 (PM12)
• Real-time output port mode register (RTPM)
• Real-time output port control register (RTPC)
(1) Port mode register 12 (PM12)
This register sets the input or output mode of port 12 pins (P120 to P127) which are multiplexed with realtime output pins (RTP0 to RTP7). To use port 12 as a real-time output port, the port pin that performs realtime output must be set in the output mode (PM12n = 0: n = 0 to 7).
PM12 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to FFH.
Figure 17-3. Format of Port Mode Register 12
Symbol
7
6
5
4
3
2
1
0
PM12 PM127 PM126 PM125 PM124 PM123 PM122 PM121 PM120
PM12n
Address
After Reset
R/W
FF2CH
FFH
R/W
Selects I/O Mode of P12n Pin (n = 0 to 7)
0
Output mode (output buffer on)
1
Input mode (output buffer off)
(2) Real-time output port mode register (RTPM)
This register selects the real-time output port mode/port mode in 1-bit units.
RTPM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 17-4. Format of Real-Time Output Port Mode Register
Symbol
7
6
5
4
3
2
1
0
RTPM RTPM7 RTPM6 RTPM5 RTPM4 RTPM3 RTPM2 RTPM1 RTPM0
Address
After
Reset
R/W
FF34H
00H
R/W
Real-Time Output Port Selection (n = 0 to 7)
RTPMn
0
Port mode
1
Real-time output port mode
Cautions 1. When using these bits as a real-time output port, set the ports to which real-time output
is performed to the output mode (clear the corresponding bit of port mode register 12
(PM12) to 0).
2. In the port specified as a real-time output port, data cannot be set to the output latch.
Therefore, when setting an initial value, data should be set to the output latch before
setting the real-time output mode.
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(3) Real-time output port control register (RTPC)
This register sets the real-time output port operating mode and output trigger.
Table 17-3 shows the relationship between the operating mode of the real-time output port and output trigger.
RTPC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 17-5. Format of Real-Time Output Port Control Register
Symbol
7
6
5
4
3
2
RTPC
0
0
0
0
0
0
1
0
BYTE EXTR
Address
After
Reset
R/W
FF36H
00H
R/W
Real-Time Output Port Operating Mode
BYTE
0
4 bits × 2 channels
1
8 bits × 1 channel
Real-Time Output Control by INTP2
EXTR
0
INTP2 not specified as real-time output trigger
1
INTP2 specified as real-time output trigger
Table 17-3. Real-Time Output Port Operating Mode and Output Trigger
BYTE
EXTR
Operating Mode
RTBH → Port Output
RTBL → Port Output
0
0
4 bits × 2 channels
INTTM2
INTTM1
INTTM1
INTP2
1
1
0
8 bits × 1 channel
1
388
INTTM1
INTP2
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CHAPTER 18
INTERRUPT AND TEST FUNCTIONS
CHAPTER 18 INTERRUPT AND TEST FUNCTIONS
18.1 Interrupt Function Types
The following three types of interrupt functions are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo
interrupt priority control and is given top priority over all other interrupt requests.
A standby release signal is generated.
One interrupt request from the watchdog timer is provided for a non-maskable interrupt.
(2) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group
and a low interrupt priority group by setting the priority specify flag register (PR0L, PR0H, PR1L).
Multiple interrupt servicing in which high priority interrupts can interrupt the servicing of low priority interrupts
is possible. The priority order when two or more interrupts with the same priority are simultaneously generated
can also be predetermined (see Table 18-1).
A standby release signal is generated.
Seven external interrupt requests and fourteen internal interrupts are provided for maskable interrupts.
(3) Software interrupt
This is a vectored interrupt that occurs when the BRK instruction is executed. It is acknowledged even in an
interrupt disabled state. The software interrupt does not undergo interrupt priority control.
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18.2 Interrupt Sources and Configuration
A total of 23 non-maskable, maskable, and software interrupts are provided as the interrupt sources (see Table
18-1).
Remark
There are two watchdog timer interrupt sources (INTWDT): non-maskable interrupt and maskable
interrupt (internal), and either one can be selected.
Table 18-1. Interrupt Source List (1/2)
Note 1
Interrupt Source
Interrupt
Type
Default
Priority
Nonmaskable
–
INTWDT
Watchdog timer overflow (with
watchdog timer mode 1 selected)
Maskable
0
INTWDT
Watchdog timer overflow (with interval
timer mode selected)
1
INTP0
2
Name
Trigger
Internal
Vector
Table
Address
0004H
Basic Note 2
Configuration Type
(A)
(B)
0006H
(C)
INTP1
0008H
(D)
3
INTP2
000AH
4
INTP3
000CH
5
INTP4
000EH
6
INTP5
0010H
7
INTP6
0012H
8
INTCSI0
End of serial interface channel 0
transfer
9
INTCSI1
End of serial interface channel 1
transfer
0016H
10
INTSER
Serial interface channel 2 UART reception
error generation
0018H
11
INTSR
End of serial interface channel 2
UART reception
001AH
INTCSI2
End of serial interface channel 2
3-wire transfer
INTST
End of serial interface channel 2
UART transfer
12
Pin input edge detection
Internal/
External
External
Internal
0014H
(B)
001CH
Notes 1. The default priority is the priority order when two or more maskable interrupts are generated
simultaneously. 0 is the highest priority and 19 is the lowest priority.
2. Basic configuration types (A) to (E) correspond to (A) to (E) of Figure 18-1.
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Table 18-1. Interrupt Source List (2/2)
Note 1
Interrupt Source
Default
Priority
Maskable
13
INTTM3
Reference time interval signal from
watch timer
14
INTTM00
Generation of 16-bit timer counter 0 (TM0),
capture/compare register (CR00)
match signal
0020H
15
INTTM01
Generation of 16-bit timer counter 0 (TM0),
capture/compare register (CR01)
match signal
0022H
16
INTTM1
Generation of 8-bit timer/event
counter 1 match signal
0024H
17
INTTM2
Generation of 8 bit timer/event
counter 2 match signal
0026H
18
INTAD
End of A/D converter conversion
0028H
19
INTIE
When the IEBus controller writes a value
(including the same value) to the return
code register (RCR), or when a program
loop of the IEBus interface is detected
002AH
—
BRK
BRK instruction execution
Software
Name
Trigger
Internal/
External
Vector
Table
Address
Interrupt
Type
Internal
—
001EH
003EH
Basic Note 2
Configuration Type
(B)
(E)
Notes 1. The default priority is the priority order when two or more maskable interrupts are generated
simultaneously. 0 is the highest priority and 19 is the lowest priority.
2. Basic configuration types (A) to (E) correspond to (A) to (E) of Figure 18-1.
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Figure 18-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal Bus
Vector Table
Address
Generator
Priority
Controller
Interrupt
Request
Standby
Release Signal
(B) Internal maskable interrupt
Internal Bus
MK
Interrupt
Request
IE
PR
ISP
Vector Table
Address
Generator
Priority
Controller
IF
Standby
Release Signal
(C) External maskable interrupt (INTP0)
Internal Bus
Interrupt
Request
Sampling Clock
Select Register
(SCS)
External Interrupt Mode
Register (INTM0)
Sampling
Clock
Edge
Detector
MK
IF
IE
PR
Priority
Controller
ISP
Vector Table
Address
Generator
Standby
Release Signal
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Figure 18-1. Basic Configuration of Interrupt Function (2/2)
(D) External maskable interrupt (except INTP0)
Internal Bus
External Interrupt
Mode Register
(INTM0, INTM1)
Interrupt
Request
Edge
Detector
MK
IE
PR
ISP
Priority
Controller
IF
Vector Table
Address
Generator
Standby
Release Signal
(E) Software interrupt
Internal Bus
Interrupt
Request
Priority
Controller
IF:
Interrupt request flag
IE:
Interrupt enable flag
Vector Table
Address
Generator
ISP: In-service priority flag
MK: Interrupt mask flag
PR: Priority specify flag
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18.3 Registers Controlling Interrupt Function
The following six types of registers are used to control the interrupt functions.
• Interrupt request flag register (IF0L, IF0H, IF1L)
• Interrupt mask flag register (MK0L, MK0H, MK1L)
• Priority specification flag register (PR0L, PR0H, PR1L)
• External interrupt mode register (INTM0, INTM1)
• Sampling clock select register (SCS)
• Program status word (PSW)
Table 18-2 lists the interrupt request flags, interrupt mask flags, and priority specification flags corresponding to
interrupt request sources.
Table 18-2. Various Flags Corresponding to Interrupt Request Sources
Interrupt Source
Interrupt Request Flag
Interrupt Mask Flag
Register
IF0L
Priority Specification Flag
Register
INTWDT
TMIF4
INTP0
PIF0
PMK0
PPR0
INTP1
PIF1
PMK1
PPR1
INTP2
PIF2
PMK2
PPR2
INTP3
PIF3
PMK3
PPR3
INTP4
PIF4
PMK4
PPR4
INTP5
PIF5
PMK5
PPR5
INTP6
PIF6
PMK6
PPR6
INTCSI0
CSIIF0
IF0H
TMMK4
CSIMK0
MK0L
Register
MK0H
TMPR4
CSIPR0
INTCSI1
CSIIF1
CSIMK1
CSIPR1
INTSER
SERIF
SERMK
SERPR
INTSR/INTCSI2
SRIF
SRMK
SRPR
INTST
STIF
STMK
STPR
INTTM3
TMIF3
TMMK3
TMPR3
INTTM00
TMIF00
TMMK00
TMPR00
INTTM01
TMIF01
TMMK01
TMPR01
INTTM1
TMIF1
INTTM2
TMIF2
TMMK2
TMPR2
INTAD
ADIF
ADMK
ADPR
INTIE
IEIF
IEMK
IEPR
394
IF1L
TMMK1
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TMPR1
PR0L
PR0H
PR1L
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(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction
is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request
or upon RESET input.
IF0L, IF0H, and IF1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used
as the 16-bit register IF0, use a 16-bit memory manipulation instruction for the setting.
RESET input clears these registers to 00H.
Figure 18-2. Format of Interrupt Request Flag Register
Symbol
IF0L
7
6
5
4
3
2
PIF6
PIF5
PIF4
PIF3
PIF2
PIF1
7
6
5
4
3
2
1
0
PIF0 TMIF4
1
IF1L WTIF
Note
6
5
4
3
0
0
0
IEIF
××IF
Note
2
1
After Reset
R/W
FFE0H
00H
R/W
FFE1H
00H
R/W
FFE2H
00H
R/W
0
IF0H TMIF01 TMIF00 TMIF3 STIF SRIF SERIF CSIIF1 CSIIF0
7
Address
0
ADIF TMIF2 TMIF1
Interrupt Request Flag
0
No interrupt request signal
1
Interrupt request signal is generated; Interrupt request state
WTIF is the test input flag. A vectored interrupt request is not generated.
Cautions 1. The TMIF4 flag is R/W enabled only when the watchdog timer is used as an interval timer.
If the watchdog timer is used in watchdog timer mode 1, set the TMIF4 flag to 0.
2. Always set bits 4 to 6 of IF1L to 0.
3. If an interrupt is acknowledged, the interrupt request flag is first cleared automatically,
and then the interrupt is entered.
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(2) Interrupt mask flag registers (MK0L, MK0H, MK1L)
The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set
standby clear enable/disable.
MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H
are used as the 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.
RESET input sets these registers to FFH.
Figure 18-3. Format of Interrupt Mask Flag Register
Symbol
7
6
5
4
3
2
1
MK0L PMK6 PMK5 PMK4 PMK3 PMK2 PMK
7
6
5
4
3
2
0
PMK TMMK4
1
MK1L WTMK
Note
6
5
4
1
1
1
3
1
R/W
FFE4H
FFH
R/W
FFE5H
FFH
R/W
FFE6H
FFH
R/W
0
IEMK ADMK TMMK2 TMMK1
××MK
Note
2
After
Reset
0
MK0H TMMK01 TMMK00 TMMK3 STMK SRMK SERMK CSIMK1 CSIMK0
7
Address
Interrupt Servicing Control
0
Interrupt servicing enabled
1
Interrupt servicing disabled
WTMK controls standby mode release enable/disable. This bit does not control the interrupt function.
Cautions 1. If the TMMK4 flag is read when the watchdog timer is used in watchdog timer mode 1,
the MK0 value becomes undefined.
2. Because port 0 also functions as the external interrupt request input, when the output
level is changed by specifying the output mode of the port function, an interrupt request
flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output
mode.
3. Always set bits 4 to 6 of MK1L to 1.
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(3) Priority specification flag registers (PR0L, PR0H, and PR1L)
The priority specify flag is used to set the corresponding maskable interrupt priority orders.
PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are
used as the 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.
RESET input sets these registers to FFH.
Figure 18-4. Format of Priority Specification Flag Register
Symbol
7
6
5
4
3
2
1
0
PR0L PPR6 PPR5 PPR4 PPR3 PPR2 PPR1 PPR0 TMPR4
7
6
5
4
3
2
1
PR1L
6
5
4
1
1
1
1
××PR
3
2
1
After
Reset
R/W
FFE8H
FFH
R/W
FFE9H
FFH
R/W
FFEAH
FFH
R/W
0
PR0H TMPR01TMPR00 TMPR3 STPR SRPR SERPR CSIPR1 CSIPR0
7
Address
0
IEPR ADPR TMPR2 TMPR1
Priority Level Selection
0
High priority level
1
Low priority level
Cautions 1. When the watchdog timer is used in watchdog timer mode 1, set the TMPR4 flag to 1.
2. Always set bits 4 to 7 of PR1L to 1.
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(4) External interrupt mode register (INTM0, INTM1)
These registers set the valid edge for INTP0 to INTP6.
INTM0 and INTM1 are set by an 8-bit memory manipulation instructions.
RESET input clears these registers to 00H.
Figure 18-5. Format of External Interrupt Mode Register 0
Symbol
7
6
5
4
3
2
INTM0 ES31 ES30 ES21 ES20 ES11 ES10
1
0
Address
After
Reset
R/W
0
0
FFECH
00H
R/W
ES31 ES30
INTP2 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
INTP1 Valid Edge Selection
ES21 ES20
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES11 ES10
INTP0 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
Caution When using the INTP0/TI00/P00 pin as timer input (TI00), be sure to set the valid edge after setting
bits 1 to 3 (TMC01 to TMC03) of 16-bit timer mode control register 0 (TMC0) to 0, 0, 0 to stop the
operation of 16-bit timer counter 0.
Note that when using the INTP0/TI00/P00 pin as external interrupt input (INTP0), the valid edge
can be set during operation of 16-bit timer counter 0.
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Figure 18-6. Format of External Interrupt Mode Register 1
Symbol
7
6
5
4
3
2
1
0
INTM1 ES71 ES70 ES61 ES60 ES51 ES50 ES41 ES40
ES71 ES70
Address
After
Reset
R/W
FFEDH
00H
R/W
INTP6 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES61 ES60
INTP5 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES51 ES50
INTP4 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
ES41 ES40
INTP3 Valid Edge Selection
0
0
Falling edge
0
1
Rising edge
1
0
Setting prohibited
1
1
Both falling and rising edges
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(5) Sampling clock select register (SCS)
This register is used to set the valid edge clock sampling clock to be input to INTP0. When remote control
data reception is carried out using INTP0, digital noise is eliminated using the sampling clock.
SCS is set with an 8-bit memory manipulation instruction.
RESET input clears SCS to 00H.
Figure 18-7. Format of Sampling Clock Select Register
Symbol
7
6
5
4
3
2
SCS
0
0
0
0
0
0
1
0
SCS1 SCS0
Address
After
Reset
R/W
FF47H
00H
R/W
INTP0 Sampling Clock Selection
SCS1 SCS0
N
0
0
fXX/2
0
1
fX/27 (31.3 kHz)
1
0
fX/25 (125.0 kHz)
1
1
fX/26 (62.5 kHz)
Caution fXX/2N is the clock to be supplied to the CPU and fXX/25, fXX/26 and fXX/27 are the clocks to be
supplied to the peripheral hardware. fXX/2N stops in the HALT mode.
Remarks 1. N:
Value (N = 0 to 4) set to bits 0 to 2 (PCC0 to PCC2) of the processor clock control register
(PCC)
2. fXX : Main system clock frequency
3. Values in parentheses apply to operation with fXX = 4.0 MHz.
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The noise eliminator sets the interrupt request flag (PIF0) to 1 if the input level of the sampled INTP0 is active
twice in succession.
Figure 18-8 shows the noise eliminator I/O timing.
Figure 18-8. Noise Eliminator I/O Timing (Rising Edge Detection)
(a) When input is less than the sampling cycle (tSMP)
tSMP
Sampling Clock
INTP0
"L"
PIF0
PIF0 output remains low because the level of INTP0 is not
high when it is sampled.
(b) When input is equal to or twice the sampling cycle (tSMP)
tSMP
Sampling Clock
INTP0
<1>
<2>
PIF0
The PIF0 flag is set to 1 because the sampled INTP0 level is high
twice in succession in <2>.
(c) When input is twice or more than the cycle frequency (tSMP)
tSMP
Sampling Clock
INTP0
PIF0
The PIF0 flag is set to 1 when INTP0 goes high twice in succession.
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(6) Program status word (PSW)
The program status word is a register to hold the instruction execution result and the current status for interrupt
requests. An IE flag used to set maskable interrupt enable/disable and an ISP flag used to control multiple
interrupt servicing are mapped to the PSW.
Besides 8-bit unit read/write, this register can carry out operations using bit manipulation instructions and
dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged or when the BRK
instruction is executed, the contents of the PSW are automatically saved to the stack and the IE flag is reset
to 0. If a maskable interrupt request is acknowledged, the contents of the priority specification flag of the
acknowledged interrupt are transferred to the ISP flag. The contents of the PSW are also saved to the stack
with the PUSH PSW instruction. The contents are restored from the stack with the RETI, RETB, and POP
PSW instructions.
RESET input sets the PSW to 02H.
Figure 18-9. Configuration of Program Status Word
PSW
7
6
5
4
3
2
1
0
After Reset
IE
Z
RBS1
AC
RBS0
0
ISP
CY
02H
Used when normal instruction is executed
ISP
0
402
Priority of Interrupt Currently Being Serviced
High-priority interrupt being serviced
(low-priority interrupts disabled)
1
Interrupt request not acknowledged or low-priority
interrupt being serviced
(all maskable interrupts enabled)
IE
Interrupt Request Acknowledge Enable/Disable
0
Disabled
1
Enabled
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18.4 Interrupt Servicing Operations
18.4.1 Non-maskable interrupt request acknowledge operation
A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledgement
disabled state. It does not undergo interrupt priority control and has highest priority over all other interrupts.
If a non-maskable interrupt request is acknowledged, the acknowledged interrupt is saved in the stack, PSW and
PC, in that order, the IE and ISP flags are reset to 0, and the vector table contents are loaded into the PC and branched.
A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program
is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following
RETI instruction execution) and one main routine instruction is executed. If a new non-maskable interrupt request
is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt
request is acknowledged after termination of the non-maskable interrupt service program execution.
Figure 18-10 shows the flowchart illustrating how the non-maskable interrupt request occurs and is acknowledged.
Figure 18-11 shows the acknowledgement timing of the non-maskable interrupt request. Figure 18-12 shows the
acknowledgement operation of multiple non-maskable interrupt requests.
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Figure 18-10. Non-Maskable Interrupt Request Occurrence and Acknowledgement Flowchart
Start
WDTM4 = 1
(with watchdog timer
mode selected)?
No
Interval timer
Yes
Overflow in WDT?
No
Yes
WDTM3 = 0
(with non-maskable
interrupt selected)?
No
Reset processing
Yes
Interrupt request generation
WDT interrupt servicing?
No
Interrupt request
held pending
Yes
Interrupt control
register unaccessed?
No
Yes
Interrupt
service start
WDTM: Watchdog timer mode register
WDT:
Watchdog timer
Figure 18-11. Non-Maskable Interrupt Request Acknowledgement Timing
CPU Instruction
Instruction
Instruction
PSW and PC Save, Jump Interrupt Servicing
to Interrupt Servicing
Program
TMIF4
An interrupt request generated during
this period is acknowledged at the
timing marked .
TMIF4:
404
Watchdog timer interrupt request flag
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Figure 18-12. Non-Maskable Interrupt Request Acknowledgement Operation
(a)
If a new non-maskable interrupt request is generated during
non-maskable interrupt servicing program execution
Main Routine
NMI Request <1>
NMI Request <2>
NMI Request <1> Executed.
NMI Request <2> Held.
1 Instruction Execution
Held NMI Request <2> Processed.
(b)
If two non-maskable interrupt requests are generated during
non-maskable interrupt servicing program execution
Main Routine
NMI Request <1>
NMI Request <2>
1 Instruction Execution
NMI Request <3>
NMI Request <1> Executed.
NMI Request <2> Held.
NMI Request <3> Held.
Held NMI Request <2> Processed.
NMI Request <3> is not acknowledged.
Even if more than 2 NMI requests are generated,
they can only be acknowledged 1 at a time.
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18.4.2 Maskable interrupt request acknowledgement operation
A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the interrupt
mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enabled state (with the
IE flag set to 1). However, a low-priority interrupt is not acknowledged during high-priority interrupt servicing (with
the ISP flag reset to 0).
Wait times from maskable interrupt request generation to interrupt servicing are shown in Table 18-3.
Figures 18-14 and 18-15 show interrupt request acknowledge timing.
Table 18-3. Times from Maskable Interrupt Request Generation to Interrupt Servicing
Minimum Time
Maximum Time Note
When ××PR = 0
7 clocks
32 clocks
When ××PR = 1
8 clocks
33 clocks
Note If an interrupt request is generated just before a divide instruction, the wait time is the maximum
value.
Remark
1 clock :
1
(fCPU: CPU clock)
fCPU
If two or more maskable interrupt requests are generated simultaneously, the request specified as the higher priority
with the priority specification flag is acknowledged first. If two or more requests are specified as the same priority
by the interrupt priority specification flag, the one with the higher default priority is acknowledged first.
Any pending interrupt requests are acknowledged when they become acknowledgeable.
Figure 18-13 shows interrupt request acknowledgement algorithms.
If a maskable interrupt request is acknowledged, the contents of the acknowledged interrupt are saved in the stack,
program status word (PSW) and program counter (PC), in that order, the IE flag is reset to 0, and the acknowledged
interrupt priority specification flag contents are transferred to the ISP flag. Further, the vector table data determined
for each interrupt request is loaded into the PC and branched.
Return from the interrupt is possible with the RETI instruction.
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Figure 18-13. Interrupt Request Acknowledgement Processing Algorithm
Start
No
× × IF = 1?
Yes (Interrupt Request
Generation)
No
× × MK = 0?
Yes
Interrupt request
held pending
Yes (High priority)
× × PR = 0?
No (Low Priority)
Any highpriority interrupt among
simultaneously generated
××PR = 0 interrupt
requests?
Yes
Interrupt request
held pending
Any
Simultaneously
generated ××PR = 0
interrupt
requests?
No
No
Interrupt request
held pending
No
Any
Simultaneously
generated high-priority
interrupt
requests?
IE = 1?
Yes
Interrupt request
held pending
Yes
Vectored interrupt
servicing
Yes
Interrupt request
held pending
No
IE = 1?
No
Interrupt request
held pending
Yes
ISP = 1?
Yes
No
Interrupt request
held pending
Vectored interrupt
servicing
××IF:
Interrupt request flag
××MK:
Interrupt mask flag
××PR:
Priority specify flag
IE:
Flag that controls maskable interrupt request acknowledgement (1 = enable, 0 = disable)
ISP:
Flag indicating priority of interrupt currently being serviced (0 = interrupt with high priority is being
serviced. 1 = interrupt request is not acknowledged or interrupt with low priority is being serviced).
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Figure 18-14. Interrupt Request Acknowledgement Timing (Minimum Time)
6 Clocks
CPU Processing
Instruction
Instruction
PSW and PC Save,
Jump to Interrupt
Servicing
Interrupt
Servicing
Program
× × IF
(× × PR = 1)
8 Clocks
× × IF
(× × PR = 0)
7 Clocks
Remark
1 clock:
1
(fCPU: CPU clock)
fCPU
Figure 18-15. Interrupt Request Acknowledgement Timing (Maximum Time)
25 Clocks
CPU Processing
Instruction
Divide Instruction
× × IF
(× × PR = 1)
33 Clocks
× × IF
(× × PR = 0)
32 Clocks
Remark
408
1 clock:
1
(fCPU: CPU clock)
fCPU
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PSW and PC Save,
Jump to Interrupt
Servicing
Interrupt
Servicing
Program
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18.4.3 Software interrupt request acknowledgement operation
A software interrupt request is acknowledged by the execution of a BRK command. A software interrupt cannot
be disabled.
If a software interrupt request is acknowledged, the contents of the program status word (PSW) and the program
counter (PC) are saved to the stack in that order, the IE flag is reset (to 0) and the contents of the vector table (003EH,
003FH) are loaded into the PC and branched.
Return from the software interrupt is possible with the RETB instruction.
Caution Do not use the RETI instruction for returning from the software interrupt.
18.4.4 Multiple interrupt servicing
During interrupt servicing, the capacity to receive other distinct interrupt requests is called multiple interrupts.
Multiple interrupts are not generated (except for non-maskable interrupts) unless acknowledgement of interrupt
requests is enabled (IE = 1). However, at the point when an interrupt request is acknowledged, further acknowledgement
of an interrupt request is disabled (IE = 0), so to enable multiple interrupts, it is necessary to set the IE flag at (1)
by the IE command during interrupt servicing and enable interrupt acknowledgement.
Also, even if interrupt acknowledgement is enabled, there are some cases when multiple interrupts are not enabled,
but that is controlled by the interrupts’ priority order. There are two types of interrupt priorities, the default priority
and the programmable priority, but control of multiple interrupts is controlled by the programmable priority.
In the interrupt enabled state, if an interrupt request is generated with the same or higher priority than the interrupt
currently being serviced, it is acknowledged as a multiple interrupt. If an interrupt request with a lower priority than
the interrupt currently being serviced is generated, it is not acknowledged as a multiple interrupt.
An interrupt request generated while interrupts are disabled, or when multiple interrupts are not enabled due to
the interrupt request’s low priority, is held pending. Then, when the interrupt servicing currently in progress is
completed, the interrupt request is acknowledged after 1 main servicing command has been executed.
Note that multiple interrupts are not enabled during servicing of a non-maskable interrupt.
Table 18-4 shows interrupt requests that can be multiple interrupts and Figure 18-16 shows an example of multiple
interrupts.
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Table 18-4. Interrupt Requests Enabled as Multiple Interrupts During Interrupt Servicing
Multiple Interrupt
Request
Interrupt Currently
Being Serviced
PR = 0
PR = 1
IE = 1
IE = 0
IE = 1
IE = 0
D
D
D
D
D
ISP = 0
E
E
D
D
D
ISP = 1
E
E
D
E
D
E
E
D
E
D
Non-maskable interrupt
Maskable interrupt
Maskable Interrupt Request
Non-Maskable
Interrupt
Request
Software interrupt
Remarks 1. E:
Multiple interrupt enable
2. D:
Multiple interrupt disable
3. ISP and IE are the flags contained in the PSW
ISP = 0: An interrupt with higher priority being serviced
ISP = 1: An interrupt request is not acknowledged or an interrupt with a lower
priority is being serviced
IE = 0:
Interrupt request acknowledgement is disabled
IE = 1:
Interrupt request acknowledgement is enabled
4. PR is a flag contained in PR0L, PR0H, and PR1L
410
PR = 0:
Higher priority level
PR = 1:
Lower priority level
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Figure 18-16.
INTERRUPT AND TEST FUNCTIONS
Example of Multiple Interrupts (1/2)
Example 1 Example of multiple interrupt requests being generated twice
Main Processing
INTxx
Servicing
IE = 0
INTyy
Servicing
IE = 0
IE = 0
EI
EI
INTxx
(PR = 1)
INTzz
Servicing
EI
INTyy
(PR = 0)
INTzz
(PR = 0)
RETI
RETI
RETI
During servicing of interrupt INTxx, 2 interrupt requests, INTyy and INTzz, are acknowledged and
multiple interrupts are generated. Before reception of each interrupt request, the IE command must
be issued and the interrupt request acknowledgement enabled state must exist.
Example 2 Example of multiple interrupts not being generated due to priority order control
Main Processing
EI
INTxx
Servicing
INTyy
Servicing
IE = 0
EI
INTyy
(PR = 1)
INTxx
(PR = 0)
RETI
1 Instruction
Execution
IE = 0
RETI
During servicing of interrupt INTxx, interrupt request INTyy was generated, but the priority order of
this interrupt was lower than that of INTxx, so it was not acknowledged and multiple interrupts were
not generated. Interrupt request INTyy was held pending and acknowledged after 1 main processing
command was executed.
PR = 0:
High priority order level
PR = 1:
Low priority order level
IE = 0:
Interrupt request acknowledgement disabled
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Figure 18-16.
INTERRUPT AND TEST FUNCTIONS
Example of Multiple Interrupts (2/2)
Example 3 Example of a multiple interrupt not being generated because an interrupt was not enabled
Main Processing
INTxx
Servicing
INTyy
Servicing
IE = 0
EI
INTyy
(PR = 0)
INTxx
(PR = 0)
RETI
1 Instruction
Execution
IE = 0
RETI
During servicing of interrupt INTxx, interrupt acknowledgement was not enabled (the IE command
was not issued), so interrupt request INTyy was not acknowledged and multiple interrupts were not
generated. Interrupt request INTyy was held and acknowledged after 1 main processing command
was executed.
PR = 0: High priority order level
IE = 0:
412
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INTERRUPT AND TEST FUNCTIONS
18.4.5 Interrupt request pending
Among the commands, there are some for which acknowledgement of the interrupt request is held pending until
execution of the next command is completed, even if an interrupt request is generated while they are being executed.
The commands of this type (interrupt request hold commands) are shown below.
• MOV PSW, #byte
• MOV A, PSW
• MOV PSW, A
• MOV1 PSW.bit, CY
• MOV1 CY, PSW.bit
• AND1 CY, PSW.bit
• OR1 CY, PSW.bit
• XOR1 CY, PSW.bit
• SET1 PSW.bit
• CLR1 PSW.bit
• RETB
• RETI
• PUSH PSW
• POP PSW
• BT PSW.bit, $addr16
• BF PSW.bit, $addr16
• BTCLR PSW.bit, $addr16
• EI
• DI
• Manipulation instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0, INTM1
registers
Caution The BRK command is not an interrupt request hold command like those above. However, in a
software interrupt that is started by execution of the BRK command, the IE flag is cleared to 0.
Therefore, even if a maskable interrupt is generated during execution of the BRK command, the
interrupt request is not acknowledged. However, a non-maskable interrupt request is acknowledged.
The timing for holding an interrupt request pending is shown in Figure 18-17.
Figure 18-17. Interrupt Request Hold
CPU processing
Instruction N
Instruction M
Save PSW and PC,
Jump to interrupt servicing
Interrupt service
program
× × IF
Remarks 1. Instruction N: Instruction that holds interrupts requests pending
2. Instruction M: Instructions other than instruction N
3. The × ×IF (interrupt request) operation is not affected by the value of × ×PR (priority order level).
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18.5 Test Functions
The test function sets the corresponding test input flag to 1 and generates a standby release signal when the watch
timer overflows and when the falling edge of port 4 is detected.
Unlike the interrupt function, this function does not perform vector processing.
There are two test input factors as shown in Table 18-5. The basic configuration is shown in Figure 18-18.
Table 18-5. Test Input Factors
Test Input Factors
Name
Internal/
External
Trigger
INTWT
Watch timer overflow
Internal
INTPT4
Falling edge detection at port 4
External
Figure 18-18. Basic Configuration of Test Function
Internal Bus
MK
Test Input
Signal
IF:
Standby
Release Signal
IF
Test input flag
MK: Test mask flag
18.5.1 Registers controlling the test function
The test function is controlled by the following three registers.
• Interrupt request flag register 1L (IF1L)
• Interrupt mask flag register 1L (MK1L)
• Key return mode register (KRM)
The names of the test input flags and test mask flags corresponding to the test input signals are listed in Table
18-6.
Table 18-6. Flags Corresponding to Test Input Signals
Test Input Signal Name
INTWT
INTPT4
414
Test Input Flag
WTIF
KRIF
Test Mask Flag
WTMK
KRMK
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(1) Interrupt request flag register 1L (IF1L)
This register indicates whether a watch timer overflow is detected or not.
IF1L is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input clears IF1L to 00H.
Figure 18-19. Format of Interrupt Request Flag Register 1L
Symbol
7
IF1L WTIF
6
5
4
3
0
0
0
IEIF
2
1
0
ADIF TMIF2 TMIF1
WTIF
Address
After Reset
R/W
FFE2H
00H
R/W
Watch Timer Overflow Detection Flag
0
Not detected
1
Detected
Caution Be sure to set bits 4 to 6 to 0.
(2) Interrupt mask flag register 1L (MK1L)
This register is used to set the standby mode enable/disable at the time the standby mode is released by the
watch timer.
MK1L is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets MK1L to FFH.
Figure 18-20. Format of Interrupt Mask Flag Register 1L
Symbol
7
MK1L WTMK
WTMK
6
5
4
1
1
1
3
2
1
0
IEMK ADMK TMMK2 TMMK1
Address
After Reset
R/W
FFE6H
FFH
R/W
Standby Mode Control by Watch Timer
0
Enables releasing the standby mode.
1
Disables releasing the standby mode.
Caution Be sure to set bits 4 to 6 to 1.
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(3) Key return mode register (KRM)
This register is used to set enable/disable of standby function clear by key return signal (port 4 falling edge
detection).
KRM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets KRM to 02H.
Figure 18-21. Format of Key Return Mode Register
Symbol
7
6
5
4
3
2
KRM
0
0
0
0
0
0
KRMK
1
0
KRMK KRIF
Address
After
Reset
R/W
FFF6H
02H
R/W
Standby Mode Control by Key Return Signal
0
Standby mode release enabled
1
Standby mode release disabled
KRIF
Key Return Signal
0
Not detected
1
Detected (port 4 falling edge detection)
Caution When port 4 falling edge detection is used, be sure to clear KRIF to 0 (KRIF is not cleared
to 0 automatically).
18.5.2 Test input signal acknowledge operation
(1) Internal test signal (INTWT)
The internal test input signal (INTWT) is generated by a clock timer overflow and according to this, the WTIF
flag is set. At this time, a standby release signal is generated if it is not masked by an interrupt mask flag
(WTMK). Because the WTIF flag is checked for a shorter period than the clock timer’s overflow period, the
clock function can be realized.
(2) External test input signal (INTPT4)
The external test input signal (INPT4) is generated when the falling edge is input to the port 4 (P40 to P47)
pins, and according to this, the KRIF flag is set. At this time, a standby release signal is generated if it is not
masked by the KRMK flag. By using port 4 as the key matrix key return signal input, it can be checked whether
there is key input or not by the status of the KRIF flag.
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CHAPTER 19
EXTERNAL DEVICE EXPANSION FUNCTION
EXTERNAL DEVICE EXPANSION FUNCTION
19.1 External Device Expansion Function
The external device expansion function connects external devices to areas other than the internal ROM, RAM,
and SFR. Connection of external devices is performed using ports 4 to 6. Ports 4 to 6 control address/data, read/
write strobe, wait, address strobe etc.
Caution When generating the main system clock, the external device expansion function cannot be used
if the 2/3 divider (in divider 1) of the clock generator is used.
Table 19-1. Pin Functions in External Memory Expansion Mode
Pin Function When External Device Is Connected
Name
Alternate Function
Function
AD0 to AD7
Multiplexed address/data bus
P40 to P47
A8 to A15
Address bus
P50 to P57
RD
Read strobe signal
P64
WR
Write strobe signal
P65
WAIT
Wait signal
P66
ASTB
Address strobe signal
P67
Table 19-2. State of Ports 4 to 6 Pins in External Memory Expansion Mode
Ports and Bits
Port 4
Modes
0 to 7
Port 5
0
1
2
3
4
Port 6
5
6
7
0-3
4 to 7
Single-chip mode
Port
Port
Port
Port
256-byte expansion mode
Address/data
Port
Port
RD, WR, WAIT, ASTB
4 KB expansion mode
Address/data
Address
Port
RD, WR, WAIT, ASTB
16 KB expansion mode
Address/data
Address
Port
RD, WR, WAIT, ASTB
Full address mode
Address/data
Address
Port
RD, WR, WAIT, ASTB
Port
Port
Caution When the external wait function is not used, the WAIT pin can be used as a port in all modes.
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Memory maps when using the external device expansion function are as follows.
Figure 19-1. Memory Map When Using External Device Expansion Function (1/2)
(a) Memory map of µPD78095B and µPD78P098B
when internal PROM capacity is 40 KB
(b) Memory map of µPD78096B and µPD78P098B
when internal PROM capacity is 48 KB
FFFFH
FF00H
FEFFH
FFFFH
SFR
FF00H
FEFFH
Internal High-Speed RAM
Internal High-Speed RAM
FB00H
FAFFH
FAE0H
FADFH
FB00H
FAFFH
Reserved
FAE0H
FADFH
Buffer RAM
FAC0H
FABFH
Reserved
Reserved
F900H
F8FFH
F000H
EFFFH
F900H
F8FFH
IEBus Register
F8E0H
F8DFH
Reserved
F000H
EFFFH
Full-Address Mode
(when MM2 to MM0 = 111)
or
16 KB Expansion Mode
(when MM2 to MM0 = 101)
B000H
AFFFH
A000H
9FFFH
Reserved
D000H
CFFFH
256-byte Expansion Mode
(when MM2 to MM0 = 011)
4 KB Expansion Mode
(when MM2 to MM0 = 100)
C100H
C0FFH
C000H
BFFFH
Single-Chip Mode
256-byte Expansion Mode
(when MM2 to MM0 = 011)
Single-Chip Mode
0000H
418
IEBus Register
Full-Address Mode
(when MM2 to MM0 = 111)
or
16 KB Expansion Mode
(when MM2 to MM0 = 101)
4 KB Expansion Mode
(when MM2 to MM0 = 100)
A100H
A0FFH
Reserved
Buffer RAM
FAC0H
FABFH
F8E0H
F8DFH
SFR
0000H
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EXTERNAL DEVICE EXPANSION FUNCTION
Figure 19-1. Memory Map When Using External Device Expansion Function (2/2)
(c) Memory map of µPD78098B and µPD78P098B
when internal ROM (PROM) capacity is 56 KB
(d) Memory map of µPD78098B and µPD78P098B
when internal PROM capacity is 60 KB
FFFFH
FF00H
FEFFH
FFFFH
SFR
FF00H
FEFFH
Internal High-Speed RAM
Internal High-Speed RAM
FB00H
FAFFH
FAE0H
FADFH
FB00H
FAFFH
Reserved
FAE0H
FADFH
Buffer RAM
FAC0H
FABFH
Reserved
Reserved
F900H
F8FFH
F800H
F7FFH
Reserved
Buffer RAM
FAC0H
FABFH
F8E0H
F8DFH
SFR
F900H
F8FFH
IEBus Register
F8E0H
F8DFH
Reserved
F800H
F7FFH
Internal Expansion RAM
IEBus Register
Reserved
Internal Expansion RAM
F000H
EFFFH
F000H
EFFFH
Full-Address Mode
(when MM2 to MM0 = 111)
or
4 KB Expansion Mode
(when MM2 to MM0 = 100)
E100H
E0FFH
E000H
DFFFH
256-byte Expansion Mode
(when MM2 to MM0 = 011)
Single-Chip Mode
Single-Chip Mode
0000H
0000H
Caution When the internal ROM (PROM) capacity is 60 KB, the external device expansion function cannot
be used. When the internal ROM (PROM) capacity is set to 56 KB or lower by using the memory
size switching register (IMS), the last address of the internal ROM (PROM) through address
EFFFH can be used as an external memory.
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19.2
EXTERNAL DEVICE EXPANSION FUNCTION
Registers Controlling External Device Expansion Function
The external device expansion function is controlled by the memory expansion mode register (MM) and memory
size switching register (IMS).
(1) Memory expansion mode register (MM)
MM sets the wait count and external expansion area, and also sets the input/output of port 4.
MM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 10H.
Figure 19-2. Format of Memory Expansion Mode Register
Symbol
7
6
5
4
3
2
MM
0
0
PW1
PW0
0
MM2
PW1
PW0
0
0
No wait
0
1
Wait (one wait state insertion)
1
0
Setting prohibited
1
1
Wait control by external wait pin
MM2 MM1
0
0
1
0
MM1 MM0
Address
After
Reset
R/W
FFF8H
10H
R/W
Wait Control
MM0
Single-Chip/
Memory Expansion
Mode Selection
0
Single-chip mode
0
0
1
0
1
1
256-byte
mode
0
4 KB
mode
P40 to P47, P50 to P57, P64 to P67 Pin state
P40 to P47 P50 to P53 P54, P55
Port Input
mode Output
P56, P57
P64 to P67
Port mode
Port mode
P64 = RD
1
1
0
0
Memory
expansion
mode
Port mode
P66 = WAIT
AD0 to AD7
1
16 KB
mode
1
Fulladdress
Note
mode
P65 = WR
Port mode P67 = ASTB
A8 to A11
A12, A13
1
1
Other than above
Note
A14, A15
Setting prohibited
The full-address mode allows external expansion to the entire 64 KB address space except for the
internal ROM, RAM, and SFR areas and the reserved areas.
Remark
P60 to P63 are used as port pins without regard to the mode (single-chip mode or memory expansion
mode).
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(2) Memory size switching register (IMS)
This register specifies the internal memory size. In principle, use IMS in the default status. However, when
using the external device expansion function with the µPD78098B, set IMS so that the internal ROM capacity
is 56 KB or lower.
IMS is set with an 8-bit memory manipulation instruction.
RESET input sets this register to the value indicated in Table 19-3.
Figure 19-3. Format of Memory Size Switching Register
Symbol
7
6
5
IMS RAM2 RAM1 RAM0
4
0
3
2
1
ROM3 ROM2 ROM1 ROM0
RAM2 RAM1 RAM0
1
1
0
Other than above
After
reset
R/W
FFF0H
Note
R/W
1,024 bytes
Setting prohibited
Internal ROM Size Selection
1
0
1
0
40 KB
1
1
0
0
48 KB
1
1
1
0
56 KB
1
1
1
1
60 KB
Note
Address
Internal High-Speed RAM Size Selection
ROM3 ROM2 ROM1 ROM0
Other than above
0
Setting prohibited
The values after reset depend on the product. (See Table 19-3)
Table 19-3. Values After Memory Size Switching Register Is Reset
Part Number
Reset Value
µPD78095B
CAH
µPD78096B
CCH
µPD78098B
CFH
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19.3 External Device Expansion Function Timing
The timing control signal output pins in the external memory expansion mode are as follows.
(1) RD pin (Alternate function: P64)
Read strobe signal output pin. The read strobe signal is output in data accesses and instruction fetches from
external memory.
During internal memory access, the read strobe signal is not output (maintains high level).
(2) WR pin (Alternate function: P65)
Write strobe signal output pin. The write strobe signal is output in data access to external memory.
During internal memory access, the write strobe signal is not output (maintains high level).
(3) WAIT pin (Alternate function: P66)
External wait signal input pin. When the external wait is not used, the WAIT pin can be used as an I/O port.
During internal memory access, the external wait signal is ignored.
(4) ASTB pin (Alternate function: P67)
Address strobe signal output pin. Timing signal is output without regard to data accesses and instruction
fetches from external memory. The ASTB signal is also output when the internal memory is accessed.
(5) AD0 to AD7, A8 to A15 pins (Alternate function: P40 to P47, P50 to P57)
Address/data signal output pin. A valid signal is output or input during data accesses and instruction fetches
from external memory.
These signals change when the internal memory is accessed (output values are undefined).
Timing charts are shown in Figure 19-4 to 19-7.
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Figure 19-4. Instruction Fetch from External Memory
(a) No wait setting (PW1, PW0 = 0, 0)
ASTB
RD
AD0 to AD7
A8 to A15
Lower Address
Operation Code
Higher Address
(b) Wait setting (PW1, PW0 = 0, 1)
ASTB
RD
AD0 to AD7
Lower Address
A8 to A15
Operation Code
Higher Address
Internal Wait Signal
(1-clock wait)
(c) External wait setting (PW1, PW0 = 1, 1)
ASTB
RD
AD0 to AD7
A8 to A15
Lower Address
Operation Code
Higher Address
WAIT
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Figure 19-5. External Memory Read Timing
(a) No wait setting (PW1, PW0 = 0, 0)
ASTB
RD
AD0 to AD7
Lower Address
A8 to A15
Read Data
Higher Address
(b) Wait setting (PW1, PW0 = 0, 1)
ASTB
RD
AD0 to AD7
Lower Address
A8 to A15
Read Data
Higher Address
Internal Wait Signal
(1-clock wait)
(c) External wait setting (PW1, PW0 = 1, 1)
ASTB
RD
AD0 to AD7
A8 to A15
Lower Address
Read Data
Higher Address
WAIT
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Figure 19-6. External Memory Write Timing
(a) No wait setting (PW1, PW0 = 0, 0)
ASTB
WR
AD0 to AD7
Lower Address
Hi-Z
Write Data
Higher Address
A8 to A15
(b) Wait setting (PW1, PW0 = 0, 1)
ASTB
WR
AD0 to AD7
Lower Address
Hi-Z
Write Data
Higher Address
A8 to A15
Internal Wait Signal
(1-clock wait)
(c) External wait setting (PW1, PW0 = 1, 1)
ASTB
WR
AD0 to AD7
A8 to A15
Lower Address
Hi-Z
Write Data
Higher Address
WAIT
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Figure 19-7. External Memory Read Modify Write Timing
(a) No wait setting (PW1, PW0 = 0, 0)
ASTB
RD
WR
AD0 to AD7
Lower Address
Hi-Z
Read Data
Write Data
Higher Address
A8 to A15
(b) Wait setting (PW1, PW0 = 0, 1)
ASTB
RD
WR
AD0 to AD7
Lower Address
Read Data
Hi-Z
Write Data
Higher Address
A8 to A15
Internal Wait Signal
(1-clock wait)
(c) External wait setting (PW1, PW0 = 1, 1)
ASTB
RD
WR
AD0 to AD7
A8 to A15
Lower Address
Read Data
Hi-Z
Higher Address
WAIT
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CHAPTER 19
EXTERNAL DEVICE EXPANSION FUNCTION
19.4 Example of Connection with Memory
An example of connecting the µPD78095B with external memory (in this example, SRAM) is shown in Figure 198. In this example, the external device expansion function is used in the full-address mode, and the addresses from
0000H to 9FFFH (40 KB) are allocated to internal ROM, and the addresses after A000H to SRAM.
Figure 19-8. Connection Example of µPD78095B and Memory
VDD
µ PD78095B
µ PD43256B
CS
RD
OE
WR
WE
I/O1 to I/O8
Data Bus
Address Bus
A8 to A14
ASTB
A0 to A14
74HC573
LE
Q0 to Q7
AD0 to AD7
D0 to D7
OE
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CHAPTER 20
IEBus CONTROLLER
CHAPTER 20 IEBus CONTROLLER
20.1 IEBus Controller Function
IEBus (Inter-Equipment BusTM) is a small-scale digital data transfer system that transfers data between equipment.
To implement IEBus with the µPD78098B Subseries, an external IEBus driver/receiver is required because the
µPD78098B Subseries is not provided with an IEBus driver/receiver.
The internal IEBus controller of the µPD78098B Subseries can select positive logic/negative logic via software
in accordance with the external IEBus driver/receiver (refer to 20.4 (2) IEBus controller mode register).
20.1.1 IEBus communication protocol
The communication protocol of IEBus is as follows:
(1) Multi-master mode
All the units connected to IEBus can transfer data to the other units.
(2) Broadcast communication function
Normally, communication is individually carried out from one unit to another. By using the broadcast
communication function, however, communication can be executed from one unit to plural units as follows:
• Group broadcast communication: Broadcast communication to group units
• Simultaneous broadcast communication: Broadcast communication to all units
(3) Effective transmission rate
The effective transmission rate can be selected from the following three communication modes:
• Communication mode 0: About 3.9 kbps
• Communication mode 1: About 17 kbps
• Communication mode 2: About 26 kbps
Caution Different modes must not exist together on one IEBus.
(4) Communication method
Data is transferred by the half-duplex synchronous communication method.
(5) Access control: CSMA/CD (Carrier Sense Multiple Access with Collision Detection)
The priority of occupying IEBus is as follows:
<1> Broadcast communication takes precedence over individual communication.
<2> The lower the master address, the higher the priority.
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IEBus CONTROLLER
(6) Communication scale
The communication scale of IEBus is as follows:
• Number of units: 50 MAX.
• Cable length: 150 m MAX. (when a twisted pair cable is used)
Caution The communication scale in an actual system differs depending on the IEBus driver/receiver
and the characteristics of the cable configuring the IEBus.
20.1.2 Determining bus mastership (arbitration)
Equipment (unit) connected to IEBus performs an operation to occupy the bus when it controls the other equipment.
This operation is called arbitration.
When two or more units start transmission, one of the units is selected and granted the permission to occupy the
bus as a result of arbitration.
Because only one unit occupies the bus as a result of arbitration, the priority is determined as follows. The bus
mastership is released if communication is aborted.
(1) Priority according to type of communication
Broadcast communication (communication between one unit and plural units) takes precedence over
individual communication (communication between one unit and another).
(2) Priority by master address
If the type of communication is the same, communication with the lower master address takes precedence.
A master address consists of 12 bits. The unit with address 000H has the highest priority, and the unit with
FFFH has the lowest priority.
20.1.3 Communication mode
IEBus has three communication modes each having a different transmission rate. The transmission rate in each
communication mode and the maximum number of bytes transmitted in one communication frame are listed in Table
20-1.
Table 20-1. Transmission Rate in Each Communication Mode and Maximum Number of Transmit Bytes
Communication Mode
Note
Effective Transmission Rate (kbps)Note
Maximum Number of Transmit Bytes (Bytes/Frame)
0
About 3.9
16
1
About 17
32
2
About 26
128
Effective transmission rate when the maximum number of bytes is transmitted.
Each unit connected to IEBus selects a communication mode before starting communication. If the master unit
and the other units (slave units) are not in the same communication mode, communication is not performed correctly.
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20.1.4 Communication address
Each unit connected to IEBus is assigned a specific 12-bit address. This communication address is configured
as follows:
Higher 4 bits: Group number (number identifying group to which each unit belongs)
Lower 8 bits: Unit number (number identifying each unit in a group)
20.1.5 Broadcast communication
In normal individual communication, the master unit communicates with a slave unit on a one-to-one basis. In
broadcast communication, the master unit transmits data to more than one slave unit (the master unit does not receive
data). Because more than one slave unit exists, the slave units do not return an acknowledge signal to the master
unit during communication.
Whether broadcast communication or individual communication is executed can be selected by a broadcast bit
(for the broadcast bit, refer to 20.2.1 (1) Header).
Broadcast communication can be classified into the following two types:
(1) Group broadcast communication
Broadcast communication is performed for the units of the same group number (which is indicated by the higher
4 bits of the communication address).
(2) Simultaneous broadcast communication
Broadcast communication is performed for all the units, regardless of the group number.
Group broadcast communication and simultaneous broadcast communication are identified by the value of the
slave address (for the slave address, refer to 20.2.1 (4) Slave address field).
20.2 Transmission System of IEBus
20.2.1 Transmit signal format of IEBus
Figure 20-1 shows the transmit signal format of IEBus.
Figure 20-1. Transmit Signal Format of IEBus
MSB
Start
Bit
LSB
Broad- Master
Address
cast
Bit
Bit
Header
Master
Address
Field
P
Slave
Address
Bit
P A
Slave
Address
Field
Control
Bit
P A
Control Field
Message
Length P A Data Bit P A
Bit
Message
Length
Field
Data Bit P A
Data Field
Remarks 1. P: Parity bit, A: ACK/NAK bit
2. The master unit ignores the acknowledge bit during broadcast communication.
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(1) Header
A header consists of a start bit and a broadcast bit.
• Start bit
The start bit is a signal that informs the other units of the start of data transfer.
The unit that is to start data transfer outputs a low-level signal for a specified time. This signal is the start
bit.
• Broadcast bit
The broadcast bit indicates whether the master selects a single slave (individual communication) as the
other party of communication, or plural slaves (broadcast communication).
If the broadcast bit is 0, broadcast communication is selected; if it is 1, individual communication is selected.
Broadcast communication is classified into group broadcast communication and simultaneous broadcast
communication, which are identified by the value of a slave address (for the slave address, refer to (4) Slave
address field).
If a unit occupies the bus as the master, the value set to the broadcast bit (bit 7) of the master communication
control register is output.
(2) Parity bit and acknowledge bit
• Parity bit
The parity bit is used to check that no error has occurred during transmission.
The parity is an even parity. Therefore, a parity bit is appended to the end of each data so that the number
of bits that are “1” in the data to be transmitted is even. If the number of bits that are “1” is odd, the parity
bit is “1”; if the number of bits that are “1” is even, the parity bit is 0.
The data to which the parity bit is to be appended are as follows. For the details of each data, refer to (3)
to (7).
• Master address bit
• Slave address bit
• Control bit
• Message length bit
• Data bit
• Acknowledge bit
The acknowledge bit is an acknowledge signal that is output by the unit on the reception side. In individual
communication, the acknowledge bit is appended to check whether data has been correctly received.
The definition of the acknowledge bit is as follows:
“0”: Transmit data is recognized (ACK).
“1”: Transmit data is not recognized (NAK).
The acknowledge bit is appended to the end of each of the following fields. For the details of each field,
refer to (3) to (7).
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• Slave address field
• Control field
• Message length field
• Data field
When broadcast communication is performed, the contents of the acknowledge bit are ignored.
(3) Master address field
This field is output by the master unit to inform the slave unit of the address and parity bit of the master unit.
Figure 20-2 shows the configuration of the master address field.
Figure 20-2. Configuration of Master Address Field
Master Address Bits (12 bits)
Parity
MSB
LSB
If a unit occupies the bus as the master, the address set by unit address registers 1 and 2 (UAR1 and UAR2)
is output as the master address.
(4) Slave address field
The master unit outputs the address of a slave unit with which the master unit is to communicate individually,
and a parity bit to this field.
In the case of broadcast communication, a value to identify group broadcast communication or simultaneous
broadcast communication is output as a slave address, as follows:
• If slave address is FFFH:
Simultaneous broadcast communication
• If slave address is other than FFFH: Group broadcast communication
Figure 20-3 shows the configuration of the slave address field.
Figure 20-3. Configuration of Slave Address Field
Slave Address Bits (12 bits)
Group No.
Parity
ACK
Unit No.
MSB
LSB
If a unit occupies the bus as the master unit, the address set by slave address registers 1 and 2 (SAR1 and
SAR2) is output as the slave address.
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(5) Control field
The master unit outputs a value by which it requests the slave unit for an operation, and a parity bit to this
field. In response, the slave unit outputs an acknowledge bit.
Figure 20-4 shows the configuration of the control field.
Figure 20-4. Configuration of Control Field
Control Bits (4 bits)
MSB
Parity
ACK
LSB
If a unit occupies the bus as the master unit, the value set by the control bits of the master communication
control register (MCR) is output.
The contents of the control bits are shown in Table 20-2.
Table 20-2. Contents of Control Bits
Bit 3 Note 1
Bit 2
Bit 1
Bit 0
0
0
0
0
Reads slave status.
0
0
1
1
Reads data and locks unit Note 2.
0
1
0
0
Reads lock address (lower 8 bits) Note 3.
0
1
0
1
Reads lock address (higher 4 bits) Note 3.
0
1
1
0
Reads slave status and unlocks unit Note 2.
0
1
1
1
Reads data.
1
0
1
0
Writes command and locks unit.
1
0
1
1
Writes data and locks unit.
1
1
1
0
Writes command
1
1
1
1
Writes data
Other than above
Function
Undefined
Notes 1. The data transfer direction of the message length bit and data field of the subsequent message
length field is changed depending on the value of bit 3 (MSB).
When bit 3 is “0”: Transfer from slave unit to master unit
When bit 3 is “1”: Transfer from master unit to slave unit
2. For the lock function, refer to 20.5.6 Lock function.
3. For the lock address, refer to 20.2.3 (3) Lock address.
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(6) Message length field
The transmission side outputs a value indicating the number of bytes in transmit data and a parity bit to the
reception side by using this field. The reception side outputs an acknowledge bit in response.
Figure 20-5 shows the configuration of the message length field, and Table 20-3 shows the relationship
between the message length bit and the number of bytes of transmit data.
Figure 20-5. Configuration of Message Length Field
Message Length Bits (8 bits)
Parity
MSB
ACK
LSB
Table 20-3. Message Length Bit and Number of Bytes of Transmit Data
Value of Message Length Bit
Number of Bytes of Transmit Data
01H
02H
|
FFH
00H
1 byte
2 bytes
|
255 bytes
256 bytes
(7) Data field
The transmission side outputs data and a parity bit by using this field.
The master unit transmits data to the slave unit or receives data from the slave unit by using the data field.
Figure 20-6 shows the configuration of the data field.
Figure 20-6. Configuration of Data Field
Data Field (number specified by message length bit)
Data of 1 byte
Data Bits (8 bits)
MSB
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LSB
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20.2.2 Bit format
Figure 20-7 shows the format of the bits constituting the communication frame of IEBus.
Figure 20-7. Bit Format of IEBus
1 bit
High Level
Low Level
Preparation
Period
Synchronization
Period
Data Period
Stop Period
Caution Negative logic: High level = “0”, low level = “1”
Positive logic: High level = “1”, low level = “0”
Preparation period:
First low-level period
Synchronization period: Next high-level period
Data period:
Period indicating value of bit
Stop period:
Last low-level period
IEBus synchronizes each bit. The lengths of the synchronization period and data period are almost the same.
The time of the entire bits, and specification related to the time of each period allocated to it differ depending on
the type of the transmit bit, and on whether the unit is the master or a slave unit.
20.2.3 Transmit data
The data transmitted between the master unit and slave unit in the data field include a slave status and a lock
address, in addition to the ordinary data.
(1) Data
When the control bits specify reading of data (3H or 7H), the data in the data buffer of the slave unit is read
to the master unit.
When the control bits specify writing of data (BH or FH), the data received by the slave unit is processed
according to the operation convention of that slave unit.
(2) Slave status
During individual communication, the slave unit does not return an acknowledge bit in some cases. At this
time, the master unit can learn the reason by reading the slave status.
The slave status indicates the status of the slave unit as a result of the communication performed last by the
slave unit.
All the slave units can supply information of the slave status.
Figure 20-8 shows the bit configuration of the slave status, and Table 20-4 shows the meaning of each bit.
Figure 20-8. Bit Configuration of Slave Status
MSB
bit 7
LSB
bit 6
bit 5
bit 4
bit 3
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bit 1
bit 0
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Table 20-4. Meaning of Slave Status
Bit
Value
Bit 0
Note 1
Bit 1
Note 2
Meaning
0
Slave transmit buffer is empty.
1
Slave transmit buffer is not empty.
0
Slave receive buffer is empty.
1
Slave receive buffer is not empty.
0
Unit is not locked.
1
Unit is locked.
0
Fixed to “0”
0
Slave transmission is stopped.
1
Slave transmission is enabled.
Bit 5
0
Fixed to 0
Bits 7, 6
00
Mode 0
01
Mode 1
10
Mode 2
11
(For future expansion)
Bit 2
Bit 3
Bit 4
Note 3
Indicates highest mode supported by
unit Note 4.
Notes 1. The slave transmit buffer is accessed during data read processing.
If the µPD78098B Subseries is used as a slave unit, this buffer is TBF (transmit buffer register).
2. The slave receive buffer is accessed during data write processing.
If the µPD78098B Subseries is used as a slave unit, this buffer is RBF (receive buffer register).
3. If the µPD78098B Subseries is used as a slave unit, “0” indicates disabling slave reception and
broadcast reception, and “1” indicates enabling the reception.
4. If the µPD78098B Subseries is used as a slave unit, bits 6 and 7 are fixed to “0” and “1”, respectively.
(3) Lock address
If a unit is locked by the master unit, the address of the master unit that has issued the lock instruction is called
the lock address.
If reading the lock address is specified to the locked unit (control bits: 4H or 5H), this lock address is read.
The lock address is of 12 bits. However, it is read in 1-byte (8-bit) units as shown in Figure 20-9.
For the lock function, refer to 20.5.6 Lock function.
Figure 20-9. Configuration of Lock Address
MSB
LSB
Control Bits: 4H
Control Bits: 5H
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20.3 IEBus Controller Configuration
The IEBus controller consists of the following hardware.
Caution The IEBus register of this product is not registered in the device file.
Table 20-5. IEBus Controller Configuration
Item
Configuration
Register
Transmit buffer register (TBF)
Receive buffer register (RBF)
Control register
Clock select register 1 (IECL1)
IEBus controller mode register (IECM)
Control register (CTR)
Command register (CMR)
Master communication control register (MCR)
Status registers 1 and 2 (STR1 and STR2)
Number of receive data registers 1 and 2 (RDR1 and RDR2)
Return code register (RCR)
Unit address registers 1 and 2 (UAR1 and UAR2)
Slave address registers 1 and 2 (SAR1 and SAR2)
Broadcast destination address registers 1 and 2 (DAR1 and DAR2)
Lock address registers 1 and 2 (LOR1 and LOR2)
(1) Transmit buffer register (TBF)
This register is used to pass a message length and transmit data to the IEBus controller when transmission
is executed. Internally, this register is an FIFO buffer of 33 bytes.
Data can be written to TBF when it is not full (when bit 7 (TFL) of status register 1 (STR1) is “0”), with an 8bit memory manipulation instruction.
The value of this register is undefined at hardware RESET input or when the IEBus controller is reset by
software.
Figure 20-10. TBF Setting Format
First Byte
Second Byte
Third Byte
Message Length (Transmit Data)
Transmit Data of First Byte
Transmit Data of Second Byte
33th Byte
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(2) Receive buffer register (RBF)
This register is used to receive information, such as the master address (transmission unit address), message
length, and receive data, from the IEBus controller during reception. Internally, this register is an FIFO buffer
of 40 bytes.
RBF can be read when it is not empty (when bit 4 (REP) of status register 1 (STR1) is 0), with an 8-bit memory
manipulation instruction.
The value of this register is undefined at hardware RESET input or when the IEBus controller is reset by means
of software.
Figure 20-11. RBF Setting Format
First Byte
Second Byte
Third Byte
Fourth Byte
Master (Transmission Source) Address (Higher 8 Bits)
Master Address (Lower 4 Bits)
Control Bits
Message Length (receive data)
Receive Data of First Byte
First Receive Frame
Fifth Byte
Receive Data of Second Byte
:
:
Last Receive Data
Master (Transmission Source) Address (Higher 8 Bits)
Master Address (Lower 4 Bits)
Control Bits
Message Length (Receive Data)
Receive Data of First Byte
Receive Data of Second Byte
:
40th Byte
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20.4 Registers Controlling IEBus Controller
The IEBus controller is controlled by the following 12 types of registers:
• Clock select register 1 (IECL1)
• IEBus controller mode register (IECM)
• Control register (CTR)
• Command register (CMR)
• Master communication control register (MCR)
• Status registers 1 and 2 (STR1 and STR2)
• Number of receive data registers 1 and 2 (RDR1 and RDR2)
• Return code register (RCR)
• Unit address registers 1 and 2 (UAR1 and UAR2)
• Slave address registers 1 and 2 (SAR1 and SAR2)
• Broadcast destination address registers 1 and 2 (DAR1 and DAR2)
• Lock address registers 1 and 2 (LOR1 and LOR2)
(1) Clock select register 1 (IECL1)
This register specifies whether the output of the main system clock oscillation circuit goes through divider 2
before it is supplied to the IEBus controller.
IECL1 is manipulated with an 8-bit memory manipulation instruction. When it is used in combination with clock
select register 2 (IECL2) as a 16-bit register IECL, it is manipulated with a 16-bit memory manipulation
instruction.
RESET input clears this register to 00H.
Remark
IECL1 also has a function to specify whether the output of the main system clock oscillator goes
through the 2/3 divider in divider 1.
Figure 20-12. Format of Clock Select Register 1
Symbol
7
6
5
4
3
2
IECL1
0
0
0
0
0
0
IECL11
1
0
IECL11 IECL10
Address
After
Reset
R/W
F8E0H
00H
R/W
Main System Clock Divider Control (Divider 2)
0
Does not use 1/2 divider in divider 2
1
Uses 1/2 divider in divider 2
Caution Be sure to set bits 2 to 7 to 0.
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(2) IEBus controller mode register (IECM)
This register selects the alternate function or an output logic level when the IEBus function is used.
IECM is manipulated with an 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
Figure 20-13. Format of IEBus Controller Mode Register
Symbol
7
6
5
4
3
2
IECM
0
0
0
0
0
0
IECM1
1
0
IECM1 IECM0
Address
After
Reset
R/W
F8E3H
00H
R/W
P124/TX and P125/RX Pins Logic Selection
0
Pin output is negative logic (1: low level, 0: high level).
1
Pin output is positive logic (1: high level. 0: low level).
IECM0
Function Selection of P124/TX and P125/RX Pins
0
As normal port
1
As IEBus controller pin
Caution Be sure to set bits 2 to 7 to 0.
(3) Control register (CTR)
This register controls the operation of the IEBus controller.
CTR is written with an 8-bit memory manipulation instruction.
This register is set to ×××00×01B at RESET input or when the IEBus controller is reset by means of software.
Cautions 1. When using the IEBus controller, be sure to reset this register first (bit 3 (SRST) = 1).
Resetting by setting SRST = 1 and releasing the standby mode by setting bit 1 (STREQ)
= 0 can be performed at the same time.
2. Do not reset the IEBus controller by means of software by setting SRST = 1 while the
IEBus controller is operating (when bit 1 (STM) of status register 2 (STR2) is 0).
3. To stop the main system clock by using the STOP instruction or setting bit 7 (MCC) of
the processor clock control register (PCC) to 1, be sure to set bit 0 (STREQ) to 1 and
confirm that the IEBus controller has entered the standby status. Confirm the standby
status by using bit 1 (STM) of STR2.
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Figure 20-14. Control Register Format
Symbol
7
6
5
CTR
0
0
0
4
3
REEN SRST
2
0
1
0
Address
After
Reset
R/W
F8F0H
×××00×01B
W
FAI STREQ
Note 1
REEN Used to request for enabling the IEBus controller to receive data (individual/broadcast mode).
By setting this bit to 1, the IEBus controller is requested to be enabled to receive data.
This bit is automatically cleared to 0 in the IEBus controller.
Therefore, it does not have to be cleared to 0 after the request has been made.
SRST Used to reset the IEBus controller by means of software.
When this bit is set to 1, the IEBus controller is requested to be reset.
This bit is automatically cleared to 0 in the IEBus controller.
Therefore, it does not have to be cleared to 0 after the request has been made.
Note 2
FAI
Specifies the position at which FCH Note 3 is set to 1 when the receive buffer register (RBF) is read.
When this bit is set to 1, the position at which FCH is set to 1 is moved when reading the current frame has
been completed. Each time this bit has been set, the position is moved backward by one frame.
This bit is automatically cleared to 0 in the IEBus controller.
Up to four frames (including the frame being read) can be moved.
Standby Operation Control Note 4
STREQ
0
Requests the IEBus controller to release the standby status.
1
Requests the IEBus controller to set the standby status.
Caution Be sure to set bit 2 and bits 5 to 7 to 0.
Notes 1. The result of the request (enabling or disabling reception) is reflected on SLRE (bit 4 of the status
register (STR2)). Therefore, for the actual status, check SLRE.
2. This function is valid only when bit 1 (FCHC) of the command register (CMR) is set to 1 so that
reading of a received communication frame is checked. Do not set a number of times greater than
the number of completely received frames stored in the receive buffer register (RBF) to FAI.
3. FCH: Bit 3 of status register 1 (STR1)
FCH is a flag that is set to 1 when reading the number of communication frames set by FAI when
RBF was read is completed. By reading this flag, the reading status of RBF can be checked (refer
to 20.4 (6) Status register 1).
4. The result of the request (standby status/releasing) is reflected on STM (bit 1 of STR2). Therefore,
for the actual status, check STM. If STREQ is set in the middle of communication, the standby
status is not requested until the current communication frame completes communication.
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(4) Command register (CMR)
This register controls communication and the transmit/receive buffer, and specifies option functions.
How this register is used is specified by the value of the most significant bit (0: Control/1: Option setting).
CMR is written with an 8-bit memory manipulation instruction.
This register is cleared to 00H at RESET input or when the IEBus controller is reset by means of software.
Figure 20-15. Command Register Format (When Used for Control)
Symbol
7
CMR
0
6
5
4
3
2
1
0
LOCK BUFC1 BUFC0 COMC3 COMC2 COMC1 COMC0
Address
After Reset
R/W
F8F1H
00H
W
Updating Control of Lock Address Registers 1 and 2 (LOR1 and LOR2)
LOCK
0
Disables updating LOR1 and LOR2.
1
Enables updating LOR1 and LOR2.
Transmit/Receive Buffer Control
BUFC1 BUFC0
0
0
Performs nothing.
0
1
Clears transmit buffer register (TBF).
1
0
Clears all frames of receive buffer register (RBF).
1
1
Clears one frame (the newest receive frame) of receive buffer register (RBF).
IEBus Controller Communication Control
COMC3 COMC2 COMC1 COMC0
0
0
0
0
Performs nothing.
0
0
0
1
Requests for releasing from lock status (requested by other unit).
1
0
0
0
Requests for communication as master.
1
0
0
1
Requests for communication as master by continuing previous master communication
status.
1
0
1
0
Requests for forced stop of master communication. However, frame currently
communicated is output to the end.
1
0
1
1
Requests slave to transmit data.
1
1
0
0
Requests data transmission by continuing previous data transmission status from slave.
1
1
0
1
Requests forced stop of data transmission from slave. However, frame currently
communicated is output to the end.
1
1
1
0
Requests for self-check communication.
1
1
1
1
Requests disabling reception (individual/broadcast).
Other than above
Setting prohibited
Caution Write CMR when bit 3 (CEX) of the status register 2 (STR2) is 0.
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Figure 20-16. Command Register Format (for Option Setting)
Symbol
7
6
5
4
3
2
CMR
1
0
0
0
0
0
FCHCNote
0
FCHC DERC
Address
After
Reset
R/W
F8F1H
00H
W
Reading Received Communication Frame Checking Control
0
Does not check reading of received communication frame.
1
Checks reading of received communication frame.
DERC
Note
1
Broadcast Reception Error Operation Control
0
Disables broadcast reception error check.
1
Enables broadcast reception error check.
When FCHC is set to 1, to read a new communication frame from the receive buffer, be sure to set
bit 1 (FA1) of the control register (CTR) to 1. In this operation, if the receive buffer has a vacant area,
5 or more communication frames cannot be recorded in the receive buffer.
Cautions 1. Be sure to set bits 2 to 6 to 0.
2. Before setting an option function, set bit 3 (SRST) of the control register (CTR) to 1 and
reset the IEBus controller by means of software.
The IEBus controller does not
communicate at all until the option function has been set.
3. Write CMR when bit 3 (CEX) of the status register 2 (STR2) is 0.
(5) Master communication control register (MCR)
This register sets the communication condition when the device communicates as the master unit.
MCR is written with an 8-bit memory manipulation instruction.
This register is made to an undefined value at RESET input or when the IEBus controller is reset by means
of software.
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Figure 20-17. Format of Master Communication Control Register
Symbol
7
6
MCR
Broadcast
Bit
5
4
3
2
Arbitration Count
Broadcast
Bit
1
0
Address
Control Bit
F8F6H
0
Broadcast communication (plural slaves)
1
Individual communication (single slave)
W
Arbitration Count
Number of Retries if Arbitration Is Lost During Master Communication or Self-Check Communication
0
0
0
0 (no retries)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Description of Control
0Note1
0
0
0
Reading slave status
0Note1
0
1
1
Reading data and locking Note 2
0Note1
1
0
0
Reading lock address (lower 8 bits)
0Note1
1
0
1
Reading lock address (higher 4 bits)
0Note1
1
1
0
Reading slave status and unlocking Note 2
0Note1
1
1
1
Reading data
Note1
0
1
0
Writing command and locking Note 2
1Note1
0
1
1
Writing data and locking Note 2
1Note1
1
1
0
Writing command
Note1
1
1
1
Writing data
1
R/W
Broadcast or Individual Communication Selection
Control Bit
1
After
Reset
Undefined
Other than above
Setting prohibited
Caution Write MCR when bit 6 (MARQ) of status register 2 (STR2) is 0.
Notes 1. The data transfer direction of the message length bit and data field of the subsequent message
length field is changed depending on the value of bit 3 (MSB).
When bit 3 is “0”: Transfer from slave unit to master unit
When bit 3 is “1”: Transfer from master unit to slave unit
2. Control bit that specifies lock setting and cancellation
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(6) Status register 1 (STR1)
This register indicates the status of the transmit buffer register (TBF) and receive buffer register (RBF).
STR1 is read with an 8-bit memory manipulation instruction. When STR1 is used in combination with status
register 2 (STR2) as a 16-bit register STR, this register is read with a 16-bit memory manipulation instruction.
This register is set to 01011×××B at RESET input or when the IEBus controller is reset by means of software.
Figure 20-18. Format of Status Register 1
Symbol
STR1
7
6
5
4
3
2
1
0
Address
After
Reset
R/W
TFL
TEP
RFL
REP
FCH
—
—
—
F8F0H
01011×××B
R
TFL
Indicates Whether TBF Is Full
0
TBF is not full
1
TBF is full
TEP
Indicates Whether TBF Is Empty
0
TBF is not empty
1
TBF is empty
RFL
Indicates Whether RBF Is Full
0
RBF is not full
1
RBF is full
REP
Indicates Whether RBF Is Empty
0
RBF is not empty
1
RBF is empty
Indicates Completion of Reading Number of Communication Frames Set by FAI Note
FCH
0
Reading of number of communication frames set by FAI is not complete
1
Reading of number of communication frames set by FAI is complete.
This bit is automatically cleared to 0 when next frame information is read.
Note
FCH is valid when bit 1 (FCHC) of the command register (CMR) is set to 1 so that reading of a received
communication frame is checked, and when moving the read frame is specified by setting FAI to 1.
Remark
FAI: Bit 1 of control register (CTR)
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(7) Status register 2 (STR2)
This register indicates the communication status, command status, and interrupt status.
STR2 is read with an 8-bit memory manipulation instruction. When STR2 is used in combination with status
register 1 (STR1) as a 16-bit register STR, this register is read with a 16-bit memory manipulation instruction.
STR2 can be read in the standby mode (STM = 1).
This register is set to 02H at RESET input or when the IEBus controller is reset by means of software.
Figure 20-19. Format of Status Register 2
Symbol
7
STR2
0
6
5
4
3
MARQ STRQ SLRE CEX
MARQ
2
1
0
Address
After
Reset
R/W
RAW
STM
IRQ
F8F1H
02H
R
Indicates Communication Request Period as Master Unit
0
Not communication request period as master unit
1
Communication request period as master unit
STRQ
Indicates Communication Request Period as Slave Unit
0
Not communication request period as slave unit
1
Communication request period as slave unit
Enables or Disables Slave Reception or Broadcast Reception Note 1
SLRE
0
Disables slave reception or broadcast reception
1
Enables slave reception or broadcast reception
CEX
Indicates Command Processing in Progress
0
Command processing is not in progress (writing CMR is enabled)
1
Command processing is in progress (writing CMR is disabled)
RAW
Indicates Program Loop Detection Status of IEBus Interface
0
IEBus interface does not enter program loop
1
IEBus interface enters program loop Note 2
STM
Indicates Standby Status of IEBus Controller
0
Not standby status
1
Standby status
IRQ
Indicates Change of RCR and Program Loop of IEBus Controller Note 3
0
Does not detect change of RCR and program loop of IEBus controller
1
Detects change of RCR and program loop of IEBus controller
Notes 1. Unless SLRE is set to 1 until the end of the control field of a reception frame, the communication
frame cannot be received.
2. When RAW is 1, reset the IEBus controller.
3. IRQ is automatically cleared to 0 once it has been read.
Caution When the IEBus controller is operating (bit 1 (STM) of STR2 is 1), do not reset the IEBus
controller by software (do not set bit 3 (SRST) of the control register (CTR) to 1)
Remark
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(8) Number of receive data registers 1 and 2 (RDR1 and RDR2)
These registers store the number of received data when reception is performed.
RDR1 stores the number of data received by the master. RDR2 stores the number of data received by the
slave (individual/broadcast).
RDR1 and RDR2 are read with an 8-bit memory manipulation instruction. When RDR1 and RDR2 are used
in combination as the 16-bit register RDR, these registers are read with a 16-bit memory manipulation
instruction.
Both the registers are cleared to 00H at RESET input or when the IEBus controller is reset by means of
software.
(9) Return code register (RCR)
This register stores return codes for transmission/reception operations.
RCR is read with an 8-bit memory manipulation instruction.
This register is set to 4FH at RESET input or when the IEBus controller is reset by means of software.
Figure 20-20. Format of Return Code Register (1/3)
Symbol
7
RCR
0
6
5
4
3
2
1
0
TRC2 TRC1 TRC0 REC3 REC2 REC1 REC0
Address
F8F8H
After
Reset
4FH
R/W
R
Meanings of Return Codes (Those Related to Transmission)
TRC2 TRC1 TRC0
0
0
0
Indicates start of master transmission or slave transmission.
<1> On starting master transmission
Indicates that transmission of master address field in communication frame has
been completed, that unit has won as master unit, and that master transmission
has been started.
<2> On starting slave transmission
Indicates that control bits (0011B, or 0111B) requesting data transmission has
been received from master unit, and that slave transmission has been started.
0
0
1
Indicates that transmission buffer register (TBF) is empty during master transmission or slave
transmission.
Unless the following data is not set to TBF within the following specified times, communication
is stopped in the middle.
Communication mode 0: About 1,570 µ s Note
Communication mode 1: About 390 µ s Note
Communication mode 2: About 280 µ s Note
0
1
0
Indicates completion of transmission of number of data specified by message length field
during master transmission or slave transmission.
0
1
1
Indicates end of communication without completion of transmission of number of data
specified by message length field in one communication frame during master transmission or
slave transmission.
1
0
0
Undefined
1
0
1
Indicates completion without self-check communication executed because unit lost in
arbitration.
1
1
0
Indicates that result of self-check communication is normal.
1
1
1
Indicates that result of self-check communication is abnormal.
(Cont’d)
Note Value at fS = 6.0 MHz
Remark fS: Bus controller system clock frequency
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Figure 20-20. Format of Return Code Register (2/3)
Meaning of Return Codes (Those Related to Reception)
REC3 REC2 REC1 REC0
0
0
0
0
Indicates start of master reception.
Three-byte information, slave (transmission unit) address, control bit, and message
length (number of data to be received), can be read from the receive buffer (RBF).
0
0
0
1
Indicates that the receive buffer register (RBF) for master reception is full.
Unless data of RBF is not read within the following specified times, data cannot be
received and NAK is returned.
Communication mode 0: About 1,570 µ s Note
Communication mode 1: About 390 µ s Note
Communication mode 2: About 280 µ s Note
0
0
1
0
Indicates that master has received data of message length and that communication has
been completed normally.
Receive data can be read from the receive buffer (RBF). Number of master receive data
can be read from the number of receive data register 1 (RDR1).
0
0
1
1
Indicates that master cannot receive data of message length and that communication
has been aborted (there are still data to be communicated).
Receive data can be read from the receive buffer (RBF). Number of master receive data
can be read from the number of receive data register 1 (RDR1).
0
1
0
0
Indicates start of slave individual reception.
Three-byte information, master (transmission unit) address, control bit, and message
length (number of data to be received), can be read from the receive buffer (RBF).
0
1
0
1
Indicates that the receive buffer (RBF) for slave individual reception is full.
Unless data of RBF is not read within the following specified times, data cannot be
received and NAK is returned.
Communication mode 0: About 1,570 µ s Note
Communication mode 1: About 390 µ s Note
Communication mode 2: About 280 µ s Note
0
1
1
0
Indicates that the master has received data of message length and that communication
has been completed normally.
Receive data can be read from receive buffer (RBF). Number of slave receive data
can be read from number of receive data register 2 (RDR2).
0
1
1
1
Indicates that the master cannot receive data of message length and that communication
has been aborted (there are still data to be communicated).
Receive data can be read from the receive buffer (RBF). Number of master receive data
can be read from number of the receive data register 2 (RDR2).
(Cont’d)
Note Value at fS = 6.0 MHz
Remark fS = Bus controller system clock frequency
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Figure 20-20. Format of Return Code Register (3/3)
Meaning of Return Codes (those related to reception)
REC3 REC2 REC1 REC0
1
0
0
0
Indicates start of broadcast reception.
Three-byte information, master (transmission unit) address, control bit, and message
length (number of data to be received), can be read from the receive buffer (RBF).
1
0
0
1
Indicates that the receive buffer (RBF) for slave broadcast reception is full.
Unless data of RBF is not read within the following specified times, data cannot be
received and NAK is returned.
Communication mode 0: About 1,570 µ s Note 1
Communication mode 1: About 390 µ s Note 1
Communication mode 2: About 280 µ s Note 1
1
0
1
0
Indicates that a unit has received data of message length and that communication has
been completed normally during broadcast reception.
Receive data can be read from the receive buffer (RBF). Number of slave receive data
can be read from the number of receive data register 2 (RDR2).
1
0
1
1
Indicates that a unit cannot receive data of message length and that communication
has been aborted (there are still data to be communicated).
Receive data can be read from the receive buffer (RBF). Number of master receive data
can be read from the number of receive data register 2 (RDR2).
1
1
0
0
Indicates that the error occurs during broadcast reception.
Address of master that executes broadcast transmission can be learned by using the
broadcast destination address registers 1 and 2 (DAR1 and DAR2) Note 2.
1
1
0
1
Undefined
1
1
1
0
1
1
1
1
Notes 1. Value at fS = 6.0 MHz
2. This code is generated if an error occurs only when bit 0 (DERC) of the command register (CMR)
is set to 1.
Remark fS: Bus controller system clock frequency
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(10) Unit address registers 1 and 2 (UAR1 and UAR2)
These registers specify a unit address and transmission conditions (communication mode and transmission
control).
Of the 12 bits of the unit address, the higher 8 bits are set by UAR2, and the lower 4 bits are set by UAR1.
The transmission conditions are specified by UAR1.
UAR1 and UAR2 are written with an 8-bit memory manipulation instruction. When UAR1 and UAR2 are used
in combination as the 16-bit register UAR, these registers are written with a 16-bit memory manipulation
instruction.
The values of both registers are undefined at RESET input or when the IEBus controller is reset by means
of software.
Caution Before setting a unit address, reset the IEBus controller by software (by setting bit 3 (SRST)
of the control register (CTR) to 1).
Figure 20-21. Format of Unit Address Registers 1 and 2
Symbol
7
6
5
4
3
2
1
0
Unit Address (Higher 8 Bits)
UAR2
7
6
5
4
3
2
UAR1 Unit Address (Lower 4 Bits) UAR13 UAR12
1
0
0
UAR10
Address
After Reset
R/W
F8F3H
Undefined
W
F8F2H
Undefined
W
Communication Mode Selection
UAR13 UAR12
0
0
Communication mode 0
0
1
Communication mode 1
1
0
Communication mode 2
1
1
Setting prohibited
Slave Transmission Control
UAR10
0
Disables slave transmission.
1
Enables slave transmission.
Caution Write UAR1 and UAR2 when bit 3 (CEX) of status register 2 (STR2) is 0 (command processing
is not in progress).
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(11) Slave address registers 1 and 2 (SAR1 and SAR2)
These registers specify a slave address (the address of a unit to be communicated).
Of the 12 bits of a slave address, the higher 8 bits are set by SAR2 and the lower 4 bits are set by SAR1.
SAR1 and SAR2 are written with an 8-bit memory manipulation instruction. When SAR1 and SAR2 are used
in combination as the 16-bit register UAR, these registers are written with a 16-bit memory manipulation
instruction.
The values of both the registers are undefined at RESET input or when the IEBus controller is reset by means
of software.
Figure 20-22. Format of Slave Address Registers 1 and 2
Symbol
7
6
5
4
3
2
1
0
Slave Address (Higher 8 Bits)
SAR2
7
6
5
4
SAR1 Slave Address (Lower 4 Bits)
3
2
1
0
0
0
0
0
Address
After Reset
R/W
F8F5H
Undefined
W
F8F4H
Undefined
W
Cautions 1. Be sure to clear bits 0 to 3 of SAR1 to 0.
2. Write SAR1 and SAR2 when bit 6 (MARQ) of status register 2 (STR2) is 0 (not
communication request period as master unit).
(12) Broadcast destination address registers 1 and 2 (DAR1 and DAR2)
These registers store a broadcast destination address (the address of the master that performs broadcast
communication) if a broadcast reception error occurs.
DAR1 and DAR2 are read with an 8-bit memory manipulation instruction. When DAR1 and DAR2 are used
in combination as the 16-bit register DAR, these registers are read with a 16-bit memory manipulation
instruction.
The values of both the registers are undefined at RESET input or when the IEBus controller is reset by means
of software.
Cautions 1. DAR1 and DAR2 are valid only when bit 0 (DERC) of the command register (CMR) is set
to 1 (when checking of broadcast communication error is enabled).
2. DAR1 and DAR2 are updated each time a broadcast reception error has occurred.
Therefore, unless DAR1 and DAR2 are read within the following specified times, their
contents may be updated by a new error.
Communication mode 0: About 5,420 µs (at fS = 6.0 MHz)
Communication mode 1: About 1,490 µs (at fS = 6.0 MHz)
Communication mode 2: About 1,110 µs (at fS = 6.0 MHz)
Remark fS: Bus controller system clock frequency
Figure 20-23. Format of Broadcast Destination Address Registers 1 and 2
Symbol
DAR1
DAR2
4
3
2
1
0
Address
After Reset
R/W
Broadcast Destination
Address (Lower 4 Bits)
—
—
—
—
F8F6H
Undefined
R
7
3
2
1
0
F8F7H
Undefined
R
7
6
6
5
5
4
Broadcast Destination Address (Higher 8 Bits)
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(13) Lock address registers 1 and 2 (LOR1 and LOR2)
These registers indicate whether the unit is locked or unlocked, and store the lock address (the address of
the master unit that requests for locking) if the unit is locked.
LOR1 and LOR2 are read with an 8-bit memory manipulation instruction. When LOR1 and LOR2 are used
in combination as a 16-bit register LOR, these registers are read with a 16-bit memory manipulation instruction.
The lock status is set to 0000B and the lock address is undefined at RESET input or when the IEBus controller
is reset by means of software.
Caution LOR1 and LOR2 can be read only when updating these registers is enabled (by setting bit
6 (LOCK) of the command register (CMR) to 1) and when bit 3 (CEX) of status register 2 (STR2)
is cleared to 0 (command processing is not in progress).
Figure 20-24. Format of Lock Address Registers 1 and 2
Symbol
7
6
5
4
3
2
1
Lock Address (Lower 8 Bits)
LOR1
7
6
5
4
Lock Status
LOR2
3
2
1
After Reset
R/W
F8F4H
Undefined
R
F8F5H
0000××××B
R
Lock Status
0
0
0
0
Not locked
0
0
0
1
Locked
Other than above
Address
0
Lock Address (Higher 4 Bits)
Higher 4 Bits of LOR2
452
0
Undefined
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20.5 Communication Operation by IEBus
Communication by IEBus is executed in frame units where one frame consists of a start bit, data field, and so on.
Therefore, data output of each field in one frame is explained.
Because individual communication is executed on a one-unit-to-one-unit basis, an acknowledge bit that indicates
whether data has been correctly received is output after the data has been received.
When broadcast communication is performed, however, the acknowledge bit is not output after data reception,
because the master unit communicates with two or more units.
20.5.1 Start bit output
The master unit outputs a start bit to inform the other unit(s) of the start of data transmission. The units other than
the one that has started transmission detect this start bit and enter the reception status.
If an other unit has already output a start bit when the master unit is to output a start bit, the master unit does not
output the start bit, but waits for completion of the already output start bit. The master unit starts outputting a broadcast
bit in synchronization with the completion of the start bit output.
Arbitration is determined by the data output after the broadcast bit has been output.
20.5.2 Broadcast bit output
The master unit outputs a value identifying the type of communication it is to execute (i.e., individual communication
or broadcast communication) as a broadcast bit (the broadcast bit is set to 1 for individual communication, and to
0 for broadcast communication).
If two or more units start transmitting a broadcast bit at the same time, arbitration is determined depending on the
type of communication. Broadcast communication takes precedence over individual communication, and wins in
arbitration.
If two or more units start transmitting a broadcast bit of the same value, judgment of arbitration is made by the
master address field.
20.5.3 Master address output
The master unit outputs a master address to inform the slave unit(s) of its address.
If two or more units start transmitting a broadcast bit of the same value at the same time, judgment of arbitration
is made by the master address field.
The master address field compares the data output by the master with the data on the bus each time the master
has transmitted 1 bit. Because IEBus has a wired-AND configuration, the unit having the lowest master address of
those the units participating in arbitration (arbitration masters) wins in arbitration, and its value (value of the master
address) is output to the bus.
Therefore, as a result of the comparison, the unit whose output data is different from the data on the master address
bus is judged to be a loser in arbitration. This unit stops transmission and enters the reception status.
After a 12-bit master address has been output, only one unit remains in the transmission status. The master unit
that has won in arbitration outputs a parity bit after the master address, makes the other units recognize the master
address, and starts outputting a slave address.
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20.5.4 Slave address output
The master unit outputs the address of the other unit with which it is to communicate individually (slave address).
In the case of broadcast communication, it outputs a value to identify simultaneous broadcast communication or group
broadcast communication, as follows:
Simultaneous broadcast communication: FFFH
Group broadcast communication:
Value other than FFFH
After the 12-bit slave address has been transmitted, the master outputs a parity bit to prevent a wrong slave address
from being received by mistake. In the case of broadcast communication, it then starts outputting control bits.
In the case of individual communication, the master unit detects an acknowledge signal from a slave unit to confirm
that the slave unit exists on the bus, after it has output the parity bit. If the acknowledge signal is detected, the master
starts outputting control bits. If the acknowledge signal is not detected, the master unit enters the standby (monitor)
status, and ends communication.
The slave unit confirms that the parity of the master address it has received and the parity of the slave address
are even, and outputs the acknowledge signal, if the slave address sent by the master matches its address.
If the parities are odd, the slave assumes that the master address or slave address has not been correctly received,
and does not output the acknowledge signal.
In any of the following cases, the acknowledge bit is set to “1”, indicating that the transmit data has not been
recognized. If this happens, transmission is aborted.
• If the parity bit of the master address field or slave address field is not even
• If an error (timing error) occurs in the bit format
• If no slave unit exists
20.5.5 Control bit output
The master unit outputs control bits corresponding to the operations it requests the slave unit to perform, followed
by a parity bit (for the contents of the control bits, refer to 20.2.1 (5) Control field).
For individual communication, the master unit detects and confirms the acknowledge signal from the slave unit,
and starts outputting a message length bit, after it has output the parity bit. If the acknowledge signal cannot be
detected, the master unit enters the standby status, and ends communication.
For broadcast communication, the master unit does not detect an acknowledge signal, but starts outputting a
message length bit.
The slave unit does not output an acknowledge signal if any of the following incidents occur in the control field.
At this time, transmission is stopped, and both the master and slave units enter the standby (monitor) status.
• If the parity of the control bits is not even
• If writing is instructed by the control bits (bit 3 of control bits = 1) even when the slave receive buffer is not empty
• If reading of data is instructed by the control bits (3H or 7H) even if the slave transmit buffer is empty
• If an operation other than those below is requested by a unit that has not locked the master unit when locking is set
• Reading slave status
• Reading lock address (lower 8 bits and higher 4 bits)
• If reading the lock address is instructed by the control bits (4H) when locking is not set
• If a timing error occurs
• If the control bits are undefined
For the lock function, refer to 20.5.6 Lock function.
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20.5.6 Lock function
The lock function is used to transfer a message over two or more communication frames during individual
communication (this function is not used during broadcast communication).
The unit locked by the master unit rejects accepting control bits from the unit other than those that has requested
for locking, and does not output an acknowledge bit. However, if the control bits shown in the table below are received
from a unit other than the master unit that has requested for locking, the locked unit receives them.
Table 20-6. Control Bits That Can Be Specified for Locked Slave Unit
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
Reads slave status.
0
1
0
1
Reads lock address (lower 8 bits)
0
1
0
1
Reads lock address (higher 4 bits)
Remark
Function
The lock address is the address of the master unit that has issued a lock instruction to the slave unit.
For the details of the lock address, refer to 20.2.3 (3) Lock address.
A unit is locked or unlocked as follows:
(1) Locking
Specify locking by the control bits (3H, AH, or BH), and transmit/receive the acknowledge bit, which is 0, in
the message length field. After that, the communication frame is completed without successful transmission
or reception of the number of data bytes specified by the message length bit. As a result, the master unit locks
a slave unit. At this time, a bit related to locking in the byte indicating the slave status (bit 2) is set to 1.
(2) Unlocking
Specify locking (3H, AH, or BH) or unlocking (6H) by the control bits. When the slave unit has completed
transmission or reception of the number of data bytes specified by the message length bit within one frame,
the slave unit is unlocked from the master unit.
At this time, a bit related to locking in the byte indicating the slave status (bit 2) is reset to 0.
20.5.7 Message length bit output
The transmission unit outputs a value indicating the number of bytes of the data to be transmitted (message length
bit) and a parity bit to the reception unit. In response, the reception unit outputs an acknowledge signal (however,
the slave unit does not output the acknowledge signal in the case of broadcast communication).
If either of the following incidents occur in the message length field, the reception unit assumes that the message
length bit has not been correctly received, and does not output the acknowledge signal. At this time, transmission
is stopped, and both the master and slave units enter the standby (monitor) status.
• If the parity of the message length bit is odd
• If a timing error occurs
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20.5.8 Data bit output
The transmission unit outputs data (data bits). Following the data bits, the transmission unit outputs a parity bit,
and the reception unit outputs an acknowledge bit in response.
In the case of broadcast communication, the master unit initiates transmission (the slave unit does not start
transmission). At this time, the reception unit does not output the acknowledge bit, and the master unit ignores the
acknowledge bit.
In the case of individual communication, the reception unit rejects accepting the data and does not output the
acknowledge signal if any of the following incidents occur in the data field.
• If the parity of the data bits is odd
• If a timing error occurs after the previous acknowledge bit has been transmitted
• If the reception buffer is full and can receive no more data
If the cause is a timing error, each unit enters the standby status, and communication is stopped. If the cause
is other than a timing error, the transmission unit transmits the data field again if the number of bytes to be transmitted
is within the maximum value of one frame.
The operations during master transmission and master reception are explained next.
(1) Operation during master transmission
If the master unit is on the transmission side, the slave unit receives the data bits and parity bit, and outputs
an acknowledge signal after confirming that the parity is even and that the receive buffer is empty. If the parity
is odd or if the receive buffer is not empty, the slave unit rejects accepting the data, and does not output the
acknowledge signal.
Even if the slave unit does not output the acknowledge signal, the master unit transmits the same data again.
This operation is continued until the master unit detects the acknowledge signal from the slave unit, or the
number of the data has reached the maximum number of transmit bytes (refer to 20.1.3 Communication
mode).
When the slave unit outputs the acknowledge signal, the master unit transmits the next data if there is
continuation of the data and if the maximum number of transmit bytes is not exceeded.
In the case of broadcast communication, the slave unit does not output the acknowledge signal. The master
unit ignores the acknowledge bit, and transfers data on a 1-byte-by-1-byte basis.
(2) Operation during master reception
When the master unit reads data from the slave unit, the master unit outputs a synchronization signal that
corresponds to all read bits (refer to 20.2.2 Bit format).
The slave unit outputs the data bits and parity bit to the bus in response to the synchronization signal from
the master unit. The master unit reads these data bits and parity bit.
The master unit checks the parity bit output by the slave unit. If the parity is even and if the receive buffer
is empty, the master unit accepts the output data and returns an acknowledge signal. If the data is within
the maximum number of bytes that can be transmitted in one frame, the master unit reads the next data.
If the parity is odd, or if the receive buffer is not empty, the master unit rejects accepting the data and does
not output the acknowledge signal. If the data is in the maximum number of bytes that can be transmitted
in one frame, the master unit repeatedly reads the same data.
20.5.9 Timing chart
Refer to Figures 20-25 to 20-27.
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Figure 20-25. Operation Example of Individual Communication (Master Transmission - Slave Reception)
Master
Broadcast Bit
(bit 7 of MCR)
CMR COMC0 to
COMC3
STR2
1000B
CEX
MARQ
STRQ
SLRE
RCR
TRC0 to
TRC2
000B (Master starts transmission)
010B
REC0 to
REC3
RDR1
RDR2
INTIE
TX
Address Slave Address
Header Master
Field
Field
Control
Field
Message
Data Field
Length Field
Address Slave Address
Header Master
Field
Field
Control
Field
Message
Data Field
Length Field
Signal on IEBus
Communication Frame
Slave
CTR
STR2
REEN
CEX
MARQ
STRQ
Frame of this time cannot be received unless
reception is enabled up to control field.
SLRE
RCR
TRC0 to
TRC2
REC0 to
REC3
0100B
0110B
3 4 ...
n+3
RDR1
RDR2
INTIE
TX
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IEBus CONTROLLER
Figure 20-26. Operation Example of Individual Communication (Master Reception - Slave Transmission)
Master
Broadcast Bit
(bit 7 of MCR)
CMR COMC0 to
COMC3
STR2
1000B
CEX
MARQ
STRQ
SLRE
RCR
TRC0 to
TRC2
REC0 to
REC3
0000B
0
RDR1
3 4
...
0010B
n+3
RDR2
INTIE
TX
Address Slave Address
Header Master
Field
Field
Control
Field
Address Slave Address
Header Master
Field
Field
Control
Field
Signal on IEBus
Communication Frame
Message
Data Field
Length Field
Slave
CTR
REEN
CMR COMC0 to
COMC3
STR2
1011B
CEX
MARQ
STRQ
SLRE
RCR
TRC0 to
TRC2
000B (Slave starts
transmission)
REC0 to
REC3
RDR1
RDR2
INTIE
Message
Length Field Data Field
TX
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010B (Slave ends
transmission)
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IEBus CONTROLLER
Figure 20-27. Operation Example of Broadcast Communication (Master Transmission - Slave Reception)
Master
Broadcast Bit
(bit 7 of MCR)
CMR COMC0 to
COMC3
STR2
1000B
CEX
MARQ
STRQ
SLRE
RCR
TRC0 to
TRC2
000B (Master starts transmission)
010B
REC0 to
REC3
RDR1
RDR2
INTIE
TX
Address Slave Address
Header Master
Field
Field
Control
Field
Message
Data Field
Length Field
Address Slave Address
Header Master
Field
Field
Control
Field
Message
Data Field
Length Field
Signal on IEBus
Communication Frame
Slave
CTR
STR2
REEN
CEX
MARQ
STRQ
SLRE
RCR
TRC0 to
TRC2
REC0 to
REC3
1000B
1010B
3 4 ...
n+3
RDR1
RDR2
INTIE
TX
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20.6 Communication Procedure of IEBus
20.6.1 Initialization
Perform initialization in the following procedure when executing communication with IEBus.
(1) Reset IEBus
Register to be set: Control register (CTR)
Setting: Bit 3 (SRST) = 1
(2) Select a clock
Register to be set: Clock select register 1 (IECL1)
Setting: Bit 1 (IECL11) = Any
(3) Set the output logic level or the alternate function
Register to be set: IEBus controller mode register (IECM)
Setting: Bit 0 (IECM0) = 1, bit 1 (IECM1) = Any
(4) Set a unit address and communication conditions
Register to be set: Unit address registers 1 and 2 (UAR1 and UAR2)
Setting: Any
(5) Confirm that command processing is not in progress
Register to be set: Status register 2 (STR2)
Setting: Bit 3 (CEX) = 0
(6) Set the communication option function
Register to be set: Command register (CMR)
Setting: CMR = 100000×× (×: Don’t care)
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20.6.2 Master transmission procedure
When the master unit transmits data to the slave unit, perform settings in the following procedure:
(1) Set communication conditions
Register to be set: Master communication control register (MCR)
Setting:
Select broadcast communication or individual communication (any).
Set the number of times of retry of arbitration (any).
Select the control bits related to writing as the control contents for communication (any).
Caution MCR cannot be written during the communication request period as the master unit. Check
bit 6 (MARQ) of status register 2 (STR2).
(2) Set the address of the other unit to communicate with, and the type of broadcast communication
Register to be set: Slave address registers 1 and 2 (SAR1 and SAR2)
Setting:
Any other unit address for individual communication.
Other than FFFH for group broadcast communication, and FFFH for simultaneous
broadcast communication.
(3) Confirm that the transmit buffer register (TBF) is not full
Register to be set: Status register 1 (STR1)
Setting:
Bit 7 (TFL) = 0
(4) Set a message length and transmit data to the transmit buffer register (TBF)
Register to be set: Transmit buffer register (TBF)
Setting:
Any
(5) Request the IEBus controller for communication as master
Register to be set: Command register (CMR) (control: bit 7 = 0)
Setting:
Bits 3 to 0 (COMC3 to COMC0) = 1000B
(6) Start outputting the communication frame from the TX pin
Caution Before starting output of the communication frame, confirm that bit 6 (MARQ) of status
register 2 (STR2) is set to 1 during the communication request period as the master unit.
.
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CHAPTER 21
CHAPTER 21
STANDBY FUNCTION
STANDBY FUNCTION
21.1 Standby Function and Configuration
21.1.1 Standby function
The standby function is designed to decrease the power consumption of the system. The following two modes
are available.
(1) HALT mode
HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock.
The system clock oscillator continues oscillation. In this mode, the current consumption cannot be decreased
as much as in the STOP mode, but the HALT mode is effective when it is necessary to restart immediately
upon interrupt request and to carry out intermittent operations such as in watch applications.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops
and the whole system stops. The CPU current consumption can be considerably decreased.
Data memory low-voltage hold (down to VDD = 2.0 V) is possible. Thus, the STOP mode is effective to hold
data memory contents with ultra-low current consumption. Because this mode can be released upon interrupt
request, it enables intermittent operations to be carried out.
However, because a wait time is necessary to secure oscillation stabilization time after the STOP mode is
released, select the HALT mode if it is necessary to start processing immediately upon interrupt request.
In either mode, all the contents of the registers, flags and data memory just before the standby mode is set are
held. The statuses of the I/O port output latches and output buffers are also held.
Cautions 1. The STOP mode can be used only when the system operates with the main system clock
(subsystem clock oscillation cannot be stopped). The HALT mode can be used with either
the main system clock or the subsystem clock.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before
executing the STOP instruction.
3. The following sequence is recommended for power consumption reduction of the A/D
converter when the standby function is used: first clear bit 7 (CS) of ADM to 0 to stop the
A/D conversion operation, and then execute the HALT or STOP instruction.
4. To reduce the power consumption of the IEBus controller, execute the HALT or STOP
instruction after confirming that bit 0 (STREQ) of the control register (CTR) has been set and
that the bit 1 (STM) of status register 2 (STR2) has been set.
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21.1.2 Register controlling standby function
A wait time after the STOP mode is released upon interrupt request till the oscillation stabilizes is controlled by
the oscillation stabilization time select register (OSTS).
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H.
Figure 21-1. Format of Oscillation Stabilization Time Select Register
Symbol
7
6
5
4
3
OSTS
0
0
0
0
0
2
1
0
Address
OSTS2 OSTS1 OSTS0
FFFAH
After
Reset
04H
R/W
R/W
Selection of Oscillation Stabilization Time When STOP Mode Is Released
OSTS2 OSTS1 OSTS0
12
0
0
0
2 /f xx (1.02 ms)
0
0
1
2 /f xx (4.10 ms)
0
1
0
215/f xx (8.19 ms)
0
1
1
216/f xx (16.4 ms)
1
0
0
217/f xx (32.8 ms)
14
Other than above Setting prohibited
Caution The wait time after STOP mode is released does not include the time (see "a" in the illustration
below) from STOP mode clearance to clock oscillation start, regardless of whether STOP mode
is released by RESET input or by interrupt request generation.
STOP Mode Release
X1 Pin
Voltage
Waveform
a
VSS
Remarks 1. fXX: Main system clock frequency
2. Values in parentheses apply to operation with fXX = 4.0 MHz
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21.2 Standby Function Operations
21.2.1 HALT mode
(1) HALT mode setting and operating status
The HALT mode is set by executing the HALT instruction. It can be set with the main system clock or the
subsystem clock.
The operating status in the HALT mode is described below.
Table 21-1. HALT Mode Operating Status
Setting of HALT Mode
On Execution of HALT Instruction During Main
On Execution of HALT Instruction During
System Clock Operation
Subsystem Clock Operation
Without subsystem
With subsystem
When main system clock When main system
Item
clock Note 1
clock Note 1
continues oscillation
Clock generator
Both main system and subsystem clocks can be oscillated. Clock supply to the CPU stops.
CPU
Operation stops.
Port (output latch)
Status before HALT mode setting is held.
16-bit timer/event counter 0
Operable.
clock stops oscillation
Operable when watch
timer output is selected
as count clock (fXT is
selected as count clock
of watch timer) or when
TI00 is selected.
8-bit timer/event counters 1 and 2
Operable.
Operable when TI1 or
TI2 is selected as
count clock.
Operable when fXX/27 is
Watch timer
Operable.
Operable when fXT is
selected as count clock.
Watchdog timer
Operable.
A/D converter
Operable.
D/A converter
Operable.
Real-time output port
Operable.
Serial interface
Other than
selected as count clock.
Operation stops.
Operation stops.
Operable.
Operable when
automatic
external SCK is used.
transmit/
receive
function
Automatic
Operation stops.
transmit/
receive
function
IEBus controller
External interrupt
Operable when bit 0 (STREQ) of control register (CTR) is cleared to 0
INTP0
INTP0 is operable when clock supplied for peripheral hardware is selected
as sampling clock (fXX/25, fXX/26, fXX/27).
INTP1 to INTP6
Operable.
Bus line for
AD0 to AD7
High impedance.
external
expansion
A0 to A15
Status before HALT mode setting is held.
ASTB
Low level.
WR, RD
High level.
WAIT
High impedance.
Notes 1. Including when external clock is not supplied
2. Including when external clock is supplied
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(2) HALT mode release
The HALT mode can be released by the following four sources.
(a) Release upon unmasked interrupt request
If an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement
is enabled, vectored interrupt servicing is carried out. If disabled, the next address instruction is executed.
Figure 21-2. Releasing HALT Mode by Interrupt Request Generation
HALT
Instruction
Interrupt
Request
Wait
Standby
Release Signal
Operating
Mode
HALT Mode
Wait
Operating Mode
Oscillation
Clock
Remarks 1. The broken lines indicate the case when the interrupt request that has released the standby
status is acknowledged.
2. The wait time will be as follows:
• When vectored interrupt servicing is carried out:
8 to 9 clocks
• When vectored interrupt servicing is not carried out: 2 to 3 clocks
(b) Releasing by non-maskable interrupt request generation
If a non-maskable interrupt request is generated, the HALT mode is released and vectored interrupt
servicing is carried out irrespective of whether interrupt acknowledgement is enabled or disabled.
(c) Releasing by unmasked test input
If an unmasked test signal is input, the HALT mode is released, and the next address instruction after
the HALT instruction is executed.
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(d) Releasing by RESET input
If the RESET signal is input, the HALT mode is released. As is the case with a normal reset operation,
a program is executed after a branch to the reset vector address.
Figure 21-3. Releasing HALT Mode by RESET Input
Wait
(217/f x : 21.8 ms)
HALT
Instruction
RESET
Signal
Operating
Mode
HALT Mode
Oscillation
Clock
Oscillation
Stabilization
Wait Status
Reset
Period
Oscillation
stop
Operating
Mode
Oscillation
Remarks 1. fX: main system clock oscillation frequency
2. ( ): fX: 6.0 MHz
Table 21-2. Operation After HALT Mode Release
Release Source
MK××
PR××
IE
ISP
0
0
0
×
Next address instruction execution
0
0
1
×
Interrupt service execution
0
1
0
1
Next address instruction execution
0
1
×
0
0
1
1
1
Interrupt service execution
1
×
×
×
HALT mode hold
Non-maskable interrupt
request
–
–
×
×
Interrupt service execution
Test input
0
–
×
×
Next address instruction execution
1
–
×
×
HALT mode hold
–
–
×
×
Reset processing
Maskable interrupt
request
RESET input
Operation
×: Don't care
21.2.2 STOP mode
(1) STOP mode setting and operating status
The STOP mode is set by executing the STOP instruction. It can be set only with the main system clock.
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Cautions 1. When the STOP mode is set, the X2 pin is internally connected to VDD via a pull-up resistor
to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode
in a system where an external clock is used for the main system clock.
2. Because the interrupt request signal is used to release the standby mode, if there is an
interrupt source with the interrupt request flag set and the interrupt mask flag reset, the
standby mode is immediately released if set. Thus, the STOP mode is reset to the HALT
mode immediately after execution of the STOP instruction. After the wait set using the
oscillation stabilization time select register (OSTS), the operating mode is set.
3. To stop the main system clock by using the STOP instruction or setting bit 7 (MCC) of
the processor clock control register (PCC) to 1, be sure to set bit 0 (STREQ) of the control
register (CTR) to 1 and confirm that the IEBus controller has entered the standby status.
The standby status can be confirmed by reading bit 1 (STM) of status register 2 (STR2).
The operating status in the STOP mode is described below.
Table 21-3. STOP Mode Operating Status
Setting of STOP Mode
Item
With Subsystem Clock
Without Subsystem Clock
Clock generator
Only main system clock stops oscillation.
CPU
Operation stops.
Port (output latch)
Status before STOP mode setting is held.
16-bit timer/event counter 0
Operable when watch timer output is
selected as count clock (fXT is selected as
count clock of watch timer)
8-bit timer/event counters 1 and 2
Operable when TI1 and TI2 are selected for the count clock.
Watch timer
Operable when fXT is selected for the
count clock.
Watchdog timer
Operation stops.
Operation stops.
Operation stops.
A/D converter
D/A converter
Operable.
Real-time output port
Operable when external trigger is used or TI1 and TI2 are selected for the 8-bit
timer/event counter count clock.
Serial interface
Other than
automatic
transmit/receive
function and
UART
Operable when externally supplied clock is specified as the serial clock.
Automatic
transmit/receive
function and
UART
Operation stops.
IEBus controller
External interrupt
Bus line for
external
expansion
Operation stops (internal data is retained)
INTP0
Not operable.
INTP1 to INTP6
Operable.
AD0 to AD7
High impedance.
A0 to A15
Status before STOP mode setting is held.
ASTB
Low level.
WR, RD
High level.
WAIT
High impedance.
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(2) STOP mode release
The STOP mode can be released by the following three sources.
(a) Release by unmasked interrupt request
If an unmasked interrupt request is generated, the STOP mode is released. If interrupt acknowledgement
is enabled after the lapse of the oscillation stabilization time, vectored interrupt servicing is carried out.
If interrupt acknowledgement is disabled, the next address instruction is executed.
Figure 21-4. Releasing STOP Mode by Interrupt Request Generation
STOP
Instruction
Interrupt
Request
Wait
(Time set by OSTS)
Standby
Release Signal
Clock
Operating
Mode
STOP Mode
Oscillation Stabilization
Wait Status
Oscillation
Oscillation Stop
Oscillation
Operating
Mode
Remark The broken lines indicate the case when the interrupt request that has released the standby
status is acknowledged.
(b) Releasing by unmasked test input
If an unmasked test signal is input, the STOP mode is released. After the lapse of the oscillation
stabilization time, the instruction at the next address after the STOP instruction is executed.
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(c) Releasing by RESET input
If the RESET signal is input, the STOP mode is released and after the lapse of the oscillation stabilization
time, a reset operation is carried out.
Figure 21-5. Releasing STOP Mode by RESET Input
Wait
(217/f x : 21.8 ms)
STOP
Instruction
RESET
Signal
Operating
Mode
Reset
Period
STOP Mode
Operating
Mode
Oscillation
Oscillation Stop
Oscillation
Oscillation
Stabilization
Wait Status
Clock
Remarks 1. fX: Main system clock oscillation frequency
2. ( ): fX: 6.0 MHz
Table 21-4. Operation After STOP Mode Release
Release Source
Maskable interrupt request
Test input
RESET input
MK××
PR××
IE
ISP
Operation
0
0
0
×
Next address instruction execution
0
0
1
×
Interrupt service execution
0
1
0
1
Next address instruction execution
0
1
×
0
0
1
1
1
Interrupt service execution
1
×
×
×
STOP mode hold
0
–
×
×
Next address instruction execution
1
–
×
×
STOP mode hold
–
–
×
×
Reset processing
×: Don't care
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CHAPTER 22 RESET FUNCTION
CHAPTER 22 RESET FUNCTION
22.1 Reset Function
The following two operations are available to generate the reset signal.
(1)
External reset input via RESET pin
(2)
Internal reset by watchdog timer program loop time detection
External reset and internal reset have no functional differences. In both cases, program execution starts at the
address at 0000H and 0001H by RESET input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each item of
hardware is set to the status shown in Table 22-1. Each pin is high impedance during reset input or during the
oscillation stabilization time just after reset release.
When a high level is input to the RESET pin, the reset is released and program execution starts after the lapse
of the oscillation stabilization time (217/fX). The reset applied by watchdog timer overflow is automatically released
after the reset and program execution starts after the lapse of the oscillation stabilization time (217/fX) (see Figures
22-2 to 22-4).
Cautions 1. For an external reset, input a low level to the RESET pin for 10 µs or more.
2. During reset input, main system clock oscillation remains stopped but subsystem clock
oscillation continues.
3. When the STOP mode is released by reset, the STOP mode contents are held during reset
input. However, the port pin becomes high-impedance.
Figure 22-1. Block Diagram of Reset Function
RESET
Count Clock
Watchdog Timer
Stop
470
Reset
Signal
Reset Controller
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Overflow
Interrupt
Function
CHAPTER 22 RESET FUNCTION
Figure 22-2. Timing of Reset by RESET Input
X1
Oscillation
Stabilization
Time Wait
Reset Period
(Oscillation
Stop)
Normal Operation
Normal Operation
(Reset Processing)
RESET
Internal
Reset Signal
Delay
Delay
Hi-Z
Port Pin
Figure 22-3. Timing of Reset due to Watchdog Timer Overflow
X1
Reset Period
(Oscillation
Stop)
Normal Operation
Watchdog
Timer
Overflow
Oscillation
Stabilization
Time Wait
Normal Operation
(Reset Processing)
Internal
Reset Signal
Hi-Z
Port Pin
Figure 22-4. Timing of Reset by RESET Input in STOP Mode
X1
STOP Instruction Execution
Stop Status
(Oscillation
Stop)
Normal Operation
Reset Period
(Oscillation
Stop)
Oscillation
Stabilization
Time Wait
Normal Operation
(Reset Processing)
RESET
Internal
Reset Signal
Delay
Delay
Hi-Z
Port Pin
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CHAPTER 22 RESET FUNCTION
Table 22-1. Hardware Status After Reset (1/3)
Hardware
Program counter (PC)
Status After Reset
Note 1
The contents of reset vector
tables (0000H and 0001H) are
set.
Stack pointer (SP)
Undefined
Program status word (PSW)
RAM
Port (output latch)
02H
Data memory
UndefinedNote 2
General-purpose register
UndefinedNote 2
Ports 0 to 3, Port 7, 12, 13
(P0 to P3, P7, P12, P13)
00H
Port 4 to Port 6 (P4 to P6)
Undefined
Port mode register (PM0 to PM3, PM5 to PM7, PM12, PM13)
FFH
Pull-up resistor option register (PUOH, PUOL)
00H
Processor clock control register (PCC)
04H
Oscillation mode selection register (OSMS)
00H
Clock select registers 1 and 2 (IECL1, IECL2)
00H
Note 3
Memory size switching register (IMS)
Internal expansion RAM size switching register (IXS)Note 4
08H
Memory expansion mode register (MM)
10H
Oscillation stabilization time select register (OSTS)
04H
16-bit timer/event counter
00H
Timer counter 0 (TM0)
Capture/compare register 00, 01 (CR00, CR01)
8-bit timer/event counter 1 and 2
Undefined
Clock select register 0 (TCL0)
00H
Mode control register 0 (TMC0)
00H
Capture/compare control register 0 (CRC0)
04H
Output control register 0 (TOC0)
00H
Timer counters 1, 2 (TM1, TM2)
00H
Compare registers 10, 20 (CR10, CR20)
Undefined
Clock select register 1 (TCL1)
00H
Mode control register 1 (TMC1)
00H
Output control register 1 (TOC1)
00H
Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
2. If the reset signal is input in the standby mode, the status before reset is retained even after reset.
3. The values after reset depend on the product.
µPD78095B: CAH, µPD78096B: CCH, µPD78098B, 78P098B: CFH
4. Provided only in the µPD78098B and 78P098B.
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Table 22-1. Hardware Status After Reset (2/3)
Hardware
Watch timer
Watchdog timer
Serial interface
Status After Reset
Mode control register 2 (TMC2)
00H
Clock select register 2 (TCL2)
00H
Mode register (WDTM)
00H
Clock select register 3 (TCL3)
Shift registers 0, 1 (SIO0, SIO1)
Mode registers 0 to 2 (CSIM0, CSIM1, CSIM2)
Serial bus interface control register (SBIC)
Slave address register (SVA)
88H
Undefined
00H
00H
Undefined
Automatic data transmit/receive control register (ADTC)
00H
Automatic data transmit/receive address pointer (ADTP)
00H
Automatic data transmit/receive interval specify register (ADTI)
00H
Asynchronous serial interface mode register (ASIM)
00H
Asynchronous serial interface status register (ASIS)
00H
Baud rate generator control register (BRGC)
00H
Transmit shift register (TXS)
FFH
Receive buffer register (RXB)
Interrupt timing specify register (SINT)
A/D converter
Mode register (ADM)
Conversion result register (ADCR)
Input select register (ADIS)
D/A converter
Real-time output port
00H
01H
Undefined
00H
Mode register (DAM)
00H
Conversion value setting registers 0, 1 (DACS0, DACS1)
00H
Mode register (RTPM)
00H
Control register (RTPC)
00H
Buffer register (RTBL, RTBH)
00H
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Table 22-1. Hardware Status After Reset (3/3)
Hardware
IEBus controller
Status After Reset
Clock select registers 1, 2 (IECL1, IECL2)
00H
A/D current cut select register (IEAD)
00H
IEBus controller mode register (IECM)
00H
Control register (CTR)
×××00×01B
Status register 1 (STR1)
01011×××B
Command register (CMR)
00H
Status register 2 (STR2)
Unit address register 1 (UAR1)
Number of receive data register 1 (RDR1)
Unit address register 2 (UAR2)
Number of receive data register 2 (RDR2)
Slave address register 1 (SAR1)
02H
Undefined
00H
Undefined
00H
Undefined
Lock address register 1 (LOR1)
Slave address register 2 (SAR2)
Undefined
Lock address register 2 (LOR2)
0000××××B
Master communication control register (MCR)
Undefined
Broadcast destination address register 1 (DAR1)
Broadcast destination address register 2 (DAR2)
Return code register (RCR)
Transmit buffer register (TBF)
Undefined
4FH
Undefined
Receive buffer register (RBF)
Interrupt
474
Request flag registers 0L, 0H, 1L (IF0L, IF0H, IF1L)
00H
Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L)
FFH
Priority specify flag registers 0L, 0H, 1L (PR0L, PR0H, PR1L)
FFH
External interrupt mode registers 0, 1 (INTM0, INTM1)
00H
Key return mode register (KRM)
02H
Sampling clock select register (SCS)
00H
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µPD78P098B
CHAPTER 23 µPD78P098B
The µPD78P098B replaces the internal mask ROM of the µPD78098B with one-time PROM. Table 23-1 lists the
differences between the µPD78P098B and the mask ROM versions.
Table 23-1. Differences Between µPD78P098B and Mask ROM Versions
µPD78P098B
Item
Mask ROM Version
Internal ROM structure
One-time PROM
Mask ROM
Internal ROM capacity
60 KB
µPD78095B: 40 KB
µPD78096B: 48 KB
µPD78098B: 60 KB
Internal expansion RAM capacity
2,048 bytes
µPD78095B: None
µPD78096B: None
µPD78098B: 2,048 bytes
Changing internal ROM and internal highspeed RAM capacities with memory size
switching register (IMS)
PossibleNote 1
ImpossibleNote 2
Changing of internal expansion RAM
PossibleNote 3
Impossible
IC pin
None
Available
VPP pin
Available
None
Mask option for connecting on-chip pull-
None
Available
capacity by internal expansion RAM size
switching register (IXS)
up resistor to P60 to P63 pins
Electrical specifications
Refer to the separate data sheet.
Notes 1. The internal PROM and internal high-speed RAM capacities are set as follows by RESET input:
Internal PROM: 60 KB
Internal high-speed RAM: 1,024 bytes
2. Except when the external device expansion function of the µPD78098B is used.
3. The internal expansion RAM is set to 2,048 bytes by RESET input.
Caution There are differences in noise immunity and noise radiation between the PROM and mask ROM
versions. When pre-producing an application set with the PROM version and then massproducing it with the mask ROM version, be sure to conduct sufficient evaluations using
commercial samples (not engineering samples) of the mask ROM version.
Remark
Only the µPD78098B and 78P098B are provided with an internal expansion RAM size switching register.
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23.1 Memory Size Switching Register
Users can define the internal ROM and high-speed RAM sizes in the µPD78P098B using the memory size switching
register (IMS), so that the same memory mapping as that of a mask ROM version with a different-size internal ROM
and high-speed RAM is possible.
IMS is set with an 8-bit memory manipulation instruction.
RESET input sets IMS to CFH.
Figure 23-1. Format of Memory Size Switching Register
Symbol
7
6
5
IMS RAM2 RAM1 RAM0
4
0
3
2
1
1
0
Other than above
After
Reset
R/W
FFF0H
CFH
R/W
Internal High-Speed RAM Capacity Selection
1,024 bytes
Setting prohibited
ROM3 ROM2 ROM1 ROM0
Internal ROM Capacity Selection
1
0
1
0
40 KB
1
1
0
0
48 KB
1
1
1
0
56 KB
1
1
1
1
60 KB
Other than above
Address
ROM3 ROM2 ROM1 ROM0
RAM2 RAM1 RAM0
1
0
Setting prohibited
The IMS settings to give the same memory map as mask ROM versions are shown in Table 23-2.
Table 23-2. Examples of Memory Size Switching Register Settings
Relevant Mask ROM Version
476
IMS Setting
µPD78095B
CAH
µPD78096B
CCH
µPD78098B
CFH
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µPD78P098B
23.2 Internal Expansion RAM Size Switching Register
Users can define the internal expansion RAM size in the µPD78P098B by using the internal expansion RAM size
switching register (IXS), so that the same memory mapping as that of a mask ROM version with a different-size internal
expansion RAM is possible.
IXS is set with an 8-bit memory manipulation instruction.
RESET input sets IXS to 08H.
Figure 23-2. Format of Internal Expansion RAM Size Switching Register
Symbol
7
6
5
4
IXS
0
0
0
0
3
2
1
Address
After
Reset
R/W
FFF4H
08H
W
IXRAM3 IXRAM2 IXRAM1 IXRAM0
IXRAM3 IXRAM2 IXRAM1 IXRAM0
Internal Extension RAM Capacity Selection
1
1
0
0
0 bytes
1
0
0
0
2,048 bytes
Other than above
0
Setting prohibited
The IXS settings to give the same memory map as mask ROM versions are shown in Table 23-3.
Table 23-3. Values Set to Internal Expansion RAM Size Switching Register
Relevant Mask ROM Version
µPD78095B
IXS Setting
0CH
µPD78096B
µPD78098B
08H
Remark: If a program for the µPD78P098B which includes
“MOV IXS, #0CH” is implemented with the
µPD78095B or 78096B, this instruction is ignored
and causes no malfunction.
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23.3 PROM Programming
The µ PD78P098B incorporates a 60 KB PROM as program memory.
To write a program into the
µ PD78P098B PROM, set the device in PROM programming mode by setting the levels of the V PP and RESET
pins as specified. For the connection of unused pins, see (2) “PROM programming mode” in 1.4 Pin
Configuration (Top View).
Caution Write the program in the range of addresses 0000H to EFFFH (specify the last address as
EFFFH).
The program cannot be correctly written by a PROM programmer that does not have a write
address specification function.
23.3.1 Operating modes
When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the µPD78P098B
is set to a PROM programming mode. This is one of the operating modes shown in Table 23-4 below according to
the setting of the CE, OE, and PGM pins.
The PROM contents can be read when the operating mode is the read mode.
Table 23-4. PROM Programming Operating Modes
Pin
RESET
VPP
VDD
CE
OE
PGM
D0 to D7
L
+12.5 V
+6.5 V
H
L
H
Data input
Page write
H
H
L
High impedance
Byte write
L
H
L
Data input
Program verify
L
L
H
Data output
Program inhibit
×
H
H
High impedance
×
L
L
L
L
H
Data output
L
H
×
High impedance
H
×
×
High impedance
Operating Mode
Page data latch
Read
Output disable
+5 V
Standby
+5 V
×: L or H
(1) Read mode
Read mode is set by setting CE and OE to L.
(2) Output disable mode
If OE is set to H, data output becomes high impedance and the output disable mode is set.
Therefore, if multiple µPD78P098Bs are connected to the data bus, data can be read from any one device
by controlling the OE pin.
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(3) Standby mode
Setting CE to H sets the standby mode.
In this mode, data output becomes high impedance irrespective of the status of OE.
(4) Page data latch mode
Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode.
In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit.
(5) Page write mode
After a 1-page 4-byte address and data are latched by the page data latch mode, a page write is executed
by applying a 0.1 ms program pulse (active-low) to the PGM pin while CE = H and OE = H. After this, program
verification can be performed by setting CE to L and OE to L.
If programming is not performed by one program pulse, repeated write and verify operations are executed
X times (X ≤ 10).
(6) Byte write mode
A byte write is executed by applying a 0.1 ms program pulse (active-low) to the PGM pin while CE = L and
OE = H. After this, program verification can be performed by setting OE to L.
If programming is not performed by one program pulse, repeated write and verify operations are executed
X times (X ≤ 10).
(7) Program verify mode
Setting CE to L, PGM to H, and OE to L sets the program verify mode.
After writing is performed, this mode should be used to check whether the data was written correctly.
(8) Program inhibit mode
The program inhibit mode is used when the OE pins, VPP pins and pins D0 to D7 of multiple µPD78P098Bs
are connected in parallel and any one of these devices must be written to.
The page write mode or byte write mode described above is used to perform a write. At this time, the write
is not performed on the device which has the PGM pin driven high.
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23.3.2 PROM write procedure
Figure 23-3. Page Program Mode Flowchart
Start
Address = G
VDD = 6.5 V, VPP = 12.5 V
X=0
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
Address = Address + 1
Address = Address + 1
Latch
X=X+1
No
X = 10?
0.1-ms program pulse
Yes
Fail
Verify 4 Bytes
Pass
No
Address = N?
Yes
VDD = 4.5 to 5.5 V, VPP = VDD
Pass
All bytes verified?
Fail
All Pass
End of write
Remark G = Start address
N = Last address of program
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Figure 23-4. Page Program Mode Timing
Page Data Latch
Page
Program
Program Verify
A2 to A16
A0, A1
D0 to D7
Data Input
Data Output
VPP
VPP
VDD
VDD+1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
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Figure 23-5. Byte Program Mode Flowchart
Start
Address = G
VDD = 6.5 V, VPP = 12.5 V
X=0
X=X+1
No
X = 10?
0.1-ms program pulse
Address = Address + 1
Verify
Yes
Fail
Pass
No
Address = N?
Yes
VDD = 4.5 to 5.5 V, VPP = VDD
Pass
All bytes verified?
Fail
All Pass
End of write
Remark G = Start address
N = Last address of program
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Figure 23-6. Byte Program Mode Timing
Program
Program Verify
A0 to A16
D0 to D7
Data Input
Data Output
VPP
VPP
VDD
VDD+1.5
VDD
VDD
VIH
CE
VIL
VIH
PGM
VIL
VIH
OE
VIL
Cautions 1. Be sure to apply VDD before applying VPP, and cut it after cutting VPP.
2. VPP must not exceed +13.5 V including overshoot voltage.
3. Removing/inserting the device from/in the on-board socket while +12.5 V is being applied to
the VPP pin may have an adverse affect on device reliability.
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23.3.3 PROM reading procedure
PROM contents can be read to the external data bus (D0 to D7) using the following procedure.
(1) Fix the RESET pin low, and supply +5 V to the VPP pin. Unused pins are handled as shown in (2) “PROM
programming mode” in section 1.4 Pin Configuration (Top View).
(2) Supply +5 V to the VDD and VPP pins.
(3) Input the address of the data to be read to pins A0 to A16.
(4) Read mode is entered.
(5) Data is output to pins D0 to D7.
The timing for steps (2) through (5) above is shown in Figure 23-7.
Figure 23-7. PROM Read Timing
A0 to A16
Address Input
CE (Input)
OE (Input)
Hi-Z
Hi-Z
D0 to D7
Data Output
23.4 Screening of One-Time PROM Versions
One-time PROM versions (µPD78P098BGC-8BT) cannot be fully tested by NEC before shipment due to the
structure of one-time PROM. Therefore, after users have written data into the PROM, screening should be
implemented by the user: that is, store devices at a high temperature for one day as specified below, and verify
their contents after the devices have returned to room temperature.
Storage Temperature
Storage Time
125°C
24 hours
For users who do not wish to implement screening by themselves, NEC provides a service (for a fee) in which
NEC performs a series of processes from writing one-time PROMs and screening them to verifying their contents
for users by request.
The PROM version devices for which this service is provided are called QTOPTM
microcontrollers. For details, please consult an NEC sales representative.
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CHAPTER 24
INSTRUCTION SET
CHAPTER 24 INSTRUCTION SET
This chapter describes the instruction set of the µPD78098B Subseries as a list table. For details of the operation
and operation code of each instruction, refer to the separate document “78K/0 Series Instruction User’s Manual
(U12326E).”
24.1 Conventions
24.1.1 Operand identifiers and description methods
Operands are described in the “Operand” column of each instruction in accordance with the description method
of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more
description methods, select one of them. Uppercase letters and the symbols #, !, $ and [ ] are key words and must
be described as they are. Each symbol has the following meaning.
• #:
Immediate data specification
• !:
Absolute address specification
• $:
Relative address specification
• [ ]:
Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $, and [ ] symbols.
For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Table 24-1. Operand Identifiers and Description Methods
Identifier
Description Method
r
rp
sfr
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7),
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special-function register symbolNote
sfrp
Special-function register symbol (16-bit manipulatable register even addresses only)Note
saddr
saddrp
FE20H to FF1FH Immediate data or labels
FE20H to FF1FH Immediate data or labels (even address only)
addr16
addr11
addr5
0000H to FFFFH Immediate data or labels
(Only even addresses for 16-bit data transfer instructions)
0800H to 0FFFH Immediate data or labels
0040H to 007FH Immediate data or labels (even address only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
RBn
RB0 to RB3
Note
Addresses from FFD0H to FFDFH cannot be accessed with these operands.
Remark
For special-function register symbols, refer to Table 3-2 Special-Function Register List.
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24.1.2 Description of “operation” column
A:
A register; 8-bit accumulator
X:
X register
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
AX register pair; 16-bit accumulator
BC:
BC register pair
DE:
DE register pair
HL:
HL register pair
PC:
Program counter
SP:
Stack pointer
PSW:
Program status word
CY:
Carry flag
AC:
Auxiliary carry flag
Z:
Zero flag
RBS:
Register bank select flag
IE:
Interrupt request enable flag
NMIS:
Non-maskable interrupt servicing flag
( ):
Memory contents indicated by address or register contents in parentheses
×H, ×L:
Higher 8 bits and lower 8 bits of 16-bit register
:
Logical product (AND)
:
Logical sum (OR)
:
——:
Exclusive logical sum (exclusive OR)
Inverted data
addr16: 16-bit immediate data or label
jdisp8:
Signed 8-bit data (displacement value)
24.1.3 Description of “flag operation” column
(Blank): Nt affected
0:
Cleared to 0
1:
Set to 1
×:
Set/cleared according to the result
R:
Previously saved value is restored
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INSTRUCTION SET
24.2 Operation List
Clock
Instruction
Mnemonic
Group
8-bit data
transfer
MOV
Operands
Byte
r, #byte
2
Note 2
4
–
Flag
Operation
3
6
7
(saddr) ← byte
sfr, #byte
3
–
7
sfr ← byte
A, r
Note 3
1
2
–
A←r
r, A
Note 3
1
2
–
r←A
A, saddr
2
4
5
A ← (saddr)
saddr, A
2
4
5
(saddr) ← A
A, sfr
2
–
5
A ← sfr
sfr, A
2
–
5
sfr ← A
A, !addr16
3
8
9+n
A ← (addr16)
!addr16, A
3
8
9+m
(addr16) ← A
PSW, #byte
3
–
7
PSW ← byte
A, PSW
2
–
5
A ← PSW
PSW, A
2
–
5
PSW ← A
A, [DE]
1
4
5+n
A ← (DE)
[DE], A
1
4
5+m
(DE) ← A
A, [HL]
1
4
5+n
A ← (HL)
[HL], A
1
4
5+m
(HL) ← A
A, [HL + byte]
2
8
9+n
A ← (HL + byte)
[HL + byte], A
2
8
9+m
(HL + byte) ← A
A, [HL + B]
1
6
7+n
A ← (HL + B)
[HL + B], A
1
6
7+m
(HL + B) ← A
A, [HL + C]
1
6
7+n
A ← (HL + C)
1
6
7+m
(HL + C) ← A
1
2
–
A, r
Note 3
Z AC CY
r ← byte
saddr, #byte
[HL + C], A
XCH
Note 1
×
×
×
×
×
×
A↔r
A, saddr
2
4
6
A ↔ (saddr)
A, sfr
2
–
6
A ↔ sfr
A, !addr16
3
8
10 + n + m A ↔ (addr16)
A, [DE]
1
4
6+n+m
A ↔ (DE)
A, [HL]
1
4
6+n+m
A ↔ (HL)
A, [HL + byte]
2
8
10 + n + m A ↔ (HL + byte)
A, [HL + B]
2
8
10 + n + m A ↔ (HL + B)
A, [HL + C]
2
8
10 + n + m A ↔ (HL + C)
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed.
3. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written to.
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Clock
Instruction
Mnemonic
Group
16-bit
data
transfer
MOVW
Operands
Byte
Note 2
Flag
Operation
Z AC CY
3
6
–
rp ← word
saddrp, #word
4
8
10
(saddrp) ← word
sfrp, #word
4
–
10
sfrp ← word
AX, saddrp
2
6
8
AX ← (saddrp)
saddrp, AX
2
6
8
(saddrp) ← AX
AX, sfrp
2
–
8
AX ← sfrp
2
–
8
sfrp ← AX
AX, rp
Note 3
1
4
–
AX ← rp
rp, AX
Note 3
1
4
–
rp ← AX
3
10
12 + 2n AX ← (addr16)
3
10
12 + 2m (addr16) ← AX
1
4
–
AX ↔ rp
2
4
–
A, CY ← A + byte
×
×
×
3
6
8
(saddr), CY ← (saddr) + byte
×
×
×
AX, !addr16
!addr16, AX
XCHW
AX, rp
ADD
A, #byte
Note 3
saddr, #byte
2
4
–
A, CY ← A + r
×
×
×
r, A
2
4
–
r, CY ← r + A
×
×
×
A, saddr
2
4
5
A, CY ← A + (saddr)
×
×
×
A, !addr16
3
8
9+n
A, CY ← A + (addr16)
×
×
×
A, r
ADDC
Note 1
rp, #word
sfrp, AX
8-bit
operation
INSTRUCTION SET
Note 4
A, [HL]
1
4
5+n
A, CY ← A + (HL)
×
×
×
A, [HL + byte]
2
8
9+n
A, CY ← A + (HL + byte)
×
×
×
A, [HL + B]
2
8
9+n
A, CY ← A + (HL + B)
×
×
×
A, [HL + C]
2
8
9+n
A, CY ← A + (HL + C)
×
×
×
A, #byte
2
4
–
A, CY ← A + byte + CY
×
×
×
saddr, #byte
3
6
8
(saddr), CY ← (saddr) + byte + CY
×
×
×
2
4
–
A, CY ← A + r + CY
×
×
×
r, A
2
4
–
r, CY ← r + A + CY
×
×
×
A, saddr
2
4
5
A, CY ← A + (saddr) + CY
×
×
×
A, !addr16
3
8
9+n
A, CY ← A + (addr16) + CY
×
×
×
A, [HL]
1
4
5+n
A, CY ← A + (HL) + CY
×
×
×
A, [HL + byte]
2
8
9+n
A, CY ← A + (HL + byte) + CY
×
×
×
A, r
Note 4
A, [HL + B]
2
8
9+n
A, CY ← A + (HL + B) + CY
×
×
×
A, [HL + C]
2
8
9+n
A, CY ← A + (HL + C) + CY
×
×
×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Only when rp = BC, DE or HL
4. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written to.
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Clock
Instruction
Mnemonic
Group
8-bit
operation
SUB
Operands
Byte
A, #byte
saddr, #byte
Note 2
2
4
–
A, CY ← A – byte
×
×
×
3
6
8
(saddr), CY ← (saddr) – byte
×
×
×
Z AC CY
2
4
–
A, CY ← A – r
×
×
×
2
4
–
r, CY ← r – A
×
×
×
A, saddr
2
4
5
A, CY ← A – (saddr)
×
×
×
A, !addr16
3
8
9+n
A, CY ← A – (addr16)
×
×
×
Note 3
A, [HL]
1
4
5+n
A, CY ← A – (HL)
×
×
×
A, [HL + byte]
2
8
9+n
A, CY ← A – (HL + byte)
×
×
×
A, [HL + B]
2
8
9+n
A, CY ← A – (HL + B)
×
×
×
A, [HL + C]
2
8
9+n
A, CY ← A – (HL + C)
×
×
×
A, #byte
2
4
–
A, CY ← A – byte – CY
×
×
×
saddr, #byte
3
6
8
(saddr), CY ← (saddr) – byte – CY
×
×
×
2
4
–
A, CY ← A – r – CY
×
×
×
r, A
2
4
–
r, CY ← r – A – CY
×
×
×
A, saddr
2
4
5
A, CY ← A – (saddr) – CY
×
×
×
A, !addr16
3
8
9+n
A, CY ← A – (addr16) – CY
×
×
×
A, [HL]
1
4
5+n
A, CY ← A – (HL) – CY
×
×
×
A, [HL + byte]
2
8
9+n
A, CY ← A – (HL + byte) – CY
×
×
×
A, r
AND
Flag
Operation
Note 1
r, A
A, r
SUBC
INSTRUCTION SET
Note 3
A, [HL + B]
2
8
9+n
A, CY ← A – (HL + B) – CY
×
×
×
A, [HL + C]
2
8
9+n
A, CY ← A – (HL + C) – CY
×
×
×
A, #byte
2
4
–
A←A
×
3
6
8
(saddr) ← (saddr)
saddr, #byte
byte
byte
×
2
4
–
A←A
r, A
2
4
–
r←r
A, saddr
2
4
5
A←A
(saddr)
×
A, !addr16
3
8
9+n
A←A
(addr16)
×
A, r
Note 3
r
×
×
A
A, [HL]
1
4
5+n
A←A
(HL)
×
A, [HL + byte]
2
8
9+n
A←A
(HL + byte)
×
A, [HL + B]
2
8
9+n
A←A
(HL + B)
×
A, [HL + C]
2
8
9+n
A←A
(HL + C)
×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written to.
User’s Manual U12761EJ2V0UM
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CHAPTER 24
Clock
Instruction
Mnemonic
Group
8-bit
operation
OR
Operands
Byte
A, #byte
saddr, #byte
Note 2
2
4
–
A ← A byte
×
3
6
8
(saddr) ← (saddr) byte
×
Z AC CY
2
4
–
A←A r
×
2
4
–
r←r A
×
A, saddr
2
4
5
A ← A (saddr)
×
A, !addr16
3
8
9+n
A ← A (addr16)
×
Note 3
A, [HL]
1
4
5+n
A ← A (HL)
×
A, [HL + byte]
2
8
9+n
A ← A (HL + byte)
×
A, [HL + B]
2
8
9+n
A ← A (HL + B)
×
A, [HL + C]
2
8
9+n
A ← A (HL + C)
×
A, #byte
2
4
–
A←A
saddr, #byte
3
6
8
(saddr) ← (saddr)
2
4
–
A←A
r, A
2
4
–
r←r
A, saddr
2
4
5
A←A
(saddr)
×
A, !addr16
3
8
9+n
A←A
(addr16)
×
A, [HL]
1
4
5+n
A←A
(HL)
×
A, [HL + byte]
2
8
9+n
A←A
(HL + byte)
×
A, r
CMP
Flag
Operation
Note 1
r, A
A, r
XOR
INSTRUCTION SET
Note 3
×
byte
byte
r
×
×
×
A
A, [HL + B]
2
8
9+n
A←A
(HL + B)
×
A, [HL + C]
2
8
9+n
A←A
(HL + C)
×
A, #byte
2
4
–
A – byte
×
×
×
3
6
8
(saddr) – byte
×
×
×
saddr, #byte
2
4
–
A–r
×
×
×
r, A
2
4
–
r–A
×
×
×
A, saddr
2
4
5
A – (saddr)
×
×
×
A, !addr16
3
8
9+n
A – (addr16)
×
×
×
A, r
Note 3
A, [HL]
1
4
5+n
A – (HL)
×
×
×
A, [HL + byte]
2
8
9+n
A – (HL + byte)
×
×
×
A, [HL + B]
2
8
9+n
A – (HL + B)
×
×
×
A, [HL + C]
2
8
9+n
A – (HL + C)
×
×
×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except "r = A"
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written to.
490
User’s Manual U12761EJ2V0UM
CHAPTER 24
Clock
Instruction
Mnemonic
Group
16-bit
operation
Multiply/
divide
Bit
manipulate
Byte
Note 1
Note 2
Flag
Operation
Z AC CY
AX, #word
3
6
–
AX, CY ← AX + word
×
×
×
SUBW
AX, #word
3
6
–
AX, CY ← AX – word
×
×
×
CMPW
AX, #word
3
6
–
AX – word
×
×
×
MULU
X
2
16
–
AX ← A × X
DIVUW
C
2
25
–
AX (Quotient), C (Remainder) ← AX ÷ C
r
1
2
–
r←r+1
×
×
saddr
2
4
6
(saddr) ← (saddr) + 1
×
×
r
1
2
–
r←r–1
×
×
saddr
2
4
6
(saddr) ← (saddr) – 1
×
×
INCW
rp
1
4
–
rp ← rp + 1
DECW
rp
1
4
–
rp ← rp – 1
ROR
A, 1
1
2
–
(CY, A7 ← A0, Am – 1 ← Am) × 1 time
×
ROL
A, 1
1
2
–
(CY, A0 ← A7, Am + 1 ← Am) × 1 time
×
RORC
A, 1
1
2
–
(CY ← A0, A7 ← CY, Am – 1 ← Am) × 1 time
×
ROLC
A, 1
1
2
–
(CY ← A7, A0 ← CY, A m + 1 ← Am) × 1 time
×
DEC
BCD
adjust
Operands
ADDW
Increment/ INC
decrement
Rotate
INSTRUCTION SET
ROR4
[HL]
2
10
A3 – 0 ← (HL)3 – 0, (HL)7 – 4 ← A3 – 0,
12 + n + m
(HL)3 – 0 ← (HL)7 – 4
ROL4
[HL]
2
10
12 + n + m
A3 – 0 ← (HL)7 – 4, (HL)3 – 0 ← A3 – 0,
(HL)7 – 4 ← (HL)3 – 0
ADJBA
2
4
–
Decimal Adjust Accumulator after
Addition
×
×
×
ADJBS
2
4
–
Decimal Adjust Accumulator after
Subtract
×
×
×
CY, saddr.bit
3
6
7
CY ← (saddr.bit)
×
CY, sfr.bit
3
–
7
CY ← sfr.bit
×
CY, A.bit
2
4
–
CY ← A.bit
×
CY, PSW.bit
3
–
7
CY ← PSW.bit
×
CY, [HL].bit
2
6
7+n
CY ← (HL).bit
×
saddr.bit, CY
3
6
8
(saddr.bit) ← CY
sfr.bit, CY
3
–
8
sfr.bit ← CY
A.bit, CY
2
4
–
A.bit ← CY
PSW.bit, CY
3
–
8
PSW.bit ← CY
[HL].bit, CY
2
6
8+n+m
(HL).bit ← CY
MOV1
×
×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written to.
User’s Manual U12761EJ2V0UM
491
CHAPTER 24
Clock
Instruction
Mnemonic
Group
Bit
manipulate
AND1
OR1
XOR1
SET1
INSTRUCTION SET
Operands
Byte
Note 1
Note 2
Flag
Operation
Z AC CY
CY, saddr.bit
3
6
7
CY ← CY
(saddr.bit)
×
CY, sfr.bit
3
–
7
CY ← CY
sfr.bit
×
CY, A.bit
2
4
–
CY ← CY
A.bit
×
CY, PSW.bit
3
–
7
CY ← CY
PSW.bit
×
CY, [HL].bit
2
6
7+n
CY ← CY
(HL).bit
×
CY, saddr.bit
3
6
7
CY ← CY (saddr.bit)
×
CY, sfr.bit
3
–
7
CY ← CY sfr.bit
×
CY, A.bit
2
4
–
CY ← CY A.bit
×
CY, PSW.bit
3
–
7
CY ← CY PSW.bit
×
CY, [HL].bit
2
6
7+n
CY ← CY (HL).bit
×
CY, saddr.bit
3
6
7
CY ← CY
(saddr.bit)
×
CY, sfr.bit
3
–
7
CY ← CY
sfr.bit
×
CY, A.bit
2
4
–
CY ← CY
A.bit
×
CY, PSW. bit
3
–
7
CY ← CY
PSW.bit
×
CY ← CY
(HL).bit
×
CY, [HL].bit
2
6
7+n
saddr.bit
2
4
6
(saddr.bit) ← 1
sfr.bit
3
–
8
sfr.bit ← 1
A.bit
2
4
–
A.bit ← 1
6
PSW.bit ← 1
×
×
×
×
×
×
PSW.bit
2
–
[HL].bit
2
6
saddr.bit
2
4
6
(saddr.bit) ← 0
sfr.bit
3
–
8
sfr.bit ← 0
A.bit
2
4
–
A.bit ← 0
PSW.bit
2
–
6
PSW.bit ← 0
[HL].bit
2
6
CY
1
2
–
CY ← 1
1
CLR1
CY
1
2
–
CY ← 0
0
NOT1
CY
1
2
–
CY ← CY
×
CLR1
SET1
8 + n + m (HL).bit ← 1
8 + n + m (HL).bit ← 0
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written to.
492
User’s Manual U12761EJ2V0UM
CHAPTER 24
Clock
Instruction
Mnemonic
Group
Call/return
Stack
manipulate
Operands
Byte
Note 1
Note 2
Flag
Operation
Z AC CY
(SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,
PC ← addr16, SP ← SP – 2
CALL
!addr16
3
7
–
CALLF
!addr11
2
5
–
(SP – 1) ← (PC + 2)H, (SP – 2) ← (PC + 2)L,
PC15 – 11 ← 00001, PC10 – 0 ← addr11,
SP ← SP – 2
CALLT
[addr5]
1
6
–
(SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP – 2
BRK
1
6
–
(SP – 1) ← PSW, (SP – 2) ← (PC + 1)H,
(SP – 3) ← (PC + 1)L, PCH ← (003FH),
PCL ← (003EH), SP ← SP – 3, IE ← 0
RET
1
6
–
RETI
1
6
–
RETB
1
6
–
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3
PSW
1
2
–
(SP – 1) ← PSW, SP ← SP – 1
rp
1
4
–
(SP – 1) ← rpH, (SP – 2) ← rpL,
SP ← SP – 2
PSW
1
2
–
PSW ← (SP), SP ← SP + 1
rp
1
4
–
rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
SP, #word
4
–
10
SP ← word
SP, AX
2
–
8
SP ← AX
PUSH
POP
MOVW
Unconditional
branch
INSTRUCTION SET
BR
PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0
AX, SP
2
–
8
AX ← SP
!addr16
3
6
–
PC ← addr16
$addr16
2
6
–
PC ← PC + 2 + jdisp8
AX
2
8
–
PCH ← A, PCL ← X
$addr16
2
6
–
PC ← PC + 2 + jdisp8 if CY = 1
$addr16
2
6
–
PC ← PC + 2 + jdisp8 if CY = 0
BZ
$addr16
2
6
–
PC ← PC + 2 + jdisp8 if Z = 1
BNZ
$addr16
2
6
–
PC ← PC + 2 + jdisp8 if Z = 0
Conditional BC
branch
BNC
R
R
R
R
R R
R
R
R
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written to.
User’s Manual U12761EJ2V0UM
493
CHAPTER 24
Clock
Instruction
Mnemonic
Group
Conditional
branch
BT
BF
Operands
Byte
Note 1
Note 2
Flag
Operation
Z AC CY
saddr.bit, $addr16
3
8
9
PC ← PC + 3 + jdisp8 if(saddr.bit) = 1
sfr.bit, $addr16
4
–
11
PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16
3
8
–
PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr16
3
–
9
PC ← PC + 3 + jdisp8 if PSW.bit = 1
[HL].bit, $addr16
3
10
11 + n
PC ← PC + 3 + jdisp8 if (HL).bit = 1
saddr.bit, $addr16
4
10
11
PC ← PC + 4 + jdisp8 if(saddr.bit) = 0
sfr.bit, $addr16
4
–
11
PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16
3
8
–
PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr16
4
–
11
PC ← PC + 4 + jdisp8 if PSW. bit = 0
[HL].bit, $addr16
3
10
11 + n
saddr.bit, $addr16
4
10
12
sfr.bit, $addr16
4
–
12
PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr16
3
8
–
PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr16
4
–
12
PC ← PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
[HL].bit, $addr16
3
10
12 + n + m
PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
B, $addr16
2
6
–
B ← B – 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16
2
6
–
C ← C –1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
saddr. $addr16
3
8
10
(saddr) ← (saddr) – 1, then
PC ← PC + 3 + jdisp8 if(saddr) ≠ 0
RBn
2
4
–
RBS1, 0 ← n
NOP
1
2
–
No Operation
EI
2
–
6
IE ← 1(Enable Interrupt)
DI
2
–
6
IE ← 0(Disable Interrupt)
HALT
2
6
–
Set HALT Mode
STOP
2
6
–
Set STOP Mode
BTCLR
DBNZ
CPU
control
INSTRUCTION SET
SEL
PC ← PC + 3 + jdisp8 if (HL).bit = 0
PC ← PC + 4 + jdisp8
if(saddr.bit) = 1
then reset(saddr.bit)
×
×
×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (fCPU) selected by the processor clock
control register (PCC).
2. This clock cycle applies to the internal ROM program.
3. n is the number of waits when the external memory expansion area is read.
4. m is the number of waits when the external memory expansion area is written to.
494
User’s Manual U12761EJ2V0UM
CHAPTER 24
INSTRUCTION SET
24.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
User’s Manual U12761EJ2V0UM
495
CHAPTER 24
INSTRUCTION SET
Second Operand
[HL + byte]
#byte
A
r Note
sfr
saddr
!addr16
PSW
[DE]
[HL]
First Operand
A
r
ADD
MOV
MOV
MOV
MOV
ADDC
XCH
XCH
XCH
XCH
SUB
ADD
ADD
ADD
MOV
[HL + B] $addr16
[HL + C]
MOV
MOV
MOV
ROR
XCH
XCH
XCH
ROL
ADD
ADD
RORC
SUBC
ADDC
ADDC ADDC
ADDC ADDC
AND
SUB
SUB
SUB
OR
SUBC
SUBC SUBC
SUB
None
ROLC
SUB
SUBC SUBC
XOR
AND
AND
AND
AND
AND
CMP
OR
OR
OR
OR
OR
MOV
1
XOR
XOR
XOR
XOR
XOR
CMP
CMP
CMP
CMP
CMP
MOV
INC
ADD
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
B, C
DBNZ
sfr
MOV
MOV
saddr
MOV
MOV
DBNZ
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
MOV
PSW
MOV
MOV
PUSH
POP
[DE]
MOV
[HL]
MOV
ROR4
ROL4
[HL + byte]
MOV
[HL + B]
[HL + C]
X
MULU
C
DIVUW
Note
496
Except r = A
User’s Manual U12761EJ2V0UM
CHAPTER 24
INSTRUCTION SET
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
#word
AX
rp Note
sfrp
saddrp
!addr16
SP
None
First Operand
AX
ADDW
MOVW
SUBW
XCHW
MOVW
MOVW
MOVW
MOVW
CMPW
rp
MOVW
MOVWNote
INCW
DECW
PUSH
POP
sfrp
MOVW
MOVW
saddrp
MOVW
MOVW
!addr16
MOVW
SP
MOVW
Note
MOVW
Only when rp = BC, DE, HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
First Operand
A.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
sfr.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
saddr.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
PSW.bit
MOV1
BT
SET1
BF
CLR1
BTCLR
[HL].bit
MOV1
BT
SET1
BF
CLR1
BTCLR
CY
MOV1
MOV1
MOV1
MOV1
MOV1
SET1
AND1
AND1
AND1
AND1
AND1
CLR1
NOT1
OR1
OR1
OR1
OR1
OR1
XOR1
XOR1
XOR1
XOR1
XOR1
User’s Manual U12761EJ2V0UM
497
CHAPTER 24
INSTRUCTION SET
(4) Call/instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand
AX
!addr16
!addr11
[addr5]
$addr16
First Operand
Basic instruction
BR
CALL
BR
CALLF
CALLT
Compound
instruction
BT
BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
498
BR
BC
BNC
BZ
BNZ
User’s Manual U12761EJ2V0UM
APPENDIX A
DEVELOPMENT TOOLS
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems that employ the µPD78098B
Subseries.
Figure A-1 shows the configuration of the development tools.
• PC98-NX series support
Unless otherwise specified, products supported by IBM PC/ATTM compatibles can be used for PC98-NX
series products. For the use of the PC98-NX series, refer to the explanation of IBM PC/AT compatibles.
• Windows
Unless otherwise specified, “Windows” indicates the following OSs.
• Windows 3.1
• Windows 95, 98, 2000
• Windows NTTM Ver. 4.0
User’s Manual U12761EJ2V0UM
499
APPENDIX A
DEVELOPMENT TOOLS
Figure A-1. Development Tool Configuration
Language Processing Software
PROM Programmer Control Software
• PG-1500 Controller
• Assembler Package
• C Compiler Package
• C Library Source File
• Device File
Debugging Tool
• System Simulator
• Integrated Debugger
• Device File
Embedded Software
• Real-Time OS
• OS
Host Machine (PC)
Interface Adapter,
PC card Interface, etc.
PROM Write
Environment
In-Circuit Emulator
Emulation Board
PROM
programmer
I/O Board
Programmer
adapter
Power Supply Unit
Performance Board
Emulation Probe
PROM version
Conversion Socket or
Conversion Adapter
Target System
Remark Items in broken line boxes differ according to the development environment. See A.3.1 Hardware.
500
User’s Manual U12761EJ2V0UM
APPENDIX A
DEVELOPMENT TOOLS
A.1 Software Package
SP78K0
Development tools (software) common to 78K0 Series included in one package
78K0 Series software
Part number: µS××××SP78K0
package
Remark
“××××” in the part number differs depending on the host machine and OS used.
µS××××SP78K0
××××
Host Machine
OS
AB13
PC-9800 series,
Japanese Windows
BB13
IBM PC/AT compatibles
English Windows
AB17
Japanese Windows
BB17
English Windows
Supply Medium
3.5-inch 2HD FD
CD-ROM
A.2 Language Processing Software
RA78K0
This assembler converts a program written in mnemonics into object codes executable with a
Assembler Package
microcontroller.
Further, this assembler is provided with functions capable of automatically creating symbol tables
and branch instruction optimization.
Used in combination with a device file (DF78098) (sold separately).
<Cautions when using in PC environment>
The assembler package is a DOS-based application, however, it can be used in a Windows
environment by using the Project Manager (included in the assembler package) on Windows.
Part Number: µS××××RA78K/0
CC78K0
This compiler converts a program written in C language into object codes executable with
C Compiler Package
microcontroller.
Used in combination with the assembler package (RA78K0) and device file (DF78098) (both sold
separately).
<Cautions when using in PC environment>
The C compiler package is a DOS-based application, however, it can be used in a Windows
environment by using the Project Manager (included in the assembler package) on Windows
Part Number: µS××××CC78K/0
DF78098Note
This is a file containing information inherent to the device.
Device File
Used in combination with a tool (RA78K0, CC78K0, SM78K0, or ID78K0-NS) (all sold separately).
The supported OS and host machine depend on the tool(s) used in combination.
Part Number: µS××××DF78098
CC78K0-L
This is a function source program that configures the object library included in the C compiler package.
C Library Source File
This file is necessary for changing the object library included in the C compiler package in
accordance with the customer’s specifications.
Since this is a source file, the operating environment does not depend on the OS.
Part Number: µS××××CC78K0-L
Note
The DF78098 can be used commonly with the RA78K0, CC78K0, SM78K0, and ID78K0-NS.
Remark
×××× in the part number differs depending on the host machine used. Refer to the table below.
User’s Manual U12761EJ2V0UM
501
APPENDIX A
DEVELOPMENT TOOLS
µS××××RA78K0
µS××××CC78K0
××××
Host Machine
OS
AB13
PC-9800 series,
Japanese Windows
BB13
IBM PC/AT compatibles
English Windows
AB17
Japanese Windows
BB17
English Windows
3P17
HP9000 series 700™
3K17
SPARCstation™
Supply Medium
3.5-inch 2HD FD
CD-ROM
HP-UX™ (Rel. 10.10)
SunOS™ (Rel. 4.1.4)
Solaris™ (Rel. 2.5.1)
µS××××DF78098
µS××××CC78K0-L
××××
OS
Supply Medium
AB13
PC-9800 series,
Japanese Windows
BB13
IBM PC/AT compatibles
English Windows
3P16
HP9000 series 700
HP-UX (Rel. 10.10)
DAT
3K13
SPARCstation
SunOS (Rel. 4.1.4)
3.5-inch 2HD FD
Solaris (Rel. 2.5.1)
1/4-inch CGMT
3K15
502
Host Machine
User’s Manual U12761EJ2V0UM
3.5-inch 2HD FD
APPENDIX A
DEVELOPMENT TOOLS
A.3 PROM Programming Tools
A.3.1 Hardware
PG-1500
This is a PROM programmer capable of programming a single-chip microcontroller with on-chip
PROM programmer
PROM either stand-alone or by manipulating from the host machine by connecting the
separately available programmer adapter and the supplied board. It can also program separate
PROM ICs with a capacity from 256 K to 4 Mb.
PA-78P054GC
PROM programmer adapter common to the µPD78P054 and is connected to the PG-1500.
PROM programmer
PA-78P054GC: 80-pin plastic QFP (14 × 14)
adapter
A.3.2 Software
PG-1500 controller
This program controls the PG-1500 from the host machine via serial and/or parallel interface
cable(s).
Part Number: µS××××PG1500
Remark
×××× in the part number differs depending on the host machine and OS used. Refer to the table below.
µS××××PG1500
××××
5A13
Host Machine
PC-9800 series
OS
MS-DOS
(Ver. 3.30 to 6.2
7B13
Note
IBM PC/AT compatibles
Supply Medium
Refer to A.4.
3.5-inch 2HD FD
Note)
3.5-inch 2HD FD
The task swap function is provided in MS-DOS version 5.0 or later, but is not
available with this software.
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503
APPENDIX A
DEVELOPMENT TOOLS
A.4 Debugging Tools
A.4.1 Hardware
IE-78K0-NS
In-circuit emulator
This in-circuit emulator is used to debug hardware and software when developing
application systems using a 78K/0 Series product. It supports an integrated debugger
(ID78K0-NS). This emulator should be used in combination with a power supply unit,
emulation probe, and interface adapter, which is required to connect this emulator to
the host machine.
IE-78K0-NS-PA
Performance board
This board is required when expanding the functions of the IE-78K0-NS. It should be
used connected to the IE-78K0-NS. Adding this board enhances debug functions
(addition of coverage function, enhancement of tracer function and timer function,
etc.)
IE-78K0-NS-A
In-circuit emulator
This is the IE-78K0-NS combined with the IE-78K0-NS-PA.
IE-70000-MC-PS-B
Power supply unit
This adapter is used for supplying power from a socket of 100 V to 240 V AC.
IE-70000-98-IF-C
Interface adapter
This adapter is required when using a PC-9800 series computer (except notebook
PC) as the IE-78K0-NS host machine (C-bus supported).
IE-70000-CD-IF-A
PC card interface
This is the PC card and interface cable required when using a notebook PC as the
IE-78K0-NS host machine (PCMCIA-socket supported).
IE-70000-PC-IF-C
Interface adapter
This adapter is required when using an IBM PC compatible computer as the
IE-78K0-NS host machine (ISA-bus supported).
IE-70000-PCI-IF
Interface adapter
This adapter is required when connecting a personal computer that includes a PCI
bus as the host machine of the IE-78K0-NS.
IE-78098-NS-EM4
Probe board
This board emulates the operations of the peripheral hardware peculiar to a device. It
should be used in combination with an in-circuit emulator and I/O board.
NP-80GC
Emulation probe
This probe is used to connect the in-circuit emulator to the target system and is
designed for an 80-pin plastic QFP (GC-8BT type).
EV-9200GC-80
Conversion socket
(Refer to Figures
A-2 and A-3)
This conversion socket connects the NP-80GC to a target system board designed to
mount an 80-pin plastic QFP (GC-8BT type).
Remarks 1. The NP-80GC is manufactured by Naito Densei Machida Mfg. Co., Ltd.
For more information, consult Naito Densei Machida Mfg. Co., Ltd. (TEL: +8-45-475-4191)
2. The EV-9200GC-80 is sold in sets of five.
504
User’s Manual U12761EJ2V0UM
APPENDIX A
DEVELOPMENT TOOLS
A.4.2 Software (1/2)
SM78K0
This simulator can debug the target system at C source level or assembler level while simulating
System simulator
operation of the target system on the host machine.
SM78K0 runs on Windows.
By using the SM78K0, the logic and performance of the application can be verified without an incircuit emulator independently of hardware development, so that development efficiency and
software quality can be improved.
This simulator is used with a device file (DF78098) (sold separately).
Part Number: µS××××SM78K0
Remark
×××× in the part number differs depending on the host machine and OS used. Refer to the table below.
µS××××SM78K0
××××
AB13
Host Machine
IBM PC/AT compatibles
OS
Japanese Windows
BB13
English Windows
AB17
Japanese Windows
BB17
English Windows
User’s Manual U12761EJ2V0UM
Supply Medium
3.5-inch 2HD FD
CD-ROM
505
APPENDIX A
DEVELOPMENT TOOLS
A.4.2 Software (2/2)
ID78K0-NS
This is a control program that debugs the 78K/0 Series.
integrated debugger
This program employs Windows as the graphical user interface, and provides appearance and
(Supporting In-circuit
operability conforming to this interface. In addition debugging functions supporting C language
emulator IE-78K0-NS)
are reinforced. Trace results can be displayed at the C level by using the window integration
function that links the source program, disassemble display, and memory display with trace
results. Moreover, the debugging efficiency of a program using a real-time OS can be enhanced
by using function expansion modules such as a task debugger and system performance analyzer.
This program is used in combination with a device file (DF78098) (sold separately).
Part Number: µS××××ID78K0-NS
Remark
×××× in the part number differs depending on the host machine and OS used. Refer to the table below.
µS××××ID78K0-NS
××××
AB13
506
Host Machine
IBM PC/AT compatibles
OS
Japanese Windows
BB13
English Windows
AB17
Japanese Windows
BB17
English Windows
User’s Manual U12761EJ2V0UM
Supply Medium
3.5-inch 2HD FD
CD-ROM
APPENDIX A
DEVELOPMENT TOOLS
Drawing and Footprint for Conversion Socket (EV-9200GC-80)
Figure A-2. EV-9200GC-80 Drawing (For Reference Only)
A
E
M
B
N
O
L
K
S
J
C
D
R
F
EV-9200GC-80
Q
1
No.1 pin index
P
G
H
I
EV-9200GC-80-G0
ITEM
MILLIMETERS
INCHES
A
18.0
0.709
B
14.4
0.567
C
14.4
0.567
D
18.0
0.709
E
4-C 2.0
4-C 0.079
F
0.8
0.031
G
6.0
0.236
H
16.0
0.63
I
18.7
0.736
J
6.0
0.236
K
16.0
0.63
L
18.7
0.736
M
8.2
0.323
O
8.0
0.315
N
2.5
0.098
P
2.0
0.079
Q
0.35
0.014
R
φ 2.3
φ 0.091
S
φ 1.5
φ 0.059
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APPENDIX A
DEVELOPMENT TOOLS
Figure A-3. EV-9200GC-80 Footprint (For Reference Only)
G
J
H
D
E
F
K
I
L
C
B
A
EV-9200GC-80-P1E
ITEM
MILLIMETERS
A
19.7
B
15.0
0.776
0.591
C
0.65±0.02 × 19=12.35±0.05
D
+0.003
0.65±0.02 × 19=12.35±0.05 0.026+0.001
–0.002 × 0.748=0.486 –0.002
0.026+0.001
–0.002
× 0.748=0.486+0.003
–0.002
E
15.0
0.591
F
19.7
0.776
G
6.0 ± 0.05
0.236+0.003
–0.002
H
6.0 ± 0.05
0.236+0.003
–0.002
I
0.35 ± 0.02
0.014+0.001
–0.001
J
φ 2.36 ± 0.03
φ 0.093+0.001
–0.002
K
φ 2.3
φ 0.091
L
φ 1.57 ± 0.03
φ 0.062+0.001
–0.002
Caution
508
INCHES
Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (C10535E).
User’s Manual U12761EJ2V0UM
APPENDIX B
APPENDIX B
EMBEDDED SOFTWARE
EMBEDDED SOFTWARE
This section describes the embedded software provided for the µPD78098B Subseries to allow users to develop
and maintain application programs for this subseries.
Real-time OS
The RX78K0 is a real-time OS conforming to the µITRON specifications.
A tool (configurator) for generating the nucleus of the RX78K0 and plural information
tables are supplied.
This product is used in combination with an assembler package (RA78K0) and
device file (DF78098) (both sold separately).
<Cautions when using RX78K0 in PC environment>
The real-time OS is a DOS-based application. It should be used in the DOS Prompt
when using in Windows.
RX78K0
Real-time OS
Part number: µS××××RX78013-∆∆∆∆
Caution When purchasing the RX78K0, fill in the purchase application form in advance and sign the user
agreement.
Remark
×××× and ∆∆∆∆ in the part number differ depending on the host machine and OS used.
µS××××RX78013-∆∆∆∆
∆∆∆∆
Product Outline
Maximum Number for Use in Mass Production
001
Evaluation object
Do not use for mass-produced product.
100K
Mass-production object
0.1 million units
001M
1 million units
010M
S01
××××
10 million units
Source program
Source program for mass-produced object
Host Machine
OS
Supply Medium
(Japanese)Note
3.5-inch 2HD FD
3.5-inch 2HD FD
AA13
PC-9800 series
Windows
AB13
IBM PC/AT compatibles
Windows (Japanese)Note
Windows (English)Note
BB13
3P16
HP9000 series 700
HP-UX (Rel. 10.10)
DAT
3K13
SPARCstation
SunOS (Rel. 4.1.4),
3.5-inch 2HD FD
Solaris (Rel. 2.5.1)
1/4-inch CGMT
3K15
Note
Can also be operated in a DOS environment.
User’s Manual U12761EJ2V0UM
509
APPENDIX C
APPENDIX C
REGISTER INDEX
REGISTER INDEX
C.1 Register Index
8-bit timer counter 1 (TM1) ................................................................................................................................ 193
8-bit timer counter 2 (TM2) ................................................................................................................................ 193
8-bit timer mode control register 1 (TMC1) ...................................................................................................... 190
8-bit timer output control register 1 (TOC1) ..................................................................................................... 191
16-bit timer counter 0 (TM0) .............................................................................................................................. 144
16-bit timer mode control register 0 (TMC0) .................................................................................................... 146
16-bit timer output control register 0 (TOC0) ................................................................................................... 149
[A]
A/D conversion result register (ADCR) ............................................................................................................. 230
A/D converter input select register (ADIS) ....................................................................................................... 233
A/D converter mode register (ADM) .................................................................................................................. 231
A/D current cut select register (IEAD) .............................................................................................................. 235
Asynchronous serial interface mode register (ASIM) .............................................................. 352, 360, 362, 375
Asynchronous serial interface status register (ASIS) .............................................................................. 354, 363
Automatic data transmit/receive address pointer (ADTP) ................................................................................ 308
Automatic data transmit/receive control register (ADTC) ....................................................................... 312, 321
Automatic data transmit/receive interval specify register (ADTI) ........................................................... 313, 322
[B]
Baud rate generator control register (BRGC) .................................................................................. 355, 364, 376
Broadcast destination address register 1 (DAR1) ............................................................................................ 451
Broadcast destination address register 2 (DAR2) ............................................................................................ 451
[C]
Capture/compare control register 0 (CRC0) ..................................................................................................... 148
Capture/compare register 00 (CR00) ................................................................................................................ 143
Capture/compare register 01 (CR01) ................................................................................................................ 143
Clock select register 1 (IECL1) ................................................................................................................ 125, 439
Clock select register 2 (IECL2) ......................................................................................................................... 125
Command register (CMR) .................................................................................................................................. 442
Compare register 10 (CR10) ............................................................................................................................. 187
Compare register 20 (CR20) ............................................................................................................................. 187
Control register (CTR) ........................................................................................................................................ 440
[D]
D/A conversion value set register 0 (DACS0) .................................................................................................. 250
D/A conversion value set register 1 (DACS1) .................................................................................................. 250
D/A converter mode register (DAM) .................................................................................................................. 251
[E]
External interrupt mode register (INTM0) ................................................................................................ 152, 398
External interrupt mode register (INTM1) ................................................................................................ 234, 398
510
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APPENDIX C
REGISTER INDEX
[I]
IEBus controller mode register (IECM) ............................................................................................................. 440
Internal expansion RAM size switching register (IXS) ..................................................................................... 477
Interrupt mask flag register 0H (MK0H) ............................................................................................................ 396
Interrupt mask flag register 0L (MK0L) ............................................................................................................. 396
Interrupt mask flag register 1L (MK1L) .................................................................................................... 396, 415
Interrupt request flag register 0H (IF0H) ........................................................................................................... 395
Interrupt request flag register 0L (IF0L) ............................................................................................................ 395
Interrupt request flag register 1L (IF1L) ................................................................................................... 395, 415
Interrupt timing specification register (SINT) ................................................................................... 266, 284, 301
[K]
Key return mode register (KRM) .............................................................................................................. 116, 416
[L]
Lock address register 1 (LOR1) ........................................................................................................................ 452
Lock address register 2 (LOR2) ........................................................................................................................ 452
[M]
Master communication control register (MCR) ................................................................................................. 443
Memory expansion mode register (MM) .................................................................................................. 115, 420
Memory size switching register (IMS) ...................................................................................................... 421, 476
[N]
Number of receive data register 1 (RDR1) ....................................................................................................... 447
Number of receive data register 2 (RDR2) ....................................................................................................... 447
[O]
Oscillation mode selection register (OSMS) ..................................................................................................... 124
Oscillation stabilization time select register (OSTS) ........................................................................................ 463
[P]
Port 0 (P0) ........................................................................................................................................................... 95
Port 1 (P1) ........................................................................................................................................................... 97
Port 2 (P2) ........................................................................................................................................................... 98
Port 3 (P3) ......................................................................................................................................................... 100
Port 4 (P4) ......................................................................................................................................................... 101
Port 5 (P5) ......................................................................................................................................................... 102
Port 6 (P6) ......................................................................................................................................................... 103
Port 7 (P7) ......................................................................................................................................................... 105
Port 12 (P12) ...................................................................................................................................................... 107
Port 13 (P13) ...................................................................................................................................................... 110
Port mode register 0 (PM0) ............................................................................................................................... 111
Port mode register 1 (PM1) ............................................................................................................................... 111
Port mode register 2 (PM2) ............................................................................................................................... 111
Port mode register 3 (PM3) ............................................................................................. 111, 151, 192, 223, 227
Port mode register 5 (PM5) ............................................................................................................................... 111
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511
APPENDIX C
REGISTER INDEX
Port mode register 6 (PM6) ............................................................................................................................... 111
Port mode register 7 (PM7) ............................................................................................................................... 111
Port mode register 12 (PM12) .................................................................................................................. 111, 387
Port mode register 13 (PM13) ........................................................................................................................... 111
Priority specification flag register 0H (PR0H) ................................................................................................... 397
Priority specification flag register 0L (PR0L) .................................................................................................... 397
Priority specification flag register 1L (PR1L) .................................................................................................... 397
Processor clock control register (PCC) ............................................................................................................. 122
Program status word (PSW) ....................................................................................................................... 70, 402
Pull-up resistor option register H (PUOH) ........................................................................................................ 114
Pull-up resistor option register L (PUOL) .......................................................................................................... 114
[R]
Real-time output buffer register H (RTBH) ....................................................................................................... 386
Real-time output buffer register L (RTBL) ........................................................................................................ 386
Real-time output port control register (RTPC) .................................................................................................. 388
Real-time output port mode register (RTPM) ................................................................................................... 387
Receive buffer register (RBF) ............................................................................................................................ 438
Receive buffer register (RXB) ........................................................................................................................... 350
Receive shift register (RXS) .............................................................................................................................. 350
Return code register (RCR) ............................................................................................................................... 447
[S]
Sampling clock select register (SCS) ....................................................................................................... 153, 400
Serial bus interface control register (SBIC) ............................................................................. 264, 270, 282, 301
Serial I/O shift register 0 (SIO0) ........................................................................................................................ 258
Serial I/O shift register 1 (SIO1) ........................................................................................................................ 308
Serial operating mode register 0 (CSIM0) ...................................................................... 262, 267, 268, 281, 300
Serial operating mode register 1 (CSIM1) ............................................................................... 311, 315, 316, 319
Serial operating mode register 2 (CSIM2) ............................................................................... 351, 359, 361, 374
Slave address register (SVA) ............................................................................................................................ 258
Slave address register 1 (SAR1) ....................................................................................................................... 451
Slave address register 2 (SAR2) ....................................................................................................................... 451
Status register 1 (STR1) .................................................................................................................................... 445
Status register 2 (STR2) .................................................................................................................................... 446
Successive approximation register (SAR) ........................................................................................................ 230
[T]
Timer clock select register 0 (TCL0) ........................................................................................................ 144, 221
Timer clock select register 1 (TCL1) ................................................................................................................. 188
Timer clock select register 2 (TCL2) ................................................................................................ 205, 214, 225
Timer clock select register 3 (TCL3) ........................................................................................................ 260, 309
Transmit buffer register (TBF) ........................................................................................................................... 437
Transmit shift register (TXS) ............................................................................................................................. 350
[U]
Unit address register 1 (UAR1) ......................................................................................................................... 450
Unit address register 2 (UAR2) ......................................................................................................................... 450
512
User’s Manual U12761EJ2V0UM
APPENDIX C
REGISTER INDEX
[W]
Watch timer mode control register (TMC2) ...................................................................................................... 208
Watchdog timer mode control register (WDTM) ............................................................................................... 216
User’s Manual U12761EJ2V0UM
513
APPENDIX C
REGISTER INDEX
C.2 Register Index (Symbol)
[A]
ADCR:
A/D conversion result register ........................................................................................................ 230
ADIS:
A/D converter input select register ................................................................................................. 233
ADM:
A/D converter mode register .......................................................................................................... 231
ADTC:
Automatic data transmit/receive control register .................................................................. 312, 321
ADTI:
Automatic data transmit/receive interval specify register .................................................... 313, 322
ADTP:
Automatic data transmit/receive address pointer .......................................................................... 308
ASIM:
Asynchronous serial interface mode register ....................................................... 352, 360, 362, 375
ASIS:
Asynchronous serial interface status register ...................................................................... 354, 363
[B]
BRGC:
Baud rate generator control register ............................................................................. 355, 364, 376
[C]
CMR:
Command register ........................................................................................................................... 442
CR00:
Capture/compare register 00 .......................................................................................................... 143
CR01:
Capture/compare register 01 .......................................................................................................... 143
CR10:
Compare register 10 ....................................................................................................................... 187
CR20:
Compare register 20 ....................................................................................................................... 187
CRC0:
Capture/compare control register 0 ............................................................................................... 148
CSIM0:
Serial operating mode register 0 .................................................................. 262, 268, 300, 281, 300
CSIM1:
Serial operating mode register 1 ........................................................................... 311, 315, 316, 319
CSIM2:
Serial operating mode register 2 ........................................................................... 351, 359, 361, 374
CTR:
Control register ................................................................................................................................ 440
[D]
DACS0:
D/A conversion value set register 0 ............................................................................................... 250
DACS1:
D/A conversion value set register 1 ............................................................................................... 250
DAM:
D/A converter mode register .......................................................................................................... 251
DAR1:
Broadcast destination address register 1 ...................................................................................... 451
DAR2:
Broadcast destination address register 2 ...................................................................................... 451
[I]
IEAD:
A/D current cut select register ........................................................................................................ 235
IECL1:
Clock select register 1 ........................................................................................................... 125, 439
IECL2:
Clock select register 2 .................................................................................................................... 125
IECM:
IEBus controller mode register ....................................................................................................... 440
IF0H:
Interrupt request flag register 0H ................................................................................................... 395
IF0L:
Interrupt request flag register 0L .................................................................................................... 395
IF1L:
Interrupt request flag register 1L ........................................................................................... 395, 415
IMS:
Memory size switching register ............................................................................................. 421, 476
INTM0:
External interrupt mode register ............................................................................................ 152, 398
INTM1:
External interrupt mode register ............................................................................................ 234, 398
IXS:
Internal expansion RAM size switching register ........................................................................... 477
514
User’s Manual U12761EJ2V0UM
APPENDIX C
REGISTER INDEX
[K]
KRM:
Key return mode register ....................................................................................................... 116, 416
[L]
LOR1:
Lock address register 1 .................................................................................................................. 452
LOR2:
Lock address register 2 .................................................................................................................. 452
[M]
MCR:
Master communication control register .......................................................................................... 443
MK0H:
Interrupt mask flag register 0H ....................................................................................................... 396
MK0L:
Interrupt mask flag register 0L ....................................................................................................... 396
MK1L:
Interrupt mask flag register 1L .............................................................................................. 396, 415
MM:
Memory expansion mode register ......................................................................................... 115, 420
[O]
OSMS:
Oscillation mode selection register ................................................................................................ 124
OSTS:
Oscillation stabilization time select register ................................................................................... 463
[P]
P0:
Port 0 ................................................................................................................................................. 95
P1:
Port 1 ................................................................................................................................................. 97
P2:
Port 2 ................................................................................................................................................. 98
P3:
Port 3 ............................................................................................................................................... 100
P4:
Port 4 ............................................................................................................................................... 101
P5:
Port 5 ............................................................................................................................................... 102
P6:
Port 6 ............................................................................................................................................... 103
P7:
Port 7 ............................................................................................................................................... 105
P12:
Port 12 ............................................................................................................................................. 107
P13:
Port 13 ............................................................................................................................................. 110
PCC:
Processor clock control register ..................................................................................................... 122
PM0:
Port mode register 0 ....................................................................................................................... 111
PM1:
Port mode register 1 ....................................................................................................................... 111
PM2:
Port mode register 2 ....................................................................................................................... 111
PM3:
Port mode register 3 ..................................................................................... 111, 151, 192, 223, 227
PM5:
Port mode register 5 ....................................................................................................................... 111
PM6:
Port mode register 6 ....................................................................................................................... 111
PM7:
Port mode register 7 ....................................................................................................................... 111
PM12:
Port mode register 12 ............................................................................................................ 111, 387
PM13:
Port mode register 13 ..................................................................................................................... 111
PR0H:
Priority specification flag register 0H ............................................................................................. 397
PR0L:
Priority specification flag register 0L .............................................................................................. 397
PR1L:
Priority specification flag register 1L .............................................................................................. 397
PSW:
Program status word ................................................................................................................ 70, 402
PUOH:
Pull-up resistor option register H ................................................................................................... 114
PUOL:
Pull-up resistor option register L .................................................................................................... 114
User’s Manual U12761EJ2V0UM
515
APPENDIX C
REGISTER INDEX
[R]
RBF:
Receive buffer register ................................................................................................................... 438
RCR:
Return code register ....................................................................................................................... 447
RDR1:
Number of receive data register 1 ................................................................................................. 447
RDR2:
Number of receive data register 2 ................................................................................................. 447
RTBH:
Real-time output buffer register H .................................................................................................. 386
RTBL:
Real-time output buffer register L .................................................................................................. 386
RTPC:
Real-time output port control register ............................................................................................ 388
RTPM:
Real-time output port mode register .............................................................................................. 387
RXB:
Receive buffer register ................................................................................................................... 350
RXS:
Receive shift register ...................................................................................................................... 350
[S]
SAR:
Successive approximation register ................................................................................................ 230
SAR1:
Slave address register .................................................................................................................... 451
SAR2:
Slave address register .................................................................................................................... 451
SBIC:
Serial bus interface control register ......................................................................264, 270, 282, 301
SCS:
Sampling clock select register ............................................................................................... 153, 400
SINT:
Interrupt timing specification register ............................................................................ 266, 284, 301
SIO0:
Serial I/O shift register 0 ................................................................................................................. 258
SIO1:
Serial I/O shift register 1 ................................................................................................................. 308
SRT1:
Status register 1 .............................................................................................................................. 445
SRT2:
Status register 2 .............................................................................................................................. 446
SVA:
Slave address register .................................................................................................................... 258
[T]
TBF:
Transmit buffer register .................................................................................................................. 437
TCL0:
Timer clock select register 0 ................................................................................................. 144, 221
TCL1:
Timer clock select register 1 .......................................................................................................... 188
TCL2:
Timer clock select register 2 ......................................................................................... 205, 214, 225
TCL3:
Timer clock select register 3 ................................................................................................. 260, 309
TM0:
16-bit timer counter 0 ...................................................................................................................... 144
TM1:
8-bit timer counter 1 ........................................................................................................................ 193
TM2:
8-bit timer counter 2 ........................................................................................................................ 193
TMC0:
16-bit timer mode control register 0 ............................................................................................... 146
TMC1:
8-bit timer mode control register 1 ................................................................................................. 190
TMC2:
Watch timer mode control register 2 .............................................................................................. 208
TOC0:
16-bit timer output control register 0 .............................................................................................. 149
TOC1:
8-bit timer output control register 1 ................................................................................................ 191
TXS:
Transmit shift register ..................................................................................................................... 350
[U]
UAR1:
Unit address register 1 ................................................................................................................... 450
UAR2:
Unit address register 2 ................................................................................................................... 450
[W]
WDTM:
516
Watchdog timer mode register ....................................................................................................... 216
User’s Manual U12761EJ2V0UM
APPENDIX D
APPENDIX D
REVISION HISTORY
REVISION HISTORY
(1/3)
Edition
2nd
Description
Change of part numbers
Applied to
Throughout
µPD78095BGC-×××-3B9 → µPD78095BGC-×××-8BT
µPD78096BGC-×××-3B9 → µPD78096BGC-×××-8BT
µPD78098BGC-×××-3B9 → µPD78098BGC-×××-8BT
µPD78P098BGC-3B9 → µPD78P098BGC-8BT
Addition of Caution in 2.2.9 P120 to P127 (Port 12)
CHAPTER2 PIN
Addition of recommended connection (I/O circuit) at output in Table 2-1 Pin I/O Circuit
FUNCTION
Types
Addition of Caution in Table 3-3 IEBus Register List
CHAPTER 3 CPU
ARCHTECTURE
Modification of Figure 5-7 Format of Clock Select Register 1
CHAPTER 5
CLOCK
GENERATOR
Modification of Caution 2 in Table 6-4 INTP0/TI00 Pin Valid Edge and CR00 Capture
CHAPTER 6 16-
Trigger Valid Edge
BIT TIMER/EVENT
Change of Caution in Figure 6-8 Format of External Interrupt Mode Register 0
COUNTER 0
Change of Figure 6-19 Timing of Pulse Width Measurement Operation by FreeRunning Counter and One Capture Register (with Both Edges Specified)
Addition of Figure 6-21 CR01 Capture Operation with Rising Edge Specified
Change of Figure 6-22 Timing of Pulse Width Measurement Operation by FreeRunning Counter (with Both Edges Specified)
Change of Figure 6-24 Timing of Pulse Width Measurement Operation by FreeRunning Counter and Two Capture Registers (with Rising Edge Specified)
Change of Figure 6-26 Timing of Pulse Width Measurement Operation by Restart
(with Rising Edge Specified)
Change of TI00 pin input to count clock in Figure 6-31 Square-Wave Output Operation
Timing
Addition of Note and modification of Caution in 6.5.7 One-shot pulse output operation
(1) One-shot pulse output using software trigger
Modification of (a) 16-bit timer mode control register 0 (TMC0) and Caution in Figure
6-32 Control Register Setting for One-Shot Pulse Output Operation Using Software
Trigger
Change of setting value of TMC0 in Figure 6-33 Timing of One-Shot Pulse Output
Operation Using Software Trigger
Addition of Note in 6.5.7 One-shot pulse output operation (2) One-shot pulse output
using external trigger
Modification of Caution in Figure 6-34 Control Register Settings for One-Shot Pulse
Output Operation Using External Trigger
User’s Manual U12761EJ2V0UM
517
APPENDIX D
REVISION HISTORY
(2/3)
Edition
2nd
Description
Deletion of following items in 6.6 Cautions for 16-Bit Timer/Event Counter 0
Applied to
CHAPTER 6 16-
(2) 16-bit compare register setting (when in the clear & start mode on match between BIT TIMER/EVENT
TM0 and CR00)
COUNTER 0
(3) Operation after compare register change during timer count operation
(4) Capture register data retention timing
(6) Re-trigger of one-shot pulse
(a) One-shot pulse output using software
(b) One-shot pulse output using external trigger
(7) Operation of OVF0 flag
(a) OVF0 flag setting
Addition of following items in 6.6 Cautions for 16-Bit Timer/Event Counter 0
(6) Re-trigger of one-shot pulse
(c) One-shot pulse output function
(7) Operation of OVF0 flag
(b) OVF0 flag clear
(8) Conflict operation
(9) Timer operation
(10) Capture operation
(11) Compare operation
(12) Edge detection
Change of Caution in Figure 8-2 Format of Timer Clock Select Register 2
CHAPTER 8
Addition of Figure 8-4 Watch Timer/Interval Timer Operation Timing
WATCH TIMER
Modification of Figure 9-2 Format of Timer Clock Select Register 2
CHAPTER 9
WATCHDOG
TIMER
Modification of Figure 11-2 Format of Timer Clock Select Register 2
CHAPTER 11
BUZZER OUTPUT
CONTROLLER
Addition of Caution in Figure 12-5 Format of A/D Current Cut Select Register
CHAPTER 12
Addition of 12.5 How to Read the A/D Converter Characteristics Table
A/D CONVERTER
Modification of (4) Pins ANI0/P10 to ANI7/P17 and (5) AVREF0 pin input impedance in
12.6 Cautions for A/D Converter
Addition of (9) A/D conversion result register (ADCR) read operation and (10) Timing
at which A/D conversion result is undefined in 12.6 Cautions for A/D Converter
Modification of Example of preventive measures in 16.4.4 Restrictions in UART mode CHAPTER 16
SERIAL
INTERFACE
CHANNEL 0
Addition of Remark in 18.2 Interrupt Source and Configuration
CHAPTER 18
Addition of Caution 3 in Figure 18-2 Format of Interrupt Request Flag Register
INTERRUPT AND
Change of Caution in Figure 18-5 Format of External Interrupt Mode Register 0
518
User’s Manual U12761EJ2V0UM
TEST FUNCTION
APPENDIX D
REVISION HISTORY
(3/3)
Edition
2nd
Description
Applied to
Addition of 19.4 Example of Connection with Memory
CHAPTER 19
EXTERNAL
DEVICE
EXPANSION
FUNCTION
Addition of Caution in 20.3 IEBus Controller Configuration
CHAPTER 20
Addition of Note in Figure 20-16 Command Register Format (for Option Setting)
IEBus
CONTROLLER
Addition of Notes in Figure 20-17 Format of Master Communication Control Register
Addition of description and Note 2 and Caution in Figure 20-19 Format of Status Register
2
Modification of APPENDIX A DEVELOPMENT TOOLS and APPENDIX B EMBEDDED
SOFTWARE
User’s Manual U12761EJ2V0UM
APPENDIX A
DEVELOPMENT
TOOLS/
APPENDIX B
EMBEDDED
SOFTWARE
519
APPENDIX D
REVISION HISTORY
[MEMO]
520
User’s Manual U12761EJ2V0UM
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