Institutionen för systemteknik Department of Electrical Engineering Electromigration Analysis of Signal Nets Examensarbete

Institutionen för systemteknik Department of Electrical Engineering Electromigration Analysis of Signal Nets Examensarbete
Institutionen för systemteknik
Department of Electrical Engineering
Examensarbete
Electromigration Analysis of Signal Nets
Examensarbete utfört i Elektroteknik
vid Tekniska högskolan vid Linköpings universitet
av
Rahul Nadgouda
LiTH-ISY-EX–14/4811–SE
Linköping 2014
Department of Electrical Engineering
Linköpings universitet
SE-581 83 Linköping, Sweden
Linköpings tekniska högskola
Linköpings universitet
581 83 Linköping
Electromigration Analysis of Signal Nets
Examensarbete utfört i Elektroteknik
vid Tekniska högskolan vid Linköpings universitet
av
Rahul Nadgouda
LiTH-ISY-EX–14/4811–SE
Handledare:
Professor Mark Vesterbacka
isy, Linköpings universitet
Examinator:
Dr J.J.Wikner
isy, Linköpings universitet
Linköping, 4 november 2014
Avdelning, Institution
Division, Department
Datum
Date
Avdelningen för ditten
Department of Electrical Engineering
SE-581 83 Linköping
2014-11-04
Språk
Language
Rapporttyp
Report category
ISBN
Svenska/Swedish
Licentiatavhandling
ISRN
Engelska/English
Examensarbete
C-uppsats
D-uppsats
—
LiTH-ISY-EX–14/4811–SE
Serietitel och serienummer
Title of series, numbering
Övrig rapport
ISSN
—
URL för elektronisk version
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-XXXXX
Titel
Title
Undersökning av ett problem
Författare
Author
Rahul Nadgouda
Electromigration Analysis of Signal Nets
Sammanfattning
Abstract
The scaling down of technologies presents new challenges in reliability, one of them being electromigration. Electromigration was not cause of concern until interconnects widths
shrunk to the micrometer scale. At this point, research was focused into electromigration
analysis of interconnects. International conferences on reliability have recognized electromigration as one of the biggest problems in reliability.
This thesis focuses on electromigration analysis of signal nets and was carried out in Design
Methodology department at a company in Eindhoven. The purpose of this thesis work was to
setup a flow for electromigration analysis using existing tools at the company. Comparison
of tools and theoretical study of electromigration also forms a big part of this internship.
A summary of theoretical studies on electromigration phenomenon and their implications
on design parameters is investigated in this thesis report. The approach of setting up tools,
evaluation strategy and results of the evaluation are also documented in this report. Lastly
a conclusion in a form of an effective design methodology and comparison of tools are presented.
This report also contains challenges encountered while setting up of tools and motivation
for enabling different options for electromigration analysis. Trade-offs between simulation
run time, parasitic extraction, chip area and reliability concerns are also discussed in this
report.
Nyckelord
Keywords
Electromigration, analog, design methodology, signal nets
Abstract
The scaling down of technologies presents new challenges in reliability, one of
them being electromigration. Electromigration was not cause of concern until interconnects widths shrunk to the micrometer scale. At this point, research was focused into electromigration analysis of interconnects. International conferences
on reliability have recognized electromigration as one of the biggest problems in
reliability.
This thesis focuses on electromigration analysis of signal nets and was carried
out in Design Methodology department at a company in Eindhoven. The purpose
of this thesis work was to setup a flow for electromigration analysis using existing
tools at the company. Comparison of tools and theoretical study of electromigration also forms a big part of this internship.
A summary of theoretical studies on electromigration phenomenon and their
implications on design parameters is investigated in this thesis report. The approach of setting up tools, evaluation strategy and results of the evaluation are
also documented in this report. Lastly a conclusion in a form of an effective design methodology and comparison of tools are presented.
This report also contains challenges encountered while setting up of tools and
motivation for enabling different options for electromigration analysis. Tradeoffs between simulation run time, parasitic extraction, chip area and reliability
concerns are also discussed in this report.
iii
Acknowledgments
Linköping, November 2014
First and foremost I would like to sincerely thank my parents for the eternal
love and support they have given me. Further more I would like to express my
gratitude to my supervisor Jacob Bakker at the company for his valuable comments. His critical reasoning abilities is one of the important things among others which I will try to imbibe in my professional career. Special thanks to Hans
van Walderveen and Andries van der Veen for sharing their knowledge and for
their timely tips and hints.
This internship presented an opportunity to enjoy the orange culture of The
Netherlands. My work experience in the company at Eindhoven has been memorable. The priceless knowledge gained, both academically and professionally,
has definitely given me a competitive edge. The mix of nationality in Eindhoven
made the city warm and friendly.
v
Contents
List of Tables
ix
List of Figures
x
1 Introduction
1.1 Overview of electromigration . . .
1.2 Literature survey . . . . . . . . . .
1.2.1 Research from papers . . . .
1.3 Motivation and problem statement
1.4 Organization summary of thesis . .
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2 Theoretical study of electromigration parameters
2.1 Driving force behind electromigration . . . . . . . . . .
2.1.1 Forces acting on the atom of a conductor . . . . .
2.1.2 Mechanical stresses . . . . . . . . . . . . . . . . .
2.1.3 Stress driven back flow . . . . . . . . . . . . . . .
2.1.4 Effects of different diffusion mechanisms . . . . .
2.1.5 Effects of temperature . . . . . . . . . . . . . . .
2.1.6 Formation of voids and hillocks . . . . . . . . . .
2.1.7 Atomic flux divergence . . . . . . . . . . . . . . .
2.2 Parameters for electromigration analysis . . . . . . . . .
2.2.1 Black’s Law for estimating mean time to failure .
2.2.2 Analysis of current flowing through a conductor
2.2.3 Blech’s length and average recovery factor . . . .
2.3 Summary of parameters for electromigration analysis .
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3 Tools setup for electromigration analysis of circuits
3.1 Overview of method for evaluation and analysis
3.2 Basic methodology for analysis . . . . . . . . . .
3.3 Introduction to the tools . . . . . . . . . . . . . .
3.3.1 Strategy for evaluation of tools . . . . . .
3.3.2 Parasitic extraction details . . . . . . . . .
3.3.3 Description of methodology . . . . . . . .
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viii
Contents
3.4 Description of design under test . . . . . . . . . . . . . . . . . . . .
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
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4 Results
4.1 Results of test cases . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Summary of results . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5 Conclusions and future work
5.1 Conclusions based on thereotical study . . . . . .
5.2 Conclusion on tools setup and analysis of designs
5.2.1 Comparison of the tools . . . . . . . . . .
5.2.2 Analysis of designs . . . . . . . . . . . . .
5.3 Summary of conclusion and future work . . . . .
5.4 Future work . . . . . . . . . . . . . . . . . . . . .
5.4.1 Learning outcomes . . . . . . . . . . . . .
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Acronyms
67
Bibliography
69
List of Tables
1.1 Scaling down of cross sectional area of metals with technology. . .
8
5.1 Comparison of tools . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
ix
List of Figures
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Electron wind force acting on atoms . . . . . . . . . . . . . .
Mechanical stresses . . . . . . . . . . . . . . . . . . . . . . . .
Illustration of atom migration though an interconnect . . . .
Bamboo structure to reduce electromigration . . . . . . . . .
Effects of temperature on electromigration . . . . . . . . . . .
Graph of mean time to failure vs width based on Black’s law
Output waveforms of a typical inverter . . . . . . . . . . . . .
Current waveform in analog circuit . . . . . . . . . . . . . . .
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3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Methodology for analysis . . . . . . . . .
Evaluation strategy . . . . . . . . . . . .
Fracture length . . . . . . . . . . . . . . .
Example of DSPF netlist . . . . . . . . .
ToolA methodology . . . . . . . . . . . .
ToolB analysis methodology . . . . . . .
Illustration of probe points . . . . . . . .
Illustration of characterization of device
Mapping files for ToolB . . . . . . . . . .
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4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
Simple resistor test case . . . . . .
Inverter test case . . . . . . . . .
Polysilicon resistor on layout . .
Inverter test case . . . . . . . . .
LDO test case . . . . . . . . . . .
ToolA direct method waveforms
ToolA indirect method waveforms
LNA1 test bench . . . . . . . . .
GDSII view of layout . . . . . . .
ToolB layout trace view . . . . . .
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5.1 Conclusion on design methodology . . . . . . . . . . . . . . . . . .
5.2 Recovery techniques . . . . . . . . . . . . . . . . . . . . . . . . . .
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1
Introduction
The rapid scaling down of technology to make chips faster and smaller also
presents new and challenging constraints on design of ICs. These issues are related to power consumption, lower noise margins, reliability etc. This thesis lies
within the scope of reliability issues encountered, specifically focusing on electromigration.
This thesis report is a result of an internship undertaken at a company in Eindhoven. Work done during thesis is a part of a bigger project of setting up design
environment at the company. After completion of thesis work, the tools will be
included in design environment which will enable designers to evaluate their
chips for electromigration. Knowledge of electromigration phenomenon was not
available in sufficient details, hence the resulting theoretical studies in physics
behind electromigration are included in this thesis report. The aim was to gather
knowledge in order to understand the phenomenon without conducting an in
depth study of physics. Reliability of chips consist spectrum of analysis. Some of
these are IR drop analysis, substrate noise, chip package analysis and electromigration. As the thesis topic suggests, the purpose of this work is to analyze signal
nets for electromigration and if possible, to formulate a design methodology or
guidelines which will help reduce risks of electromigration in analog and digital
designs of chips.
1.1
Overview of electromigration
As per the simplified technical definition, electromigration is movement of atoms
of conductor in direction of flow of electrons. An analogy which can be presented
is, the movement of sand on riverbed in direction of flow of water. The riverbed
can be compared to a conductor, sand particles as atoms in the conductor and
1
2
1
Introduction
flow of water as the flow of electrons. As one can imagine that overtime, sand
will migrate and accumulate at the mouth of river which will in turn cause depletion of sand at the other end.
The electromigration phenomenon is not new and has been known for over a century. However it did not pose a significant threat since width of conductors was
big enough in the past as compared to present day widths. Electromigration has
been a topic of research mainly in early 70’s. Summary of research papers relevant to this thesis work has been covered in the next section.
From the above introduction it is clear that electromigration depends on current
among other factors. More specifically electromigration is a function of current
density and temperatures. As technology scaled down, the problem of electromigration started raising concerns due to increasing current densities. Hence there
is abundance of literature on reducing electromigration risks, which mostly focus
on power grids, under the assumption that signal interconnects carry negligible
or no currents. However as mentioned earlier, width of interconnects in present
technologies is small enough to have large current densities even for signal interconnects.
The methodology used for assessing electromigration risks have been developed
by EDA vendors. Detailed work has been done on tools for reliable analysis of
power grid electromigration. However signal net electromigration is fairly new
and should be treated differently. This thesis work focuses on setting up a tool
flow for accurate analysis of signal nets electromigration. Motivation for such an
analysis, literature survey and organization of the thesis has been described in
later sections of this chapter.
1.2
Literature survey
Since electromigration related reliability issues were identified long time back,
there is sufficient amount of literature available on internet. Most of the research
focuses on current driven routing algorithms, electromigration methodology and
material physics related to electromigration. Following are list of a few papers
which have been referred to, during the course of thesis work and a short summary of each one of them.
1.2.1
Research from papers
• Embedded Tutorial: Electromigration-Aware Physical Design of Integrated
Circuits [1]
This paper describes the following three points:
– Problems due to electromigration.
– Obtaining realistic current values.
– Physical design methodologies addressing electromigration.
1.2
Literature survey
3
The first point gives a short description of failure mechanisms due to electromigration. Three types of currents are used for electromigration analysis.
Iavg is average current calculated in a net, Irms is root mean square current
and Ipeak is peak current. Accurate calculations of these currents determine
the accuracy of electromigration analysis. In this paper, three methods are
proposed to calculate currents. In order to design reliable interconnects,
different types of routing methods can be used. For electromigration reliability current driven routing methodology will provide optimal results.
Lastly, examples of different tools which can carry out verification of layouts are mentioned in this paper.
• AC and Pulsed-DC Stress Electromigration Failure Mechanisms in Cu Interconnects [2]
The following points are covered in this paper:
– Experimental evaluation of interconnect under pulsed DC and AC current stress.
– Results of experiments and most importantly the conclusion made in
this paper.
An experimental evaluation of lifetime of a copper interconnect are conducted and results are reported in this paper. The stress signal used is an
AC signal and a pulsed DC signal. Results of an interconnect on silicon are
given in this paper which makes the paper important from project point of
view. Graphs depicting lifetimes for a copper interconnect give us an idea
of relation between mean time to failure (MTTF) and current density. The
paper concludes that an interconnect under AC stress performs orders of
magnitudes better than DC stress.
• Electromigration- and Obstacle-Avoiding Routing Tree Construction [3]
Following points are covered in this paper:
– Methodology to use electromigration rules while layouting.
– A routing algorithm to avoid obstacles while laying interconnects in
layout.
Investigation of various electromigration aware methodologies is one of
the goals of thesis work, which makes this paper particularly important.
There is also a proposal for automated routing algorithm for analog design.
The layout done with routing methodology conforms with electromigration
rules.
• Accurate Estimation of Signal Currents for Reliability Analysis Considering
4
1
Introduction
Advanced Waveform -Shape Effects [4]
This paper covers the following points:
– Improving accuracy of the currents calculated in interconnects.
– Calculation of root mean square and average current considering aperiodic waveform.
One of the reasons which makes this paper interesting is second point mentioned above. The accuracy improves by 40% which is substantial. It also
concludes that the design approach could be less conservative from electromigration point of view.
• Current density aware algorithm for net generation in analog high current
application [5]
Following points are covered in this paper:
– Introduction to the problem of electromigration and voltage drop.
– Motivation for analyzing average and RMS current in an interconnect.
– Algorithms for net generation such as Greedy algorithm, exhaustive
algorithm and divide and conquer algorithm.
This paper explains differences between an analog current and a digital
current. This paper presents examples of routing algorithms which can be
used effectively. Computation efficiency is an important factor while generating nets specially if the computational resources are not readily available.
Hence this paper concludes with comparison of various algorithms.
• On potential design impacts of electromigration awareness [6]
This paper covers following points:
– Introduction to electromigration based on the scaling of wire width
and current density.
– Experimental evaluation of mean time to failure versus Fmax and mean
time to failure versus area.
– Results of the experiments and conclusions.
Since the issue of electromigration is gaining importance, more constraints
are put on designs. The impact of these constraints are evaluated in this paper. It gives us an insight on how electromigration rules can affect different
design parameters. The paper concludes that as mean time to failure is decreased the maximum operating frequency can be increased substantially.
1.2
Literature survey
5
Hence specifying mean time to failure for different applications becomes
an important parameter which designers should consider.
• Design of prognostic circuit for electromigration failure of integrated circuit [7]
Following points are covered in this paper:
– Architecture of the circuit.
– Design of various modules like two stage comparator etc.
– Simulation results.
This paper presents a circuit to predict electromigration failure. Most of
the papers mentioned above are focused on the layout parameters or the
physics behind algorithm. Hence this paper gives a different approach towards electromigration. Since we cannot eliminate electromigration, but if
we can predict an impending failure of the circuit then preemptive actions
can be taken accordingly. The circuit proposed in this paper detects a 20%
change in resistance.
• Interconnects exhibiting enhanced electromigration short-length effects by
line width variation [8]
Following points are covered in this paper:
– The mathematical analysis to a new approach.
– Experimental results.
– The behavior of interconnects under stress. This paper elaborates on
the effects of geometry of layout structure on the resistance to electromigration. This paper opens up a possibility of implementing intelligent structures in order to increase the resistance to electromigration.
The findings in this paper are based on variations of width of interconnects and corresponding stress patterns observed in the experiments.
• Electromigration design rules for bidirectional current [9]
Following points are covered in this paper:
– Experimental setup for AC stress.
– Results which show change in resistance under AC and DC stress conditions.
– Summary of results which include comments on the performance of
interconnect under AC and DC stress conditions.
– Design rule recommendations for electromigration.
6
1
Introduction
This paper contains experimental evaluation of an interconnect under bidirectional or AC current stress. The performance of such an interconnect
is noted and proves useful from a design point of view. The paper concludes
with a result that an interconnect under AC stress offers greater electromigration resistance than one under DC current stress. Hence for analog
circuits, with a low DC current, there is a possibility to reduce the width
without compromising on electromigration reliability.
• A New Reliability Evaluation Methodology With Application to Lifetime
Oriented Circuit Design [10]
Following points are covered in this paper:
– Information and mathematical models of different breakdown mechanisms.
– Methodology for proposing an optimized floor plan and layout.
– A detailed analysis of the design methodology. Better mean time to
failures are achieved.
– Conclusion with comparison to other floor plans which produced 15%
better lifetimes.
– Future work is to implement this methodology for design of various
chips. It will be interesting to know whether similar increase in lifetimes is achieved by this design methodology
One more methodology of making the layout electromigration resistant
based on the circuit design is proposed in this paper. This paper also considers several other aging mechanisms like thermal cycling, stress migration
along with electromigration. Mathematical models for various breakdown
mechanisms are given which can be used for a reliable layout. Monte Carlo
simulations is the core processing engine for optimization. With inputs
as VHDL/Verilog models and device technology parameters, an optimized
layout scheme can be proposed.
• Methodology for electromigration critical threshold design rule evaluation
[11]
Following points are covered in this paper:
– Electromigration model for determining the critical physical design
parameters.
– Utilization of nodal analysis for electromigration analysis.
– Results with summary of steps for implementing such a design methodology.
In this methodology a critical threshold for width of the interconnect is calculated based on nodal analysis. This critical design threshold can reduce
1.3
Motivation and problem statement
7
the possibility of a conservative design approach. A design rule for such
an interconnect is proposed in this paper. By considering other models and
combining methodologies from different papers, an optimized methodology can be achieved.
• Electromigration in thin aluminum films on titanium nitride [12]
Following points are covered in this paper:
– Experimental evaluation of short lengths
– The results of the experiment and conclusions.
This paper along with Black’s paper on the empirical relation [13] are one
of the most significant papers on electromigration. In this paper I.Blech
proved experimentally that an interconnect under a particular length is
completely immune to electromigration. This relation has been used extensively for design rule check for electromigration. The result is also used
in this thesis report to analyze circuits for electromigration.
• Comments on electromigration analysis methods [14]
Following are the important points made in this paper:
– electromigration is a complicated process that can be described as a
mass transport process that is dominated by current density but thermal and mechanical stress factors such as temperature gradient or hydrostatic stress gradient also have significantly influence.
– A good overview of various electromigration mechanisms and advances
in this topic are given in this paper.
– Challenges posed by electromigration to the semiconductor industry.
This paper revisits the theoretical relationships between temperature and
mechanical stress. It also comments on Blech length and Black’s equations
used for electromigration modeling. A need for accurate prediction of void
formation and various stresses is emphasized in the conclusion.
Some of the papers gave a better insight into electromigration and others have
information on methodology development. One conclusion which is common to
most of the papers is a need for a design methodology, electromigration models
and deeper understanding of physics behind electromigration. A short summary
gathered from papers and literature on internet of the physics behind electromigration have been given in next chapter.
1.3
Motivation and problem statement
Table 1.1 gives an idea of the growing current density with technology scaling
down.
8
1
Technology node
140 nm
90 nm
65 nm
40 nm
Introduction
Cross sectional area
0.192 um2
0.0288 um2
0.0162 um2
0.0091 um2
Table 1.1: Scaling down of cross sectional area of metals with technology.
The purpose of table 1.1 is to indicate the rise in current density with scaling
down of technology. Hence electromigration analysis becomes an important reliability concern as technology scales down.
At the same time research is focused on electromigration analysis of power grids.
Hence research conducted during this thesis work was mostly focused on signal
net electromigration. The designers tend to be more conservative with their designs which leads to bigger widths of interconnects and larger area on chip. An
accurate electromigration analysis will help reduce size of the chip. Full chip
electromigration is yet another concern. The tools should be able to handle large
layouts and analyze for electromigration without increasing the simulation time
considerably. The results presented to a designer should be easily understandable. The problem statement can be framed as follows:
• Setting up the tool flow required for accurate analysis
• Analysis of layouts for electromigration violations using the flow.
• To investigate theoretically various causes for electromigration.
• To investigate various electromigration aware design methodologies.
From the company’s point of view this internship was mostly about setting up
tools for accurate analysis of circuits for electromigration. From an academic
perspective, researching on various causes of electromigration and investigating
an efficient way to design circuits from electromigration point of view were the
main intentions.
1.4
Organization summary of thesis
This thesis is divided into 4 chapters. The 2nd chapter describes the physics behind electromigration. Physical parameters, which are closely related to parameters under designer’s control are also investigated in this chapter. The 3rd chapter
describes the tools and setting up for analysis. This is a major part of work done
at the company. Results of setting up the tools and analysis methodologies is
described in the 4th chapter. The 5th chapter contains conclusions of this thesis
work with respect to the tools, methodology and work which can be carried out
in the future.
2
Theoretical study of electromigration
parameters
The physics behind electromigration helps us to understand the phenomenon
and its implications. Research is being conducted on material properties of conductors, formation of voids and hillocks and dependency of grain size on electromigration resistance. Using these researches certain conclusions have been
derived in recent times which can be related to the design parameters. This chapter describes the physics behind electromigration and design related parameters
influenced by the physics.
9
10
2.1
2
Theoretical study of electromigration parameters
Driving force behind electromigration
Since electromigration phenomenon was discovered early on, substantial amount
of research is available on physics behind electromigration. This helps to understand the phenomenon better. Using this research, EDA industry has come up
with tools which address the issue of electromigration. Some of the points which
affect electromigration are discussed in this section.
2.1.1
Forces acting on the atom of a conductor
If the river bed analogy is considered, particles of sand on a river bed will experience a force in the direction of flow of water. Similarly, when an electric field
is applied across a conductor, atoms experience a force which is called the direct
force (Fdirect ). This force is a function of applied electric field.
However there is another component of force acting on atoms which is due to
scattering of electrons. This scattering also gives the electrical property of "resistance" to a conductor. This force known as the electron wind force is mainly a
function of current density. The net force acting on atom is
Ftotal = Fdirect + Fwind
(2.1)
Under an external applied electric field, collisions of electrons with each other
causes the electron wind force to increase. Also imperfections in crystal lattice
structure cause scattering which in turn increases the Fwind . Once this force acts
on an activated atom, it causes atoms to move in the direction of electron flow,
which is due to ’momentum transfer’.
Figure 2.1: Electron wind force and direct force acting on an atom. Electron
wind force dominates, forcing the atom to migrate towards anode.
The direction of electrons flow is opposite to conventional current direction. Hence
a build up of atoms can be expected on anode while a void at cathode end. However formation of voids and hillocks are also observed elsewhere on metal interconnect. So in general, atoms diffuse towards anode but due to imperfections
in the conductor, a void or a hillock can be formed along the length of interconnect which is a strong function of imperfections in a conductor. Hence the Ftotal ,
which also represents a driving force, can be given as [15]
Ftotal = Z ∗ e · ρ · j
(2.2)
2.1
Driving force behind electromigration
11
where Z ∗ e is effective charge number, ρ is resistivity and j is current density.
There are various forms of equation (2.2) on the internet and other literatures,
which take into account different factors related to properties of material. The
electron wind force becomes dominant as current density increases. Hence this
force dislodges an atom from its position to cause migration of atoms in direction of the flow of electrons. By controlling current density, the effect of Fwind
can be minimized. The accurate analysis of this force is beyond the scope of this
thesis work. There are other factors which cause the atom to migrate [16], but
Fwind exhibits dependency on design parameters. From the thesis point of view
we are interested in the impact of this force in copper interconnect and whether
this force increases with scaling down of interconnects. Since the activation energy of copper is higher than that of aluminum, makes copper more resistant to
electron wind force. A paper titled ’Dynamic Study of the Physical Processes in
the Intrinsic Line Electromigration of Deep-Submicron Copper and Aluminum
Interconnects’ [16] concludes with the result that copper interconnects are more
dependent on migration due to thermal energy than due to electron wind force.
Also a paper on ’Size effect on the electron wind force for electromigration at the
top metal-dielectric interface in nanoscale interconnects’ [15] concludes that as
technology scales down, the effect of electron wind force only slightly increases.
In ’Dynamics of electromigration induced void in submicron Cu interconnects’
suggests that electron wind force becomes dominant after the formation of the
voids. An intuitive understanding of this dependency is discussed as follows.
In a given cross section of the conductor number of electrons passing through a
cross section at given instant in time is termed as current density. As the cross
sectional area reduces, without scaling down of current, the same number of electrons present in small area can be translated as increase in current density. This
will also increase the collisions with each other, which in turn will cause a momentum transfer. Hence intuitively, the momentum transfer will exert a force
on the atom which is Fwind . This explanation simplifies the understanding of
relation between current density and Fwind . Current topics of research focus on
developing a single model which takes into account all the forces causing electromigration. Such models can be used in design process to accurately determine
the width and maximum current that can be allowed to flow through the conductor.
2.1.2
Mechanical stresses
The basic property of interconnect which gives rise to mechanical stresses is
the ’elasticity’ of an interconnect. Compressive and tensile forces prevail on
the length of an interconnect because of its elasticity. In other words, tensile
stress corresponds to the interconnect being ’pulled’ at a certain location and
compressive stress corresponds to the interconnect being ’pushed’ to a certain
location [17]. The mechanical stresses are also dependent on the atom distribution in an interconnect and are mainly by products of fabrication process. The
thermal treatment of an interconnect during fabrication introduces mechanical
stresses, which encourages formation of voids and hillocks due to electromigration. Again an intuitive understanding of the mechanical stress can be discussed
12
2
Theoretical study of electromigration parameters
as follows.
Consider an interconnect with unequal distribution of atoms. If density of atoms
is high at one end of the interconnect then excess material will cause a compressive stress at the location. On the other hand, a tensile stress is created due to
lack of atoms. Hence there is a stress gradient through the length of an interconnect caused by the fabrication process. Due to electromigration, the stress
gradients increase as atoms begin to migrate. Once mechanical stress threshold
of the interconnect is violated, it might develop cracks. This will lead to a failure
of the interconnect. An important point to note is, factors such as these should
be considered for electromigration aware design. This will not only give an accurate model but will also lead to a less conservative design approach. There is
substantial amount of research available on the modeling of such stresses.
Figure 2.2: Tensile and compressive forces acting on the atoms. Tensile force
cause voids formation while compressive force cause hillocks to form.
2.1.3
Stress driven back flow
As discussed in earlier sections, we have seen different physical parameters which
encourage electromigration. However if the length of an interconnect is short
enough, then mechanical stress work to reduce electromigration. The short length
helps to nullify forces causing electromigration, and hence make an interconnect
’immortal’ atleast theoretically This section focuses on the discussion of effects
of the stress driven back flow.
The direction of mechanical stresses which develop in an interconnect is opposite
to the direction of electron wind force. Hence an atom experiences an equal and
opposite force which stops the migration of atom. In practice, this effect considerably slows down the process of electromigration which results in stronger interconnects. The critical length known as Blech’s length [18] was experimentally
2.1
Driving force behind electromigration
13
proven and this length is used as a constraint while layouting the interconnects.
A long length of line can be broken into shorter Blech’s length by introducing
vias as boundaries. However this leads to undesired increase of resistance of interconnect. Various foundries provide this data which can be used for defining
layout rules. If current density increases, so will the electron wind force. This
length varies for different current densities. Hence in this effect, a current density factor should also be included while calculating the length of an interconnect.
The ’Blech product’ is defined as jl. The model for calculating length for a given
current density is described in [18]. [19] describes the possible utilization of the
Blech effect to have stronger interconnects. [20] has experimental numbers of the
Blech length for copper interconnects.
2.1.4
Effects of different diffusion mechanisms
If atoms find a readily available path to migrate, then formation of such paths
accelerate the rate of electromigration. The interconnects which are made from
Copper or Aluminum are polycrystalline in nature. This means that the lattice
structures of a material group together to form a single grain and a collection of
such grains forms the copper interconnect. Again referring to the river bed analogy, when a river dries out, one can see cracks on the river bed. These cracks can
be compared to boundaries defining the grains of copper. When electromigration
occurs, these cracks or boundaries offer a path for an atom to migrate. This effect
is strongly dependent on the fabrication process specifically pertaining to the
method of deposition of material. Since the atoms migrate or diffuse through the
boundaries of the grains, this mechanism is aptly defined as ’Grain Boundary Diffusion’. The in-depth analysis of this effect has not been done during the course
of thesis work. Apart from grain boundary diffusion there are various diffusion
mechanism at work, but according to literature survey, grain boundary diffusion
has the maximum impact on electromigration.
Figure 2.3: The atom finds a path through boundaries of grains to migrate
in direction of current flow.
As illustrated in figure 2.3, grains are distributed such that their lies an interface
between each grain. This interface provides path for atom migration, path of migration is shown in red.
14
2
Theoretical study of electromigration parameters
Figure 2.4: Grain boundaries running parallel to each other. Also called
bamboo structure, it gives more resistance for an atom to migrate.
If grain structure configuration is made in a way where the grain boundaries run
more or less parallel to each other then an atom does not have an obvious path to
migrate. In such cases, interconnects offers higher resistance to electromigration.
One way of achieving this is to decrease the width of an interconnect or increase
size of grain greater than width of the interconnect.
2.1.5
Effects of temperature
Electromigration is a strong function of temperature. Figure 2.5 shows an interdependence of growth of voids with temperature. We already know that a current
carrying conductor dissipates energy in the form of heat. This phenomenon is
called ’Joule Heating’ which is also an underlying principal for electric heaters.
The heat dissipated in a conductor is a form of energy. When this energy equals
activation energy of an atom, then it is easier to dislodge the atom from its location. Under the influence of electron wind force, mechanical stresses and diffusion mechanisms, an atom readily migrates.
Q ∝ I · R2
(2.3)
A root mean square current can be related to the amount of Joule heating, which
gives us a constraint on root mean square current flow. Usage of root mean square
current is discussed in later chapters. Owing to the fact that rise in temperature
accelerates electromigration, a test can be devised where a conductor is tested for
electromigration failure under high temperature. Results from such a test is extrapolated to temperatures of interest, in order to provide current density limits.
A relation between mean time to failure and temperature has been established
using the Black’s law, which is discussed in later sections.
2.1
Driving force behind electromigration
15
Figure 2.5: Temperature encourages growth of voids which in turn increases
temperature. This figure shows the importance of considering temperature
in electromigration analysis.
2.1.6
Formation of voids and hillocks
From discussions on migration of atoms, two failure mechanisms can be derived.
The first one is due to depletion of material at cathode end leading to formation
of ’voids’. The voids increase resistance of an interconnect, which in turn increase
Joule heating. The second mechanism is formation of ’hillocks’ due to accumulation of atoms towards anode side. The interconnect protrudes due to this effect,
which might short an adjacent interconnect leading to a failure of a chip. The prediction of location of hillocks and voids has been a topic of research and several
models have been proposed. The main factor, however, for formation of voids
and hillocks are material properties of an interconnect.
2.1.7
Atomic flux divergence
If atoms migrate in orderly fashion, i.e a region of depletion corresponds to a
region of accumulation, then migration of material will not cause a huge problem. In other words, the amount of material leaving an area corresponds to same
amount of material entering it, then net amount of atomic flux will be zero. Under such conditions, the movement of material will be of interest only theoretically and will not be a cause of concern in semiconductor industry. However
this is not the case. Based on material properties, the net flux is never zero and
mathematical models have been derived to predict the same. These mathematical models for flux divergence can also be used to predict locations of voids and
hillocks under certain conditions.
16
2
2.2
Theoretical study of electromigration parameters
Parameters for electromigration analysis
The short summaries on physics behind electromigration allow us to find the relation to design parameters. Since we are concerned only with signal nets, we
will exclude nets which source and sink currents from power supplies. Typically
power nets are connected to power supply and ground nets. Hence we can imagine that current flowing through a signal net will be order of magnitudes lower
which allows designers to use minimum width as defined by the DRC rules. It has
been observed that many times violations occur in signal nets because the width
is kept minimum and other times width is kept too big leading to a conservative
design approach. An optimal trade-off between width and reliability calculations
can be achieved if a report of violations are presented to the designer. This is one
more reason of importance of electromigration analysis from a reliability point
of view. In this section the relation of physical parameters and their utilization
to produce an accurate analysis is discussed in details.
2.2.1
Black’s Law for estimating mean time to failure
Electromigration is a slow process. Over time formation of voids and hillocks will
lead to a failure of circuit. In automotive sector, circuits are exposed to high temperatures which increases rate of electromigration. Predictions of time before a
circuit fails based on operating conditions such as the amount of current flowing
through a circuit, the operating time (in hours), temperature and process related
parameters, could be valuable information. The relation between mean time to
failure and various parameters was first established by J.R Black in 1969. This
relation is used extensively by foundries to indicate maximum current values and
also serves as a measure for electromigration. The significance of this equation
demands a bit more of explanation. The work done by J.R Black is indeed very
significant from electromigration reliability point of view. In this thesis work, the
relation for MTTF has been used extensively, and hence an explanation of Black’s
equation is beneficial.
In literature surveys for this thesis work, sufficient amount of papers have been
found which were devoted to explanation of the Black’s relation in details. Let us
first have a look at the relation itself.
Ea
A
· e k·T
N
J
MTTF =
(2.4)
Where:
MT T F: is the predicted mean time to failure
A: is constant depending on cross sectional area
N : is the constant dependent on process, which can be experimentally calculated
Ea : is the activation energy required for atom migration (0.9eV for copper)
2.2
17
Parameters for electromigration analysis
k: is the Boltzmann constant
T : is the temperature.
The paper written by J.R.Black [13] has references to his earlier publications for
the derivation of the empirical relation. A simple model was used to prove the
equation. If rate of migration of atoms increases then interconnect should fail
faster. This was a basic assumption which can be put as follows
MTTF ∝
1
Rm
(2.5)
The rate of migration is proportional to momentum transfer between an activated
ion and electrons which are moving due to conduction. The next assumption
made was the fact that current density is directly proportional to momentum
transfer and density of electrons. Considering that conducting electrons follow
Arrhenius law, results into an equation stated before. Since the derivation deals
with material physics, only a short logical flow has been described. The reader
can look into details by reading the paper [13].
An interesting point to note is [21] significance of the exponent. A value close
to one indicates a higher possibility of failure due to voids while a value close to
two indicates higher possibility of failure due to hillocks formation. Emphasis on
accuracy of calculation of currents is given in the later sections.
Figure 2.6: Mean time to failure versus current of an interconnect
18
2
Theoretical study of electromigration parameters
The constant A is dependent on process and technology along with width. The
expression for constant A from Black’s equation can be evaluated.
− kE·aT
A = Jn · MTTF · e
(2.6)
Ea
Considering temperature to be fixed hence the expression k.T
will evaluate to
a constant and N = 1. Now thickness of interconnects is almost constant for a
given technology. Hence further simplification will give us
I
· MTTF · constant
(2.7)
w
E a
where constant is factored by thickness and k.T
. Keeping width same, if current
I increases then MT T F will decrease and vice versa. This effect will keep value
of constant A unchanged. However if we change width then MT T F will vary for
a fixed current. The purpose of this discussion is to show that value of constant
A is fixed for certain width. However as width varies so will A which leads to the
conclusion that
1
A∝
(2.8)
width
It has been mentioned in numerous literatures that constant A is dependent on
cross section area. The above discussion explains this dependency.
A=
2.2
19
Parameters for electromigration analysis
2.2.2
Analysis of current flowing through a conductor
Analysis of profiles of currents in analog and digital signal nets are necessary to
determine the limits. Consider a typical signal net in a digital circuit. For simplicity consider an inverter with a periodic pulsating signal at the output of an
inverter. A simple voltage and current waveform is shown in figure 2.7.
Figure 2.7: Output current and voltage waveforms of a typical inverter.
Such type of signaling will be encountered throughout a digital circuit. Here
the waveform shown is ideal with an assumption that charging and discharging
path offer same parasitic resistance and capacitance. In practice the charging and
discharging time constants are different but for simplicity of calculations we can
continue with such a waveform. The average current for one period is defined as:
Iavg
1
=
T
ZT
I(t) dt
(2.9)
0
where
I(t) = I0 e−t/RCparasitic
(2.10)
is the discharge current. The charging current can be defined as
I(t) = −I0 e−t/RCparasitic
(2.11)
Both the equations are standard equations for charging and discharging of a capacitor through a resistor. Here the resistance and capacitance is assumed to be
the parasitic resistance and capacitance.
To find the average of this current, the integration can be done in parts over the
entire period of the square wave pulse as follows:
T
Iavg
1
=
T
Z2
I0 e
0
−t/RCparasitic
1
+
T
ZT
T
2
T
−I0 e(−t− 2 /RCparasitic )
(2.12)
20
2
Theoretical study of electromigration parameters
The integration of such a current waveform is obviously evaluated to zero since
area under current curve for positive and negative half cycle are opposite in values. This also means that if the average current is zero, then the effect of electromigration may become less due to migration of atoms in both the direction,
hence ’healing’ the interconnect. We have considered that a voltage pulse has
50% duty cycle. If the duty cycle was varied with close to 100% duty cycle then
the maximum value that the average current will reach is
Imaxavg =
Vconductor
Rparasitic
(2.13)
Since interconnects are desired to be more ohmic, increasing resistance of an interconnect will also help in reducing average current. This analysis shows that
correct inclusion of parasitic resistors and capacitors are crucial to accurate average current calculation.
The reason to calculate the root mean square current is to include the Joule heating effect. The analysis for average current can also be carried out for root mean
square current. The root mean square current can be defined as follows:
v
u
u
u
u
t ZT
1
IRMS =
I(t)2 dt
(2.14)
T
0
where I(t) is defined by equation (2.5). The root mean square of the current is
evaluated as follows:
v
u
!
u
u
t
− RC T
2
parasitic
I0 RCparasitic e
−1
−
(2.15)
T
The root mean square current also is a strong function of parasitic resistors and
capacitors. Also if the period is reduced, i.e frequency is increased, so does RMS
current which is also intuitively correct. However this is true only till a certain
frequency, because as frequency increases duration of positive and negative half
cycle is not enough for atoms to get dislodged and migrate. Rate of electromigration saturates after a certain frequency. The value of this frequency ranges from
two to ten MHz in different papers.
The reason for this analysis is to emphasize on strong dependency of parasitic
extraction to calculate accurate currents. However detailed extraction of parasitic resistances and capacitances can increase simulation time. Hence a designer
must take into account the trade-off between accuracy and simulation time.
The same analysis can be carried out for analog signal net analysis. A bias current flows through an analog circuit. This bias current is DC in nature with signal
fluctuations around it.
2.2
Parameters for electromigration analysis
21
Figure 2.8: Current waveform in analog circuit. Unlike in a typical digital circuit there could be numerous waveforms profiles of current in analog
circuit.
As shown in figure 2.8 the average current calculation done by the equation (2.5)
will give a current which is a little higher or lower than the bias current. This
obviously depends on the waveform of the current in an analog circuit. There
is no typical waveform of a current in analog circuit. Hence discussion of analog current like the digital current analysis cannot be done since we will have to
consider a large number of analog current waveforms. However the average current will be centered around the bias current and the root mean square of such a
fluctuating current will give us the Joule heating effect.
2.2.3
Blech’s length and average recovery factor
Joule heating has been adequately emphasized and can be factored in the analysis
by considering the root mean square current in the interconnect. In this section
Blech’s length and average recovery factor are discussed in details.
Blech’s Length: An experiment conducted by I A Blech [18] to study the effects
of length of the interconnect on electromigration resistance resulted in a very
interesting conclusion. According to this experiment, it was observed that the
tensile and compressive forces discussed before affect the rate of electromigration. These forces also induce mechanical stress on an interconnect. However
within a certain length, the mechanical stress actually oppose the other driving
forces for electromigration in the opposite direction. Any interconnect smaller
than the critical length will have infinite resistance to electromigration, making
the interconnect theoretically ’immortal’. However in practice the current limit
increases dramatically but not infinitely.
The Blech’s product can be given by
(jl)c =
4·σ ·Ω
ρ · Z∗ e
(2.16)
22
2
Theoretical study of electromigration parameters
All variables are related to process and materials and we will not go into details.
However significance of above equation is we can calculate a critical length for
a given technology and this length is also proportional to current density. From
this thesis point of view this means that every metal layer will have a different
critical length or current density for a fixed length will be different for each layer.
The routing algorithms discussed before could also make use of Blech’s length
parameter to calculate an optimum length. In [22] this critical product was
determined for 45nm and 65nm technology which gives us a good insight on
significance of Blech’s product.
In this thesis, we will be using Blech’s length in electromigration analysis. A
very intuitive approach would be that as length reduces, maximum current limit
should increase. The model for calculation of maximum current as a function of
width and length of an interconnect is given by the foundry and conforms with
our intuitive approach. These details are given in a technology file which is used
for comparison during post processing of results.
Average recovery factor: For a bi-directional current, AC or DC, one can imag-
ine that current flows in opposite direction depending on phase of current. So
while atoms move in one direction in the first phase, they will move in opposite
direction in the second phase. This could give a property of ’self healing’ to an interconnect, which also could be used in our analysis. Termed as average recovery
factor, it depends heavily on the nature of current flowing through a conductor.
However if frequency of bi-directional current is too high then average recovery
factor cannot be used since time duration for atoms to migrate back and forth
will be very less. Also this factor is only applicable to average current calculation.
If average recovery factor is specified which should be less than one then average
current can be calculated as follows:
Iavg = max(|pos|, |neg|) − avgrecoveryfactor · min(|pos|, |neg|)
(2.17)
where pos and neg is the current flowing in positive and negative cycle respectively. Finding the value of this factor should be addressed in order to give a
more accurate analysis. As mentioned before the average recovery factor is not
only dependent on current profile but also on material properties. If the current
profile (with respect to the duty cycle, amplitude, frequency) remains constant
throughout the lifetime of the interconnect then calculating average recovery factor makes sense. With varying current profiles over time, the average recovery
factor will change for each profile. Hence a worse case average recovery factor
could be considered in the analysis. To find the worse case average recovery factor,
the circuit should be stressed out for every possible variation of current profile
in the interconnect. This is a huge computational effort. Also if the frequencies
are greater than 1 MHz then this calculation will not make much sense. Hence
during the course of the thesis work average recovery factor is not considered.
2.3
Summary of parameters for electromigration analysis
2.3
23
Summary of parameters for electromigration
analysis
In this chapter we have seen various physical parameters affecting electromigration. These physical parameters can be influenced by some design related parameters which were investigated. Different current routing algorithms proposed
make use of the design related parameters for making a reliable layout. Although
technology itself affects electromigration behavior to a great extent, but investigation of process related parameters is beyond the scope of thesis work. The
Black’s law for mean time to failure and Blech’s length have been derived by using physics behind electromigration. We have seen various forces which cause
electromigration and models for such forces could be included in design process
to make analysis more accurate. In summary we have following design related
parameters and their effects:
• Design related parameters:
– Current Density: Influences electron wind force
– Length of an interconnect: Influences the mechanical stresses and Blech
length is useful for increasing resistance to electromigration.
– Current profile: Average current influences the current density while
root mean square current take Joule heating into account.
• Process related parameters: Diffusion mechanisms, atomic flux divergence
are parameters related to technology itself. The models of such parameters
could be used in design phase but this is beyond the scope of thesis work.
These parameters form a basis of analyzing circuits for electromigration.
3
Tools setup for electromigration
analysis of circuits
The Design Methodology group at the company deals with setting up design
methodologies from a designer’s point of view. Designers assume that the tools
have been evaluated thoroughly and their results are valid. EDA vendors are constantly optimizing their tools, troubleshooting reported bugs and are in contact
with the customer. Since a new visualization tool was introduced by the company,
an evaluation was necessary from their end. A part of this thesis work was also
spent in evaluating the tools from a designer’s perspective. To verify functionality of the tools, test cases are needed where user knows results before hand.
By comparing results of the tools, user can evaluate the behavior. During this
thesis work, we started evaluation from a very simple test case like a network of
resistances and slowly increased the complexity of test cases. If problems were
encountered at any step, they were solved in co-operation with EDA vendor contact persons. Increasing complexity of designs translates into higher amount of
nodes, active devices and size of a layout. Since designing complex analog circuits takes considerable amount of time, we decided to use existing designs with
knowledge of design and behavior. Hence throughout this project, involvement
of a designer and EDA vendor’s AE was very important. If all functionalities of
the tools are evaluated on less complex designs then as a final evaluation, three
designs i.e LNA1, LNA2 and Mixer will be used. This serves two purpose, first is
evaluation of the tools and second is evaluation of designs for electromigration.
The evaluation strategy is elaborated in later sections of this chapter. This chapter describes the methodology of analysis, a short description of the tools used
for analysis and setting up the tools
25
26
3.1
3
Tools setup for electromigration analysis of circuits
Overview of method for evaluation and analysis
In second chapter, different design parameters affecting electromigration have
been described. The width, length and current flowing through an interconnect
can be modified in order to reduce electromigration risks. The performance specifications like gain, phase margin, signal to noise ratios etc. dictate the amount
of current flowing through an interconnect. The risks for electromigration must
be reduced without compromising on the performance specifications. Hence an
option to reduce current in an interconnect will be avoided by designers. We are
left with length and width of the interconnect. Both parameters will also affect
area on chip, and hence an optimum trade off between area and design parameters must be achieved. One of the focus of this thesis work is achieving the trade
off. Width and length of an interconnect could be higher or lesser than required
electromigration safety margins, which is calculated on the amount of current
flowing through an interconnect. An accurate calculation of width and length depends on accurate calculations of current flowing through an interconnect under
operating conditions set by the designer. In turn accuracy of current calculation
will affect the accuracy of electromigration analysis. In order to increase the accuracy of calculation of currents, parasitic extraction of the layout is crucial since
simulation of such a layout will determine realistic currents and hence safety margin can be calculated for a particular interconnect. Another factor which affects
currents is temperature, which has been described in second chapter. The operating temperature and period (MTTF) must be known before hand to the designer.
Negative or positive temperature coefficients will help in increasing accuracy of
calculation of current, and the MTTF will help in calculating the safety margins.
A parasitic extraction of layout must contain sufficient parasitic information. If
parasitics of very less values are extracted (femtofarads and miliohms) then accuracy of currents and simulation time will increase. Increase in simulation time
is undesirable. In addition such small values will not substantially affect current
flowing in an interconnect. On the contrary, ignoring smaller value parasitics
will hamper the accuracy of the currents. This leads to one more trade off which
is parasitic extraction versus simulation time.
So far accuracy of current calculation has been discussed, details of which are
included in later sections. Based on widths of an interconnect, safety margins
can be calculated, i.e the maximum current that can flow through an interconnect for a given width, length and number of operating hours. With this safety
margin, designers can either reduce or increase physical dimensions of an interconnect. Hence we will need a model to calculate the safety margin. This model is
generally given by respective foundry. Comparison of calculated current and safe
currents gives us a measure of electromigration risks. Hence if maximum current
and operating hours are known, the designer can also calculate minimum width
and length of an interconnect in order to make the design resistant to electromigration. This can be achieved through a design methodology aimed at reducing
the electromigration risks. One such methodology is discussed in later sections.
3.2
Basic methodology for analysis
27
Different tools offer various methodologies for electromigration analysis. Some
methodologies must be studied in order to understand effects of them on accuracy of analysis. A study of methodologies of two tools is presented in later sections. Based on the analysis one can also tell whether a design approach was
conservative or aggressive. With a conservative design approach, we get room to
save chip area. If the design approach is aggressive then steps must be taken to
correct the design before tape out. Analysis made by the tools should use design
parameters like length, width, MTTF and current flowing through an interconnect. The MTTF must be given to the tools while length, width and current must
be extracted by the tools. Accuracy of these parameters will determine the accuracy of analysis as stated before. Hence both tools used in this thesis work must
be verified for functionality and accuracy.
3.2
Basic methodology for analysis
The most common method is to analyze currents in every signal net for different
analysis like AC, DC and transient. Currents are superimposed on layout to calculate current densities based on geometry of structure. These calculated current
densities are compared to limits provided by the foundry to determine electromigration risks. An important factor to note here is the dependency on accuracy of
calculation of currents in nets and computational effort required.
Figure 3.1: Basic methodology for analysis.
An analysis of electromigration is fairly standardized among all tools. As shown
in figure 3.1, the analysis starts with parasitic extraction of layout. There are several options available for parasitic extraction, which can be changed depending
28
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Tools setup for electromigration analysis of circuits
on the type of analysis. An optimum extraction options considering simulation
time and accuracy for currents must be chosen.
Second step is to determine the current flowing in each branch. Types of currents which will be extracted during simulation are Iavg and Irms . Here designers
should also choose a suitable test bench which will simulate realistic loads and
hence produce realistic currents in each branch. Power grids should be excluded
from the analysis which will also reduce simulation time.
In the last step, currents extracted should be compared to limiting values given
by the foundry. Limiting values should be present in technology files. Any violations should be reported graphically and in textual form.
Description of the basic methodology of analysis indicates the comparison points
for the tools used in this project. This thesis work does not include benchmarking
the tools but a brief summary as to whether the tools can be used in a design flow.
Following points can be used for comparison:
• Accuracy and run time of analysis.
• Ease of tools setup for analysis. Designers should be able to run the analysis
for different circuits without the need of too many modifications to different
settings. In short a push button approach will be preferred.
• Visualization of violations should be clear and easily understandable to a
designer. This becomes more important as the size of layout increases.
• The designer should be able to analyze part of simulation results in order
to reduce post processing time.
• The tools should be able to exclude power nets and only simulate signal
nets.
• The tools should be able to handle big designs. A full chip simulation is
preferred.
As one can see these points can only justify behavior of tools and not benchmark
them. Benchmarking a tool is a time consuming process which also might include
validation on silicon.
3.3
Introduction to the tools
Reliability concerns have been on the rise since growth of semiconductor industry. Hence the market for providing tools for accurate reliability analysis is also
developing at a fast pace. There are a few vendors in the EDA market which
provide tools for electromigration analysis. In this project the company decided
to use a new visualization tool which will be henceforth referred as ’ToolA’. One
more tool, henceforth referred as ’ToolB’ is also used in the company’s design
flow. Both tools have their own limitations. Bugs were found with both tools and
they were reported to respective vendors. Due to the non-disclosure agreement
in effect, names of the vendors and bugs encountered cannot be mentioned. How-
3.3
Introduction to the tools
29
ever for the sake of understanding a short summary is provided in this thesis
report.
ToolA: ToolA has its own parasitic extraction engine, simulator and electromigration post processing engine. The electromigration analysis engine provides
two ways of analysis. First one is direct method where the circuit along with
parasitics are simulated in a brute-force way. This method translates to heavy
computational effort. Second option is to analyze a circuit and its parasitics separately. This method inherently increases inaccuracy but also reduces computational effort. If inaccuracy is within limits then this method can be extensively
used and could possibly do a full chip simulation. The results of evaluation are
discussed in results section. The inputs to the electromigration post-processing
tool is as follows:
• DSPF netlist.
• Technology file with electromigration limits.
• Test bench.
• Path to simulation results.
Once all files are given to ToolA, the post-processing utility generates a text report
and a graphical representation on the layout. Graphical representation contains
color coding for different violation limits.
ToolB: The purpose of ToolB is to provide various reliability analysis under one
roof. ToolB relies on third party extraction and simulation since it does not have
a simulator of its own. It provides more options for analysis, but at the same time,
there are limits on the resolution of simulation output file. With these limits the
simulation runtime of simulator increases. The analysis method is to stream in
the DSPF netlist and the GDSII file. Then co-ordinates of devices, nodes and
subnodes are extracted which are superimposed on the GDSII file. With this
information, each device can be modeled as a current source (an electrical characterization of devices) by extracting current from simulator output file. To show
the results, currents and the geometry of a shape are used to calculate the current
density. A geometry in a layout can be analyzed in different ways. For example, a big shape can be broken into smaller shape and current densities can be
reported for each shape. This gives a more detailed analysis of current densities.
This current density is compared to electromigration limits and violations are reported. Violations are reported graphically and textually. The inputs to ToolB
are as follows:
• DSPF netlist
• Technology file containing electromigration limits.
• Simulation results file.
• GDSII file.
• Seven miscellaneous files related to settings and options for the analysis.
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Tools setup for electromigration analysis of circuits
It can be seen that the number of files one needs to maintain is greater than ToolA.
Additional steps need to be taken, like writing a script, to maintain integrity of
the input files.
3.3
Introduction to the tools
3.3.1
31
Strategy for evaluation of tools
Evaluation of tools is done from a designer’s point of view. However during evaluation one must also know different options and functionality provided by the
tools. Hence there is a learning curve involved for the person evaluating the tool.
During this learning curve one should reason the advantages or disadvantages of
different options present in tools, again from a designer’s perspective. This is one
of the evaluation points along with much important points like verification of
functionality of tools. As the complexity of input design increases, various other
functionality of tools are evaluated. Hence test cases must be chosen such that
all aspects related to the working of tools are covered. A short introduction of
strategy used for testing is given at the beginning of this chapter. In this section
detailed information on the method used for evaluation are documented.
Figure 3.2: Methodology used for evaluation of the tools.
A simple design could be as simple as a network of two resistors in series and
in parallel with another two resistors in series and a respective layout. Such a
design is meant to perform a ’sanity check’. Evaluation of such a simple design
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Tools setup for electromigration analysis of circuits
should not be a problem for both the tools. If some fundamental points have been
overlooked during design of the tools, then such points will surface during a very
basic evaluation of tools. ToolA happened to face a problem at a very early stage
with respect to net name identification. This was a very primitive bug which was
reported to the ToolA support. This circuit also helped in getting familiar with
working of the tools and various functionality both tools have to offer.
The complexity of the design was increased by designing a single inverter circuit
and a corresponding layout. This type of circuit includes an active device with
less number of interconnects. A test bench is designed to stress the inverter circuit. Since it is a simple inverter we know the results expected from both tools.
ToolB showed some errors but they were fixed after which both tools gave same
result.
The complexity was increased to two inverters in series. This type of circuit
helped us compare between inclusion of complex components in a layout. An
interconnect between two inverters were connected by poly resistors, which were
not like regular resistors. With this test case we also saw which tool handles
the inclusion of complex components in a correct way. ToolB again had some
problems while tracing through a design. However problems were resolved and
results when compared appeared slightly different. This was an indication that
as complexity increases results of both tools might deviate from each other. In
order to find which one shows a greater accuracy, hand calculations of current
density limits should be performed on the test cases.
Another test case is LDO design. A fairly big layout but not big enough to validate whether a full chip simulation is possible. However this type of circuit gives
a clear indication whether both tools will be able to handle a full chip simulation.
While ToolB could not trace layout correctly, analysis was still performed to evaluate amount of time taken to analyze. Here results were obviously wrong since
layout was not traced correctly.
Final test cases are LNA1, LNA2 and Mixer. The results of these test cases are
covered in subsequent sections.
3.3.2
Parasitic extraction details
As emphasized earlier, parasitic extraction is a very important step in electromigration analysis. Accurate calculation of currents heavily depends on parasitic
extraction. As mentioned before, electrical characterization of devices is done by
invoking a transient simulation of circuit. If this simulation contains a netlist
with parasitics then a more accurate current will be calculated at every node.
However there is a limit to consider parasitics and this limit is defined by the
simulation time. Hence a trade-off between parasitic extraction and simulation
time must be considered by designers. Considerable amount of time was invested
in choosing right options for parasitic extraction. An analysis of the options are
described in this section.
Extraction Parameters:
• Transistor DSPF: It is already clear that we will be using DSPF in both tools.
A transistor level DSPF includes transistors with co-ordinate information.
3.3
Introduction to the tools
33
This option is favorable for analog simulations. A DSPF format is described
in details in later section.
• Extract Diffusion resistance: This option is not needed because we are mainly
interested in electromigration of interconnects and not in diffusion regions.
• Extraction type: We will use RC extraction since as demonstrated before
parasitic resistance and capacitances both play an important role.
• Capacitance coupling: Coupled, since we want detailed capacitances between nets as well.
• Fracture length: An interconnect can be broken into multiple parts with
resistance associated to each part.
Figure 3.3: Illustration of interconnect broken down by fracture length variable.
In figure 3.3 L1, L2, L3 indicate the fracture lengths and R1, R2, R3 indicate respective extracted resistances depending on length. Notice the placement of capacitors. With a finite fracture length, a capacitance is modeled
for each piece of interconnect. This increases amount of subnodes and also
simulation time due to RC nonlinearity. Since values of parasitic capacitances are very small (in order of picofarads), its affect on value of current
is negligible. Also a fracture length which is less than Blech’s length would
mean that interconnect will be analyzed with higher current limits, which
will again give a wrong indication of violations. Hence a fracture length of
’infinite’ will be used. This will model an entire length of interconnect by
one parasitic resistor and parasitic capacitance at both ends of an interconnect.
• Net selection: All nets need to be extracted, hence full chip extraction is
chosen.
• Minimum R and C extraction: Minimum resistance (R) and capacitance
(C) required for extraction is dependent on a designer. Smaller resistance
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Tools setup for electromigration analysis of circuits
and capacitance extraction will give better accuracy but increase simulation time. Here an important point to note is the accuracy with which a
designer wishes to simulate the circuit with or without electromigration
analysis. Hence minimum R and C is the same as given by a designer.
• Exclude self capacitance: This option does not extract capacitance on the
same net. Current flowing through an interconnect will remain unaffected
even if this option is disabled. Hence we will not enable this option.
• Exclude floating nets: There is no current flowing through floating nets.
Hence floating nets will be excluded from the analysis.
• Dangling resistors: This option reduces the number of parasitic resistances
which are not connected to anything on a layout, hence no current will flow.
This option is enabled.
• Merge parallel resistors: This option merges resistances in parallel which
help in reducing the sub nodes. Hence this option is enabled.
• Parasitic extraction width: We want the silicon width to be reflected in extracted view and parasitic resistors and capacitors associated with it.
• Miscellaneous: With electromigration analysis option enabled, some parameters are set by default which are mostly related to information presented in the extracted netlist. We have also enabled ’add explicit vias’ option which will ensure connectivity between active and poly and rest of the
layout. We would also like to have co-ordinate information of all parasitic
elements which will be extracted, like parasitic diodes etc.
With all options set, we proceed towards running the extraction engine and getting an extracted netlist. As mentioned before we will be using a xDSPF format.
The details of xDSPF format are as follows
A transistor DSPF is used in this flow. A DSPF file is an ASCII
flat parasitic extracted netlist of a circuit with co-ordinates of all active, passive
and parasitic devices at every node. We also want detailed information about
transistors like for example location of source, gate, drain and body pins, connection of these pins to various nets etc. This detailed information will help us
analyze analog circuits. The other format is cell level DSPF which is a netlist
optimized for timing analysis in digital circuit. Since our test cases are analog
designs, we will continue with extraction of xDSPF. xDSPF and DSPF are used
interchangeably throughout this thesis report. The basic syntax of a DSPF netlist
is as follows
DSPF extraction:
• *|NET: Indicates name of net in a circuit.
• *|P: Indicates pins or primary ports connected to a net.
• *|I: Indicates instances connected to a specific net.
• *|S: Indicates sub nodes of a specific net.
3.3
Introduction to the tools
35
There is an instance section at the end of the DSPF file which provides details
of models used for instances in DSPF netlist. The inclusion of co-ordinates of
different devices is taken care in the miscellaneous settings of parasitic extraction
tab. There are certain resistors which are included in the netlist, like ”Rmwires”.
These resistors are required to put an exclusive label to ports of different devices
which are connected to the same net and if a parasitic resistor does not exist. With
a default value of 0.001 ohms, these resistors are used to maintain the integrity
of the DSPF netlist. During simulations these resistances are not considered for
analysis.
An example of a DSPF netlist is shown below:
Figure 3.4: A snapshot of DSPF netlist from one of the extracted netlist.
In figure 3.4 shown above there is a substantial amount of information given in
the netlist. Let us use this example to understand the syntax better. The value
after ∗|N ET ibias i.e 2.86767e−15 gives total capacitance between net and ground.
On a layout, every track or drains, source and gate of a transistor can be viewed as
shapes. To define a shape the co-ordinates of end points of a shape must be given.
The $llx, $lly, $urx, $ury values specify the ’lower left x’ co-ordinate, ’lower
left y’ co-ordinate, ’upper right x’ co-ordinate and ’upper right y’ co-ordinate
receptively. Hence we can see that from the ASCII information, one can build
a layout view again. Thus a DSPF format is just an ASCII representation of an
extracted view as mentioned earlier. The advantages of xDSPF format are as
follows:
• Universal format for parasitic extraction. Extracted netlist from one tool
can be used by other tools for analysis.
• ASCII readable file, hence in certain cases this file is useful for debugging.
This netlist will later be simulated by a simulator for finding currents in each and
every net. For the simulator to understand this netlist, syntax in DSPF file should
be simulator friendly. Considerable amount of time was put in this task to make
the netlist useful for simulation. A methodology for verifying the xDSPF netlist
contents was necessary before proceeding with the setup. As we can see the DSPF
file contains RC parasitic. If we simulate the DSPF and a valid extracted view,
then both simulations should give same results. If they do not give same results
then DSPF file needs corrections. During thesis work we found that simulation
results were not consistent.
To find out source of the problem, following steps were followed:
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Tools setup for electromigration analysis of circuits
• Extracted netlist with both parasitic resistors and capacitors. The simulation results showed that waveforms has closed resemblance in terms of
functionality. However the DSPF simulation waveforms also indicated a
sharp rise in voltage, which meant that capacitive or resistive effect were
not being correctly simulated. Hence either intended resistors, capacitors
or devices were not being extracted according to requirements of the simulator or problem could be with parasitic extraction. Next step would be to
eliminate one of the two options.
• Extracted netlist without parasitic and compare simulation results. Simulation results were identical indicating that intended devices are correctly
extracted.
• Extracted netlist with parasitic resistors only. Simulation results were identical and hence the parasitic resistor extraction was not a problem.
• Extracted netlist with parasitic capacitor only. Simulation results as expected were not identical. Upon close inspection of random parasitic capacitor extraction, it was seen that the capacitor model parameters were
not in accordance with simulator requirements. After fixing all problems,
simulation results were identical to the extracted view.
• It made sense to verify all components in 65nm technology library for which
electromigration analysis was to be setup. This will also prevent any surprises in future. Hence all components were instantiated on a dummy layout and extraction was done. There were other components with which
problems were found. Tickets were raised for the same.
The problem noted was wrong syntaxes extracted by the DSPF extraction engine
which simulator could not understand, and hence value of capacitors was calculated as zero. After identifying the problem a local compilation of technology file
was used to proceed with the project.
Test bench requirements
The test bench does not have any special requirements. The only condition to
be put on a test bench is, it should reflect realistic currents and should be simulated at worst case corner. Also simulation should be done at the temperature of
interest.
3.3.3
Description of methodology
In the introduction of this chapter, explanation of a very generic flow to analyze
circuits for electromigration is described. Both tools implement this methodology to analyze circuits for electromigration in their own way. The aim of these
methodologies is to achieve an analysis at minimal computational effort. This
section contains description of methodologies.
3.3
Introduction to the tools
37
Methodology of ToolA
The methodology for ToolA is illustrated in figure 3.5. As mentioned before the
simulator and parasitic extraction engine are used for electromigration analysis.
These engines are also necessary to make ToolB flow work.
Figure 3.5: Methodology for analysis used by ToolA
After extraction is done, the DSPF file is used for simulations. Hence the accuracy
of electromigration analysis is dominated by parasitic extraction engine and simulator. Since electromigration analysis engine is a part of the tool flow, databases
which are created, for example simulation results, DSPF files etc. are handled
internally. This is one of the advantages of ToolA.
A test bench needs to be created for electromigration analysis as per the requirements mentioned above. Two ways can be used to do simulations. Before simulation starts, a form can be filled up which has several options for electromigration
analysis. The options are as follows:
• Field: Net names and type of analysis
This field allows users to give specific nets for electromigration analysis.
This is useful in reducing the simulation time provided the designer has
knowledge about all currents flowing through other nets are not a cause for
concern. Selection of all nets in a design is also possible. Type of analysis
field allows a designer to choose root mean square, average or peak analysis
for a current.
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Tools setup for electromigration analysis of circuits
• Field: Time window
This field allows a user to analyze currents in nets for a specific simulation
period only. If simulation time is 10ns then a designer can choose to analyze
only a part of simulation for example from 3ns to 7ns. This option will
reduce post processing time for bigger circuits.
• Field: Technology file path and name.
This field allows users to specify a technology file which contains all electromigration limits. A technology file is provided by the foundry which
contains a vast amount of information about the technology used. Information like resistance of every metal used in the technology, maximum width
of vias, information relevant to parasitic extraction like optical correction,
silicon width etc are present in this file. The format in which a foundry
gives the file may not be accepted by different tools. Hence technology file
from a foundry needs to be adapted. The naming conventions of metal layers, inclusion of electromigration data were some of the problems which
were fixed by running scripts. For ToolA a derivative of the technology file
which contained only electromigration limits was needed. This meant that
two files need to be maintained and delivered with PDK. A preference to
run electromigration analysis on a single file was communicated to ToolA
support. Following information is given in a technology file:
– Average, root mean square and peak current limits for all metals and
vias.
– Length dependent average, root mean square and peak current limits.
– Width dependent average, root mean square and peak current limits.
The models (equations) of electromigration behavior of metals and vias
with length and width as variables are used to calculate maximum current
allowed in an interconnect and vias. Current calculated by the simulator
are compared to these limits. Technology file is specified for certain operating hours. If a circuit needs to be evaluated for less number of hours then
limits need to be modified proportionally. For example, if the technology
file has limits specified for 50,000 working hours and a circuit needs to be
evaluated for 25,000 hours then current limits must be increased by twice
the amount for 25,000 hours.
• Field: Type of simulation method
This field allows users to either use one of the two methodologies(direct or
indirect) offered by this tool.
– Direct method:
In this method a circuit along with its parasitics are analyzed all at
once. Although this method increases accuracy but also increases the
simulation time.
– Indirect method:
In this method, parasitic resistors and capacitors are separated from
3.3
Introduction to the tools
39
the intended devices in a circuit. The parasitic resistors and capacitors
network can be solved by applying KCL and KVL, and this network
is also more linear than intended devices which contain non linear
components like transistors, diodes, poly resistors etc. The intended
devices are also characterized and a netlist in an encrypted format is
produced for these devices. When a designer changes the layout, effectively only parasitic values should change. This change is accounted
for and since we already have an intended circuit profile, all we have
to do is simulate parasitic resistors and capacitors network again. Results of a parasitic simulation is superimposed on the intended circuit,
which calculates currents in all interconnects. Although this method
speeds up simulation but since separation of all non linear devices is
not mathematically equivalent to the original circuit some amount of
inaccuracy will be introduced in the analysis. Hence a comparison
with direct method will help understand how much of inaccuracy is
introduced and whether it is within acceptable limits. Results of such
a test is detailed in later sections.
• Field: DSPF checker
This field checks the DSPF file for any unusual devices whose models have
not been defined. A text report with all models is generated and included
in a configuration file.
During simulation, the temperature must be specified for using right models of
instances which will lead to accurate calculation of current. In our case a temperature of 110 degrees was specified in all simulations. All values from above
fields are collected in a configuration file which is used during simulations. Once
simulation is completed, an encrypted file containing electromigration results
is dumped in a predefined location. This file can be used standalone with the
visualization utility.
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Tools setup for electromigration analysis of circuits
Methodology of ToolB
The difference between electromigration analysis of ToolA and ToolB is the handling of layout. ToolB is essentially a third party tool. Hence it needs to read a
layout from variety of EDA tools. To make this step generic, ToolB uses the GDSII
format to stream in a layout.
Figure 3.6: The methodology of analysis used by ToolB
The methodology of ToolB has dependence on ToolA parasitic extraction and simulator. ToolB uses the DSPF file to extract co-ordinates of devices and nets, takes
information from simulation output file and replaces all active devices by their
respective currents sources from simulation output file. Hence to average current
over entire simulation time window, ToolB will have to put some limits to the resolution in order to increase level of accuracy. There are three steps involved in
ToolB methodology which are explained as follows:
3.3
Introduction to the tools
41
• Creation of probes file: ToolB reads the DSPF netlist and identifies all active devices. The terminals of active devices are probed for currents. A file
containing all these probes are generated in this step. Based on the simulator, syntax of probes statement in probes file may change. Hence some
manual modifications may be required depending on version and requirements of the simulator. As we can see in figure 3.7, Rp and Cp are parasitic
resistances and capacitances. Probe point two which is at gate is expected
to have minimal current since ideally no current can pass through a gate of
a transistor due to the oxide layer.
Figure 3.7: Probe points used for characterization.
• Simulation and characterization of devices: The probe file created in the
first step is included while doing simulations. The simulator is ToolA simulator and correct test bench is needed to include a probe file. The output of
simulator is current waveforms over an entire duration of simulation with
resolution in order of picoseconds. These current profile must be taken to
characterize a device over the entire time duration. Hence a device will be
replaced by a current source with the current profile which includes time
and position co-ordinate information.
Figure 3.8: Using probe points in figure 3.7 a device is characterized.
As shown in figure 3.8 NMOS is modeled as a current source, where the
current is a function of voltage and time. Hence an entire network can be
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Tools setup for electromigration analysis of circuits
solved by using Kirchoff’s current and voltage laws.
• Transient analysis and displaying results on the GUI: The last step involves
doing a transient analysis using information from the second step and displaying results accordingly on the GDSII file. In this step, characterized
devices along with their position information are analyzed for root mean
square, average and peak current for any possible violations. An important
part in this step is verifying whether the GDSII file has been correctly traced
by a tool. For example if a tool is not able to trace a particular interconnect
then during transient analysis no current will flow since it is considered
as open. This will give errors in results. While many similar errors were
encountered and solved in smaller test cases, it becomes difficult to identify such missing interconnects as size of layout increases. If tracing goes
correctly then violations are displayed on the GDSII file in a colour coding.
Generally all layouting tools are capable of making a standardized GDSII file.
However reading the GDSII file is not as easy as it looks. A mapping of customer
specific devices and layers must be done for ToolB to understand circuit and to
trace it correctly.
Figure 3.9: Mapping files required for ToolB.
Appreciable amount of options are available for electromigration analysis. However not all of them are necessary. On the contrary choosing all of them will only
increase post processing time. There are options related to generation of probe
files and for characterization of devices and finally for the analysis itself. Our aim
was to be able to setup this tool for a very basic analysis, and so that results make
logical sense. If this is achieved then next step is to use options for advanced
analysis. The options chosen for basic analysis are more or less same like ToolA
options. However problems were faced while streaming in the GDSII file and
tracing a circuit.
3.4
Description of design under test
3.4
43
Description of design under test
A short description of the design under test is given in this section. As mentioned
earlier complexity of design was increased gradually while testing the tools. Complexity was based on number of nodes of designs. The LDO test case had approximately 3000 nodes which was considered big. However designs like LNA1 has
nodes which are greater than 500,000 and over 1,000,000 resistors and capacitors. Thus this gives an indication of complexity of circuits which tools should be
able to handle. Again LNA1 is one part of a chip. A full chip simulation will be
atleast four times the size of LNA1. The automotive standard specification generally include temperature of 125 degrees. The operational working hours cannot
be exactly specified in this report but it is more than 20,000 hours.
3.5
Summary
The tools used during this project have been discussed extensively in this chapter.
The tools provide various options for analysis but processing time must be taken
into account before using all options. A strategy to evaluate tools has been discussed and an optimum strategy has been devised. Both tool methodologies have
differences. ToolB has more number of steps to be followed before an analysis can
be presented to a user. However automation of these steps is also possible. In the
beginning of this chapter, evaluation points for both tools have been mentioned.
The summary of both tools can be put as follows:
• Evaluation of both tools is being done using test cases with increasing complexity.
• ToolA and ToolB both need simulator and extraction engine of ToolA for
calculating value of currents.
• ToolB methodology can be compared to ToolA indirect approach.
• ToolB becomes a third party tool, which means that ToolB and ToolA must
be interfaced correctly for ToolB to work.
• Test bench for evaluation should be carefully designed however does not
have strict requirements.
While setting up both tools, number of problems were faced. Some were related
to setup itself while others were related to functionality of tools. Considerable
amount of problems were found and resolved by using simpler test cases. Both
tools were finally setup and the LNA1 was analyzed using these tools. The results
of analysis have been documented in next chapter.
4
Results
In previous chapters we studied electromigration and its effects theoretically. We
also studied different parameters affecting electromigration and we setup tools
for accurate analysis. These tools were used to analyze analog circuits. One of the
goals of thesis work was to analyze LNA1, LNA2 and mixer for electromigration.
Although results of each test cases cannot be included graphically as is, but an
illustration of results with its analysis is presented and discussed in this chapter.
45
46
4
4.1
Results
Results of test cases
As mentioned before the complexity of test cases was increased gradually to evaluate both tools. A simple calculation by hand was done to check whether results
were correct in cases where number of nets were huge. This was based on assumption that ToolA simulator is validated and currents reported were correct.
Following steps were followed:
• Pick up random nets.
• Check for currents and width of nets.
• Calculate current density.
• Compare current density with limits.
• Compare reported violation and violations calculated by hand.
For maximum coverage, atleast five nets with least current, maximum current
and an average of both were chosen for hand calculations. The hand calculations
were performed for all test cases. //
The following section includes results of test cases used for evaluation:
Two resistors test case
The schematic of two resistors test case is presented in figure 4.1. This test case
allowed us to perform a ’sanity check’.
Figure 4.1: Simple test case with two resistors.
4.1
Results of test cases
47
The results were as follows:
• Analysis was done with ToolA and problems were found in the visualization tool of ToolA. The visualization tool could not recognize nets correctly,
and the tool included resistor ’R0’ inside net ’snet1’. The reason for this
behavior was unknown and hence a ticket was raised for the same.
• ToolB showed correct nets and result. However setting up ToolB for such
as simple test case took appreciable amount of time as compared to ToolA.
Problems were encountered with incorrect syntax for probe files which led
to unrecognized currents while characterizing the devices. However correction of syntax is a one time step. Hence this test case helped to prepare
ToolB for future analysis.
• Simulation time of ToolB was longer than ToolA by two seconds.
• Analysis of currents and violations displayed were as expected. Both tools
showed violations of 170% and hand calculations resulted in same result.
• Number of desirable and undesirable aspects of ToolB analysis were revealed with this test case, regarding analysis, error reporting, GUI etc.
• The GUI of both tools could be explored with this test case. ToolA GUI was
a little slow and unresponsive as compared to ToolB. This indicated better
handling of database by ToolB.
• Both tools also gave same and expected result with an Alternating Current
(AC) source.
The functionality of both tools was verified. ToolA indirect method was not used
with this test case since this test case was very small to verify indirect method.
Single inverter test case
The single inverter test case was used to understand whether both tools handle
active devices correctly. The schematic is given in 4.2 and since layout was a
standard Intellectual Property (IP) from the company, it cannot be disclosed. The
inverter however had multiple fingers on NMOS and PMOS. The test bench is
shown as below:
48
4
Results
Figure 4.2: Test case with single inverter.
Following are the results of the test case:
• ToolA results were as expected, however identification of nets was still a
problem.
• ToolB progressed smoothly however changes were needed in files with respect to names of instances, designs and output file names. Although minimum set of changes are necessary to make the tool work and are trivial but
user must be careful so that erroneous results are not produced. This step is
not required in ToolA which makes ToolA a bit more comfortable and user
friendly. The changes required to ToolA were minimal and were embedded
in the design flow.
• Both tools reported same result. However ToolB took twice as long as
ToolA.
• Files produced by ToolB which contained device characterizations were encrypted. Hence another tool was needed to verify the correctness of currents analyzed by ToolB. This made debugging in ToolB a bit difficult.
• The output log files produced by ToolB were quite a few as opposed to
ToolA producing only two log files. Hence this also increased complexity
to debug ToolB. With this test case, ToolB generated a few errors in the beginning which were related to connecting nets with correct ports of devices.
4.1
Results of test cases
49
Although these errors were few because of the small test case and hence
could be resolved, but it will become difficult for a larger test case.
With this test case we got a clear indication about complications which ToolB
could offer. However based on this test case we cannot discard ToolB because
its methodology looks promising for full chip simulation. We also understood
that increasing complexity of a circuit in smaller steps could take more time but
suppress surprises in future. For a given technology, test cases covering all components of technology library must be used in order to ensure compatibility of
technology library with the tools used.
Two inverters layout with poly resistor layout
Poly-resistors which are extensively used in layouts are put differently in a layout.
Identification of poly resistors is done by using marker layers in a layout which
indicate their presence. These resistors must be identified by both tools.
Figure 4.3: Polysilicon resistor construction on layout.
Figure 4.3 illustrates a typical polysilicon resistor in layout. If this resistor is not
traced correctly then the analysis could result in errors.
50
4
Results
Figure 4.4: Test case with two inverters
The test bench in figure 4.4 shows that this test case is stressed for high current
consumption. The resistors along with ’snet1’ offer high resistance which will
not cause voltage to drop across them in order to drive second inverter in the
schematic. An important point to note here is in previous test case and this test
case are typical examples of digital circuit. However we are working on analysis of analog signal nets, so are these test cases relevant? The answer is yes
because we are testing tools for functionality and from tools point of view analysis is done on active devices without their timing information. The tools are
configured for analog analysis and parasitic extraction is done in xDSPF format
and not cell DSPF. Hence inverters are being analyzed from an analog standpoint
which should give same result as digital analysis.
The results are as follows:
• ToolA ran smoothly with minimal changes as expected. However ToolA
gave errors as layout complexity increased, which were related to insufficient information in technology file. The technology file has information
which was provided by foundry and this was double checked. For example
the RMS current limits for metal layers did not have length dependency
and only depended on temperature. Such errors can be ignored.
• ToolA also gave errors with regards to instances. Some customized resistors
have three terminals when the tool expects two terminals. Hence for elec-
4.1
Results of test cases
51
tromigration post processing it needs to be given information about such
resistors. This information which contains models of instances needs to be
manually included before the start of simulation. It is possible for the tool
to manage data internally and hence eliminate this step.
• ToolB ran into problems with polysilicon resistor layout. Since ToolB could
not trace it, ’snet1’ was open circuited. This also changed functionality
of the circuit. Current at output net was reported as zero and hence no
violations. The mapping files needed to be modified and certain keywords
related to processing of polysilicon resistors were included to resolve this
problem.
• After investigating and solving problems, both tools gave expected result.
• ToolB took two and a half times more to analyze than ToolA. ToolB is dependent on resolution of the simulator output. For accuracy ToolB needs
resolution in picoseconds. Hence if resolution required is 100 picoseconds
then for one nanosecond duration of simulation, ToolB will need ten points
for each net. If we add one more net then ToolB has to analyze ten more
points in the simulation even if duration remains same. Hence ToolB shows
heavy dependency on number of nets which leads to extended simulation
time.
• ToolA indirect method was used to analyze this circuit. The simulation time
was negligibly lesser than direct method. Hence a bigger design is needed
to verify functionality of indirect approach.
With this test case we could narrow down problem of ToolB’s inability to trace
layout currently. This was also communicated to ToolB’s support team.
Low drop-out regulator test case
The earlier test cases were simple designs. We also had design information and
expected functionality was known before hand. However this might not always
be the case because a user might not have complete information about the design
and functionality. Hence under such circumstances a user must make sure with
the designer that functionality is verified. For the sake of evaluation we needed
a test case which was big but at the same time simple enough to understand its
functionality. The LDO test case fulfilled these parameters. Since this test case is
an IP of the company, limited amount of information is allowed to be disclosed.
However test bench information and a few results are shared in this sub section.
The test bench bench is shown in figure 4.5
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4
Results
Figure 4.5: LDO test bench used for analysis.
The results of the test were as follows:
• ToolA direct method reported results with a few errors related to via layer
definitions and metal layer definitions. However these errors were trivial
and can be ignored.
• ToolA indirect method resulted in a failure. The output waveforms in indirect method of the LDO test case did not match with output of direct
method of LDO test case. Comparison of text reports between indirect and
direct method resulted in relative errors to more than 200%. The comparison of lower current values showed big errors. The investigation revealed
that the cause was related to handling of database. In indirect method, parasitic information and device profiles are stored separately. During analysis
both informations (netlists) are stitched together to find current flowing
through a certain net. Optimization on parasitic information is also done,
which merges parallel resistors and capacitor into single RC equivalent circuit. During this stitching process some values of equivalent RC circuit
were incorrectly calculated. Since circuit profiles and parasitic information
were stored in an encrypted format, we could not go into details of how
exactly was the circuit being simulated. However we did try to isolate the
problem which has been mentioned. The number of nodes which were simulated was drastically low in iterated approach (3200 in direct versus 29 in
indirect method) which also gave an indication that stitching process has
some issues. The output waveforms are shown in figure 4.6:
4.1
Results of test cases
53
Figure 4.6: Output waveform of ToolA direct method.
In figure 4.6 waveform shows results of some of the nets using direct method
simulation. The same output waveform was seen after simulation of schematic
netlist. This indicates that direct method is behaving correctly. Although
direct method worked as expected result of indirect method was not correct.
Waveforms of indirect method for same nets is shown for comparison.
Figure 4.7: Output waveform of ToolA indirect method. It can be clearly
seen that output waveforms are not same.
As seen in waveform in figure 4.7, currents shown for all nets differ. In
the beginning it was thought to be an issue with capacitances not being included properly. Hence test case were built by using only resistances and extraction was done without including capacitances. However we still found
erratic results. Considerable amount of time was spent in finding the problem, and at the end it was concluded that the encrypted netlist must be seen
in order to understand the problem. Since this was not possible to provide
by ToolA vendor due to confidentiality clause, we had to leave this issue to
ToolA vendor development department to resolve.
• ToolB reported wrong results because ToolB could not resolve the polysil-
54
4
Results
icon structures. Since no tracing was done, results were wrong and could
not be trusted.
• ToolB took substantially longer time than ToolA to produce results.
As the results suggest most of the comparison of tools was done using LDO test
case. This test case was also beneficial in explaining problem and reproducing it
at vendor’s end.
Low noise amplifier test case
Finally after all the above evaluation results we started evaluating LNA1. We
already know that ToolB has some issues in tracing through a layout and ToolA
indirect method has some fundamental flaws. ToolA direct method however has
worked fine so far. With this information we expect ToolA direct method to give
correct results. We will also evaluate how ToolA handles big test cases. This test
case will give us a clear indication which tool can be included in the design flow.
The test bench of this test case is given in figure 4.8:
Figure 4.8: Test bench of LNA1 used for analysis.
As can be seen from figure 4.8, the test bench is complex and hence support of
the designer was needed. The test bench has realistic loads. The results were as
follows:
• ToolA completed simulation successfully with direct method. Waveforms
of simulation results were confirmed to be correct by comparing them to a
simulation without electromigration analysis. ToolA took around 45 minutes to complete. This simulation time is acceptable.
• ToolA simulation results with indirect method did not yield correct right
waveforms as expected. Although ToolA indirect method took substantially
less time than direct approach but results cannot be trusted.
4.1
55
Results of test cases
• ToolB resulted in wrong results because complex resistor structures (like
serpentine structure) could not be resolved. Hence ToolB gave wrong results. Also simulation time was more than one hour.
As mentioned before some complex shapes could not be resolved by ToolB. The
following two pictures illustrates this problem
Figure 4.9: GDSII view of LNA1
Figure 4.9 shows GDSII in which resistor in a serpentine structure is highlighted.
56
4
Results
We expect this structure to be present in layout view formed by ToolB. Without
this layout structure ToolB is going to consider it as an open circuit which give
incorrect results.
Figure 4.10: Layout traced by ToolB. The serpentine resistor structure in
figure 4.9 is missing.
Figure 4.10 shows the missing shape in ToolB as compared to GDSII figure 4.9.
4.2
Summary of results
57
Number of such misappropriations were found in layout. It becomes very difficult to find out each and every anomaly in layout specially when a layout contains
several metal layers with huge number of nodes.
Additional results
Apart from results of above test cases a few other results were noted.
• Results displayed by ToolA and ToolB have one difference. ToolA displays
nets and includes parasitic resistors in the information. For example, for
any violation on a net and the parasitic resistor location is given to user.
ToolB displays based on shapes since it works on GDSII file. The net along
with a shape is displayed to user. Although both convey same information,
but during evaluation parasitic resistor data information was found easier
to work with.
• A full chip simulation was one of the goals of thesis work. Since a full chip
was not available it was decided to use four instances of LNA1 which will
make the layout as big as an entire chip. A full chip simulation result with
ToolA direct method yielded correct results and took approximately two
hours. ToolB was not used for full chip simulation since the tracing issue
was not resolved.
• It was mentioned before that for ToolA two technology files can be used.
’FileA’ has extraction information and ’FileB’ has electromigration limits. It
is desired to have only one file which also contains information from ’FileB’.
This becomes easier from maintenance point of view. Hence such a file was
created and simulated with ToolA. This simulation resulted in failure and it
was later understood that ToolA did not support such a file. Hence a ticket
was filed to include this support.
• The calculation of average and root mean square currents depending on
waveforms were verified for ToolA and ToolB. An expression solver tool
was used for the same. Both tools reported expected result. Hence incorrect
calculation of average and root means square current was ruled out.
4.2
Summary of results
The results shown in this section can be summarized as follows:
• For simpler test cases, both tools behaved as expected.
• Interfacing of ToolB with ToolA is required for ToolB methodology to work.
This involves a few complex steps.
• For LDO test case and LNA1 test case, ToolA direct method worked while
ToolB could not resolve shapes in layout.
• Identifying connection of transistors to correct nets is an issue with ToolB.
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4
Results
• ToolA indirect method has some issues in its algorithm which needs to be
resolved by its vendor.
• ToolA direct method works for all designs.
These results are used to decide the tool to be included in design environment.
5
Conclusions and future work
Let us revisit the goals of thesis work before we conclude. The goals of thesis
work were defined in first chapter which were as follows:
• Setting up tool flow required for accurate analysis
• Analysis of a layout for electromigration violations using the flow.
• To investigate theoretically various causes for electromigration.
• To investigate various electromigration aware design methodologies.
A very obvious conclusion is, as technology scales down, electromigration risks
will only increase. This is specially true for digital designs since chip area reduces
with scaling down of technology nodes while area of analog circuits remains almost the same in majority of designs. However electromigration analysis for analog designs needs to be done in order to have an optimum trade-off between chip
area and electromigration risks.
Second chapter is dedicated to theoretical investigations as defined in the goals
of this internships. Third chapter is dedicated to investigations related to both
tools. Hence the conclusion can be divided in two parts. First part is related
to conclusions based on theoretical study and its practical implications. Second
part will include conclusions related to tools evaluated in this thesis work.
59
60
5.1
5
Conclusions and future work
Conclusions based on thereotical study
Figure 5.1: Formulation of design methodology based on theoretical study
and work performed during thesis.
The purpose of theoretical study was not only to understand electromigration
phenomenon but also to find novel ways of using them for accurate electromigration analysis. We studied various models in physics which cause electromigration. Using these models we identified parameters which can be used to accu-
5.1
Conclusions based on thereotical study
61
rately model electromigration in design phase to make designs safer. This leads
us to study various electromigration related design methodologies. Hence a very
useful conclusion would be a design methodology which takes into account all
factors of electromigration to build robust designs. Figure 5.1 shows a design
methodology which was put on paper during the course of thesis work.
This methodology is implemented in two steps to obtain an optimized layout.
First step is estimating currents from schematic simulation, and next step is calculating currents to high degree of accuracy using parasitic layout simulation.
There is a common factor for all methodologies studied. This common factor is
usage of efficient current driven routing methodology. Such methodologies will
ensure that designs are safe before performing electromigration checks. An effective design methodology would be one which will enable users for a confident
chip sign off. Along with currents, the methodology should also include various
parameters like Blech’s length, process and material related parameters for interconnects. These parameters are often given by foundry in form of models. For
example
Iavgmax = a + b(width − c)
(5.1)
where a, b and c are process related constants experimentally calculated by stress
tests for interconnects of different metals. This equation is specified for certain
number of hours based on Black’s equation. If maximum average current is
known then corresponding width can be calculated during design phase, and
vice versa during analysis phase. Figure 5.1 shows a possible design methodology which could be used during design phase using tools evaluated during thesis
work.
The schematic simulation will not include parasitic effects hence currents calculated will not be realistic but accurate enough to calculate widths for first iteration. A layout is designed by considering widths calculated from the previous
step and by using an automated current driven algorithms studied from papers
in first chapter. Once a layout is done, currents due to parasitics can be found
out by doing an extraction and a simulation. These currents are compared to previously calculated schematic currents, and only interconnects which are affected
heavily due to parasitics are modified. This methodology will give an optimum
trade-off between area and electromigration risks. Also this methodology can be
implemented using tools evaluated during the course of thesis work.
There are of-course advantages and disadvantages to this methodology. This
methodology will eliminate the need to buy licenses for tools to implement vendor specific design methodology. Although for setting up methodology, some
amount of scripting is required but this needs to be done only once. This methodology can be used for various designs over various technologies. All that needs to
be changed is input technology file. The electromigration engine can be invoked
via Unix command line, and scripting language like python or perl can be used
to setup the methodology and automate it.
Modifying a layout for changes is a tedious task from design point of view, specially if its a big layout. Hence last step in the methodology which is to optimize
62
5
Conclusions and future work
layout will prove cumbersome for big designs. However if this methodology is
used for smaller designs then it could be easier to optimize a small layout. Hence
designer can ensure electromigration reliability in a modular approach. Also
time taken for electromigration analysis of smaller designs is less. As more and
more smaller designs are integrated to build a chip, then designers will only have
to analyze interconnects at top level. Almost all EDA tools provide selective analysis and tools which are not capable of full chip electromigration analysis could
also be used.
The design methodology shown in 5.1 might not be unique, and could be found in
articles or papers. However based on tools available at the company, this design
methodology could be implemented successfully in practice.
5.2
Conclusion on tools setup and analysis of
designs
At the start of thesis work, both tools were in nascent stage. It was desired to
have at least one of the tools working in order to produce usable electromigration
analysis. By the end of project at least one flow out of three flows was found to
be correctly working. It was also decided by the company to include the working
flow in their design environment which emphasizes on successful completion of
this thesis work. A useful conclusion will be a result of comparison of both tools
which is done in this section.
5.2.1
Comparison of the tools
Some basic parameters for comparison were established in chapter three. Although both both tools calculate current densities to perform electromigration
analysis, there is a difference in methodology of analysis. Discussion on this point
is important since it will affect usability of both tools.
As seen in chapter three methodology of ToolA is pretty straightforward and
simple. Once ToolA is validated, the time required to setup ToolA for analysis is
very less. ToolA can work standalone and does not have to depend on third party
software. This is a very big advantage of ToolA because interfacing two tools is
always a very daunting and time consuming task. If a new version is released of
any tools, then the setup needs to be changed to adapt to newer version. This is
just one of the disadvantages out of many with respect to interfacing two tools.
ToolA also has a feature in which all electromigration and other analysis options
are integrated in one single GUI which makes it more user friendly. After successful simulation of LNA1 ToolA is expected to work on any designs for which
a normal simulation runs successfully. Although indirect method of ToolA has
fundamental flaws but direct method works successfully. ToolA’s visualization is
slow and unresponsive but analysis can be done successfully using text reports.
Also from debugging point of view only two files need to be inspected which are
simulation log file and electromigration post processing engine’s log file. Hence
debugging does not take much efforts. Very importantly, ToolA successfully sim-
5.3
Summary of conclusion and future work
63
ulated a layout which could be compared to area of a full chip.
In ToolB, DSPF along with simulation output file is used for creating electrical
models. The DSPF contains sections which has *|I, *|P, *|S and *|NET as discussed before. In instances section every device with its input and output ports
are mapped. Also a list of subnodes, instances and pins with their co ordinates
are listed in a separate file. Now these files are the basis for creating physical models. Resistance of each shape connected to a subnode is extracted from the tech
file. This resistance of a shape is used to calculate distribution of current throughout net. Hence ToolB relies on size of a shape, connection of a shape to devices in
nets and then distributes current through all shapes accordingly. Here key point
is parasitic extraction of capacitances. ToolB uses capacitance at every node from
DSPF as a golden reference. Hence distribution of parasitic capacitances may
differ in comparison to ToolA. Apart from this setup time, files required for debugging and number of steps involved in analysis are some of the drawbacks of
ToolB in comparison to ToolA. Also from analysis perspective ToolB does not offer any significant advantages. GUI is smooth and informative as compared to
ToolA. However this is not a blocking point for ToolA. Hence from a designer
perspective ToolB will not be a most favorable option even if issues in ToolB are
solved completely.
5.2.2
Analysis of designs
This thesis work started with a goal of analyzing LNA1, LNA2 and Mixer layouts for electromigration. Analysis of LNA1 was done successfully during thesis
work, and a push button approach of ToolA direct method makes analysis of
LNA2 and Mixer fairly easy. If respective test benches are acquired then both
designs could be very easily analyzed for electromigration. Also considering successful full chip simulation of ToolA, both designs can be analyzed at the same
time, provided simulation converges. LNA1 was found to be almost four times
safe, which also indicates that design approach was fairly conservative. Hence
from electromigration perspective, area of LNA1 can be reduced. Transient simulation time was 100 nanoseconds in order to give better accuracy for average and
RMS currents. The time taken for simulation was one and a half hour which is
acceptable.
5.3
Summary of conclusion and future work
This section marks the end of this thesis report. Hence it would be beneficial to
sum up this thesis work in the form of short summary of conclusions.
• The theoretical study during the thesis work resulted in a two step design
methodology as discussed in conclusions section.
• Electromigration analysis for analog design in 65 nm technology was successfully implemented.
• Standalone tools preferred instead of interfacing two or more tools.
64
5
Conclusions and future work
• A tabular form of tools comparison can be shown in table 5.1:
Comparison
point
Ease of analysis
and setup
Methodology
ToolA
method
Simpler
direct
ToolA indirect
method
Simpler
ToolB method
Complex
Direct method Indirect method Could not setup
results can be has issues to re- the methodoltrusted
solve
ogy
Accuracy
Depends
on Depends
on Depends
on
ToolA simulator ToolA simulator ToolA simulator
and
parasitic and
parasitic and
parasitic
extraction
extraction
extraction
Graphics user Slow and unre- Slow and unre- Smooth and ininterface
sponsive
sponsive
formative
Full chip simula- Can
simulate Not until fun- Not applicable
tion capability
full chip
damental issues since methodare resolved
ology is not
setup
Runtime
Acceptable run- Runtime can be Very long runtime
reduced drasti- times even for
cally if issues smaller designs
are resolved
Table 5.1: Comparison of tools
• It was concluded that ToolA direct methodology can be used in design flow
without substantial increase in runtime and loss of accuracy.
• Goals of internship and thesis were fulfilled to our satisfaction.
The conclusions made above were also presented to the company and respective
stake holders and it was well received. Also it was agreed that more work needs
to be done in order to make electromigration safe designs.
5.4
Future work
On a number of occasions, interesting information in articles, papers and presentation related to electromigration was noted. However some of them were out of
the scope of this thesis work, but could be useful in future to investigate in order
to increase reliability of designs. Apart from these some of the work which was
left pending at end of this project can also be included as future work. They are
listed as follows:
• Silicon validation of results given by tools. A silicon validation is a formal
way of verification of result. Although this could be expensive, but will give
5.4
Future work
65
a benchmark of tools.
• Electromigration analysis to be done on LNA2 and Mixer. Same setup for
LNA1 can be used which is single push button analysis.
• Electrically aware design flow from different vendors look promising and
should be investigated.
• Implementation of digital signal net electromigration.
• Implementation of signal net electromigration for other technologies.
• Study of various layout structures to increase resistance to electromigration.
• Automation of ToolA direct method.
• Circuit techniques which could help in prediction, diagnosis or reduction
of electromigration. One such possible technique is shown below
Figure 5.2: Primitive circuit which tries to ’heal’ the interconnect by making
the current flow in the opposite direction.
As shown in the circuit of figure 5.2, an interconnect damage can be detected by periodically checking resistance of the interconnect. If resistance
is higher than desired then a ’recovery phase’ can be incorporated, where
current is made to flow in opposite direction for a particular time. This
will partially heal interconnect and increase lifetime. There are problems
with respect to leakage currents of transistors which are used as switches,
chip area and power consumption. Hence a more efficient circuit could be
a possible future work.
• Another possible work could be imposing restrictions on layout design based
on electromigration models. This can be done through scripting and backannotation. This methodology will ensure that interconnects will not violate electromigration rules, however this will also put more restrictions on
66
5
Conclusions and future work
designer.
The points in future work aims at producing an effective and generic design
methodology which can be adapted to future technologies.
5.4.1
Learning outcomes
The motive behind taking up this internship was not only to understand electromigration and tools but also to get a first hand view of semiconductor industry.
During the course of internship I interacted extensively with application engineers of both EDA tool vendors. I was exposed to various process technologies
available in market and which are extensively used by other companies. I also attended presentation on state of the art technologies being developed by company
and interacted with designers from various other countries. Setting up tools in
Linux environment and learning Python to automate tasks is a valuable addition
to my skill set. Understanding company’s way of working on tools and designs
gave me a solid view of what to expect in semiconductor industry.
Acronyms
Fmax Maximum Frequency. 4
Iavg Average Current. 3
Ipeak Peak Current. 3
Irms Root Mean Square Current. 3
AC Alternating Current. 3, 5, 6, 22, 27, 47
AE Application Engineer. 25
ASCII American Standard Code for Information Interchange. 34, 35
DC Direct Current. 3, 5, 6, 20, 22, 27
DRC Design Rule Check. 16
DSPF Detailed Standard Parasitic Format. 29, 32–37, 39–41, 63
EDA Electronic Design Automation. 2, 10, 25, 28, 40, 62, 66
GDSII Graphic Database System. 29, 40, 42, 55–57
GUI Graphics User Interface. 42, 47, 62, 63
IC Integrated Circuits. 1
IP Intellectual Property. 47, 51
IR Voltage drop analysis. I stands for current and R for resistance.. 1
LDO Low Drop Out voltage regulator. 32, 43, 51, 52, 54, 57
LNA1 Low Noise Amplifier. ’1’ stands for the first one in series.. 25, 32, 43, 45,
54, 57, 62, 63, 65
67
68
Acronyms
LNA2 Low Noise Amplifier. ’2’ stands for the second one in series.. 25, 32, 45,
63, 65
MTTF Mean Time To Failure. 3, 16, 26, 27
PDK Process Development Kit. 38
RC Resistor and Capacitor. 33, 35, 52
RMS Root Mean Square. 4, 20, 50, 63
VHDL Verilog Hardware Description Language. 6
xDSPF Tansistor Detailed Standard Parasitic Format. 34, 35, 50
Bibliography
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circuits. In VLSI Design, 2005. 18th International Conference on, pages 77–
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[2] M.H. Lin and AS. Oates. Ac and pulsed-dc stress electromigration failure
mechanisms in cu interconnects. In Interconnect Technology Conference
(IITC), 2013 IEEE International, pages 1–3, June 2013. Cited on page 3.
[3] Yun-Chih Tsai, Tai-Hung Li, Tai-Chen Chen, and Chung-Wei Yeh.
Electromigration- and obstacle-avoiding routing tree construction. In VLSI
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