for Phase Ballasts Digital Controller Design

for Phase Ballasts Digital Controller Design
2004 35th Annual IEEE Power Electronics Specialists Conference
Aachen, Germany. 2004
Digital Controller Design for Electronic Ballasts with Phase Control
Yan Yin and Regan Zane
Colorado Power Electronics Center
University of Colorado at Boulder
Boulder, CO 80309-0425
[email protected], [email protected]
Abslrncf-This paper presents an approach for digital
controller design and implementation in resonant inverters and
electronic ballasts. The controller is designed around an inner
phase loop for fast regulation of the resonant tank operating
point and an outer current loop to control the output load
current. The concept ofdirect digital phase control is reviewed,
followed by a description of a complete dual-loop digital
controller design. The controller is applied to an HID ballast
control system with additional functions including lamp startup and output over-voltage protection. The digital system is
described with Verilog coding and can be synthesized and
implemented automatically in standard digital logic. An
FPGA-based test bed for the digital controller is implemented
for rapid prototyping. re-programmability, and realistic
hardware realization.
High-frequency resonant inverters find a wide range of
applications, including electronic ballasts, induction heating,
and motor drives [I-41. The dc input power is generally
converted to ac output through a switching network
followed by a resonant tank. In most applications, a closedloop controller is required to regulate the output waveforms
for improved rejection of component tolerances, variations
in environmental conditions, and variable power control.
Common approaches for regulating the output include
control of duty cycle, switching frequency, or dc input
voltage [5-71, where frequency control is one of the most
popular control schemes due to its simplicity and wide
dynamic range. Another promising control method is to
regulate the relative phase angle between mid-point voltage
and resonant inductor current or voltage. A direct digital
approach to phase control was proposed in [8]. Compared
with frequency control, the phase control approach provides
advantages such as self-tuning to resonance and less
sensitivity to variations.
A digital controller implementation has many advantages
over its analog counterpart, including low sensitivity to
parameter and temperature variations, fewer external
components and smaller size. It can also utilize the fast
advances in digital CAD and silicon processing for full
design automation, reprogrammability and low cost
hardware implementation. By targeting standard submicron digital processes, the hardware-based digital
controller is not only cost effective, but also provides fine
time resolution (down to sub nano-second), allowing
accurate control even in the MHz switching frequency
In this paper, the design of a digital controller for an LCC
resonant inverter is presented with inductor current phase
regulation. The controller is successfully applied to a 400W
HID ballast controller. The control functions are described
in Verilog and synthesized and implemented through
automated CAD tools on a Xilinx FPGA for rapid
prototyping and realistic hardware evaluation. The direct
digital phase control concept is reviewed first in Section 11.
The key control blocks for the digital controller are
discussed in Section 111, followed by an application to the
HID ballast with lamp start-up and over-voltage protection
in Section IV. The FGPA implementation details are present
in Section V along with experimental results. The
conclusions are given in Section VI.
The direct digital phase control concept, strategy and
hardware implementation were presented in [E]. The key
concept and resulting control equation and state diagram for
digital realization are briefly reviewed here.
A typical resonant LCC inverter is shown in Figure 1.
When it is operated above resonance, the resonant inductor
dominates the resonant tank such that the input impedance
of the inverter is inductive and the inductor current ir lags
(and hence the inductor voltage vL leads) the mid-point
voltage v, from 0" to 90" as the switching frequency shifts
away from resonance. The output power decreases as the
phase angle varies from 0" to 90". Thus it is possible to
control the output power by directly controlling the phase
angle between the mid-point voltage and the inductor
current or voltage. The switching frequency is thus
sponsored by General Electric CO Global Research, through
Colorado Power Electronics Center and IS cofunded by the Department of
Energy's National Energy Technology Laboratory under Cwperatlve
Agreement DE-FC26-OZNT41252
This work
0-7803-8399-0/04/$20.0002004 IEEE.
Figure I Typical resonant inverter configurationwith LCC r a n a n t rank
2004 35th Annual IEEE Power Electronics Specialists Conference
Aochen, Cermorry, 2004
Figure 2 Inductor current and mid-paint voltage in a half-bridge LCC
monani inverter
indirectly controlled through phase control. By controlling
the inductor current phase angle to be greater than Oo, the
system will be forced to operate above resonance, resulting
in ZVS operation for appropriately designed resonant tanks.
If the resonant frequency shifts due to variations of the tank
elements and load, the phase controller will self-tune to the
resonant frequency on a near cycle-by-cycle basis and the
operating point will not be affected.
The basic strategy to directly control the inductor current
phase can be illustrated by Figure 2. The essence of the
control is to time the period by detecting the inductor
current zero crossing, then compute the required time delays
from the zero crossing to determine when to turn on or off
the high and low-side gates to achieve the desired phase.
Given a phase command, the time delay from the zero
crossing of the inductor current to the falling edge of the
mid-point voltage can be computed as
Figure 3 illustrates the system diagram for a digitally
controlled LCC invtzrter with inductor current phase
regulation. The functional diagram for the digital controller
is shown in Figure 4. The outer loop controls the output
current (it can also he output voltage or power) sensed by a
small resistor. The current is converted to a digital
representation by an A D converter. The peakdetector
block detects the peak value of the output current found for
each switching cycle The detected peak current is then
compared with a reference current and the error signal is
sent to the compensator. The compensator generates the
phase command to the inner phase loop to regulate the phase
angle between the mid-point voltage and the inductor
current. In the following, the design details for key
functional blocks of this digital control system will be
Phase controller
The basic concept of the phase control is reviewed in
Section II and the alesign implementation details were
presented in [SI. The core of the phase controller is
described in a synchronous state machine, where the state
diagram is illustrated in Figure 5 . T,,
is computed
according to (I). Th: phase command comes from the
compensator, and the inductor current is sensed by a current
transformer and converted to a square wave through a highspeed comparator. Thi: state machine runs at 200MHz with
5ns time resolution.
where 0 < a,[n] 2 2" - 1, m is the number of bits of the
digital phase command, and a,[n] = 0 corresponds to 0"
while al[n] = 2" - 1 corresponds to 90".
The control scheme based on Figure 2 is:
(a) Detect the zero crossing of the inductor current
using a high-speed comparator;
(b) Record T, of the previous cycle, which is the time
interval between two positive zero-crossing points;
(c) Compute T& according to (I);
(d) Wait for Td+, then turn off the high-side (HS) gate
and turn on the low-side (LS) gate with a proper
(e) Wait for half of C,then turn on the HS gate and
turn off the LS gate with a proper deadtime;
(f) Wait for the next zero crossing of the inductor
voltage, then repeat this cycle.
Similar control scheme can also be applied to the inductor
voltage phase control [SI. This control scheme can be easily
realized using standard digital logic and implemented in a
custom CMOS digital control IC or programmable logic. It
can also be implemented in a microcontroller or DSP.
= 400
= 5nF
Figure 3 System diagram for digitally eontrolled LCC inverter wilh
inductor current phase control
2004 35th Annual IEEE Power Electronics Specialists Conference
Aachen. Germany, 2004
Figure 4 Funaianal diagram for digital controller
MD converter
The AID converter converts the sensed output current to
an 8-bit digital representation. The full scale of the current is
flOA and the LSB of the current represents about 78mA.
The A/D conversion is clocked at 32 times of the switching
frequency and synchronized to the positive zero crossing of
the inductor current.
C. Peak detection
The peak detector finds the peak current for each
switching cycle. The finding process can be illustrated using
Figure 6. A temporary register is used to store the peak
value. The final peak value for each switching cycle is
latched by peak-/atch that is generated by the phase
Figure 6 Peak-current detector
controller at the positive zero-crossing of the inductor
current. The temporary peak register is cleared at the same
time to prepare for the next switching cycle comparison.
D. Compensator
The design of the compensator is according to the smallsignal transfer function from the inductor phase to the
output current as shown in Figure 7, which is derived using
the small-signal model developed in [9] at steady-state
operating point 9, = 73.8' and F, = 14OHz. The model in
[9] was established to find the transfer function from
switching frequency to the output current. With this model,
the phase-to-output current transfer function is found
indirectly as
io", = 0
t f,
G ( s )= -
Figure 5 State diagram ofthe digital phase conuoller
From the small-signal transfer function illustrated in Figure
7, it can be seen that it exhibits a single pole response in
low-frequency range. Thus a simple integrator-type
compensator is enough to achieve sufficient phase margin
as well as very high low frequency gain. The digital
compensator is designed according to the signal flow graph
shown in Figure 8 with the form of
Anchen, Germany, 2004
2004 M f h Annual IEEE Power Elecrronics Specialists Conference
Figure 9 HID lamp sfaTt-u~)conmller
be implemented internally for a standalone system. The
DCO runs at a frequency much higher than closed-loop
system operating frequency range such that it does not
interfere with normal operation.
JOk 5Ok
/ m w (H:)
Figure 7 Small-signal transfer function from inductor current phase to
output current
~ [ k [10:01
The digital controllsr described in Section 111 has been
applied to control a complete HID ballast system. For this
application, additional supervisory and control functions are
required beyond the tiasic controller of Section 111. Here,
two additional functions are described and implemented to
demonstrate the flexibility and capability of the digital
approach. First, a lamp start-up (ignition) controller is used
to sweep the lamp voltage to ignite the lamp, followed by
ignition detection and immediate transition to closed-loop
control. Second, the output voltage is monitored for output
over-voltage protection in order to prevent component
failures and excessive !;tress.
Figure 8 Compensator design
where e[k] = /&I and p[k] is a 9-hit phase command.
The error signal generated hy the comparison is truncated to
4 hits to reduce processing requirements (smaller look-up
tahle or multiplier).
With the gains of the A D and the digitalization of the
phase taken into consideration, fl is selected as 0.25 to
achieve the crossover frequency ahout 1 kHz. With this
design, (3) can he easily implemented digitally by shilling
the decimal point of the error signal two-bit left and adding
it to the previous phase command. To improve the accuracy,
the two decimal hits are always kept during the internal
computation, which means p[k] is an 1 I-bit signal with two
LSBs being decimal hits. The final output is truncated to get
a 9-hit phase output.
E. Digitally controlled oscillator (DCO)
The function of the digitally controlled oscillator (DCO)
is to initiate the oscillation of the resonant tank, which is
necessay for detection of the inductor current for phase
regulation. When the system starts to oscillate, the closedloop controller takes over the control of the system. The
DCO mode and closed-loop mode outputs are selected by a
multiplexer as shown in Figure 4, which is controlled hy an
external mode selection signal in our test bed and can also
Start-up controller.
The purpose ofthe start-up controller is to generate a high
voltage to strike the iirc of the lamp. To incorporate the
start-up function with the digital phase controller, the startup controller sweeps the phase command from 90° toward
resonance. Every 5ms (programmable), the phase decreases
ILSB (about 0.175O). Hefore the lamp ignites, the system is
operating near open-circuit. During the phase sweep, the
voltage across the lamp increases, until at some point the
lamp ignites and the current flows through the arc. The
digital controller keeps: monitoring the lamp current. When
it detects a lamp current above a preset threshold, the phase
sweep is stopped and .the closed-loop controller takes over
the control and the system operates in closed-loop mode.
The diagram of the start-up controller is shown in Figure 9.
If the ignition fails (no desired current detected) even if the
phase has been swept I:O a very low value (close to O"), the
start-up controller will stop the sweep process and jump to
DCO mode. The phase command is set to 90" and the startup controller will try to ignite the lamp again.
2004 35th Annual IEEE Power Electronics Speciulists Conference
Aachen. Germany, 2004
Figure 10 Syslem d i a m of FGPA-baEe digital HID c~nwllei
As the compensator is usually saturated during the lamp
start-up process (because the lamp current is far from the
reference current), the phase output of the closed-loop
compensator (phase-cl[S:O] in Figure 9) is quite different
from that of the start-up controller @hme-st[S:O] in Figure
9). To avoid the large transition during the switching from
start-up mode to the closed-loop mode, the output of the
compensator can be forced to he equal to the output of the
start-up controller during the start-up process and the
compensator works normally only after the lamp is ignited.
B. Over-voltage protection
The over-voltage protection module monitors the lamp
voltage by a voltage divider. When over-voltage happens, it
immediately shuts down the gate driver and switches back to
DCO mode, which runs at a much higher frequency and
generates a very low output voltage. The system will not
restart until the over-voltage is removed and the lamp cools
The digital controller discussed in Sections 111 and IV can
be implemented in an ASIC with standard digital process.
For rapid prototyping and hardware evaluation, it is realized
using a Xilinx Virtex II xc2v1000 FPGA. Figure IO
illustrates the system diagram for the test bed. All functional
blocks except the AiD converter are described in Verilog
and synthesized and implemented automatically in the
FPGA, as shown inside the dashed box. The inductor current
is sensed through a current transformer (CT). The AID
converter is THS 1230 from Texas Instruments, which is a
12-bit AiD with only eight bits being -used for our
application. An external switch is used to select DCO mode
(250KHz) or closed-loop mode. When the closed-loop mode
is selected, the start-up controller initiates the phase-sweep
until the lamp ignites, then the system runs at closed-loop
mode. The over-voltage threshold is set to 3KV. The lamp
voltage for the normal operation is about 200V and the
ignition voltage is about IKV. The normal operating
frequency for full power is I40KHz.
The steady-state operating waveforms are shown in
Figure 11 and the step response is shown in Figure 12. It can
be seen that the system is stable. Figure 13 illustrates the
start-up process with a 40R resistive load. The system first
runs at DCO mode for IOms, then starts to sweep the phase.
When the current reaches the threshold that is set to be the
same as the steady-state value, the system enters into the
closed-loop operation mode smoothly.
2004 351h Annual IEEE Power Electronics Specialisls Conference
Aachen. Germany, 2004
(a) Lamp peak current = 3A. lamp power = 350W
\”. . .
. .I . . ...... .. . .r.ii-....:..
.*.. .
Figure I2 Step response (lamp peak current: 2.5A3 2.8A) (chl: lamp
voltage: ch2 lamp curient, ch3: inductor current; cM:mid-point
,.. . . . .
(b) Lamp peak current = 2A, lamp power = 190W
Figure II Steady-statewaveforms (chl: lamp voltage; ch2: lamp current;
ch3 inductor current; ch4: mid-point voltage)
This paper presents a digital controller design for resonant
inverten and electronic ballasts with resonant inductor
current phase regulation. The key control blocks are
discussed that can be described with Verilog and
implemented in standard digital logic with automatic
synthesis, layout and route. The digital controller is
successfully applied to a 400W HID ballast and
implemented in an FGPA for rapid prototyping and realistic
hardware implementation.
Figure I3 S M - u p waveiorms with resistive load (ch2: output voltage;
eh3: inductor current)
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