datasheet for EN29LV320C by Eon Silicon Solution

datasheet for EN29LV320C by Eon Silicon Solution
EN29LV320C
EN29LV320C
32 Megabit (4096K x 8-bit / 2048K x 16-bit) Flash Memory
Boot Sector Flash Memory, CMOS 3.0 Volt-only
FEATURES
• Single power supply operation
- Full voltage range: 2.7 to 3.6 volts read and
write operations
• High performance
- Access times as fast as 70 ns
• Low power consumption (typical values at 5
MHz)
- 9 mA typical active read current
- 20 mA typical program/erase current
- Less than 1 μA current in standby or automatic
sleep mode
• Flexible Sector Architecture:
- Eight 8-Kbyte sectors, sixty-three 64k-byte
sectors
- 8-Kbyte sectors for Top or Bottom boot
- Sector Group protection:
Hardware locking of sectors to prevent
program or erase operations within individual
sectors
Additionally, temporary Sector Unprotect
allows code changes in previously locked
sectors
• Secured Silicon Sector
- Provides a 128-words area for code or data
that can be permanently protected.
- Once this sector is protected, it is prohibited
to program or erase within the sector again.
•
-
High performance program/erase speed
Word program time: 8µs typical
Sector erase time: 100ms typical
Chip erase time: 8s typical
• JEDEC Standard compatible
• Standard DATA# polling and toggle bits
feature
• Erase Suspend / Resume modes:
Read and program another Sector during
Erase Suspend Mode
• Support JEDEC Common Flash Interface
(CFI).
• Low Vcc write inhibit < 2.5V
• Minimum 100K program/erase endurance
cycles
• RESET# hardware reset pin
- Hardware method to reset the device to read
mode
• WP#/ACC input pin
- Write Protect (WP#) function allows
protection of outermost two boot sectors,
regardless of sector protect status
- Acceleration (ACC) function provides
accelerated program times
• Package Options
- 48-pin TSOP (Type 1)
- 48 ball 6mm x 8mm TFBGA
• Industrial Temperature Range
GENERAL DESCRIPTION
The EN29LV320C is a 32-Megabit, electrically erasable, read/write non-volatile flash memory,
organized as 4,194,304 bytes or 2.097,152 words. Any word can be programmed typically in 8µs.
The EN29LV320C features 3.0V voltage read and write operation, with access times as fast as 70ns
to eliminate the need for WAIT states in high-performance microprocessor systems.
The EN29LV320C has separate Output Enable (OE#), Chip Enable (CE#), and Write Enable (WE#)
controls, which eliminate bus contention issues. This device is designed to allow either single Sector
or full Chip erase operation, where each Sector can be individually protected against program/erase
operations or temporarily unprotected to erase or program. The device can sustain a minimum of
100K program/erase cycles on each Sector.
.
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
1
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
CONNECTION DIAGRAMS
48-Ball TFBGA
Top View, Balls Facing Down
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
2
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
TABLE 1. PIN DESCRIPTION
LOGIC DIAGRAM
Pin Name
Function
A0-A20
21 Address inputs
DQ0-DQ14
15 Data Inputs/Outputs
DQ15 / A-1
DQ15 (data input/output, in word mode),
A-1 (LSB address input, in byte mode)
CE#
CE#
Chip Enable
OE#
OE#
Output Enable
WE#
Write Enable
WP#/ACC
Write Protect / Acceleration Pin
RESET#
Hardware Reset Pin
BYTE#
Byte/Word mode selection
RY/BY#
Ready/Busy Output
Vcc
Supply Voltage
(2.7-3.6V)
Vss
Ground
NC
Not Connected to anything
EN29LV320C
21
16 or 8
A0 – A20
DQ0 – DQ15
(A-1)
WE#
WP#/ACC
RESET#
RY/BY#
BYTE#
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
3
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
Table 2A. Top Boot Sector Address Tables (EN29LV320CT)
U
64/32
Address Range (h)
Byte mode (x8)
000000–00FFFF
Address Range (h)
Word Mode (x16)
000000–007FFF
000001xxx
64/32
010000–01FFFF
008000–00FFFF
SA2
000010xxx
64/32
020000–02FFFF
010000–017FFF
SA3
000011xxx
64/32
030000–03FFFF
018000–01FFFF
SA4
000100xxx
64/32
040000–04FFFF
020000–027FFF
SA5
000101xxx
64/32
050000–05FFFF
028000–02FFFF
SA6
000110xxx
64/32
060000–06FFFF
030000–037FFF
SA7
000111xxx
64/32
070000–07FFFF
038000–03FFFF
SA8
001000xxx
64/32
080000–08FFFF
040000–047FFF
SA9
001001xxx
64/32
090000–09FFFF
048000–04FFFF
SA10
001010xxx
64/32
0A0000–0AFFFF
050000–057FFF
SA11
001011xxx
64/32
0B0000–0BFFFF
058000–05FFFF
SA12
001100xxx
64/32
0C0000–0CFFFF
060000–067FFF
SA13
001101xxx
64/32
0D0000–0DFFFF
068000–06FFFF
SA14
001110xxx
64/32
0E0000–0EFFFF
070000–077FFF
SA15
001111xxx
64/32
0F0000–0FFFFF
078000–07FFFF
SA16
010000xxx
64/32
100000–10FFFF
080000–087FFF
SA17
010001xxx
64/32
110000–11FFFF
088000–08FFFF
SA18
010010xxx
64/32
120000–12FFFF
090000–097FFF
SA19
010011xxx
64/32
130000–13FFFF
098000–09FFFF
SA20
010100xxx
64/32
140000–14FFFF
0A0000–0A7FFF
SA21
010101xxx
64/32
150000–15FFFF
0A8000–0AFFFF
SA22
010110xxx
64/32
160000–16FFFF
0B0000–0B7FFF
SA23
010111xxx
64/32
170000–17FFFF
0B8000–0BFFFF
SA24
011000xxx
64/32
180000–18FFFF
0C0000–0C7FFF
SA25
011001xxx
64/32
190000–19FFFF
0C8000–0CFFFF
SA26
011010xxx
64/32
1A0000–1AFFFF
0D0000–0D7FFF
SA27
011011xxx
64/32
1B0000–1BFFFF
0D8000–0DFFFF
SA28
011100xxx
64/32
1C0000–1CFFFF
0E0000–0E7FFF
SA29
011101xxx
64/32
1D0000–1DFFFF
0E8000–0EFFFF
SA30
011110xxx
64/32
1E0000–1EFFFF
0F0000–0F7FFF
SA31
011111xxx
64/32
1F0000–1FFFFF
0F8000–0FFFFF
SA32
100000xxx
64/32
200000–20FFFF
100000–107FFF
SA33
100001xxx
64/32
210000–21FFFF
108000–10FFFF
SA34
100010xxx
64/32
220000–22FFFF
110000–117FFF
SA35
100011xxx
64/32
230000–23FFFF
118000–11FFFF
SA36
100100xxx
64/32
240000–24FFFF
120000–127FFF
SA37
100101xxx
64/32
250000–25FFFF
128000–12FFFF
SA38
100110xxx
64/32
260000–26FFFF
130000–137FFF
SA39
100111xxx
64/32
270000–27FFFF
138000–13FFFF
Sector
A20 – A12
Sector Size
(Kbytes / Kwords)
SA0
000000xxx
SA1
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
4
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
SA40
101000xxx
64/32
280000–28FFFF
140000–147FFF
SA41
101001xxx
64/32
290000–29FFFF
148000–14FFFF
SA42
101010xxx
64/32
2A0000–2AFFFF
150000–157FFF
SA43
101011xxx
64/32
2B0000–2BFFFF
158000–15FFFF
SA44
101100xxx
64/32
2C0000–2CFFFF
160000–167FFF
SA45
101101xxx
64/32
2D0000–2DFFFF
168000–16FFFF
SA46
101110xxx
64/32
2E0000–2EFFFF
170000–177FFF
SA47
101111xxx
64/32
2F0000–2FFFFF
178000–17FFFF
SA48
110000xxx
64/32
300000–30FFFF
180000–187FFF
SA49
110001xxx
64/32
310000–31FFFF
188000–18FFFF
SA50
110010xxx
64/32
320000–32FFFF
190000–197FFF
SA51
110011xxx
64/32
330000–33FFFF
198000–19FFFF
SA52
110100xxx
64/32
340000–34FFFF
1A0000–1A7FFF
SA53
110101xxx
64/32
350000–35FFFF
1A8000–1AFFFF
SA54
110110xxx
64/32
360000–36FFFF
1B0000–1B7FFF
SA55
110111xxx
64/32
370000–37FFFF
1B8000–1BFFFF
SA56
111000xxx
64/32
380000–38FFFF
1C0000–1C7FFF
SA57
111001xxx
64/32
390000–39FFFF
1C8000–1CFFFF
SA58
111010xxx
64/32
3A0000–3AFFFF
1D0000–1D7FFF
SA59
111011xxx
64/32
3B0000–3BFFFF
1D8000–1DFFFF
SA60
111100xxx
64/32
3C0000–3CFFFF
1E0000–1E7FFF
SA61
111101xxx
64/32
3D0000–3DFFFF
1E8000–1EFFFF
SA62
111110xxx
64/32
3E0000–3EFFFF
1F0000–1F7FFF
SA63
111111000
8/4
3F0000–3F1FFF
1F8000–1F8FFF
SA64
111111001
8/4
3F2000–3F3FFF
1F9000–1F9FFF
SA65
111111010
8/4
3F4000–3F5FFF
1FA000–1FAFFF
SA66
111111011
8/4
3F6000–3F7FFF
1FB000–1FBFFF
SA67
111111100
8/4
3F8000–3F9FFF
1FC000–1FCFFF
SA68
111111101
8/4
3FA000–3FBFFF
1FD000–1FDFFF
SA69
111111110
8/4
3FC000–3FDFFF
1FE000–1FEFFF
SA70
111111111
8/4
3FE000–3FFFFF
1FF000–1FFFFF
Note: The address bus is A20:A-1 in byte mode where BYTE# = VIL or A20:A0 in word mode where
BYTE# = VIH
B
B
B
B
Table 2B. Top Boot Security Sector Address (EN29LV320CT)
Sector Address
A20 ~ A12
Sector Size
(bytes / words)
Address Range (h)
Byte mode (x8)
Address Range (h)
Word Mode (x16)
111111111
256 / 128
3FFF00–3FFFFF
1FFF80–1FFFFF
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
5
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
Table 2C. Bottom Boot Sector Address Tables (EN29LV320CB)
U
8/4
Address Range (h)
Byte mode (x8)
000000–001FFF
Address Range (h)
Word Mode (x16)
000000–000FFF
000000001
8/4
002000–003FFF
001000–001FFF
SA2
000000010
8/4
004000–005FFF
002000–002FFF
SA3
000000011
8/4
006000–007FFF
003000–003FFF
SA4
000000100
8/4
008000–009FFF
004000–004FFF
SA5
000000101
8/4
00A000–00BFFF
005000–005FFF
SA6
000000110
8/4
00C000–00DFFF
006000–006FFF
SA7
000000111
8/4
00E000–00FFFF
007000–007FFF
SA8
000001xxx
64/32
010000–01FFFF
008000–00FFFF
SA9
000010xxx
64/32
020000–02FFFF
010000–017FFF
SA10
000011xxx
64/32
030000–03FFFF
018000–01FFFF
SA11
000100xxx
64/32
040000–04FFFF
020000–027FFF
SA12
000101xxx
64/32
050000–05FFFF
028000–02FFFF
SA13
000110xxx
64/32
060000–06FFFF
030000–037FFF
SA14
000111xxx
64/32
070000–07FFFF
038000–03FFFF
SA15
001000xxx
64/32
080000–08FFFF
040000–047FFF
SA16
001001xxx
64/32
090000–09FFFF
048000–04FFFF
SA17
001010xxx
64/32
0A0000–0AFFFF
050000–057FFF
SA18
001011xxx
64/32
0B0000–0BFFFF
058000–05FFFF
SA19
001100xxx
64/32
0C0000–0CFFFF
060000–067FFF
SA20
001101xxx
64/32
0D0000–0DFFFF
068000–06FFFF
SA21
001110xxx
64/32
0E0000–0EFFFF
070000–077FFF
SA22
001111xxx
64/32
0F0000–0FFFFF
078000–07FFFF
SA23
010000xxx
64/32
100000–10FFFF
080000–087FFF
SA24
010001xxx
64/32
110000–11FFFF
088000–08FFFF
SA25
010010xxx
64/32
120000–12FFFF
090000–097FFF
SA26
010011xxx
64/32
130000–13FFFF
098000–09FFFF
SA27
010100xxx
64/32
140000–14FFFF
0A0000–0A7FFF
SA28
010101xxx
64/32
150000–15FFFF
0A8000–0AFFFF
SA29
010110xxx
64/32
160000–16FFFF
0B0000–0B7FFF
SA30
010111xxx
64/32
170000–17FFFF
0B8000–0BFFFF
SA31
011000xxx
64/32
180000–18FFFF
0C0000–0C7FFF
SA32
011001xxx
64/32
190000–19FFFF
0C8000–0CFFFF
SA33
011010xxx
64/32
1A0000–1AFFFF
0D0000–0D7FFF
SA34
011011xxx
64/32
1B0000–1BFFFF
0D8000–0DFFFF
SA35
011100xxx
64/32
1C0000–1CFFFF
0E0000–0E7FFF
SA36
011101xxx
64/32
1D0000–1DFFFF
0E8000–0EFFFF
SA37
011110xxx
64/32
1E0000–1EFFFF
0F0000–0F7FFF
SA38
011111xxx
64/32
1F0000–1FFFFF
0F8000–0FFFFF
SA39
100000xxx
64/32
200000–20FFFF
100000–107FFF
Sector
A20 – A12
Sector Size
(Kbytes / Kwords)
SA0
000000000
SA1
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
6
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
SA40
100001xxx
64/32
210000–21FFFF
108000–10FFFF
SA41
100010xxx
64/32
220000–22FFFF
110000–117FFF
SA42
100011xxx
64/32
230000–23FFFF
118000–11FFFF
SA43
100100xxx
64/32
240000–24FFFF
120000–127FFF
SA44
100101xxx
64/32
250000–25FFFF
128000–12FFFF
SA45
100110xxx
64/32
260000–26FFFF
130000–137FFF
SA46
100111xxx
64/32
270000–27FFFF
138000–13FFFF
SA47
101000xxx
64/32
280000–28FFFF
140000–147FFF
SA48
101001xxx
64/32
290000–29FFFF
148000–14FFFF
SA49
101010xxx
64/32
2A0000–2AFFFF
150000–157FFF
SA50
101011xxx
64/32
2B0000–2BFFFF
158000–15FFFF
SA51
101100xxx
64/32
2C0000–2CFFFF
160000–167FFF
SA52
101101xxx
64/32
2D0000–2DFFFF
168000–16FFFF
SA53
101110xxx
64/32
2E0000–2EFFFF
170000–177FFF
SA54
101111xxx
64/32
2F0000–2FFFFF
178000–17FFFF
SA55
110000xxx
64/32
300000–30FFFF
180000–187FFF
SA56
110001xxx
64/32
310000–31FFFF
188000–18FFFF
SA57
110010xxx
64/32
320000–32FFFF
190000–197FFF
SA58
110011xxx
64/32
330000–33FFFF
198000–19FFFF
SA59
110100xxx
64/32
340000–34FFFF
1A0000–1A7FFF
SA60
110101xxx
64/32
350000–35FFFF
1A8000–1AFFFF
SA61
110110xxx
64/32
360000–36FFFF
1B0000–1B7FFF
SA62
110111xxx
64/32
370000–37FFFF
1B8000–1BFFFF
SA63
111000xxx
64/32
380000–38FFFF
1C0000–1C7FFF
SA64
111001xxx
64/32
390000–39FFFF
1C8000–1CFFFF
SA65
111010xxx
64/32
3A0000–3AFFFF
1D0000–1D7FFF
SA66
111011xxx
64/32
3B0000–3BFFFF
1D8000–1DFFFF
SA67
111100xxx
64/32
3C0000–3CFFFF
1E0000–1E7FFF
SA68
111101xxx
64/32
3D0000–3DFFFF
1E8000–1EFFFF
SA69
111110xxx
64/32
3E0000–3EFFFF
1F0000–1F7FFF
SA70
111111xxx
64/32
3F0000–3FFFFF
1F8000–1FFFFF
Note: The address bus is A20:A-1 in byte mode where BYTE# = VIL or A20:A0 in word mode where
BYTE# = VIH
B
B
B
B
Table 2D. Bottom Boot Security Sector Address (EN29LV320CB)
Sector Address
A20 ~ A12
Sector Size
(bytes / words)
000000000
256 / 128
Address Range (h)
Byte mode (x8)
000000
0000FF
Address Range (h)
Word Mode (x16)
000000
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
7
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
00007F
www.eonssi.com
EN29LV320C
Table 3. PRODUCT SELECTOR GUIDE
Product Number
EN29LV320C
Speed
-70
Max Access Time, ns (tacc)
70
Max CE# Access, ns (tce)
70
Max OE# Access, ns (toe)
30
B
B
B
B
B
B
BLOCK DIAGRAM
RY/BY#
Vcc
Vss
DQ0-DQ15 (A-1)
Block Protect Switches
Erase Voltage Generator
Input/Output Buffers
State
Control
WE#
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
Vcc Detector
Timer
Address Latch
STB
STB
Data Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A20
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
8
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
TABLE 4. OPERATING MODES
32M FLASH USER MODE TABLE
Operation
A0A20
CE#
OE#
WE#
RESET#
WP#/ACC
Read
Write
L
L
L
H
H
L
H
H
L/H
(Note 1)
AIN
AIN
Accelerated
Program
L
H
L
H
VHH
AIN
DQ8-DQ15
BYTE#
BYTE#
= VIH
= VIL
DOUT
DQ8DQ14=
DIN
High-Z,
DQ15 =
DIN
A-1
DQ0DQ7
B
B
B
B
B
B
B
DOUT
DIN
B
B
B
B
B
B
DIN
B
B
B
B
B
B
B
B
B
B
Vcc
±0.3V
L
X
X
X
Vcc±0.3V
H
X
High-Z
High-Z
High-Z
H
X
H
X
H
L
L/H
L/H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Sector Group
Protect
L
H
L
VID
(Note 2)
X
X
Chip Unprotect
L
H
L
VID
X
X
SA,
A6=L,
A1=H,
A0=L
SA,
A6=H,
A1=H,
A0=L
(Note 2)
X
X
Temporary
Sector
Unprotect
X
X
X
VID
AIN
(Note 2)
(Note 2)
High-Z
CMOS Standby
Output Disable
Hardware Reset
L/H
B
B
B
B
(Note 1)
B
(Note 1)
B
B
B
L=logic low= VIL, H=Logic High= VIH, VID =VHH = 9 ± 0.5V = 8.5-9.5V, X=Don’t Care (either L or H, but not floating ),
SA=Sector Addresses, DIN=Data In, DOUT=Data Out, AIN=Address In
B
B
B
B
B
B
B
B
B
B
B
B
B
Notes:
1. If WP#/ACC = VIL , the two outermost boot sectors remain protected. If WP# / ACC = VIH, the outermost boot
sector protection depends on whether they were last protected or unprotected. If WP#/ACC = VHH, all sectors will
be unprotected.
B
B
B
B
B
B
2. Please refer to “Sector Group Protection & Chip Unprotection”, Flowchart 7a and Flowchart 7b.
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
9
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
TABLE 5. Autoselect Codes (Using High Voltage, VID)
B
B
32M FLASH MANUFACTURER/DEVICE ID TABLE
CE#
OE#
WE#
A20
to
A12
A11
to
A10
A9
Manufacturer ID:
Eon
L
L
H
X
X
VID
Device ID
Word
L
L
H
(top boot
sector)
Byte
L
L
H
Device ID
Word
L
L
H
Description
2
A8
P
P
A7
A6
A5
to
A2
A1
A0
DQ8
to
DQ15
X
L
X
L
L
X
1
(bottom boot
sector)
H
1Ch
P
P
B
B
L
Byte
L
L
H
L
L
H
7Fh
X
X
VID
X
X
L
X
L
H
X
X
VID
X
X
L
X
L
H
SA
X
VID
X
X
L
X
H
L
B
B
B
B
22h
F6h
X
F6h
22h
F9h
X
F9h
01h
X
Sector Protection
Verification
B
B
DQ7 to DQ0
X
(Protected)
00h
(Unprotected)
32M FLASH SECURED SILICON SECTOR TABLE3
Description
Secured Silicon
4
Sector Lock
Secured Silicon
Sector Lock Bit
Verification
4
(DQ0)
CE#
OE#
L
V ID
B
L
WE#
B
L
H
A21
to
A12
A11
to
A10
A9
X
X
V ID
X
X
2
P
P
B
B
V ID
B
B
A8
A7
A6
A5
to
A2
A1
A0
DQ8
to
DQ15
DQ7
to
DQ0
X
X
L
X
H
L
X
X
X
X1h
(Locked)
X0h
(Unlocked)
X
X
L
X
H
L
L=logic low= VIL, H=Logic High= VIH, VID = 9 0.5V, X=Don’t Care (either L or H, but not floating!), SA=Sector
Addresses
Note:
1. A8 = H is recommended for Manufacturing ID check. If a manufacturing ID is read with A8=L, the chip will output
a configuration code 7Fh.
2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect
Mode.
3. 32M FLASH SECURED SILICON SECTOR TABLE is valid only in Secured Silicon Sector.
4.
AC Waveform for Secured Silicon Sector Lock / Verification Operations Timings
VID
Vcc
0V
0V
tVIDR
tVIDR
A6, A1, A0
Valid
Valid
Valid
Valid
Verify
>0.4 s
>1 s
Lock : 150 s
VID
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
10
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
USER MODE DEFINITIONS
Word / Byte Configuration
The signal set on the BYTE# pin controls whether the device data I/O pins DQ15-DQ0 operate in the
byte or word configuration. When the BYTE# Pin is set at logic ‘1’, then the device is in word
configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.
On the other hand, if the BYTE# Pin is set at logic ‘0’, then the device is in byte configuration, and only
data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14 are
tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
Standby Mode
The EN29LV320C has a CMOS-compatible standby mode, which reduces the current to < 1µA (typical).
It is placed in CMOS-compatible standby when the CE# pin is at VCC ± 0.5. RESET# and BYTE# pin
must also be at CMOS input levels. The device also has a TTL-compatible standby mode, which
reduces the maximum VCC current to < 1mA. It is placed in TTL-compatible standby when the CE# pin
is at VIH. When in standby modes, the outputs are in a high-impedance state independent of the OE#
input.
B
B
B
B
B
B
B
Automatic Sleep Mode
The EN29LV320C has an automatic sleep mode, which minimizes power consumption. The devices
will enter this mode automatically when the states of address bus remain stable for tacc + 30ns. ICC4 in
the DC Characteristics table shows the current specification. With standard access times, the device
will output new data when addresses change.
Read Mode
The device is automatically set to reading array data after device power-up or hardware reset. No
commands are required to retrieve data. The device is also ready to read array data after completing an
Embedded Program or Embedded Erase algorithm.
After the device accepts a Sector Erase Suspend command, the device enters the Sector Erase
Suspend mode. The system can read array data using the standard read timings, except that if it reads
at an address within erase-suspended sectors, the device outputs status data. After completing a
programming operation in the Sector Erase Suspend mode, the system may once again read array
data with the same exception. See “Sector Erase Suspend/Resume Commands” for more additional
information.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes
high or while in the autoselect mode. See the “Reset Command” for additional details.
Output Disable Mode
When the OE# pin is at a logic high level (VIH), the output from the EN29LV320C is disabled. The
output pins are placed in a high impedance state.
B
B
Autoselect Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ15–DQ0. This mode is primarily intended for programming
equipment to automatically match a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed in-system through the command
register.
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
11
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
When using programming equipment, the autoselect mode requires VID (8.5 V to 9.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In addition, when
verifying sector protection, the sector address must appear on the appropriate highest order address
bits. Refer to the corresponding Sector Address Tables. The “Command Definitions” table shows the
remaining address bits that are don’t-care. When all necessary bits have been set as required, the
programming equipment may then read the corresponding identifier code on DQ15–DQ0.
B
B
To access the autoselect codes in-system; the host system can issue the autoselect command via the
command register, as shown in the Command Definitions table. This method does not require VID. See
“Command Definitions” for details on using the autoselect mode.
B
B
Writing Command Sequences
To write a command or command sequence to program data to the device or erase data, the system
has to drive WE# and CE# to VIL, and OE# to VIH.
B
B
B
For program operations, the BYTE# pin determines whether the device accepts program data in bytes
or words. An erase operation can erase one sector or the whole chip.
The system can also read the autoselect codes by entering the autoselect mode, which need the
autoselect command sequence to be written. Please refer to the “Command Definitions” for all the
available commands.
RESET#: Hardware Reset
When RESET# is driven low for tRP, all output pins are tristates. All commands written in the internal
state machine are reset to reading array data.
B
B
Please refer to timing diagram for RESET# pin in “AC Characteristics”.
Sector Group Protection & Chip Unprotection
The hardware sector group protection feature disables both program and erase operations in any
sector. The hardware chip unprotection feature re-enables both program and erase operations in
previously protected sectors. A sector group implies three or four adjacent sectors that would be
protected at the same time. Please see the following tables which show the organization of sector
groups.
There are two methods to enable this hardware protection circuitry. The first one requires only that the
RESET# pin be at VID and then standard microprocessor timings can be used to enable or disable this
feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings.
When doing Chip Unprotect, all the unprotected sector groups must be protected prior to any unprotect
write cycle.
The second method is for programming equipment. This method requires VID to be applied to both
OE# and A9 pins and non-standard microprocessor timings are used. This method is described in a
separate document named EN29LV320C Supplement, which can be obtained by contacting a
representative of Eon Silicon Solution, Inc.
U
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
12
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
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EN29LV320C
TABLE 6. Top Boot Sector/Sector Group Organization Table (EN29LV320CT) for
(Un)Protection
Sector Group
Sectors
A20-A12
Sector Group Size
SG 0
SG 1
SG 2
SG 3
SG 4
SG 5
SG 6
SG 7
SG 8
SG 9
SG10
SG11
SG12
SG13
SG14
SA 0-SA 3
SA 4-SA 7
SA 8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
SA32-SA35
SA36-SA39
SA40-SA43
SA44-SA47
SA48-SA51
SA52-SA55
SA56-SA59
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
SG15
SA60-SA62
SG16
SG17
SG18
SG19
SG20
SG21
SG22
SG23
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
0000XXXXX
0001XXXXX
0010XXXXX
0011XXXXX
0100XXXXX
0101XXXXX
0110XXXXX
0111XXXXX
1000XXXXX
1001XXXXX
1010XXXXX
1011XXXXX
1100XXXXX
1101XXXXX
1110XXXXX
111100XXX
111101XXX
111110XXX
111111000
111111001
111111010
111111011
111111100
111111101
111111110
111111111
64 Kbytes x 3
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
TABLE 7. Bottom Boot Sector/Sector Group Organization Table (EN29LV320CB)
for (Un)Protection
Sector Group
Sectors
A20-A12
Sector Group Size
SG23
SG22
SG21
SG20
SG19
SG18
SG17
SG16
SG15
SG14
SG13
SG12
SG11
SG10
SG 9
SA70-SA67
SA66-SA63
SA62-SA59
SA58-SA55
SA54-SA51
SA50-SA47
SA46-SA43
SA42-SA39
SA38-SA35
SA34-SA31
SA30-SA27
SA26-SA23
SA22-SA19
SA18-SA15
SA14-SA11
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
64 Kbytes x 4
SG 8
SA10-SA 8
SG
SG
SG
SG
SG
SG
SG
SG
SA
SA
SA
SA
SA
SA
SA
SA
1111XXXXX
1110XXXXX
1101XXXXX
1100XXXXX
1011XXXXX
1010XXXXX
1001XXXXX
1000XXXXX
0111XXXXX
0110XXXXX
0101XXXXX
0100XXXXX
0011XXXXX
0010XXXXX
0001XXXXX
000011XXX
000010XXX
000001XXX
000000111
000000110
000000101
000000100
000000011
000000010
000000001
000000000
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
64 Kbytes x 3
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
8 Kbytes
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
13
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
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EN29LV320C
Write Protect / Accelerated Program (WP# / ACC)
The WP#/ACC pin provides two functions. The Write Protect (WP#) function provides a hardware method of protecting the outermost two 8K-byte Boot Sector. The ACC function allows faster manufacturing
throughput at the factory, using an external high voltage.
When WP#/ACC is Low, the device protects the outermost two 8K-byte Boot Sector; no matter the
sectors are protected or unprotected using the method described in “Sector/Sector Group Protection &
Chip Unprotection”, Program and Erase operations in these sectors are ignored.
When WP#/ACC is High, the device reverts to the previous protection status of the outermost two 8Kbyte boot sector. Program and Erase operations can now modify the data in the two outermost 8K-byte
Boot Sector unless the sector is protected using Sector Protection.
When WP#/ACC is raised to VHH the memory automatically enters the Accelerated Program mode, this
mode permit the system to skip the normal command unlock sequences and program byte/word
locations directly to reduces the time required for program operation. When WP#/ACC returns to VIH or
VIL, normal operation resumes. The transitions from VIH or VIL to VHH and from VHH to VIH or VIL must be
slower than tBVHHB, see Figure 11.
Note that the WP#/ACC pin must not be left floating or unconnected. In addition, WP#/ACC pin
must not be at VHH for operations other than accelerated programming. It could cause the device to be
damaged.
Never raise this pin to VHH from any mode except Read mode. Otherwise the memory may be left in an
indeterminate state.
A 0.1µF capacitor should be connected between the WP#/ACC pin and the VSS Ground pin to
decouple the current surges from the power supply. The PCB track widths must be sufficient to carry
the currents required during Accelerated Program mode.
Temporary Sector Unprotect
Start
This feature allows temporary unprotection of previously protected
sector groups to change data while in-system. The Temporary
Sector Unprotect mode is activated by setting the RESET# pin to
VBIDB. During this mode, formerly protected sectors can be
programmed or erased by simply selecting the sector addresses.
Once VBIDB is removed from the RESET# pin, all the previously
protected sectors are protected again.
See accompanying
flowchart and figure 10 for more timing details.
Notes:
1. All protected sectors are unprotected. (If
WP#/ACC=VIL, outermost boot sectors will remain
protected.)
2. Previously protected sectors are protected again.
B
Reset#=VID (note 1)
B
B
B
B
Perform Erase or Program
Operations
RESET#=VIH
B
B
Temporary Sector Unprotect
Completed (note 2)
B
B
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
14
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
COMMON FLASH INTERFACE (CFI)
The common flash interface (CFI) specification outlines device and host systems software
interrogation handshake, which allows specific vendor-specified software algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC IDindependent, and forward- and backward-compatible for the specified flash device families. Flash
vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address 55h in word mode (or address AAh in byte mode), any time the device is ready to read
array data.
The system can read CFI information at the addresses given in Tables 5-8.In word mode, the upper
address bits (A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the
reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The
device enters the CFI query mode and the system can read CFI data at the addresses given in
Tables 5–8. The system must write the reset command to return the device to the autoselect mode.
Table 8. CFI Query Identification String
Addresses
(Word Mode)
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
Adresses
(Byte Mode)
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
Data
0051h
0052h
0059h
0002h
0000h
0040h
0000h
0000h
0000h
0000h
0000h
Description
Query Unique ASCII string “QRY”
Primary OEM Command Set
Address for Primary Extended Table
Alternate OEM Command set (00h = none exists)
Address for Alternate OEM Extended Table (00h = none
exists)
Table 9. System Interface String
Addresses
(Word Mode)
Addresses
(Byte Mode)
1Bh
36h
1Ch
38h
1Dh
1Eh
1Fh
3Ah
3Ch
3Eh
20h
40h
21h
22h
23h
24h
25h
42h
44h
46h
48h
4Ah
26h
4Ch
Data
0027h
0036h
0000h
0000h
0004h
0000h
000Ah
0000h
0005h
0000h
0004h
0000h
Description
Vcc Min (write/erase)
DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt
Vcc Max (write/erase)
DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt
Vpp Min. voltage (00h = no Vpp pin present)
Vpp Max. voltage (00h = no Vpp pin present)
Typical timeout per single byte/word write 2N μS
Typical timeout for Min, size buffer write 2N μS (00h = not
supported)
Typical timeout per individual block erase 2N ms
Typical timeout for full chip erase 2N ms (00h = not supported)
Max. timeout for byte/word write 2N times typical
Max. timeout for buffer write 2N times typical
Max. timeout per individual block erase 2N times typical
Max timeout for full chip erase 2N times typical (00h = not
supported)
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
15
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
Table 10. Device Geometry Definition
Addresses
(Word mode)
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
Addresses
(Byte Mode)
4Eh
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
Data
0016h
0002h
0000h
0000h
0000h
0002h
0007h
0000h
0020h
0000h
003Eh
0000h
0000h
0001h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Description
Device Size = 2N bytes
Flash Device Interface description (refer to CFI publication
100)
Max. number of byte in multi-byte write = 2N
(00h = not supported)
Number of Erase Block Regions within device
P
P
P
P
Erase Block Region 1 Information
(refer to the CFI specification of CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
Table 11. Primary Vendor-specific Extended Query
Addresses
(Word Mode)
40h
41h
42h
43h
44h
Addresses
(Byte Mode)
80h
82h
84h
86h
88h
Data
0050h
0052h
0049h
0031h
0031h
45h
8Ah
0000h
46h
8Ch
0002h
47h
8Eh
0004h
48h
90h
0001h
49h
92h
0004h
4Ah
94h
0000h
4Bh
96h
0000h
4Ch
98h
0000h
4Dh
9Ah
00A5h
4Eh
9Ch
00B5h
4Fh
9Eh
0002h/
0003h
Description
Query-unique ASCII string “PRI”
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required, 1 = Not Required
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
Simultaneous Operation
00 = Not Supported, 01 = Supported
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
Minimum ACC (Acceleration) Supply Voltage
00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV
Maximum ACC (Acceleration) Supply Voltage
00 = Not Supported, DQ7-DQ4 : Volts, DQ3-DQ0 : 100mV
Top/Bottom Boot Sector Identifier
02h = Bottom Boot, 03h = Top Boot
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
16
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
Hardware Data protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by false system level signals during Vcc power up and power down transitions, or
from system noise.
SECURED SILICON SECTOR
The EN29LV320C features an OTP memory region where the system may access through a command
sequence to create a permanent part identification as so called Electronic Serial Number (ESN) in the
device. Once this region is programmed and then locked by writing the Secured Silicon Sector Lock
command (refer to Table 5 on page 10), any further modification in the region is impossible. The
secured silicon sector is 128 words in length, and the Secured Silicon Sector Lock Bit (DQ0) is used to
indicate whether the Secured Silicon Sector is locked or not.
The system accesses the Secured Silicon Sector through a command sequence (refer to “Enter
Secured Silicon/ Exit Secured Silicon Sector command Sequence which are in Table 12 on page 18).
After the system has written the Enter Secured Silicon Sector command sequence, it may read the
Secured Silicon Sector by using the address normally occupied by the last sector SA70 (for
EN29LV320CT) or first sector SA0 (for EN29LV320CB). Once entry the Secured Silicon Sector the
operation of boot sectors and main sectors are disabled, the system must write Exit Secured Silicon
Sector command sequence to return to read and write within the remainder of the array. This mode of
operation continues until the system issues the Exit Secured Silicon Sector command sequence, or
until power is removed from the device. On power-up, or following a hardware reset, the device reverts
to sending command to sector SA0.
Low VCC Write Inhibit
B
B
When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc
power up and power down. The command register and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The system must
provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than
VLKO.
B
B
B
B
B
B
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH, or WE# = VIH. To initiate a write
cycle, CE# and WE# must be a logical zero while OE# is a logical one. If CE#, WE#, and OE# are all
logical zero (not recommended usage), it will be considered a read.
B
B
B
B
B
B
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even with
CE# = VIL, WE#= VIL and OE# = VIH, the device will not accept commands on the rising edge of WE#.
B
B
B
B
B
B
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
17
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
COMMAND DEFINITIONS
The operations of the device are selected by one or more commands written into the command
register. Commands are made up of data sequences written at specific addresses via the command
register. The sequences for the specified operation are defined in the Command Definitions table
(Table 9). Incorrect addresses, incorrect data values or improper sequences will reset the device to
Read Mode.
Table 12. EN29LV320C Command Definitions
Cycles
Bus Cycles
Command
Sequence
st
1 Cycle
P
P
Read
1
RA
RD
Reset
1
xxx
F0
Word
Manufacturer ID
555
4
Autoselect
Byte
Device ID
Top Boot
Word
Device ID
Bottom Boot
Word
Byte
Byte
AAA
555
4
Word
Program
Byte
Byte
Word
Byte
AAA
AA
Sector Erase Suspend
1
xxx
B0
Sector Erase Resume
1
xxx
30
CFI Query
Enter Secured
Silicon Sector
Exit Secured
Silicon Sector
Byte
Word
Byte
Word
Byte
1
3
4
55
AA
555
AAA
555
AAA
90
AAA
555
555
2AA
555
90
555
P
000
100
000
200
x01
7F
1C
7F
1C
22F6
x02
F6
x01
22F9
x02
F9
90
00
01
00
01
A0
PA
PD
AAA
55
P
(SA)
X02
(SA)
X04
555
55
2AA
90
AAA
5th Cycle
P
P
555
55
55
AAA
555
AAA
555
80
80
AAA
555
AAA
2AA
AA
AA
2AA
555
2AA
555
P
P
AA
555
2AA
555
55
555
AA
A
10
55
SA
30
98
AA
6th Cycle
AAA
2AA
AA
555
AAA
Word
55
555
6
Sector Erase
2AA
555
555
6
555
P
555
2AA
AA
P
AAA
55
4th Cycle
3 Cycle
55
AA
555
rd
555
555
AAA
Word
Chip Erase
AA
AAA
4
Cycle
2AA
AA
555
Byte
P
555
AAA
Word
Sector Protect
Verify
P
AA
555
4
2
2AA
AAA
4
nd
55
55
555
AAA
555
AAA
88
90
xxx
xxx
00
00
Address and Data values indicated are in hex. Unless specified, all bus cycles are write cycles
RA = Read Address: address of the memory location to be read. This is a read cycle.
RD = Read Data: data read from location RA during Read operation. This is a read cycle.
PA = Program Address: address of the memory location to be programmed. X = Don’t-Care
PD = Program Data: data to be programmed at location PA
SA = Sector Address: address of the Sector to be erased or verified. Address bits A20-A12 uniquely select any Sector.
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
18
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
Reading Array Data
The device is automatically set to reading array data after power up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
Following a Sector Erase Suspend command, Sector Erase Suspend mode is entered. The system can
read array data using the standard read timings from sectors other than the one which is being erasesuspended. If the system reads at an address within erase-suspended sectors, the device outputs
status data. After completing a programming operation in the Sector Erase Suspend mode, the system
may once again read array data with the same exception.
The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high
during an active program or erase operation or while in the autoselect mode. See next section for
details on Reset.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’tcare for this command.
The reset command may be written between the cycle sequences in an erase command sequence
before erasing begins. This resets the device to reading array data. Once erasure begins, however, the
device ignores reset commands until the operation is complete. The reset command may be written
between the sequence cycles in a program command sequence before programming begins. This
resets the device to reading array data (also applies to programming in Sector Erase Suspend mode).
Once programming begins, however, the device ignores reset commands until the operation is
complete.
The reset command may be written between the cycle sequences in an autoselect command sequence.
Once in the autoselect mode, the reset command must be written to return to reading array data.
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to
reading array data (also applies in Sector Erase Suspend mode).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices ID
codes, and determine whether or not a sector (group) is protected. The Command Definitions table
shows the address and data requirements. This is an alternative to the method that requires VID on
address bit A9 and is intended for commercial programmers.
B
B
Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.
Autoselect mode is then entered and the system may read at addresses shown in Table 9 any number
of times, without needing another command sequence.
The system must write the reset command to exit the autoselect mode and return to reading array
data.
Word / Byte Programming Command
The device can be programmed by byte or by word, depending on the state of the BYTE# Pin.
Programming the EN29LV320C is performed by using a four-bus-cycle operation (two unlock write
cycles followed by the Program Setup command and Program Data Write cycle). When the program
command is executed, no additional CPU controls or timings are necessary. An internal timer
terminates the program operation automatically. Address is latched on the falling edge of CE# or WE#,
whichever is last; data is latched on the rising edge of CE# or WE#, whichever is first.
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
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or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
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EN29LV320C
Any commands written to the device during the program operation are ignored. Programming status
can be checked by sampling data on DQ7 (DATA# polling) or on DQ6 (toggle bit). When the program
operation is successfully completed, the device returns to read mode and the user can read the data
programmed to the device at that address. Note that data can not be programmed from a “0” to a “1”.
Attempting to do so may halt the operation and set DQ5 to “1”, or cause the Data# Polling algorithm to
indicate the operation was successful. However, a succeeding read will show that the data is still “0”.
Only erase operations can convert a “0” to a “1”. When programming time limit is exceeded, DQ5 will
produce a logical “1” and a Reset command can return the device to Read mode.
Programming is allowed in any sequence across sector boundaries.
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by
the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not
require the system to preprogram prior to erase. The Embedded Erase algorithm automatically
preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations. The Command
Definitions table shows the address and data requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.
The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and addresses are no longer latched.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing
two un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed
by the address of the sector to be erased, and the sector erase command. The Command Definitions
table shows the address and data requirements for the sector erase command sequence.
Once the sector erase operation has begun, only the Sector Erase Suspend command is valid. All
other commands are ignored. If there are several sectors to be erased, Sector Erase Command
sequences must be issued for each sector. That is, only a sector address can be specified for each
Sector Erase command. Users must issue another Sector Erase command for the next sector to be
erased after the previous one is completed.
When the Embedded Erase algorithm is completed, the device returns to reading array data and
addresses are no longer latched. The system can determine the status of the erase operation by using
DQ7, DQ6, or DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4
illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the
“AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for
timing waveforms.
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
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or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
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EN29LV320C
Sector Erase Suspend / Resume Command
The Sector Erase Suspend command allows the system to interrupt a sector erase operation and then
read data from, or program data to, any sector not selected for erasure. This command is valid only
during the sector erase operation. The Sector Erase Suspend command is ignored if written during the
chip erase operation or Embedded Program algorithm. Addresses are don’t-cares when writing the
Sector Erase Suspend command.
When the Sector Erase Suspend command is written during a sector erase operation, the device
requires a maximum of 20 µs to suspend the erase operation.
After the erase operation has been suspended, the system can read array data from or program data to
any sector not selected for erasure. Normal read and write timings and command definitions apply.
Please note that Autoselect command sequence can not be accepted during Sector Erase
Suspend.
Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erasesuspended. See “Write Operation Status” for information on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data
within non-suspended sectors. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for
more information. The Autoselect command is not supported during Sector Erase Suspend Mode.
The system must write the Sector Erase Resume command (address bits are don’t-care) to exit the
sector erase suspend mode and continue the sector erase operation. Further writes of the Resume
command are ignored. Another Sector Erase Suspend command can be written after the device has
resumed erasing.
WRITE OPERATION STATUS
DQ7: DATA# Polling
The EN29LV320C provides DATA# polling on DQ7 to indicate the status of the embedded operations.
The DATA# Polling feature is active during the Word/Byte Programming, Sector Erase, Chip Erase, and
Sector Erase Suspend. (See Table 10)
When the embedded programming is in progress, an attempt to read the device will produce the
complement of the data written to DQ7. Upon the completion of the programming operation, an attempt
to read the device will produce the true data written to DQ7. DATA# polling is valid after the rising edge
of the fourth WE# or CE# pulse in the four-cycle sequence for program.
When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the DQ7
output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7 output
during the read cycles. For Chip Erase or Sector Erase, DATA# polling is valid after the rising edge of
the last WE# or CE# pulse in the six-cycle sequence.
DATA# Polling must be performed at any address within a sector that is being programmed or erased
and not a protected sector. Otherwise, DATA# polling may give an inaccurate result if the address used
is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the
output enable (OE#) is low. This means that the device is driving status information on DQ7 at one
instant of time and valid data at the next instant of time. Depending on the time the system samples the
DQ7 output, it may read the status of valid data. Even if the device has completed the embedded
operation and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid data on
DQ0-DQ7 should be read on the subsequent read attempts.
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
21
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
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EN29LV320C
The flowchart for DATA# Polling (DQ7) is shown on Flowchart 5. The DATA# Polling (DQ7) timing
diagram is shown in Figure 6.
RY/BY#: Ready/Busy Status output
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or completed. The RY/BY# status is valid after the rising edge of the final WE# pulse in the
command sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together
in parallel with a pull-up resistor to Vcc.
In the output-low period, signifying Busy, the device is actively erasing or programming. This includes
programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is
ready to read array data (including during the Erase Suspend mode), or is in the standby mode.
DQ6: Toggle Bit I
The EN29LV320C provides a “Toggle Bit” on DQ6 to indicate the status of the embedded programming
and erase operations. (See Table 10)
During an embedded Program or Erase operation, successive attempts to read data from the device at
any address (by active OE# or CE#) will result in DQ6 toggling between “zero” and “one”. Once the
embedded Program or Erase operation is completed, DQ6 will stop toggling and valid data will be read
on the next successive attempts. During Programming, the Toggle Bit is valid after the rising edge of
the fourth WE# pulse in the four-cycle sequence. During Erase operation, the Toggle Bit is valid after
the rising edge of the sixth WE# pulse for sector erase or chip erase.
In embedded programming, if the sector being written to is protected, DQ6 will toggles for about 2 μs,
then stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all
selected sectors are protected, DQ6 will toggle for about 100 μs. The chip will then return to the read
mode without changing data in all protected sectors.
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is shown
in Figure 7.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or
erase cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the
device has successfully completed its operation and has returned to read mode, the user must check
again to see if the DQ6 is toggling after detecting a “1” on DQ5.
The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition,
the device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a
“1.” Under both these conditions, the system must issue the reset command to return the device to
reading array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the output on DQ3 can be checked to determine
whether or not an erase operation has begun. (The sector erase timer does not apply to the chip erase
command.) When sector erase starts, DQ3 switches from “0” to “1”. This device does not support
multiple sector erase (continuous sector erase) command sequences so it is not very meaningful since
it immediately shows as a “1” after the first 30h command. Future devices may support this feature.
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
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EN29LV320C
DQ2: Erase Toggle Bit II
The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended.
Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2
toggles when the system reads at addresses within those sectors that have been selected for erasure.
(The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether
the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected
for erasure. Thus, both status bits are required for sector and mode information. Refer to the following
table to compare outputs for DQ2 and DQ6.
Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm.
See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit
timing diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical
form.
Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle
bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, a system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
However, after the initial two read cycles, the system determines that the toggle bit is still toggling. And
the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the
system should then determine again whether the toggle bit is toggling, since the toggle bit may have
stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has
successfully completed the program or erase operation. If it is still toggling, the device did not complete
the operation successfully, and the system must write the reset command to return to reading array
data.
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
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or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
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EN29LV320C
Table 13. Write Operation Status
Operation
Standard
Mode
Erase
Suspend
Mode
DQ7
DQ6
DQ5
DQ3
DQ2
RY/BY#
Embedded Program
Algorithm
DQ7#
Toggle
0
N/A
No
toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
1
No
Toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
DQ7#
Toggle
0
N/A
N/A
0
Reading within Erase
Suspended Sector
Reading within Non-Erase
Suspended Sector
Erase-Suspend Program
Table 14. Status Register Bits
DQ
Name
Logic Level
‘1’
7
DATA#
POLLING
‘0’
DQ7
DQ7#
‘-1-0-1-0-1-0-1-’
6
TOGGLE BIT
DQ6
‘-1-1-1-1-1-1-1-‘
5
3
2
TIME OUT BIT
ERASE TIME
OUT BIT
TOGGLE BIT
Definition
Erase Complete or erased sector in Sector Erase
Suspend
Erase On-Going
Program Complete or data of non-erased sector
during Sector Erase Suspend
Program On-Going
Erase or Program On-going
Read during Sector Erase Suspend
Erase Complete
‘1’
Program or Erase Error
‘0’
Program or Erase On-going
‘1’
Erase operation start
‘0’
Erase timeout period on-going
‘-1-0-1-0-1-0-1-’
DQ2
Chip Erase, Sector Erase or Read within EraseSuspended sector. (When DQ5=1, Erase Error due
to currently addressed Sector or Program on
Erase-Suspended sector
Read on addresses of non Erase-Suspend sectors
Notes:
DQ7: DATA# Polling: indicates the P/E status check during Program or Erase, and on completion before checking bits DQ5 for
Program or Erase Success.
DQ6: Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged. Successive
reads output complementary data on DQ6 while programming or Erase operation are on-going.
DQ5: Time Out Bit: set to “1” if failure in programming or erase
DQ3: Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).
DQ2: Toggle Bit: indicates the Erase status and allows identification of the erased Sector.
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or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
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EN29LV320C
EMBEDDED ALGORITHMS
Flowchart 1. Embedded Program
START
Write Program
Command Sequence
(shown below)
Data# Poll Device
Verify Data?
No
Yes
Increment
Address
Last
No
Address?
Yes
Programming Done
Flowchart 2. Embedded Program Command Sequence
(See the Command Definitions section for more information.)
555H / AAH
2AAH / 55H
555H / A0H
PROGRAM ADDRESS / PROGRAM DATA
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EN29LV320C
Flowchart 3. Embedded Erase
START
Write Erase
Command Sequence
Data Poll from
System or Toggle Bit
successfully
completed
Data =FFh?
No
Yes
Erase Done
Flowchart 4. Embedded Erase Command Sequence
(See the Command Definitions section for more information.)
Chip Erase
Sector Erase
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
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EN29LV320C
Flowchart 5. DATA# Polling
Algorithm
Start
Read Data
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read Data (1)
Notes:
(1) This second read is necessary in case the
first read was done at the exact instant when
the status data was in transition.
Yes
DQ7 = Data?
No
Fail
Pass
Start
Flowchart 6. Toggle Bit Algorithm
Read Data twice
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Data twice (2)
Notes:
(2) This second set of reads is necessary in
case the first set of reads was done at the
exact instant when the status data was in
transition.
No
DQ6 = Toggle?
Yes
Fail
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or modifications due to changes in technical specifications.
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Pass
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EN29LV320C
Flowchart 7a. In-System Sector Group Protect Flowchart
START
PLSCNT = 1
RESET# = VID
Wait 1 μs
No
Temporary Sector
Unprotect Mode
First Write
Cycle =
60h?
Yes
Set up sector
group address
To Protect: Write 60h to
sector addr with
A6 = 0, A1 = 1, A0 = 0
Wait 150 μs
To Verify: Write 40h to
sector group address with
A6 = 0, A1 = 1, A0 = 0
Increment
PLSCNT
Reset
PLSCNT = 1
Wait 0.4 μs
Read from sector
address with
A6 = 0, A1 = 1, A0 = 0
No
PLSCNT = 25?
No
Data = 01h?
Yes
Yes
Device failed
Protect another
sector?
Yes
No
Remove VID
from RESET#
Write reset
command
Sector Group Protect
Algorithm
Sector Protect
complete
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or modifications due to changes in technical specifications.
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EN29LV320C
Flowchart 7b. In-System Chip Unprotect Flowchart
START
PLSCNT = 1
Protect all sector
groups: The
indicated portion of
the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector unprotect
address (see
Diagram 7a.)
RESET# = VID
Wait 1 μs
No
Temporary Sector
Unprotect Mode
First Write
Cycle = 60h?
Yes
No
All sectors
protected?
Yes
Set up first sector
address
Chip Unprotect: Write 60H to sector
address with A6 = 1,
A1 = 1, A0 = 0
Wait 15 ms
Increment
PLSCNT
Verify Chip Unprotect: Write
40h to sector address with
A6 = 1, A1 = 1, A0 =0
Wait 0.4 μs
No
PLSCCNT =
1000?
Yes
Device failed
Read from sector address with
A6 = 1, A1 = 1, A0 = 0
No
Set up next sector
group address
Data = 00h?
Yes
Last sector
verified?
No
Yes
Chip Unprotect Algorithm
Remove VID from
RESET#
Write reset
command
Chip Unprotect
complete
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
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EN29LV320C
DC Characteristics
Table 15. DC Characteristics
(TBaB = 0°C to 70°C or - 40°C to 85°C; VBCCB = 2.7-3.6V)
Symbol
ILI
B
Parameter
Test Conditions
Output Leakage Current
ILO
B
B
Active Read Current ( Byte mode )
ICC1
B
B
Active Read Current ( Word mode )
B
B
Supply Current (Program or Erase)
B
B
Supply Current (Standby - CMOS)
B
ICC4
B
Reset Current
B
B
B
Automatic Sleep Mode
B
VIL
B
B
B
B
B
VHH
B
B
VID
B
B
VOL
B
B
VOH
B
B
VLKO
B
B
9
16
mA
20
30
mA
1
5.0
µA
1
5.0
µA
1
5.0
µA
-0.5
0.7 x
Vcc
0.8
Vcc +
0.3
V
8.5
9.5
V
8.5
9.5
V
0.45
V
B
B
RESET# = Vss ± 0.3V
VIH = Vcc ± 0.3V
B
VIL = Vss ± 0.3V
B
Input High Voltage
VIH
µA
B
Input Low Voltage
B
µA
mA
WE# = VIL
CE# = BYTE# =
RESET# = Vcc ± 0.3V
(Note 1)
B
±5
16
CE# = VIL, OE# = VIH ,
B
ICC5
Unit
±5
B
B
ICC3
Max
9
B
CE# = VIL ; OE# = VIH ;
f = 5MHz
B
ICC2
B
0V≤ VOUT ≤ Vcc
B
B
Typ
0V≤ VIN ≤ Vcc
Input Leakage Current
B
Min
#WP/ACC Voltage (Write Protect /
Program Acceleration)
Voltage for Autoselect or
Temporary Sector Unprotect
Output Low Voltage
IOL = 4.0 mA
Output High Voltage CMOS
IOH = -100 μA
B
B
B
B
Supply voltage (Erase and
Program lock-out)
Vcc 0.4V
2.3
V
V
2.5
V
Notes:
1. BYTE# pin can also be GND ± 0.3V. BYTE# and RESET# pin input buffers are always enabled so that
they draw power if not at full CMOS supply voltages.
2. Maximum ICC specifications are tested with Vcc = Vcc max.
B
B
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
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EN29LV320C
Test Conditions
Test Specifications
Test Conditions
-70
Unit
Output Load Capacitance, CL
30
pF
Input Rise and Fall times
5
ns
Input Pulse Levels
Input timing measurement
reference levels
Output timing measurement
reference levels
0.0-3.0
V
1.5
V
1.5
V
B
B
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
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EN29LV320C
AC CHARACTERISTICS
Table 16. Hardware Reset (RESET#)
Paramete
r Std
tRP1
tRP2
tRH
tRB1
tRB2
tREADY1
tREADY2
Description
RESET# Pulse Width (During Embedded Algorithms)
RESET# Pulse Width (NOT During Embedded Algorithms)
Reset# High Time Before Read
RY/BY# Recovery Time ( to CE#, OE# go low)
RY/BY# Recovery Time ( to WE# go low)
Reset# Pin Low (During Embedded Algorithms)
to Read or Write
Reset# Pin Low (NOT During Embedded Algorithms)
to Read or Write
Test
Setup
Min
Min
Min
Min
Min
Speed
-70
10
500
50
0
50
Max
20
us
Max
500
ns
Unit
us
ns
ns
ns
ns
Figure 1. AC Waveforms for RESET#
Reset# Timings
tRB1
CE#, OE#
WE#
tREADY1
tRB2
RY/BY#
RESET#
tRP1
Reset Timing during Embedded Algorithms
CE#, OE#
tRH
RY/BY#
RESET#
tRP2
tREADY2
Reset Timing NOT during Embedded Algorithms
This Data Sheet may be revised by subsequent versions
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or modifications due to changes in technical specifications.
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EN29LV320C
AC CHARACTERISTICS
Table 17. Word / Byte Configuration (BYTE#)
Std
Parameter
tBCS
tCBH
tRBH
Description
Byte# to CE# switching setup time
CE# to Byte# switching hold time
RY/BY# to Byte# switching hold time
Speed
Test
Setup
-70
Min
Min
Min
0
0
0
Unit
ns
ns
ns
Figure 2. AC Waveforms for BYTE#
CE#
OE#
Byte#
tCBH
tBCS
Byte# timings for Read Operations
CE#
WE#
Byte#
tBCS
tRBH
RY/BY#
Byte #timings for Write Operations
Note: Switching BYTE# pin not allowed during embedded operations
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EN29LV320C
AC CHARACTERISTICS
Table 18. Read-only Operations Characteristics
Parameter
Symbols
JEDEC
Standard
Speed
Test Setup
Description
Unit
-70
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable To Output Delay
tGLQV
tOE
tEHQZ
Min
70
ns
CE# = VIL
OE#= VIL
Max
70
ns
OE#= VIL
Max
70
ns
Output Enable to Output Delay
Max
30
ns
tDF
Chip Enable to Output High Z
Max
20
ns
tGHQZ
tDF
Output Enable to Output High Z
Max
20
ns
tAXQX
tOH
Output Hold Time from
Addresses, CE# or OE#,
whichever occurs first
Min
0
ns
Output Enable
Hold Time
MIn
0
ns
tOEH
Min
10
ns
Read
Toggle and
DATA# Polling
Notes:
1. High Z is Not 100% tested.
2. For - 70
Vcc = 2.7V – 3.6V
Output Load: 30pF
Input Rise and Fall Times: 5ns
Input Pulse Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level, Input and Output: 1.5 V
Figure 3. AC Waveforms for READ Operations
tBRCB
Addresses
Addresses Stable
tBACC
CE#
tBDF
tBOEB
OE#
tBOEHB
WE#
tBOH
tBCEB
HIGH Z
Outputs
Output Valid
HIGH Z
RESET#
RY/BY#
0V
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
34
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
AC CHARACTERISTICS
Table 19. Write (Erase/Program) Operations
Parameter
Symbols
JEDEC
Standard
tAVAV
tWC
B
B
Min
70
ns
Address Setup Time
Min
0
ns
tWLAX
B
tAH
Address Hold Time
Min
45
ns
tDS
Data Setup Time
Min
30
ns
Data Hold Time
Min
0
ns
Output Enable Setup Time
Min
0
ns
Read Recovery Time before
Write (OE# High to WE# Low)
Min
0
ns
CE# Setup Time
Min
0
ns
CE# Hold Time
Min
0
ns
Write Pulse Width
Min
45
ns
Write Pulse Width High
Min
20
ns
Byte
Typ
8
Word
Typ
8
Accelerated Programming
Operation
(Word AND Byte Mode)
Typ
7
µs
Sector Erase Operation
Typ
0.1
s
Chip Erase Operation
Typ
8
s
Vcc Setup Time
Min
50
µs
WE# High to RY/BY# Low
Max
70
ns
Min
0
ns
B
tAS
B
B
B
B
B
B
tDVWH
B
B
B
tWHDX
B
B
tDH
B
B
B
B
tOES
B
tGHWL
B
tELWL
B
B
tGHWL
B
B
B
tWHEH
B
B
tCH
B
B
B
tWLWH
tWP
tWHDL
tWPH
B
B
B
B
B
B
Programming
Operation
B
tWHW1
B
tWHWH1
B
B
B
B
B
tWHWH1
B
tWHW2
B
B
tWHW1
B
B
tCS
B
Unit
-70
Write Cycle Time
B
tAVWL
Speed
Description
tWHWH2
B
tVCS
B
B
t BUSY
B
tRB
B
µs
B
Recovery Time from RY/BY#
Notes: tWC is Not 100% tested.
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
35
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
AC CHARACTERISTICS
Table 20. Write (Erase/Program) Operations
Alternate CE# Controlled Writes
Parameter
Symbols
JEDEC
Standard
tAVAV
tWC
tAVEL
tAS
tELAX
Speed Options
Description
Unit
-70
Write Cycle Time
Min
70
ns
Address Setup Time
Min
0
ns
tAH
Address Hold Time
Min
45
ns
tDVEH
tDS
Data Setup Time
Min
30
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
Output Enable Setup Time
Min
0
ns
Read Recovery Time before
Write (OE# High to CE# Low)
Min
0
ns
WE# Setup Time
Min
0
ns
WE# Hold Time
Min
0
ns
CE# Pulse Width
Min
35
ns
CE# Pulse Width High
Min
20
ns
Byte
Typ
8
Word
Typ
8
Accelerated Programming
Operation
(Word AND Byte Mode)
Typ
7
µs
Sector Erase Operation
Typ
0.1
s
Vcc Setup Time
Min
50
µs
Min
0
ns
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
tOES
B
tGHEL
B
B
tGHEL
B
tWLEL
B
tWS
B
tEHWH
B
B
tWH
B
B
B
tCP
tEHEL
tCPH
B
B
B
B
B
Programming
Operation
B
tWHW1
B
B
B
B
tWHWH1
B
B
B
tWHWH1
B
tWHW2
B
B
tWHW1
B
B
tELEH
B
B
tWHWH2
B
tVCS
tRB
B
B
Recovery Time from RY/BY#
µs
Notes: tWC is Not 100% tested.
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
36
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
AC CHARACTERISTICS
Figure 4. AC Waveforms for WE# Control Chip/Sector Erase Operations Timings
Erase Command Sequence (last 2 cycles)
tAS
tWC
Addresses
0x2AA
Read Status Data (last two cycles)
tAH
SA
VA
VA
0x555 for chip
erase
CE#
tGHWL
tCH
OE#
tWP
WE#
tWPH
tCS
0x55
Data
tDS
tWHWH2
0x30
tDH
Status
10 for chip
erase
DOUT
tRB
tBUSY
RY/BY#
VCC
tVCS
Notes:
1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout =true data at read address.
2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command
sequence.
B
B
B
B
B
B
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
37
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
Figure 5. Program Operation Timings
Program Command Sequence (last 2 cycles)
tAS
tWC
Addresses
0x555
Program Command Sequence (last 2 cycles)
tAH
PA
PA
PA
CE#
tGHWL
OE#
tCH
tWP
WE#
tWPH
tWHWH1
tCS
Data
OxA0
tDS
RY/BY#
Status
PD
tDH
DOUT
tBUSY
tRB
tVCS
VCC
Notes:
1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address.
2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid command
sequence.
B
B
B
B
B
B
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
38
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
Figure 6. AC Waveforms for /DATA Polling During Embedded Algorithm
Operations
tRC
Addresses
VA
VA
VA
tACC
tCH
tCE
CE#
tOE
OE#
tOEH
tDF
WE#
tOH
DQ[7]
Complement
DQ[6:0]
Status Data
Comple
-ment
Status
Data
Valid Data
True
True
Valid Data
tBUSY
RY/BY#
Notes:
1. VA=Valid Address for reading Data# Polling status data
2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.
Figure 7. AC Waveforms for Toggle Bit During Embedded Algorithm Operations
tRC
Addresses
VA
VA
tCH
VA
VA
tACC
tCE
CE#
tOE
OE#
tOEH
WE#
tDF
tOH
Valid Status
DQ6, DQ2
tBUSY
(first read)
Valid Status
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
39
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
Figure 8. Alternate CE# Controlled Write Operation Timings
PA for Program
SA for Sector Erase
0x555 for Chip Erase
0x555 for Program
0x2AA for Erase
Addresses
VA
tWC
tAS
tAH
WE#
tWH
tGHEL
OE#
tCP
tCPH
tWS
CE#
tWHWH1 / tWHWH2
tBUSY
tDH
tDS
Status
Data
0xA0 for
Program
0x55 for Erase
DOUT
PD for Program
0x30 for Sector Erase
0x10 for Chip Erase
RY/BY
tRH
Reset#
Notes:
PA = address of the memory location to be programmed.
PD = data to be programmed at byte address.
VA = Valid Address for reading program or erase status
Dout = array data read at VA
Shown above are the last two cycles of the program or erase command sequence and the last status read cycle
RESETt# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command
sequence.
B
B
B
B
Figure 9. DQ2 vs. DQ6
Enter
Embedded
Erase
WE#
Enter Erase
Suspend
Program
Erase
Suspend
Erase
Enter
Suspend
Read
Erase
Resume
Enter
Suspend
Program
Erase
Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
40
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
AC CHARACTERISTICS
Table 21. Temporary Sector Unprotect
Parameter
Std
Description
tVIDR
VID Rise and Fall Time
tVIHH
VHH Rise and Fall Time
RESET# Setup Time for Temporary
Sector Unprotect(Note)
B
B
B
B
tRSP
B
B
B
B
B
B
Speed Option
-70
Unit
Min
500
ns
Min
500
ns
Min
4
µs
Notes: Not 100% tested.
Figure 10. Temporary Sector Unprotect Timing Diagram
VID
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
CE#
WE#
tRSP
RY/BY#
AC CHARACTERISTICS
Write Protect / Accelerated Program
Figure 11. Accelerated Program Timing Diagram
VHH
B
B
WP#/ACC
0 or 3 V
0 or 3 V
tVHH
B
B
tVHH
B
B
CE#
WE#
tRSP
B
B
AC CHARACTERISTICS
Sector (Group) Protect and Chip Unprotect
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
41
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
Figure 12. Sector Group Protect and Chip Unprotect Timing Diagram
VID
RESET#
Vcc
0V
0V
tVIDR
tVIDR
SA,
A6,A1,A0
Data
60h
Valid
Valid
Valid
60h
40h
Status
Sector Protect/Unprotect
CE#
Verify
>0.4μS
WE#
>1μS
Protect: 150 uS
Unprotect: 15 mS
OE#
Notes:
Use standard microprocessor timings for this device for read and write cycles.
For Sector Group Protect, use A6=0, A1=1, A0=0. For Chip Unprotect, use A6=1, A1=1, A0=0.
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
42
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
Table 22. ERASE AND PROGRAM PERFORMANCE
Parameter
Typ
Sector Erase Time
Limits
Max
0.1
2
sec
Chip Erase Time
8
70
sec
Byte Programming Time
8
200
µs
Accelerated Byte/Word Program Time
7
200
µs
Word Programming Time
8
200
µs
Byte
33.6
100.8
Word
16.8
50.4
Chip Programming Time
Erase/Program Endurance
Comments
Unit
Excludes 00h programming prior to
erasure
Excludes system level overhead
sec
100K
Minimum 100K cycles
Cycles
Notes:
1. Typical program and erase times assume the following conditions: room temperature, 3V and checkboard
pattern programmed.
2. Maximum program and erase times assume the following conditions: worst case Vcc, 90 C and 100,000 cycles.
Table 23. 48-PIN TSOP AND BGA PACKAGE CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
CIN
Input Capacitance
VIN = 0
B
B
COUT
B
CIN2
B
B
B
Output Capacitance
Control Pin Capacitance
B
Package
Typ
Max
TSOP
6
7.5
BGA
1.2
1.2
TSOP
8.5
12
BGA
1.1
1.2
TSOP
7.5
9
BGA
1.0
1.3
B
VOUT = 0
B
B
VIN = 0
B
B
Unit
pF
pF
pF
Note: Test conditions are Temperature = 25°C and f = 1.0 MHz.
Table 24. DATA RETENTION
Parameter Description
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Data Retention Time
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
43
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
Storage Temperature
-65 to +150
C
Plastic Packages
-65 to +125
C
-55 to +125
C
200
mA
-0.5 to +11.5
V
-0.5 to Vcc+0.5
V
-0.5 to + 4.0
V
Ambient Temperature
With Power Applied
Output Short Circuit Current1
P
P
A9, OE#, RESET#
and WP#/ACC2
P
P
P
P
Voltage with
Respect to Ground
All other pins 3
P
P
Vcc
Notes:
1.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
2.
Minimum DC input voltage on A9, OE#, RESET# and WP#/ACC pins is –0.5V. During voltage transitions, A9, OE#, RESET#
and WP#/ACC pins may undershoot V ss to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure
below. Maximum DC input voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns.
3.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot V ss to –1.0V for periods
of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is V cc +
0.5 V. During voltage transitions, outputs may overshoot to V cc + 1.5 V for periods up to 20ns. See figure below.
4.
Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress
rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the
device to the maximum rating values for extended periods of time may adversely affect the device reliability.
B
B
B
B
B
B
RECOMMENDED OPERATING RANGES 1
P
P
Parameter
Value
Unit
-40 to 85
C
Full Voltage Range:
2.7 to 3.6V
V
Ambient Operating Temperature
Industrial Devices
Operating Supply Voltage
Vcc
1.
B
B
Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc
+1.5V
Maximum Negative Overshoot
Waveform
Maximum Positive Overshoot
Waveform
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
44
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
FIGURE 13. 48L TSOP 12mm x 20mm package outline
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
45
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
FIGURE 14. 48L TFBGA 6mm x 8mm package outline
SYMBOL
DIMENSION IN MM
MIN.
NOR
MAX
A
---
---
1.30
A1
0.23
0.29
---
A2
0.84
0.91
---
D
7.90
8.00
8.10
E
5.90
6.00
6.10
D1
---
5.60
---
E1
---
4.00
---
e
---
0.80
---
b
0.35
0.40
Note : 1. Coplanarity: 0.1 mm
0.45
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
46
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
Purpose
Eon Silicon Solution Inc. (hereinafter called “Eon”) is going to provide its products’ top marking on
ICs with < cFeon > from January 1st, 2009, and without any change of the part number and the
compositions of the ICs. Eon is still keeping the promise of quality for all the products with the
same as that of Eon delivered before. Please be advised with the change and appreciate your
kindly cooperation and fully support Eon’s product family.
Eon products’ Top Marking
cFeon Top Marking Example:
cFeon
Part Number: XXXX-XXX
Lot Number: XXXXX
Date Code:
XXXXX
For More Information
Please contact your local sales office for additional information about Eon memory solutions.
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
47
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
ORDERING INFORMATION
EN29LV320C
T
70
T
I
P
PACKAGING CONTENT
P = RoHS compliant
TEMPERATURE RANGE
I = Industrial (-40°C to +85°C)
PACKAGE
T = 48-pin TSOP
B = 48-Ball Thin Fine Pitch Ball Grid Array (TFBGA)
0.80mm pitch, 6mm x 8mm package
SPEED
70 = 70ns
BOOT CODE SECTOR ARCHITECTURE
T = Top boot Sector
B = Bottom boot Sector
BASE PART NUMBER
EN = EON Silicon Solution Inc.
29LV = FLASH, 3V Read, Program and Erase
320 = 32 Megabit (4M x 8 / 2M x 16)
C = version identifier
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
48
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
www.eonssi.com
EN29LV320C
Revisions List
Revision No
Description
Date
A
B
C
Initial Release
2011/01/07
2011/05/13
2011/10/26
Update VHH and VID from 10.5-11.5V to 8.5-9.5V.
Add BGA PACKAGE CAPACITANCE on page 43.
B
B
This Data Sheet may be revised by subsequent versions
© 2004 Eon Silicon Solution, Inc.,
49
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2011/10/26
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