UPD789871 Subseries User's Manual(Preliminary)

UPD789871 Subseries User's Manual(Preliminary)

To our customers,

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On April 1

st

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both companies.

Therefore, although the old company name remains in this document, it is a valid

Renesas

Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

st

, 2010

Renesas Electronics Corporation

Issued by:

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(http://www.renesas.com)

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Preliminary User’s Manual

µ

PD789871 Subseries

8-Bit Single-Chip Microcontrollers

µPD789870

µPD789871

µPD78F9872

Document No. U14938EJ1V0UM00 (1st edition)

Date Published January 2001 N CP(K)

©

Printed in Japan

2001

[MEMO]

2

Preliminary User’s Manual U14938EJ1V0UM

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V

DD

or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

EEPROM is a trademark of NEC Corporation.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun-Microsystems, Inc.

OSF/Motif is a trademark of Open Software Foundation, Inc.

NEWS and NEWS-OS are trademarks of Sony Corporation.

TRON is an abbreviation of The Realtime Operating System Nucleus.

ITRON is an abbreviation of Industrial TRON.

Preliminary User’s Manual U14938EJ1V0UM

3

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

Licence not needed:

µPD78F9872

The customer must judge the need for license:

µPD789870, 789871

The information contained in this document is being issued in advance of the production cycle for the

device. The parameters for the device may change before final production or NEC Corporation, at its own

discretion, may withdraw the device prior to its production.

Not all devices/types available in every country. Please check with local NEC representative for availability

and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these circuits,

software, and information in the design of the customer's equipment shall be done under the full responsibility

of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third

parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

M5D 98. 12

4

Preliminary User’s Manual U14938EJ1V0UM

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy

Tel: 02-66 75 41

Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 040-2444580

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

Fax: 2886-9022/9044

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

Fax: 01-30-67 58 99

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics (France) S.A.

Madrid Office

Madrid, Spain

Tel: 91-504-2787

Fax: 91-504-2860

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore

Tel: 65-253-8311

Fax: 65-250-3583

NEC Electronics (Germany) GmbH

Scandinavia Office

Taeby, Sweden

Tel: 08-63 80 820

Fax: 08-63 80 388

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division

Guarulhos-SP Brasil

Tel: 55-11-6462-6810

Fax: 55-11-6462-6829

J00.7

Preliminary User’s Manual U14938EJ1V0UM

5

INTRODUCTION

Target Readers

Purpose

Organization

This manual is intended for users who wish to understand the functions of the

µPD789871 Subseries and to design and develop application systems and programs using these microcontrollers.

This manual is intended for users to understand the functions described in the organization below.

The

µPD789871 Subseries User's Manual is divided into two parts: this manual and instructions (common to the 78K/0S Series).

µPD789871

Subseries

User’s Manual (This manual)

• Pin functions

• Internal block functions

• Interrupt

• Other internal peripheral functions

78K/0S Series

User’s Manual

Instructions

• CPU function

• Instruction set

• Instruction description

How to Read This Manual

It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers.

Conventions

Related Documents

To understand the overall functions in general

→ Read this manual in the order of the CONTENTS.

How to interpret register formats

→ The name of a bit whose number is encircled is reserved for the assembler and is defined for the C compiler by the header file sfrbit.h.

To learn the detailed functions of a register whose register name is known

→ Refer to APPENDIX C REGISTER INDEX.

To learn the details of the instruction functions of the 78K/0S Series

→ Refer to 78K/0S Series User’s Manual Instructions (U11047E).

Data significance: Higher digits on the left and lower digits on the right

Active low representation:

××× (overscore over pin or signal name)

Note: Footnote for item marked with Note in the text

Caution: Information requiring particular attention

Remark: Supplementary information

Numerical representation: Binary ...

×××× or ××××B

Decimal ...

××××

Hexadecimal ...

××××H

The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

6

Preliminary User’s Manual U14938EJ1V0UM

Documents Related to Devices

Document Name

µPD789870, 789871 Preliminary Product Information

µPD78F9872 Preliminary Product Information

µPD789871 Subseries User’s Manual

78K/0S Series User’s Manual Instruction

78K/0, 78K/0S Series Application Note Flash Memory Write

Document No.

English

U14916E

U14880E

This manual

U11047E

U14458E

Documents Related to Development Tools (User’s Manuals)

RA78K0S Assembler Package

CC78K0S C Compiler

Document Name

SM78K0S System Simulator Windows

TM

Based

SM78K Series System Simulator

ID78K0S-NS Integrated Debugger

Windows Based

IE-78K0S-NS In-Circuit Emulator

IE-789872-NS-EM1 Emulation Board

Operation

Assembly Language

Structured Assembly Language

Operation

Document No.

English

U11622E

U11599E

U11623E

U11816E

Language

Reference

U11817E

U11489E

External components user open U10092E interface specification

Reference U12901E

U13549E

To be prepared

Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.

Preliminary User’s Manual U14938EJ1V0UM

7

Document Related to Embedded Software (User’s Manual)

Document Name

78K/0S Series OS MX78K0S Basics

Document No.

English

U12938E

Other Documents

Document Name

SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)

Semiconductor Device Mounting Technology Manual

Quality Grades on NEC Semiconductor Devices

NEC Semiconductor Device Reliability/Quality Control System

Document No.

English

X13769X

C10535E

C11531E

C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E

Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.

8

Preliminary User’s Manual U14938EJ1V0UM

CONTENTS

CHAPTER 1 GENERAL ....................................................................................................................

18

1.1 Features ...............................................................................................................................

18

1.2 Applications ........................................................................................................................

18

1.3 Ordering Information .........................................................................................................

18

1.4 Pin Configuration (Top View) ...........................................................................................

19

1.5 78K/0S Series Lineup ........................................................................................................

20

1.6 Block Diagram ....................................................................................................................

22

1.7 Overview of Functions ......................................................................................................

23

CHAPTER 2 PIN FUNCTIONS .........................................................................................................

24

2.1 List of Pin Functions .........................................................................................................

24

2.2 Description of Pin Functions ...........................................................................................

26

2.2.1 P00 to P07 (Port 0) ..................................................................................................................

26

2.2.2 P10 to P12 (Port 1) ..................................................................................................................

26

2.2.3 P20 to P25 (Port 2) ..................................................................................................................

26

2.2.4 P80 to P87 (Port 8) ..................................................................................................................

26

2.2.5 P90 to P97 (Port 9) ..................................................................................................................

27

2.2.6 FIP0 to FIP8 .............................................................................................................................

27

2.2.7 RESET ......................................................................................................................................

27

2.2.8 X1, X2 .......................................................................................................................................

27

2.2.9 XT1, XT2 ...................................................................................................................................

27

2.2.10 V

DD0

.........................................................................................................................................

27

2.2.11 V

DD1

.........................................................................................................................................

27

2.2.12 V

LOAD

.......................................................................................................................................

27

2.2.13 V

SS0

.........................................................................................................................................

27

2.2.14 V

PP

(

µPD78F9872 only) .........................................................................................................

27

2.2.15 IC (mask ROM version only) .................................................................................................

28

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ..............................

29

CHAPTER 3 CPU ARCHITECTURE ................................................................................................

31

3.1 Memory Space ....................................................................................................................

31

3.1.1 Internal program memory space ..............................................................................................

34

3.1.2 Internal data memory (internal high-speed RAM) space ........................................................

35

3.1.3 Special function register (SFR) area .......................................................................................

35

3.1.4 Data memory addressing .........................................................................................................

35

3.2 Processor Registers ..........................................................................................................

39

3.2.1 Control registers .......................................................................................................................

39

3.2.2 General-purpose registers .......................................................................................................

42

3.2.3 Special function registers (SFRs) ............................................................................................

43

3.3 Instruction Address Addressing ......................................................................................

45

3.3.1 Relative addressing ..................................................................................................................

45

3.3.2 Immediate addressing ..............................................................................................................

46

3.3.3 Table indirect addressing .........................................................................................................

47

3.3.4 Register addressing .................................................................................................................

47

3.4 Operand Address Addressing ..........................................................................................

48

Preliminary User’s Manual U14938EJ1V0UM

9

3.4.1 Direct addressing .....................................................................................................................

48

3.4.2 Short direct addressing ............................................................................................................

49

3.4.3 Special function register (SFR) addressing ............................................................................

50

3.4.4 Register addressing .................................................................................................................

51

3.4.5 Register indirect addressing ....................................................................................................

52

3.4.6 Based addressing .....................................................................................................................

53

3.4.7 Stack addressing ......................................................................................................................

53

CHAPTER 4 PORT FUNCTIONS .....................................................................................................

54

4.1 Functions of Ports .............................................................................................................

54

4.2 Port Configuration .............................................................................................................

56

4.2.1 Port 0 ........................................................................................................................................

56

4.2.2 Port 1 ........................................................................................................................................

57

4.2.3 Port 2 ........................................................................................................................................

58

4.2.4 Port 8 ........................................................................................................................................

61

4.2.5 Port 9 ........................................................................................................................................

62

4.3 Port Function Control Registers ......................................................................................

63

4.4 Operation of Port Functions .............................................................................................

65

4.4.1 Writing to I/O port .....................................................................................................................

65

4.4.2 Reading from I/O port ..............................................................................................................

65

4.4.3 Arithmetic operation of I/O port ................................................................................................

65

CHAPTER 5 CLOCK GENERATOR ................................................................................................

66

5.1 Clock Generator Functions ..............................................................................................

66

5.2 Clock Generator Configuration ........................................................................................

66

5.3 Register Controlling Clock Generator ............................................................................

68

5.4 System Clock Oscillators .................................................................................................

70

5.4.1 Main system clock oscillator ....................................................................................................

70

5.4.2 Subsystem clock oscillator ........................................................................................................

70

5.4.3 Frequency divider .....................................................................................................................

72

5.4.4 When no subsystem clock is used ..........................................................................................

72

5.5 Clock Generator Operation ...............................................................................................

73

5.6 Changing Setting of System Clock and CPU Clock ......................................................

74

5.6.1 Time required for switching between system clock and CPU clock ......................................

74

5.6.2 Switching between system clock and CPU clock ...................................................................

75

CHAPTER 6 8-BIT REMOTE CONTROL TIMER .............................................................................

76

6.1 8-Bit Remote Control Timer Functions ...........................................................................

76

6.2 8-Bit Remote Control Timer Configuration ....................................................................

76

6.3 Registers Controlling 8-Bit Remote Control Timer .......................................................

77

6.4 Operation of 8-Bit Remote Control Timer .......................................................................

78

CHAPTER 7 8-BIT TIMER ................................................................................................................

80

7.1 8-Bit Timer Functions ........................................................................................................

80

7.2 8-Bit Timer Configuration .................................................................................................

81

7.3 Registers Controlling 8-Bit Timer ....................................................................................

83

7.4 8-Bit Timer Operation ........................................................................................................

85

7.4.1 Operation as interval timer .......................................................................................................

85

10

Preliminary User’s Manual U14938EJ1V0UM

CHAPTER 8 WATCH TIMER ..........................................................................................................

87

8.1 Watch Timer Functions .....................................................................................................

87

8.2 Watch Timer Configuration ...............................................................................................

88

8.3 Register Controlling Watch Timer ...................................................................................

88

8.4 Watch Timer Operation .....................................................................................................

89

8.4.1 Operation as watch timer .........................................................................................................

89

8.4.2 Operation as interval timer .......................................................................................................

90

CHAPTER 9 WATCHDOG TIMER ....................................................................................................

91

9.1 Watchdog Timer Functions ...............................................................................................

91

9.2 Watchdog Timer Configuration ........................................................................................

92

9.3 Registers Controlling Watchdog Timer ..........................................................................

93

9.4 Watchdog Timer Operation ...............................................................................................

95

9.4.1 Operation as watchdog timer ...................................................................................................

95

9.4.2 Operation as interval timer .......................................................................................................

96

CHAPTER 10 SERIAL INTERFACE 10 ......................................................................................

97

10.1 Serial Interface 10 Functions .........................................................................................

97

10.2 Serial Interface 10 Configuration ...................................................................................

97

10.3 Register Controlling Serial Interface 10 .......................................................................

99

10.4 Serial Interface 10 Operation ......................................................................................... 101

10.4.1 Operation stop mode ..............................................................................................................

101

10.4.2 3-wire serial I/O mode ............................................................................................................

102

CHAPTER 11 VFD CONTROLLER/DRIVER .................................................................................... 104

11.1 VFD Controller/Driver Functions .................................................................................... 104

11.2 VFD Controller/Driver Configuration .............................................................................

105

11.3 Registers Controlling VFD Controller/Driver ...............................................................

106

11.3.1 Control registers .....................................................................................................................

106

11.3.2 One display period and blanking width .................................................................................

109

11.4 Display Data Memory .......................................................................................................

110

11.5 Key Scan Flag and Key Scan Data ................................................................................

112

11.5.1 Key scan flag ..........................................................................................................................

112

11.5.2 Key scan data .........................................................................................................................

112

11.6 Leakage Emission of Fluorescent Indicator Panel .....................................................

113

11.7 Calculation of Total Power Dissipation .........................................................................

116

CHAPTER 12 INTERRUPT FUNCTIONS ........................................................................................

119

12.1 Interrupt Function Types .................................................................................................

119

12.2 Interrupt Sources and Configuration ............................................................................

119

12.3 Interrupt Function Control Registers ............................................................................ 123

12.4 Interrupt Processing Operation ..................................................................................... 128

12.4.1 Non-maskable interrupt request acknowledgement operation .............................................

128

12.4.2 Maskable interrupt request acknowledgement operation .....................................................

130

12.4.3 Multiple interrupt processing ..................................................................................................

132

12.4.4 Interrupt request pending .......................................................................................................

134

CHAPTER 13 STANDBY FUNCTION .............................................................................................. 135

13.1 Standby Function and Configuration ............................................................................ 135

Preliminary User’s Manual U14938EJ1V0UM

11

13.1.1 Standby function .....................................................................................................................

135

13.1.2 Register controlling standby function ....................................................................................

136

13.2 Operation of Standby Function ...................................................................................... 137

13.2.1 HALT mode .............................................................................................................................

137

13.2.2 STOP mode ............................................................................................................................

140

CHAPTER 14 RESET FUNCTION ................................................................................................... 143

CHAPTER 15

µPD78F9872 .............................................................................................................. 146

15.1 Flash Memory Programming .......................................................................................... 147

15.1.1 Selecting communication mode .............................................................................................

147

15.1.2 Function of flash memory programming ................................................................................

148

15.1.3 Flashpro III connection example ...........................................................................................

148

15.1.4 Example of settings for Flashpro III (PG-FP3) .......................................................................

149

CHAPTER 16 MASK OPTION (MASK ROM VERSION) ................................................................ 150

CHAPTER 17 INSTRUCTION SET .................................................................................................. 151

17.1 Operation ........................................................................................................................... 151

17.1.1 Operand identifiers and description methods .......................................................................

151

17.1.2 Description of “operation” column .........................................................................................

152

17.1.3 Description of “flag operation” column ..................................................................................

152

17.2 Operation List ................................................................................................................... 153

17.3 Instructions Listed by Addressing Type ....................................................................... 158

APPENDIX A DEVELOPMENT TOOLS ........................................................................................... 161

A.1 Language Processing Software ...................................................................................... 163

A.2 Flash Memory Writing Tools ............................................................................................ 164

A.3 Debugging Tools ................................................................................................................ 164

A.3.1 Hardware ..................................................................................................................................

164

A.3.2 Software ...................................................................................................................................

165

APPENDIX B EMBEDDED SOFTWARE ......................................................................................... 166

APPENDIX C REGISTER INDEX ...................................................................................................... 167

C.1 Register Name Index (Alphabetic Order) ....................................................................... 167

C.2 Register Symbol Index (Alphabetic Order) .................................................................... 169

12

Preliminary User’s Manual U14938EJ1V0UM

LIST OF FIGURES (1/3)

Figure No.

Title Page

2-1 Pin I/O Circuits ......................................................................................................................................

30

3-1

3-2

3-3

3-4

3-5

3-6

Memory Map (

µPD789870) ..................................................................................................................

31

Memory Map (

µPD789871) ..................................................................................................................

32

Memory Map (

µPD78F9872) ................................................................................................................

33

Data Memory Addressing (

µPD789870) ..............................................................................................

36

Data Memory Addressing (

µPD789871) ..............................................................................................

37

Data Memory Addressing (

µPD78F9872) ............................................................................................

38

Program Counter Configuration ...........................................................................................................

39 3-7

3-8

3-9

Program Status Word Configuration ....................................................................................................

39

Stack Pointer Configuration ..................................................................................................................

41

3-10 Data to Be Saved to Stack Memory .....................................................................................................

41

3-11 Data to Be Restored from Stack Memory ............................................................................................

41

3-12 General-Purpose Register Configuration .............................................................................................

42

4-1

4-2

4-3

4-4

Port Types .............................................................................................................................................

54

Block Diagram of P00 to P07 ...............................................................................................................

56

Block Diagram of P10 to P12 ...............................................................................................................

57

Block Diagram of P20 ...........................................................................................................................

58

4-5 Block Diagram of P21 ...........................................................................................................................

59

4-6 Block Diagram of P22 to P25 ...............................................................................................................

60

4-7

4-8

Block Diagram of P80 to P87 (

µPD789870, 789871) .........................................................................

61

Block Diagram of P80 to P87 (

µPD78F9872) ......................................................................................

61

4-9 Block Diagram of P90 to P97 (

µPD789870, 789871) .........................................................................

62

4-10 Block Diagram of P90 to P97 (

µPD78F9872) ......................................................................................

62

4-11 Port Mode Register Format ..................................................................................................................

64

4-12 Pull-Up Resistor Option Register 0 Format .........................................................................................

64

4-13 Pull-Up Resistor Option Register B2 Format .......................................................................................

64

5-5

5-6

5-7

5-8

5-1

5-2

5-3

5-4

Block Diagram of Clock Generator .......................................................................................................

67

Processor Clock Control Register Format ...........................................................................................

68

Suboscillation Mode Register Format ..................................................................................................

69

Subclock Control Register Format .......................................................................................................

69

External Circuit of Main System Clock Oscillator ................................................................................

70

External Circuit of Subsystem Clock Oscillator ...................................................................................

70

Examples of Incorrect Resonator Connection .....................................................................................

71

Switching Between System Clock and CPU Clock .............................................................................

75

6-1

6-2

6-3

Block Diagram of 8-Bit Remote Control Timer ....................................................................................

76

Remote Control Timer Control Register 50 Format .............................................................................

77

Pulse Width Measurement Timing ........................................................................................................

78

7-1

7-2

Block Diagram of 8-Bit Timer 80 ..........................................................................................................

81

Block Diagram of 8-Bit Timer 81 ..........................................................................................................

82

Preliminary User’s Manual U14938EJ1V0UM

13

LIST OF FIGURES (2/3)

Figure No.

Title Page

7-3

7-4

7-5

8-Bit Timer Mode Control Register 80 Format .....................................................................................

83

8-Bit Timer Mode Control Register 81 Format .....................................................................................

84

Interval Timer Operation Timing ...........................................................................................................

86

8-1

8-2

8-3

Block Diagram of Watch Timer .............................................................................................................

87

Watch Timer Mode Control Register Format .......................................................................................

89

Watch Timer/Interval Timer Operation Timing .....................................................................................

90

9-1

9-2

9-3

Block Diagram of Watchdog Timer .......................................................................................................

92

Watchdog Timer Clock Select Register Format ...................................................................................

93

Watchdog Timer Mode Register Format ..............................................................................................

94

10-1 Block Diagram of Serial Interface 10 ...................................................................................................

98

10-2 Serial Operation Mode Register 10 Format .........................................................................................

99

10-3 3-Wire Serial I/O Mode Timing .............................................................................................................

103

11-1 Block Diagram of VFD Controller/Driver ..............................................................................................

105

11-2 Display Mode Register 0 Format ..........................................................................................................

106

11-3 Display Mode Register 1 Format ..........................................................................................................

107

11-4 Display Mode Register 2 Format ..........................................................................................................

108

11-5 Blanking Width of VFD Output Signal ..................................................................................................

109

11-6 Relationship Between Address Location of Display Data Memory and VFD Output

(with 25 VFD Output Pins and 16 Patterns) ........................................................................................

110

11-7 Relationship Between Address Location of Display Data Memory and VFD Output

(with 20 VFD Output Pins and 9 Patterns) ..........................................................................................

111

11-8 Leakage Emission Because of Short Blanking Time ...........................................................................

113

11-9 Leakage Emission Caused by C

SG

.......................................................................................................

114

11-10 Leakage Emission Caused by C

SG

.......................................................................................................

115

11-11 Total Power Dissipation P

T

(T

A

= –40 to +85

°C) .................................................................................. 116

11-12 Relationship Between Display Data Memory Contents and VFD Output with

10 Segments-11 Digits Displayed ........................................................................................................

118

14

12-1 Basic Configuration of Interrupt Function ............................................................................................

121

12-2 Interrupt Request Flag Register Format ..............................................................................................

124

12-3 Interrupt Mask Flag Register Format ...................................................................................................

125

12-4 External Interrupt Mode Register 0 Format .........................................................................................

126

12-5 Program Status Word Configuration ....................................................................................................

127

12-6 Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement .........................

129

12-7 Timing of Non-Maskable Interrupt Request Acknowledgement ..........................................................

129

12-8 Acknowledging Non-Maskable Interrupt Request ...............................................................................

129

12-9 Interrupt Acknowledgement Program Algorithm ..................................................................................

131

12-10 Interrupt Request Acknowledgement Timing (Example of MOV A,r) ..................................................

132

12-11 Interrupt Request Acknowledgement Timing

(When Interrupt Request Flag Is Generated at the Last Clock During Instruction Execution) .........

132

Preliminary User’s Manual U14938EJ1V0UM

LIST OF FIGURES (3/3)

Figure No.

Title Page

12-12 Example of Multiple Interrupts ..............................................................................................................

133

13-1 Oscillation Stabilization Time Select Register Format ........................................................................

136

13-2 Releasing HALT Mode by Interrupt ......................................................................................................

138

13-3 Releasing HALT Mode by RESET Input ..............................................................................................

139

13-4 Releasing STOP Mode by Interrupt .....................................................................................................

141

13-5 Releasing STOP Mode by RESET Input ..............................................................................................

142

14-1 Block Diagram of Reset Function .........................................................................................................

143

14-2 Reset Timing by RESET Input ..............................................................................................................

144

14-3 Reset Timing by Overflow in Watchdog Timer .....................................................................................

144

14-4 Reset Timing by RESET Input in STOP Mode ....................................................................................

144

15-1 Communication Mode Selection Format ..............................................................................................

147

15-2 Flashpro III Connection in 3-Wire Serial I/O Mode .............................................................................

148

A-1 Development Tool Configuration ..........................................................................................................

162

Preliminary User’s Manual U14938EJ1V0UM

15

LIST OF TABLES (1/2)

Table No.

Title Page

2-1 Types of Pin I/O Circuits .......................................................................................................................

29

3-1

3-2

3-3

Internal ROM Capacity .........................................................................................................................

34

Vector Table ...........................................................................................................................................

34

Special Function Register List ..............................................................................................................

44

4-1

4-2

4-3

Port Functions .......................................................................................................................................

55

Configuration of Port .............................................................................................................................

56

Port Mode Register and Output Latch Settings When Using Alternate Functions ............................

63

5-1

5-2

Configuration of Clock Generator .........................................................................................................

66

Maximum Time Required for Switching CPU Clock ............................................................................

74

6-1 Configuration of 8-Bit Remote Control Timer ......................................................................................

76

7-1

7-2

7-3

7-4

7-5

Interval Time of 8-Bit Timer 80 .............................................................................................................

80

Interval Time of 8-Bit Timer 81 .............................................................................................................

80

Configuration of 8-Bit Timer ..................................................................................................................

81

Interval Time of 8-Bit Timer 80 .............................................................................................................

85

Interval Time of 8-Bit Timer 81 .............................................................................................................

85

8-1

8-2

8-3

Interval Time of Interval Timer ..............................................................................................................

88

Configuration of Watch Timer ...............................................................................................................

88

Interval Time of Interval Timer ..............................................................................................................

90

9-1

9-2

9-3

9-4

9-5

Runaway Detection Time of Watchdog Timer ......................................................................................

91

Interval Time ..........................................................................................................................................

91

Configuration of Watchdog Timer .........................................................................................................

92

Runaway Detection Time of Watchdog Timer ......................................................................................

95

Interval Time of Interval Timer ..............................................................................................................

96

10-1 Configuration of Serial Interface 10 .....................................................................................................

97

10-2 Settings of Serial Interface 10 Operation Mode ..................................................................................

100

11-1 VFD Output Pins and Alternate-Function Pins for Ports .....................................................................

104

11-2 Configuration of VFD Controller/Driver ................................................................................................

105

12-1 Interrupt Source List .............................................................................................................................

120

12-2 Flags Corresponding to Interrupt Request Signal ...............................................................................

123

12-3 Time from Generation of Maskable Interrupt Request to Processing ................................................

130

13-1 HALT Mode Operating Status ...............................................................................................................

137

13-2 Operation After Release of HALT Mode ...............................................................................................

139

16

Preliminary User’s Manual U14938EJ1V0UM

LIST OF TABLES (2/2)

Table No.

Title Page

13-3 STOP Mode Operating Status ..............................................................................................................

140

13-4 Operation After Release of STOP Mode ..............................................................................................

142

14-1 Hardware Status After Reset ................................................................................................................

145

15-1 Differences Between Flash Memory and Mask ROM Versions ..........................................................

146

15-2 Communication Mode ...........................................................................................................................

147

15-3 Functions of Flash Memory Programming ...........................................................................................

148

15-4 Example of Settings for PG-FP3 ..........................................................................................................

149

17-1 Operand Identifiers and Description Methods .....................................................................................

151

Preliminary User’s Manual U14938EJ1V0UM

17

CHAPTER 1 GENERAL

1.1 Features

• ROM and RAM capacities

Item Program Memory

(ROM)

Part Number

µPD789870

µPD789871

µPD78F9872

ROM

Flash memory

4 KB

8 KB

16 KB

Data Memory

Internal High-Speed LCD Display RAM

512 bytes

RAM

96 bytes

• Minimum instruction execution time can be changed from high-speed (0.4

µs: @ 5.0 MHz operation with main system clock) to ultra-low-speed (122

µs: @ 32.768 kHz operation with subsystem clock)

• I/O ports: 33

• Timer: 5 channels

• 8-bit remote control timer: 1 channel

• 8-bit timer:

• Watch timer:

• Watchdog timer:

• Serial interface:

2 channels

1 channel

1 channel

1 channel

• VFD controller/driver: Display output total 25

• Vectored interrupt sources: 12

• Power supply voltage: V

DD

= 2.7 to 5.5 V (in normal operation)

V

DD

= 4.5 to 5.5 V (in VFD operation)

• Operating ambient temperature: T

A

= –40 to +85

°C

1.2 Applications

Products with a front panel such as DVD, VCD, and S-VCD.

1.3 Ordering Information

Part Number

µPD789870GB-×××-8ET

µPD789871GB-×××-8ET

µPD78F9872GB-8ET

Remark

××× indicates ROM code suffix.

Package

52-pin plastic LQFP (10

× 10)

52-pin plastic LQFP (10

× 10)

52-pin plastic LQFP (10

× 10)

Internal ROM

Mask ROM

Mask ROM

Flash memory

18

Preliminary User’s Manual U14938EJ1V0UM

1.4 Pin Configuration (Top View)

• 52-pin plastic LQFP (10

× 10)

µPD789870GB-×××-8ET

µPD789871GB-×××-8ET

µPD78F9872GB-8ET

CHAPTER 1 GENERAL

V

DD0

XT1

XT2

RESET

P10

P11

P12

P20/SCK10

P21/SO10

P22/SI10

P23/INTP0

P24/INTP1

P25/TI

1

52 51 50 49 48 47 46 45 44 43 42

41 40

39

2

38

3

37

4

36

5

35

6

34

7

33

8

32

9

31

10

30

11

12

29

28

13

14 15 16 17 18 19 20 21 22 23 24

27

25 26

P81/FIP23

P82/FIP22

P83/FIP21

P84/FIP20

P85/FIP19

P86/FIP18

P87/FIP17

P90/FIP16

P91/FIP15

P92/FIP14

P93/FIP13

V

LOAD

V

DD1

Caution Connect the IC (Internally Connected) pin directly to V

SS0

.

Remark The parenthesized values apply to

µPD78F9872.

FIP0 to FIP24: Fluorescent Indicator Panel

IC: Internally Connected

INTP0, INTP1: Interrupt from Peripherals

P00 to P07:

P10 to P12:

Port 0

Port 1

P20 to P25:

P80 to P87:

P90 to P97:

RESET:

SCK10:

Port 2

Port 8

Port 9

Reset

Serial Clock

SI10:

SO10:

TI:

V

DD0

,V

DD1

: Power Supply

V

LOAD

:

V

PP

:

V

SS0

:

X1, X2:

Serial Input

Serial Output

Remote Control Timer Input

Negative Power Supply

Programming Power Supply

Ground

Crystal (Main System Clock)

XT1, XT2: Crystal (Subsystem Clock)

Preliminary User’s Manual U14938EJ1V0UM

19

CHAPTER 1 GENERAL

1.5 78K/0S Series Lineup

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

44-pin

42/44-pin

30-pin

28-pin

Products in mass production

Products under development

Y Subseries products support SMB.

Small-scale package, general-purpose applications

µ

PD789046

µ

PD789026

µ

µ

PD789074

PD789014

On-chip UART and capable of low voltage (1.8 V) operation

78K/0S

Series

80-pin

80-pin

64-pin

64-pin

64-pin

64-pin

64-pin

64-pin

44-pin

44-pin

30-pin

30-pin

30-pin

30-pin

30-pin

30-pin

44-pin

52-pin

144-pin

88-pin

52-pin

52-pin

44-pin

44-pin

20-pin

20-pin

Small-scale package, general-purpose applications and A/D converter

µ

µ

PD789177

PD789167

µ

PD789156

µ

µ

PD789146

PD789134A

µ

PD789124A

µ

PD789114A

µ

PD789104A

µ

PD789177Y

µ

PD789167Y

Inverter control

µ

PD789842

On-chip Inverter controller and UART

VFD drive

µ

PD789871

LCD drive

µ

µ

PD789417A

PD789407A

µ

PD789456

µ

µ

PD789446

PD789436

µ

PD789426

µ

µ

PD789316

PD789306

Dot LCD drive

µ

PD789835

µ

PD789830

ASSP

µ

PD789467

µ

PD789327

µ

PD789800

µ

µ

PD789840

PD789861

µ

PD789860

Display output total: 25

Basic subseries for LCD drive

Segment/common output: 96

Segments: 40, commons: 16

For remote controller, on-chip LCD controller/driver

For keyboard, on-chip USB function

For keypad, on-chip POC

For keyless entry, on-chip POC and key return circuit

20

Preliminary User’s Manual U14938EJ1V0UM

CHAPTER 1 GENERAL

The major functional differences among the subseries are listed below.

Function

ROM

Capacity

8-Bit 16-Bit

Watch WDT

8-Bit

A/D

10-Bit

A/D

Subseries Name

Small-scale package generalpurpose applications

µ

µ

PD789046 16 K

PD789026

µ

PD789074

µ

PD789014

4 K to 16 K

2 K to 8 K

2 K to 4 K

Small-scale package generalpurpose applications and A/D converter

µ

PD789177

µ

PD789167

µ

PD789156

µ

µ

PD789146

PD789134A

µ

PD789124A

µ

PD789114A

16 K to 24 K

8 K to 16 K

2 K to 8 K

Inverter control

µ

PD789104A

µ

PD789842 8 K to 16 K

For LCD driving

µ

PD789871

µ

PD789417A

4 K to 8 K

12K to

µ

PD789407A 24 K

µ

PD789456

µ

PD789446

12K to

16 K

µ

PD789436

µ

PD789426

µ

PD789316 8 K to 16 K

1 ch

2 ch

1 ch 1 ch 1 ch

3 ch 1 ch

1 ch

3 ch

Note

3 ch

3 ch

2 ch

1 ch

1 ch

1 ch

1 ch

1 ch

1 ch

1 ch

8 ch

4 ch

4 ch

4 ch

1 ch 8 ch

7 ch

6 ch

6 ch

8 ch

1 ch (UART:

1 ch)

4 ch

4 ch

4 ch

6 ch

6 ch

Serial

Interface

1 ch (UART:

1 ch)

1 ch (UART:

1 ch)

1 ch

7 ch

1 ch (UART:

1 ch)

2 ch (UART:

1 ch)

For Dot

LCD driving

µ

PD789306

µ

PD789835 12K to

60 K

24 K

6 ch

1 ch

1 ch

1 ch 1 ch 3 ch

1 ch (UART:

1 ch)

ASSP

µ

PD789830

µ

PD789467

µ

PD789327

µ

PD789800

4 K to 24 K 2 ch

8 K

1 ch

1 ch 1 ch

1 ch

2 ch (USB:

1 ch)

µ

PD789840

µ

PD789861 4 K

4 ch

1 ch

µ

PD789860

24

22

31

20

30

40

V

DD

I/O

MIN.

Value

34 1.8 V

30 4.0 V

33 2.7 V

43 1.8 V

23

28 1.8 V

RC-oscillation version

30 2.7 V

18 1.8 V

On-chip LCD

21

31 4.0 V

29 2.8 V

Remarks

On-chip

EEPROM

RC-oscillation version

14 1.8 V

RC-oscillation version, on-chip

EEPROM

On-chip

EEPROM

Note 10-bit timer: 1 channel

Preliminary User’s Manual U14938EJ1V0UM

21

CHAPTER 1 GENERAL

1.6 Block Diagram

TI/P25

8-bit remote control timer 50

8-bit timer 80

78K/0S

CPU core

ROM

8-bit timer 81

Watch timer

Watchdog timer

Serial interface10

RAM

512 bytes

VFD controller/ driver

SO10/P21

SI10/P22

SCK10/P20

INTP0/P23

INTP1/P24

Interrupt control

V

DD0

V

SS0

IC

(V

PP

)

Remarks 1. The internal ROM capacity varies depending on the product.

2. The parenthesized values apply to

µPD78F9872.

System control

Port0

Port1

Port2

Port8

Port9

P00 to P07

P10 to P12

P20 to P25

P80 to P87

P90 to P97

FIP0 to FIP8

FIP9/P97 to

FIP16/P90

FIP17/P87 to

FIP24/P80

V

LOAD

V

DD1

RESET

X1

X2

XT1

XT2

22

Preliminary User’s Manual U14938EJ1V0UM

CHAPTER 1 GENERAL

An outline of the timer is shown below.

Operation mode Interval timer

Function Pulse width measurement

Interrupt sources

8-Bit Remote

Control Timer

1 input

3

8-Bit

Timer

1 channel

2

Watch Timer

1 channel

Note 1

1

Watchdog

Timer

1 channel

Note 2

1

Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time.

2. The watchdog timer has the watchdog timer and interval timer function. However, use the watchdog timer by selecting either the watchdog timer function or interval timer function.

1.7 Overview of Functions

Internal memory

Item

ROM

High-speed RAM

VFD display RAM

Minimum instruction execution time

General-purpose registers

Instruction set

µPD789870

Mask ROM

µPD789871 µPD78F9872

Flash memory

4 KB

512 bytes

8 KB 16 KB

96 bytes

• 0.4

µs/1.6 µs (@ 5.0 MHz operation with main system clock)

•122

µs (@ 32.768 kHz operation with subsystem clock)

8 bits

× 8 registers

• 16-bit operations

I/O ports

VFD controller/driver Display output total: 25

Serial interfaces 3-wire serial I/O:

Timers

Vectored interrupt sources

Power supply voltage

Maskable

Non-maskable

• Bit manipulations (such as set, reset, and test)

Total:

• CMOS I/O:

33

17

• P-ch open-drain I/O:

• P-ch open-drain output:

• 8-bit remote control timer:

• 8-bit timer:

• Watch timer:

• Watchdog timer:

Internal: 8, external: 4

Internal: 1

8

8

1 channel

1 channel

2 channels

1 channel

1 channel

Operating ambient temperature

Package

V

DD

= 2.7 to 5.5 V (in normal operation)

V

DD

= 4.5 to 5.5 V (in VFD operation)

T

A

= –40 to +85

°C

52-pin plastic LQFP (10

× 10)

Preliminary User’s Manual U14938EJ1V0UM

23

CHAPTER 2 PIN FUNCTIONS

2.1 List of Pin Functions

(1) Port pins

Pin Name

P00 to P07 I/O

I/O

P10 to P12 I/O

P20

P21

P22

P23

P24

P25

P80 to P87

I/O

I/O

P90 to P97 Output

Function

Port 0.

8-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0).

Port 1.

3-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0).

Port 2.

6-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B2 (PUB2).

After Reset Alternate Function

Input —

Input

Input SCK10

SO10

SI10

INTP0

INTP1

TI

FIP24 to FIP17 Port 8.

P-ch open-drain 8-bit high-tolerance I/O port.

For mask ROM versions, use of a pull-down resistor for V

LOAD

can be specified in 1-bit units by a mask option (when used as a general-purpose I/O port, the pull-down resistor is connected to V

SS0

).

Port 9

P-ch open-drain 8-bit high-tolerance output port.

Mask ROM versions include an on-chip pull-down resistor (connected to V

LOAD

).

Output

Output FIP16 to FIP9

24

Preliminary User’s Manual U14938EJ1V0UM

CHAPTER 2 PIN FUNCTIONS

(2) Non-port pins

X1

X2

XT1

XT2

V

LOAD

V

DD0

V

DD1

V

SS0

RESET

IC

Pin Name

INTP0

INTP1

SI10

SO10

SCK10

TI

FIP0 to FIP8

FIP9 to FIP16

FIP17 to FIP24

Note

V

PP

I/O

Input

Input

Output

I/O

Input

Output

Input

Input

Input

Serial interface serial data input

Serial interface serial data output

Serial interface serial clock input/output

Timer input to 8-bit remote control timer

VFD controller/driver high-tolerance high current output

Function

External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified

Connecting crystal resonator for main system clock oscillation

Connecting crystal resonator for Subsystem clock oscillation

Connecting pull-down resistor of VFD controller/driver

Positive power supply for ports

Positive power supply for VFD controller/driver

Ground potential

System reset input

Internally connected. Connect directly to V

SS0

.

Sets flash memory programming mode. Applies high voltage when a program is written or verified. Connect directly to V

SS0

in normal operation mode.

Input

After Reset Alternate Function

Input P23

Input

Input

Input

Input

P24

P22

P21

P20

P25

Output —

P97 to P90

P87 to P80

— —

— —

Note

Pins set as P-ch open-drain I/O port by a mask option cannot be used as VFD controller/driver.

Preliminary User’s Manual U14938EJ1V0UM

25

CHAPTER 2 PIN FUNCTIONS

2.2 Description of Pin Functions

2.2.1 P00 to P07 (Port 0)

These pins constitute an 8-bit I/O port and can be set in input or output port mode in 1-bit units by using port mode register 0 (PM0). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0) in port units.

2.2.2 P10 to P12 (Port 1)

These pins constitute a 3-bit I/O port and can be set in input or output port mode in 1-bit units by port mode register

1 (PM1). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0) in port units.

2.2.3 P20 to P25 (Port 2)

These pins constitute a 6-bit I/O port. In addition, these pins enable timer input serial interface data I/O, and external interrupt input.

Port 2 can be specified in the following operation modes in 1-bit units.

(1) Port mode

In this mode, port 2 functions as a 6-bit I/O port. Port 2 can be set in the input or output mode in 1-bit units by port mode register 2 (PM2). When used as an input port, use of an on-chip pull-up resist can be specified by pull-up resistor option register B2 (PUB2) in 1-bit units.

(2) Control mode

In this mode, P20 to P25 function as the timer input, serial interface data I/O, and external interrupt input.

(a) TI

This is the timer input pin of 8-bit remote control timer.

(b) SI10, SO10

These are the serial data I/O pins of the serial interface.

(c) SCK10

This is the serial clock I/O pin of the serial interface.

(d) INTP0, INTP1

These are the external interrupt input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified.

2.2.4 P80 to P87 (Port 8)

These pins constitute an 8-bit P-ch open-drain I/O port. In addition, they also function as VFD controller/driver outputs. Port 8 can be specified in the following operation mode in 1-bit units.

(1) Port mode

In this mode, port 8 functions as an 8-bit P-ch open-drain I/O Port. Port 8 can be set in the input or output port mode in 1-bit units by port mode register 8 (PM8).

26

(2) Control mode

In this mode, these pins function as VFD controller/driver outputs (FIP17 to FIP24). For mask ROM versions, use of a pull-down resistor for V

LOAD

can be specified by a mask option.

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CHAPTER 2 PIN FUNCTIONS

2.2.5 P90 to P97 (Port 9)

These pins constitute an 8-bit P-ch open-drain I/O port. In addition, they also function as VFD controller/driver outputs. Port 9 can be specified in the following operation modes in 1-bit units.

(1) Port mode

In this mode, port 9 functions as a P-ch open-drain I/O port. Port 9 can be set in the input or output port mode in 1-bit units by port mode register 9 (PM9).

(2) Control mode

In this mode, these pins function as VFD controller/driver outputs (FIP9 to FIP16). Mask ROM versions include an on-chip pull-down resistor (connected to V

LOAD

).

2.2.6 FIP0 to FIP8

These pins are output pins for the VFD controller/driver.

2.2.7 RESET

This pin inputs an active-low system reset signal.

2.2.8 X1, X2

These pins are used to connect a crystal resonator for main system clock oscillation.

2.2.9 XT1, XT2

These pins are used to connect a crystal resonator for subsystem clock oscillation.

2.2.10 V

DD0

This is the positive power supply pin.

2.2.11 V

DD1

This is the positive power supply pin for VFD controller/driver.

2.2.12 V

LOAD

This pin is used to connect a pull-down resistor of VFD controller/driver.

2.2.13 V

SS0

This is the ground pin.

2.2.14 V

PP

(

µPD78F9872 only)

A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified.

Directly connect this pin to V

SS0

in the normal operation mode.

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CHAPTER 2 PIN FUNCTIONS

2.2.15 IC (mask ROM version only)

The IC (Internally Connected) pin is used to set the

µPD789870 and µPD789871 in the test mode before shipment.

In the normal operation mode, directly connect this pin to the V

SS0

pin with as short a wiring length as possible.

If a potential difference is generated between the IC pin and V

SS0

pin due to a long wiring length, or an external noise superimposed on the IC pin, the user program may not run correctly.

Directly connect the IC pin to the V

SS0

pin.

V

SS0

IC

Keep short

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CHAPTER 2 PIN FUNCTIONS

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The I/O circuit type for each pin and recommended connection of unused pins are shown in Table 2-1.

For the input/output circuit configuration of each type, see Figure 2-1.

Pin Name

P00 to P07

P10 to P12

P20/SCK10

P21/SO10

P22/SI10

P23/INTP0

P24/INTP1

P25/TI

FIP0 to FIP8

FIP9/P97 to FIP16/P90

FIP17/P87 to FIP24/P80

(Mask ROM version)

FIP17/P87 to FIP24/P80

(Flash memory version)

RESET

IC

V

PP

Table 2-1. Types of Pin I/O Circuits

I/O Circuit Type

5-H

I/O

I/O

Recommended Connection of Unused Pins

Input: Independently connect to V

DD0

or V

SS0

via a resistor.

Output: Leave open.

8-C

5-H

8-C

14-F

15-G

15-H

2

Output Leave open.

I/O

Input

Connect directly to V

SS0

.

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CHAPTER 2 PIN FUNCTIONS

Type 2

Figure 2-1. Pin I/O Circuits

Type 14-F

V

DD0

P-ch

V

DD1

P-ch

IN data

OUT

N-ch R

3

V

LOAD

Type 5-H

Pull-up enable

Output disable

Input enable

Type 8-C

Pull-up enable

Output disable

V

SS0

Schmitt-triggered input with hysteresis characteristics.

Data

Data

V

DD0

V

DD0

P-ch

P-ch

IN/OUT

V

SS0

N-ch

resistor at FIP9/P97 to FIP16/P90.

Type 15-G

V

DD0

P-ch

V

DD1

P-ch

Data

N-ch

V

SS0

V

DD0

P-ch

V

DD0

P-ch

IN/OUT

Type 15-H

Data

IN/OUT

(Mask option)

V

LOAD

V

SS0

V

DD0

P-ch

V

DD1

P-ch

IN/OUT

N-ch

V

SS0

P-ch

High-voltage transistor

V

SS0

N-ch

V

SS0

RD

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CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

The

µPD789871 Subseries can access 64 KB of memory space. Figures 3-1 to 3-3 show the memory maps.

Figure 3-1. Memory Map (

µPD789870)

F F F F H

Special function registers

256

× 8 bits

F F 0 0 H

F E F F H

Internal high-speed RAM

512

× 8 bits

Data memory space

F D 0 0 H

F C F F H

F A 6 0 H

F A 5 F H

F A 0 0 H

F 9 F F H

1 0 0 0 H

0 F F F H

Reserved

VFD display RAM

96

× 8 bits

Reserved

0 F F F H

Program memory space

0 0 0 0 H

Internal ROM

4,096

× 8 bits

0 0 8 0 H

0 0 7 F H

0 0 4 0 H

0 0 3 F H

0 0 1 C H

0 0 1 B H

0 0 0 0 H

Program area

CALLT table area

Program area

Vector table area

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-2. Memory Map (

µPD789871)

F F F F H

F F 0 0 H

F E F F H

Special function registers

256

× 8 bits

Internal high-speed RAM

512

× 8 bits

Data memory space

F D 0 0 H

F C F F H

F A 6 0 H

F A 5 F H

F A 0 0 H

F 9 F F H

2 0 0 0 H

1 F F F H

Reserved

VFD display RAM

96

× 8 bits

Reserved

1 F F F H

Program memory space

0 0 0 0 H

Internal ROM

8,192

× 8 bits

0 0 8 0 H

0 0 7 F H

0 0 4 0 H

0 0 3 F H

0 0 1 C H

0 0 1 B H

0 0 0 0 H

Program area

CALLT table area

Program area

Vector table area

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CHAPTER 3 CPU ARCHITECTURE

Data memory space

Figure 3-3. Memory Map (

µPD78F9872)

F F F F H

F F 0 0 H

F E F F H

Special function registers

256

× 8 bits

Internal high-speed RAM

512

× 8 bits

F D 0 0 H

F C F F H

F A 6 0 H

F A 5 F H

F A 0 0 H

F 9 F F H

4 0 0 0 H

3 F F F H

Reserved

VFD display RAM

96

× 8 bits

Reserved

3 F F F H

Program memory space

0 0 0 0 H

Flash memory

16,384

× 8 bits

0 0 8 0 H

0 0 7 F H

0 0 4 0 H

0 0 3 F H

0 0 1 C H

0 0 1 B H

0 0 0 0 H

Program area

CALLT table area

Program area

Vector table area

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CHAPTER 3 CPU ARCHITECTURE

3.1.1 Internal program memory space

The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC).

The

µPD789871 Subseries provides the following internal ROMs (or flash memory) containing the following capacities.

µPD789870

µPD789871

µPD78F9872

Part Number

Table 3-1. Internal ROM Capacity

Structure

Mask ROM

Flash memory

Internal ROM

Capacity

4,096

× 8 bits

8,192

× 8 bits

16,384

× 8 bits

The following areas are allocated to the internal program memory space:

(1) Vector table area

A 28-byte area of addresses 0000H to 001BH is reserved as a vector table area. This area stores program start addresses to be used when branching by the RESET input or an interrupt request generation. Of a 16bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address.

Vector Table Address

0000H

0004H

0006H

0008H

000AH

000CH

000EH

Interrupt Request

RESET input

INTWDT

INTP0

INTP1

INTTM50

INTTM51

INTTM52

Table 3-2. Vector Table

Vector Table Address

0010H

0012H

0014H

0016H

0018H

001AH

Interrupt Request

INTKS

INTCSI10

INTTM80

INTTM81

INTWT

INTWTI

(2) CALLT instruction table area

In a 64-byte area of addresses 0040H to 007FH, the subroutine entry address of a 1-byte call instruction

(CALLT) can be stored.

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CHAPTER 3 CPU ARCHITECTURE

3.1.2 Internal data memory (internal high-speed RAM) space

The

µPD789871 Subseries provides following internal RAMs.

(1) Internal high-speed RAM

An Internal high-speed RAM is incorporated in the area of FD00H to FEFFH. This RAM can also be used as a stack.

(2) VFD display RAM

A VFD display RAM is allocated to the area of FA00H to FA5FH (96 bytes). This RAM can also be used as an ordinary RAM.

3.1.3 Special function register (SFR) area

Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (refer to Table 3-3).

3.1.4 Data memory addressing

The

µPD789871 Subseries provides a variety of addressing modes which take account of memory manipulability, etc. Especially at addresses corresponding to data memory area (FE00H to FEFFH), particular addressing modes are possible to meet the functions of the special function registers (SFRs) and general-purpose registers. Figures

3-4 to 3-6 show the data memory addressing modes.

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-4. Data Memory Addressing (

µPD789870)

FFFFH

FF20H

FF1FH

FF00H

FEFFH

Special function registers (SFRs)

256

× 8 bits

SFR addressing

Internal high-speed RAM

512

× 8 bits

Short direct addressing

FE20H

FE1FH

FD00H

FCFFH

Reserved

FA60H

FA5FH

VFD display RAM

96

× 8 bits

Direct addressing

Register indirect addressing

Based addressing

FA00H

F9FFH

Reserved

1000H

0FFFH

Internal ROM

4,096

× 8 bits

0000H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-5. Data Memory Addressing (

µPD789871)

FFFFH

FF20H

FF1FH

FF00H

FEFFH

Special function registers (SFRs)

256

× 8 bits

SFR addressing

Internal high-speed RAM

512

× 8 bits

FE20H

FE1FH

FD00H

FCFFH

Reserved

FA60H

FA5FH

VFD display RAM

96

× 8 bits

FA00H

F9FFH

Reserved

2000H

1FFFH

Internal ROM

8,192

× 8 bits

0000H

Short direct addressing

Direct addressing

Register indirect addressing

Based addressing

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-6. Data Memory Addressing (

µPD78F9872)

FFFFH

FF20H

FF1FH

FF00H

FEFFH

Special function registers (SFRs)

256

× 8 bits

SFR addressing

Internal high-speed RAM

512

× 8 bits

FE20H

FE1FH

FD00H

FCFFH

Reserved

FA60H

FA5FH

VFD display RAM

96

× 8 bits

FA00H

F9FFH

Reserved

4000H

3FFFH

Flash memory

16,384

× 8 bits

0000H

Short direct addressing

Direct addressing

Register indirect addressing

Based addressing

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3.2 Processor Registers

The

µPD789871 Subseries provides the following on-chip processor registers:

3.2.1 Control registers

The control registers contain special functions to control the program sequence statuses and stack memory. The program counter, program status word, and stack pointer are control registers.

(1) Program counter (PC)

The program counter is a 16-bit register which holds the address information of the next program to be executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents is set.

RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 3-7. Program Counter Configuration

15 0

PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.

Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions.

RESET input sets the PSW to 02H.

Figure 3-8. Program Status Word Configuration

PSW

7

IE Z 0 AC 0 0 1

0

CY

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CHAPTER 3 CPU ARCHITECTURE

(a) Interrupt enable flag (IE)

This flag controls interrupt request acknowledge operations of CPU.

When IE = 0, the IE is set to interrupt disabled (DI) status. All interrupt requests except non-maskable interrupt are disabled.

When IE = 1, the IE is set to interrupt enabled (EI) status and interrupt request acknowledgement is controlled with an interrupt mask flag for various interrupt sources.

This flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.

(c) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to (1). It is reset (0) in all other cases.

(d) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.

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CHAPTER 3 CPU ARCHITECTURE

(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area.

Figure 3-9. Stack Pointer Configuration

15

SP SP15

0

SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory.

Each stack operation saves/restores data as shown in Figures 3-10 and 3-11.

Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before instruction execution.

Figure 3-10. Data to Be Saved to Stack Memory

PUSH rp instruction

CALL, CALLT instructions

Interrupt

SP SP _ 2

SP _ 2

SP _ 1

SP

Register pair lower

Register pair higher

SP SP _ 2

SP _ 2

SP _ 1

SP

PC7 to PC0

PC15 to PC8

SP SP _ 3

SP _ 3

SP _ 2

SP _ 1

SP

PC7 to PC0

PC15 to PC8

PSW

Figure 3-11. Data to Be Restored from Stack Memory

POP rp instruction

RET instruction RETI instruction

SP

SP + 1

SP SP + 2

Register pair lower

Register pair higher

SP

SP + 1

SP SP + 2

PC7 to PC0

PC15 to PC8

SP

SP + 1

SP + 2

SP SP + 3

PC7 to PC0

PC15 to PC8

PSW

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CHAPTER 3 CPU ARCHITECTURE

3.2.2 General-purpose registers

The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H).

Each register can be used as an 8-bit register, and in addition, two 8-bit registers in pairs can be used as a 16bit register (AX, BC, DE, and HL).

They can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3).

Figure 3-12. General-Purpose Register Configuration

(a) Absolute names

16-bit processing

RP3

15

RP2

RP1

RP0

0 7

8-bit processing

R7

R6

R5

R4

R3

R2

R1

R0

0

15

16-bit processing

HL

DE

BC

AX

(b) Functional names

0 7

8-bit processing

H

L

D

E

B

C

A

X

0

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3.2.3 Special function registers (SFRs)

Unlike general-purpose registers, special function registers have their own functions and are allocated to the 256byte area FF00H to FFFFH.

Special function registers can be manipulated, like general-purpose registers, with operation, transfer, and bit manipulation instructions. The bit units in which one register can be manipulated (1, 8, and 16) differ depending on the special function register type.

Each bit unit for manipulation can be specified as follows.

• 1-bit manipulation

A symbol reserved by assembler is described as the operand (sfr.bit) of a 1-bit manipulation instruction. This manipulation can also be specified with an address.

• 8-bit manipulation

A symbol reserved by assembler is described as the operand (sfr) of an 8-bit manipulation instruction. This manipulation can also be specified with an address.

• 16-bit manipulation

A symbol reserved by assembler is described as the operand of a 16-bit manipulation instruction. When specifying an address, describe an even address.

Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows:

• Symbol

Indicates the addresses of the implemented special function registers. The symbols shown in this column are the reserved words of the assembler, and have already been defined in the header file called “sfrbit.h” of the

C compiler. Therefore, these symbols can be used as instruction operands if assembler or integrated debugger is used.

• R/W

Indicates whether the special function register in question can be read or written.

R/W:

R:

W:

Read/write

Read only

Write only

• Bit units for manipulation

Indicates the bit units (1, 8, and 16) in which the special function register in question can be manipulated.

• After reset

Indicates the status of the special function register when the RESET signal is input.

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CHAPTER 3 CPU ARCHITECTURE

Address

FF32H

FF42H

FF4AH

FF50H

FF51H

FF53H

FF54H

FF55H

FF00H

FF01H

FF02H

FF08H

FF09H

FF20H

FF21H

FF22H

FF57H

FF58H

FF5AH

FF5BH

FF72H

Port 0

Port 1

Port 2

Port 8

Port 9

Port mode register 0

Port mode register 1

Port mode register 2

Pull-up register option register B2

Watchdog time clock select register

Watch time mode control register

8-bit compare register 80

8-bit timer counter 80

8-bit timer mode control register 80

8-bit compare register 81

8-bit timer counter 81

8-bit timer mode control register 81

Remote control timer control register 50

Remote control timer capture register 50

Remote control timer capture register 51

Serial operation mode register 11

FF74H

FFA0H

FFA1H

FFA2H

FFE0H

FFE1H

FFE4H

FFE5H

Transmit/receive shift register 10

Display mode register 0

Display mode register 1

Display mode register 2

Interrupt request flag register 0

Interrupt request flag register 1

Interrupt mask flag register 0

Interrupt mask flag register 1

FFECH External interrupt mode register 0

FFF0H Suboscillation mode register

FFF2H

FFF7H

Subclock control register

Pull-up register option register 0

FFF9H

FFFAH

FFFBH

Watchdog timer mode register

Oscillation stabilization timer select register

Processor clock control register

Table 3-3. Special Function Register List

Special Function Register (SFR) Name

P0

P1

P2

P8

P9

Symbol R/W Bit Units for Manipulation

PM0

PM1

PM2

PUB2

WDCS

WTM

CR80

TM80

TMC80

CR81

TM81

TMC81

TMC50

CP50

CP51

CSIM10

SIO10

DSPM0

DSPM1

DSPM2

IF0

IF1

MK0

MK1

INTM0

SCKM

CSS

PU0

WDTM

OSTS

PCC

R/W

W

R

R/W

W

R

R/W

R

R/W

1 Bit

8 Bits 16 Bits

After Reset

00H

FFH

00H

Undefined

00H

Undefined

00H

Undefined

10H

01H

00H

FFH

00H

04H

02H

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3.3 Instruction Address Addressing

An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (For details of each instruction, refer to 78K/0S Series User’s

Manual Instruction (U11047E)).

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign bit.

In other words, the range of branch in relative addressing is between –128 and +127 of the start address of the following instruction.

This function is carried out when the “BR $addr16” instruction or a conditional branch instruction is executed.

[Illustration]

15

15

α

PC

+

8 7 6

S

0

... PC is the start address of

the next instruction of

a BR instruction.

0 jdisp8

PC

15

When S = 0,

α indicates all bits “0”.

When S = 1,

α indicates all bits “1”.

0

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CHAPTER 3 CPU ARCHITECTURE

3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched.

This function is carried out when the “CALL !addr16 and BR !addr16” instructions are executed.

CALL !addr16 and BR !addr16 instructions can branch to all the memory spaces.

[Illustration]

In case of CALL !addr16, BR !addr16 instruction

7 0

CALL or BR

Low Addr.

High Addr.

PC

15 8 7 0

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3.3.3 Table indirect addressing

[Function]

Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.

Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can refer to the address stored in the memory table 40H to 7FH and branch to all the memory spaces.

[Illustration]

Instruction code

7 6

1 1

5 ta

4–0

1 0

1

Effective address

15

0

8 7

0 0 0 0 0 0 0 0

6 5

1

1 0

0

Effective address + 1

7 Memory (Table)

Low Addr.

High Addr.

0

PC

15 8 7 0

3.3.4 Register addressing

[Function]

Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched.

This function is carried out when the “BR AX” instruction is executed.

[Illustration]

rp

7

A

0 7

X

0

PC

15 8 7 0

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CHAPTER 3 CPU ARCHITECTURE

3.4 Operand Address Addressing

The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution.

3.4.1 Direct addressing

[Function]

The memory indicated by immediate data in an instruction word is directly addressed.

[Operand format]

Identifier addr16

Description

Label or 16-bit immediate data

[Description example]

MOV A, !FE00H; When setting !addr16 to FE00H

Instruction code 0 0 1 0 1 0 0 1 OP code

0 0 0 0 0 0 0 0 00H

1 1 1 1 1 1 1 0 FEH

[Illustration]

7 0

OP code addr16 (low) addr16 (high)

Memory

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3.4.2 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.

The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. An internal highspeed RAM and a special function register (SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.

The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of all SFR areas. In this area, ports which are frequently accessed in a program and a compare register of the timer/event counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to

1FH, bit 8 is set to 1. Refer to [Illustration].

[Operand format]

Identifier saddr saddrp

Description

Label or FE20H to FF1FH immediate data

Label or FE20H to FF1FH immediate data (even address only)

[Description example]

MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H

Instruction code 1 1 1 1 0 1 0 1 OP code

1 0 0 1 0 0 0 0 90H (saddr-offset)

0 1 0 1 0 0 0 0 50H (immediate data)

[Illustration]

7 0

OP code saddr-offset

Short direct memory

Effective address

15

1 1 1 1 1 1 1

8

α

When 8-bit immediate data is 20H to FFH, = 0.

When 8-bit immediate data is 00H to 1FH, = 1.

0

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CHAPTER 3 CPU ARCHITECTURE

3.4.3 Special function register (SFR) addressing

[Function]

Memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an instruction word.

This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.

[Operand format]

Identifier sfr Special function register name

Description

[Description example]

MOV PM0, A; When selecting PM0 for sfr

Instruction code 1 1 1 0 0 1 1 1

0 0 1 0 0 0 0 0

[Illustration]

7 0

OP code sfr-offset

SFR

Effective address

15

1 1 1 1 1 1 1 1

8 7

0

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CHAPTER 3 CPU ARCHITECTURE

3.4.4 Register addressing

[Function]

General-purpose registers are accessed as operands. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code.

Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.

[Operand format]

Identifier r rp

X, A, C, B, E, D, L, H

AX, BC, DE, HL

Description

‘r’ and ‘rp’ can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X,

A, C, B, E, D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; When selecting the C register for r

Instruction code 0 0 0 0 1 0 1 0

0 0 1 0 0 1 0 1

Register specify code

INCW DE; When selecting the DE register pair for rp

Instruction code 1 0 0 0 1 0 0 0

Register specify code

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CHAPTER 3 CPU ARCHITECTURE

3.4.5 Register indirect addressing

[Function]

The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier

— [DE], [HL]

Description

[Description example]

MOV A, [DE]; When selecting register pair [DE]

Instruction code 0 0 1 0 1 0 1 1

[Illustration]

DE

15

D

8 7

The contents of addressed memory are transferred

7 0

A

7

E

0

0

Memory address specified by register pair DE

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CHAPTER 3 CPU ARCHITECTURE

3.4.6 Based addressing

[Function]

8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to

16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier

— [HL+byte]

Description

[Description example]

MOV A, [HL+10H]; When setting byte to 10H

Instruction code 0 0 1 0 1 1 0 1

0 0 0 1 0 0 0 0

3.4.7 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call, and RETURN instructions are executed or the register is saved/reset upon generation of an interrupt request.

Stack addressing enables to address the internal high-speed RAM area only.

[Description example]

In the case of PUSH DE

Instruction code 1 0 1 0 1 0 1 0

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CHAPTER 4 PORT FUNCTIONS

4.1 Functions of Ports

The

µPD789871 Subseries provides the ports shown in Figure 4-1, enabling various methods of control.

Numerous other functions are provided that can be used in addition to the digital I/O port function. For more information on these additional functions, refer to CHAPTER 2 PIN FUNCTIONS.

Figure 4-1. Port Types

P80 P00

Port 8 Port 0

Port 9

P87

P90

P07

P10

P12

P20

Port 1

Port 2

P97

P25

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Pin Name

P00 to P07 I/O

I/O

P10 to P12 I/O

P20

P21

P22

P23

P24

P25

P80 to P87

I/O

I/O

P90 to P97 Output

CHAPTER 4 PORT FUNCTIONS

Table 4-1. Port Functions

Function

Port 0.

8-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0).

Port 1.

3-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register 0 (PU0).

Port 2.

6-bit I/O port.

Input/output can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can be specified by means of pull-up resistor option register B2 (PUB2).

After Reset Alternate Function

Input —

Input

Input SCK10

SO10

SI10

INTP0

INTP1

TI

FIP24 to FIP17 Port 8.

P-ch open-drain 8-bit high-tolerance I/O port.

For mask ROM versions, use of a pull-down resistor for V

LOAD

can be specified in 1-bit units by a mask option (when used as a general-purpose I/O port, the pull-down resistor is connected to V

SS0

).

Port 9

P-ch open-drain 8-bit high-tolerance output port.

Mask ROM versions include an on-chip pull-down resistor (connected to V

LOAD

).

Output

Output FIP16 to FIP9

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CHAPTER 4 PORT FUNCTIONS

4.2 Port Configuration

A port consists of the following hardware.

Parameter

Control register

Port

Pull-up resistor

Pull-down resistor

Table 4-2. Configuration of Port

Configuration

Port mode register (PMm: m = 0 to 2)

Pull-up resistor option register 0 (PU0)

Pull-up option register B2 (PUB2)

Total:

CMOS I/O:

33

17

P-ch open-drain I/O: 8

P-ch open-drain output: 8

17 (software control)

• Mask ROM versions: 16 (8 of these can be specified by the mask option)

• Flash memory versions: None

4.2.1 Port 0

This is a 8-bit I/O port with output latches. Port 0 can be specified as input or output mode in 1-bit units by using port mode register 0 (PM0). When pins P00 to P07 are used as input port pins, on-chip pull-up resistors can be connected in 8-bit units by using pull-up resistor option register 0 (PU0).

RESET input sets port 0 to input mode.

Figure 4-2 shows the block diagram of port 0.

Figure 4-2. Block Diagram of P00 to P07

V

DD0

WR

PU0

PU00

P-ch

RD

WR

PORT

WR

PM

Output latch

(P00 to P07)

PM00 to PM07

56

PU0:

PM:

RD:

WR:

Pull-up resistor option register 0

Port mode register

Port 0 read signal

Port 0 write signal

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P00 to P07

CHAPTER 4 PORT FUNCTIONS

4.2.2 Port 1

This is a 3-bit I/O port with output latches. Port 1 can be specified as input or output mode in 1-bit units by using port mode register 1 (PM1). When pins P10 to P12 are used as input port pins, on-chip pull-up resistors can be connected in 3-bit units by using pull-up resistor option register 0 (PU0).

RESET input sets port 1 to input mode.

Figure 4-3 shows the block diagram of port 1.

Figure 4-3. Block Diagram of P10 to P12

V

DD0

WR

PU0

PU01

P-ch

RD

WR

PORT

WR

PM

Output latch

(P10 to P12)

PM10 to PM12

PU0:

PM:

RD:

WR:

Pull-up resistor option register 0

Port mode register

Port 1 read signal

Port 1 write signal

P10 to P12

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CHAPTER 4 PORT FUNCTIONS

4.2.3 Port 2

This is a 6-bit I/O port with output latches. Port 2 can be specified as input or output mode in 1-bit units by using port mode register 2 (PM2). Use of on-chip pull-up resistors can be specified for pins P20 to P25 in 1-bit units by using pull-up resistor option register B2 (PUB2).

The port is also used as a serial interface I/O, remote control timer input, and external interrupt input.

RESET input sets port 2 to input mode.

Figures 4-4 to 4-6 show block diagrams of port 2.

Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set according to the function to be used. For how to set the latches, see Table 10-2 Serial Interface 10 Operating

Mode Settings.

Figure 4-4. Block Diagram of P20

V

DD0

WR

PUB2

PUB20

Alternate function

P-ch

RD

WR

PORT

WR

PM

Output latch

(P20)

PM20

Alternate function

P20/SCK10

PUB2: Pull-up resistor option register B2

PM: Port mode register

RD:

WR:

Port 2 read signal

Port 2 write signal

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WR

PUB2

RD

PUB21

CHAPTER 4 PORT FUNCTIONS

Figure 4-5. Block Diagram of P21

V

DD0

P-ch

WR

PORT

WR

PM

Output latch

(P21)

PM21

Alternate function

PUB2: Pull-up resistor option register B2

PM: Port mode register

RD:

WR:

Port 2 read signal

Port 2 write signal

P21/SO10

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CHAPTER 4 PORT FUNCTIONS

Figure 4-6. Block Diagram of P22 to P25

WR

PUB2

PUB22 to PUB25

Alternate function

RD

WR

PORT

WR

PM

Output latch

(P22 to P25)

PM22 to PM25

V

DD0

P-ch

P22/SI10,

P23/INTP0,

P24/INTP1,

P25/TI

PUB2: Pull-up resistor option register B2

PM: Port mode register

RD:

WR:

Port 2 read signal

Port 2 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.4 Port 8

This is an 8-bit P-ch open-drain I/O port with output latches. For mask ROM versions, use of a pull-down resistor for V

LOAD

can be specified by a mask option.

RESET input sets port 8 to input mode.

Figures 4-7 and 4-8 show block diagrams of port 8.

Figure 4-7. Block Diagram of P80 to P87 (

µPD789870, 789871)

V

DD1

WR

PORT

Output latch

(P80 to P87)

P-ch

P80/FIP24 to

P87/FIP17

Alternate function

RD

PORT

Mask option switch

V

LOAD

PM:

RD:

WR:

Port mode register

Port 8 read signal

Port 8 write signal

Figure 4-8. Block Diagram of P80 to P87 (

µPD78F9872)

V

DD1

WR

PORT

Output latch

(P80 to P87)

P-ch

Alternate function

P-ch

RD

PORT

P80/FIP24 to

P87/FIP17

PM:

RD:

WR:

Port mode register

Port 8 read signal

Port 8 write signal

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CHAPTER 4 PORT FUNCTIONS

4.2.5 Port 9

This is an 8-bit P-ch open-drain output port. Mask ROM versions include an on-chip pull-down resistor (connected to V

LOAD

).

RESET input sets port 9 to output mode.

Figures 4-9 and 4-10 show block diagrams of port 9.

Figure 4-9. Block Diagram of P90 to P97 (

µPD789870, 789871)

V

DD1

WR

PORT

Output latch

(P90 to P97)

P-ch

P90/FIP16 to

P97/FIP9

Alternate function

RD

PORT V

LOAD

WR

PORT

Figure 4-10. Block Diagram of P90 to P97 (

µPD78F9872)

V

DD1

Output latch

(P90 to P97)

P-ch

Alternate function

RD

PORT

P90/FIP16 to

P97/FIP9

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CHAPTER 4 PORT FUNCTIONS

4.3 Port Function Control Registers

The following three types of registers control the ports.

• Port mode registers (PM0 to PM2)

• Pull-up resistor option register 0 (PU0)

• Pull-up resistor option register B2 (PUB2)

(1) Port mode registers (PM0 to PM2)

These registers are used to set port input/output in 1-bit units.

Port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets these registers to FFH.

When port pins are used as alternate-function pins, set the port mode register and output latch according to

Table 4-3.

Caution As port 2 has an alternate function as external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to 1 beforehand.

P23

P24

P25

Table 4-3. Port Mode Register and Output Latch Settings When Using Alternate Functions

Pin Name Alternate Function

Name

PM

××

P

××

INTP0

INTP1

TI

Input/Output

Input

Input

Input

1

1

1

×

×

×

Caution When Port 2 is used for serial interface pin, the I/O latch or output latch must be set according to its function. For the setting method, refer to Table 10-2 Serial Interface 10 Operating Mode

Settings.

Remark

×: don’t care

PM

××: Port mode register

P

××:

Port output latch

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CHAPTER 4 PORT FUNCTIONS

Figure 4-11. Port Mode Register Format

Symbol

PM0

7 6 5 4 3 2 1 0

PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00

Address After reset

FF20H FFH

R/W

R/W

PM1 1 1 1 1 1 PM12 PM11 PM10 FF21H FFH R/W

PM2 1 1 PM25 PM24 PM23 PM22 PM21 PM20 FF22H FFH R/W

PMmn

0

1

Pmn pin I/O mode selection (m = 0 to 2, n = 0 to 7)

Output mode (output buffer ON)

Input mode (output buffer OFF)

(2) Pull-up resistor option register 0 (PU0)

Pull-up resistor option register (PU0) sets whether to use an on-chip pull-up resistor at each port or not.

At a port where use of on-chip pull-up resistors has been specified by PU0, a pull-up resistor can be internally used only for the bits set in input mode. On-chip pull-up resistors cannot be used for the bits set in output mode, regardless of setting of PU0, or when the pins are used as alternate-function output pins.

PU0 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears PU0 to 00H.

Symbol

PU0

7

0

6

0

5

0

Figure 4-12. Pull-Up Resistor Option Register 0 Format

4 3 2 <1> <0>

0 0 0 PU01 PU00

Address

FFF7H

After reset

00H

R/W

R/W

64

PU0m

Pm on-chip pull-up resistor selection (m = 0, 1)

On-chip pull-up resistor not used

0

1 On-chip pull-up resistor used

(3) Pull-up resistor option register B2 (PUB2)

Pull-up register option register B2 (PUB2) sets whether to use an on-chip resistor at each pin of port 2. At a pin for which use of on-chip pull-up resistors has been specified by PUB2, a pull-up resistor can be internally used only for the bits set in input mode. On-chip pull-up resistors cannot be used for the bits set in output mode, regardless of the setting of PUB2, or when the pins are used as alternate-function output pins.

PUB2 is set with a 1-bit or 8-bit manipulation instruction.

RESET input clears PUB2 to 00H.

Symbol

PUB2

7

0

Figure 4-13. Pull-Up Resistor Option Register B2 Format

6 <5> <4> <3> <2> <1> <0>

0 PUB25 PUB24 PUB23 PUB22 PUB21 PUB20

Address

FF32H

After reset

00H

R/W

R/W

PUB2n

P2n on-chip pull-up resistor selection (n = 0 to 5)

On-chip pull-up resistor not used

0

1 On-chip pull-up resistor used

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CHAPTER 4 PORT FUNCTIONS

4.4 Operation of Port Functions

The operation of a port differs depending on whether the port is set in input or output mode, as described below.

4.4.1 Writing to I/O port

(1) In output mode

A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port.

The data once written to the output latch is retained until new data is written to the output latch.

(2) In input mode

A value can be written to the output latch by using a transfer instruction. However, the status of the port pin is not changed because the output buffer is OFF.

The data once written to the output latch is retained until new data is written to the output latch.

Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined.

4.4.2 Reading from I/O port

(1) In output mode

The contents of the output latch can be read by using a transfer instruction. The contents of the output latch are not changed.

(2) In input mode

The status of a pin can be read by using a transfer instruction. The contents of the output latch are not changed.

4.4.3 Arithmetic operation of I/O port

(1) In output mode

An arithmetic operation can be performed with the contents of the output latch. The result of the operation is written to the output latch. The contents of the output latch are output from the port pins.

The data once written to the output latch is retained until new data is written to the output latch.

(2) In input mode

The contents of the output latch become undefined. However, the status of the pin is not changed because the output buffer is OFF.

Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined.

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CHAPTER 5 CLOCK GENERATOR

5.1 Clock Generator Functions

The clock generator generates the clock to be supplied to the CPU and peripheral hardware.

The following two types of system clock oscillators are used.

Main system clock (ceramic/crystal) oscillator

This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC).

Subsystem clock oscillator

This circuit oscillates at 32.768 kHz. Oscillation can be stopped by the suboscillation mode register (SCKM).

5.2 Clock Generator Configuration

The clock generator includes the following hardware.

Item

Control registers

Oscillators

Table 5-1. Configuration of Clock Generator

Configuration

Processor clock control register (PCC)

Suboscillation mode register (SCKM)

Subclock control register (CSS)

Main system clock oscillator

Subsystem clock oscillator

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CHAPTER 5 CLOCK GENERATOR

Figure 5-1. Block Diagram of Clock Generator

Internal bus

XT1

XT2

X1

X2

FRC SCC Suboscillation mode register

(SCKM)

Subsystem clock oscillator f

XT

Main system clock oscillator f

X

Prescaler f

X

2

2

1/2 f

XT

2

Prescaler

Watch timer

Clock to peripheral hardware

Standby controller

Wait controller

CPU clock

(f

CPU

)

STOP

MCC PCC1

Processor control register

(PCC)

CLS CSS0

Internal bus

Subclock control register (CSS)

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CHAPTER 5 CLOCK GENERATOR

5.3 Register Controlling Clock Generator

The clock generator is controlled by the following registers.

• Processor clock control register (PCC)

• Suboscillation mode register (SCKM)

• Subclock control register (CSS)

(1) Processor clock control register (PCC)

PCC sets the CPU clock selection and the division ratio.

PCC is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets the PCC to 02H.

Figure 5-2. Processor Clock Control Register Format

Symbol

PCC

7

MCC

6

0

5

0

4

0

3

0

2 1 0

0 PCC1 0

Address After reset

FFFBH 02H

R/W

R/W

MCC

0

Operation enabled

1 Operation stopped

Control of main system clock oscillator operation

CSS0 PCC1

0 0

0

1

1

0 f

X

µ f

X

/2 2

µ f

XT

µ

1 1

CPU clock (f

CPU

) selection

Note

Note

The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control register (PCC and the CSS0 flag in the subclock control register (CSS) (refer to 5.3 (3) subclock

control register (CSS)).

Cautions 1. Bit 0 and 2 to 6 must be set to 0.

2. The MCC can be set only when the subsystem clock has been selected as the CPU clock.

Remarks

1. f

X

: Main system clock oscillation frequency

2. f

XT

: Subsystem clock oscillation frequency

3. The parenthesized values apply to operation at f

X

= 5.0 MHz or f

XT

= 32.768 kHz.

4. Minimum instruction execution time: 2f

CPU

• f

CPU

= 0.2

µs: 0.4 µs

• f

CPU

= 0.8

µs: 1.6 µs

• f

CPU

= 61

µs: 122 µs

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(2) Suboscillation mode register (SCKM)

SCKM selects a the feedback resistor for the subsystem clock, and controls the oscillation of the clock.

SCKM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears SCKM to 00H.

Symbol

SCKM

7

0

6

0

5

0

4

0

Figure 5-3. Suboscillation Mode Register Format

3

0

2 1 0

0 FRC SCC

Address After reset

FFF0H 00H

R/W

R/W

FRC

0

1

On-chip feedback resistor used

On-chip feedback resistor not used

Feedback resistor selection

SCC

0

1

Operation enabled

Operation stopped

Control of subsystem clock oscillator operation

Caution Bit 2 to 7 must be set to 0.

(3) Subclock control register (CSS)

CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the

CPU clock operation status.

CSS is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CSS to 00H.

Symbol

CSS

7

0

Figure 5-4. Subclock Control Register Format

6

0

5 4 3

CLS CSS0 0

2

0

1

0

0

0

Address

FFF2H

After reset

00H

R/W

R/W

Note

CLS

0

CPU clock operation status

Operation based on the divided main system clock output

1 Operation based on the subsystem clock output

CSS0

0

Selection of the main system or subsystem clock oscillator

Divided output from the main system clock oscillator

1 Output from the subsystem clock oscillator

Note

Bit 5 read only.

Caution Bits 0 to 3, 6, and 7 must be set to 0.

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CHAPTER 5 CLOCK GENERATOR

5.4 System Clock Oscillators

5.4.1 Main system clock oscillator

The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins.

Figure 5-5 shows the external circuit of the main system clock oscillator.

Figure 5-5. External Circuit of Main System Clock Oscillator

V

SS0

X1

Crystal or ceramic resonator

X2

5.4.2 Subsystem clock oscillator

The subsystem clock oscillator by the crystal resonator (32.768 kHz TYP.) connected across the XT1 and XT2 pins.

Figure 5-6 shows the external circuit of the subsystem clock oscillator.

Figure 5-6. External Circuit of Subsystem Clock Oscillator

V

SS0

XT1

32.768

kHz

XT2

Crystal resonator

Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V

SS0

. Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

When using the subsystem clock, particular care is required because the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption.

Figure 5-7 shows examples of incorrect resonator connection.

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CHAPTER 5 CLOCK GENERATOR

Figure 5-7. Examples of Incorrect Resonator Connection (1/2)

(a) Tool long wiring (b) Crossed signal line

V

SS0

X1 X2

PORTn

(n = 0 to 2, 8, 9)

V

SS0

X1 X2

(c) Wiring near high fluctuating current

V

SS0

X1 X2

(d) Current flowing through ground line of oscillator

(potential at points A, B, and C fluctuates)

V

DD

V

SS0

X1

P mn

X2

High current

A B

High current

C

Remark

When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to the XT2 in series.

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CHAPTER 5 CLOCK GENERATOR

Figure 5-7. Examples of Incorrect Resonator Connection (2/2)

(e) Signal is fetched (f) Parallel and near signal lines of main

system clock and subsystem clock

V

SS0

X1 X2

V

SS0

X2 X1 XT2 XT1

XT2 is wired parallel to X1.

Remark

When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to the XT2 in series.

Caution If the X1 wire is in parallel with the XT2 wire, crosstalk noise may occur between the X1 and

XT2, resulting in a malfunction.

To avoid this, do not lay the X1 and XT2 wires in parallel.

5.4.3 Frequency divider

The frequency divider divides the output of the main system clock oscillator (f

X

) to generate various clocks.

5.4.4 When no subsystem clock is used

If a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation, handle the XT1 and XT2 pins as follows:

XT1: Connect to V

SS0

XT2: Leave open

In this case, however, a small leakage current flows via the on-chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the suboscillation mode register

(SCKM) so that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as stated above.

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5.5 Clock Generator Operation

The clock generator generates the following clocks and controls the operating modes of the CPU, such as the standby mode:

• Main System clock f

X

• Subsystem clock f

XT

• CPU clock f

CPU

• Clock to peripheral hardware

The operation and function of the clock generator is determined by the processor clock control register (PCC), suboscillation mode register (SCKM), and subclock control register (CSS), as follows.

(a) The low-speed mode 2f

CPU

(1.6

µs : at 5.0 MHz operation) of the main system clock is selected when the

RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the main system clock is stopped.

(b) Three types of CPU clocks f

CPU

(0.2

µs and 0.8 µs: main system clock (at 5.0 MHz operation), 61 µs: subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM, and CSS settings.

(c) Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system where no subsystem clock is used, setting SCKM bit 1 (FRC) so that the on-chip feedback resistor cannot be used reduces current consumption in STOP mode. In a system where a subsystem clock is used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation.

(d) CSS bit 4 (CSS0) can be used to select the subsystem clock so that low current consumption operation is used (122

µs : at 32.768 kHz operation).

(e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating using bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot.

(f) The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system clock, but the subsystem clock pulse is only supplied to the watch timer. The watch timer can therefore keep running even during standby. The other hardware stops when the main system clock stops because if runs based on the main system clock (except for the external input clock operations).

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CHAPTER 5 CLOCK GENERATOR

5.6 Changing Setting of System Clock and CPU Clock

5.6.1 Time required for switching between system clock and CPU clock

The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS).

Actually, the specified clock is not selected immediately after the setting of PCC has been changed, and the old clock is used for the duration of several instructions after that (see Table 5-2).

Table 5-2. Maximum Time Required for Switching CPU Clock

Set Value Before Switching

CSS0 PCC1

0

1

0

1

×

CSS0

0

2 clocks

2 clocks

PCC1

0

Set Value After Switching

CSS0 PCC1

0 1

4 clocks

2 clocks

CSS0

1

PCC1

×

2f

X

/f

XT

clocks

(306 clocks) f

X

/2f

XT

clocks

(76 clocks)

Remarks 1. Two clocks are the minimum instruction execution time of the CPU clock before switching.

2. The parenthesized values apply to operation at f

X

= 5.0 MHz or f

XT

= 32.768 kHz.

3.

×: don't care

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5.6.2 Switching between system clock and CPU clock

The following figure illustrates how the CPU clock and system clock switch.

Figure 5-8. Switching Between System Clock and CPU Clock

V

DD

RESET

Interrupt request signal

System clock

CPU clock f

X

Low-speed operation f

X

High-speed operation f

XT

Subsystem clock operation f

X

High-speed operation

Wait (6.55 ms: 5.0 MHz operation)

Internal reset operation

<1> The CPU is reset when the RESET pin is made low on power application. The reset state is released when the RESET pin is made high, and the main system clock starts oscillating. At this time, the oscillation stabilization time (2 15 /f

X

) is automatically secured.

After that, the CPU starts instruction execution at the low speed of the main system clock (1.6

µs: at 5.0 MHz operation).

<2> After the time required for the V

DD

voltage to rise to the level at which the CPU can operate at high speed has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS) are rewritten so that high-speed operation can be selected.

<3> A drop of the V

DD

voltage is detected with an interrupt request signal. The clock is switched to the subsystem clock (at this moment, the subsystem clock must be in the oscillation stabilization state).

<4> A recover of the V

DD

voltage is detected with an interrupt request signal. Bit 7 (MCC) of PCC is set to 0, and then the main system clock starts oscillating. After the time required for the oscillation to stabilize has elapsed, PCC1 and CSS0 are rewritten so that high-speed operation can be selected again.

Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.

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CHAPTER 6 8-BIT REMOTE CONTROL TIMER

6.1 8-Bit Remote Control Timer Functions

The 8-bit remote control timer has a pulse width measurement function with a resolution of 8 bits.

Pulse width is measured from a difference in count value when the valid edge has been detected while the timer operates in the free-running mode.

6.2 8-Bit Remote Control Timer Configuration

The 8-bit remote control timer consists of the following hardware.

Table 6-1. Configuration of 8-Bit Remote Control Timer

Item

Timer counter

Register

Control register

Configuration

8-bit timer (TM50)

Remote control timer capture register:

× 2 (CP50 and CP51)

Remote control timer control register 50 (TMC50)

TI/P25 f

X

/2

6 f

X

/2

7 f

X

/2

8 f

X

/2

9

Figure 6-1. Block Diagram of 8-Bit Remote Control Timer

Internal bus

INTTM50

Noise rejection

Rising edge detection

Remote control timer capture register 50

(CP50)

1/2

8-bit timer counter 50

(TM50)

Clear

INTTM52

INTTM51

Noise rejection

Falling edge detection

Remote control timer capture register 51

(CP51)

TCE50 TCL52 TCL51

Remote control timer control register 50 (TMC50)

Internal bus

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(1) Remote control timer capture registers (CP50 and CP51)

These 8-bit registers capture the contents of the 8-bit timer counter 50 (TM50).

The capture operation is performed in synchronization with the valid edge input to the TI pin (capture trigger).

The contents of CP50 are retained until the next rising edge of the TI pin is detected. The contents of CP51 are retained until the next falling edge of the TI pin is detected.

CP50 and CP51 can be read by using an 8-bit memory manipulation instruction.

RESET input clears CP50 and CP51 to 00H.

(2) 8-bit timer counter 50 (TM50)

This 8-bit register counts the count pulse.

RESET input or clearing the TCE50 bit clears TM50 to 00H.

6.3 Registers Controlling 8-Bit Remote Control Timer

The following register controls the 8-bit remote control timer.

(1) Remote control timer control register 50 (TMC50)

This register enables or disables the operation of the 8-bit timer counter 50 (TM50), and sets the count clock.

TMC50 is set by using a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC50 to 00H.

Figure 6-2. Remote Control Timer Control Register 50 Format

Symbol

TMC50

< 7 >

TCE50

6

0

5

0

4

0

3

0

2

0

1

TCL52

0

TCL51

Address

FF58H

After reset

00H

R/W

R/W

TCE50

0

1

TM50 count operation control

Clears counter to 0 and stops operation

Starts count operation

TCL52 TCL51

0 0

0

1

1

1

0

1 f

X

/2

9

(9.8 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

7

(39.1 kHz) f

X

/2

6

(78.1 kHz)

Caution Be sure to clear bits 2 to 6 to 0.

Count clock selection

Remarks 1. f

X

: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f

X

= 5.0 MHz

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CHAPTER 6 8-BIT REMOTE CONTROL TIMER

6.4 Operation of 8-Bit Remote Control Timer

The 8-bit remote control timer operates as a pulse width measuring circuit.

The width of a high-level or low-level external pulse input to the TI pin is measured by operating the 8-bit timer counter 50 (TM50) in the free-running mode.

Noise with short pulse width can be detected since the detection of the valid edge is sampled every 2 cycles of the count clock selected by TCL51 and TCL52, and the capture operation is not performed until the valid level has been detected two times. Therefore, the pulse width input to the TI pin must be 5 or more of the count clock set by

TCL51 and TCL52, regardless of whether the level is high or low. If the pulse width is less than 5 clocks, it cannot be detected, and the capture operation is not performed.

The value of timer register 50 (TM50) being counted is loaded to and retained in the capture registers (CP50 and

CP51) in synchronization with the valid edge of the pulse input to the TI pin, as shown in Figure 6-3.

Figure 6-3 shows the timing of pulse width measurement.

Figure 6-3. Pulse Width Measurement Timing (1/2)

(1) To measure pulse width in synchronization with rising edge

FFH FFH

Count value of TM50

D3

D1

D0

0H

TI

Count starts

TCE50 = 1

Capture

INTTM50

CP50

INTTM52

00H D0

Capture

D1

D2

Capture t0 t1

D2

Capture

D3

Remark

t0 = (D1 – D0)

× 1/f

COUNT t1 = (100H – D1 + D2)

× 1/f

COUNT f

COUNT

: Count clock frequency set by TCL51 and TCL52

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Figure 6-3. Pulse Width Measurement Timing (2/2)

(2) Measure pulse width in synchronization with both rising and falling edges

FFH FFH

Count value of TM50

D1

D0

0H

Count starts

Capture Capture Capture

TCE50 = 1

D2

TI

INTTM50

INTTM51

CP50

CP51

INTTM52

00H

00H

D0

D1 t0

D2 t1

D3

Capture

D3

Remark

t0 = (D2 – D1)

× 1/f

COUNT t1 = (100H – D2 + D3)

× 1/f

COUNT f

COUNT

: Count clock frequency set by TCL51 and TCL52

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CHAPTER 7 8-BIT TIMER

7.1 8-Bit Timer Functions

The 8-bit timers (TM80 and TM81) enable to use the interval function.

(1) 8-bit interval timer

(1) 8-bit interval timer

When the 8-bit timer is used as an interval timer, it generates an interrupt at any time intervals set in advance.

Minimum Interval Time

2

2

/f

X

(0.8

µs)

2

4

/f

X

(3.2

µs)

2

6

/f

X

(12.8

µs)

Table 7-1. Interval Time of 8-Bit Timer 80

Maximum Interval Time

2

10

/f

X

(204.8

µs)

2

12

/f

X

(819.2

µs)

2

4

/f

X

(3.28 ms)

2

2

/f

X

(0.8

µs)

2

4

/f

X

(3.2

µs)

2

6

/f

X

(12.8

µs)

Resolution

Remarks

1. f

X

: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f

X

= 5.0 MHz.

Minimum Interval Time

2/f

X

(0.4

µs)

2

5

/f

X

(6.4

µs)

2

7

/f

X

(25.6

µs)

Table 7-2. Interval Time of 8-Bit Timer 81

Maximum Interval Time

2

8

/f

X

(51.2

µs)

2

13

/f

X

(1.64 ms)

2

15

/f

X

(6.55 ms)

2/f

X

(0.4

µs)

2

5

/f

X

(6.4

µs)

2

7

/f

X

(25.6

µs)

Resolution

Remarks

1. f

X

: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f

X

= 5.0 MHz.

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7.2 8-Bit Timer Configuration

The 8-bit timer consists of the following hardware.

Timer counter

Register

Control register

Item

Table 7-3. Configuration of 8-Bit Timer

Configuration

8 bits

× 2 (TM80 and TM81)

Compare register: 8 bits

× 2 (CR80 and CR81)

8-bit timer mode control registers 80 and 81 (TMC80 and TMC81)

Figure 7-1. Block Diagram of 8-Bit Timer 80

Internal bus f

X

/2

2 f

X

/2

4 f

X

/2

6

2

8-bit compare register 80

(CR80)

Match

8-bit timer counter 80

(TM80)

Clear

Selector

INTTM80

TCE80 TCL801 TCL800

8-bit timer mode control register 80 (TMC80)

Internal bus

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81

82

f

X

/2 f

X

/2

5 f

X

/2

7

2

CHAPTER 7 8-BIT TIMER

Figure 7-2. Block Diagram of 8-Bit Timer 81

Internal bus

8-bit compare register 81

(CR81)

Match

8-bit timer counter 81

(TM81)

Clear

Selector

INTTM81

TCE81 TCL811 TCL810

8-bit timer mode control register 81 (TMC81)

Internal bus

(1) 8-bit compare register 8n (CR8n)

This is an 8-bit register to compare the value set to CR8n with 8-bit timer counter 8n (TM8n) count value, and if they match, generates an interrupt request (INTTM8n).

CR8n is set with an 8-bit memory manipulation instruction. The 00H to FFH values can be set.

RESET input makes CR8n undefined.

Caution Be sure to set CR8n after the timer operation is stopped.

Remark

n = 0 or 1

(2) 8-bit timer counter 8n (TM8n)

This is an 8-bit register to count pulses.

TM8n is read with an 8-bit memory manipulation instruction.

RESET input clears TM8n to 00H.

Remark

n = 0 or 1

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CHAPTER 7 8-BIT TIMER

7.3 Registers Controlling 8-Bit Timer

The following register is used to control the 8-bit timer.

• 8-bit timer mode control registers 80 and 81 (TMC80 and TMC81)

(1) 8-bit timer mode control register 80 (TMC80)

This register enables/stops operation of 8-bit timer counter 80 (TM80) and sets the counter clock of 8-bit timer

80.

TMC80 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC80 to 00H.

Symbol

<7> 6

TMC80 TCE80 0

5

0

Figure 7-3. 8-Bit Timer Mode Control Register 80 Format

4

0

3 2 1 0

0

TCL801TCL800

0

Address After reset

FF53H 00H

R/W

R/W

TCE80 8-bit timer counter 80 operation control

Operation stopped (TM80 cleared to 0)

0

1 Operation enabled

TCL801 TCL800

0 0

0

1

1

1

0

1 f

X

/2

2

(1.25 MHz) f

X

/2

4

(312.5 kHz) f

X

/2

6

(78.1 kHz)

Setting prohibited

8-bit timer 80 count clock selection

Caution Be sure to set the count clock after the timer operation is stopped (TCE80 = 0).

Refer to 7.4 8-Bit Timer Operation for details.

Remarks

1. f

X

: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f

X

= 5.0 MHz.

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CHAPTER 7 8-BIT TIMER

(2) 8-bit timer mode control register 81 (TMC81)

This register enables/stops operation of 8-bit timer counter 81 (TM81), sets the count clock of 8-bit timer 81, and controls the operation of the output control circuit.

TMC81 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC81 to 00H.

Symbol <7> 6

TMC81 TCE81 0

5

0

Figure 7-4. 8-Bit Timer Mode Control Register 81 Format

4

0

3 2 1 0

0

TCL811TCL810

0

Address After reset

FF57H 00H

R/W

R/W

TCE81

0

1

8-bit timer counter 81 operation control

Operation stopped (TM81 cleared to 0)

Operation enabled

TCL811 TCL810

0 0

0

1

1

1

0

1 f

X

/2 (2.5 MHz) f

X

/2

5

(156.3 kHz) f

X

/2

7

(39.1 kHz)

Setting prohibited

8-bit timer 81 count clock selection

Caution Be sure to set the count clock after the timer operation is stopped (TCE81 = 0).

Refer to 7.4 8-Bit Timer Operation for details.

Remarks

1. f

X

: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f

X

= 5.0 MHz.

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7.4 8-Bit Timer Operation

7.4.1 Operation as interval timer

Interval timer repeatedly generates an interrupt at time intervals specified by the count value set to 8-bit compare register 8n (CR8n) in advance.

To operate 8-bit timer counter as an interval timer, the following settings are required.

<1> Disable operation of the 8-bit timer counter 8n (TM8n) by setting TCE8n (bit 7 of the 8-bit timer mode control register 8n (TMC8n)) to 0.

<2> Set the count clock of the 8-bit timer 8n (see Tables 7-5 and 7-6).

<3> Set count values to CR8n.

<4> Enable operation of TM8n by setting TCE0n to 1.

When the count value of 8-bit timer counter 8n (TM8n) matches the value set to CR8n, the value of TM8n is cleared to 0 and TM8n continues counting. At the same time, an interrupt request signal (INTTM8n) is generated.

Tables 7-5 and 7-6 show interval time, and Figures 7-6 and 7-7 show the interval timer operation timing.

TCL801

0

0

1

1

Caution When the TMC8n count clock is set and the operation of TM8n is enabled simultaneously by an 8-bit memory manipulation instruction, an error of more than 1 clock may occur in 1 cycle after the timer has been started. Therefore, be sure to follow the settings above when the 8-bit timer is operating as an internal timer.

Remark

n = 0 or 1

TCL800

0

1

0

1

Table 7-4. Interval Time of 8-Bit Timer 80

Minimum Interval Time

2

2

/f

X

(0.8

µs)

2

4

/f

X

(3.2

µs)

2

6

/f

X

(12.8

µs)

Setting prohibited

Maximum Interval Time

2

10

/f

X

(204.8

µs)

2

12

/f

X

(819.2

µs)

2

14

/f

X

(3.28 ms)

Resolution

2

2

/f

X

(0.8

µs)

2

4

/f

X

(3.2

µs)

2

6

/f

X

(12.8

µs)

Remarks 1. f

X

: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f

X

= 5.0 MHz.

TCL811

0

0

1

1

TCL810

0

1

0

1

Table 7-5. Interval Time of 8-Bit Timer 81

Minimum Interval Time

2/f

X

(0.4

µs)

2

5

/f

X

(6.4

µs)

2

7

/f

X

(25.6

µs)

Setting prohibited

Maximum Interval Time

2

8

/f

X

(51.2

µs)

2

13

/f

X

(1.64 ms)

2

15

/f

X

(6.55 ms)

Resolution

2/f

X

(0.4

µs)

2

5

/f

X

(6.4

µs)

2

7

/f

X

(25.6

µs)

Remarks 1. f

X

: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f

X

= 5.0 MHz.

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CHAPTER 7 8-BIT TIMER

Figure 7-5. Interval Timer Operation Timing

t

Count clock

TM8n count value 00 01 N 00

Clear

01

N

N 00

Clear

01

N

N

CR8n N N

TCE8n

Count starts

INTTM8n

Interrupt acknowledged

Interval time

Interrupt acknowledged

Interval time Interval time

Caution An error of up to 1 clock may occur in the period until the match signal is generated after the timer starts.

This is because 8-bit timer counter 8n (TM8n) starts operation asynchronously with the count pulse.

Remarks 1. Interval time = (N + 1)

× t where N = 00H to FFH

2. n = 0 or 1

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CHAPTER 8 WATCH TIMER

8.1 Watch Timer Functions

The watch timer has the following functions.

• Watch timer

• Interval timer

The watch and interval timers can be used at the same time.

Figure 8-1 shows a block diagram of the watch timer.

Figure 8-1. Watch Timer Block Diagram

f

X

/2

7 f

XT f

W f

W

2

4

Clear

9-bit prescaler f

W

2

5 f

2

W

6 f

2

W

7 f

W

2

8 f

W

2

9

5-bit counter

Clear

INTWT

INTWTI

WTM7 WTM6 WTM5 WTM4 WTM1 WTM0

Watch timer mode control register (WTM)

Internal bus

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CHAPTER 8 WATCH TIMER

(1) Watch timer

The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to generate an interrupt request

(INTWT) at 0.5-second intervals.

Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5second interval. In this case, the subsystem clock, which operates at 32.768 kHz, should be used instead.

(2) Interval timer

The interval timer is used to generate an interrupt request (INTWT) at specified intervals.

Table 8-1. Interval Time of Interval Timer

Interval

2

4

× 1/f

W

2

5

× 1/f

W

2

6

× 1/f

W

2

7

× 1/f

W

2

8

× 1/f

W

2

9

× 1/f

W

During f

X

= 5.0 MHz Operation

409.6

µs

819.2

µs

1.64 ms

3.28 ms

6.55 ms

13.1 ms

During f

X

= 4.19 MHz Operation

489

µs

978

µs

1.96 ms

3.91 ms

7.82 ms

15.6 ms

During f

XT

= 32.768 kHz Operation

488

µs

977

µs

1.95 ms

3.91 ms

7.81 ms

15.6 ms

Remarks

1. f

W

: Watch timer clock frequency (f

X

/2

7

or f

XT

)

2. f

X

: Main system clock oscillation frequency

3. f

XT

: Subsystem clock oscillation frequency

8.2 Watch Timer Configuration

The watch timer includes the following hardware.

Item

Counter

Prescaler

Control register

Table 8-2. Configuration of Watch Timer

Configuration

5 bits

× 1

9 bits

× 1

Watch timer mode control register (WTM)

8.3 Register Controlling Watch Timer

The watch timer mode control register (WTM) is used to control the watch timer.

• Watch timer mode control register (WTM)

WTM selects a count clock for the watch timer and specifies whether to enable clocking of the timer. It also specifies the prescaler interval and how the 5-bit counter is controlled.

WTM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears WTM to 00H.

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Figure 8-2. Watch Timer Mode Control Register Format

Symbol 7 6 5 4 3

WTM WTM7 WTM6 WTM5 WTM4 0

2 1 0

0 WTM1 WTM0

Address After reset

FF4AH 00H

R/W

R/W

WTM7

0

1 f f

X

/2

7

(39.1 kHz)

XT

(32.768 kHz)

WTM6 WTM5 WTM4

0

0

0

0

0

1

0

0

1

1

1

1

0

0

0

1

0

1

Other than above

2

4

/f

W

(488 s)

2

5

/f

W

(977 s)

2

6

/f

W

(1.95 ms)

2

7

/f

W

(3.91 ms)

2

8

/f

W

(7.81 ms)

2

9

/f

W

(15.6 ms)

Setting prohibited

WTM1

0

Cleared after operation stop

1 Started

Watch timer count clock selection

Prescaler interval selection

Control of 5-bit counter operation

WTM0

0

Watch timer operation

Operation stopped (both prescaler and timer cleared)

1 Operation enabled

Remarks 1. f

W

: Watch timer clock frequency (f

X

/2

7

or f

XT

)

2. f

X

: Main system clock oscillation frequency

3. f

XT

: Subsystem clock oscillation frequency

4. The parenthesized values apply to operation at f

X

= 5.0 MHz or at f

XT

= f

W

= 32.768 kHz.

8.4 Watch Timer Operation

8.4.1 Operation as watch timer

The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used as a watch timer with 0.5-second intervals.

The watch timer is used to generate an interrupt request at specified intervals.

By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer starts counting. By setting them to 0, the 5-bit counter is cleared and the watch timer stops counting.

When the interval timer also operates at the same time, only the watch timer can be started from 0 seconds by setting WTM1 to 0. However, an error of up to 2

9

× 1/f

W

seconds may occur for the first overflow of the watch timer

(INTWT) after a 0-second start because the 9-bit prescaler is not cleared in this case.

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CHAPTER 8 WATCH TIMER

8.4.2 Operation as interval timer

The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count value.

The interval time can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM).

Table 8-3. Interval Time of Interval Timer

WTM6 WTM5 WTM4 Interval During f

X

= 5.0 MHz Operation During f

X

= 4.19 MHz Operation During f

XT

= 32.768 kHz Operation

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

2

2

4

5

× 1/f

× 1/f

W

W

409.6

819.2

µs

µs

2

6

× 1/f

W

1.64 ms

2

7

× 1/f

W

3.28 ms

2

8

× 1/f

W

6.55 ms

2

9

× 1/f

W

13.1 ms

489

µs

978

µs

1.96 ms

3.91 ms

7.82 ms

15.6 ms

488

977

µs

µs

1.95 ms

3.91 ms

7.81 ms

15.6 ms

Other than above Setting prohibited

Remark

f

X

: Main system clock oscillation frequency f

XT

: Subsystem clock oscillation frequency f

W

: Watch timer clock frequency

Figure 8-3. Watch Timer/Interval Timer Operation Timing

90

5-bit counter

0H

Start

Overflow Overflow

Count clock f

W

/2

9

Watch timer interrupt

INTWT

Interval timer interrupt

INTWTI

Watch timer interrupt time (0.5 s) Watch timer interrupt time (0.5 s)

Interval timer (T)

T

Caution When operation of the watch timer and 5-bit counter has been enabled by setting the watch timer mode control register (WTM) (setting WTM0 (bit 0 of WTM) to 1), the time until the first interrupt request after this setting will not be exactly the same as the time set by WTM3 (bit

3 of WTM). This is because the 5-bit counter starts counting one cycle after the output of the 9-bit prescaler. The INTWT signal will be generated at the set time from its second generation.

Remarks

1. f

W

: Watch timer clock frequency

2. The parenthesized values apply to operation at f

W

= 32.768 kHz.

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CHAPTER 9 WATCHDOG TIMER

The watchdog timer can generate non-maskable interrupts, maskable interrupts and RESET with arbitrary preset intervals.

9.1 Watchdog Timer Functions

The watchdog timer has the following functions:

• Watchdog timer

• Interval timer

Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM).

(1) Watchdog timer

The watchdog timer is used to detect program runaway. When a runaway is detected, a non-maskable interrupt or the RESET signal can be generated.

Table 9-1. Runaway Detection Time of Watchdog Timer

Runaway

Detection Time

2

11

× 1/f

X

2 13

× 1/f

X

2

15

× 1/f

X

2

17

× 1/f

X

410

µs

1.64 ms

6.55 ms

26.2 ms

At f

X

= 5.0 MHz Operation

f

X

: Main system clock oscillation frequency

(2) Interval timer

The interval timer generates an interrupt at a given interval set in advance.

Table 9-2. Interval Time

Interval Time

2

11

× 1/f

X

2

13

× 1/f

X

2

15

× 1/f

X

2

17

× 1/f

X

410

µs

1.64 ms

At f

X

= 5.0 MHz Operation

6.55 ms

26.2 ms

f

X

: Main system clock oscillation frequency

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CHAPTER 9 WATCHDOG TIMER

9.2 Watchdog Timer Configuration

The watchdog timer consists of the following hardware.

Item

Control register

Table 9-3. Configuration of Watchdog Timer

Configuration

Watchdog timer clock select register (WDCS)

Watchdog timer mode register (WDTM)

Figure 9-1. Block Diagram of Watchdog Timer

Internal bus f

X

2

4 f

X

2 6

Prescaler f

X

2 8 2 f

X

10

7-bit counter

Clear

Control circuit

WDTIF

WDTMK

2

INTWDT maskable interrupt request

RESET

INTWDT non-maskable interrupt request

WDCS2 WDCS1

Watchdog timer clock select register

(WDCS)

RUN

Internal bus

WDTM4 WDTM3

Watchdog timer mode register (WDTM)

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CHAPTER 9 WATCHDOG TIMER

9.3 Registers Controlling Watchdog Timer

The following two types of registers are used to control the watchdog timer.

• Watchdog timer clock select register (WDCS)

• Watchdog timer mode register (WDTM)

(1) Watchdog timer clock select register (WDCS)

This register sets the watchdog timer count clock.

TCL2 is set with an 8-bit memory manipulation instruction.

RESET input clears TCL2 to 00H.

Symbol

WDCS

7

0

6

0

5

0

Figure 9-2. Watchdog Timer Clock Select Register Format

4

0

3 2 1 0

0 WDCS2 WDCS1 0

Address

FF42H

After reset

00H

R/W

R/W

WDCS2 WDCS1

Watchdog timer count clock selection

0

0

1

0

1

0

1 1

Other than above f

X

/2

4

(312.5 kHz) f

X

/2

6

(78.1 kHz) f

X

/2

8

(19.5 kHz) f

X

/2

10

(4.88 kHz)

Setting prohibited

2

11

/f

X

2

13

/f

X

(1.64 ms)

2

15

/f

X

(6.55 ms)

2

17

/f

X

(26.2 ms)

Interval time

Remark

f

X

: Main system clock oscillation frequency

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CHAPTER 9 WATCHDOG TIMER

(2) Watchdog timer mode register (WDTM)

This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog timer.

WDTM is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears WDTM to 00H.

Symbol

WDTM

<7> 6

RUN 0

Figure 9-3. Watchdog Timer Mode Register Format

5 4 3 2

0 WDTM4 WDTM3 0

1

0

0

0

Address After reset

FFF9H 00H

R/W

R/W

RUN

0 Stops counting

1 Clears counter and starts counting

Watchdog timer operation selection

Note 1

WDTM4 WDTM3

0

0

0

1

1

1

0

1

Watchdog timer operation mode selection

Operation stop

Interval timer mode (overflow and maskable interrupt occur)

Note 3

Watchdog timer mode 1 (overflow and non-maskable interrupt occur)

Note 2

Watchdog timer mode 2 (overflow occurs and reset operation started)

Notes

1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is started, it cannot be stopped by any means other than RESET input.

2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software.

3. The watchdog timer starts operations as an interval timer when RUN is set to 1.

Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to 0.8% shorter than the time set by watchdog timer clock select register (WDCS).

2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming WDTIF (bit 0 of interrupt request flag 0) has been set to 0. When watchdog timer mode 1 or 2 is selected under the condition where WDTIF is 1, a non-maskable interrupt occurs at the completion of rewriting.

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CHAPTER 9 WATCHDOG TIMER

9.4 Watchdog Timer Operation

9.4.1 Operation as watchdog timer

The watchdog timer operates to detect a runaway when bit 4 (WDTM4) of the watchdog timer mode register

(WDTM) is set to 1.

The count clock (runaway detection time interval) of the watchdog timer can be selected by bits 1 and 2 (WDCS1 and WDCS2) of watchdog timer clock select register (WDCS). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is started. Set RUN to 1 within the set runaway detection time interval after the watchdog timer has been started.

By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the runaway detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the value of bit 3 (WDTM3) of WDTM.

The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1 before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction.

Cautions 1. The actual runaway detection time may be up to 0.8% shorter than the set time.

2. When the subsystem clock is specified as the CPU clock, the count operation of the watchdog timer stops. Therefore, even if the main system clock is oscillating at that time, watchdog timer operation stops.

Table 9-4. Runaway Detection Time of Watchdog Timer

WDCS2 WDCS1

0 0

0

1

1

1

0

1

At f

X

= 5.0 MHz Operation

410

µs

1.64 ms

6.55 ms

26.2 ms f

X

: Main system clock oscillation frequency

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CHAPTER 9 WATCHDOG TIMER

9.4.2 Operation as interval timer

When bits 4 and 3 (WDTM4, WDTM3) of watchdog timer mode register (WDTM) are set to 1, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a count value set in advance.

Select a count clock (or interval time) by setting bits 1 and 2 (WDCS1 and WDCS2) of watchdog timer clock select register (WDCS). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1.

In the interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can be generated. The priority of INTWDT is set as the highest of all the maskable interrupts.

The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to

1 before entering the STOP mode to clear the interval timer, and then execute the STOP instruction.

Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the interval timer mode is not set, unless the RESET signal is input.

2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the set time.

Table 9-5. Interval Time of Interval Timer

WDCS2 WDCS1

0 0

0

1

1

1

0

1

At f

X

= 5.0 MHz Operation

410

µs

1.64 ms

6.55 ms

26.2 ms

f

X

: Main system clock oscillation frequency

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CHAPTER 10 SERIAL INTERFACE 10

10.1 Serial Interface 10 Functions

The serial interface 10 has the following two modes.

• Operation stop mode

• 3-wire serial I/O mode

(1) Operation stop mode

This mode is used when serial transfer is not carried out. It reduces power consumption.

(2) 3-wire serial I/O mode (MSB first/LSB first selectable)

In this mode, 8-bit data transfer is carried out with three lines, one for serial clock (SCK10) and two for serial data (SI10 and SO10).

The 3-wire serial I/O mode supports simultaneous transmit and receive operation, reducing data transfer processing time.

It is possible to select the start bit of 8-bit data to be transmitted between the MSB and the LSB, thus allowing connection to devices with either start bit.

The 3-wire serial I/O mode is effective for connecting display controllers and peripheral I/Os such as the 75XL

Series, 78K Series, and 17K Series that have internal conventional clock synchronous serial interface.

10.2 Serial Interface 10 Configuration

Serial interface 10 has the following hardware configuration.

Item

Register

Control register

Table 10-1. Configuration of Serial Interface 10

Configuration

Transmit/receive shift register 10 (SIO10)

Serial operating mode register 10 (CSIM10)

(1) Transmit/receive shift register 10 (SIO10)

This is an 8-bit register used for parallel-to-serial conversion and to perform serial data transmission/reception in synchronization with serial clocks.

SIO10 is set with an 8-bit memory manipulation instruction.

RESET input makes SIO10 undefined.

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97

SI10/P22

SO10/P21

SCK10/P20

Figure 10-1. Block Diagram of Serial Interface 10

Internal bus

Serial operation mode register 10 (CSIM10)

CSIE10 TPS100 TPS101 DIR10 CSCK10

Transmit/receive shift register 10

(SIO10)

Serial clock counter

F/F

Clock control circuit

Interrupt request generator f

X

/2

2 f

X

/2

3 f

X

/2

4 f

X

/2

5

INTCSI10

CHAPTER 10 SERIAL INTERFACE 10

10.3 Register Controlling Serial Interface 10

The following register is used to control serial interface 10.

• Serial operation mode register 10 (CSIM10)

(1) Serial operation mode register 10 (CSIM10)

This register is used to control serial interface 10 operation and set the serial clock and start bit.

CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CSIM10 to 00H.

Figure 10-2. Serial Operation Mode Register 10 Format

Symbol <7> 6 5 4 3 2 1 0

CSIM10 CSIE10 0 TPS101 TPS100 0 DIR10 CSCK10 0

Address

FF72H

After reset

00H

R/W

R/W

CSIE10

0

1

Operation stopped

Operation enabled

Operation control in 3-wire serial I/O mode

TPS101 TPS100

0

0

0

1

Count clock selection during operation enable in 3-wire serial I/O mode f

X

/2 2 (1.25 MHz) f

X

/2 3 (625 kHz)

1

1

0

1 f

X

/2 4 (313 kHz) f

X

/2 5 (157 kHz)

DIR10

0

1

MSB

LSB

Start bit specification

CSCK10

0

1

Clock selection in 3-wire serial I/O mode

Input clock to SCK10 pin from external

Internal clock selected by TPS100, TPS101

Caution Bits 0, 3, and 6 must be set to 0.

Remarks 1. f

X

: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f

X

= 50 MHz.

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CHAPTER 10 SERIAL INTERFACE 10

Table 10-2. Settings of Serial Interface 10 Operation Mode

(1) Operation stop mode

CSIM10

CSIE10 DIR10 CSCK10

0

× ×

Other than above

PM22

×

Note 1

×

P22

Note 1

PM21 P21 PM20 P20 Start Shift

×

Note 1

×

Note 1

×

Note 1

P22/SI10 P21/SO10 P20/SCK10

Bit Clock Pin Function Pin Function Pin Function

×

Note 1

– – P22 P21 P20

Setting prohibited

(2) 3-wire serial I/O mode

CSIM10 PM22 P22

CSIE10 DIR10 CSCK10

1 0 0 1

Note 2

×

Note 2

1 1

1

0

1

Other than above

PM21 P21 PM20 P20 Start Shift

0 1 1

0

×

1 External clock

P22/SI10 P21/SO10 P20/SCK10

Bit Clock Pin Function Pin Function Pin Function

MSB External SI10

Note 2

clock

SO10

(CMOS output)

SCK10 input

SCK10 output

1

×

LSB External clock

SCK10 input

0 1 External clock

Setting prohibited

SCK10 output

Notes 1. Can be used as port function.

2. If used only for transmission, can be used as P22 (CMOS I/O port).

Remark

×: don’t care

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CHAPTER 10 SERIAL INTERFACE 10

10.4 Serial Interface 10 Operation

Serial interface 10 provides the following two types of modes.

• Operation stop mode

• 3-wire serial I/O mode

10.4.1

Operation stop mode

In the operation stop mode, serial transfer is not executed; therefore, the power consumption can be reduced.

P20/SCK10, P21/SO10, and P22/SI10 pins can be used as normal I/O ports.

(1) Register setting

Operation stop mode is set by serial operation mode register 10 (CSIM10).

Serial operation mode register 10 (CSIM10)

CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CSIM10 to 00H.

Symbol <7> 6 5 4 3 2 1 0

CSIM10 CSIE10 0 TPS101 TPS100 0 DIR10 CSCK10 0

Address

FF72H

After reset

00H

R/W

R/W

CSIE10

0

1

Operation stopped

Operation enabled

Operation control in 3-wire serial I/O mode

Caution Bits 0, 3, and 6 must be set to 0.

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CHAPTER 10 SERIAL INTERFACE 10

10.4.2

3-wire serial I/O mode

The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75XL Series, 78K Series, 17K Series, etc.

Communication is performed using three lines: the serial clock (SCK10), serial output (SO10), and serial input

(SI10).

(1) Register setting

3-wire serial I/O mode settings are performed using serial operation mode register 10 (CSIM10).

(a) Serial operation mode register 10 (CSIM10)

CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CSIM10 to 00H.

Symbol <7> 6 5 4 3 2 1 0

CSIM10 CSIE10 0 TPS101TPS100 0 DIR10 CSCK10 0

Address

FF72H

After reset

00H

R/W

R/W

CSIE10

0

1

Operation stopped

Operation enabled

Operation control in 3-wire serial I/O mode

TPS101 TPS100

0

0

0

1

Count clock selection during operation enabled in 3-wire serial I/O mode f

X

/2 2 (1.25 MHz) f

X

/2 3 (625 kHz)

1

1

0

1 f

X

/2 4 (313 kHz) f

X

/2 5 (157 kHz)

DIR10

0

1

MSB

LSB

Start bit specification

CSCK10

0

1

Clock selection in 3-wire serial I/O mode

Input clock to SCK10 pin from external

Count clock selected by TPS100, TPS101

Caution Bits 0, 3, and 6 must be set to 0.

Remarks 1. f

X

: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f

X

= 5.0 MHz.

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CHAPTER 10 SERIAL INTERFACE 10

(2) Communication operation

In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received in 1-bit units in synchronization with the serial clock.

Transmit/receive shift register 10 (SIO10) shift operations are performed in synchronization with the fall of the serial clock (SCK10). Then transmit data is held in the SO10 latch and output from the SO10 pin. Also, receive data input to the SI10 pin is latched in input bits of SIO10 on the rise of SCK10.

At the end of an 8-bit transfer, the operation of SIO10 stops automatically, and the interrupt request signal

(INTCSI10) is generated.

Figure 10-3. 3-Wire Serial I/O Mode Timing

SCK10

SI10

1 2 3 4 5 6 7 8

DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0

SO10 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

INTCSI10

End of transfer

Transfer start at the falling edge of SCK10

Cautions 1. When data is written to SIO10 in the serial operation disabled status (CSIE10 = 0), the data cannot be transmitted or received.

2. When data is written to SIO10 in the serial operation disabled status (CSIE10 = 0) and then serial operation is enabled (CSIE10 = 1), the data cannot be transmitted or received.

3. Once data has been written to SIO10 with the serial clock selected (CSCK10 = 0), overwriting the data does not update the contents of SIO10.

4. When CSIM10 is operated during data transmission/reception, data cannot be transmitted or received normally.

5. When SIO10 is operated during data transmission/reception, the data cannot be transmitted or received normally.

(3) Transfer start

Serial transfer is started by setting transfer data to the transmit/receive shift register 10 (SIO10) when the following two conditions are satisfied.

• Bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) = 1

• Internal serial clock is stopped or SCK10 is a high level after 8-bit serial transfer.

An end of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal

(INTCSI10).

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CHAPTER 11 VFD CONTROLLER/DRIVER

11.1 VFD Controller/Driver Functions

The on-chip VFD controller/driver of the

µPD789871 Subseries has the following functions.

(1) Can output display signals (DMA operation) by automatically reading display data.

(2) The pins not used for VFD display can be used as I/O port or output port pins (FIP9 to FIP24 pins only).

(3) Luminance can be adjusted in 8 steps by VFD display mode register 1 (DSPM1).

(4) Hardware for key scan application

• Generates an interrupt signal (INTKS) indicating key scan timing.

• Timing in which key scan data is output can be detected by key scan flag (KSF).

• Whether key scan timing is inserted or not can be selected.

(5) High-tolerance output buffer that can directly drive VFD

(6) The FIP17 to FIP24 pins can be connected to pull-down resistors (connected to V

LOAD

) using mask option (mask

ROM version only). The

µPD78F9872 does not have on-chip pull-down resistors).

Of the 25 VFD output pins of the

µPD789871 Subseries, FIP9 to FIP24 are alternate function pins with port function.

FIP0 to FIP8 are output-only pins.

FIP9 to FIP24 can be used as port pins when VFD display is disabled by bit 7 (DSPEN) of the display mode register

0 (DSPM0). Even when VFD display is enabled, the VFD output pins not used for display signal output can be used as port pins.

Table 11-1. VFD Output Pins and Alternate-Function Pins for Ports

FIP Pin Name

FIP9 to FIP16

FIP17 to FIP24

Multiplexed Port Name

P97 to P90

P87 to P80

I/O

Output-only port

I/O port

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CHAPTER 11 VFD CONTROLLER/DRIVER

11.2 VFD Controller/Driver Configuration

The VFD controller/driver consists of the following hardware.

Table 11-2. Configuration of VFD Controller/Driver

Item

Display 25

Configuration

Control register Display mode register 0 (DSPM0)

Display mode register 1 (DSPM1)

Display mode register 2 (DSPM2)

Figure 11-1. Block Diagram of VFD Controller/Driver

Internal bus

Display data memory

Display data selector

Display data latch

Port output latch

FIP0 FIP9/P97

High-voltage buffer

FIP24/P80

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CHAPTER 11 VFD CONTROLLER/DRIVER

11.3 Registers Controlling VFD Controller/Driver

11.3.1 Control registers

The following three types of registers control the VFD controller/driver.

• Display mode register 0 (DSPM0)

• Display mode register 1 (DSPM1)

• Display mode register 2 (DSPM2)

(1) Display mode register 0 (DSPM0)

DSPM0 performs the following setting.

• Enables or disables display

• Number of VFD output pins

DSPM0 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets DSPM0 to 10H.

Figure 11-2. Display Mode Register 0 Format

Symbol < 7 >

DSPM0 DSPEN

6

0

5 4 3 2 1 0

FOUT5 FOUT4 FOUT3 FOUT2 FOUT1 FOUT0

Address After reset R/W

FFA0H 10H R/W

DSPEN

0

1

Disables

Enables

Enables or disables VFD display

0

0

0

0

FOUT5 FOUT4 FOUT3 FOUT2 FOUT1 FOUT0

0 1 0 0 0 0

0

0

1

1

0

0

0

0

0

1

1

0

1

1

1

1

0

0

0

0

0

1

1

1

1

0

0

1

1

0

1

0

0

0

1

1

Other than above

0

1

1

0

1

0

1

0

Number of VFD output pins

20

21

22

23

17

18

19

24

25

Setting prohibited

Cautions 1. Be sure to set bit 6 to 0.

2. Do not write data to the bits other than DSPEN when bit 7 (DSPEN) = 1.

3. Be sure to set the output latch of the alternate-function port of a pin used for VFD output to 0.

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CHAPTER 11 VFD CONTROLLER/DRIVER

(2) Display mode register 1 (DSPM1)

DSPM1 performs the following setting.

• Blanking width of VFD output signal

• Number of display patterns

DSPM1 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets DSPM1 to 01H.

Figure 11-3. Display Mode Register 1 Format

Symbol 7 6

DSPM1 FBLK2 FBLK1

5

FBLK0

4

FPAT4

3 2

FPAT3 FPAT2

1 0

FPAT1 FPAT0

Address After reset R/W

FFA1H 01H R/W

1

1

0

1

1

FBLK2 FBLK1 FBLK0

0 0 0

0

0

0

1

1

0

1

0

0

1

1

1

0

1

0

1

1/16

2/16

4/16

6/16

8/16

10/16

12/16

14/16

Blanking width of VFD output signal

0

0

0

0

FPAT4 FPAT3 FPAT2 FPAT1 FPAT0

0 0 0 0 1

0

0

0

0

0

0

1

1

0

1

0

0

0

0

1

1

1

1

0

0

1

1

0

1

0

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

Other than above

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

7

8

5

6

2

3

4

9

10

11

12

13

14

15

16

Setting prohibited

Number of display patterns

Caution Do not write data to the display mode register 1 (DSPM1) when bit 7 (DSPEN) of the display mode register 0 (DSPM0) is 1.

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CHAPTER 11 VFD CONTROLLER/DRIVER

(3) Display mode register 2 (DSPM2)

DSPM2 performs the following setting. It also indicates the status of the display timing/key scan.

• Insertion of key scan timing

• Display cycle (T

DSP

)

DSPM2 is set with a 1-bit or 8-bit memory manipulation instruction. However, only bit 7 (KSF) can be read by a 1-bit memory manipulation instruction.

RESET input clears DSPM2 to 00H.

Figure 11-4. Display Mode Register 2 Format

Symbol

DSPM2

7

KSF

6

KSM

5

0

4

0

3

0

2

0

1 0

FCYC1 FCYC0

Address After reset R/W

FFA2H 00H R/W

KSF

0

1

Other than key scan cycle

Key scan cycle

KSM

0

1

Not inserted

Inserted

Status of key scan cycle

Key scan cycle insertion selection

FCYC1 FCYC0

0 0

0

1

1

1

0

1

2

12

/f

X

(819

µs)

2

11

/f

X

(410

µs)

2

10

/f

X

(205

µs)

Setting prohibited

Display cycle

Cautions 1. Be sure to set bits 2 to 5 to 0.

2. Do not write data to the display mode register 2 (DSPM2) when bit 7 (DSPEN) of the display mode register 0 (DSPM0) is 1.

Remarks 1. f

X

: Main system clock oscillation frequency

2. The parenthesized values apply to operation at f

X

= 5.0 MHz.

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11.3.2 One display period and blanking width

The VFD output signals are blanked equally at the beginning and end of the display period by the blanking width set by bits 0 to 2 (FBLK0 to FBLK2) of the display mode register 1 (DSPM1).

Figure 11-5. Blanking Width of VFD Output Signal

1/16

1 display period = T

DSP

1/16

VFD output signal

(blanking width: 1/16)

1/8 1/8

VFD output signal

(blanking width: 2/16)

1/4 1/4

VFD output signal

(blanking width: 4/16)

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CHAPTER 11 VFD CONTROLLER/DRIVER

11.4 Display Data Memory

The display data memory is a 96-byte RAM area that stores data to be displayed, and is mapped to addresses

FA00H to FA5FH.

The VFD controller reads the data stored in the display data memory independently of the CPU operation for VFD display (DMA operation).

The area of the display data memory not used for display can be used as a normal RAM area.

At key scan timing (T

KS

), all the VFD output pins are cleared to 0, and the data of the output latches of ports 8 and

9 are output to FIP9/P97 to FIP24/P80.

The address location of the display data memory is as follows:

(1) With 25 VFD output pins and 16 patterns

The addresses of the display data memory corresponding to the data output at each display timing (T0 to T15) are as shown in Figure 11-6 (for example, T0 = FA00H to FA03H, and T1 = FA04H to FA07H). When 25 VFD output pins (FIP0 to FIP24) are used, one block of display data consists of 4 bytes. VFD output pins 0 (FIP0) to 24 (FIP24) correspond to one block of display data sequentially, starting from the least significant bit toward the most significant bit.

Figure 11-6. Relationship Between Address Location of Display Data Memory and VFD Output

(with 25 VFD Output Pins and 16 Patterns)

Address

FA3CH to FA3FH

FA38H to FA3BH

3FH

3BH

3EH

3AH

3DH

39H

3CH

38H

Display timing

T

KS

T15

T14

FA0CH to FA0FH

FA08H to FA0BH

FA04H to FA07H

FA00H to FA03H

0FH

0BH

07H

03H

24

0EH

0AH

06H

02H

0DH

09H

05H

01H

0CH

08H

04H

00H

7 0

(VFD output pins)

T3

T2

T1

T0

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CHAPTER 11 VFD CONTROLLER/DRIVER

(2) With 20 VFD output pins and 9 patterns

The addresses of the display data memory corresponding to the data output at each display timing (T0 to T8) are as shown in Figure 11-7 (for example, T0 = FA00H to FA02H, and T1 = FA03H to FA05H). When 20 VFD output pins (FIP0 to FIP19) are used, one block of display data consists of 3 bytes. VFD output pins 0 (FIP0) to 19 (FIP19) correspond to one block of display data sequentially, starting from the least significant bit toward the most significant bit.

Figure 11-7. Relationship Between Address Location of Display Data Memory and VFD Output

(with 20 VFD Output Pins and 9 Patterns)

Address

FA18H to FA1AH

FA15H to FA17H

6BH

64H

6AH

63H

69H

62H

Display timing

T

KS

T8

T7

FA09H to FA0BH

FA06H to FA08H

FA03H to FA05H

FA00H to FA02H

17H

10H

09H

02H

19 16

16H

0FH

08H

01H

15H

0EH

07H

00H

7 0

(VFD output pins)

T3

T2

T1

T0

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CHAPTER 11 VFD CONTROLLER/DRIVER

11.5 Key Scan Flag and Key Scan Data

11.5.1 Key scan flag

The key scan flag (KSF) is set to 1 during key scan timing, and is automatically reset to 0 at display timing.

KSF is mapped to bit 7 of the display mode register 2 (DSPM2) and can be tested in 1-bit units. It cannot be written, however.

By testing KSF, it can be determined whether key scan timing is in progress, and whether key input data is correct can be checked.

Whether key scan timing is inserted or not can be selected by using the key scan timing insertion specification flag

(KSM) (bit 6 of the display mode register 2 (DSPM2)).

11.5.2 Key scan data

Data stored in ports 8 and 9 are output from the FIP9 to FIP24 pins during key scan timing.

Caution If scanning is performed in such a manner that both a segment and a digit turn ON during key scan timing, the display may flicker.

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CHAPTER 11 VFD CONTROLLER/DRIVER

11.6 Leakage Emission of Fluorescent Indicator Panel

Leakage emission may take place when a fluorescent indicator panel is driven by the

µPD789871 Subseries. The possible causes of this leakage emission are as follows.

(1) Short blanking time

Figure 11-8 shows the signal waveforms of a 2-digit display where the first digit T0 lights and the second digit

T1 remains dark. If the blanking time is too short as shown in this figure, the T1 signal rises before the segment signal is deasserted, causing leakage emission. Generally, the blanking time must be about 20

µs. Determine the set value of the display mode register 1 (DSPM1), taking this into consideration.

Figure 11-8. Leakage Emission Because of Short Blanking Time

Blanking width

T0

T1

S0

Leakage emission occurs

;;

;;

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CHAPTER 11 VFD CONTROLLER/DRIVER

(2) Segment-grid capacitance of fluorescent indicator panel

Even if a sufficiently long blanking time is ensured as shown in Figure 11-10, leakage emission may still occur.

This is because the fluorescent indicator panel has a capacitance between the grid and segment, as indicated by C

SG

in Figure 11-9, and the timing signal pin is raised via C

SG

when segment signal turns on. If the voltage of the timing signal rises beyond the cutoff voltage (E

K

) as shown in Figure 11-10, leakage emission occurs.

This whisker-like voltage changes with the values of C

SG

and internal pull-down resistor (R

L

). The greater the value of C

SG

, and the greater the value of R

L

, the higher this voltage, increasing the possibility of the occurrence of leakage emission.

The value of C

SG

differs depending on the display area of the fluorescent indicator panel. The larger the area, the higher the C

SG

.

Therefore, the value of the pull-down resistor differs depending on the size of the fluorescent indicator panel, in order to prevent leakage emission.

Because the value of the pull-down resistor that can be connected by mask option is relatively high, the leakage emission may not be suppressed by the internal pull-down resistor alone.

In case sufficient display quality cannot be obtained, deepen the back bias (increase E

K

), attach a filter to the fluorescent indicator panel, or connect an external pull-down resistor of several 10 k

Ω to the timing signal pin.

The likelihood of leakage emission caused by C

SG

occurring changes depending on the duty cycle of the whisker voltage vis-a-vis the total display cycle. The fewer the number of display digits, the greater the likelihood of occurrence of leakage emission.

Lowering the display luminance also has an effect of suppressing the leakage emission.

Figure 11-9. Leakage Emission Caused by C

SG

µ

PD789871

V

DD

+5 V

S0–

T0–

C

SG

VFD

Segment grid filament

114

R

L

R

L

E

K

: Cutoff voltage

R

L

: On-chip pull-down resistor

E

K

V

LOAD –30 V

Preliminary User’s Manual U14938EJ1V0UM

T0

T1

S0

CHAPTER 11 VFD CONTROLLER/DRIVER

Figure 11-10. Leakage Emission Caused by C

SG

E

K

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CHAPTER 11 VFD CONTROLLER/DRIVER

11.7 Calculation of Total Power Dissipation

The following three power consumption are available for the

µPD789871 Subseries. The sum of the three power consumption should be less than the total power dissipation P

T

(refer to Figure 11-11) (80% or less of ratings is recommended).

<1> CPU power consumption:

<2> Output pin power consumption:

Calculate V

DD

(MAX.)

× I

DD

(MAX.).

Power consumption when maximum current flows into each VFD output pin.

<3> Pull-down resistor power consumption: Power consumption by pull-down resistor incorporated in VFD output pin.

Figure 11-11. Total Power Dissipation P

T

(T

A

= –40 to +85

°

C)

800

600

400

200

–40 0

Temperature [°C]

+40 +80

The following is how to calculate total power dissipation for the example in Figure 11-12.

Example Assume the following conditions:

V

DD

= 5.5 V, 5.0 MHz oscillation

Supply current (I

DD

) = 15 mA

VFD output: 11 grids

× 10 segments (Blanking width = 1/16: when FBLK0 to FBLK2 = 000B)

Maximum current at the grid pin is 15 mA.

Maximum current at the segment pin is 5 mA.

At the key scan timing, VFD output pin is OFF.

VFD output voltage: grid V

OD

= V

DD

– 2 V (voltage drop of 2 V) segments V

OD

= V

DD

– 0.5 V (voltage drop of 0.5 V)

Fluorescent indicator panel voltage (V

LOAD

) = –35 V

Mask option pull-down resistor = 30 k

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CHAPTER 11 VFD CONTROLLER/DRIVER

By placing the above conditions in calculation <1> to <3>, the total dissipation can be worked out.

<1> CPU power consumption: 5.5 V

× 15 mA = 82.5 mW

<2> Output pin power consumption:

Grid (V

DD

– V

OD

)

×

Total current value of each grid × (1 – Blanking width) =

Number of grids + 1

2 V

×

15 mA

× 11 grids × (1 – 1 )

11 grids + 1 16

= 25.8 mW

Segment (V

DD

– V

OD

)

×

Total segment current value of illuminated dots

Number of grids + 1

× (1 – Blanking width) =

0.5 V

×

5 mA

× 31 dots

× (1 –

11 grids + 1

1

16

) = 6.1 mW

<3> Pull-down resistor power consumption:

Grid

(V

DD

– V

LOAD

)

2

×

Number of grids × (1 – Blanking width)

Pull-down resistor value Number of grids + 1

(5.5 V – 2 V – (–35 V))

2

30 k

× 31 dots × (1 – 1 )

11 grids + 1 16

=

(5.5 V – 2 V – (–35 V))

2

×

30 k

11 grids

11 grids + 1

× (1 –

1

)

16

= 42.5 mW

Segment

(V

OD

– V

LOAD

)

2

Pull-down resistor value

×

Number of illuminated dots

Number of grids + 1

× (1 – Blanking width)=

= 129.2 mW

Total power consumption = <1> + <2> + <3> = 82.5 + 25.8 + 6.1 + 42.5 + 129.2 = 286.1 mW

In this example, the total power consumption do not exceed the rating of the total power dissipation, so there is no problem in power consumption.

However, when the total power consumption exceeds the rating of the total power dissipation, it is necessary to lower the power consumption. To reduce power consumption, reduce the number of pulldown resistors.

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CHAPTER 11 VFD CONTROLLER/DRIVER

Figure 11-12. Relationship Between Display Data Memory Contents and VFD Output with

10 Segments-11 Digits Displayed

Display data memory

F

F

F

F

A

A

A

A

0

0

1

1

2

9

0

7

H

H

H

H

,

,

,

,

F A

F A

F A

F A

0

0

0

1

1

8

6

H ,

H ,

F H ,

H ,

F

F

F

A

A

F A

A

0

0

0

1

0

7

E

5

H

H

H ,

H

,

,

,

0

0

0

0

F A 1 E H , F A 1 D H , F A 1 C H , 0

F

F

F

F

A

A

A

A

2

2

3

3

5

C

3

A

H

H

H

H

,

,

,

,

F A

F A

F A

F A

2

3

3

4

2 B

2

9

H ,

H ,

H ,

H ,

F

F

F

A

F A

A

A

2

2

3

3

3

A

1

8

H

H ,

H

H

,

,

,

1

0

0

0

F A 4 1 H , F A 4 0 H , F A 3 F H , 0

F A 4 8 H , F A 4 7 H , F A 4 6 H , 0

0

1

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

1

1

0

1

0

1

1

0

0

0

0

1

1

0

0

0

1

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

0

0

1

0

0

1

0

0

0

1

1

1

1

1

1

1

0

0

0

0

1

0

1

1

1

1

0

0

0

0

0

0

1

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

T5

T6

T7

T8

T9

T0

T1

T2

T3

T4

0

0

0

0

0

0

0

1

0

0

0 T10

0

0

0

0

0

0

0

0

1

0

0

(VFD output pins :

FIP0 to FIP20)

20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 j i h g f e d c b a

AM

PM

0 j i i

SUN

1

MON

2

TUE j j

3

WED THU

4 5

FRI SAT

6 7 8 9 f e a g b d

10 h c

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CHAPTER 12 INTERRUPT FUNCTIONS

12.1 Interrupt Function Types

The following two types of interrupt functions are used.

(1) Non-maskable interrupt

This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests.

A standby release signal is generated.

The non-maskable interrupt has one source of interrupt from the watchdog timer.

(2) Maskable interrupt

These interrupts undergo mask control. If two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority as shown in Table 12-1.

A standby release signal is generated.

The maskable interrupt has four sources of external interrupts and seven sources of internal interrupts.

12.2 Interrupt Sources and Configuration

There are total of 12 non-maskable and maskable interrupts in the interrupt sources (see Table 12-1).

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CHAPTER 12 INTERRUPT FUNCTIONS

Table 12-1. Interrupt Source List

Interrupt Type Priority

Note 1

Non-maskable

Maskable

0

1

2

3

4

5

6

7

8

9

10

11

Interrupt Source

Trigger Name

INTWDT Watchdog timer overflow (watchdog timer mode 1 selected)

INTWDT Watchdog timer overflow (interval timer mode selected)

INTP0

INTP1

Pin input edge detection

INTTM50 TI pin input rising edge detection

INTTM51 TI pin input falling edge detection

INTTM52 8-bit remote control timer over flow signal

INTKS Key scan timing

INTCSI10 End of serial interface 10 transmission/ reception

INTTM80 Generation of 8-bit timer 80 match signal

INTTM81 Generation of 8-bit timer 81 match signal

INTWT Watch timer interrupt

INTWTI Watch timer interval timer interrupt

Internal

/External

Internal

External

Internal

Vector Basic

Table Configuration

Address Type

Note 2

0004H (A)

0006H

0008H

000AH

000CH

000EH

0010H

0012H

0014H

0016H

0018H

001AH

(B)

(C)

(D)

(B)

Notes 1. Priority is the priority applicable when two or more maskable interrupts are simultaneously generated.

0 is the highest priority and 11 is the lowest priority.

2. Basic configuration types A to C correspond to A to C in Figure 12-1.

Remark

As the interrupt source of the watchdog timer (INTWDT), either a non-maskable interrupt or a maskable interrupt (internal) can be selected.

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CHAPTER 12 INTERRUPT FUNCTIONS

Figure 12-1. Basic Configuration of Interrupt Function

(A) Internal non-maskable interrupt

Interrupt request

Internal bus

Vector table address generator

Standby release signal

(B) Internal maskable interrupt

MK

Internal bus

IE

Interrupt request IF

Vector table address generator

Standby release signal

(C) External maskable interrupt (INTP0, INTP1)

External interrupt mode register (INTM0)

MK

Internal bus

IE

Interrupt request

Edge detector

IF

Vector table address generator

Standby release signal

IF: Interrupt request flag

IE: Interrupt enable flag

MK: Interrupt mask flag

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CHAPTER 12 INTERRUPT FUNCTIONS

(D) External maskable interrupt (INTTM50, INTTM51)

Internal bus

MK IE

Interrupt request

Edge detector

IF

Vector table address generator

Standby release signal

IF: Interrupt request flag

IE: Interrupt enable flag

MK: Interrupt mask flag

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CHAPTER 12 INTERRUPT FUNCTIONS

12.3 Interrupt Function Control Registers

The following four registers are used to control the interrupt functions.

• Interrupt request flag registers (IF0, IF1)

• Interrupt mask flag registers (MK0, MK1)

• External interrupt mode register (INTM0)

• Program status word (PSW)

Table 12-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests.

Table 12-2. Flags Corresponding to Interrupt Request Signal

Interrupt Request Signal Name

INTWDT

INTP0

INTP1

INTTM50

INTTM51

INTTM52

INTKS

INTCSI10

INTTM80

INTTM81

INTWT

INTWTI

WDTIF

PIF0

PIF1

TMIF50

TMIF51

TMIF52

KSIF

CSIIF10

TMIF80

TMIF81

WTIF

WTIIF

Interrupt Request Flag

WDTMK

PMK0

PMK1

TMMK50

TMMK51

TMMK52

KSMK

CSIMK10

TMMK80

TMMK81

WTMK

WTIMK

Interrupt Mask Flag

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CHAPTER 12 INTERRUPT FUNCTIONS

(1) Interrupt request flag registers (IF0, IF1)

The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgement of an interrupt request or upon RESET input.

IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction.

RESET input clears these registers to 00H.

Figure 12-2. Interrupt Request Flag Register Format

Symbol

<7>

IF0

<6> <5> <4> <3> <2> <1> <0>

CSIIF10 KSIF TMIF52 TMIF51 TMIF50 PIF1 PIF0 WDTIF

Address

FFE0H

After reset

00H

R/W

R/W

Symbol

IF1

7

0

6

0

5

0

4 <3> <2> <1> <0>

0 WTIIF WTIF TMIF81 TMIF80

Address

FFE1H

After reset

00H

R/W

R/W

××IF×

0

1

Interrupt request flag

No interrupt request signal is generated

Interrupt request signal is generated; Interrupt request state

Cautions 1. WDTIF flag is R/W enabled only when the watchdog timer is used as an interval timer.

If the watchdog timer mode 1 and 2 are used, set the WDTIF flag to 0.

2. Because port 2 has an alternate function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode.

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CHAPTER 12 INTERRUPT FUNCTIONS

(2) Interrupt mask flag registers (MK0, MK1)

The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service.

MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets these registers to FFH.

Figure 12-3. Interrupt Mask Flag Register Format

Symbol

MK0

<7> <6> <5> <4> <3> <2> <1> <0>

CSIMK10 KSMK TMMK52 TMMK51 TMMK50 PMK1 PMK0 WDTMK

Address After reset

FFE4H FFH

R/W

R/W

Symbol

MK1

7

1

6

1

5

1

4 <3> <2> <1> <0>

1 WTIMK WTMK TMMK81 TMMK80

Address After reset

FFE5H FFH

R/W

R/W

××MK×

0

1

Interrupt servicing enabled

Interrupt servicing disabled

Interrupt servicing control

Cautions 1. If the WDTMK flag is read when the watchdog timer is used in watchdog timer mode 1 and 2, its value becomes undefined.

2. Because port 2 has an alternate function as the external interrupt input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before using the output mode.

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CHAPTER 12 INTERRUPT FUNCTIONS

(3) External interrupt mode register 0 (INTM0)

This register is used to set the valid edge of INTP0 and INTP1.

INTM0 is set with an 8-bit memory manipulation instruction.

RESET input clears INTM0 to 00H.

Figure 12-4. External Interrupt Mode Register 0 Format

Symbol

INTM0

7

0

6 5 4 3 2

0 ES11 ES10 ES01 ES00

1

0

0

0

Address

FFECH

After reset

00H

R/W

R/W

ES11 ES10

0 0

Falling edge

0 1

Rising edge

1 0

1 1

Setting prohibited

Both rising and falling edges

INTP1 valid edge selection

ES01 ES00

0 0

0

1

1

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

INTP0 valid edge selection

Cautions 1. Be sure to set bits 0, 1, 6, and 7 to 0.

2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag

(

××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt

request flag (

××IF× = 0), then clear the interrupt mask flag (××MK× = 0), which will enable

interrupts.

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(4) Program status word (PSW)

The program status word is a register used to hold the instruction execution result and the current status for interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped.

This register can be read/written in 8-bit units and can carry out operations using a bit manipulation and dedicated instructions (EI, DI). When a vectored interrupt request is acknowledged, PSW is automatically saved into a stack, and the IE flag is reset to 0. It is reset from the stack by the RETI and POP PSW instructions.

RESET input sets PSW to 02H.

Figure 12-5. Program Status Word Configuration

Symbol

PSW

7

IE

6

Z

5

0

4

AC

3

0

2

0

1

1

0

CY

After reset

02H

R/W

R/W

Used when normal instruction is executed

Interrupt acknowledge enable/disable IE

0

1

Disable

Enable

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CHAPTER 12 INTERRUPT FUNCTIONS

12.4 Interrupt Processing Operation

12.4.1 Non-maskable interrupt request acknowledgement operation

The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts.

When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the

IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.

Figure 12-6 shows the flowchart from non-maskable interrupt request generation to acknowledgement. Figure

12-7 shows the timing of non-maskable interrupt request acknowledgement. Figure 12-8 shows the acknowledgement operation if multiple non-maskable interrupts are generated.

Caution During a non-maskable interrupt service program execution, do not input another non-maskable interrupt request; if it is input, the service program will be interrupted and the new interrupt request will be acknowledged.

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Figure 12-6. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement

Start

WDTM4 = 1

(watchdog timer mode is selected)

Yes

No

Interval timer

CPU processing

WDT overflows

No

Yes

WDTM3 = 0

(non-maskable interrupt is selected)

Yes

Interrupt request is generated

No

Interrupt processing is started

Reset processing

WDTM: Watchdog timer mode register

WDT: Watchdog timer

Figure 12-7. Timing of Non-Maskable Interrupt Request Acknowledgement

Instruction Instruction

Save PSW and PC, and jump to interrupt processing

Interrupt processing program

WDTIF

Figure 12-8. Acknowledging Non-Maskable Interrupt Request

Main routine

First interrupt processing

NMI request

(first)

NMI request

(second)

Second interrupt processing

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CHAPTER 12 INTERRUPT FUNCTIONS

12.4.2 Maskable interrupt request acknowledgement operation

A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled status (when the IE flag is set to 1).

The time required to start the interrupt processing after a maskable interrupt request has been generated is shown in Table 12-3.

Refer to Figures 12-10 and 12-11 for the interrupt request acknowledgement timing.

Table 12-3. Time from Generation of Maskable Interrupt Request to Processing

Minimum Time

9 clocks

Maximum Time

Note

19 clocks

Note

The wait time is maximum when an interrupt request is generated immediately before BT and BF instruction.

Remark

1 clock:

1 f

CPU

(f

CPU

: CPU clock)

When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the interrupt request assigned the highest priority.

A pending interrupt is acknowledged when the status where it can be acknowledged is set.

Figure 12-9 shows the algorithm of acknowledging interrupt requests.

When a maskable interrupt request is acknowledged, the contents of PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the

PC, and execution branches.

To return from interrupt processing, use the RETI instruction.

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Figure 12-9. Interrupt Acknowledgement Program Algorithm

Start

No

××IF = 1 ?

Yes (Interrupt request generated)

No

××MK = 0 ?

Yes

Interrupt request pending

No

IE = 1 ?

Yes

Vectored interrupt processing

Interrupt request pending

××IF:

Interrupt request flag

××MK: Interrupt mask flag

IE: Flag to control maskable interrupt request acknowledgement (1 = enable, 0 = disable)

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CHAPTER 12 INTERRUPT FUNCTIONS

Figure 12-10. Interrupt Request Acknowledgement Timing (Example of MOV A,r)

8 clocks

Clock

CPU MOV A,r

Save PSW and PC, jump to interrupt processing

Interrupt processing program

Interrupt

If an interrupt request flag (

××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n–

1, the interrupt is acknowledged after the instruction under execution is complete. Figure 12-10 shows an example of the interrupt request acknowledgement timing for an 8-bit data transfer instruction MOV A,r. Since this instruction is executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgement processing is performed after the MOV A,r instruction is completed.

Figure 12-11. Interrupt Request Acknowledgement Timing

(When Interrupt Request Flag Is Generated at the

Last Clock During Instruction Execution)

8 clocks

Clock

CPU NOP MOV A,r

Save PSW and PC, jump to interrupt processing

Interrupt processing program

Interrupt

If an interrupt request flag (

××IF) is set at the last clock of the instruction, the interrupt acknowledgement processing starts after the next instruction is executed.

Figure 12-11 shows an example of the interrupt acknowledgement timing for an interrupt request flag that is set at the second clock of NOP (2-clock instruction). In this case, the MOV A,r instruction after the NOP instruction is executed, and then the interrupt acknowledgement processing is performed.

Caution Interrupt requests are kept pending while the interrupt request flag register (IF0, IF1) or the interrupt mask flag register (MK0, MK1) is being accessed.

12.4.3 Multiple interrupt processing

Multiple interrupt processing in which another interrupt is acknowledged while an interrupt is being processed can be processed by priority. When the priority is controlled by the default priority and two or more interrupts are generated at once, interrupt processing is performed according to the priority assigned to each interrupt request in advance (refer to Table 12-1).

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INTxx

CHAPTER 12 INTERRUPT FUNCTIONS

Figure 12-12. Example of Multiple Interrupts

Example 1. Multiple interrupts are acknowledged

Main processing INTxx processing INTyy processing

EI

IE = 0

EI

IE = 0

INTyy

RETI RETI

During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and a multiple interrupt is generated.

An EI instruction is issued before each interrupt request acknowledgement, and the interrupt request acknowledgement enable state is set.

Example 2. A multiple interrupt is not generated because interrupts are not enabled

Main processing INTxx processing INTyy processing

EI

IE = 0

INTyy

INTyy is kept pending

RETI

INTxx

IE = 0

RETI

Because interrupts are not enabled in interrupt INTxx servicing (an EI instruction is not issued), interrupt request

INTyy is not acknowledged, and a multiple interrupt is not generated. The INTyy request is kept pending and acknowledged after the INTxx processing is performed.

IE = 0: Interrupt request acknowledgement disabled

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12.4.4 Interrupt request pending

Some instructions may hold pending the acknowledgement of an instruction request until the completion of the execution of the next instruction even if the interrupt request (maskable interrupt, non-maskable interrupt, and external interrupt) is generated during the execution. The following shows such instructions.

• Manipulation instruction for the interrupt request flag register (IF0, IF1)

• Manipulation instruction for the interrupt mask flag register (MK0, MK1)

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CHAPTER 13 STANDBY FUNCTION

13.1 Standby Function and Configuration

13.1.1 Standby function

The standby function is to reduce the power consumption of the system and can be effected in the following two modes:

(1) HALT mode

This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the

CPU. The system clock oscillation circuit continues oscillating. This mode does not reduce the power consumption as much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations.

(2) STOP mode

This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock oscillation circuit and stops the entire system. The power consumption of the CPU can be substantially reduced in this mode.

The low voltage (V

DD

= 1.8 V) of the data memory can be retained. Therefore, this mode is useful for retaining the contents of the data memory at an extremely low current.

The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent operation. However, some time is required until the system clock oscillation circuit stabilizes after the STOP mode has been released. If processing must be resumed immediately by using an interrupt request, therefore, use the HALT mode.

In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained.

Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then execute the STOP instruction.

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13.1.2 Register controlling standby function

The wait time after the STOP mode is released upon interrupt request until the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS).

OSTS is set with an 8-bit memory manipulation instruction.

RESET input sets OSTS to 04H. However, the oscillation stabilization time after RESET input is 2

15

/f

X

, instead of 2

17

/f

X

.

Symbol

OSTS

7

0

6

0

Figure 13-1. Oscillation Stabilization Time Select Register Format

5

0

4

0

3 2 1 0

0 OSTS2 OSTS1 OSTS0

Address

After reset

FFFAH 04H

R/W

R/W

OSTS2 OSTS1 OSTS0

0 0 0

0

1

1

0

0

0

Other than above

2

12

/f

X

µ

2

15

/f

X

(6.55 ms)

2

17

/f

X

(26.2 ms)

Setting prohibited

Oscillation stabilization time selection

Caution The wait time after the STOP mode is released does not include the time from STOP mode release to clock oscillation start (“a” in the figure below), regardless of release by RESET input or by interrupt generation.

STOP mode release

X1 pin voltage waveform a

V

SS

Remarks

1. f

X

: Main system clock oscillation frequency

2. Values in parentheses apply to operation with f

X

= 5.0 MHz.

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CHAPTER 13 STANDBY FUNCTION

13.2 Operation of Standby Function

13.2.1 HALT mode

(1) HALT mode

The HALT mode is set by executing the HALT instruction.

The operation status in the HALT mode is shown in the following table.

Table 13-1. HALT Mode Operating Status

Item Operating Status in HALT Mode Operating Status in HALT Mode

During Main System Clock Operation During Subsystem Clock Operation

Subsystem Clock

Operating

Subsystem

Clock Stopped

Main System

Clock

Operating

Main System Clock

Stopped

Main system clock

CPU

Oscillation enabled

Operation stopped

Oscillation stopped

Port (output latch) Retains the status before setting the HALT mode

8-bit remote control timer 50 Operable

8-bit timer 80

8-bit timer 81

Watch timer

Watchdog timer

Serial interface 10

VFD controller/driver

External interrupt

Operable

Operable

Operable Operable

Note 1

Operable

Operable Operation stopped

Operable

Operation stopped (retains output data)

Operable

Note 4

Operation stopped

Operation stopped

Operation stopped

Operable

Operable

Note 2

Note 3

Notes 1. Operable when the main system clock is selected.

2. Operable when the subsystem clock is selected.

3. Operable only when the external clock is selected.

4. Maskable interrupt that is not masked.

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CHAPTER 13 STANDBY FUNCTION

(2) Releasing HALT mode

The HALT mode can be released by the following three types of sources.

(a) Releasing by unmasked interrupt request

The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt request is able to be acknowledged, vectored interrupt processing is performed. If the interrupt is disabled, the instruction at the next address is executed.

Figure 13-2. Releasing HALT Mode by Interrupt

HALT instruction

Wait

Standby release signal

Operating mode

Operating mode HALT mode Wait

Oscillation

Clock

Remarks 1. The broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged.

2. The wait time is as follows:

• When vectored interrupt processing is performed: 9 to 10 clocks

• When vectored interrupt processing is not performed: 1 to 2 clocks

(b) Releasing by non-maskable interrupt request

The HALT mode is released regardless of whether the interrupt is enabled or disabled, and vectored interrupt processing is performed.

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CHAPTER 13 STANDBY FUNCTION

(c) Releasing by RESET input

When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started.

Figure 13-3. Releasing HALT Mode by RESET Input

HALT instruction

RESET signal

Operating mode

Clock

HALT mode

Oscillation

Reset period

Oscillation stop

Wait

Oscillation stabilization wait status

Oscillation

Operating mode

Remark

f

X

: Main system clock oscillation frequency

Releasing Source

Maskable interrupt request

Non-maskable interrupt request

RESET input

×: don’t care

Table 13-2. Operation After Release of HALT Mode

MK

××

0

0

1

IE

0

1

×

×

Operation

Executes next address instruction

Executes interrupt processing

Retains HALT mode

Executes interrupt processing

Reset processing

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CHAPTER 13 STANDBY FUNCTION

13.2.2 STOP mode

(1) Setting and operation status of STOP mode

The STOP mode is set by executing the STOP instruction.

Cautions 1. When the STOP mode is set, the X2 or CL2 pin is internally pulled up to V

DD

to suppress the current leakage of the oscillation circuit block. Therefore, do not use the STOP mode in a system where the external clock is used as the system clock.

2. Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the

HALT mode is set immediately after the STOP instruction has been executed, the wait time set by the oscillation stabilization time select register (OSTS) elapses, and then an operation mode is set.

The operation status in the STOP mode is shown in the following table.

Table 13-3. STOP Mode Operating Status

Item

Main system clock

CPU

Operating Status in STOP Mode During Main System Clock Operation

Subsystem Clock Operating Subsystem Clock Stopped

Oscillation stopped

Operation stopped

Port (output latch) Retains the status before setting the STOP mode

8-bit remote control timer 50 Operation stopped

8-bit timer 80

8-bit timer 81

Watch timer

Watchdog timer

Serial interface 10

VFD controller/driver

External interrupt

Operation stopped

Operation stopped

Operable

Note 1

Operation stopped

Operation stopped

Operable

Note 2

Operation stopped (retains output data)

Operable

Note 3

Notes 1. Operable when the subsystem clock is selected.

2. Operable only when the external clock is selected.

3. Maskable interrupt that is not masked.

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(2) Releasing STOP mode

The STOP mode can be released by the following two types of sources.

(a) Releasing by unmasked interrupt request

The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is able to be acknowledged, vectored interrupt processing is performed, after the oscillation stabilization time has elapsed. If the interrupt is disabled, the instruction at the next address is executed.

Figure 13-4. Releasing STOP Mode by Interrupt

STOP instruction

Wait

(set time by OSTS)

Standby release signal

Operating mode

Clock

Oscillation

STOP mode

Oscillation stop

Oscillation stabilization wait status

Oscillation

Operating mode

Remark

The broken lines indicate the case where the interrupt request that has released the standby mode is acknowledged.

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CHAPTER 13 STANDBY FUNCTION

(b) Releasing by RESET input

When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed.

Figure 13-5. Releasing STOP Mode by RESET Input

STOP instruction

RESET signal

Operating mode

Clock

Oscillation

STOP mode

Oscillation stop

Reset period

Wait

Oscillation stabilization wait status

Oscillation

Operating mode

Remark

f

X

: Main system clock oscillation frequency

Releasing Source

Maskable interrupt request

Table 13-4. Operation After Release of STOP Mode

MK

××

0

0

1

IE

0

1

×

Operation

Executes next address instruction

Executes interrupt processing

Retains STOP mode

Reset processing RESET input

×: don’t care

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CHAPTER 14 RESET FUNCTION

The following two operations are available to generate reset signals.

(1) External reset input with RESET pin

(2) Internal reset by program runaway time detection with watchdog timer

External and internal reset have no functional differences. In both cases, program execution starts at the addresses

0000H and 0001H by reset signal input.

When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware item is set to the status shown in Table 14-1. Each pin has a high impedance during reset input or during the oscillation stabilization time just after reset clear.

When a high level is input to the RESET pin, the reset is cleared and program execution is started after the oscillation stabilization time has elapsed. The reset applied by the watchdog timer overflow is automatically cleared after reset, and program execution is started after the oscillation stabilization time has elapsed (see Figures 14-2 to 14-4).

Cautions 1. For an external reset, input a low level for 10

µ

s or more to the RESET pin.

2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input.

However, the port pins become high impedance.

Figure 14-1. Block Diagram of Reset Function

RESET

Reset control circuit

Reset signal

Count clock

Watchdog timer

Stop

Overflow

Interrupt function

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CHAPTER 14 RESET FUNCTION

Figure 14-2. Reset Timing by RESET Input

X1, CL1

During normal operation

Reset period

(oscillation

stops)

Oscillation stabilization time wait

Normal operation

(reset processing)

RESET

Internal reset signal

Delay Delay

Hi-Z

Port pin

Figure 14-3. Reset Timing by Overflow in Watchdog Timer

X1, CL1

During normal operation

Overflow in watchdog timer

Internal reset signal

Reset period

(oscillation

continues)

Oscillation stabilization time wait

Normal operation

(reset processing)

Hi-Z

Port pin

Figure 14-4. Reset Timing by RESET Input in STOP Mode

X1, CL1

STOP instruction execution

During normal operation

Stop status

(oscillation

stops)

RESET

Internal reset signal

Delay

Port pin

Reset period

(oscillation

stops)

Delay

Oscillation stabilization time wait

Hi-Z

Normal operation

(reset processing)

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Table 14-1. Hardware Status After Reset

Hardware

Program counter (PC)

Note 1

Stack pointer (SP)

Program status word (PSW)

RAM Data memory

General-purpose register

Port (P0 to P2, P8, P9) (Output latch)

Port mode register (PM0 to PM2)

Pull-up resistor option register 0 (PU0)

Pull-up resistor option register B2 (PUB2)

Processor clock control register (PCC)

Oscillation stabilization time select register (OSTS)

8-bit remote control timer Control register (TMC50)

Capture register (CP50, CP51)

8-bit timer

Watch timer

Watchdog timer

Timer counter (TM80, TM81)

Compare register (CR80, CR81)

Mode control register (TMC80, TMC81)

Mode control register (WTM)

Serial interface 10

Timer clock select register (WDCS)

Mode register (WDTM)

Mode register (CSIM10)

Transmit/receive shift register 10 (SIO10)

VFD controller/driver

Interrupt

Display mode register 0 (DSPM0)

Display mode register 1 (DSPM1)

Display mode register 2 (DSPM2)

Request flag register (IF0, IF1)

Mask flag register (MK0, MK1)

External Interrupt mode register (INTM0)

Notes

1. During reset input and oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined.

All other hardware remains unchanged after reset.

2. If the reset signal is input in the standby mode, the status before reset is retained even after reset.

00H

00H

FFH

00H

00H

00H

00H

00H

00H

Undefined

10H

01H

00H

00H

00H

00H

00H

00H

02H

04H

Status after Reset

The contents of reset vector tables (0000H and

0001H) are set.

Undefined

02H

Undefined

Note 2

Undefined

Note 2

00H

FFH

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CHAPTER 15

µPD78F9872

The

µPD78F9872 is a version with flash memory instead of the internal ROM of the mask ROM version in the

µPD789871 Subseries. The differences between the flash memory and the mask ROM versions are shown in Table

15-1.

Table 15-1. Differences Between Flash Memory and Mask ROM Versions

Item

Internal memory

ROM

High-speed RAM

VFD display RAM

IC pin

V

PP

pin

Pull-down resister of FIP0 to FIP8

On-chip pull-down resister of

P80/FIP24 to P87/FIP17

(connected to V

LOAD

using mask option)

Pull-down resister of P90/FIP16 to

P97/FIP9

Electrical specifications

Flash Memory

µPD78F9872

16 KB

(flash memory)

512 bytes

96 bytes

Not provided

Provided

Provided

Not provided

Not provided

4 KB

µPD789870

Provided

Not provided

Provided

Provided

Mask ROM

8 KB

µPD789871

There are differences between flash memory versions and mask ROM versions.

Caution There are differences in noise immunity and noise radiation between the flash memory versions and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM versions.

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µPD78F9872

15.1 Flash Memory Programming

The on-chip program memory in the

µPD78F9872 is flash memory.

The flash memory can be written with the

µPD78F9116A mounted on the target system (on-board). Connect the dedicated flash programmer (Flashpro III (part number: FL-PR3, PG-FP3)) to the host machine and target system to write the flash memory.

Remark

FL-PR3 is made by Naito Densei Machida Mfg. Co., Ltd.

15.1.1 Selecting communication mode

The flash memory is written by using Flashpro III and by means of serial communication. Select a communication mode from those listed in Table 15-2. To select a communication mode, the format shown in Figure 15-1 is used.

Each communication mode is selected by the number of V

PP

pulses shown in Table 15-2.

Communication Mode

3-wire serial I/O

Table 15-2. Communication Mode

Pins Used

SCK10/P20

SO10/P21

SI10/P22

0

Number of V

PP

Pulses

Caution Be sure to select a communication mode based on the V

PP

pulse number shown in Table 15-2.

Figure 15-1. Communication Mode Selection Format

V

PP

10 V

V

DD

V

SS

1 2 n

RESET

V

DD

V

SS

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µPD78F9872

15.1.2 Function of flash memory programming

By transmitting/receiving commands and data in the selected communication mode, operations such as writing to the flash memory are performed. Table 15-3 shows the major functions of flash memory programming.

Function

Batch erase

Batch blank check

Data write

Batch verify

Table 15-3. Functions of Flash Memory Programming

Description

Erases all contents of memory

Checks erased state of entire memory

Write to flash memory based on write start address and number of data written (number of bytes)

Compares all contents of memory with input data

15.1.3 Flashpro III connection example

A connection example between the Flashpro III and the

µPD78F9872 is shown in Figure 15-2.

Figure 15-2. Flashpro III Connection in 3-Wire Serial I/O Mode

Flashpro III

V

PP n

Note

V

DD

RESET

CLK

SCK

SO

SI

GND

µ

PD78F9872

V

PP

V

DD0

, V

DD1

RESET

X1

SCK10

SI10

SO10

V

SS0

Note

n = 1, 2

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µPD78F9872

15.1.4 Example of settings for Flashpro III (PG-FP3)

Make the following setting when writing to flash memory using Flashpro III (PG-FP3).

<1> Load the parameter file.

<2> Select serial mode and serial clock using the type command.

<3> An example of the settings for the PG-FP3 is shown below.

Communication Mode

3-wire serial I/O

Table 15-4. Example of Settings for PG-FP3

COMM PORT

CPU CLK

Example of Setting for PG-FP3

SIO-ch0

On Target Board

In Flashpro

On Target Board

SIO CLK

In Flashpro

SIO CLK

4.1943 MHz

1.0 MHz

4.0 MHz

1.0 MHz

0

Number of V

PP

Pulses

Note

Note

The number of V

PP

pulses supplied from Flashpro III when serial communication is initialized. The pins to be used for communication are determined according to the number of these pulses.

Remark

COMM PORT: Selection of serial port

SIO CLK: Selection of serial clock frequency

CPU CLK: Selection of source of CPU clock to be input

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CHAPTER 16 MASK OPTION (MASK ROM VERSION)

• Mask option of FIP17/P87 to FIP24/P80

An on-chip pull-down resistor for V

LOAD

can be specified by a mask option.

Caution The flash memory versions do not provide the on-chip pull-down resistor of P80 to P87.

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CHAPTER 17 INSTRUCTION SET

This chapter lists the instruction set of the

µPD789871 Subseries. For the details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series User’s Manual Instruction (U11047E).

17.1 Operation

17.1.1 Operand identifiers and description methods

Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are described as they are. Each symbol has the following meaning.

• #: Immediate data specification

• !: Absolute address specification

• $: Relative address specification

• [ ]: Indirect address specification

In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols.

For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parenthesis in the table below, R0, R1, R2, etc.) can be used for description.

Table 17-1. Operand Identifiers and Description Methods

r rp sfr

Identifier saddr saddrp addr16 addr5 word byte bit

Description Method

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)

AX (RP0), BC (RP1), DE (RP2), HL (RP3)

Special-function register symbol

FE20H to FF1FH Immediate data or labels

FE20H to FF1FH Immediate data or labels (even addresses only)

0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)

0040H to 007FH Immediate data or labels (even addresses only)

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

Remark Refer to Table 3-3 Special Function Register List for symbols of special function registers.

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CHAPTER 17 INSTRUCTION SET

17.1.2 Description of “operation” column

D:

E:

H:

L:

A:

X:

B:

C:

A register; 8-bit accumulator

X register

B register

C register

D register

E register

H register

L register

AX:

BC:

DE:

HL:

AX register pair; 16-bit accumulator

BC register pair

DE register pair

HL register pair

PC:

SP:

Program counter

Stack pointer

PSW: Program status word

CY: Carry flag

AC:

Z:

Auxiliary carry flag

Zero flag

IE: Interrupt request enable flag

NMIS: Flag indicating non-maskable interrupt servicing in progress

( ): Memory contents indicated by address or register contents in parenthesis

×

H

,

×

L

: Higher 8 bits and lower 8 bits of 16-bit register

∧:

Logical product (AND)

∨:

∨:

Logical sum (OR)

Exclusive logical sum (exclusive OR)

: Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value)

17.1.3 Description of “flag operation” column

(Blank): Unchanged

0: Cleared to 0

1:

×:

R:

Set to 1

Set/cleared according to the result

Previously saved value is restored

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CHAPTER 17 INSTRUCTION SET

17.2 Operation List

Mnemonic

MOV

XCH

Operands

[DE],A

A,[HL]

[HL],A

A,[HL+byte]

[HL+byte],A

A,X

A,r

Note 2

A,saddr

A,sfr

A,[DE]

A,[HL]

A,[HL+byte] r,#byte saddr,#byte sfr,#byte

A,r

Note 1

r,A

Note 1

A,saddr saddr,A

A,sfr sfr,A

A,!addr16

!addr16,A

PSW,#byte

A,PSW

PSW,A

A,[DE]

Byte Clock

2

2

2

1

1

1

1

2

1

2

2

1

2

1

3

2

3

3

2

2

3

2

3

3

2

2

2

6

6

6

4

6

6

6

6

8

8

6

8

4

6

6

4

8

8

4

4

6

4

6

6

4

4

4 r

← byte

(saddr)

← byte sfr

← byte

A

← r r

← A

A

← (saddr)

(saddr)

← A

A

← sfr sfr

← A

A

← (addr16)

(addr16)

← A

PSW

← byte

A

← PSW

PSW

← A

A

← (DE)

(DE)

← A

A

← (HL)

(HL)

← A

A

← (HL+byte)

(HL+byte)

← A

A

↔ X

A

↔ r

A

↔ (saddr)

A

↔ sfr

A

↔ (DE)

A

↔ (HL)

A

↔ (HL+byte)

Operation

Flag

Z AC CY

× × ×

× × ×

Notes

1. Except r = A.

2. Except r = A, X.

Remark

One instruction clock cycle is one CPU clock cycle (f

CPU

) selected by the Processor Clock Control

Register (PCC).

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CHAPTER 17 INSTRUCTION SET

rp,#word

AX,saddrp saddrp,AX

AX,rp

Note

rp,AX

Note

AX,rp

Note

A,#byte saddr,#byte

A,r

A,saddr

A,!addr16

A,[HL]

A,[HL+byte]

A,#byte saddr,#byte

A,r

A,saddr

A,!addr16

A,[HL]

A,[HL+byte]

A,#byte saddr,#byte

A,r

A,saddr

A,!addr16

A,[HL]

A,[HL+byte]

Mnemonic

MOVW

XCHW

ADD

ADDC

SUB

Operands

Note

Only when rp = BC, DE, or HL.

3

2

2

2

2

2

3

1

1

2

2

3

2

3

1

2

2

3

3

2

2

1

3

2

1

1

2

6

4

6

4

4

4

8

6

6

6

4

8

4

6

6

6

4

8

6

4

8

4

6

6

4

8

4

Byte Clock Operation rp

← word

AX

← (saddrp)

(saddrp)

← AX

AX

← rp rp

← AX

AX

↔ rp

A,CY

← A + byte

(saddr),CY

← (saddr) + byte

A,CY

← A + r

A,CY

← A + (saddr)

A,CY

← A + (addr16)

A,CY

← A + (HL)

A,CY

← A + (HL+byte)

A,CY

← A+ byte + CY

(saddr),CY

← (saddr) + byte + CY

A,CY

← A + r + CY

A,CY

← A + (saddr) + CY

A,CY

← A + (addr16) + CY

A,CY

← A + (HL) + CY

A,CY

← A + (HL+byte) + CY

A,CY

← A – byte

(saddr), CY

← (saddr) – byte

A,CY

← A – r

A,CY

← A – (saddr)

A,CY

← A – (addr16)

A,CY

← A – (HL)

A,CY

← A – (HL+byte)

Flag

Z AC CY

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

Remark

One instruction clock cycle is one CPU clock cycle (f

CPU

) selected by the Processor Clock Control

Register (PCC).

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CHAPTER 17 INSTRUCTION SET

Mnemonic

SUBC

AND

OR

XOR

Operands saddr,#byte

A,r

A,saddr

A,!addr16

A,[HL]

A,[HL+byte]

A,#byte saddr,#byte

A,r

A,saddr

A,!addr16

A,[HL]

A,[HL+byte]

A,#byte saddr,#byte

A,r

A,saddr

A,!addr16

A,[HL]

A,[HL+byte]

A,#byte saddr,#byte

A,r

A,saddr

A,!addr16

A,[HL]

A,[HL+byte]

A,#byte

2

3

1

2

3

2

2

3

3

1

2

2

2

2

2

3

1

2

2

2

3

2

2

2

3

3

1

2

4

6

6

6

6

4

4

8

8

6

4

4

6

6

4

8

6

4

4

4

6

4

4

4

6

8

6

6

Byte Clock Operation

A,CY

← A – byte – CY

(saddr),CY

← (saddr) – byte – CY

A,CY

← A – r – CY

A,CY

← A – (saddr) – CY

A,CY

← A – (addr16) – CY

A,CY

← A – (HL) – CY

A,CY

← A – (HL+byte) – CY

A

← A ∧ byte

(saddr)

← (saddr) ∧ byte

A

← A ∧ r

A

← A ∧ (saddr)

A

← A ∧ (addr16)

A

← A ∧ (HL)

A

← A ∧ (HL+byte)

A

← A ∨ byte

(saddr)

← (saddr) ∨ byte

A

← A ∨ r

A

← A ∨ (saddr)

A

← A ∨ (addr16)

A

← A ∨ (HL)

A

← A ∨ (HL+byte)

A

← A ∨ byte

(saddr)

← (saddr) ∨ byte

A

← A ∨ r

A

← A ∨ (saddr)

A

← A ∨ (addr16)

A

← A ∨ (HL)

A

← A ∨ (HL+byte)

Flag

Z AC CY

×

×

×

×

×

×

×

×

×

×

×

×

×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

×

×

×

×

×

×

×

×

Remark

One instruction clock cycle is one CPU clock cycle (f

CPU

) selected by the Processor Clock Control

Register (PCC).

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CHAPTER 17 INSTRUCTION SET

Mnemonic

CMP

ADDW

SUBW

CMPW

INC

DEC

INCW

DECW

ROR

ROL

RORC

ROLC

SET1

CLR1

SET1

CLR1

NOT1

Operands

PSW.bit

[HL].bit

saddr.bit

sfr.bit

A.bit

PSW.bit

[HL].bit

CY

CY

CY rp

A,1

A,1

A,1

A,1 saddr.bit

sfr.bit

A.bit

A,#byte saddr,#byte

A,r

A,saddr

A,!addr16

A,[HL]

A,[HL+byte]

AX,#word

AX,#word r

AX,#word r saddr saddr rp

Byte Clock

4

6

10

2

2

2

6

6

6

10

6

4

2

6

4

2

2

2

4

4

4

4

6

4

6

6

4

4

4

6

8

6

6

2

3

2

1

1

1

3

3

3

2

3

2

1

3

1

1

1

1

2

1

2

2

3

2

3

3

2

2

2

3

3

1

2

Operation

A – byte

(saddr) – byte

A – r

A – (saddr)

A – (addr16)

A – (HL)

A – (HL+byte)

AX,CY

← AX + word

AX,CY

← AX – word

AX – word r

← r + 1

(saddr)

← (saddr) + 1 r

← r – 1

(saddr)

← (saddr) – 1 rp

← rp + 1 rp

← rp – 1

(CY,A

7

← A

0

, A m–1

← A m

)

× 1

(CY,A

0

← A

7

, A m+1

← A m

)

× 1

(CY

← A

0

, A

7

← CY, A m–1

← A m

)

× 1

(CY

← A

7

, A

0

← CY, A m+1

← A m

)

× 1

(saddr.bit)

← 1 sfr.bit

← 1

A.bit

← 1

PSW.bit

← 1

(HL).bit

← 1

(saddr.bit)

← 0 sfr.bit

← 0

A.bit

← 0

PSW.bit

← 0

(HL).bit

← 0

CY

← 1

CY

← 0

CY

← CY

Flag

Z AC CY

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× ×

× ×

× ×

× ×

×

×

×

×

× × ×

× × ×

1

0

×

Remark

One instruction clock cycle is one CPU clock cycle (f

CPU

) selected by the Processor Clock Control

Register (PCC).

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CHAPTER 17 INSTRUCTION SET

Mnemonic

CALL

CALLT

RET

RETI

PUSH

POP

MOVW

BR

BC

BNC

BZ

BNZ

BT

BF

DBNZ

NOP

EI

DI

HALT

STOP

!addr16

[addr5]

Operands

PSW rp

PSW rp

SP, AX

AX, SP

!addr16

$addr16

AX

$addr16

$addr16

$saddr16

$saddr16 saddr.bit,$addr16 sfr.bit,$addr16

A.bit,$addr16

PSW.bit,$addr16 saddr.bit,$addr16 sfr.bit,$addr16

A.bit,$addr16

PSW.bit,$addr16

B,$addr16

C,$addr16 saddr,$addr16

3

4

4

4

2

2

3

4

4

2

2

3

4

2

1

2

3

2

2

1

1

1

1

2

10

10

8

10

6

6

8

10

10

6

6

8

10

6

6

6

6

6

6

4

6

2

4

8

Byte Clock

3

1

1

1

1

3

3

1

1

6

8

6

8

2

6

6

2

2

Operation

(SP – 1)

← (PC + 3)

H

, (SP – 2)

← (PC + 3)

L

,

PC

← addr16, SP ← SP – 2

(SP – 1)

← (PC + 1)

H

, (SP – 2)

← (PC + 1)

L

,

PC

H

← (00000000, addr5 + 1),

PC

L

← (00000000, addr5), SP ← SP – 2

PC

H

← (SP + 1), PC

L

← (SP), SP ← SP + 2

PC

H

← (SP + 1), PC

L

← (SP),

PSW

← (SP + 2), SP ← SP + 3, NMIS ← 0

(SP – 1)

← PSW, SP ← SP – 1

(SP – 1)

← rp

H

, (SP – 2)

← rp

L

, SP

← SP – 2

PSW

← (SP), SP ← SP + 1 rp

H

← (SP + 1), rp

L

← (SP), SP ← SP + 2

SP

← AX

AX

← SP

PC

← addr16

PC

← PC + 2 + jdisp8

PC

H

← A, PC

L

← X

PC

← PC + 2 + jdisp8 if CY = 1

PC

← PC + 2 + jdisp8 if CY = 0

PC

← PC + 2 + jdisp8 if Z = 1

PC

← PC + 2 + jdisp8 if Z = 0

PC

← PC + 4 + jdisp8 if (saddr.bit) = 1

PC

← PC + 4 + jdisp8 if sfr.bit = 1

PC

← PC + 3 + jdisp8 if A.bit = 1

PC

← PC + 4 + jdisp8 if PSW.bit = 1

PC

← PC + 4 + jdisp8 if (saddr.bit) = 0

PC

← PC + 4 + jdisp8 if sfr.bit = 0

PC

← PC + 3 + jdisp8 if A.bit = 0

PC

← PC + 4 + jdisp8 if PSW.bit = 0

B

← B – 1, then PC ← PC + 2 + jdisp8 if B ≠ 0

C

← C – 1, then PC ← PC + 2 + jdisp8 if C ≠ 0

(saddr)

← (saddr) – 1, then

PC

← PC + 3 + jdisp8 if (saddr) ≠ 0

No Operation

IE

← 1 (Enable Interrupt)

IE

← 0 (Disable Interrupt)

Set HALT Mode

Set STOP Mode

Flag

Z AC CY

R R R

R R R

Remark

One instruction clock cycle is one CPU clock cycle (f

CPU

) selected by the Processor Clock Control

Register (PCC).

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CHAPTER 17 INSTRUCTION SET

17.3 Instructions Listed by Addressing Type

r

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,

POP, DBNZ

2nd Operand

#byte

1st Operand

A ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

A r sfr saddr !addr16

PSW [DE] [HL] [HL+byte] $addr16 1

MOV

Note

XCH

Note

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

MOV

XCH

MOV MOV

XCH

ADD ADD

ADDC ADDC

SUB SUB

SUBC SUBC

AND AND

OR

XOR

CMP

OR

XOR

CMP

MOV MOV

XCH

MOV

XCH

ADD

MOV

XCH

ADD

ADDC ADDC

SUB SUB

SUBC SUBC

AND AND

OR

XOR

CMP

OR

XOR

CMP

ROR

ROL

RORC

ROLC

None

MOV MOV INC

DEC

B, C sfr saddr

DBNZ

DBNZ INC

DEC

!addr16

PSW

MOV

MOV

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

MOV

MOV

MOV

MOV

MOV PUSH

POP

[DE]

[HL]

[HL+byte]

MOV

MOV

MOV

Note

Except r = A.

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CHAPTER 17 INSTRUCTION SET

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

2nd Operand

1st Operand

AX rp

#word

ADDW

SUBW

CMPW

MOVW

AX

MOVW

Note

rp

Note

MOVW

XCHW saddrp

MOVW

SP

MOVW

None

INCW

DECW

PUSH

POP saddrp

SP

Note

Only when rp = BC, DE, or HL.

MOVW

MOVW

(3) Bit manipulation instructions

SET1, CLR1, NOT1, BT, BF

2nd Operand

1st Operand

A.bit

sfr.bit

saddr.bit

PSW.bit

$addr16

BT

BF

BT

BF

BT

BF

BT

BF

[HL].bit

CY

None

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

NOT1

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CHAPTER 17 INSTRUCTION SET

(4) Call instructions/branch instructions

CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ

2nd Operand

1st Operand

Basic Instructions BR

AX

Compound Instructions

!addr16

CALL

BR

[addr5]

CALLT

$addr16

BR

BC

BNC

BZ

BNZ

DBNZ

(5) Other instructions

RET, RETI, NOP, EI, DI, HALT, STOP

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APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for the development of systems that employ the

µPD789871

Subseries.

Figure A-1 shows the development tool configuration.

• Support of the PC98-NX Series

Unless otherwise specified, the

µPD789104A/114A/124A/134A Subseries supported by IBM PC/AT™ and compatibles can be used for the PC98-NX Series. When using the PC98-NX Series, refer to the descriptions of the IBM PC/AT and compatibles.

• Windows

Unless otherwise specified, “Windows” indicates the following OSs.

Windows 3.1

Windows 95

Windows NT™ Ver. 4.0

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APPENDIX A DEVELOPMENT TOOLS

Figure A-1. Development Tool Configuration

Language processing software

• Assembler package

• C compiler package

• System simulator

• Device file

• C compiler source file

• Integrated debugger

Embedded software

• OS

Flash memory write environment

Flash programmer

Flash memory write adapter

Flash memory

Host machine (PC or EWS)

Interface adapter

In-circuit emulator

Emulation board

Emulation probe

Power supply unit

Conversion socket

Target system

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APPENDIX A DEVELOPMENT TOOLS

A.1 Language Processing Software

RA78K0S

Assembler package

CC78K0S

C compiler package

DF789872

Note

Device file

CC78K0S-L

C compiler source file

A program that converts a program written in mnemonic into object codes that can be executed by microcontrollers.

In addition, automatic functions to generate symbol tables and optimize branch instructions are also provided.

Used in combination with a device file (DF789872) (sold separately).

<Caution when used in PC environment>

The assembler package is a DOS-based application but may be used in the Windows environment by using the Project Manager of Windows (included in the assembler package).

Part number:

µS××××RA78K0S

A program that converts a program written in C language into object codes that can be executed by microcontrollers.

Used in combination with an assembler package (RA78K0S) and device file

(DF789872) (both sold separately).

<Caution when used in PC environment>

The C compiler package is a DOS-based application but may be used in the Windows environment by using the Project Manager of Windows (included in the assembler package).

Part number:

µS××××CC78K0S

File containing the information inherent to the device.

Used in combination with RA78K0S, CC78K0S, and SM78K0S (all sold separately).

Part number:

µS××××DF789872

Source file of functions for generating the object library included in the C compiler package.

Necessary for changing the object library included in the C compiler package according to customer's specifications. Since this is a source file, its working environment does not depend on any particular operating system.

Part number:

µS××××CC78K0S-L

Note

DF789872 is a common file that can be used with RA78K0S, CC78K0S, and SM78K0S.

Remark

×××× in the part number differs depending on the host machine and operating system to be used.

µS××××RA78K0S

µS××××CC78K0S

µS××××DF789872

µS××××CC78K0S-L

××××

AA13

AB13

3P16

3K13

3K15

3R13

Host Machine

PC-9800 Series

IBM PC/AT and compatibles

HP9000 Series 700™

SPARCstation™

NEWS™ (RISC)

OS

Japanese Windows

Note

Japanese Windows

Note

HP-UX™ (Rel.10.10)

SunOS™ (Rel.4.1.1)

Solaris™ (Rel.2.5.1)

NEWS-OS™ (Rel.6.1)

Supply Media

3.5" 2HD FD

3.5" 2HC FD

DAT (DDS)

3.5" 2HC FD

1/4" CGMT

3.5" 2HC FD

Note

Also operates in the DOS environment

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163

APPENDIX A DEVELOPMENT TOOLS

A.2 Flash Memory Writing Tools

Flashpro III

(Part No. FL-PR3, PG-FP3)

Flash programmer

FA-52GB

Flash memory writing adapter

Dedicated flash programmer for microcontrollers incorporating flash memory

Adapter for writing to flash memory and connected to Flashpro III.

Remark

The FL-PR3 and FA-52GB are products made by Naito Densei Machida Mfg. Co., Ltd.

(TEL +81-44-822-3813).

A.3 Debugging Tools

A.3.1 Hardware

IE-78K0S-NS

In-circuit emulator

IE-70000-MC-PS-B

AC adapter

IE-70000-98-IF-C

Interface adapter

IE-70000-CD-IF-A

PC card interface

IE-70000-PC-IF-C

Interface adapter

IE-70000-PCI-IF

Interface adapter

IE-789872-NS-EM1

Emulation board

NP-52GB

Emulation probe

NGS-30

Conversion socket

In-circuit emulator for debugging the hardware and software of an application system using the 78K/0S Series. Supports an integrated debugger (ID78K0S-NS). Used in combination with an AC adapter, emulation probe, and interface adapter for connecting the host machine.

Adapter for supplying power from an AC 100 to 240 V outlet.

Adapter necessary when using a PC-9800 series PC (except notebook type) as the host machine of the IE-78K0S-NS (C bus supported)

PC card and interface cable necessary when using a notebook PC as the host machine of the IE-78K0S-NS (PCMCIA socket supported)

Interface adapter necessary when using an IBM PC/AT or compatible as the host machine of the IE-78K0S-NS (ISA bus supported)

Adapter necessary when using a personal computer incorporating the PCI bus as the host machine of the IE-78K0S-NS

Board for emulating the peripheral hardware inherent to the device. Used in combination with an in-circuit emulator.

Probe for connecting the in-circuit emulator and target system.

This is for a 30-pin plastic SSOP (MC-5A4 type).

Conversion socket to connect the NP-36GS and a target system board on which a 30-pin plastic SSOP (MC-5A4 type) can be mounted.

Remark

The NP-52GB, and NGS-30 are products made by Naito Densei Machida Mfg. Co., Ltd. For details of these products, contact Naito Densei Machida Mfg. Co., Ltd. (TEL +81-44-822-3813).

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APPENDIX A DEVELOPMENT TOOLS

A.3.2 Software

ID78K0S-NS

Integrated debugger

(Supports in-circuit emulator

IE-78K0S-NS)

Control program for debugging the 78K/0S Series.

This program provides a graphical user interface. It runs on Windows for personal computer users and on OSF/Motif™ for engineering work station users, and has visual designs and operationability that comply with these operating systems. In addition, it has a powerful debug function that supports C language. Therefore, trace results can be displayed at a C language level by the window integration function that links the source program, disassembled display, and memory display, to the trace result. This software also allows users to add other function extension modules such as a task debugger and system performance analyzer to improve the debug efficiency for programs using a real-time operating system.

Used in combination with a device file (DF789872) (sold separately).

Part number:

µS××××ID78K0S-NS

Remark

×××× in the part number differs depending on the host machine and operating system to be used.

µS××××ID78K0S-NS

××××

AA13

AB13

Host Machine

PC-9800 Series

IBM PC/AT compatibles

OS

Japanese Windows

Note

Japanese Windows

Note

Supply Media

3.5" 2HD FD

3.5" 2HC FD

Note

Also operates in the DOS environment.

SM78K0S

System simulator

DF789872

Note

Device file

Debugs the program at C source level or assembler level while simulating operation of the target system on the host machine.

SM78K0S runs in Windows.

By using SM78K0S, the logic and performance of an application can be verified independently of hardware development even when the in-circuit emulator is not used. This enhances development efficiency and improves software quality.

Used in combination with a device file (DF789872) (sold separately).

Part number:

µS××××SM78K0S

File containing the information inherent to the device.

Used in combination with the RA78K0S, CC78K0S, and SM78K0S (all sold separately).

Part number:

µS××××DF789872

Note

DF789872 is a common file that can be used with the RA78K0S, CC78K0S, and SM78K0S.

Remark

×××× in the part number differs depending on the host machine and operating system to be used.

µS××××SM78K0S

××××

AA13

AB13

Host Machine

PC-9800 Series

IBM PC/AT compatibles

OS

Japanese Windows

Note

Japanese Windows

Note

Supply Media

3.5" 2HD FD

3.5" 2HC FD

Note

Also operates in the DOS environment.

Preliminary User’s Manual U14938EJ1V0UM

165

APPENDIX B EMBEDDED SOFTWARE

The following embedded software products are available for efficient program development and maintenance of the

µPD789871 Subseries.

MX78K0S

OS

MX78K0S is a subset OS that is based on the

µITRON specification. Supplied with the MX78K0S nucleus. The MX78K0S OS controls tasks, events, and time. In task control, the MX78K0S OS controls task execution order, and then perform the switching process to a task to be executed.

<Caution when used in a PC environment>

The MX78K0S is a DOS-based application. Use this software in the DOS pane when running it on

Windows.

Part number:

µS××××MX78K0S

Remark

×××× in the part number differ depending on the host machine and OS used.

µS××××MX78K0S

××××

AA13

AB13

BB13

Host Machine

PC-9800 Series

IBM PC/AT compatibles

OS

Japanese Windows

Note

Japanese Windows

Note

English Windows

Note

Supply Media

3.5" 2HD FD

3.5" 2HD FD

Note

Can also be operated in the DOS environment.

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Preliminary User’s Manual U14938EJ1V0UM

APPENDIX C REGISTER INDEX

C.1 Register Name Index (Alphabetic Order)

8-bit compare registers 80, 81 (CR80, CR81) .............................................................................................. 82

8-bit timer mode control registers 80, 81 (TMC80, TMC81) ......................................................................... 83

8-bit timer counters 80, 81 (TM80, TM81) ..................................................................................................... 82

[E]

External interrupt mode register 0 (INTM0) ................................................................................................. 126

[I]

Interrupt mask flag register 0 (MK0) ............................................................................................................ 125

Interrupt mask flag register 1 (MK1) ............................................................................................................ 125

Interrupt request flag register 0 (IF0) ........................................................................................................... 124

Interrupt request flag register 1 (IF1) ........................................................................................................... 124

[O]

Oscillation stabilization time select register (OSTS) ................................................................................... 136

[P]

Port 0 (P0) ....................................................................................................................................................... 56

Port 1 (P1) ....................................................................................................................................................... 57

Port 2 (P2) ....................................................................................................................................................... 58

Port 8 (P8) ....................................................................................................................................................... 61

Port 9 (P9) ....................................................................................................................................................... 62

Port mode register 0 (PM0) ............................................................................................................................ 63

Port mode register 1 (PM1) ............................................................................................................................ 63

Port mode register 2 (PM2) ............................................................................................................................ 63

Processor clock control register (PCC) ......................................................................................................... 68

Pull-up resistor option register 0 (PU0) ......................................................................................................... 64

Pull-up resistor option register B2 (PUB2) .................................................................................................... 64

[R]

Remote control timer capture registers 50, 51 (CP50, CP51) ..................................................................... 77

Remote control timer control register 50 (TMC50) ....................................................................................... 77

[S]

Serial operating mode register 10 (CSIM10) ................................................................................................. 99

Subclock control resistor (CSS) ..................................................................................................................... 69

Suboscillation mode resistor (SCKM) ............................................................................................................ 69

[T]

Transmit/receive shift register 10 (TXS10) .................................................................................................... 97

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167

APPENDIX C REGISTER INDEX

[V]

VFD display mode register 0 (DSPM0) ....................................................................................................... 106

VFD display mode register 1 (DSPM1) ....................................................................................................... 107

VFD display mode register 2 (DSPM2) ....................................................................................................... 108

[W]

Watchdog timer clock select register (WDCS) .............................................................................................. 93

Watchdog timer mode register (WDTM) ........................................................................................................ 94

Watch timer mode control register (WTM) .................................................................................................... 88

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APPENDIX C REGISTER INDEX

C.2 Register Symbol Index (Alphabetic Order)

[C]

CSS:

CP50:

CP51:

CR80:

Subclock control register .............................................................................................................. 69

Remote control timer capture register 50 ................................................................................... 77

Remote control timer capture register 51 ................................................................................... 77

8-bit compare register 80 ............................................................................................................. 82

CR81: 8-bit compare register 81 ............................................................................................................. 82

CSIM10: Serial operating mode register 10 ............................................................................................... 99

[D]

DSPM0: VFD display mode register 0 ..................................................................................................... 106

DSPM1: VFD display mode register 1 ..................................................................................................... 107

DSPM2: VFD display mode register 2 ..................................................................................................... 108

[I]

IF0:

IF1:

INTM0:

Interrupt request flag register 0 ................................................................................................. 124

Interrupt request flag register 1 ................................................................................................. 124

External interrupt mode register 0 ............................................................................................. 126

[M]

MK0:

MK1:

Interrupt mask flag register 0 ..................................................................................................... 125

Interrupt mask flag register 1 ..................................................................................................... 125

[O]

OSTS: Oscillation stabilization time select register .............................................................................. 136

[P]

P0:

P1:

P2:

P8:

P9:

PCC:

PM0:

PM1:

PM2:

PU0:

PUB2:

Port 0 ............................................................................................................................................ 56

Port 1 ............................................................................................................................................ 57

Port 2 ............................................................................................................................................ 58

Port 8 ............................................................................................................................................ 61

Port 9 ............................................................................................................................................ 62

Processor clock control register .................................................................................................. 68

Port mode register 0 .................................................................................................................... 63

Port mode register 1 .................................................................................................................... 63

Port mode register 2 .................................................................................................................... 63

Pull-up resistor option register 0 ................................................................................................. 64

Pull-up resistor option register B2 ............................................................................................... 64

[S]

SCKM: Suboscillation mode register ........................................................................................................ 69

[T]

TM80:

TM81:

16-bit timer counter 80 ................................................................................................................. 82

8-bit timer counter 81 ................................................................................................................... 82

TMC50: Remote control timer control register 50 ..................................................................................... 77

TMC80: 8-bit timer mode control register 80 ............................................................................................ 83

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169

APPENDIX C REGISTER INDEX

TMC81: 8-bit timer mode control register 81 ............................................................................................ 83

TXS10: Transmit/receive shift register 10 ................................................................................................ 97

[W]

WDCS: Watchdog timer clock select register .......................................................................................... 93

WDTM: Watchdog timer mode register .................................................................................................... 94

WTM: Watch timer mode control register .............................................................................................. 88

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