Hello, and welcome to this presentation of the STM32L4
System Configuration Controller.
STM32L4 devices feature a set of configuration
registers. The System Configuration Controller gives
access to the following features: Remapping memory
areas to address 0, managing the external interrupt line
connection to the GPIOs, certain robustness features,
SRAM2 write-protection and erase, floating point unit
interrupts, firewall control and finally the configuration of
the 20 mA high-drive I/Os used for I²C Fast-mode Plus.
Pictured here is the 4 gigabyte linear address mapping of
the STM32L4.
The Flash memory is up to 1 Mbytes, in a dual-bank
configuration. The FB_MODE bit determines the
address mapping of Banks 1 and 2, as shown. It also
determines which bank is aliased to address 0, which is
the start of the vector table as seen by the CortexM4
The SRAM total size is 128 Kbytes. It is split into 2 parts:
SRAM1 is 96 Kbytes starting from address 0xx20000000
and SRAM2 is 32 Kbytes starting from address
0x10000000. SRAM1 is located in the usual ARM
memory space for RAM while SRAM2 can be directly
accessed through Data code and Instruction code buses
with 0 wait states, and can be used for code execution.
The memory remap at address 0 allows to boost up
performance thanks to Instruction and Data bus access
instead of using the System bus.
The memory remap at address 0 is selected using the
MEM_MODE bits in the System Configuration Remap
register. They allow to select either the main Flash
memory, or the system Flash memory, the FMC bank 1
which addresses NOR or PSRAM, the SRAM1, or the
The FB_MODE bit in the System Configuration Remap
register allows to swap Flash memory banks 1 and 2,
which allows to boot either in Bank 1 or in Bank 2.
Here we have the STM32L4’s bus matrix. The bus
masters are shown on top, and the Cortex-M4 core and
the two DMA controllers communicate with the bus
slaves, shown on the right via the circled intersections.
The Flash memory is read through the accelerator.
Cortex-M4 instructions are fetched through Instruction
bus and Literal Pools are read through the Data bus. The
SRAM1 is accessed by default by the System bus, and
can be accessed though I-bus and D-bus when it is
remapped at address 0, shown by the dark blue circles in
order to increase performance. SRAM2 is always
accessed through the I-bus and D-bus allowing zerowait-state code execution. The Quad-SPI and FMC
banks can be read and executed through the System
bus by default, and can be remapped at 0 to increase
performance. The two DMAs can access all memories
and peripherals.
Different bus masters are able to access different
memories and peripherals simultaneously via the bus
matrix, enabling high performance compute operations.
There are 3 boot modes which are selected by the
BOOT0 pin and an option bit named nBOOT1. When
the BOOT0 pin is at a low level, the STM32L4 boots from
the User Flash memory, which is aliased at address 0.
This is the standard method of booting the STM32L4.
When the BOOT0 pin is at a high level, the nBOOT1 bit
determines the boot mode. The default option bit setting
is high, enabling the bootloader in the system memory
portion of the Flash memory. The other option is booting
from the SRAM1 memory region, which may be used for
debugging purposes.
When the selected boot is the User Flash memory, the
STM32L4 boots from Bank 1 if the option bit BFB2 is ‘0’,
which is the default value. If the BFB2 option bit is set to
‘1’, the STM32L4 boots from the Flash memory Bank 2,
as long as its first address is a valid SRAM address.
Otherwise it boots from Bank 1. This check ensures a
valid vector table.
The on-chip bootloader allows the user to program the
Flash memory through a serial communications
peripheral. The supported protocols are USART, USB,
CAN, SPI and I²C.
The 32 Kbytes of SRAM2 is particularly suitable for
performance, integrity and safety, and low power.
The SRAM2 is accessed through the Data and
Instruction busses without any remapping, which enables
code execution at zero-wait-states.
The SRAM2 supports parity check. The Data bus width
is 36 bits because 4 bits are available for parity check (1
bit per byte) in order to increase memory robustness, as
required, for instance, by Class B or SIL standards.
Class B and SIL are safety standards: Class B is for
Home Appliances and SIL for the Safety Integrity Level.
The parity bits are computed and stored when writing
into the SRAM. Then, they are automatically checked
when reading. If one bit fails, an NMI is generated. The
same error can also be linked to the Break input of the
timers. Note that the SRAM2 parity check is disabled by
The SRAM2 content can optionally be retained in
The SRAM2 is also suitable for secure applications.
The SRAM2 can be write-protected with a 1-Kbyte
The SRAM2 can also be readout-protected via the RDP
option byte. When protected, the SRAM2 cannot be read
or written by the JTAG or serial wire debug port, and
when the boot in System flash or boot in SRAM is
selected. The SRAM2 is erased when the readout
protection is changed from Level 1 to Level 0. Please
refer to the System Memory Protections training for
further details.
The SRAM2 can be erased by software by setting the
SRAM2ER bit in the SRAM2 System Configuration
Control and Status register. The SRAM2 can also be
erased with the system reset depending on the option bit
SRAM2_RST in the user option bytes.
The System Configuration Register 2 contains the
control and status bits linked to safety and robustness
such as the SRAM2 parity error flag, and the control bits
to direct some error detections events to the timers’
break inputs. This allows timer outputs to be placed in a
known state during an application crash. Once
programmed, the connection is locked until the next
system reset. These internal events include a Flash
error-code-correction event, a power voltage detector
event, SRAM2 parity error event, and the Cortex M4
hard fault.
The System Configuration Controller manages the
selection of the GPIO to the external interrupt or event
signal, which is used as asynchronous external interrupt
or event with wakeup from Stop capability.
Configuration register 1 contains the floating point unit
interrupt control bits. It contains also the I²C Fast-modePlus 20 mA drive enable control bits. Four I/Os can be
configured with high drive mode even if they are not
used as I2C alternate functions. They can be used to
drive LEDs for instance.
The I/O analog switch voltage booster is also selected
here as well as the Firewall.
Here we compare code execution performance at 80
MHz while running the EEMBC CoreMark benchmark.
The maximum performance is reached when the code is
executed in SRAM2 with data located in SRAM1. It is
also possible to reach maximum performance with code
in SRAM1 and data in SRAM2 if the SRAM1 is
remapped at address 0.
When executing from Flash memory at 80 MHz, the
maximum CoreMark performance is reached when the
ART accelerator is enabled, and there is almost no loss
of performance due to the Flash access time requiring 4
wait states at 80 MHz. Enabling the prefetch buffer yields
a slightly higher score, 3.35 CoreMark / MHz.
In addition to this training, you can refer to the Reset and
Clock Control, Power Controller, Interrupts, Flash and
System Memory Protections, Timers and I²C trainings.
For more details, please refer to application notes
AN2606 STM32 microcontroller system memory boot
mode and AN4435 Guidelines for obtaining UL/CSA/IEC
60335 Class B certification in any STM32 application.
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