Dallas semiconductor DS1302 (73-769-81)

Dallas semiconductor DS1302 (73-769-81)
Datum 971001
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73-769-81 DS1302 Seriell tidräknare
Antal sidor: 13
73-770-88 DS1302Z Seriell tidräknare (Y)
DS1302
DS1302
Trickle Charge Timekeeping Chip
FEATURES
PIN ASSIGNMENT
• Real time clock counts seconds, minutes, hours, date
of the month, month, day of the week, and year with
leap year compensation valid up to 2100
• 31 x 8 RAM for scratchpad data storage
• Serial I/O for minimum pin count
VCC2
1
8
VCC1
X1
2
7
SCLK
X2
3
6
I/O
GND
4
5
RST
DS1302
8–PIN DIP (300 MIL)
• 2.5–5.5 volt full operation
– Optional 2.0–5.5 volt full operation also available
VCC2
X1
X2
GND
• Uses less than 300 nA at 2.5 volts
• Single–byte or multiple–byte (burst mode) data trans-
1
2
3
4
8
7
6
5
VCC1
SCLK
I/O
RST
DS1302S 8–PIN SOIC (200 MIL)
DS1302Z 8–PIN SOIC (150 MIL)
fer for read or write of clock or RAM data
• 8–pin DIP or optional 8–pin SOIC’s for surface mount
• Simple 3–wire interface
• TTL–compatible (VCC = 5V)
• Optional industrial temperature range –40°C to +85°C
• DS1202 compatible
• Added features over DS1202
– Optional trickle charge capability to VCC1
– Dual power supply pins for primary and backup
power supplies
– Backup power supply pin can be used for battery
or super cap input
– Additional scratchpad memory (7 bytes)
PIN DESCRIPTION
X1, X2
GND
RST
I/O
SCLK
VCC1, VCC2
–
–
–
–
–
–
32.768 kHz Crystal Pins
Ground
Reset
Data Input/Output
Serial Clock
Power Supply Pins
ORDERING INFORMATION
PART #
DS1302
DS1302S
DS1302Z
DESCRIPTION
Serial Timekeeping Chip; 8–pin DIP
Serial Timekeeping Chip;
8–pin SOIC (200 mil)
Serial Timekeeping Chip;
8–pin SOIC (150 mil)
DESCRIPTION
The DS1302 Trickle Charge Timekeeping Chip contains
a real time clock/calendar and 31 bytes of static RAM. It
communicates with a microprocessor via a simple serial
interface. The real time clock/calendar provides
seconds, minutes, hours, day, date, month, and year
information. The end of the month date is automatically
adjusted for months with less than 31 days, including
corrections for leap year. The clock operates in either
the 24–hour or 12–hour format with an AM/PM indicator.
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
Interfacing the DS1302 with a microprocessor is simplified by using synchronous serial communication. Only
three wires are required to communicate with the clock/
RAM: (1) RST (Reset), (2) I/O (Data line), and (3) SCLK
(Serial clock). Data can be transferred to and from the
clock/RAM one byte at a time or in a burst of up to 31
bytes. The DS1302 is designed to operate on very low
power and retain data and clock information on less
than 1 microwatt.
041697 1/12
DS1302
After the first eight clock cycles have loaded the command word into the shift register, additional clocks will
output data for a read or input data for a write. The number of clock pulses equals eight plus eight for byte mode
or eight plus up to 248 for burst mode.
The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the DS1202,
the DS1302 has the additional features of dual power
pins for primary and back–up power supplies, programmable trickle charger for VCC1, and seven additional
bytes of scratchpad memory.
COMMAND BYTE
The command byte is shown in Figure 2. Each data
transfer is initiated by a command byte. The MSB (Bit 7)
must be a logic “1”. If it is zero, writes to the DS1302 will
be disabled. Bit 6 specifies clock/calendar data if logic
“0” or RAM data if logic “1”. Bits one through five specify
the designated registers to be input or output, and the
LSB (Bit 0) specifies a write operation (input) if logic “0”
or read operation (output) if logic “1”. The command
byte is always input starting with the LSB (Bit 0).
OPERATION
The main elements of the Serial Timekeeper are shown
in Figure 1: shift register, control logic, oscillator, real
time clock, and RAM. To initiate any transfer of data,
RST is taken high and eight bits are loaded into the shift
register providing both address and command information. Data is serially input on the rising edge of the SCLK.
The first eight bits specify which of 40 bytes will be
accessed, whether a read or write cycle will take place,
and whether a byte or burst mode transfer is to occur.
DS1302 BLOCK DIAGRAM Figure 1
VCC1
32.768 kHz
POWER
CONTROL
VCC2
GND
X1
I/O
OSCILLATOR
AND DIVIDER
REAL TIME
CLOCK
INPUT SHIFT
REGISTERS
X2
DATA BUS
SCLK
RST
COMMAND AND
CONTROL LOGIC
31 X 8 RAM
ADDRESS BUS
ADDRESS/COMMAND BYTE Figure 2
7
1
6
RAM
CK
041697 2/12
5
4
3
2
1
A4
A3
A2
A1
A0
0
RD
W
DS1302
RESET AND CLOCK CONTROL
All data transfers are initiated by driving the RST input
high. The RST input serves two functions. First, RST
turns on the control logic which allows access to the shift
register for the address/command sequence. Second,
the RST signal provides a method of terminating either
single byte or multiple byte data transfer.
A clock cycle is a sequence of a falling edge followed by
a rising edge. For data inputs, data must be valid during
the rising edge of the clock and data bits are output on
the falling edge of clock. If the RST input is low all data
transfer terminates and the I/O pin goes to a high impedance state. Data transfer is illustrated in Figure 3. At
power–up, RST must be a logic “0” until VCC2.5 volts.
Also SCLK must be at a logic “0” when RST is driven to a
logic “1” state.
DATA INPUT
Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the
next eight SCLK cycles. Additional SCLK cycles are
ignored should they inadvertently occur. Data is input
starting with bit 0.
DATA OUTPUT
Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of
the next eight SCLK cycles. Note that the first data bit to
be transmitted occurs on the first falling edge after the
last bit of the command byte is written. Additional SCLK
cycles retransmit the data bytes should they inadvertently occur so long as RST remains high. This operation permits continuous burst mode read capability.
Also, the I/O pin is tri–stated upon each rising edge of
SCLK. Data is output starting with bit 0.
However, when writing to RAM in burst mode it is not
necessary to write all 31 bytes for the data to transfer.
Each byte that is written to will be transferred to RAM
regardless of whether all 31 bytes are written or not.
CLOCK/CALENDAR
The clock/calendar is contained in seven write/read registers as shown in Figure 4. Data contained in the clock/
calendar registers is in binary coded decimal format
(BCD).
CLOCK HALT FLAG
Bit 7 of the seconds register is defined as the clock halt
flag. When this bit is set to logic “1”, the clock oscillator is
stopped and the DS1302 is placed into a low–power
standby mode with a current drain of less than 100
nanoamps. When this bit is written to logic “0”, the clock
will start.
AM-PM/12-24 MODE
Bit 7 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10 hour bit (20 – 23 hours).
WRITE PROTECT BIT
Bit 7 of the control register is the write protect bit. The
first seven bits (bits 0 – 6) are forced to zero and will
always read a zero when read. Before any write operation to the clock or RAM, bit 7 must be zero. When high,
the write protect bit prevents a write operation to any
other register.
TRICKLE CHARGE REGISTER
BURST MODE
Burst mode may be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (address/command bits one through five = logical
one). As before, bit six specifies clock or RAM and bit 0
specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or
writes in burst mode start with bit 0 of address 0.
As in the case with the DS1202, when writing to the
clock registers in the burst mode, the first eight registers
must be written in order for the data to be transferred.
This register controls the trickle charge characteristics
of the DS1302. The simplified schematic of Figure 5
shows the basic components of the trickle charger. The
trickle charge select (TCS) bits (bits 4 – 7) control the
selection of the trickle charger. In order to prevent accidental enabling, only a pattern of 1010 will enable the
trickle charger. All other patterns will disable the trickle
charger. The DS1302 powers up with the trickle charger
disabled. The diode select (DS) bits (bits 2 – 3) select
whether one diode or two diodes are connected
between VCC2 and VCC1. If DS is 01, one diode is
selected or if DS is 10, two diodes are selected. If DS is
00 or 11, the trickle charger is disabled independent of
041697 3/12
DS1302
TCS. The RS bits (bits 0 – 1) select the resistor that is
connected between VCC2 and VCC1. The resistor
selected by the resistor select (RS) bits is as follows:
RS Bits
Resistor
Typical Value
00
None
None
01
R1
2KΩ
10
R2
4KΩ
11
R3
8KΩ
If RS is 00, the trickle charger is disabled independent
of TCS.
Diode and resistor selection is determined by the user
according to the maximum current desired for battery or
super cap charging. The maximum charging current
can be calculated as illustrated in the following example.
Assume that a system power supply of 5V is applied to
VCC2 and a super cap is connected to VCC1. Also
assume that the trickle charger has been enabled with 1
diode and resistor R1 between VCC2 and VCC1. The
maximum current Imax would therefore be calculated as
follows:
Imax = (5.0V – diode drop) / R1
~ (5.0V – 0.7V) / 2KΩ
~ 2.2 mA
Obviously, as the super cap charges, the voltage drop
between VCC2 and VCC1 will decrease and therefore the
charge current will decrease.
to any of the eight clock/calendar registers (this includes
the control register). The trickle charger is not accessible in burst mode.
RAM
The static RAM is 31 x 8 bytes addressed consecutively
in the RAM address space.
RAM BURST MODE
The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively read or written (see Figure 4) starting with bit 0 of
address 0.
REGISTER SUMMARY
A register data format summary is shown in Figure 4.
CRYSTAL SELECTION
A 32.768 kHz crystal can be directly connected to the
DS1302 via pins 2 and 3 (X1, X2). The crystal selected
for use should have a specified load capacitance (CL) of
6 pF.
POWER CONTROL
VCC1 provides low power operation in single supply and
battery operated systems as well as low power battery
backup.
VCC2 provides the primary power in dual supply systems where VCC1 is connected to a backup source to
maintain the time and data in the absence of primary
power.
CLOCK/CALENDAR BURST MODE
The clock/calendar command byte specifies burst
mode operation. In this mode the first eight clock/calendar registers can be consecutively read or written (see
Figure 4) starting with bit 0 of address 0.
If the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur
041697 4/12
The DS1302 will operate from the larger of VCC1 or
VCC2. When VCC2 is greater than VCC1 + 0.2V, VCC2 will
power the DS1302. When VCC2 is less than VCC1, VCC1
will power the DS1302.
DS1302
DATA TRANSFER SUMMARY Figure 3
SINGLE BYTE TRANSFER
SCLK
RST
0
R/W
I/O
1
2
A0
A1
3
A2
4
A3
5
6
7
A4
R/C
1
0
1
2
ADDRESS COMMAND
3
4
5
6
7
DATA INPUT/OUTPUT
BURST MODE TRANSFER
SCLK
RST
0
R/W
I/O
1
1
2
1
3
1
4
1
5
6
7
1
R/C
1
ADDRESS COMMAND
0
1
DATA I/O BYTE 1
FUNCTION
BYTE N
SCLK n
CLOCK
8
72
RAM
31
256
2
4
5
6
7
DATA I/O BYTE N
041697 5/12
DS1302
REGISTER ADDRESS/DEFINITION Figure 4
REGISTER ADDRESS
A. CLOCK
7
6
5
REGISTER DEFINITION
4
3
2
1
SEC
1
0
0
0
0
0
0
MIN
1
0
0
0
0
0
1
HR
1
0
0
0
0
1
0
DATE
1
0
0
0
0
1
1
MONTH
1
0
0
0
1
0
0
DAY
1
0
0
0
1
0
1
YEAR
1
0
0
0
1
1
0
CONTROL
1
0
0
0
1
1
1
TRICKLE
CHARGER
1
0
0
1
0
0
0
CLOCK
BURST
1
0
1
1
1
1
1
RAM 0
1
1
0
0
0
0
0
RAM 30
1
1
1
1
1
1
0
RAM
BURST
1
1
1
1
1
1
1
0
RD
00–59
CH
10 SEC
SEC
00–59
0
10 MIN
MIN
W
01–12
00–23
12/
24
0
W
01–28/29
01–30
01–31
0
0
10 DATE
01–12
0
0
0
10
M
01–07
0
0
0
0
W
RD
W
RD
RD
RD
W
RD
W
RD
W
W
RD
W
RD
W
B. RAM
041697 6/12
RD
W
RD
W
RD
W
RAM DATA 0
RAM DATA 30
HR
HR
DATE
MONTH
0
10 YEAR
00–99
RD
10
A/P
DAY
YEAR
WP
0
0
0
0
0
0
0
TCS
TCS
TCS
TCS
DS
DS
RS
RS
DS1302
DS1302 PROGRAMMABLE TRICKLE CHARGER Figure 5
R1
2KΩ
VCC1
VCC2
R2
4KΩ
PIN #8
PIN #1
R3
8KΩ
1 OF 16 SELECT
1 OF 2
SELECT
(NOTE: ONLY 1010 CODE ENABLES CHARGER
TRICKLE
CHARGE
REGISTER
1 OF 3
SELECT
TCS
TCS
TCS
TCS
DS
DS
RS
RS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TCS
=
TRICKLE CHARGER SELECT
DS
=
DIODE SELECT
RS
=
RESISTOR SELECT
041697 7/12
DS1302
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
–0.5V to +7.0V
0°C to 70°C
–55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
The Dallas Semiconductor DS1302 is built to the highest quality standards and manufactured for long term reliability.
All Dallas Semiconductor devices are made using the same quality materials and manufacturing methods. However,
standard versions of the DS1302 are not exposed to environmental stresses, such as burn–in, that some industrial
applications require. Products which have successfully passed through this series of environmental stresses are
marked IND or N, denoting their extended operating temperature and reliability rating. For specific reliability information on this product, please contact the factory in Dallas at (972) 371–4448.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Supply Voltage VCC1, VCC2
SYMBOL
(0°C to 70°C)
MIN
TYP
MAX
UNITS
NOTES
VCC1,
VCC2
2.5
5.5
V
1, 11
Logic 1 Input
VIH
2.0
VCC+0.3
V
1
+0.3
VIL
VCC=2.5V
–0.3
Logic 0 Input
V
1
VCC=5V
–0.3
+0.8
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Input Leakage
ILI
I/O Leakage
ILO
Logic 1 Output
Logic 0 Output
Active Supply Current
Timekeeping Current
Standby Current
Active Supply Current
*Unless otherwise noted.
041697 8/12
(0°C to 70°C; VCC = 2.5 to 5.5V*)
SYMBOL
VOH
VOL
ICC1A
ICC1T
ICC1S
ICC2A
MIN
VCC=2.5V
1.6
VCC=5V
2.4
TYP
MAX
UNITS
NOTES
+500
µA
6
+500
µA
6
V
2
V
3
mA
5 12
5,
µA
4 12
4,12
nA
10, 12,
14
mA
5 13
5,
VCC=2.5V
0.4
VCC=5V
0.4
VCC1=2.5V
0.4
VCC1=5V
1.2
VCC1=2.5V
0.3
VCC1=5V
1
VCC1=2.5V
100
VCC1=5V
100
VCC2=2.5V
0.425
VCC2=5V
1.28
DS1302
DC ELECTRICAL CHARACTERISTICS (cont’d)
PARAMETER
Timekeeping Current
Standby Current
SYMBOL
ICC2T
ICC2S
(0°C to 70°C; VCC = 2.5 to 5.5V*)
MIN
TYP
MAX
VCC2=2.5V
25.3
VCC2=5V
81
VCC2=2.5V
25
VCC2=5V
80
UNITS
NOTES
µA
4 13
4,13
µA
10 13
10,
Trickle Charge Resistors
R1
R2
R3
2
4
8
KΩ
KΩ
KΩ
Trickle Charger Diode Voltage Drop
VTD
0.7
V
*Unless otherwise noted.
CAPACITANCE
PARAMETER
Input Capacitance
(tA = 25°C)
SYMBOL
CONDITION
TYP
MAX
UNITS
CI
10
pF
I/O Capacitance
CI/O
15
pF
Crystal Capacitance
CX
6
pF
(0°C to 70°C; VCC = +5V ± 10%*)
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Data to CLK Setup
CLK to Data Hold
CLK to Data Delay
CLK Low Time
CLK High Time
CLK Frequency
CLK Rise and Fall
RST to CLK Setup
SYMBOL
tDC
tCDH
tCDD
tCL
tCH
tCLK
tR, tF
tCC
NOTES
MIN
VCC =2.5V
200
VCC=5V
50
VCC=2.5V
280
VCC=5V
70
TYP
MAX
VCC=2.5V
800
VCC=5V
200
VCC=2.5V
1000
VCC=5V
250
VCC=2.5V
1000
VCC=5V
250
VCC=2.5V
VCC=5V
UNITS
NOTES
ns
7
ns
7
ns
7 8,
7,
8 9
ns
7
ns
7
MHz
7
0.5
DC
2.0
VCC=2.5V
2000
VCC=5V
500
ns
VCC=2.5V
4
VCC=5V
1
µs
7
*Unless otherwise noted.
041697 9/12
DS1302
(0°C to 70°C; VCC = +5V ± 10%*)
AC ELECTRICAL CHARACTERISTICS (cont’d)
PARAMETER
SYMBOL
CLK to RST Hold
tCCH
RST Inactive Time
tCWH
RST to I/O High Z
tCDZ
SCLK to I/O High Z
tCCZ
MIN
VCC =2.5V
240
VCC=5V
60
VCC=2.5V
4
VCC=5V
1
TYP
MAX
VCC=2.5V
280
VCC=5V
70
VCC=2.5V
280
VCC=5V
70
UNITS
NOTES
ns
7
µs
7
ns
7
ns
7
*Unless otherwise noted.
TIMING DIAGRAM: READ DATA TRANSFER Figure 5
RST
tCC
SCLK
tCCZ
tCDH
tCDZ
tCDD
tDC
I/O
tCDD
0
1
7
WRITE COMMAND BYTE
0
1
READ DATA BIT
TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6
tCWH
RST
tCC
tCCH
tR
tCL
tF
SCLK
tCDH
tCH
tDC
I/O
0
1
WRITE COMMAND BYTE
041697 10/12
7
0
WRITE DATA
DS1302
NOTES:
1. All voltages are referenced to ground.
2. Logic one voltages are specified at a source current of 1 mA at VCC=5V and 0.4 mA at VCC=2.5V, VOH=VCC for
capacitive loads.
3. Logic zero voltages are specified at a sink current of 4 mA at VCC=5V and 1.5 mA at VCC=2.5V, VOL=GND for
capacitive loads.
4. ICC1T and ICC2T are specified with I/O open, RST set to a logic “0”, and clock halt flag=0 (oscillator enabled).
5. ICC1A and ICC2A are specified with the I/O pin open, RST high, SCLK=2 MHz at VCC=5V; SCLK=500 kHz,
VCC=2.5V and clock halt flag=0 (oscillator enabled).
6. RST, SCLK, and I/O all have 40KΩ pulldown resistors to ground.
7. Measured at VIH=2.0V or VIL=0.8V and 10 ms maximum rise and fall time.
8. Measured at VOH=2.4V or VOL=0.4V.
9. Load capacitance = 50 pF.
10. ICC1S and ICC2S are specified with RST, I/O, and SCLK open. The clock halt flag must be set to logic one (oscillator
disabled).
11. VCC=VCC2, when VCC2>VCC1+0.2V; VCC=VCC1, when VCC1>VCC2.
12. VCC2=0 volts.
13. VCC1=0 volts.
14. Typical values are at 25°C.
DS1302 SERIAL TIMEKEEPER 8–PIN DIP
8
5
PKG
B
1
4
A
C
E
K
8–PIN
DIM
MIN
MAX
A IN.
MM
0.360
9.14
0.400
10.16
B IN.
MM
0.240
6.10
0.260
6.60
C IN.
MM
0.120
3.05
0.140
3.56
D IN.
MM
0.300
7.62
0.325
8.26
E IN.
MM
0.015
0.38
0.040
1.02
F IN.
MM
0.120
3.04
0.140
3.56
G IN.
MM
0.090
2.29
0.110
2.79
H IN.
MM
0.320
8.13
0.370
9.40
J IN.
MM
0.008
0.20
0.012
0.30
K IN.
MM
0.015
0.38
0.021
0.53
F
G
D
J
H
041697 11/12
DS1302
DS1302S SERIAL TIMEKEEPER 8–PIN SOIC (150 MIL AND 200 MIL)
8–PIN
(150 MIL)
PKG
DIM
MIN
MAX
MIN
MAX
A IN.
MM
0.188
4.78
0.196
4.98
0.203
5.16
0.213
5.41
B IN.
MM
0.150
3.81
0.158
4.01
0.203
5.16
0.213
5.41
C IN.
MM
0.048
1.22
0.062
1.57
0.070
1.78
0.074
1.88
E IN.
MM
0.004
0.10
0.010
0.25
0.004
0.10
0.010
0.25
F IN.
MM
0.053
1.35
0.069
1.75
0.074
1.88
0.084
2.13
G IN.
MM
0.050 BSC
1.27 BSC
H IN.
MM
0.230
5.84
0.244
6.20
0.302
7.67
0.318
8.08
J IN.
MM
0.007
0.18
0.011
0.28
0.006
0.15
0.010
0.25
K IN.
MM
0.012
0.30
0.020
0.51
0.013
0.33
0.020
0.51
L IN.
MM
0.016
0.41
0.050
1.27
0.019
0.48
0.030
0.76
phi
0°
8°
0°
8°
56–G2008–001
56–G4010–001
041697 12/12
8–PIN
(200 MIL)
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