datasheet for A43L2616B by AMIC Technology

datasheet for A43L2616B by AMIC Technology

A43L2616B

1M X 16 Bit X 4 Banks Synchronous DRAM

Document Title

1M X 16 Bit X 4 Banks Synchronous DRAM

Revision History

0.0 Initial issue

0.2

1.0

1.1

1.2

1.3

Add 54B Pb-Free CSP package type

Final version release

Change BS0 to BA0, BS1 to BA1

Add p art numbering scheme

Erase 54B CSP package type

August 24, 2006

February 14, 2007

March 15, 2007

Preliminary

April 3, 2007

August 15, 2007

February 15, 2008

December 16, 2009

Final

(December, 2009, Version 1.3)

AMIC Technology, Corp.

A43L2616B

1M X 16 Bit X 4 Banks Synchronous DRAM

Feature

̈

JEDEC standard 3.3V power supply

̈

LVTTL compatible with multiplexed address

̈

Four banks / Pulse RAS

̈

MRS cycle with address key programs

- CAS Latency (2,3)

- Burst Length (1,2,4,8 & full page)

Burst Type (Sequential & Interleave)

̈

All inputs are sampled at the positive going edge of the system clock

̈

Clock Frequency: 166MHz @ CL=3

143MHz @ CL=3

̈

Burst Read Single-bit Write operation

̈

DQM for masking

̈

Auto & self refresh

̈

64ms refresh period (4K cycle)

̈

Commercial Temperature Operation : 0 C~70 C

̈

Industrial Temperature Operation : -40 C~85 C for –U grade

̈

Available in 54-pin TSOP(II) package

̈

Package is available to lead free (-F series)

̈

All Pb-free (Lead-free) products are RoHS compliant

General Description

The A43L2616B is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 X 1,048,576 words by

16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock.

Pin Configuration

̈

TSOP (II)

I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28

A43L2616BV

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

(December, 2009, Version 1.3) 1

AMIC Technology, Corp.

Block Diagram

Data Input Register

Bank Select

CLK

1M X 16

1M X 16

1M X 16

1M X 16

ADD

LRAS

Column Decoder

Latency & Burst Length

LRAS LCBR LWE

LCAS

Programming Register

LWCBR

DQM

Timing Register

CLK CKE

CS RAS CAS WE

DQM

A43L2616B

LWE

DQM

DQi

(December, 2009, Version 1.3) 2

AMIC Technology, Corp.

A43L2616B

Pin Descriptions

Symbol Name

CLK

CS

System Clock

Chip Select

Description

Active on the positive going edge to sample all inputs.

Disables or Enables device operation by masking or enabling all inputs except

CLK, CKE and L(U)DQM

Masks system clock to freeze operation from the next clock cycle.

A0~A11 Address

BA0, BA1

Disable input buffers for power down in standby.

Row / Column addresses are multiplexed on the same pins.

Row address : RA0~RA11, Column address: CA0~CA7

Bank Select Address

Selects bank to be activated during row address latch time.

Selects band for read/write during column address latch time.

RAS

Row Address Strobe

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

CAS

WE

Column Address

Strobe

Write Enable

L(U)DQM

Data Input/Output

Mask

DQ

0-15

VDD/VSS

Data Input/Output

Power

Supply/Ground

VDDQ/VSSQ

Data Output

Power/Ground

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Enables write operation and Row precharge.

Makes data output Hi-Z, t SHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

Data inputs/outputs are multiplexed on the same pins.

Power Supply: +3.3V

±

0.3V/Ground

Provide isolated Power/Ground to DQs for improved noise immunity.

(December, 2009, Version 1.3) 3

AMIC Technology, Corp.

A43L2616B

Absolute Maximum Ratings*

Voltage on any pin relative to VSS (Vin, Vout ) . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +4.6V

Voltage on VDD supply relative to VSS (VDD, VDDQ )

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +4.6V

Storage Temperature (T

STG

) . . . . . . . . . . -55

°

C to +150

°

C

Soldering Temperature X Time (T

SOLDER

) . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

°

C X 10sec

Power Dissipation (P

D

) . . . . . . . . . . . . . . . . . . . . . . . . .1W

Short Circuit Current (Ios) . . . . . . . . . . . . . . . . . . . . 50mA

Capacitance (T

A

=25

°

C, f=1MHz)

*Comments

Permanent device damage may occur if “Absolute

Maximum Ratings” are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

Parameter Symbol Condition

Input Capacitance CI1 A0 to A11, BA0, BA1

CS

,

RAS

,

CAS

,

WE

,

DQM

2.5

Typ Unit

3.8

Data Input/Output Capacitance

DC Electrical Characteristics

CI/O DQ0 to DQ15 4

Recommend operating conditions (Voltage referenced to VSS = 0V, T

A

= 0ºC to +70ºC or T

A

= -40ºC to +85ºC)

6.5 pF pF

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

Input Leakage Current

Output Leakage Current

Output Loading Condition

VDD,VDDQ

V

IH

2.0 3.0 V

V

IL

-0.3 0 0.8 V Note

V

OH

2.4 - - V = -2mA

V

OL

- - 0.4 V

I

IL

-5 - 5

μ

A

I

OL

-5 - 5

μ

A

Note 2

Note 3

See Figure 1

Note:

1. V

IL

(min) = -1.5V AC (pulse width

5ns).

2. Any input 0V

VIN

VDD + 0.3V, all other pins are not under test = 0V

3. Dout is disabled, 0V

Vout

VDD

(December, 2009, Version 1.3) 4

AMIC Technology, Corp.

Decoupling Capacitance Guide Line

Recommended decoupling capacitance added to power line at board.

A43L2616B

Decoupling Capacitance between VDD and VSS

Decoupling Capacitance between VDDQ and VSSQ

C

DC1

C

DC2

0.1 + 0.01

0.1 + 0.01

μ

F

μ

F

Note:

1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

DC Electrical Characteristics

(Recommended operating condition unless otherwise noted, T

A

= 0

°

C to 70

°

C T

A

= -40ºC to +85ºC)

Symbol Parameter

Speed

Unit Notes

-6 -7

I

I

I

cc1 cc2 cc2

P

PS

Operating Current

(One Bank Active)

Precharge Standby Current in power-down mode

Burst Length = 1 t

RC

t

RC

(min), t

CC

t

CC

(min

)

, I

OL

= 0mA

CKE

V

IL

(max), t

CC

= 15ns

CKE

VIL(max), t

CC

=

I

I

CC2

CC2

I

CC3

I

N

CC4

Active Standby current in non power-down mode

(One Bank Active)

Operating Current

(Burst Mode)

I

CC5

Refresh

I

N

NS

CC6

Precharge Standby Current in non power-down mode

CKE

V

IH

(min), CS

V

IH

(min), t

CC

= 15ns

Input signals are changed one time during 30ns

CKE

V

IH

(min), CLK

V

IL

(max), t

CC

=

Input signals are stable.

Self Refresh Current

I t

CKE

OL

V

IH

(min), CS

All bank Activated, t

RC

= 0mA, Page Burst

t

RC

(min)

CKE

0.2V

CCD

V

IH

= t

(min), t

CCD

CC

(min)

= 15ns

Input signals are changed one time during 30ns

Note:

1. Measured with outputs open. Addresses are changed only one time during t

CC

(min).

2. Refresh period is 64ms. Addresses are changed only one time during t

CC

(min).

2

1

20

15 mA mA

30 mA

1.5 mA

1

1

2

(December, 2009, Version 1.3) 5

AMIC Technology, Corp.

A43L2616B

AC Operating Test Conditions

(VDD = 3.3V

±

0.3V, T

A

= 0

°

C to +70

°

C or T

A

= -40ºC to +85ºC)

Parameter Value

AC input levels

Input timing measurement reference level

Input rise and all time (See note3)

Output timing measurement reference level

Output load condition

V

IH

/V

1.4V

IL

= 2.4V/0.4V tr/tf = 1ns/1ns

1.4V

See Fig.2

3.3V

1200

Ω

V

OH

(DC) = 2.4V, I

OH

= -2mA

V

OL

(DC) = 0.4V, I

OL

= 2mA

V

TT

=1.4V

50

Ω

Output

OUTPUT Z

O

=50

Ω

870

Ω

50pF

50pF

(Fig. 2) AC Output Load Circuit

(Fig. 1) DC Output Load Circuit

AC Characteristics

(AC operating conditions unless otherwise noted) t t t

CC

SAC

OH

t

CH

CLK cycle time

CLK to valid Output delay

Output data hold time

CLK high pulse width

Min Max Min Max

3 6

1000

2 10

7

10

1000 ns 1

3 - 5 - 6 ns 1,2

2 - 6 - 6

3 2.5

-

2 3

3

- ns 2

3

2.5 - 3 - ns 3 t

CL

CLK low pulse width 2.5 - 3 - ns 3 t

SS

t

SH

Input setup time

Input hold time

1.5

1

-

-

2

1

-

- ns ns

3

3 t t

SLZ

SHZ

CLK to output in Low-Z

CLK to output In Hi-Z

1 - 1 - ns 2

3 - 5 - 6 ns

2 - 6 - 6

*All AC parameters are measured from half to half.

Note :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered, i.e.,

[

(tr + tf)/2-1

] ns should be added to the parameter.

(December, 2009, Version 1.3) 6

AMIC Technology, Corp.

A43L2616B

Operating AC Parameter

(AC operating conditions unless otherwise noted)

Symbol Parameter

Version

Unit Note

-6 -7

t

RRD(min)

Row active to row active delay t

RCD(min)

RAS to CAS delay

12 14 ns 1 t

RP(min)

Row precharge time 18 20 ns 1 t t

RAS(min)

ns

Row active time

RAS(max)

100

μ s t

RC(min)

Row cycle time 60 63 ns 1 t

CDL(min)

Last data in new col. Address delay t

RDL(min)

Last data in row precharge t

BDL(min)

Last data in to burst stop t

CCD(min)

Col. Address to col. Address delay

CAS Latency = 3

Number of valid output data

CAS Latency = 2

6

12

6

6

2

1

7

14

7

7 ns ns ns ns

2

2

2 ea 3

Note:

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. In case of row precharge interrupt, auto precharge and read burst stop.

(December, 2009, Version 1.3) 7

AMIC Technology, Corp.

A43L2616B

Simplified Truth Table

Command CKEn-1 CKEn

CS RAS CAS WE

DQM BA0 A10

BA1 /AP

A9~A0,

A11

Notes

Register

Mode Register Set

L L CODE 1,2

Refresh Auto Refresh

Self

Refresh

Bank Active & Row Addr.

Read & Auto Precharge Disable

Column Addr. Auto Precharge Enable

Write & Auto Precharge Disable

Column Addr. Auto Precharge Enable

Burst Stop

Precharge

Bank Selection

Both Banks

Clock Suspend or

Active Power Down

Precharge Power Down Mode

Entry

Entry

H

H

H

H

L

L L L H X X

3

3

L H H H

H

H X X X

3

X X

3

X L L H H X V Row Addr. 4

L

X L

L H H H

H L

Entry H L

H H L

H X X X

L H H H

H X X X

Exit L

L V V V

H

H X X X

X

X

X

X

V

L

L

X

X

X

Column

Addr.

Column

Addr.

X

4

4,5

4

4,5

No Operation Command H X

L H H H

X X

H X X X

(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)

Note :

1. OP Code: Operand Code

A0~A11, BA0, BA1: Program keys. (@MRS)

2. MRS can be issued only at both banks precharge state.

A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions as same as CBR refresh of DRAM.

The automatical precharge without Row precharge command is meant by “Auto”.

Auto/Self refresh can be issued only at both precharge state.

4. BA0, BA1 : Bank select address.

If both BA1 and BA0 are “Low” at read, write, row active and precharge, bank A is selected.

If both BA1 is “Low” and BA0 is “High” at read, write, row active and precharge, bank B is selected.

If both BA1 is “High” and BA0 is “Low” at read, write, row active and precharge, bank C is selected.

If both BA1 and BA0 are “High” at read, write, row active and precharge, bank D is selected.

If A10/AP is “High” at row precharge, BA1 and BA0 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read write command cannot be issued.

Another bank read write command can be issued at every burst length.

6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0) but masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)

(December, 2009, Version 1.3) 8

AMIC Technology, Corp.

A43L2616B

Mode Register Filed Table to Program Modes

Register Programmed with MRS

Address BA0, BA1

Function RFU

(Note 1) (Note 2)

Test Mode

A8 A7 Type

A11, A10

RFU

A9

W.B.L

A8

TM

A7 A6 A5

CAS Latency

A4 A3

BT

A2 A1

Burst Length

A0

CAS Latency

A6 A5 A4 Latency A3

Burst Type

Type A2

Burst Length

A1 A0 BT=0 BT=1

0 0

0 1

Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0

Vendor 0 0 1 - 1 Interleave 0 0 1

1

2

1 0

1 1

Use

Only

0 1 0

0 1 1

2

3

0

0

1 0

1 1

4

8

Write Burst Length

1 0 0 Reserved

1

2

4

8

1 0 0 Reserved Reserved

A9 Length 1 0 1 Reserved

0 Burst 1 Reserved

1 0 1 Reserved Reserved

1 Reserved Reserved

Bit 1 Reserved 1 1 1 256(Full) Reserved

Power Up Sequence

1. Apply power and start clock, Attempt to maintain CKE = “H”, DQM = “H” and the other pins are NOP condition at inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200

μ s.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 may be changed.

The device is now ready for normal operation.

Note :

1. RFU(Reserved for Future Use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “Burst Read Single Bit Write” function will be enabled.

(December, 2009, Version 1.3) 9

AMIC Technology, Corp.

A43L2616B

Burst Sequence (Burst Length = 4)

Initial address

A1 A0

Sequential Interleave

0 0 0 1 2 3 0 1 2 3

0 1 1 2 3 0 1 0 3 2

1 0 2 3 0 1 2 3 0 1

1 1 3 0 1 2 3 2 1 0

Burst Sequence (Burst Length = 8)

Initial address

Sequential Interleave

A2 A1 A0

0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6

0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5

0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4

1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3

1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2

1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1

1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0

(December, 2009, Version 1.3) 10

AMIC Technology, Corp.

A43L2616B

Device Operations

Clock (CLK)

The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V

IL

and V

IH

. During operation with CKE high all inputs are assumed to be in valid state (low or high) for the duration of set up and hold time around positive edge of the clock for proper functionality and ICC specifications.

Clock Enable (CKE)

The clock enable (CKE) gates the clock onto SDRAM. If

CKE goes low synchronously with clock (set-up and hold time same as other inputs), the internal clock is suspended form the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When both banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode form the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When

CKE goes high at least “t

SS

+ 1

CLOCK

” before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands.

Bank Select (BA0, BA1)

This SDRAM is organized as 4 independent banks of

1,048,576 words X 16 bits memory arrays. The BA0, BA1 inputs is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank select BA0, BA1 is latched at bank activate, read, write mode register set and precharge operations.

Address Input (A0 ~ A11)

The 20 address bits required to decode the 262,144 word locations are multiplexed into 12 address input pins

(A0~A11). The 12 bit row address is latched along with

RAS , BA0 and BA1 during bank activate command. The 8 bit column address is latched along with

CAS

, WE , BA0 and BA1during read or write command.

NOP and Device Deselect

When RAS , CAS and

WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS ,

CAS

and

WE

, and all the address inputs are ignored.

Power-Up

The following sequence is recommended for POWER UP

1. Power must be applied to either CKE and DQM inputs to pull them high and other pins are NOP condition at the inputs before or along with VDD (and VDDQ) supply.

The clock signal must also be asserted at the same time.

2. After VDD reaches the desired voltage, a minimum pause of 200 microseconds is required with inputs in

NOP condition.

3. Both banks must be precharged now.

4. Perform a minimum of 2 Auto refresh cycles to stabilize the internal circuitry.

5. Perform a MODE REGISTER SET cycle to program the

CAS latency, burst length and burst type as the default value of mode register is undefined.

At the end of one clock cycle from the mode register set cycle, the device is ready for operation.

When the above sequence is used for Power-up, all the out-puts will be in high impedance state. The high impedance of outputs is not guaranteed in any other power-up sequence. cf.) Sequence of 4 & 5 may be changed.

Mode Register Set (MRS)

The mode register stores the data for controlling the various operation modes of SDRAM. It programs the CAS latency, addressing mode, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS , RAS ,

CAS

, WE (The SDRAM should be in active mode with

CKE already high prior to writing the mode register). The state of address pins A0~A11, BA0 and BA1 in the same cycle as CS , RAS ,

CAS

, WE going low is the data written in the mode register. One clock cycle is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as both banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length field uses A0~A2, burst type uses A3, addressing mode uses A4~A6, A7~A8, A11, BA0 and BA1 are used for vendor specific options or test mode. And the write burst length is programmed using A9. A7~A8, A11, BA0 and BA1 must be set to low for normal SDRAM operation.

Refer to table for specific codes for various burst length, addressing modes and CAS latencies.

(December, 2009, Version 1.3) 11

AMIC Technology, Corp.

Device Operations (continued)

Bank Activate

The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and

CS with desired row and bank addresses, a row access is initiated. The read or write operation can occur after a time delay of t

RCD

(min) from the time of bank activation. t

RCD

(min) is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing t

RCD

(min) with cycle time of the clock and then rounding off the result to the next higher integer. The

SDRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of both banks immediately. Also the noise generated during sensing of each bank of SDRAM is high requiring some time for power supplies recover before the other bank can be sensed reliably. t

RRD

(min) specifies the minimum time required between activating different banks. The number of clock cycles required between different bank activation must be calculated similar to t

RCD

specification. The minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t

RAS

(min) specification before a precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by t

RAS

(max). The number of cycles for both t

RAS

(min) and t

RAS

(max) can be calculated similar to t

RCD

specification.

Burst Read

The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and

CAS with WE being high on the positive edge of the clock. The bank must be active for at least t

RCD

(min) before the burst read command is issued. The first output appears CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length.

A43L2616B

Burst Write

The burst write command is similar to burst read command, and is used to write data into the SDRAM consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on

CS ,

CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing may not have been completed yet. The writing can not complete to burst length. The burst write can be terminated by issuing a burst read and DQM for blocking data inputs or burst write in the same or the other active bank. The burst stop command is valid only at full page burst length where the writing continues at the end of burst and the burst is wrap around.

The write burst can also be terminated by using DQM for blocking data and precharging the bank “t

RDL

” after the last data input to be written into the active row. See DQM

OPERATION also.

DQM Operation

The DQM is used to mask input and output operation. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means

DQM masking occurs two cycles later in the read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock, therefore the masking occurs for a complete cycle. The DQM signal is important during burst interrupts of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required.

Precharge

The precharge operation is performed on an active bank by asserting low on CS , RAS , WE and A10/AP with valid

BA of the bank to be precharged. The precharge command can be asserted anytime after t

RAS

(min) is satisfied from the bank activate command in the desired bank. “t

RP

” is defined as the minimum time required to precharge a bank.

The minimum number of clock cycles required to complete row precharge is calculated by dividing “t

RP

” with clock cycle time and rounding up to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by t

RAS

(max). Therefore, each bank has to be precharged within t

RAS

(max) from the bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again.

Entry to Power Down, Auto refresh, Self refresh and Mode register Set etc, is possible only when both banks are in idle state.

(December, 2009, Version 1.3) 12

AMIC Technology, Corp.

A43L2616B

Device Operations (continued)

Auto Precharge

The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy t

RAS

(min) and “t

RP

” for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst read or burst write by asserting high on A10/AP. If burst read or burst write command is issued with low on A10/AP, the bank is left active until a new command is asserted. Once auto precharge command is given, no new commands are possible to that particular bank until the bank achieves idle state.

Four Banks Precharge

Both banks can be precharged at the same time by using

Precharge all command. Asserting low on

CS

,

RAS and

WE with high on A10/AP after both banks have satisfied t

RAS

(min) requirement, performs precharge on both banks.

At the end of tRP after performing precharge all, both banks are in idle state.

Auto Refresh

The storage cells of SDRAM need to be refreshed every

64ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS ,

RAS and CAS with high on CKE and

WE

. The auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by “t

RC

(min)”. The minimum number of clock cycles required can be calculated by driving “t

RC

” with clock cycle time and then rounding up to the next higher integer. The auto refresh command must be followed by NOP’s until the auto refresh operation is completed. Both banks will be in the idle state at the end of auto refresh operation. The auto refresh is the preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed once in 15.6us or a burst of 4096 auto refresh cycles once in 64ms.

Self Refresh

The self refresh is another refresh mode available in the

SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing is internally generated to reduce power consumption.

The self refresh mode is entered from all banks idle state by asserting low on CS , RAS , CAS and CKE with high on WE . Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including clock are ignored to remain in the self refresh.

The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by

NOP’s for a minimum time of “t

RC

” before the SDRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to used burst 4096 auto refresh cycles immediately after exiting self refresh.

(December, 2009, Version 1.3) 13

AMIC Technology, Corp.

Basic feature And Function Descriptions

1. CLOCK Suspend

1) Click Suspended During Write (BL=4)

CLK

CMD

CKE

Internal

CLK

WR

Masked by CKE

DQ(CL2)

DQ(CL3)

D0

D0

D1

D1

D2

D2

Not Written

D3

D3

Note: CLK to CLK disable/enable=1 clock

2. DQM Operation

2) Clock Suspended During Read (BL=4)

RD

Masked by CKE

A43L2616B

Q0 Q1

Q0

Q2 Q3

Q1 Q2

Suspended Dout

Q3

1) Write Mask (BL=4)

CLK

CMD

DQM

DQ(CL2)

DQ(CL3)

WR

D0

D0

D1

Masked by CKE

D3

D1 D3

DQM to Data-in Mask = 0CLK

2) Read Mask (BL=4)

RD

Q0

Hi-Z

Masked by CKE

Q2 Q3

Hi-Z

Q1 Q2 Q3

DQM to Data-out Mask = 2

2) Read Mask (BL=4)

CLK

CMD

CKE

RD

DQM

DQ(CL2)

DQ(CL3)

Q0

Hi-Z

Hi-Z

Q2

Q1

Hi-Z

Hi-Z

Q4

Q3

Hi-Z

Hi-Z

Q6

Q5

Q7

Q6

Q8

Q7

* Note :

1. DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”.

2. DQM masks both data-in and data-out.

(December, 2009, Version 1.3) 14

AMIC Technology, Corp.

3. CAS Interrupt (I)

1) Read interrupted by Read (BL=4)

Note 1

CLK

CMD

ADD

DQ(CL2)

DQ(CL3)

RD

A

RD

B

QA0 QB0 QB1 QB2 QB3

QA0 QB0 QB1 QB2 QB3 t

CCD

Note2

CLK

CMD

ADD

DQ

2) Write interrupted by Write (BL =2)

WR

A

WR t

CCD Note2

B

DA0 DB0 DB1 t

CDL

Note3

A43L2616B

3) Write interrupted by Read (BL =2)

DQ(CL2)

DQ(CL3)

WR RD

A t

CCD Note2

B

DA0

DA0 t

CDL

Note3

QB0 QB1

QB0 QB1

Note : 1. By “Interrupt”, It is possible to stop burst read/write by external command before the end of burst.

By “

CAS

Interrupt”, to stop burst read/write by

CAS

access; read, write and block write.

2. t

CCD

: CAS to CAS delay. (=1CLK)

3. t

CDL

: Last data in to new column address delay. (= 1CLK).

(December, 2009, Version 1.3) 15

AMIC Technology, Corp.

4. CAS Interrupt (II) : Read Interrupted Write & DQM

(1) CL=2, BL=4

CLK i) CMD

DQM

DQ ii) CMD

DQM

DQ iii) CMD

DQM

DQ iv) CMD

DQM

DQ

(2) CL=3, BL=4

CLK i) CMD

DQM ii) CMD

DQ

DQM

DQ iii) CMD

DQM

DQ iv) CMD

DQM

DQ v) CMD

DQM

DQ

RD WR

RD

D0 D1

WR

D2 D3

RD

Hi-Z

D0 D1

WR

D2 D3

RD

Hi-Z

D0 D1

WR

D2 D3

RD WR

Q0

Hi-Z

Note 1

D0 D1 D2 D3

RD

D0 D1

WR

D2 D3

RD

RD

RD

D0 D1

WR

D2 D3

D1

WR

D2 D3

Hi-Z

D0 D1

WR

D2 D3

Q0

Hi-Z

Note 2

D0 D1 D2 D3

A43L2616B

* Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.

2. To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out.

(December, 2009, Version 1.3) 16

AMIC Technology, Corp.

5. Write Interrupted by Precharge & DQM

A43L2616B

CLK

CMD

DQM

DQ

WR PRE

Note 1

Note 2

D0 D1 D2 D3

Masked by DQM

Note : 1. To inhibit invalid write, DQM should be issued.

2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual banks operation.

6. Precharge

1 ) N o r m a l W r it e ( B L = 4 )

C L K

C M D

D Q

W R

D 0 D 1

2 ) R e a d ( B L = 4 )

C L K

C M D

D Q ( C L 2 )

R D

D Q ( C L 3 )

D 2

Q 0

D 3

Q 1

Q 0 t

R D L

P R E

P R E

Q 2

Q 1

Q 3

Q 2 Q 3

7. Auto Precharge

1) Normal Write (BL=4)

CLK

CMD

DQ

CLK

CMD

DQ(CL2)

DQ(CL3)

WR

D0

2) Read (BL=4)

RD

D1 D2

Q0

D3

Q1

Note 1

Auto Precharge Starts

Q2 Q3

Q0 Q1 Q2

Note 1

Auto Precharge Starts

Q3

* Note : 1. The row active command of the precharge bank can be issued after t

RP

from this point.

The new read/write command of other active bank can be issued from this point.

At burst read/write with auto precharge,

CAS interrupt of the same/another bank is illegal.

(December, 2009, Version 1.3) 17

AMIC Technology, Corp.

8. Burst Stop & Interrupted by Precharge

1) Normal Write (BL=4)

CLK

CMD

WR

DQM

DQ D0 D1 D2 D3 t

RDL

Note 1

PRE

1) Read Interrupted by Precharge (BL=4)

CLK

CMD

RD PRE

DQ(CL2)

DQ(CL3)

Q0 Q1

Note 3

1

Q0 Q1

2

A43L2616B

2) Write Burst Stop (BL=8)

CLK

CMD

WR

DQM

DQ D0 D1 D2

STOP

D3 D4 t

BDL

Note 2

D5

4) Read Burst Stop (BL=4)

CLK

CMD

RD STOP

Q0 DQ(CL2)

DQ(CL3)

Q1

1

Q0 Q1

2

9. MRS

Mode Register Set

CLK

CMD

PRE

Note 1 t

RP

MRS ACT

2CLK

Note : 1. t

RDL

: 1CLK

2. : 1CLK; Last data in to burst stop delay.

Read or write burst stop command is valid at every burst length.

3. Number of valid output data after row precharge or burst stop: 1,2 for CAS latency = 2, 3 respectively.

4. PRE: All banks precharge if necessary.

MRS can be issued only when all banks are in precharged state.

10. Clock Suspend Exit & Power Down Exit

1) Clock Suspend (=Active Power Down) Exit

CLK

CKE

Internal

CLK

Note 1 t

SS

CMD

RD

2) Power Down (=Precharge Power Down) Exit

CLK

CKE

Internal

CLK

Note 2 t

SS

CMD

NOP ACT

(December, 2009, Version 1.3) 18

AMIC Technology, Corp.

11. Auto Refresh & Self Refresh

1) Auto Refresh

Note 3

CLK

CM D

Note 4

PRE

CKE t

RP

AR CM D

Note 5

A43L2616B

t

RC

2) Self Refresh

Note 6

CLK

CM D

CKE

PRE

Note 4

SR CM D t

RP

t

RC

* Note : 1. Active power down : one or more bank active state.

2. Precharge power down : both bank precharge state.

3. The auto refresh is the same as CBR refresh of conventional DRAM.

No precharge commands are required after Auto Refresh command.

During t

RC

from auto refresh command, any other command can not be accepted.

4. Before executing auto/self refresh command, both banks must be idle state.

5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.

6. During self refresh mode, refresh interval and refresh operation are performed internally.

After self refresh entry, self refresh mode is kept while CKE is LOW.

During self refresh mode, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.

During t

RC

from self refresh exit command, any other command can not be accepted.

Before/After self refresh mode, burst auto refresh cycle (4K cycles ) is recommended.

(December, 2009, Version 1.3) 19

AMIC Technology, Corp.

A43L2616B

12. About Burst Type Control

Basic

MODE

Random

MODE

Sequential counting

Interleave counting

Random column Access t

CCD

= 1 CLK

At MRS A3=”0”. See the BURST SEQUENCE TABE.(BL=4,8)

BL=1,2,4,8 and full page wrap around.

At MRS A3=” 1”. See the BURST SEQUENCE TABE.(BL=4,8)

BL=4,8 At BL=1,2 Interleave Counting = Sequential Counting

Every cycle Read/Write Command with random column address can realize

Random Column Access.

That is similar to Extended Data Out (EDO) Operation of convention DRAM.

13. About Burst Length Control

Basic

MODE

Special

MODE

Interrupt

MODE

1

2

4

8

At MRS A2,1,0 = “000”.

At auto precharge, tRAS should not be violated.

At MRS A2,1,0 = “001”.

At auto precharge, tRAS should not be violated.

At MRS A2,1,0 = “010”

At MRS A2,1,0 = “011”.

BRSW

RAS Interrupt

(Interrupted by Precharge)

CAS

Interrupt

At MRS A9=”1”.

Read burst = 1,2,4,8, full page/write Burst =1

At auto precharge of write, tRAS should not be violated.

Before the end of burst, Row precharge command of the same bank

Stops read/write burst with Row precharge. t

RDL

=1 with DQM, valid DQ after burst stop is 1,2 for CL=2,3 respectively

During read/write burst with auto precharge, RAS interrupt cannot be issued.

Before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write.

During read/write burst with auto precharge, CAS interrupt can not be issued.

(December, 2009, Version 1.3) 20

AMIC Technology, Corp.

Power On Sequence & Auto Refresh

A43L2616B

CLOCK

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CKE

CS

High level is necessary t

RP

RAS t

RC

~ ~

~ ~

~ ~

~ ~

CAS

~ ~ ~ ~

ADDR KEY Ra

~ ~ ~ ~

BA0, BA1 BA

~ ~ ~ ~

A10/AP Ra

~ ~ ~ ~

WE

DQM

High level is necessary

High-Z

DQ

Precharge

(All Banks)

Auto Refresh

~ ~

~ ~

~ ~

Auto Refresh

~ ~

~ ~

~ ~

Mode Regiser Set

Row Active

(A-Bank)

: Don't care

(December, 2009, Version 1.3) 21

AMIC Technology, Corp.

A43L2616B

Single Bit Read-Write-Read Cycles (Same Page) @CAS Latency=3, Burst Length=1

CLOCK

0 1 2 t

CC

3 t

CH

4 t

CL

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

High

CKE t

RAS

t

RC

t

SH

*Note 1

CS t

SS

t

RCD

t

RP

t

SH

RAS t

SS

t

CCD

t

SH

CAS t

SS

ADDR t

SS

t

SH

Ra

BA0, BA1

*Note 2

BA

Ca

*Note 2,3

BA t

SS

t

SH

Cb

*Note 2,3

BA

Cc

*Note 2,3 *Note 4

BA BA

Rb

*Note 2

BA

*Note 3 *Note 3 *Note 3 *Note 4

A10/AP Ra Rb

WE

DQM

DQ

Row Active t

RAC

Read t

SH

t

SS

t

SS

t

SH

t

SAC

t

SLZ

t

OH

Qa t

SS

t

SHZ

Db t

SH

Write

Read

Precharge

Qc

Row Active

: Don't care

(December, 2009, Version 1.3) 22

AMIC Technology, Corp.

A43L2616B

* Note : 1. All inputs can be don’t care when CS is high at the CLK high going edge.

2. Bank active & read/write are controlled by BA0, BA1.

BA1 BA0 Active & Read/Write

0 0

0 1

1 0

1 1

3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.

A10/AP BA1 BA0

0

1

0

0

1

1

0

0

1

1

Operation

0 Disable auto precharge, leave bank A active at end of burst.

1 Disable auto precharge, leave bank B active at end of burst.

0 Disable auto precharge, leave bank C active at end of burst.

1 Disable auto precharge, leave bank D active at end of burst.

0 Enable auto precharge, precharge bank A at end of burst.

1 Enable auto precharge, precharge bank B at end of burst.

0 Enable auto precharge, precharge bank C at end of burst.

1 Enable auto precharge, precharge bank D at end of burst.

4. A10/AP and BA0, BA1 control bank precharge when precharge command is asserted.

A10/AP BA1 BA0 Precharge

0 0 0

0 0 1

0 1 0

0 1 1

1 X X

(December, 2009, Version 1.3) 23

AMIC Technology, Corp.

Read & Write Cycle at Same Bank @Burst Length=4

A43L2616B

ADDR

BA0

BA1

A10/AP

CLOCK

0

CKE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

High t

RC

*Note 1

CS t

RCD

RAS

CAS

*Note 2

Ra Ca0 Rb Cb0

Ra Rb

WE

DQM

DQ

(CL = 2)

DQ

(CL = 3) t

RAC

*Note 3 t

SAC

t

OH

Qa0 Qa1 Qa2 t

SHZ

Qa3 t

RAC

*Note 3

*Note 4 t

SAC

t

OH

Qa0 Qa1 Qa2 Qa3 t

SHZ

*Note 4

Db0 Db1 Db2 t

RDL

Db3

Db0 Db1 Db2 Db3 t

RDL

Row Active

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

Row Active

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row enters precharge.

Last valid output will be Hi-Z after t

SHZ

from the clock.

3. Access time from Row address. t

CC

*(t

RCD

+ CAS latency-1) + t

SAC

4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)

(December, 2009, Version 1.3) 24

AMIC Technology, Corp.

A43L2616B

Page Read & Write Cycle at Same Bank @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10

CLOCK

11 12 13 14 15 16 17 18 19

CKE High

CS t

RCD

RAS

*Note 2

CAS

Ra Ca Cb Cc Cd ADDR

BA0

BA1

A10/AP Ra t

RDL

t

CDL

WE

*Note 2

*Note1 *Note3

DQM

DQ

(CL=2)

Qa0 Qa1 Qb0 Qb1

Qb2

Dc0 Dc1 Dd0 Dd1

DQ

(CL=3)

Qa0 Qa1 Qb0 Qb1 Dc0 Dc1 Dd0 Dd1

Row Active

(A-Bank)

Read

(A-Bank)

Read

(A-Bank)

Write

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention.

2. Row precharge will interrupt writing. Last data input, t

RDL

before Row precharge, will be written.

3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally.

(December, 2009, Version 1.3) 25

AMIC Technology, Corp.

A43L2616B

Page Read Cycle at Different Bank @Burst Length = 4

0 1 2 3 4 5 6 7 8 9

CLOCK

10 11 12 13 14 15 16 17 18 19

CKE

CS

*Note 1

High

*Note 2

RAS

CAS

ADDR

RAa RBb CAa RCc CBb RDd CCc CDd

BA0

BA1

A10/AP

WE

DQM

DQ

(CL=2)

DQ

(CL=3)

RAa RBb

RCc RDd

QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2

QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2

Row Active

(A-Bank)

Read

(A-Bank)

Row Active

(B-Bank)

Read

(B-Bank)

Row Active

(C-Bank)

Precharge

(A-Bank)

Read

(C-Bank)

Row Active

(D-Bank)

Precharge

(B-Bank)

Read

(D-Bank)

Precharge

(C-Bank)

Precharge

(D-Bank)

* Note : 1. CS can be don’t care when RAS ,

CAS and

WE

are high at the clock high going edge.

2. To interrupt a burst read by row precharge, both the read ad the precharge banks must be the same.

: Don't care

(December, 2009, Version 1.3) 26

AMIC Technology, Corp.

A43L2616B

Page Write Cycle at Different Bank @Burst Length=4

0 1 2 3 4 5 6 7 8 9

CLOCK

10 11 12 13 14 15 16 17 18 19

High CKE

CS

RAS

CAS

ADDR

BA0

BA1

A10/AP

RAa

RAa

DQ

WE

DQM

RBb CAa CBb RCc RDd CCc CDd

RBb RCc RDd

DAa0 DAa1 DAa2 DAa3 t

CDL

DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 CDd2 t

RDL

*Note 1

*Note 2

Row Active

(A-Bank)

Write

(A-Bank)

Row Active

(B-Bank)

Write

(B-Bank)

Row Active

(C-Bank)

Row Active

(D-Bank)

Write

(C-Bank)

Write

(D-Bank)

* Note:

1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.

2. To interrupt burst write by Row precharge, both the write and precharge banks must be the same.

Precharge

(All Banks)

: Don't care

(December, 2009, Version 1.3) 27

AMIC Technology, Corp.

A43L2616B

Read & Write Cycle at Different Bank @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12

CLOCK

13 14 15 16 17 18 19

High CKE

CS

WE

DQM

DQ

(CL=2)

DQ

(CL=3)

RAS

CAS

ADDR

BA0

RAa

BA1

A10/AP RAa

CAa RDb

RDb

QAa0 QAa1 QAa2 QAa3

QAa0 QAa1 QAa2 QAa3

CDb RBc

RBC

DDb0 DDb1 DDb2 DDb3

DDb0 DDb1 DDb2 DDb3

CBc t

CDL

*Note 1

QBc0 QBc1 QBc2

QBc0 QBc1

Row Active

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

Row Active

(D-Bank)

* Note : t

CDL

should be met to complete write.

Write

(D-Bank)

Row Active

(B-Bank)

Read

(B-Bank)

: Don't care

(December, 2009, Version 1.3) 28

AMIC Technology, Corp.

A43L2616B

Read & Write Cycle with Auto Precharge @Burst Length=4

0 1 2 3 4 5 6 7 8 9 10

CLOCK

11 12 13 14 15 16 17 18 19

High CKE

CS

RAS

CAS

ADDR

BA0

BA1

RAa

A10/AP

WE

RAa

RBb CAa

RBb

CBb

DQM

DQ

(CL=2)

DQ

(CL=3)

QAa0 QAa1 QAa2 QAa3

QAa0 QAa1 QAa2 QAa3

DDb0 DDb1 DDb2 DDb3

DDb0 DDb1 DDb2 DDb3

Row Active

(A-Bank)

Read with

Auto Precharge

(A-Bank)

Row Active

(D-Bank)

Auto Precharge

Start Point

(A-Bank/CL=3)

Auto Precharge

Start Point

(A-Bank/CL=2)

Write with

Auto Precharge

(D-Bank)

*Note : tRCD should be controlled to meet minimum tRAS before internal precharge start.

(In the case of Burst Length=1 & 2, BRSW mode)

Auto Precharge

Start Point

(D-Bank)

: Don't care

(December, 2009, Version 1.3) 29

AMIC Technology, Corp.

A43L2616B

Clock Suspension & DQM Operation Cycle @CAS Latency = 2, Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

CLOCK

16 17 18 19

CKE

CS

RAS

CAS

ADDR

BA0

BA1

Ra Ca Cb Cc

Ra A10/AP

WE

* Note 1

DQM

DQ Qa0 Qa1 Qa2 t

SHZ

Qa3 Qb0 Qb1 t

SHZ

Dc0 Dc2

Row Active Read

Clock

Suspension

Read

Read DQM

Write

Write

DQM

Clock

Suspension

: Don't care

* Note : DQM needed to prevent bus contention.

(December, 2009, Version 1.3) 30

AMIC Technology, Corp.

A43L2616B

Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full Page

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

CLOCK

19

High CKE

CS

RAS

CAS

ADDR

BA0

BA1

RAa CAa CAb

A10/AP

RAa

WE

DQM

DQ

(CL=2)

QAa0 QAa1 QAa2 QAa3

1

QAa4

QAa0 QAa1 QAa2 QAa3

2

QAa4

QAb0 QAb1 QAb2 QAb3

1

QAb4 QAb5

QAb0 QAb1 QAb2 QAb3

2

QAb4 QAb5

DQ

(CL=3)

Row Active

(A-Bank)

Read

(A-Bank)

Burst Stop

Read

(A-Bank)

* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. About the valid DQ’s after burst stop, it is same as the case of RAS interrupt.

Both cases are illustrated above timing diagram. See the label 1,2 on them.

But at burst write, burst stop and RAS interrupt should be compared carefully.

Refer the timing diagram of “Full page write burst stop cycle”.

3. Burst stop is valid at every burst length.

Precharge

(A-Bank)

: Don't care

(December, 2009, Version 1.3) 31

AMIC Technology, Corp.

CAS

ADDR

BA0

BA1

A10/AP

A43L2616B

Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full Page

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

High CKE

CS

RAS

RAa

RAa

CAa CAb t

BDL

* Note 2 t

RDL

WE

DQM

DQ

DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5

Row Active

(A-Bank)

Write

(A-Bank)

Burst Stop

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

* Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. Data-in at the cycle of interrupted by precharge cannot be written into the corresponding memory cell.

It is defined by AC parameter of t

RDL

(=2CLK).

DQM at write interrupted by precharge command is needed to prevent invalid write.

DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.

Input data after Row precharge cycle will be masked internally.

3. Burst stop is valid at every burst length.

(December, 2009, Version 1.3) 32

AMIC Technology, Corp.

A43L2616B

Active/Precharge Power Down Mode @CAS Lantency=2, Burst Length=4

0 1 2 3 4 5 6 7 8 9 10 11 12 13

CLOCK t

SS

~ ~

* Note 2 t

SS

t

SS

~ ~ t

SS

CKE

* Note 1

~ ~

*Note 3

14

CS

~ ~

15

RAS

~ ~ ~ ~

CAS

~ ~ ~ ~

ADDR

Ra Ca

~ ~ ~ ~

16 17 18 19

BA0

~ ~ ~ ~

BA1

~ ~ ~ ~

A10/AP

Ra

~ ~ ~ ~

WE

~ ~ ~ ~

DQM

DQ

~ ~

~ ~

~ ~

~ ~

Qa0 Qa1 Qa2

Precharge

Powerdown

Entry

Precharge

Power-down

Exit

Row Active

Active

Power-down

Entry

Active

Powerdown

Exit

Read

* Note : 1. All banks should be in idle state prior to entering precharge power down mode.

2. CKE should be set high at least “1CLK + t

SS

” prior to Row active command.

3. Cannot violate minimum refresh specification. (64ms)

Precharge

: Don't care

(December, 2009, Version 1.3) 33

AMIC Technology, Corp.

Self Refresh Entry & Exit Cycle

A43L2616B

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

* Note : TO ENTER SELF REFRESH MODE

CAS with CKE should be low at the same clock cycle.

2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.

3. The device remains in self refresh mode as long as CKE stays “Low”.

(cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.

TO EXIT SELF REFRESH MODE

4. System clock restart and be stable before returning CKE high.

6. Minimum tRC is required after CKE going high to complete self refresh exit.

7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit.

If the system uses burst refresh.

(December, 2009, Version 1.3) 34

AMIC Technology, Corp.

RAS

CAS

ADDR

WE

DQM

DQ

Mode Register Set Cycle

0 1 2 3

CLOCK

4 5 6

CKE High

*Note 2

CS

* Note 1

* Note 3

Key Ra

Hi-Z

A43L2616B

Auto Refresh Cycle

0 1 2 3 4 5

High

6

~ ~

~ ~

7 8 9 10 t

RC

~ ~

~ ~

~ ~

~ ~

~ ~

~ ~

Hi-Z

~ ~

~ ~

MRS

Auto Refresh New Command

New

Command

: Don't care

* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

MODE REGISTER SET CYCLE

* Note : 1.

CS, RAS , CAS &

WE activation at the same clock cycle with address key will set internal mode register.

2. Minimum 2 clock cycles should be met before new RAS activation.

3. Please refer to Mode Register Set table.

(December, 2009, Version 1.3) 35

AMIC Technology, Corp.

A43L2616B

Function Truth Table (Table 1)

Current

State

IDLE

Row

Active

Read

Write

Read with

Auto

Precharge

CS RAS CAS

WE

BA Address

H X X X X X NOP

L H H H X X NOP

L H H L X X ILLEGAL

L L L X X X ILLEGAL

Action

L L H H BA RA Row Active; Latch Row Address

L L H L BA PA NOP

L L L H X X Auto Refresh or Self Refresh

L L L L OP Code Mode Register Access

H X X X X X NOP

L H H H X X NOP

L H H L X X ILLEGAL

L

L

H

H

L

L

H BA CA,A10/AP Begin Read; Latch CA; Determine AP

L BA CA,A10/AP Begin Write; Latch CA; Determine AP

L L H H RA ILLEGAL

L L H L BA PA Precharge

L L L X X X ILLEGAL

H X X X X X NOP(Continue Burst to End

Row Active)

L H H H X X NOP(Continue Burst to End

Row Active)

L H H L X X Term burst

Row Active

L H L H BA CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP

L H L L BA CA,AP Term burst; Begin Write; Latch CA; Determine AP

L L H H RA ILLEGAL

L L H L BA PA Term Burst; Precharge timing for Reads

L L L X X X ILLEGAL

H X X X X X NOP(Continue Burst to End

Row Active)

L H H H X X NOP(Continue Burst to End

Row Active)

L H H L X X Term burst

Row Active

L

L

H

H

L

L

H

L

BA

BA

CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP

CA,A10/AP Term burst; Begin Read; Latch CA; Determine AP

L L H H RA ILLEGAL

L L H L BA A10/AP Term Burst; Precharge timing for Writes

L L L X X X ILLEGAL

H X X X X X NOP(Continue Burst to End

Precharge)

L H H H X X NOP(Continue Burst to End

Precharge)

L H H L X X ILLEGAL

Note

3

3

2

3

2

2

2

3

3

2

3

2

2

4

5

5

2

2

(December, 2009, Version 1.3) 36

AMIC Technology, Corp.

A43L2616B

Function Truth Table (Table 1, Continued)

Current

State

CS RAS CAS

WE

BA Address Action Note

Write with

Auto

Precharge

H X X X X

L H H H X

L H H L X

X NOP(Continue Burst to End

X NOP(Continue Burst to End

X ILLEGAL

Precharge)

Precharge)

2

2

L L L X X X ILLEGAL

H X X X X X NOP

Idle after t

RP

L H H H X X NOP

Idle after t

RP

L H H L X X ILLEGAL

2

Precharge

L L H H RA ILLEGAL

L L H L BA A10/PA

Idle after t

RP

L L L X X X ILLEGAL

H X X X X X NOP

Row Active after t

RCD

L H H H X X NOP

Row Active after t

RCD

L H H L X X ILLEGAL

2

2

2

4

Row

Activating 2

Refreshing

L L H H RA ILLEGAL

L L L X X X ILLEGAL

H X X X X X NOP

Idle after t

RC

L H H X X X NOP

Idle after t

RC

L H L X X X ILLEGAL

L L H X X X ILLEGAL

L L L X X X ILLEGAL

H X X X X X

NOP

Idle after 2 clocks

L H H H H X NOP

Idle after 2 clocks

2

2

2

Mode

Register

Accessing

L H H L X X ILLEGAL

L H L X X X ILLEGAL

L L X X X X ILLEGAL

Abbreviations

RA = Row Address BA = Bank Address AP = Auto Precharge

NOP = No Operation Command CA = Column Address PA = Precharge All

Note: 1. All entries assume that CKE was active (High) during the preceding clock cycle and the current clock cycle.

2. Illegal to bank in specified state : Function may be legal in the bank indicated by BA, depending on the state of that bank.

3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and PA).

5. Illegal if any banks is not idle.

(December, 2009, Version 1.3) 37

AMIC Technology, Corp.

A43L2616B

Function Truth Table for CKE (Table 2)

Current

State

Self

Refresh

Both

Bank

Precharge

Power

Down

All

Banks

Idle

CKE n-1

CKE n

CS RAS CAS

WE

Address

H X X X X X X INVALID

L H H X X X X Exit Self Refresh

ABI after t

RC

L H L H H H X Exit Self Refresh

ABI after t

RC

L H L H H L X ILLEGAL

L H L H L X X ILLEGAL

L H L L X X X ILLEGAL

Action Note

H X X X X X X INVALID

L H H X X X X Exit Power Down

ABI

L H L H H H X Exit Power Down

ABI

L H L H H L X ILLEGAL

L H L H L X X ILLEGAL

L H L L X X X ILLEGAL

H L L H H L X ILLEGAL

H L L H L X X ILLEGAL

6

6

7

7

8

8

8

Any State

Other than

Listed

Above

L L X X X X X NOP

H H X X X X X Refer to Operations in Table 1

H

L

L

H

X

X

X

X

X

X

X

X

X

X

Begin Clock Suspend next cycle

Exit Clock Suspend next cycle

9

9

Abbreviations : ABI = All Banks Idle

Note: 6. After CKE’s low to high transition to exit self refresh mode. And a time of t

RC

(min) has to be elapse after CKE’s low to high transition to issue a new command.

7. CKE low to high transition is asynchronous as if restarts internal clock.

A minimum setup time “tSS + one clock” must be satisfied before any command other than exit.

8. Power-down and self refresh can be entered only from the all banks idle state.

9. Must be a legal command.

(December, 2009, Version 1.3) 38

AMIC Technology, Corp.

P

art Numbering Scheme

A43 X XX XX X X X

X

X X

A43L2616B

Package Material

Blank: normal

F: PB free

Temperature

I

Blank

U

:

:

°

:

C

0

°

C

-25

-40

°

C

~

~

~

85

°

70

C

85

°

C

°

C

Speed

95: 105 MHz

75: 133 MHz

7: 143 MHz

6: 166 MHz

55: 183 MHz

5: 200 MHz

Package Type

V: TSOP

G: CSP

Device Version*

Mobile Function*

I/O Width

16: 16 I/O

32: 32 I/O

Device Density

06: 1M

16: 2M

26: 4M

36: 8M

46: 16M

83: 256K

Operating Vcc

L: 3V~3.6V

P: 2.3V~2.7V

E: 1.7V~1.95V

Device Type

A43: AMIC SDRAM

* Optional

(December, 2009, Version 1.3) 39

AMIC Technology, Corp.

Ordering Information

Part No. Cycle Time (ns)

A43L2616BV-6F

A43L2616BV-6UF

A43L2616BV-7F

A43L2616BV-7UF

1. Pb-free for “-F” grade

2. Industrial for “-U” grade

6

7

Clock Frequency (MHz)

166 @ CL = 3

143 @ CL = 3

Access Time

5.0 ns

6.0 ns

A43L2616B

Package

54 Pb-Free TSOP (II)

54 Pb-Free TSOP (II)

54 Pb-Free TSOP (II)

54 Pb-Free TSOP (II)

(December, 2009, Version 1.3) 40

AMIC Technology, Corp.

Package Information

TSOP 54 (Type II) Outline Dimensions

54 28

Detail "A"

R1

R2

1

D

27

L

L

1

Detail "A"

θ

S

-Ce

Seating Plane b

0.1

Symbol

Dimensions in inches

Min Nom

Dimensions in mm

Max Min Nom Max

A

1

0.002

A

2

0.037

0.004

0.039

b 0.012

c 0.005

D 0.875 BSC

0.006

0.041

0.05 - 0.15

1.05

S

E

E

1

e

0.028 REF

0.463 BSC

0.400 BSC

0.031 BSC

22.22 BSC

0.71 REF

11.76 BSC

10.16 BSC

0.80 BSC

L 0.016

L

1

0.020

0.031 REF

0.024

0.80 REF

R

1

0.005

- - 0.12 - -

R

2

0.005

θ

- 0.010

0.12 - 0.25

0° - 8° 0° - 8°

Notes:

1. The maximum value of dimension D includes end flash.

2. Dimension E does not include resin fins.

3. Dimension S includes end flash.

A43L2616B

unit: inches/mm

0.21 REF

0.665 REF

(December, 2009, Version 1.3) 41

AMIC Technology, Corp.

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