V-Tec | C5-AT25/D4 | MAX8520/MAX8521 Smallest TEC Power Drivers for

MAX8520/MAX8521 Smallest TEC Power Drivers for
19-2586; Rev 0; 10/02
m
3mm x 3m
CSP
m
5mm x 5m
QFN
Smallest TEC Power Drivers for
Optical Modules
The MAX8520 is available in a 5mm x 5mm thin QFN
package and its switching frequency is adjustable up to
1MHz through an external resistor. The MAX8521 is also
available in a 5mm x 5mm thin QFN, as well as a spacesaving 3mm x 3mm UCSP™, with a pin-selectable
switching frequency of 500kHz or 1MHz.
Applications
♦ Circuit Footprint of 0.31in2
♦ Low-Profile Design
♦ On-Chip Power MOSFETs
♦ High-Efficiency Switch-Mode Design
♦ Ripple Cancellation for Low Noise
♦ Direct Current Control Prevents TEC Current
Surges
♦ 5% Accurate Adjustable Heating/Cooling Current
Limits
♦ 2% Accurate TEC Voltage Limit
♦ No Dead Zone or Hunting at Low Output Current
♦ ITEC Monitors TEC Current
♦ 1% Accurate Voltage Reference
♦ Switching Frequency Up to 1MHz
♦ Synchronization (MAX8521)
Ordering Information
TEMP RANGE
PIN-PACKAGE
MAX8520ETP
PART
-40°C to +85°C
20 Thin QFN 5mm x 5mm
MAX8521EBX
-40°C to +85°C
36 UCSP 3mm x 3mm
MAX8521ETP
-40°C to +85°C
20 Thin QFN 5mm x 5mm
SFF/SFP Modules
Fiber-Optic Laser Modules
Fiber-Optic Network Equipment
Typical Operating Circuit
ATE
Biotech Lab Equipment
INPUT
3V TO 5.5V
VDD
PVDD
LX1
FREQ
PGND1
SHDN
CS
ON
OFF
TEC CURRENT
MONITOR
CURRENTCONTROL
SIGNAL
ITEC MAX8521
CTLI
COMP
OS1
OS2
LX2
TEC
OUTPUT
ITEC = ± 1.5A
REF
GND
PGND2
Pin Configurations appear at end of data sheet.
ANALOG /DIGITAL
TEMPERATURE CONTROL
UCSP is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
EVALUATION KIT
AVAILABLE
The MAX8520/MAX8521 are designed to drive thermoelectric coolers (TECs) in space-constrained optical
modules. Both devices deliver ±1.5A output current
and control the TEC current to eliminate harmful current
surges. On-chip FETs minimize external components and
high switching frequency reduces the size of external
components.
The MAX8520 and MAX8521 operate from a single supply
and bias the TEC between the outputs of two synchronous buck regulators. This operation allows for temperature control without “dead zones” or other nonlinearities
at low current. This arrangement ensures that the control
system does not hunt when the set point is very close to
the natural operating point, requiring a small amount of
heating or cooling. An analog control signal precisely
sets the TEC current.
Both devices feature accurate, individually adjustable
heating current limit and cooling current limit, along
with maximum TEC voltage limit to improve the reliability
of optical modules. An analog output signal monitors
the TEC current. A unique ripple cancellation scheme
helps reduce noise.
Features
MAX8520/MAX8521
General Description
MAX8520/MAX8521
Smallest TEC Power Drivers for
Optical Modules
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
SHDN, MAXV, MAXIP, MAXIN,
CTLI to GND .........................................................-0.3V to +6V
COMP, FREQ, OS1, OS2, CS, REF,
ITEC to GND...........................................-0.3V to (VDD + 0.3V)
PVDD1, PVDD2 to GND...............................-0.3V to (VDD + 0.3V)
PVDD1, PVDD2 to VDD ...........................................-0.3V to +0.3V
PGND1, PGND2 to GND .......................................-0.3V to +0.3V
COMP, REF, ITEC Short to GND ...................................Indefinite
LX Current (Note 1) ........................................±2.25A LX Current
Continuous Power Dissipation (TA = +70°C)
20-Pin 5mm x 5mm x 0.9mm QFN (derate 20.8mW/°C
above +70°C) (Note 2)...................................................1.67W
3mm x 3mm UCSP (derate 22mW/°C
above +70°C).................................................................1.75W
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering 10s) ..................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Note 1: LX has internal clamp diodes to PGND and PVDD. Applications that forward bias these diodes should take care not to exceed
the IC’s package power dissipation limits.
Note 2: Solder underside metal slug to PC board ground plane.
ELECTRICAL CHARACTERISTICS
(VDD = PVDD1 = PVDD2 = SHDN = 5V, 1MHz mode (Note 3). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF,
TA = 0°C to +85°C, unless otherwise noted. Typical values at TA = +25°C.)
PARAMETER
Input Supply Range
SYMBOL
CONDITIONS
VDD
Reference Load Regulation
VREF
∆VREF
3.0
VDD = 3V to 5.5V, IREF = 150µA
VDD = 3V
NFET On-Resistance
RDS(ON-N)
PFET On-Resistance
RDS(ON-P)
NFET Leakage
ILEAK(N)
PFET Leakage
ILEAK(P)
Shutdown Supply Current
Thermal Shutdown
UVLO Threshold
2
MAX
UNITS
5.5
V
A
1.485
1.5
VMAXI_ = VREF
140
VMAXI_ = VREF/3
40
50
60
VMAXI_ = VREF
143
150
155
VMAXI_ = VREF/3
45
VDD = 3V to 5V, IREF = 10µA to 1mA
VDD = 5V
MAXIP/MAXIN Threshold
Accuracy
No-Load Supply Current
TYP
±1.5
Maximum TEC Current
Reference Voltage
MIN
1.515
V
1.2
5.0
mV
150
160
50
55
VDD = 5V, I = 0.2A
0.09
0.14
VDD = 3V, I = 0.2A
0.11
0.16
VDD = 5V, I = 0.2A
0.14
0.23
VDD = 3V, I = 0.2A
0.17
0.30
VLX = VDD = 5V, TA = +25°C
0.03
4
VLX = VDD = 5V, TA = +85°C
0.3
VLX = 0, TA = +25°C
0.03
VLX = 0, TA = +85°C
0.3
4
VCOMP = VREF =
1.500V, VDD = 5V
500kHz mode
11
14
1MHz mode
16
21
LOAD)
VCOMP = VREF =
1.500V, VDD = 3.3V
500kHz mode
8
11
1MHz mode
11
14
IDD-SD
SHDN = GND, VDD = 5V (Note 4)
2
3
IDD(NO
TSHUTDOWN Hysteresis = 15°C
VUVLO
Ω
Ω
µA
µA
mA
mA
°C
+165
VDD rising
2.50
2.65
2.80
VDD falling
2.40
2.55
2.70
_______________________________________________________________________________________
mV
V
Smallest TEC Power Drivers for
Optical Modules
(VDD = PVDD1 = PVDD2 = SHDN = 5V, 1MHz mode (Note 3). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF,
TA = 0°C to +85°C, unless otherwise noted. Typical values at TA = +25°C.)
PARAMETER
Internal Oscillator Switching
Frequency
SYMBOL
fSW-INT
MIN
TYP
MAX
MAX8521, FREQ= VDD, VDD = 3V to 5V
CONDITIONS
0.8
1
1.2
MAX8521, FREQ= 0, VDD = 3V to 5V
0.4
0.5
0.6
MAX8520, REXT = 60kΩ, VDD = 5V
0.8
1
1.2
MAX8520, REXT = 60kΩ, VDD = 3V
0.76
0.93
1.10
MAX8520, REXT = 150kΩ, VDD = 5V
0.4
0.5
0.6
0.46
0.56
UNITS
MHz
MAX8520, REXT = 150kΩ, VDD = 3V
0.36
External Sync Frequency Range
25% < duty cycle <75% (MAX8521 only)
0.7
1.2
MHz
LX_ Duty Cycle
(Note 5)
0
100
%
0 or VDD
-100
+100
µA
-5
+5
µA
VDD x
0.25
V
OS1, OS2, CS Input Current
IOS1, IOS2,
ICS
SHDN, FREQ Input Current
ISHDN,
IFREQ
0 or VDD, FREQ applicable for the
MAX8521 only
SHDN, FREQ Input Low Voltage
VIL
VDD = 3V to 5.5V, FREQ applicable for the
MAX8521 only
SHDN, FREQ Input High Voltage
VIH
VDD = 3V to 5.5V, FREQ applicable for the
MAX8521 only
VDD x
0.75
VMAXV = VREF x 0.67, VOS1 to VOS2 = ±4V,
VDD = 5V
-2
+2
%
VMAXV = VREF x 0.33, VOS1 to VOS2 = ±2V,
VDD = 3V
-3
+3
%
VMAXV = VMAXI_ = 0.1V or 1.5V
-0.1
+0.1
µA
10.5
V/V
MAXV Threshold Accuracy
MAXV, MAXI_ Input Bias Current
IMAXV-BIAS,
IMAXI_-BIAS
V
CTLI Gain
ACTLI
VCTLI = 0.5V to 2.5V (Note 6)
9.5
CTLI Input Resistance
RCTLI
1MΩ terminated at REF
0.5
1
2.0
MΩ
50
100
160
µS
+10
%
Error-Amp Transconductance
VITEC Accuracy
gm
VOS1 to VCS = ±100mV, VOS1 = VDD/2
-10
10
_______________________________________________________________________________________
3
MAX8520/MAX8521
ELECTRICAL CHARACTERISTICS (continued)
MAX8520/MAX8521
Smallest TEC Power Drivers for
Optical Modules
ELECTRICAL CHARACTERISTICS
(VDD = PVDD1 = PVDD2 = SHDN = 5V, 1MHz mode (Note 2). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF, TA =
-40°C to +85°C, unless otherwise noted.) (Note 7)
PARAMETER
Input Supply Range
SYMBOL
CONDITIONS
VDD
Reference Load Regulation
VREF
∆VREF
VDD = 3V to 5.5V, IREF = 150µA
VDD = 3V
NFET On-Resistance
RDS(ON-N)
PFET On-Resistance
RDS(ON-P)
Shutdown Supply Current
UVLO Threshold
Internal Oscillator Switching
Frequency
UNITS
5.5
V
IDD(NO
LOAD)
IDD-SD
VUVLO
fSW-INT
1.480
VDD = 3V to 5V, IREF = 10µA to 1mA
VDD = 5V
MAXIP/MAXIN Threshold
Accuracy
No-Load Supply Current
MAX
3.0
±1.5
Maximum TEC Current
Reference Voltage
MIN
A
1.515
V
5
mV
VMAXI_ = VREF
140
VMAXI_ = VREF/3
40
160
60
VMAXI_ = VREF
143
155
VMAXI_ = VREF/3
45
55
VDD = 5V, I = 0.2A
0.14
VDD = 3V, I = 0.2A
0.16
VDD = 5V, I = 0.2A
0.23
VDD = 3V, I = 0.2A
0.30
500kHz mode
1MHz mode
14
21
500kHz mode
1MHz mode
SHDN = GND, VDD = 5V (Note 4)
11
14
3
VCOMP = VREF =
1.500V, VDD = 5V
VCOMP = VREF =
1.500V, VDD = 3.3V
mV
VDD rising
2.50
2.80
VDD falling
2.40
2.70
MAX8521, FREQ = VDD, VDD = 3V to 5V
0.8
1.2
MAX8521, FREQ = 0, VDD = 3V to 5V
0.4
0.6
MAX8520, REXT = 60kΩ, VDD = 5V
0.8
1.2
MAX8520, REXT = 60kΩ, VDD = 3V
0.76
1.10
Ω
Ω
mA
mA
V
MHz
MAX8520, REXT = 150kΩ, VDD = 5V
0.4
0.6
MAX8520, REXT = 150kΩ, VDD = 3V
0.36
0.56
External Sync Frequency Range
25% < duty cycle <75% (MAX8521 only)
0.7
1.2
MHz
LX_ Duty Cycle
(Note 5)
0
100
%
-100
+100
µA
-5
+5
µA
VDD x
0.25
V
OS1, OS2, CS Input Current
SHDN, FREQ Input Current
IOS1, IOS2,
0 or VDD
ICS
ISHDN,
IFREQ
0 or VDD, FREQ applicable for the MAX8521
only
SHDN, FREQ Input Low Voltage
VIL
VDD = 3V to 5.5V, FREQ applicable for the
MAX8521 only
SHDN, FREQ Input High Voltage
VIH
VDD = 3V to 5.5V, FREQ applicable for the
MAX8521 only
4
VDD x
0.75
_______________________________________________________________________________________
V
Smallest TEC Power Drivers for
Optical Modules
(VDD = PVDD1 = PVDD2 = SHDN = 5V, 1MHz mode (Note 2). PGND1 = PGND2 = GND, CTLI = MAXV = MAXIP = MAXIN = REF, TA =
-40°C to +85°C, unless otherwise noted.) (Note 7)
PARAMETER
SYMBOL
MAXV Threshold Accuracy
IMAXVBIAS,
MAXV, MAXI_ Input Bias Current
CONDITIONS
MIN
MAX
UNITS
VMAXV = VREF x 0.67, VOS1 to VOS2 = ±4V,
VDD = 5V
-2
+2
%
VMAXV = VREF x 0.33, VOS1 to VOS2 = ±2V,
VDD = 3V
-3
+3
%
-0.1
+0.1
µA
VMAXV = VMAXI_ = 0.1V or 1.5V
IMAXI_-BIAS
CTLI Gain
ACTLI
VCTLI = 0.5V to 2.5V (Note 6)
9.5
10.5
V/V
CTLI Input Resistance
RCTLI
1MΩ terminated at REF
0.5
2.0
MΩ
50
160
µS
VOS1 to VCS = ±100mV, VOS1 = VDD/2
-10
+10
%
Error-Amp Transconductance
gm
VITEC Accuracy
Note 3:
Note 4:
Note 5:
Note 6:
Enter 1MHz mode by tying a 60kΩ resistor from FREQ to ground for the MAX8520, and tying FREQ to VDD for the MAX8521.
Includes PFET leakage.
Duty-cycle specification is guaranteed by design and not production tested.
CTLI Gain is defined as:
ACTLI =
∆VCTLI
∆( VOS1 − VCS )
Note 7: Specifications to -40°C are guaranteed by design and not production tested.
Typical Operating Characteristics
(VDD = 5V, circuit of Figure 1, TA = +25°C, unless otherwise noted)
EFFICIENCY vs. TEC CURRENT
(VDD = 3.3V, RTEC = 1.3Ω)
EFFICIENCY vs. TEC CURRENT
(VDD = 5V, RTEC = 2Ω)
70
EFFICIENCY (%)
EFFICIENCY (%)
FREQ = 1MHz
80
60
50
40
60
20
20
10
10
0
0
0.4
0.6
0.8
1.0
TEC CURENT (A)
1.2
1.4
1.6
VOS2
20mV/div
AC-COUPLED
FREQ = 1MHz
40
30
0.2
C2 = C7 = 1µF
50
30
0
FREQ = 500kHz
70
MAX8520/21 toc03
MAX8520/21 toc02
FREQ = 500kHz
80
90
MAX8520/21 toc01
90
COMMON-MODE
OUTPUT VOLTAGE RIPPLE
VOS1
20mV/div
AC-COUPLED
ITEC = 1A
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
400ns/div
TEC CURRENT (A)
_______________________________________________________________________________________
5
MAX8520/MAX8521
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(VDD = 5V, circuit of Figure 1, TA = +25°C, unless otherwise noted)
DIFFERENTIAL
OUTPUT VOLTAGE RIPPLE
TEC CURRENT RIPPLE
VDD RIPPLE
MAX8520/21 toc06
MAX8520/21 toc05
MAX8520/21 toc04
C2 = C7 = 1µF
1.5A
VOS2 - VOS1
1mV/div
AC-COUPLED
VDD
20mV/div
AC-COUPLED
ITEC = 1A
ITEC = 1A
10mA/div
AC-COUPLED
0A
400ns/div
400ns/div
400ns/div
ZERO-CROSSING TEC CURRENT
MAX8520/21 toc07
VITEC vs. TEC CURRENT
MAX8520/21 toc08
VCTLI
1V/div
3.0
2.5
VCTLI
I00mV/div
0V
MAX8520/21 toc09
TEC CURRENT vs. CTLI VOLTAGE
2.0
VITEC (V)
1.5V
1.5
0A
1.0
0A
ITEC
1A/div
0.5
ITEC
100mA/div
0
20ms/div
-2.0 -1.5 -1.0 -0.5
1ms/div
0
0.5
1.0
TEC CURRENT (A)
SWITCHING FREQUENCY
vs. TEMPERATURE
ITEC vs. AMBIENT TEMPERATURE
0.500
0.490
0.480
0.470
FREQ = 1MHz
VCTLI = 2V
RTEC = 1Ω
0.460
FREQ = 1MHz
1000
VCTLI = 1.5V
RTEC = 1Ω
900
800
700
600
FREQ = 500kHz
500
400
0.450
-40
-20
0
20
40
60
AMBIENT TEMPERATURE (°C)
6
MAX8520/21 toc11
0.510
1100
SWITCHING FREQUENCY (kHz)
MAX8520/21 toc10
0.520
TEC CURRENT (A)
MAX8520/MAX8521
Smallest TEC Power Drivers for
Optical Modules
80
-40
-20
0
20
40
60
TEMPERATURE (°C)
_______________________________________________________________________________________
80
1.5
2.0
Smallest TEC Power Drivers for
Optical Modules
SWITCHING FREQUENCY vs. REXT
800
600
FREQ = 500kHz
400
VDD = 5V
700
400
4.5
5.0
MAX8520/21 toc14
REF SOURCING 150µA
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
-1.4
60
5.5
0.6
80
100
120
140
160
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
REXT (kΩ)
VDD (V)
REFERENCE VOLTAGE CHANGE
vs. TEMPERATURE
REFERENCE VOLTAGE CHANGE
vs. LOAD CURRENT
STARTUP AND SHUTDOWN WAVEFORMS
2
1
0
-1
-2
-3
MAX8520/21 toc16
REF SOURCING 150µA
3
MAX8520/21 toc17
0
REFERENCE VOLTAGE CHANGE (mV)
MAX8520/21 toc15
5
4
VDD = 3.3V
600
0
4.0
MAX8520/21 toc13
800
500
3.5
REFERENCE VOLTAGE CHANGE vs. VDD
900
200
3.0
REFERENCE VOLTAGE CHANGE (mV)
1000
SWITCHING FREQUENCY (kHz)
MAX8520/21 toc12
SWITCHING FREQUENCY CHANGE (kHz)
FREQ = 1MHz
1000
1100
REFERENCE VOLTAGE CHANGE (mV)
SWITCHING FREQUENCY CHANGE vs. VDD
1200
-2
VSHDN
5V/div
0V
-4
IDD
200mA/div
0mA
-6
-8
ITEC
500mA/div
0mA
-10
-4
-12
-5
-40
-20
0
20
40
60
0
80
0.2
0.4
0.6
0.8
1.0
200µs/div
LOAD CURRENT (mA)
TEMPERATURE (°C)
CTLI STEP RESPONSE
VDD STEP RESPONSE
MAX8520/21 toc18
MAX8520/21 toc19
VCTLI
1V/div
VDD
2V/div
1.5V
0V
1A
ITEC
10mA/div
0A
ITEC
1A/div
1ms
MAX8520/MAX8521
Typical Operating Characteristics (continued)
(VDD = 5V, circuit of Figure 1, TA = +25°C unless otherwise noted)
10ms/div
_______________________________________________________________________________________
7
MAX8520/MAX8521
Smallest TEC Power Drivers for
Optical Modules
Typical Operating Characteristics (continued)
(VDD = 5V, circuit of Figure 1, TA = +25°C unless otherwise noted)
THERMAL STABILITY,
COOLING MODE
THERMAL STABILITY,
ROOM TEMPERATURE
MAX8520/21 toc20
THERMAL STABILITY,
HEATING MODE
MAX8520/21 toc21
TEMPERATURE
0.001°C/div
TTEC = +25°C
TA = +45°C
MAX8520/21 toc22
TEMPERATURE
0.001°C/div
TTEC = +25°C
TA = +25°C
4s/div
TEMPERATURE
0.001°C/div
TTEC = +25°C
TA = +5°C
4s/div
4s/div
Pin Description
PIN
8
NAME
FUNCTION
QFN
UCSP
1
E1, E2
LX1
2
D1, D2, D3
PGND1
3
C1
SHDN
Shutdown Control Input. Pull SHDN low to turn off PWM control and ITEC output.
4
C2
COMP
Current-Control Loop Compensation. Refer to the Compensation Capacitor section.
5
B1
ITEC
Inductor Connection. LX1 is high-impedance in shutdown.
Power Ground 1. Internal synchronous-rectifier ground connection. Connect all PGND
pins together at power ground plane.
TEC Current-Monitor Output. The ITEC output voltage is a function of the voltage across
the TEC current-sense resistor. VITEC = VREF + 8 (VOS - VCS). Keep capacitance on ITEC
<150pF.
6
A1
MAXIN
Maximum Negative TEC Current. Connect MAXIN to REF to set default negative current
limit to -150mV/RSENSE. To lower this current limit, connect MAXIN to a resistor divider
network from REF to GND. The current limit will then be equal to -(VMAXIN/VREF) x
(150mV/RSENSE).
7
A2
MAXIP
Maximum Positive TEC Current. Connect MAXIP to REF to set default positive current limit
to 150mV/RSENSE. To lower this current limit, connect MAXIP to a resistor divider network
from REF to GND. The current limit will then be equal to (VMAXIP/VREF) x (150mV/RSENSE).
8
A3
MAXV
Maximum Bipolar TEC Voltage. Connect MAXV to REF to set default maximum TEC
voltage to VDD. To lower this limit, connect MAXV to a resistor-divider network from REF to
GND. The maximum TEC voltage is equal to 4 x VMAXV or VDD, whichever is lower.
9
A4
REF
1.50V Reference Output. Bypass REF to GND with a 0. 1µF ceramic capacitor.
_______________________________________________________________________________________
Smallest TEC Power Drivers for
Optical Modules
PIN
QFN
UCSP
NAME
FUNCTION
TEC Current-Control Input. Sets TEC current. Center point is 1.50V (no TEC current). The
current is given by:
ITEC = (VOS1 - VCS) / RSENSE = (VCTLI - 1.50) / (10 x RSENSE). When (VCTLI - VREF) > 0,
then VOS2 > VOS1 > VCS.
10
A5
CTLI
11
A6
GND
Analog Ground. Start connect to PGND at underside exposed pad for QFN package.
12
B6
VDD
Analog Supply Voltage Input. Bypass VDD to GND with a 1µF ceramic capacitor.
For MAX8520: Analog FREQ Set Pin (see the Switching Frequency section).
13
C5
FREQ
14
D4, D5, D6
PGND2
15
E5, E6
LX2
16
F5, F6
PVDD2
For MAX8521: Digital FREQ Selection Pin. Tie to VDD for 1MHz operation, tie to GND for
500kHz operation. The PWM oscillator can synchronize to FREQ by switching at FREQ
between 700kHz and 1.2MHz.
Power Ground 2. Internal synchronous rectifier ground connection. Connect all PGND
pins together at the power ground plane.
Inductor Connection. LX2 is high impedance in shutdown.
Power Input 2. Connect all PVDD inputs together at the VDD power plane.
Current-Sense Input. The current through the TEC is monitored between CS and OS1. The
maximum TEC current is given by 150mV/RSENSE and is bipolar.
17
F4
CS
18
C6
OS2
Output Sense 2. OS2 senses one side of the differential TEC voltage. OS2 is a sense
point, not a power output. OS2 discharges to ground in shutdown.
19
F3
OS1
Output Sense 1. OS1 senses one side of the differential TEC voltage. OS1 is a sense
point, not a power output. OS1 discharges to ground in shutdown.
F1, F2
20
PVDD1
Power Input 1. Connect all PVDD inputs together at the VDD power plane.
B2, B5,
C3, C4
GND2
Ground. Additional ground pads aid in heat dissipation. Short to either GND or PGND
plane.
B3, B4
E3, E4
N.C.
No Connect. Connect no-connect pads to GND2 to aid in heat dissipation.
_______________________________________________________________________________________
9
MAX8520/MAX8521
Pin Description (continued)
MAX8520/MAX8521
Smallest TEC Power Drivers for
Optical Modules
Detailed Description
The MAX8520/MAX8521 TEC drivers consist of two
switching buck regulators that operate together to directly
control the TEC current. This configuration creates a
differential voltage across the TEC, allowing bidirectional
TEC current for controlled cooling and heating. Controlled
cooling and heating allow accurate TEC temperature control to within ±0.01°C. The voltage at CTLI directly sets
the TEC current. An external thermal- control loop is typically used to drive CTLI. Figures 1 and 2 show examples
of the thermal control-loop circuit.
Ripple Cancellation
Switching regulators like those used in the MAX8520/
MAX8521 inherently create ripple voltage on the output.
The dual regulators in the MAX8520/MAX8521 switch in
phase and provide complementary in-phase duty
cycles so ripple waveforms at the TEC are greatly
reduced. This feature suppresses ripple currents and
electrical noise at the TEC to prevent interference with
the laser diode.
Switching Frequency
For the MAX8521, FREQ sets the switching frequency of
the internal oscillator. With FREQ = GND, the oscillator
frequency is set to 500kHz. The oscillator frequency is
1MHz when FREQ = VDD.
For the MAX8520, connect a resistor (REXT in Figure 2)
from FREQ to GND. Choose REXT = 60kΩ for 1MHz
operation, and REXT = 150kΩ for 500kHz operation. For
any intermediary frequency between 500kHz and
1MHz, use the following equation to find the value of
REXT value needed for VDD = 5V:
 1 1
REXT = 90 ×  − 
 fs 3 
where REXT is the resistance given in kΩ, and fs is the
desired frequency given in MHz. Note that for VDD <
5V, the frequency is reduced slightly, to the extent of
about 7% when VDD reaches 3V. This should be taken
into consideration when selecting the value for REXT at
a known supply voltage.
Voltage and Current-Limit Setting
Both the MAX8520 and MAX8521 provide control of the
maximum differential TEC voltage. Applying a voltage
to MAXV limits the maximum voltage across the TEC.
The voltage at MAXIP and MAXIN sets the maximum
positive and negative current through the TEC. These
current limits can be independently controlled.
10
Table 1. TEC Connection for Figure 1
TEC CONNECTION
THERMISTOR
Heating mode
PTC
Cooling mode
NTC
Table 2. TEC Connection for Figure 2
TEC CONNECTION
THERMISTOR
Heating mode
NTC
Cooling mode
PTC
Current Monitor Output
ITEC provides a voltage output proportional to the TEC
current (ITEC). See the Functional Diagram for more
details:
VITEC = 1.5V +(8 ✕ (VOS1-VCS))
Reference Output
The MAX8520/MAX8521 include an on-chip voltage reference. The 1.50V reference is accurate to 1% over
temperature. Bypass REF with 0.1µF to GND. REF can
be used to bias an external thermistor for temperature
sensing as shown in Figures 1 and 2.
Thermal and Fault-Current Protection
The MAX8520/MAX8521 provide fault-current protection
in either FET by turning off both high-side and low-side
FETs when the peak current exceeds 3A in either FET. In
addition, thermal-overload protection limits the total
power dissipation in the chip. When the device’s die junction temperature exceeds +165°C, an on-chip thermal
sensor shuts down the device. The thermal sensor turns
the device on again after the junction temperature cools
down by 15°C.
Design Procedures
Duty-Cycle Range Selection
By design, the MAX8520/MAX8521 are capable of operating from 0% to 100% duty cycle, allowing both LX outputs to enter dropout. However, as the LX pulse width
narrows, accurate duty-cycle control becomes difficult.
This can result in a low-frequency noise appearing at the
TEC output (typically in the 20kHz to 50kHz range). While
this noise is typically filtered out by the low thermal-loop
bandwidth, for best results, operate the PWM with a pulse
width greater than 200ns. For a 500kHz application, the
recommended duty-cycle range is from 10% to 90%. For
a 1MHz application, it is from 20% to 80%.
______________________________________________________________________________________
Smallest TEC Power Drivers for
Optical Modules
MAX8520/MAX8521
VDD
L1
4.7µF
LX1
VDD
C1
1µF
REF
C2
1µF
CS
RSENSE
0.09Ω
PVDD1
R2
OS1
C3
1µF
RTHER
PGND1
C5
10µF
U1
PVDD2
MAX8521
C4
1µF
OS2
PGND2
L2
4.7µF
REF
LX2
C6
0.1µF
COMP
C8
0.1µF
C7
1µF
VDD
MAXIP
FREQ
MAXIN
49.9kΩ
ITEC
ON
MAXV
100kΩ
SHDN
CTLI
OFF
GND
0.022µF
1µF
10kΩ
243kΩ
10µF
U3A
U2
TO
U3B
OUTPUT
MAX4475
REF
DAC
INPUTS
MAX4477
510kΩ
VDD
10kΩ
100kΩ
U4
MAX5144
U3B
MAX4477
Figure 1. MAX8521 Typical Application Circuit
______________________________________________________________________________________
11
MAX8520/MAX8521
Smallest TEC Power Drivers for
Optical Modules
VDD
L1
4.7µF
LX1
VDD
C1
1µF
REF
C2
1µF
CS
RSENSE
0.09Ω
PVDD1
R2
OS1
C3
1µF
RTHER
PGND1
C5
10µF
U1
PVDD2
C4
1µF
MAX8520
OS2
PGND2
L2
4.7µF
REF
LX2
C6
0.1µF
COMP
C7
1µF
C8
0.1µF
MAXIP
FREQ
MAXIN
49.9kΩ
REXT
60kΩ
ITEC
MAXV
100kΩ
ON
SHDN
CTLI
OFF
GND
0.022µF
1kΩ
243kΩ
10µF
10µF
U2
50kΩ
MAX4238
0.01µF
DAC
INPUTS
VDD
REF
U4
MAX5144
Figure 2. Typical Application Circuit for the MAX8520 with Reduced Op-Amp Count Configuration
12
______________________________________________________________________________________
Smallest TEC Power Drivers for
Optical Modules
MAX8520/MAX8521
3/4 VDD
1/4 VDD
LX2
-1.2
REF
COMP
PWM
4X
1.2X
gm
CTLI
RSENSE
CCOMP
1
LX1
R
R
+1.2
0.5X
REF
CS
10X
OS1
Figure 3. Functional Diagram of the Current-Control Loop
Inductor Selection
The MAX8520/MAX8521 dual buck converters operate
in phase and in complementary mode to drive the TEC
differentially in a current-mode control scheme. At zero
TEC current, the differential voltage is zero; hence, the
outputs with respect to GND are equal to half of VDD.
As the TEC current demand increases, one output goes
up and the other goes down from the initial point of
0.5VDD by an amount equal to 0.5 ✕ VTEC (VTEC = ITEC
✕ RTEC). Therefore, the operating duty cycle of each
buck converter depends on the operating I TEC and
RTEC. Since inductor current calculations for heating
and cooling are identical, but reverse in polarity, the
calculations only need to be carried out for either one.
For a given inductor and input voltage, the maximum
inductor ripple current happens when the duty cycle is
at 50%. Therefore, the inductor should be calculated at
50% duty cycle to find the maximum ripple current. The
maximum desired ripple current of a typical standard
buck converter is in the range of 20% to 40% of the
maximum load. The higher the value of the inductor, the
lower the ripple current. However, the size is physically
larger. For the TEC driver, the thermal loop is inherently
slow, so the inductor can be larger for lower ripple
current for better noise and EMI performance. Picking
an inductor to yield ripple current of 10% to 20% of the
maximum TEC current is a good starting point.
Calculate the inductor value as follows:
L=
(0.25
× VDD )
LIR × I TEC(MAX) × fs
where LIR is the selected inductor ripple-current ratio,
ITEC(MAX) is the maximum TEC current, and fs is the
switching frequency.
As an example, for VDD = 3.3V, LIR = 12%, and fs =
1MHz, L = 4.58µH.
Even though each inductor ripple current is at its maximum at 50% duty cycle (zero TEC current), the ripple
cancels differentially because each is equal and in
phase.
Output Filter Capacitor
Selection
Common-Mode Filter Capacitors
The common-mode filter capacitors (C2 and C7 of Figure
1) are used as filter capacitors to ground for each output.
The output ripple voltage depends on the capacitance,
the ESR of these capacitors, and the inductor ripple
current. Ceramic capacitors are recommended for their
low ESR and impedance at high frequency.
______________________________________________________________________________________
13
MAX8520/MAX8521
Smallest TEC Power Drivers for
Optical Modules
The output common-mode ripple voltage can be calculated as follows:
bypassing may be needed to stabilize the input supply.
In such cases, a low-ESR electrolytic or ceramic capacitor of 100µF or more at VDD is sufficient.
VRIPPLE(P-P) = LIR x ITEC(MAX) (ESR + 1/8 x C x fs)
A 1µF ceramic capacitor with ESR of 10mΩ with LIR =
12% and ITEC(MAX) = 1.5A results in VRIPPLE(P-P) of
24.3mV. For size-constraint applications, the capacitor
can be made smaller at the expense of higher ripple
voltage. However, the capacitance must be high
enough so that the LC resonant frequency is less than
1/5 the switching frequency:
f=
1
2π LC
where f is the resonant frequency of the output filter.
Differential Mode Filter Capacitor
The differential-mode filter capacitor (C5 in Figure 1) is
used to bypass differential ripple current through the
TEC as the result of unequal duty cycle of each output.
This happens when the TEC current is not at zero. As
TEC current increases from zero, both outputs move
away from the 50% duty-cycle point complementarily.
The common-mode ripple decreases, but the differential
ripple does not cancel perfectly, and there is a resulting
differential ripple. The maximum value happens when
one output is at 75% duty cycle and the other is at 25%
duty cycle. At this operating point, the differential ripple
is equal to 1/2 of the maximum common-mode ripple.
The TEC ripple current determines the TEC performance, because the maximum temperature differential
that can be created between the terminals of the TEC
depends on the ratio of ripple current and DC current.
The lower the ripple current, the closer to the ideal
maximum. The differential-mode capacitor provides a
low-impedance path for the ripple current to flow, so that
the TEC ripple current is greatly reduced. The TEC ripple
current can then be calculated as follows:
ITEC(RIPPLE) = (0.5 x LIR x ITEC(MAX)) x (ZC5)/(RTEC
+ RSENSE + ZC5)
where ZC5 is the impedance of C5 at twice the switching
frequency, RTEC is the TEC equivalent resistance, and
RSENSE is the current-sense resistor.
Decoupling Capacitor Selection
Decouple each power-supply input (V DD , PV DD 1,
PVDD2) with a 1µF ceramic capacitor close to the supply
pins. In applications with long distances between the
source supply and the MAX8520/MAX8521, additional
14
Compensation Capacitor
A compensation capacitor is needed to ensure currentcontrol-loop stability (see Figure 3). Select the capacitor
so that the unity-gain bandwidth of the current-control
loop is less than or equal to 10% the resonant frequency
of the output filter:
g  

24 × RSENSE
CCOMP ≥  m  × 

 fBW   2π(RSENSE × RTEC ) 
where:
fBW = unity-gain bandwidth frequency, less than or
equal to 10% the output filter resonant frequency
gm = loop transconductance, typically 100µA/V
CCOMP = value of the compensation capacitor
RTEC = TEC series resistance; use the minimum resistance value
RSENSE = sense resistor
Setting Voltage and Current Limits
Certain TEC parameters must be considered to guarantee
a robust design. These include maximum positive current,
maximum negative current, and the maximum voltage
allowed across the TEC. These limits should be used to
set the MAXIP, MAXIN, and MAXV voltages.
Setting Max Positive and Negative TEC Current
MAXIP and MAXIN set the maximum positive and negative TEC currents, respectively. The default current limit
is ±150mV/RSENSE when MAXIP and MAXIN are connected to REF. To set maximum limits other than the
defaults, connect a resistor-divider from REF to GND to
set VMAXI_. Use resistors in the 10kΩ to 100kΩ range.
VMAXI_ is related to ITEC by the following equations:
VMAXIP = 10(ITECP(MAX) ✕ RSENSE)
VMAXIN = 10(ITECN(MAX) ✕ RSENSE)
where ITECP(MAX) is the maximum positive TEC current
and ITECN(MAX) is the negative maximum TEC current.
Positive TEC current occurs when CS is less than OS1:
ITEC x RSENSE = OS1 - CS
when ITEC > 0.
ITEC ✕ RSENSE = CS - OS1
when ITEC < 0.
______________________________________________________________________________________
Smallest TEC Power Drivers for
Optical Modules
Setting Max TEC Voltage
Apply a voltage to the MAXV pin to control the maximum
differential TEC voltage. MAXV can vary from 0 to REF.
The voltage across the TEC is four times VMAXV and
can be positive or negative:
|VOS1 - VOS2| = 4 x VMAXV or VDD, whichever is lower
Set VMAXV with a resistor-divider between REF and
GND using resistors from 10kΩ to 100kΩ. VMAXV can
vary from 0 to REF.
Control Inputs/Outputs
Output Current Control
The voltage at CTLI directly sets the TEC current. CTLI
is typically driven from the output of a temperature control loop. The transfer function relating current through
the TEC (ITEC) and VCTLI is given by:
ITEC = (VCTLI - VREF) / (10 ✕ RSENSE)
where VREF is 1.50V and:
ITEC = (VOS1 - VCS) / RSENSE
CTLI is centered around REF (1.50V). ITEC is zero when
CTLI = 1.50V. When VCTLI > 1.50V, the current flow is
from OS2 to OS1. The voltages on the pins relate as
follows:
VOS2 > VOS1 > VCS
The opposite applies when VCTLI < 1.50V current flows
from OS1 to OS2:
VOS2 < VOS1 < VCS
Shutdown Control
The MAX8520/MAX8521 can be placed in a power-saving
shutdown mode by driving SHDN low. When the
MAX8520/MAX8521 are shut down, the TEC is off (OS1
and OS2 decay to GND) and supply current is reduced to
2mA (typ).
ITEC Output
ITEC is a status output that provides a voltage proportional
to the actual TEC current. VITEC = REF when TEC current
is zero. The transfer function for the ITEC output is:
VITEC = 1.50 + 8 ✕ (VOS1 – VCS)
Use ITEC to monitor the cooling or heating current
through the TEC. For stability, keep the load capacitance on ITEC to less than 150pF.
Applications Information
The MAX8520/MAX8521 typically drive a TEC inside a
thermal-control loop. TEC drive polarity and power are
regulated based on temperature information read from a
thermistor or other temperature-measuring device to
maintain a stable control temperature. Temperature stability of ±0.01°C can be achieved with carefully selected
external components.
There are numerous ways to implement the thermal loop.
Figures 1 and 2 show designs that employ precision op
amps, along with a DAC or potentiometer to set the control temperature. The loop may also be implemented digitally, using a precision A/D to read the thermistor or
other temperature sensor, a microcontroller to implement
the control algorithm, and a DAC (or filtered-PWM signal)
to send the appropriate signal to the MAX8520/MAX8521
CTLI input. Regardless of the form taken by the thermalcontrol circuitry, all designs are similar in that they read
temperature, compare it to a set-point signal, and then
send an error-correcting signal to the MAX8520/
MAX8521 that moves the temperature in the appropriate
direction.
PC Board Layout and Routing
High switching frequencies and large peak currents
make PC board layout a very important part of design.
Good design minimizes excessive EMI and voltage
gradients in the ground plane, both of which can result
in instability or regulation errors. Follow these guidelines for good PC board layout:
1) Place decoupling capacitors as close to the IC pins
as possible.
2) Keep a separate power ground plane, which is connected to PGND1 and PGND2. PV DD 1, PV DD 2,
PGND1, and PGND2 are noisy points. Connect
decoupling capacitors from PVDDs to PGNDs as
directly as possible. Output capacitors C2 and C7
returns are connected to PGND plane.
3) Connect a decoupling capacitor from VDD to GND.
Connect GND to a signal ground plane (separate
from the power ground plane above). Other VDD
decoupling capacitors (such as the input capacitor)
need to be connected to the PGND plane.
4) Connect GND and PGND_ pins together at a single
point, as close as possible to the chip.
5) Keep the power loop, which consists of input
capacitors, output inductors, and capacitors, as
compact and small as possible.
______________________________________________________________________________________
15
MAX8520/MAX8521
Take care not to exceed the positive or negative current limit on the TEC. Refer to the manufacturer’s data
sheet for these limits.
6) To ensure high DC loop gain and minimum loop
error, keep the board layout adjacent to the negative
input pin of the integrator (U2 in Figure1) clean and
free of moisture. Any contamination or leakage
current into this node can act to lower the DC gain of
the integrator, which can degrade the accuracy of
the thermal loop. If space is available, it can also be
helpful to surround the negative input node of the
integrator with a grounded guard ring.
Refer to the MAX8520/MAX8521 evaluation kit for a PC
board layout example.
Chip Information
TRANSISTOR COUNT: 3007
PROCESS: BiCMOS
MAX8521
LX1
1
15
LX2
PGND1
2
14
PGND2
SHDN
3
13
FREQ
COMP
4
12
VDD
ITEC
5
11
GND
F5
F6
PVDD2 PVDD2
E6
LX2
E5
LX2
F4
CS
F3
OS1
E4
N.C.
E3
N.C.
F2
F1
PVDD1 PVDD1
E2
LX1
E1
LX1
D6
D5
D4
D3
D2
D1
PGND2 PGND2 PGND2 PGND1 PGND1 PGND1
B2
GND2
A5
CTLI
A4
REF
A3
MAXV
10
B3
N.C.
CTLI
B4
N.C.
9
B5
GND2
B6
VDD
REF
C2
C1
COMP SHDN
8
C3
GND2
7
C4
GND2
MAXV
C5
FREQ
MAXIP
C6
OS2
6
MAX8520/
MAX8521
A6
GND
THIN QFN
16
16 PVDD2
17 CS
18 OS2
TOP VIEW
19 OS1
20 PVDD1
Pin Configurations
MAXIN
MAX8520/MAX8521
Smallest TEC Power Drivers for
Optical Modules
B1
ITEC
A2
A1
MAXIP MAXIN
UCSP
______________________________________________________________________________________
Smallest TEC Power Drivers for
Optical Modules
ON
OFF
SHDN
REF
FREQ (MAX8521)
REF
3V TO
5.5V
VDD
PVDD1
MAXV
MAX VTEC =
VMAXV × 4
OR VDD
LX1
MAXIP
MAXIN
MAX ITEC =
(VMAXIP/VREF) ×
(0.15V/RSENSE)
PWM CONTROL
AND
GATE CONTROL
MAX ITEC =
(VMAXIN/VREF) ×
(0.15V/RSENSE)
PGND1
CS
RSENSE
OS1
CS
OS2
ITEC
OS1
PVDD2
VDD
REF
CTLI
LX2
COMP
GND
FREQ
(MAX8520)
MAX8520/
MAX8521
PGND2
______________________________________________________________________________________
17
MAX8520/MAX8521
Functional Diagram
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
0.15 C A
D
b
CL
0.10 M C A B
D2/2
D/2
PIN # 1
I.D.
QFN THIN.EPS
MAX8520/MAX8521
Smallest TEC Power Drivers for
Optical Modules
k
0.15 C B
PIN # 1 I.D.
0.35x45
E/2
E2/2
CL
(NE-1) X e
E
E2
k
L
DETAIL A
e
(ND-1) X e
CL
CL
L
L
e
e
0.10 C
A
C
0.08 C
A1 A3
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
COMMON DIMENSIONS
DOCUMENT CONTROL NO.
REV.
21-0140
C
1
2
EXPOSED PAD VARIATIONS
NOTES:
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1
SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE
ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm
FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
16, 20, 28, 32L, QFN THIN, 5x5x0.8 mm
APPROVAL
18
DOCUMENT CONTROL NO.
REV.
21-0140
C
2
2
______________________________________________________________________________________
Smallest TEC Power Drivers for
Optical Modules
36L,UCSP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX8520/MAX8521
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising