datasheet for KMPC8555EVTAPF by Freescale

Freescale Semiconductor

Technical Data

MPC8555EEC

Rev. 4.2, 1/2008

MPC8555E PowerQUICC™ III

Integrated Communications Processor

Hardware Specification

The MPC8555E integrates a PowerPC™ processor core built on Power Architecture™ technology with system logic required for networking, telecommunications, and wireless infrastructure applications. The MPC8555E is a member of the PowerQUICC™ III family of devices that combine system-level support for industry-standard interfaces with processors that implement the embedded category of the

Power Architecture technology. For functional characteristics of the processor, refer to the MPC8555E

PowerQUICC™ III Integrated Communications Processor

Reference Manual.

To locate any published errata or updates for this document refer to http://www.freescale.com or contact your Freescale sales office.

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 8

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13

4. Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6. DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8. Ethernet: Three-Speed, MII Management . . . . . . . . . . 22

9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10. CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

11. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

12. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

13. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

14. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . . . 56

15. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

16. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

17. System Design Information . . . . . . . . . . . . . . . . . . . . . 78

18. Document Revision History . . . . . . . . . . . . . . . . . . . . 85

19. Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . 86

© Freescale Semiconductor, Inc., 2008. All rights reserved.

2

Overview

1 Overview

The following section provides a high-level overview of the MPC8555E features. Figure 1 shows the

major functional units within the MPC8555E.

DDR

SDRAM

DDR SDRAM Controller

I

2

C Controller

Security

Engine

256-Kbyte

L2 Cache/

SRAM

GPIO

32b

DUART e500

Coherency

Module

Core Complex

Bus e500 Core

32-Kbyte L1

I Cache

32-Kbyte L1

D Cache

IRQs

MPHY

UTOPIA

MIIs/RMIIs

TDMs

I/Os

Local Bus Controller

Programmable

Interrupt Controller

CPM

Serial

DMA

FCC

FCC

SCC

SCC/USB

SCC

SMC

SMC

SPI

I

2

C

ROM

I-Memory

DPRAM

RISC

Engine

Parallel I/O

Baud Rate

Generators

Timers

CPM

Interrupt

Controller

OCeaN

64/32b PCI Controller

0/32b PCI Controller

DMA Controller

10/100/1000 MAC

10/100/1000 MAC

MII, GMII, TBI,

RTBI, RGMIIs

Figure 1. MPC8555E Block Diagram

1.1

Key Features

The following lists an overview of the MPC8555E feature set.

• Embedded e500 Book E-compatible core

— High-performance, 32-bit Book E-enhanced core that implements the PowerPC architecture

— Dual-issue superscalar, 7-stage pipeline design

— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection

— Lockable L1 caches—entire cache or on a per-line basis

— Separate locking for instructions and data

— Single-precision floating-point operations

— Memory management unit especially designed for embedded applications

— Enhanced hardware and software debug support

— Dynamic power management

— Performance monitor facility

MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2

Freescale Semiconductor

Overview

• Security Engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,

IEEE Std 802.11i™, iSCSI, and IKE processing. The Security Engine contains 4 Crypto-channels, a Controller, and a set of crypto Execution Units (EUs). The Execution Units are:

— Public Key Execution Unit (PKEU) supporting the following:

– RSA and Diffie-Hellman

– Programmable field size up to 2048-bits

– Elliptic curve cryptography

– F2m and F(p) modes

– Programmable field size up to 511-bits

— Data Encryption Standard Execution Unit (DEU)

– DES, 3DES

– Two key (K1, K2) or Three Key (K1, K2, K3)

– ECB and CBC modes for both DES and 3DES

— Advanced Encryption Standard Unit (AESU)

– Implements the Rinjdael symmetric key cipher

– Key lengths of 128, 192, and 256 bits.Two key

– ECB, CBC, CCM, and Counter modes

— ARC Four execution unit (AFEU)

– Implements a stream cipher compatible with the RC4 algorithm

– 40- to 128-bit programmable key

— Message Digest Execution Unit (MDEU)

– SHA with 160-bit or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— Random Number Generator (RNG)

— 4 Crypto-channels, each supporting multi-command descriptor chains

– Static and/or dynamic assignment of crypto-execution units via an integrated controller

– Buffer size of 256 Bytes for each execution unit, with flow control for large data sizes

• High-performance RISC CPM operating at up to 333 MHz

— CPM software compatibility with previous PowerQUICC families

— One instruction per clock

— Executes code from internal ROM or instruction RAM

— 32-bit RISC architecture

— Tuned for communication environments: instruction set supports CRC computation and bit manipulation.

— Internal timer

— Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and virtual DMA channels for each peripheral controller

— Handles serial protocols and virtual DMA


Freescale Semiconductor 3

Overview

— Two full-duplex fast communications controllers (FCCs) that support the following protocols:

– ATM protocol through two UTOPIA level 2 interfaces

– IEEE Std 802.3™/Fast Ethernet (10/100)

– HDLC

– Totally transparent operation

— Three full-duplex serial communications controllers (SCCs) support the following protocols:

– High level/synchronous data link control (HDLC/SDLC)

– LocalTalk (HDLC-based local area network protocol)

– Universal asynchronous receiver transmitter (UART)

– Synchronous UART (1x clock mode)

– Binary synchronous communication (BISYNC)

– Totally transparent operation

– QMC support, providing 64 channels per SCC using only one physical TDM interface

— Universal serial bus (USB) controller that is full/low-speed compliant (multiplexed on an SCC)

– USB host mode

– Supports USB slave mode

— Serial peripheral interface (SPI) support for master or slave

— I

2

C bus controller

— Two serial management controllers (SMCs) supporting:

– UART

– Transparent

– General-circuit interfaces (GCI)

— Time-slot assigner supports multiplexing of data from any of the SCCs and FCCs onto eight time-division multiplexed (TDM) interfaces. The time-slot assigner supports the following

TDM formats:

– T1/CEPT lines

– T3/E3

– Pulse code modulation (PCM) highway interface

– ISDN primary rate

– Freescale interchip digital link (IDL)

– General circuit interface (GCI)

— User-defined interfaces

— Eight independent baud rate generators (BRGs)

— Four general-purpose 16-bit timers or two 32-bit timers

— General-purpose parallel ports—16 parallel I/O lines with interrupt capability

• 256 Kbytes of on-chip memory

— Can act as a 256-Kbyte level-2 cache

— Can act as a 256-Kbyte or two 128-Kbyte memory-mapped SRAM arrays

4



Overview

— Can be partitioned into 128-Kbyte L2 cache plus 128-Kbyte SRAM

— Full ECC support on 64-bit boundary in both cache and SRAM modes

— SRAM operation supports relocation and is byte-accessible

— Cache mode supports instruction caching, data caching, or both

— External masters can force data to be allocated into the cache through programmed memory ranges or special transaction types (stashing).

— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)

— Supports locking the entire cache or selected lines

– Individual line locks set and cleared through Book E instructions or by externally mastered transactions

— Global locking and flash clearing done through writes to L2 configuration registers

— Instruction and data locks can be flash cleared separately

— Read and write buffering for internal bus accesses

• Address translation and mapping unit (ATMU)

— Eight local access windows define mapping within local 32-bit address space

— Inbound and outbound ATMUs map to larger external address spaces

– Three inbound windows plus a configuration window on PCI

– Four inbound windows

– Four outbound windows plus default translation for PCI

• DDR memory controller

— Programmable timing supporting first generation DDR SDRAM

— 64-bit data interface, up to MHz data rate

— Four banks of memory supported, each up to 1 Gbyte

— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports

— Full ECC support

— Page mode support (up to 16 simultaneous open pages)

— Contiguous or discontiguous memory mapping

— Sleep mode support for self refresh DDR SDRAM

— Supports auto refreshing

— On-the-fly power management using CKE signal

— Registered DIMM support

— Fast memory access via JTAG port

— 2.5-V SSTL2 compatible I/O

• Programmable interrupt controller (PIC)

— Programming model is compliant with the OpenPIC architecture

— Supports 16 programmable interrupt and processor task priority levels

— Supports 12 discrete external interrupts

— Supports 4 message interrupts with 32-bit messages



Overview

— Supports connection of an external interrupt controller such as the 8259 programmable interrupt controller

— Four global high resolution timers/counters that can generate interrupts

— Supports additional internal interrupt sources

— Supports fully nested interrupt delivery

— Interrupts can be routed to external pin for external processing

— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs

— Interrupt summary registers allow fast identification of interrupt source

• Two I

2

C controllers (one is contained within the CPM, the other is a stand-alone controller which is not part of the CPM)

— Two-wire interface

— Multiple master support

— Master or slave I

2

C mode support

— On-chip digital filtering rejects spikes on the bus

• Boot sequencer

— Optionally loads configuration data from serial ROM at reset via the stand-alone I

2

C interface

— Can be used to initialize configuration registers and/or memory

— Supports extended I

2

C addressing mode

— Data integrity checked with preamble signature and CRC

• DUART

— Two 4-wire interfaces (RXD, TXD, RTS, CTS)

— Programming model compatible with the original 16450 UART and the PC16550D

• Local bus controller (LBC)

— Multiplexed 32-bit address and data operating at up to 166 MHz

— Eight chip selects support eight external slaves

— Up to eight-beat burst transfers

— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller

— Three protocol engines available on a per chip select basis:

– General purpose chip select machine (GPCM)

– Three user programmable machines (UPMs)

– Dedicated single data rate SDRAM controller

— Parity support

— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)

• Two Three-speed (10/100/1000)Ethernet controllers (TSECs)

— Dual IEEE 802.3, 802.3u, 802.3x, 802.3z AC compliant controllers

— Support for Ethernet physical interfaces:

– 10/100/1000 Mbps IEEE 802.3 GMII

– 10/100 Mbps IEEE 802.3 MII

6



Overview

– 10 Mbps IEEE 802.3 MII

– 1000 Mbps IEEE 802.3z TBI

– 10/100/1000 Mbps RGMII/RTBI

— Full- and half-duplex support

— Buffer descriptors are backwards compatible with MPC8260 and MPC860T 10/100 programming models

— 9.6-Kbyte jumbo frame support

— RMON statistics support

— 2-Kbyte internal transmit and receive FIFOs

— MII management interface for control and status

— Programmable CRC generation and checking

• OCeaN switch fabric

— Three-port crossbar packet switch

— Reorders packets from a source based on priorities

— Reorders packets to bypass blocked packets

— Implements starvation avoidance algorithms

— Supports packets with payloads of up to 256 bytes

• Integrated DMA controller

— Four-channel controller

— All channels accessible by both local and remote masters

— Extended DMA functions (advanced chaining and striding capability)

— Support for scatter and gather transfers

— Misaligned transfer capability

— Interrupt on completed segment, link, list, and error

— Supports transfers to or from any local memory or I/O port

— Selectable hardware-enforced coherency (snoop/no-snoop)

— Ability to start and flow control each DMA channel from external 3-pin interface

— Ability to launch DMA from single write transaction

• PCI Controllers

— PCI 2.2 compatible

— One 64-bit or two 32-bit PCI ports supported at 16 to 66 MHz

— Host and agent mode support, 64-bit PCI port can be host or agent, if two 32-bit ports, only one can be an agent

— 64-bit dual address cycle (DAC) support

— Supports PCI-to-memory and memory-to-PCI streaming

— Memory prefetching of PCI read accesses

— Supports posting of processor-to-PCI and PCI-to-memory writes



Electrical Characteristics

— PCI 3.3-V compatible

— Selectable hardware-enforced coherency

— Selectable clock source (SYSCLK or independent PCI_CLK)

• Power management

— Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O

— Supports power save modes: doze, nap, and sleep

— Employs dynamic power management

— Selectable clock source (sysclk or independent PCI_CLK)

• System performance monitor

— Supports eight 32-bit counters that count the occurrence of selected events

— Ability to count up to 512 counter specific events

— Supports 64 reference events that can be counted on any of the 8 counters

— Supports duration and quantity threshold counting

— Burstiness feature that permits counting of burst events with a programmable time between bursts

— Triggering and chaining capability

— Ability to generate an interrupt on overflow

• System access port

— Uses JTAG interface and a TAP controller to access entire system memory map

— Supports 32-bit accesses to configuration registers

— Supports cache-line burst accesses to main memory

— Supports large block (4-Kbyte) uploads and downloads

— Supports continuous bit streaming of entire block for fast upload and download

• IEEE Std 1149.1™-compatible, JTAG boundary scan

• 783 FC-PBGA package

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC8555E. The MPC8555E is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.

2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

8




2.1.1

Absolute Maximum Ratings

Table 1

provides the absolute maximum ratings.

Table 1. Absolute Maximum Ratings

1

Characteristic Symbol Max Value Unit Notes

Core supply voltage

PLL supply voltage

DDR DRAM I/O voltage

Three-speed Ethernet I/O, MII management voltage

V

DD

AV

DD

GV

DD

LV

DD

–0.3 to 1.32

0.3 to 1.43 (for 1 GHz only)

–0.3 to 1.32

0.3 to 1.43 (for 1 GHz only)

–0.3 to 3.63

–0.3 to 3.63

–0.3 to 2.75

–0.3 to 3.63

V

V

V

V

CPM, PCI, local bus, DUART, system control and power management, I

2

C, and JTAG I/O voltage

Input voltage DDR DRAM signals

DDR DRAM reference

Three-speed Ethernet signals

CPM, Local bus, DUART,

SYSCLK, system control and power management, I

2

C, and

JTAG signals

OV

DD

MV

IN

MV

REF

LV

IN

OV

IN

–0.3 to (GV

DD

+ 0.3)

–0.3 to (GV

DD

+ 0.3)

–0.3 to (LV

DD

+ 0.3)

–0.3 to (OV

DD

+ 0.3)1

V

V

V

V

V

3

2, 5

2, 5

4, 5

5

Storage temperature range

PCI OV

IN

T

STG

–0.3 to (OV

DD

+ 0.3)

–55 to 150

V

°C

6

Notes:

1. Functional and tested operating conditions are given in

Table 2 . Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.

2. Caution: MV

IN

must not exceed GV

DD

by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

3. Caution: OV

IN

must not exceed OV

DD


4. Caution: LV

IN

must not exceed LV

DD


5. (M,L,O)V

IN

and MV

REF

may overshoot/undershoot to a voltage and for a maximum duration as shown in

Figure 2

.

6. OV

IN on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as shown in

Figure 3

.

2.1.2

Power Sequencing

The MPC8555Erequires its power rails to be applied in a specific sequence in order to ensure proper device operation. These requirements are as follows for power up:

1. V

DD

, AV

DDn

2. GV

DD

, LV

DD

, OV

DD

(I/O supplies)




Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value before the voltage rails on the current step reach ten percent of theirs.

NOTE

If the items on line 2 must precede items on line 1, please ensure that the delay does not exceed 500 ms and the power sequence is not done greater than once per day in production environment.

NOTE

From a system standpoint, if the I/O power supplies ramp prior to the V

DD core supply, the I/Os on the MPC8555E may drive a logic one or zero during power-up.

2.1.3

Recommended Operating Conditions

Table 2

provides the recommended operating conditions for the MPC8555E. Note that the values in

Table 2

are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.

Table 2. Recommended Operating Conditions

Core supply voltage

Characteristic Symbol

V

DD

Unit

V

PLL supply voltage

DDR DRAM I/O voltage

Three-speed Ethernet I/O voltage

AV

DD

GV

DD

LV

DD

OV

DD

Recommended Value

1.2 V ± 60 mV

1.3 V± 50 mV (for 1 GHz only)

1.2 V ± 60 mV

1.3 V ± 50 mV (for 1 GHz only)

2.5 V ± 125 mV

3.3 V ± 165 mV

2.5 V ± 125 mV

3.3 V ± 165 mV

V

V

V

V

I

PCI, local bus, DUART, system control and power management,

2

C, and JTAG I/O voltage

Input voltage DDR DRAM signals

DDR DRAM reference

Three-speed Ethernet signals

PCI, local bus, DUART,

SYSCLK, system control and power management, I

2

C, and

JTAG signals

Die-junction Temperature

MV

IN

MV

REF

LV

IN

OV

IN

T j

GND to GV

DD

GND to GV

DD

GND to LV

DD

GND to OV

DD

0 to 105

V

V

V

V

°C

10




Figure 2

shows the undershoot and overshoot voltages at the interfaces of the MPC8555E.

V

IH

G/L/OV

DD

+ 20%

G/L/OV

DD

+ 5%

G/L/OV

DD

GND

GND – 0.3 V

V

IL

GND – 0.7 V

Not to Exceed 10% of t

SYS

1

Note:

1. Note that t

SYS

refers to the clock period associated with the SYSCLK signal.

Figure 2. Overshoot/Undershoot Voltage for GV

DD

/OV

DD

/LV

DD

The MPC8555E core voltage must always be provided at nominal 1.2 V (see

Table 2 for actual

recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of supply pins and must be provided at the voltages shown in

Table 2

. The input voltage threshold scales with respect to the associated I/O supply voltage. OV

DD

and LV

DD

based receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential receiver referenced the externally supplied MV

REF

signal (nominally set to

GV

DD

/2) as is appropriate for the SSTL2 electrical signaling standard.




Figure 3

shows the undershoot and overshoot voltage of the PCI interface of the MPC8555E for the 3.3-V signals, respectively.

11 ns

(Min)

+7.1 V

Overvoltage

Waveform

7.1 V p-to-p

(Min)

0 V

4 ns

(Max)

4 ns

(Max)

62.5 ns

+3.6 V

Undervoltage

Waveform

7.1 V p-to-p

(Min)

–3.5 V

Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling

2.1.4

Output Driver Characteristics

Table 3

provides information on the characteristics of the output driver strengths. The values are preliminary estimates.

Table 3. Output Drive Capability

Driver Type

Programmable Output

Impedance (Ω)

Supply

Voltage

Notes

Local bus interface utilities signals

PCI signals

25

42 (default)

25

42 (default)

OV

DD

= 3.3 V

DDR signal

TSEC/10/100 signals

DUART, system control, I2C, JTAG

20

42

42

GV

DD

= 2.5 V

LV

DD

= 2.5/3.3 V

OV

DD

= 3.3 V

Notes:

1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.

2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.

1

2

12



Power Characteristics

3 Power Characteristics

The estimated typical power dissipation for this family of PowerQUICC III devices is shown in Table 4

.

Table 4. Power Dissipation

(1) (2)

CCB Frequency (MHz) Core Frequency (MHz) V

DD

Typical Power

(3)(4)

(W) Maximum Power

(5)

(W)

2.

3.

4.

5.

6.

200

267

333

400

500

600

533

667

800

667

833

1000

(6)

1.2

1.2

1.2

1.2

1.3

1.2

1.2

1.2

1.2

5.9

6.3

6.0

6.5

9.6

4.9

5.2

5.5

5.4

7.7

9.1

7.9

9.3

12.8

6.6

7.0

7.3

7.2

Notes:

1. The values do not include I/O supply power (OV

DD

, LV

DD

, GV

DD

) or AV

DD.

2. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Any customer design must take these considerations into account to ensure the maximum 105 degrees junction temperature is not exceeded on this device.

3. Typical power is based on a nominal voltage of V

DD

= 1.2V, a nominal process, a junction temperature of T j

= 105° C, and a

Dhrystone 2.1 benchmark application.

4. Thermal solutions likely need to design to a value higher than Typical Power based on the end application, T

A

target, and I/O power

5. Maximum power is based on a nominal voltage of V

DD

= 1.2V, worst case process, a junction temperature of T j

= 105° C, and an artificial smoke test.

6. The nominal recommended V

DD

= 1.3V for this speed grade.

Notes:

1.



Power Characteristics

Table 5. Typical I/O Power Dissipation

Interface Parameters

DDR I/O

PCI I/O

Local Bus I/O

TSEC I/O

CCB = 200 MHz

CCB = 266 MHz

CCB = 300 MHz

CCB = 333 MHz

64b, 66 MHz

64b, 33 MHz

32b, 66 MHz

32b, 33 MHz

32b, 167 MHz

32b, 133 MHz

32b, 83 MHz

32b, 66 MHz

32b, 33 MHz

MII

GMII or TBI

RGMII or RTBI

CPM - FCC MII

RMII

HDLC 16 Mbps

UTOPIA-8 SPHY

UTOPIA-8 MPHY

UTOPIA-16 SPHY

CPM - SCC

UTOPIA-16 MPHY

HDLC 16 Mbps

TDMA or TDMB Nibble Mode

TDMA or TDMB Per Channel

GV

DD

(2.5 V)

OV

DD

(3.3 V)

—

—

—

—

—

—

—

—

0.46

0.59

0.66

0.73

—

—

—

—

—

—

—

—

—

—

—

—

—

—

0.07

—

—

—

0.30

0.24

0.16

0.13

0.14

0.08

0.07

0.04

—

—

—

—

0.015

0.013

0.009

0.06

0.1

0.094

0.135

0.004

0.01

0.005

LV

DD

(3.3 V)

—

0.01

0.07

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

LV

DD

(2.5 V)

—

—

—

0.04

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Unit

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

Comments

—

—

—

—

—

—

Multiply by 2 if using two 32b ports

—

—

—

—

—

Multiply by number of interfaces used.

—

—

—

—

—

—

—

—

—

Up to 4 TDM channels, multiply by number of TDM channels.

14



Clock Timing

4 Clock Timing

4.1

System Clock Timing

Table 6

provides the system clock (SYSCLK) AC timing specifications for the MPC8555E.

Table 6. SYSCLK AC Timing Specifications

Parameter/Condition Symbol Min Typical Max Unit Notes

SYSCLK frequency

SYSCLK cycle time

SYSCLK rise and fall time

SYSCLK duty cycle f

SYSCLK t

SYSCLK t

KH

, t

KL t

KHK

/t

SYSCLK

—

—

6.0

0.6

40

—

—

1.0

—

166

—

1.2

60

MHz ns ns

%

1

—

2

3

SYSCLK jitter — — +/- 150 ps 4, 5

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating frequencies.

2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. For spread spectrum clocking, guidelines are ±1% of the input frequency with a maximum of 60 kHz of modulation regardless of the input frequency.

4.2

TSEC Gigabit Reference Clock Timing

Table 7

provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the

MPC8555E.

Table 7. EC_GTX_CLK125 AC Timing Specifications

Parameter/Condition Symbol Min Typical Max Unit Notes

EC_GTX_CLK125 frequency

EC_GTX_CLK125 cycle time

EC_GTX_CLK125 rise time

EC_GTX_CLK125 fall time

EC_GTX_CLK125 duty cycle f

G125 t

G125 t

G125R t

G125F t

G125H

/t

G125

—

—

—

—

125

8

—

—

—

—

—

1.0

1.0

MHz ns ns ns

%

—

—

1

1

1, 2

GMII, TBI

RGMII, RTBI

45

47

55

53

Notes:

1. Timing is guaranteed by design and characterization.

2. EC_GTX_CLK125 is used to generate GTX clock for TSEC transmitter with 2% degradation. EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as PHY device can tolerate the duty cycle generated by GTX_CLK of TSEC.



RESET Initialization

4.3

Real Time Clock Timing

Table 8

provides the real time clock (RTC) AC timing specifications.

Table 8. RTC AC Timing Specifications

Parameter/Condition

RTC clock high time

RTC clock low time

Symbol

t

RTCH t

RTCL

Min

2 x t

CCB_CLK

2 x t

CCB_CLK

Typical

—

—

Max

—

—

Unit

ns ns

Notes

—

—

5 RESET Initialization

This section describes the AC electrical specifications for the RESET initialization timing requirements of the MPC8555E.

Table 9 provides the RESET initialization AC timing specifications.

Table 9. RESET Initialization Timing Specifications

Parameter/Condition Min Max Unit Notes

Required assertion time of HRESET

Minimum assertion time for SRESET

PLL input setup time with stable SYSCLK before HRESET negation

Input setup time for POR configs (other than PLL config) with respect to negation of HRESET

Input hold time for POR configs (including PLL config) with respect to negation of HRESET

100

512

100

4

2

—

—

—

—

—

µs

SYSCLKs

µs

SYSCLKs

SYSCLKs

Maximum valid-to-high impedance time for actively driven POR configs with respect to negation of HRESET

— 5 SYSCLKs

Notes:

1. SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8555E. See the MPC8555E

PowerQUICC™ III Integrated Communications Processor Reference Manual for more details.

—

1

—

1

1

1

Table 10

provides the PLL and DLL lock times.

Table 10. PLL and DLL Lock Times

Parameter/Condition Min Max Unit Notes

PLL lock times

DLL lock times

—

7680

100

122,880

µs

CCB Clocks

—

1, 2

Notes:

1. DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio results in the minimum and an 8:1 ratio results in the maximum.

2. The CCB clock is determined by the SYSCLK × platform PLL ratio.

16



DDR SDRAM

6 DDR SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the

MPC8555E.

6.1

DDR SDRAM DC Electrical Characteristics

Table 11 provides the recommended operating conditions for the DDR SDRAM component(s) of the

MPC8555E.

Table 11. DDR SDRAM DC Electrical Characteristics

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage

I/O reference voltage

I/O termination voltage

Input high voltage

Input low voltage

Output leakage current

Output high current (V

OUT

= 1.95 V)

Output low current (V

OUT

= 0.35 V)

MV

REF

input leakage current

GV

DD

MV

REF

V

TT

V

IH

V

IL

I

OZ

I

OH

I

OL

I

VREF

2.375

0.49 × GV

DD

MV

REF

– 0.04

MV

REF

+ 0.18

–0.3

–10

–15.2

15.2

—

2.625

0.51 × GV

DD

MV

REF

+ 0.04

GV

DD

+ 0.3

MV

REF

– 0.18

10

—

—

5

V

V

V

V

V

µA mA mA

µA

1

2

3

—

—

4

—

—

—

Notes:

1. GV

DD

is expected to be within 50 mV of the DRAM GV

2. MV

REF

is expected to be equal to 0.5 × GV

DD

DD at all times.

, and to track GV

DD

DC variations as measured at the receiver. Peak-to-peak noise on MV

REF

may not exceed ±2% of the DC value.

3. V

TT

is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MV

REF

. This rail should track variations in the DC level of MV

REF

.

4. Output leakage is measured with all outputs disabled, 0 V ≤ V

OUT

≤ GV

DD

.

Table 12

provides the DDR capacitance.

Table 12. DDR SDRAM Capacitance

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS, MSYNC_IN

Delta input/output capacitance: DQ, DQS

C

IO

C

DIO

6

—

8

0.5

pF pF

1

1

Note:

1. This parameter is sampled. GV

DD

= 2.5 V ± 0.125 V, f = 1 MHz, T

A

= 25°C, V

OUT

= GV

DD

/2, V

OUT

(peak to peak) = 0.2 V.



DDR SDRAM

6.2

DDR SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface.

6.2.1

DDR SDRAM Input AC Timing Specifications

Table 13

provides the input AC timing specifications for the DDR SDRAM interface.

Table 13. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions with GV

DD

of 2.5 V ± 5%.

Parameter Symbol Min Max Unit Notes

AC input low voltage

AC input high voltage

MDQS—MDQ/MECC input skew per byte

For DDR = 333 MHz

For DDR < 266 MHz t

V

V

IL

IH

DISKEW

—

MV

REF

+ 0.31

—

MV

REF

– 0.31

GV

DD

+ 0.3

750

1125

V

V ps

—

—

1

Note:

1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 <= n <=

7) or ECC (MECC[{0...7}] if n = 8).

6.2.2

DDR SDRAM Output AC Timing Specifications

Table 14

and

Table 15

provide the output AC timing specifications and measurement conditions for the

DDR SDRAM interface.

Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode


DD

of 2.5 V ± 5%.

Parameter Symbol

1

Min Max Unit Notes

MCK[n] cycle time, (MCK[n]/MCK[n] crossing) t

MCK

6 10 ns 2 ps 3 Skew between any MCK to ADDR/CMD

333 MHz

266 MHz

200 MHz

ADDR/CMD output setup with respect to MCK

333 MHz

266 MHz

200 MHz

ADDR/CMD output hold with respect to MCK

333 MHz

266 MHz

200 MHz

MCS(n) output setup with respect to MCK

333 MHz

266 MHz

200 MHz t

AOSKEW t t t

DDKHAS

DDKHAX

DDKHCS

–1000

–1100

–1200

2.8

3.45

4.6

2.0

2.65

3.8

2.8

3.45

4.6

200

300

400

—

—

— ns ns ns

4

4

4

18



DDR SDRAM

Table 14. DDR SDRAM Output AC Timing Specifications for Source Synchronous Mode (continued)


DD

of 2.5 V ± 5%.


1


MCS(n) output hold with respect to MCK

333 MHz

266 MHz

200 MHz

MCK to MDQS

333 MHz

266 MHz

200 MHz

MDQ/MECC/MDM output setup with respect to

MDQS

333 MHz

266 MHz

200 MHz t t t t

DDKHCX

DDKHMH

DDKHDS,

DDKLDS

2.0

2.65

3.8

–0.9

–1.1

–1.2

—

0.3

0.5

0.6

— ns ns ps

4

5

6

900

900

1200

MDQ/MECC/MDM output hold with respect to

MDQS

333 MHz

266 MHz

200 MHz t t

DDKHDX,

DDKLDX

900

900

1200

— ps 6

MDQS preamble start

MDQS epilogue end t

DDKHMP t

DDKLME

–0.5 × t

MCK

–0.9

– 0.9

–0.5 × t

MCK

0.3

+0.3

ns ns

7

7

Notes:

1. The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, t

DDKHAS

symbolizes DDR timing (DD) for the time t

MCK

memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, t

DDKLDX

symbolizes DDR timing (DD) for the time t

MCK

memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. In the source synchronous mode, MCK/MCK can be shifted in 1/4 applied cycle increments through the Clock Control

Register. For the skew measurements referenced for t

AOSKEW

it is assumed that the clock adjustment is set to align the address/command valid with the rising edge of MCK.

4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the

ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied cycle. The MCSx pins are separated from the ADDR/CMD (address and command) bus in the HW spec. This was separated because the MCSx pins typically have different loadings than the rest of the address and command bus, even though they have the same timings.

5. Note that t

DDKHMH follows the symbol conventions described in note 1. For example, t

DDKHMH describes the DDR timing

(DD) from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). In the source synchronous mode,

MDQS can launch later than MCK by 0.3 ns at the maximum. However, MCK may launch later than MDQS by as much as

0.9 ns. t

DDKHMH

can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this typically is set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two parameters have been set to the same adjustment value. See the

MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits.

6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8555E.

7. All outputs are referenced to the rising edge of MCK(n) at the pins of the MPC8555E. Note that t

DDKHMP follows the symbol conventions described in note 1.



DDR SDRAM

Figure 4

shows the DDR SDRAM output timing for address skew with respect to any MCK.

MCK[n]

MCK[n] t

MCK t

AOSKEWmax)

ADDR/CMD CMD t

AOSKEW(min)

NOOP

ADDR/CMD CMD NOOP

Figure 4. Timing Diagram for t

AOSKEW

Measurement

Figure 5

shows the DDR SDRAM output timing diagram for the source synchronous mode.

MCK[n]

MCK[n] t

MCK

ADDR/CMD Write A0 t

DDKHAS

,t

DDKHCS t

DDKHAX

,t

DDKHCX

NOOP t

DDKHMP t

DDKHMH

MDQS[n] t

DDKHDS t

DDKLDS

MDQ[x] D0 D1 t

DDKLDX t

DDKHDX

Figure 5. DDR SDRAM Output Timing Diagram for Source Synchronous Mode

t

DDKLME

20



Figure 6

provides the AC test load for the DDR bus.

Output

Z

0

= 50 Ω

R

L

= 50 Ω

GV

DD

/2

Figure 6. DDR AC Test Load

Table 15. DDR SDRAM Measurement Conditions

Symbol DDR

V

TH

V

OUT

MV

REF

± 0.31 V

0.5 × GV

DD

Notes:

1. Data input threshold measurement point.

2. Data output measurement point.

Unit

V

V

Notes

1

2

7 DUART

This section describes the DC and AC electrical specifications for the DUART interface of the

MPC8555E.

7.1

DUART DC Electrical Characteristics

Table 16

provides the DC electrical characteristics for the DUART interface of the MPC8555E.

Table 16. DUART DC Electrical Characteristics

Parameter Symbol Test Condition Min Max

High-level input voltage

Low-level input voltage

Input current

High-level output voltage

V

IH

V

V

IL

I

IN

OH

V

V

IN

OUT

1

≥ V

OH

(min) or

V

OUT

≤ V

OL

(max)

= 0 V or V

IN

= V

DD

OV

DD

= min,

I

OH

= –100 µA

OV

DD

= min, I

OL

= 100 µA

OV

DD

2

–0.3

—

– 0.2

OV

DD

+ 0.3

0.8

±5

—

Low-level output voltage V

OL

— 0.2

Note:

1. Note that the symbol V

IN

, in this case, represents the OV

IN

symbol referenced in

Table 1

and

Table 2 .

Unit

V

V

µA

V

V

DUART



Ethernet: Three-Speed, MII Management

7.2

DUART AC Electrical Specifications

Table 17

provides the AC timing parameters for the DUART interface of the MPC8555E.

Table 17. DUART AC Timing Specifications

Parameter Value Unit Notes

Minimum baud rate

Maximum baud rate f

CCB_CLK

/ 1048576 f

CCB_CLK

/ 16

16 baud baud

3

1, 3

Oversample rate — 2, 3

Notes:

1. Actual attainable baud rate is limited by the latency of interrupt processing.

2. The middle of a start bit is detected as the 8 th

sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16 th

sample.

3. Guaranteed by design.

8 Ethernet: Three-Speed, MII Management

This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management.

8.1

Three-Speed Ethernet Controller (TSEC)

(10/100/1000 Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical

Characteristics

The electrical characteristics specified here apply to all GMII (gigabit media independent interface), the

MII (media independent interface), TBI (ten-bit interface), RGMII (reduced gigabit media independent interface), and RTBI (reduced ten-bit interface) signals except MDIO (management data input/output) and

MDC (management data clock). The RGMII and RTBI interfaces are defined for 2.5 V, while the GMII and TBI interfaces can be operated at 3.3 V or 2.5 V. Whether the GMII, MII, or TBI interface is operated at 3.3 or 2.5 V, the timing is compliant with the IEEE 802.3 standard. The RGMII and RTBI interfaces follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical Layer Device

Specification Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are specified in

Section 8.3, “Ethernet Management Interface Electrical Characteristics

.”

8.1.1

TSEC DC Electrical Characteristics

All GMII, MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes

specified in Table 18

and

Table 19

. The potential applied to the input of a GMII, MII, TBI, RGMII, or

RTBI receiver may exceed the potential of the receiver’s power supply (for example, a GMII driver powered from a 3.6-V supply driving V

OH

into a GMII receiver powered from a 2.5-V supply). Tolerance for dissimilar GMII driver and receiver supply potentials is implicit in these specifications. The RGMII and RTBI signals are based on a 2.5-V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.

22




Table 18. GMII, MII, and TBI DC Electrical Characteristics

Parameter Symbol Conditions Min

Supply voltage 3.3 V

Output high voltage

Output low voltage

Input high voltage

LV

DD

V

OH

V

OL

V

IH

I

I

OH

OL

= –4.0 mA

= 4.0 mA

—

—

LV

LV

DD

DD

= Min

= Min

—

3.13

2.40

GND

1.70

Input low voltage

Input high current

Input low current

V

IL

I

IH

I

IL

—

V

IN

1

= LV

DD

V

IN

1

= GND

— –0.3

—

–600

Note:

1. The symbol V

IN

, in this case, represents the LV

IN

symbol referenced in Table 1 and

Table 2

.

Max

3.47

LV

DD

+ 0.3

0.50

LV

DD

+ 0.3

0.90

40

—

Table 19. GMII, MII, RGMII RTBI, and TBI DC Electrical Characteristics

Parameters Symbol Min Max

Supply voltage 2.5 V

Output high voltage (LV

Output low voltage (LV

Input high voltage (LV

DD

= Min, I

DD

= Min, I

DD

= Min)

Input low voltage (LV

DD

= Min)

Input high current (V

IN

1

= LV

DD

)

Input low current (V

IN

1

= GND)

OH

= –1.0 mA)

OL

= 1.0 mA)

LV

DD

V

V

OL

V

V

I

OH

IH

IL

IH

2.37

2.00

GND – 0.3

1.70

–0.3

—

2.63

LV

DD

+ 0.3

0.40

LV

DD

+ 0.3

0.70

10

I

IL

–15 —

Note:


IN

, in this case, represents the LV

IN


Table 1

and Table 2

.

Unit

V

V

V

V

V

µA

µA

Unit

V

V

V

V

V

µA

µA




8.2

GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications

The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.

8.2.1

GMII AC Timing Specifications

This section describes the GMII transmit and receive AC timing specifications.

8.2.2

GMII Transmit AC Timing Specifications

Table 20

provides the GMII transmit AC timing specifications.

Table 20. GMII Transmit AC Timing Specifications

At recommended operating conditions with LV

DD

of 3.3 V ± 5%.

Parameter/Condition Symbol

1

Min Typ Max Unit

GTX_CLK clock period

GTX_CLK duty cycle

GMII data TXD[7:0], TX_ER, TX_EN setup time t

GTX t

GTXH

/t

GTX t

GTKHDV

—

40

2.5

8.0

—

—

—

60

— ns

% ns

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay

GTX_CLK data clock rise and fall times

t

GTKHDX t

GTXR

3

, t

GTXR

2,4

0.5

—

—

—

5.0

1.0

ns ns

Notes:

1. The symbols used for timing specifications herein follow the pattern t

(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t

(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t

GTKHDV

symbolizes GMII transmit timing (GT) with respect to the t

GTX

clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, t

GTKHDX

symbolizes GMII transmit timing (GT) with respect to the t

GTX

clock reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t

GTX

represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. Signal timings are measured at 0.7 V and 1.9 V voltage levels.

3. Guaranteed by characterization.


Figure 7

shows the GMII transmit AC timing diagram.

t

GTX

GTX_CLK t

GTXH t

GTXF

TXD[7:0]

TX_EN

TX_ER t

GTXR t

GTKHDX t

GTKHDV

Figure 7. GMII Transmit AC Timing Diagram

24




8.2.2.1

GMII Receive AC Timing Specifications

Table 21

provides the GMII receive AC timing specifications.

Table 21. GMII Receive AC Timing Specifications


DD

of 3.3 V ± 5%.


1


RX_CLK clock period

RX_CLK duty cycle

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK t

GRX t

GRXH

/t

GRX t

GRDVKH

—

40

2.0

8.0

—

—

—

60

— ns

% ns

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise and fall time t

GRDXKH t

GRXR

, t

GRXF

2,3

0.5

—

—

—

—

1.0

ns ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state)

(reference)(state)

for inputs and t


for outputs. For example, t

GRDVKH symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the t

RX

clock reference (K) going to the high state (H) or setup time. Also, t

GRDXKL

symbolizes GMII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the t

GRX

clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t

GRX

represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).



Figure 8

provides the AC test load for TSEC.

Output

Z

0

= 50 Ω

R

L

= 50 Ω

LV

DD

/2

Figure 8. TSEC AC Test Load

Figure 9

shows the GMII receive AC timing diagram.

t

GRX t

GRXR

RX_CLK t

GRXH t

GRXF

RXD[7:0]

RX_DV

RX_ER t

GRDXKH t

GRDVKH

Figure 9. GMII Receive AC Timing Diagram




8.2.3

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.3.1

MII Transmit AC Timing Specifications

Table 22

provides the MII transmit AC timing specifications.

Table 22. MII Transmit AC Timing Specifications


DD

of 3.3 V ± 5%.


1


TX_CLK clock period 10 Mbps

TX_CLK clock period 100 Mbps t

MTX

2 t

MTX

—

—

400

40

—

— ns ns

TX_CLK duty cycle

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay

TX_CLK data clock rise and fall time t

MTXH/ t

MTX t

MTKHDX t

MTXR

, t

MTXF

2,3

35

1

1.0

—

5

—

65

15

4.0

% ns ns

Notes:



(reference)(state)

for inputs and t



MTKHDX symbolizes MII transmit timing (MT) for the time t

MTX

clock reference (K) going high (H) until data outputs (D) are invalid

(X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of t

MTX

represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).



Figure 10

shows the MII transmit AC timing diagram.

t

MTX

TX_CLK t

MTXH t

MTXF

TXD[3:0]

TX_EN

TX_ER t

MTXR t

MTKHDX

Figure 10. MII Transmit AC Timing Diagram

26




8.2.3.2

MII Receive AC Timing Specifications

Table 23

provides the MII receive AC timing specifications.

Table 23. MII Receive AC Timing Specifications


DD

of 3.3 V ± 5%.


1


RX_CLK clock period 10 Mbps

RX_CLK clock period 100 Mbps

RX_CLK duty cycle

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK t

MRX

2 t

MRX t

MRXH

/t

MRX t

MRDVKH

—

—

35

10.0

400

40

—

—

—

—

65

— ns ns

% ns

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

RX_CLK clock rise and fall time t

MRDXKH t

MRXR

, t

MRXF

2,3

10.0

1.0

—

—

—

4.0

ns ns

Notes:


(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t



MRDVKH

symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t

MRX

clock reference

(K) going to the high (H) state or setup time. Also, t

MRDXKL

symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the t

MRX

clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.

For example, the subscript of t

MRX

represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).


3.Guaranteed by design.

Figure 11 shows the MII receive AC timing diagram.

t

MRX

RX_CLK

RXD[3:0]

RX_DV

RX_ER t

MRXR t

MRXH t

MRXF

Valid Data t

MRDVKH t

MRDXKH

Figure 11. MII Receive AC Timing Diagram




8.2.4

TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

8.2.4.1

TBI Transmit AC Timing Specifications

Table 24

provides the MII transmit AC timing specifications.

Table 24. TBI Transmit AC Timing Specifications


DD

of 3.3 V ± 5%.


1


GTX_CLK clock period

GTX_CLK duty cycle t

TTX t

TTXH

/t

TTX t

TTKHDV

—

40

8.0

—

—

60 ns

%

GMII data TCG[9:0], TX_ER, TX_EN setup time

GTX_CLK going high

2.0

— — ns

GMII data TCG[9:0], TX_ER, TX_EN hold time from

GTX_CLK going high t

TTKHDX

1.0

— — ns

GTX_CLK clock rise and fall time t

TTXR

, t

TTXF

2,3

— — 1.0

ns

Notes:


(first two letters of functional block)(signal)(state

)(reference)(state)

for inputs and t



TTKHDV symbolizes the TBI transmit timing (TT) with respect to the time from t

TTX

(K) going high (H) until the referenced data signals (D) reach the valid state (V) or setup time. Also, t

TTKHDX symbolizes the TBI transmit timing (TT) with respect to the time from t

TTX

(K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t

TTX

represents the TBI (T) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).



Figure 12

shows the TBI transmit AC timing diagram.

t

TTX t

TTXR

GTX_CLK t

TTXH t

TTXF t

TTXF

TCG[9:0] t

TTKHDV t

TTKHDX

Figure 12. TBI Transmit AC Timing Diagram

t

TTXR

28




8.2.4.2

TBI Receive AC Timing Specifications

Table 25

provides the TBI receive AC timing specifications.

Table 25. TBI Receive AC Timing Specifications


DD

of 3.3 V ± 5%.


1


RX_CLK clock period

RX_CLK skew

RX_CLK duty cycle

RCG[9:0] setup time to rising RX_CLK t

TRX t

SKTRX

7.5

t

TRXH

/t

TRX

40 t

TRDVKH

2.5

16.0

—

—

—

8.5

60

— ns ns

% ns

RCG[9:0] hold time to rising RX_CLK

RX_CLK clock rise time and fall time t

TRDXKH

1.5

t

TRXR

, t

TRXF

2,3

0.7

—

—

—

2.4

ns ns

Note:



(reference)(state)

for inputs and t



TRDVKH symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t

TRX

clock reference (K) going to the high (H) state or setup time. Also, t

TRDXKH

symbolizes TBI receive timing (TR) with respect to the time data input signals (D) went invalid (X) relative to the t

TRX

clock reference (K) going to the high (H) state.

Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t

TRX

represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX).


Figure 13

shows the TBI receive AC timing diagram.

t

TRX

RX_CLK1

RXD[9:0] t

TRXH t

TRXR t

TRXF

Valid Data Valid Data t

TRDVKH t

SKTRX t

TRDXKH

RX_CLK0 t

TRXH t

TRDVKH t

TRDXKH

Figure 13. TBI Receive AC Timing Diagram




8.2.5

RGMII and RTBI AC Timing

Specifications

Table 26

presents the RGMII and RTBI AC timing specifications.

Table 26. RGMII and RTBI AC Timing Specifications


DD

of 2.5 V ± 5%.


1


Data to clock output skew (at transmitter)

Data to clock input skew (at receiver)

Clock cycle duration

Rise and fall times

3

Duty cycle for 1000Base-T

4

2

Duty cycle for 10BASE-T and 100BASE-TX

3 t

SKRGT

5 t

SKRGT t

RGT

6 t

RGTH

/t

RGT

6 t

RGTH

/t

RGT

6 t

RGTR

6,7

, t

RGTF

6,7

–500

1.0

7.2

45

40

—

0

—

8.0

50

50

—

500

2.8

8.8

55

60

0.75

ps ns ns

%

% ns

Notes:

1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent

RGMII and RTBI timing. For example, the subscript of t

RGT

represents the TBI (T) receive (RX) clock. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. The RGMII specification requires that PC board designer add 1.5 ns or greater in trace delay to the RX_CLK in order to meet this specification. However, as stated above, this device functions with only 1.0 ns of delay.

3. For 10 and 100 Mbps, t

RGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t

RGT

of the lowest speed transitioned between.



7. Signal timings are measured at 0.5 and 2.0 V voltage levels.

30




Figure 14

shows the RBMII and RTBI AC timing and multiplexing diagrams.

t

RGT t

RGTH

GTX_CLK

(At Transmitter) t

SKRGT

TXD[8:5][3:0]

TXD[7:4][3:0]

TXD[3:0]

TXD[8:5]

TXD[7:4]

TX_CTL

TXD[4]

TXEN

TXD[9]

TXERR t

SKRGT

TX_CLK

(At PHY)

RXD[8:5][3:0]

RXD[7:4][3:0]

RXD[3:0]

RXD[8:5]

RXD[7:4] t

SKRGT

RX_CTL

RXD[4]

RXDV

RXD[9]

RXERR

RX_CLK

(At PHY)

Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams

t

SKRGT

8.3

Ethernet Management Interface Electrical Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO

(management data input/output) and MDC (management data clock). The electrical characteristics for

GMII, RGMII, TBI and RTBI are specified in

Section 8.1, “Three-Speed Ethernet Controller (TSEC)

(10/100/1000 Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical Characteristics.”

8.3.1

MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics

for MDIO and MDC are provided in Table 27

.

Table 27. MII Management DC Electrical Characteristics

Parameter

Supply voltage (3.3 V)

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Symbol

OV

DD

V

OH

V

OL

V

IH

V

IL

Conditions

—

I

OH

= –1.0 mA

I

OL

= 1.0 mA

—

—

LV

DD

= Min

LV

DD

= Min

Min

3.13

2.10

GND

1.70

—

Max

3.47

LV

DD

+ 0.3

0.50

—

0.90

Unit

V

V

V

V

V




Table 27. MII Management DC Electrical Characteristics (continued)

Parameter Symbol Conditions Min Max

Input high current

Input low current

I

IH

I

IL

LV

LV

DD

DD

= Max

= Max

V

IN

V

1

IN

= 2.1 V

= 0.5 V

—

–600

Note:


IN


IN


Table 1

and

Table 2

.

40

—

Unit

µA

µA

8.3.2

MII Management AC Electrical Specifications

Table 28

provides the MII management AC timing specifications.

Table 28. MII Management AC Timing Specifications


DD

is 3.3 V ± 5%.


1

Min Typ Max Unit Notes

MDC frequency

MDC period

MDC clock pulse width high

MDC to MDIO valid

MDC to MDIO delay

MDIO to MDC setup time

MDIO to MDC hold time

MDC rise time f

MDC t

MDC t

MDCH t

MDKHDV t

MDKHDX t

MDDVKH t

MDDXKH t

MDCR

0.893

96

32

10

5

0

—

—

—

—

—

—

—

—

1120

2*[1/(f

2*[1/(f

10.4

— ccb_clk ccb_clk

—

—

10

/8)]

/8)]

MHz ns ns ns ns ns ns ns

2

3

3

MDC fall time t

MDHF

— — 10 ns

Notes:



(reference)(state)

for inputs and t



MDKHDX symbolizes management data timing (MD) for the time t

MDC

from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, t

MDDVKH

symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the t

MDC

clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the system clock speed (that is, for a system clock of 267 MHz, the delay is 70 ns and for a system clock of 333 MHz, the delay is 58 ns).

3. This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay is 60 ns and for a

CCB clock of 333 MHz, the delay is 48 ns).


32



Local Bus

Figure 15

shows the MII management AC timing diagram.

t

MDC t

MDCR

MDC t

MDCH t

MDCF

MDIO

(Input) t

MDDVKH t

MDDXKH

MDIO

(Output) t

MDKHDX

Figure 15. MII Management Interface Timing Diagram

9 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the

MPC8555E.

9.1

Local Bus DC Electrical Characteristics

Table 29

provides the DC electrical characteristics for the local bus interface.

Table 29. Local Bus DC Electrical Characteristics




V

V

IH

IL

V

OUT

≥ V

OH

(min) or

V

OUT

≤ V

OL

(max)

V

IN

1

= 0 V or V

IN

= V

DD

2

–0.3

OV

DD

+ 0.3

0.8

Input current I

IN

—

High-level output voltage V

OH

OV

DD

= min,

I

OH

= –2mA

OV

DD

= min, I

OL

= 2mA

OV

DD

–0.2


OL

—

Note:


IN


IN


Table 1 and

Table 2 .

±5

—

0.2

Unit

V

V

µA

V

V



Local Bus

9.2

Local Bus AC Electrical Specifications

Table 30

describes the general timing parameters of the local bus interface of the MPC8555E with the DLL enabled.

Table 30. Local Bus General Timing Parameters—DLL Enabled

Configuration

7

Parameter

Local bus cycle time

LCLK[n] skew to LCLK[m] or LSYNC_OUT

Input setup to local bus clock (except

LUPWAIT)

LUPWAIT input setup to local bus clock

Input hold from local bus clock (except

LUPWAIT)

LUPWAIT input hold from local bus clock

LALE output transition to LAD/LDP output transition (LATCH hold time)

Local bus clock to output valid (except

LAD/LDP and LALE)

Symbol

1

t

LBK t

LBKSKEW t

LBIVKH1 t

LBIVKH2 t

LBIXKH1 t

LBIXKH2 t

LBOTOT t

LBKHOV1

Min

6.0

—

1.8

1.7

0.5

1.0

1.5

—

Max

—

150

—

—

—

—

—

Unit

ns ps ns ns ns ns ns ns

Notes

2

7, 9

3, 4, 8

3, 4

3, 4, 8

3, 4

6

3, 8

Local bus clock to data valid for LAD/LDP

Local bus clock to address valid for LAD

Output hold from local bus clock (except

LAD/LDP and LALE)

Output hold from local bus clock for

LAD/LDP

Local bus clock to output high Impedance

(except LAD/LDP and LALE)

LWE[0:1] = 00

LWE[0:1] = 11 (default)

LWE[0:1] = 00


LWE[0:1] = 00


LWE[0:1] = 00


LWE[0:1] = 00


LWE[0:1] = 00

LWE[0:1] = 11 (default) t

LBKHOV2 t

LBKHOV3 t

LBKHOX1 t

LBKHOX2 t

LBKHOZ1

—

—

0.7

1.6

0.7

1.6

—

2.6

4.1

—

2.3

3.8

2.5

4.0

—

2.8

4.2

ns ns ns ns ns

3, 8

3, 8

3, 8

3, 8

5, 9

34



Local Bus

Table 30. Local Bus General Timing Parameters—DLL Enabled (continued)

Parameter Configuration

7

Symbol

1


Local bus clock to output high impedance for

LAD/LDP

LWE[0:1] = 00

LWE[0:1] = 11 (default) t

LBKHOZ2

— 2.8

4.2

ns 5, 9

Notes:


(First two letters of functional block)(signal)(state)

(reference)(state)

for inputs and t

(First two letters of functional block)(reference)(state)(signal)(state)


LBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t

LBK high (H), in this case for clock one(1). Also, t

LBKHOX

symbolizes local bus timing (LB) for the t

LBK clock reference (K) goes clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for DLL enabled mode.

3. All signals are measured from OV

DD

/2 of the rising edge of LSYNC_IN for DLL enabled to 0.4 × OV

DD

of the signal in question for 3.3-V signaling levels.

4. Input timings are measured at the pin.

5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.

6. The value of t

LBOTOT

is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at OV

DD

/2.



Table 31

describes the general timing parameters of the local bus interface of the MPC8555E with the DLL bypassed.

Table 31. Local Bus General Timing Parameters—DLL Bypassed


7

Local bus cycle time

Internal launch/capture clock to LCLK delay

LCLK[n] skew to LCLK[m] or LSYNC_OUT

Input setup to local bus clock (except

LUPWAIT)

LUPWAIT input setup to local bus clock

Input hold from local bus clock (except

LUPWAIT)

LUPWAIT input hold from local bus clock

LALE output transition to LAD/LDP output transition (LATCH hold time)

Local bus clock to output valid (except

LAD/LDP and LALE)

Local bus clock to data valid for LAD/LDP

LWE[0:1] = 00


LWE[0:1] = 00


Symbol

1

t

LBK t

LBKHKT t t t t t t t

LBKSKEW t

LBIVKH1

LBIVKH2

LBIXKH1

LBIXKH2

LBOTOT

LBKLOV1

LBKLOV2

Min

6.0

1.8

—

5.2

5.1

–1.3

–0.8

1.5

—

—

Max

—

3.4

150

—

—

—

—

—

0.5

2.0

0.7

2.2

Unit

ns ns ps ns ns ns ns ns ns ns

Notes

2

8

7, 9

3, 4

3, 4

3, 4

3, 4

6

3

3



Local Bus

Table 31. Local Bus General Timing Parameters—DLL Bypassed (continued)


7

Local bus clock to address valid for LAD

Output hold from local bus clock (except

LAD/LDP and LALE)

LWE[0:1] = 00


LWE[0:1] = 00


Output hold from local bus clock for

LAD/LDP

LWE[0:1] = 00


Local bus clock to output high Impedance

(except LAD/LDP and LALE)

LWE[0:1] = 00


Local bus clock to output high impedance for LAD/LDP

LWE[0:1] = 00


Symbol

1

t

LBKLOV3 t t t t

LBKLOX1

LBKLOX2

LBKLOZ1

LBKLOZ2

Min

—

–2.7

–1.8

–2.7

–1.8

—

—

Max

0.8

2.3

—

—

1.0

2.4

1.0

2.4

Unit

ns ns ns ns ns

Notes

3

3

3

5

5

Notes:


(First two letters of functional block)(signal)(state) (reference)(state) for inputs and t

(First two letters of functional block)(reference)(state)(signal)(state)


LBIXKH1

symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t

LBK clock reference (K) goes high (H), in this case for clock one(1). Also, t

LBKHOX

symbolizes local bus timing (LB) for the t

LBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to LSYNC_IN for DLL enabled mode.

3. All signals are measured from OV

DD

/2 of the rising edge of local bus clock for DLL bypass mode to 0.4 × OV

DD

of the signal in question for 3.3-V signaling levels.



6. The value of t

LBOTOT

is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].

7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between complementary signals at OV

DD

/2.



Figure 16

provides the AC test load for the local bus.

Output

Z

0

= 50 Ω

R

L

= 50 Ω

OV

DD

/2

Figure 16. Local Bus C Test Load

36



Figure 17

to

Figure 22 show the local bus signals.

LSYNC_IN t

LBIXKH1 t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3] t

LBIXKH1 t

LBIVKH1

Input Signal:

LGTA

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3] t

LBKHOV1 t

LBKHOV2 t

LBKHOZ1 t

LBKHOX1 t

LBKHOZ2 t

LBKHOX2 t

LBKHOV3 t

LBKHOZ2 t

LBKHOX2

Output (Address) Signal:

LAD[0:31] t

LBOTOT

LALE

Figure 17. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)

Local Bus



Local Bus

Internal launch/capture clock t

LBKHKT

LCLK[n] t

LBIVKH1 t

LBIXKH1

Input Signals:

LAD[0:31]/LDP[0:3] t

LBIVKH2

Input Signal:

LGTA

Output Signals:

LA[27:31]/LBCTL/LBCKE/LOE/

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

Output (Data) Signals:

LAD[0:31]/LDP[0:3] t

LBKLOV1 t

LBKLOV2 t

LBIXKH2 t

LBKLOX1 t

LBKLOV3 t

LBKLOX2

Output (Address) Signal:

LAD[0:31] t

LBOTOT

LALE

Figure 18. Local Bus Signals, Nonspecial Signals Only (DLL Bypass Mode)

t

LBKLOZ1 t

LBKLOZ2

38



LSYNC_IN

T1

T3 t

LBKHOZ1 t

LBKHOV1

GPCM Mode Output Signals:

LCS[0:7]/LWE t

LBIXKH2 t

LBIVKH2

UPM Mode Input Signal:

LUPWAIT t

LBIXKH1 t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3] t

LBKHOZ1 t

LBKHOV1

UPM Mode Output Signals:

LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)

Local Bus



Local Bus

Internal launch/capture clock

T1

T3

LCLK t

LBKHKT t

LBKLOV1 t

LBKLOX1


LCS[0:7]/LWE t

LBKLOZ1 t

LBIVKH2 t

LBIXKH2


LUPWAIT t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

(DLL Bypass Mode) t

LBIXKH1


LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)

40



Local Bus

LSYNC_IN

T1

T2

T3

T4 t

LBKHOZ1 t

LBKHOV1


LCS[0:7]/LWE t

LBIXKH2 t

LBIVKH2


LUPWAIT t

LBIXKH1 t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3] t

LBKHOZ1 t

LBKHOV1


LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 or 8 (DLL Enabled)



Local Bus

Internal launch/capture clock

T1

T2

T3

T4 t

LBKHKT

LCLK t

LBKLOV1 t

LBKLOX1


LCS[0:7]/LWE t

LBKLOZ1 t

LBIVKH2


LUPWAIT t

LBIXKH2 t

LBIVKH1

Input Signals:

LAD[0:31]/LDP[0:3]

(DLL Bypass Mode) t

LBIXKH1


LCS[0:7]/LBS[0:3]/LGPL[0:5]

Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 or 8 (DLL Bypass Mode)

42



CPM

10 CPM

This section describes the DC and AC electrical specifications for the CPM of the MPC8555E.

10.1

CPM DC Electrical Characteristics

Table 32

provides the DC electrical characteristics for the CPM.

Table 32. CPM DC Electrical Characteristics

Characteristic Symbol Condition Min Max

Input high voltage

Input low voltage

V

IH

V

IL

2.0

GND

Output high voltage

Output low voltage

V

V

OH

OL

I

OH

= –8.0 mA

I

OL

= 8.0 mA

I

OH

= –2.0 mA

2.4

—

Output high voltage V

OH

2.4

Output low voltage V

OL

I

OL

= 3.2 mA —

Note:

1. This specification applies to the following pins: PA[0–31], PB[4–31], PC[0–31], and PD[4–31].

2. V

IL

(max) for the IIC interface is 0.8 V rather than the 1.5 V specified in the IIC standard

3.465

0.8

—

0.5

—

0.4

10.2

CPM AC Timing Specifications

Table 33

and

Table 34

provide the CPM input and output AC timing specifications, respectively.

NOTE: Rise/Fall Time on CPM Input Pins

It is recommended that the rise/fall time on CPM input pins should not exceed 5 ns. This should be enforced especially on clock signals. Rise time refers to signal transitions from 10% to 90% of VCC; fall time refers to transitions from 90% to 10% of VCC.

Table 33. CPM Input AC Timing Specifications

1

Unit

V

V

V

V

V

V

Notes

1

1, 2

1

1

1

1

FCC inputs—internal clock (NMSI) input setup time

FCC inputs—internal clock (NMSI) hold time

FCC inputs—external clock (NMSI) input setup time

FCC inputs—external clock (NMSI) hold time

SCC/SMC/SPI inputs—internal clock (NMSI) input setup time

SCC/SMC/SPI inputs—internal clock (NMSI) input hold time

SCC/SMC/SPI inputs—external clock (NMSI) input setup time

SCC/SMC/SPI inputs—external clock (NMSI) input hold time

TDM inputs/SI—input setup time t

FIIVKH t

FIIXKH t

FEIVKH t

FEIXKH b t

NIIVKH t

NIIXKH t

NEIVKH t

NEIXKH t

TDIVKH

6

0

2.5

2

6

0

4

2

4


Freescale Semiconductor 43 ns ns ns ns ns ns ns ns ns

CPM

Table 33. CPM Input AC Timing Specifications

1

(continued)

TDM inputs/SI—hold time

PIO inputs—input setup time

PIO inputs—input hold time

COL width high (FCC) t

TDIXKH t

PIIVKH t

PIIXKH t

FCCH

3

8

1

1.5

ns ns ns

CLK

Notes:

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin.



(reference)(state)

for inputs and t



FIIVKH symbolizes the FCC inputs internal timing (FI) with respect to the time the input signals (I) reaching the valid state (V) relative to the reference clock t

FCC

(K) going to the high (H) state or setup time. And t

TDIXKH

symbolizes the TDM timing

(TD) with respect to the time the input signals (I) reach the invalid state (X) relative to the reference clock t

FCC

(K) going to the high (H) state or hold time.

3. PIO and TIMER inputs and outputs are asynchronous to SYSCLK or any other externally visible clock. PIO/TIMER inputs are internally synchronized to the CPM internal clock. PIO/TIMER outputs should be treated as asynchronous.

Table 34. CPM Output AC Timing Specifications

1

Unit

FCC outputs—internal clock (NMSI) delay

FCC outputs—external clock (NMSI) delay

SCC/SMC/SPI outputs—internal clock (NMSI) delay

SCC/SMC/SPI outputs—external clock (NMSI) delay t

FIKHOX t

FEKHOX t

NIKHOX t

NEKHOX

1

2

0.5

2

5.5

8

10

8 ns ns ns ns

TDM outputs/SI delay

PIO outputs delay t

TDKHOX t

PIKHOX

2.5

1

11

11 ns ns

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t


for inputs and t



FIKHOX

symbolizes the FCC inputs internal timing (FI) for the time t

FCC

memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).

Figure 23

provides the AC test load for the CPM.

Output

Z

0

= 50 Ω

R

L

= 50 Ω

OV

DD

/2

Figure 23. CPM AC Test Load

44



CPM

Figure 24

through

Figure 30

represent the AC timing from Table 33

and

Table 34

. Note that although the specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.

Figure 24

shows the FCC internal clock.

BRG_OUT t

FIIXKH t

FIIVKH

FCC Input Signals t

FIKHOX

FCC Output Signals

(When GFMR TCI = 0) t

FIKHOX

FCC Output Signals

(When GFMR TCI = 1)

Figure 24. FCC Internal AC Timing Clock Diagram

Figure 25

shows the FCC external clock.

Serial CLKIN t

FEIXKH t

FEIVKH

FCC Input Signals t

FEKHOX

FCC Output Signals

(When GFMR TCI = 0) t

FEKHOX

FCC Output Signals

(When GFMR TCI = 1)

Figure 25. FCC External AC Timing Clock Diagram

Figure 26

shows Ethernet collision timing on FCCs.

COL

(Input) t

FCCH

Figure 26. Ethernet Collision AC Timing Diagram (FCC)



CPM

Figure 27

shows the SCC/SMC/SPI external clock.

Serial CLKIN t

NEIXKH t

NEIVKH

Input Signals:

SCC/SMC/SPI

(See Note) t

NEKHOX

Output Signals:

SCC/SMC/SPI

(See Note)

Note:

The clock edge is selectable on SCC and SPI.

Figure 27. SCC/SMC/SPI AC Timing External Clock Diagram

Figure 28

shows the SCC/SMC/SPI internal clock.

BRG_OUT t

NIIXKH t

NIIVKH

Input Signals:

SCC/SMC/SPI

(See Note) t

NIKHOX

Output Signals:

SCC/SMC/SPI

(See Note)

Note:

The clock edge is selectable on SCC and SPI.

Figure 28. SCC/SMC/SPI AC Timing Internal Clock Diagram

NOTE

1

SPI AC timings are internal mode when it is master because SPICLK is an output, and external mode when it is slave.

2

SPI AC timings refer always to SPICLK

.

46



CPM

Figure 29

shows TDM input and output signals.

Serial CLKIN t

TDIXKH t

TDIVKH

TDM Input Signals t

TDKHOX

TDM Output Signals

Note:

1.

There are 4 possible TDM timing conditions:

Input sampled on the rising edge and output driven on the rising edge (shown).

2.

3.

4.

Input sampled on the rising edge and output driven on the falling edge.

Input sampled on the falling edge and output driven on the falling edge.

Input sampled on the falling edge and output driven on the rising edge.

Figure 29. TDM Signal AC Timing Diagram

Sys clk t

PIIXKH t

PIIVKH

PIO inputs t

PIKHOX

PIO outputs

Figure 30. PIO Signal Diagram

10.3

CPM I2C AC Specification

Table 35. I2C Timing

Characteristic

SCL clock frequency (slave)

SCL clock frequency (master)

Bus free time between transmissions

Low period of SCL

High period of SCL

Start condition setup time

2

Start condition hold time

2

Data hold time

2

Data setup time

2

SDA/SCL rise time

Expression

f

SCL f

SCL t

SDHDL t

SCLCH t

SCHCL t

SCHDL t

SDLCL t

SCLDX t

SDVCH t

SRISE

Min

0

All Frequencies

BRGCLK/16512

Max

F

MAX

(1)

BRGCLK/48

1/(2.2 * f

SCL

)

1/(2.2 * f

SCL

)

1/(2.2 * f

SCL

)

2/(divider * f

SCL

3/(divider * f

SCL

)

2/(divider * f

SCL

)

3/(divider * f

SCL

)

-

-

-

-

-

-

-

1/(10 * f

SCL

)



Unit

Hz

Hz s s s s s s s s

CPM

Table 35. I2C Timing (continued)

All Frequencies

Characteristic Expression Unit

Min Max

SDA/SCL fall time

Stop condition setup time t

SFALL t

SCHDH

1/(33 * f

SCL

)

2/(divider * f

SCL

) s s

Notes:

1. F

MAX

= BRGCLK/(min_divider*prescale. Where prescaler=25-I2MODE[PDIV]; and min_divider=12 if digital filter disabled and 18 if enabled.

Example #1: if I2MODE[PDIV]=11 (prescaler=4) and I2MODE[FLT]=0 (digital filter disabled) then FMAX=BRGCLK/48

Example #2: if I2MODE[PDIV]=00 (prescaler=32) and I2MODE[FLT]=1 (digital filter enabled) then FMAX=BRGCLK/576

2. divider = f

SCL

/prescaler.

In master mode: divider=BRGCLK/(f

SCL

*prescaler)=2*(I2BRG[DIV]+3)

In slave mode: divider=BRGCLK/(f

SCL

*prescaler)

SDA t

SDHDL t

SCHDL t

SCLCH

SCL t

SCLDX t

SCHCL t

SDLCL t

SRISE t

SFALL

Figure 31. CPM I2C Bus Timing Diagram

t

SDVCH t

SCHDH

48



CPM

The following two tables are examples of I2C AC parameters at I2C clock value of 100k and 400k respectively.

Table 36. CPM I2C Timing (f

SCL

=100 kHz)

Characteristic




Low period of SCL

High period of SCL



Data hold time

Data setup time

SDA/SCL rise time

SDA/SCL fall time (master)

Stop condition setup time

Expression

f

SCL f

SCL t

SDHDL t

SCLCH t

SCHCL t

SCHDL t

SDLCL t

SCLDX t

SDVCH t

SRISE t

SFALL t

SCHDH

Frequency = 100 kHz

Min

3

2

4

2

—

—

4.7

4.7

3

—

—

2

Max

—

—

—

—

100

100

—

—

—

1

303

—

Unit

µs

µs

µs

µs kHz kHz

µs

µs

µs

µs ns

µs

Characteristic




Low period of SCL

High period of SCL



Data hold time

Data setup time

SDA/SCL rise time

SDA/SCL fall time

Stop condition setup time

Table 37. CPM I2C Timing (f

SCL

=400 kHz)

Expression

f

SCL f

SCL t

SDHDL t

SCLCH t

SCHCL t

SCHDL t

SDLCL t

SCLDX t

SDVCH t

SRISE t

SFALL t

SCHDH

Frequency = 400 kHz

Min

1

420

630

420

—

—

1.2

1.2

630

—

—

420

Max

—

—

—

—

400

400

—

—

—

250

75

—

Unit

kHz kHz

µs

µs ns ns ns ns

µs ns ns ns



JTAG

11 JTAG

This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the

MPC8555E.

Table 38

provides the JTAG AC timing specifications as defined in Figure 33 through

Figure 36

.

Table 38. JTAG AC Timing Specifications (Independent of SYSCLK)

1

At recommended operating conditions (see Table 2 ).


2


JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock pulse width measured at 1.4 V

JTAG external clock rise and fall times

TRST assert time f

JTG t

JTG t

JTKHKL t

JTGR

& t

JTGF t

TRST

0

30

15

0

25

33.3

—

—

2

—

MHz ns ns ns ns 3

Input setup times: ns

Boundary-scan data

TMS, TDI t

JTDVKH t

JTIVKH

4

0

—

—

4

Input hold times: ns

Boundary-scan data

TMS, TDI t

JTDXKH t

JTIXKH

20

25

—

—

4

Valid times: ns

Boundary-scan data

TDO t

JTKLDV t

JTKLOV

4

4

20

25

5

Output hold times: ns

Boundary-scan data

TDO t

JTKLDX t

JTKLOX

—

—

—

—

5

JTAG external clock to output high impedance:

Boundary-scan data

TDO t

JTKLDZ t

JTKLOZ

3

3

19

9 ns

5, 6

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t

TCLK

to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see

Figure 32

). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.



(reference)(state)

for inputs and t



JTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t

JTG


JTDXKH

symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the t

JTG

clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to t

TCLK

.

5. Non-JTAG signal output timing with respect to t

TCLK

.


50



Figure 32

provides the AC test load for TDO and the boundary-scan outputs of the MPC8555E.

Output

Z

0

= 50 Ω

R

L

= 50 Ω

OV

DD

/2

Figure 32. AC Test Load for the JTAG Interface

Figure 33

provides the JTAG clock input timing diagram.

JTAG

External Clock

VM VM VM t

JTKHKL t

JTG t

JTGR

VM = Midpoint Voltage (OVDD/2)

Figure 33. JTAG Clock Input Timing Diagram

Figure 34

provides the TRST timing diagram.

t

JTGF

TRST VM VM t

TRST


Figure 34. TRST Timing Diagram

Figure 35

provides the boundary-scan timing diagram.

JTAG

External Clock

Boundary

Data Inputs

Boundary

Data Outputs

Boundary

Data Outputs

VM VM t

JTDVKH

Input

Data Valid t

JTKLDV t

JTKLDX

Output Data Valid t

JTKLDZ

Output Data Valid


Figure 35. Boundary-Scan Timing Diagram

t

JTDXKH

JTAG



I2C

Figure 36

provides the test access port timing diagram.

JTAG

External Clock

VM t

JTIVKH

VM t

JTIXKH

TDI, TMS

Input

Data Valid t

JTKLOV t

JTKLOX

TDO Output Data Valid

TDO t

JTKLOZ

Output Data Valid


Figure 36. Test Access Port Timing Diagram

12 I

2

C

This section describes the DC and AC electrical characteristics for the I

2

C interface of the MPC8555E.

12.1

I

2

C DC Electrical Characteristics

Table 39

provides the DC electrical characteristics for the I

2


Table 39. I

2

C DC Electrical Characteristics

At recommended operating conditions with OV

DD

of 3.3 V ± 5%.

Parameter Symbol Min Max Unit Notes

Input high voltage level

Input low voltage level

Low level output voltage

Output fall time from V

IH

(min) to V

IL

(max) with a bus capacitance from 10 to 400 pF t

V

IH

V

IL

V

OL

I2KLKV

0.7 × OV

–0.3

0

DD

20 + 0.1 × C

B

OV

DD

+ 0.3

0.3 × OV

0.2 × OV

250

DD

DD

V

V

V ns

1

2

Pulse width of spikes which must be suppressed by the input filter t

I2KHKL

0 50 ns 3

Input current each I/O pin (input voltage is between 0.1 ×

OV

DD

and 0.9 × OV

DD

(max)

Capacitance for each I/O pin

I

I

–10 10

µA

4

C

I

— 10 pF

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. C

B

= capacitance of one bus line in pF.

3. Refer to the MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual for information on the digital filter used.

4. I/O pins obstruct the SDA and SCL lines if OV

DD

is switched off.

52



I2C

12.2

I

2

C AC Electrical Specifications

Table 40

provides the AC timing parameters for the I

2


Table 40. I

2

C AC Electrical Specifications

All values refer to V

IH

(min) and V

IL

(max) levels (see

Table 39 ).


1

Min Max Unit

SCL clock frequency

Low period of the SCL clock

High period of the SCL clock

Setup time for a repeated START condition

Hold time (repeated) START condition (after this period, the first clock pulse is generated) f

I2C t

I2CL

6 t

I2CH

6 t

I2SVKH

6 t

I2SXKL

6

0

1.3

0.6

0.6

0.6

400

—

—

—

— kHz

µs

µs

µs

µs

Data setup time

Data hold time: t

I2DVKH

6 t

I2DXKL

100 — ns

µs

CBUS compatible masters

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Set-up time for STOP condition

Bus free time between a STOP and START condition

I

2

C bus devices

Noise margin at the LOW level for each connected device (including hysteresis)

Noise margin at the HIGH level for each connected device (including hysteresis) t

I2CR t

I2CF t

I2PVKH t

I2KHDX

V

NL

V

NH

—

0

2

20 + 0.1 C b

4

20 + 0.1 C b

4

0.6

1.3

0.1 × OV

0.2 × OV

DD

DD

—

0.9

3

300

300

—

—

—

— ns ns

µs

µs

V

V

Notes:

1. The symbols used for timing specifications herein follow the pattern of t for inputs and t




I2DVKH

symbolizes I

2

C timing

(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t

I2C


I2SXKL

symbolizes I

2

C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the t

I2C

clock reference (K) going to the low (L) state or hold time. Also, t

I2PVKH symbolizes I

2

C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t

I2C

clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. MPC8555E provides a hold time of at least 300 ns for the SDA signal (referred to the V

IHmin

of the SCL signal) to bridge the undefined region of the falling edge of SCL.

3. The maximum t

I2DVKH

has only to be met if the device does not stretch the LOW period (t

I2CL

) of the SCL signal.

4. C

B

= capacitance of one bus line in pF.




PCI

Figure 16

provides the AC test load for the I

2

C.

Output

Z

0

= 50 Ω

R

L

= 50 Ω

OV

DD

/2

Figure 37. I

2

C AC Test Load

Figure 38

shows the AC timing diagram for the I

2

C bus.

SDA t

I2CF t

I2CL t

I2DVKH t

I2SXKL t

I2KHKL t

I2CR t

I2CF

SCL

S t

I2SXKL t

I2CH t

I2SVKH t

I2DXKL

Sr

Figure 38. I

2

C Bus AC Timing Diagram

t

I2PVKH

P S

13 PCI

This section describes the DC and AC electrical specifications for the PCI bus of the MPC8555E.

13.1

PCI DC Electrical Characteristics

Table 41

provides the DC electrical characteristics for the PCI interface of the MPC8555E.

Table 41. PCI DC Electrical Characteristics

1




Input current

V

IH

V

IL

I

IN

V

OH

V

OUT

V

IN

2

≥ V

V

OUT

OH

(min) or

≤ V

OL

(max)

= 0 V or V

IN

= V

DD

2

–0.3

—

OV

DD

+ 0.3

0.8

±5

High-level output voltage


OL

OV

DD

= min,

I

OH

= –100 µA

OV

DD

= min,

I

OL

= 100 µA

OV

DD

– 0.2

—

—

0.2

Notes:

1. Ranges listed do not meet the full range of the DC specifications of the

PCI 2.2 Local Bus Specifications.


IN


IN


Table 1

and

Table 2

.

Unit

V

V

µA

V

V

54



PCI

13.2

PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus of the MPC8555E. Note that the

SYSCLK signal is used as the PCI input clock.

Table 42

provides the PCI AC timing specifications at 66

MHz.

NOTE

PCI Clock can be PCI1_CLK or SYSCLK based on POR config input.

NOTE

The input setup time does not meet the PCI specification.

Table 42. PCI AC Timing Specifications at 66 MHz


1


Clock to output valid

Output hold from Clock

Clock to output high impedance t

PCKHOV t

PCKHOX t

PCKHOZ

—

2.0

—

6.0

—

14 ns ns ns

2, 3

2, 9

2, 3, 10

Input setup to Clock

Input hold from Clock

REQ64 to HRESET

9 setup time

HRESET to REQ64 hold time t

PCIVKH t

PCIXKH t

PCRVRH t

PCRHRX

3.3

0

10 × t

0

SYS

—

—

—

50 ns ns clocks ns

2, 4, 9

2, 4, 9

5, 6, 10

6, 10

HRESET high to first FRAME assertion t

PCRHFV

10 — clocks 7, 10

Notes:

1. Note that the symbols used for timing specifications herein follow the pattern of t


(reference)(state)

for inputs and t



PCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the SYSCLK clock, t

SYS

, reference (K) going to the high (H) state or setup time. Also, t

PCRHFV

symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.



5. The timing parameter t

SYS

indicates the minimum and maximum CLK cycle times for the various specified frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values see

Section 15, “Clocking .”

6. The setup and hold time is with respect to the rising edge of HRESET.

7. The timing parameter t

PCRHFV

Specifications.

is a minimum of 10 clocks rather than the minimum of 5 clocks in the

PCI 2.2 Local Bus

8. The reset assertion timing requirement for HRESET is 100 µs.


10.Guaranteed by design.

Figure 16

provides the AC test load for PCI.

Output

Z

0

= 50 Ω

R

L

= 50 Ω

OV

DD

/2

Figure 39. PCI AC Test Load



Package and Pin Listings

Figure 40

shows the PCI input AC timing conditions.

CLK t

PCIVKH t

PCIXKH

Input

Figure 40. PCI Input AC Timing Measurement Conditions

Figure 41

shows the PCI output AC timing conditions.

CLK t

PCKHOV

Output Delay t

PCKHOZ

High-Impedance

Output

Figure 41. PCI Output AC Timing Measurement Condition

14 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions.

14.1

Package Parameters for the MPC8555E FC-PBGA

The package parameters are as provided in the following list. The package type is 29 mm × 29 mm, 783 flip chip plastic ball grid array (FC-PBGA).

Die size

Package outline

8.7 mm

29 mm

× 9.3 mm × 0.75 mm

× 29 mm

Interconnects

Pitch

783

1 mm

Minimum module height 3.07 mm

Maximum module height 3.75 mm

Solder Balls 62 Sn/36 Pb/2 Ag

Ball diameter (typical) 0.5 mm

56




14.2

Mechanical Dimensions of the FC-PBGA

Figure 42

the mechanical dimensions and bottom surface nomenclature of the MPC8555E 783 FC-PBGA package.

Figure 42. Mechanical Dimensions and Bottom Surface Nomenclature of the FC-PBGA

Notes:

1.

All dimensions are in millimeters.

2.

Dimensions and tolerances per ASME Y14.5M-1994.

3.

Maximum solder ball diameter measured parallel to datum A.

4.

Datum A, the seating plane, is defined by the spherical crowns of the solder balls.

5.

Capacitors may not be present on all devices.

6.

Caution must be taken not to short capacitors or exposed metal capacitor pads on package top.

7.

The socket lid must always be oriented to A1.




14.3

Pinout Listings

Table 43

provides the pin-out listing for the MPC8555E, 783 FC-PBGA package.

Table 43. MPC8555E Pinout Listing

Signal Package Pin Number Pin Type

PCI1 and PCI2 (one 64-bit or two 32-bit)

PCI1_AD[63:32],

PCI2_AD[31:0]

PCI1_AD[31:0]

PCI_C_BE64[7:4]

PCI2_C_BE[3:0]

PCI_C_BE64[3:0]

PCI1_C_BE[3:0]

PCI1_PAR

PCI1_PAR64/PCI2_PAR

PCI1_FRAME

PCI1_TRDY

PCI1_IRDY

PCI1_STOP

PCI1_DEVSEL

PCI1_IDSEL

PCI1_REQ64/PCI2_FRAME

PCI1_ACK64/PCI2_DEVSEL

PCI1_PERR

PCI1_SERR

PCI1_REQ[0]

PCI1_REQ[1:4]

PCI1_GNT[0]

PCI1_GNT[1:4]

PCI1_CLK

PCI2_CLK

PCI2_GNT[0]

AA14, AB14, AC14, AD14, AE14, AF14, AG14, AH14,

V15, W15, Y15, AA15, AB15, AC15, AD15, AG15,

AH15, V16, W16, AB16, AC16, AD16, AE16, AF16,

V17, W17, Y17, AA17, AB17, AE17, AF17, AF18

AH6, AD7, AE7, AH7, AB8, AC8, AF8, AG8, AD9,

AE9, AF9, AG9, AH9, W10, Y10, AA10, AE11, AF11,

AG11, AH11, V12, W12, Y12, AB12, AD12, AE12,

AG12, AH12, V13, Y13, AB13, AC13

AG13, AH13, V14, W14

AH8, AB10, AD11, AC12

AA11

Y14

AC10

AG10

AD10

V11

AH10

AA9

AE13

AD13

W11

Y11

AF5

AF3, AE4, AG4, AE5

AE6

AG5, AH5, AF6, AG6

AH25

AH27

AC18

I/O

I/O

I/O

I/O

I/O

I

I/O

O

I/O

I/O

I/O

I/O

I

I

I/O

I/O

I/O

I/O

I

I/O

I/O

I/O

I/O

Power

Supply

Notes

OV

DD

OV

DD

17

17

17

17

—

—

—

5, 9

5, 10

2

2

2, 4

—

—

—

2

—

2

2

2

2

—

—

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

58



MECC[0:7]

MDM[0:8]

MDQS[0:8]

MBA[0:1]

MA[0:14]

MWE

MRAS

MCAS

MCS[0:3]

MCKE[0:1]

MCK[0:5]

MCK[0:5]

MSYNC_IN

MSYNC_OUT

LA[27]

Signal

PCI2_GNT[1:4]

PCI2_IDSEL

PCI2_IRDY

PCI2_PERR

PCI2_REQ[0]

PCI2_REQ[1:4]

PCI2_SERR

PCI2_STOP

PCI2_TRDY

MDQ[0:63]


Table 43. MPC8555E Pinout Listing (continued)

Package Pin Number

AD18, AE18, AE19, AD19

AC22

AD20

AC20

AD21

AE21, AD22, AE22, AC23

AE20

AC21

AC19

DDR SDRAM Memory Interface

M26, L27, L22, K24, M24, M23, K27, K26, K22, J28,

F26, E27, J26, J23, H26, G26, C26, E25, C24, E23,

D26, C25, A24, D23, B23, F22, J21, G21, G22, D22,

H21, E21, N18, J18, D18, L17, M18, L18, C18, A18,

K17, K16, C16, B16, G17, L16, A16, L15, G15, E15,

C14, K13, C15, D15, E14, D14, D13, E13, D12, A11,

F13, H13, A13, B12

N20, M20, L19, E19, C21, A21, G19, A19

L24, H28, F24, L21, E18, E16, G14, B13, M19

L26, J25, D25, A22, H18, F16, F14, C13, C20

B18, B19

N19, B21, F21, K21, M21, C23, A23, B24, H23, G24,

K19, B25, D27, J14, J13

D17

F17

J16

H16, G16, J15, H15

E26, E28

J20, H25, A15, D20, F28, K14

F20, G27, B15, E20, F27, L14

M28

N28

Local Bus Controller Interface

U18

Pin Type

I/O

I

I/O

I/O

I/O

O

I

I/O

I/O

I/O

O

I/O

O

I/O

O

O

O

I

O

O

O

O

O

O

O

Power

Supply

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

Notes

—

—

2,4

2

2

5, 9

—

2

2

GV

DD

OV

DD

—

5, 9

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

GV

DD

11

—

—

22

22

—

—

—

—

—

—

—

—

—





Signal Package Pin Number

LA[28:31]

LAD[0:31]

LALE

LBCTL

LCKE

LCLK[0:2]

LCS[0:4]

LCS5/DMA_DREQ2

LCS6/DMA_DACK2

LCS7/DMA_DDONE2

T18, T19, T20, T21

AD26, AD27, AD28, AC26, AC27, AC28, AA22,

AA23, AA26, Y21, Y22, Y26, W20, W22, W26, V19,

T22, R24, R23, R22, R21, R18, P26, P25, P20, P19,

P18, N22, N23, N24, N25, N26

V21

V20

U23

U27, U28, V18

Y27, Y28, W27, W28, R27

R28

P27

P28

LDP[0:3]

LGPL0/LSDA10

AA27, AA28, T26, P21

U19

LGPL1/LSDWE U22

LGPL2/LOE/LSDRAS V28

LGPL3/LSDCAS V27

LGPL4/LGTA/LUPWAIT/

LPBSE

V23

LGPL5

LSYNC_IN

V22

T27

LSYNC_OUT

LWE[0:1]/LSDDQM[0:1]/

LBS[0:1]

LWE[2:3]/LSDDQM[2:3]/

LBS[2:3]

T28

AB28, AB27

T23, P24

DMA_DREQ[0:1]

DMA_DACK[0:1]

DMA_DDONE[0:1]

MCP

UDE

DMA

H5, G4

H6, G5

H7, G6

Programmable Interrupt Controller

AG17

AG16

Pin Type

O

I/O

O

O

O

O

I

I

O

O

I

I

I/O

O

O

O

O

I/O

O

I/O

O

O

O

O

O

O

Power

Supply

OV

DD

OV

DD

Notes

5, 7, 9

—

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

—

—

—

—

—

—

5, 9

5, 9

5, 8, 9

5, 9

21

1

1

—

1

5, 8, 9

9

—

—

5, 9

—

—

1, 5, 9

1, 5, 9

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

60



Signal

IRQ[0:7]

IRQ8

IRQ9/DMA_DREQ3

IRQ10/DMA_DACK3

IRQ11/DMA_DDONE3

IRQ_OUT

EC_MDC

EC_MDIO

EC_GTX_CLK125

TSEC1_TXD[7:4]

TSEC1_TXD[3:0]

TSEC1_TX_EN

TSEC1_TX_ER

TSEC1_TX_CLK

TSEC1_GTX_CLK

TSEC1_CRS

TSEC1_COL

TSEC1_RXD[7:0]

TSEC1_RX_DV

TSEC1_RX_ER

TSEC1_RX_CLK

TSEC2_TXD[7:4]

TSEC2_TXD[3:0]

TSEC2_TX_EN

TSEC2_TX_ER

TSEC2_TX_CLK

TSEC2_GTX_CLK



Package Pin Number Pin Type

AA18, Y18, AB18, AG24, AA21, Y19, AA19, AG25

AB20

Y20

AF26

AH24

AB21

Ethernet Management Interface

F1

E1

Gigabit Reference Clock

E2

O

I/O

I

Three-Speed Ethernet Controller (Gigabit Ethernet 1)

A6, F7, D7, C7

B7, A7, G8, E8

C8

B8

C6

B6

C3

G7

D4, B4, D3, D5, B5, A5, F6, E6

D2

E5

D6

I

I

I

O

O

O

O

O

I

I

I

I

Three-Speed Ethernet Controller (Gigabit Ethernet 2)

B10, A10, J10, K11

J11, H11, G11, E11

B11

D11

D10

C10

O

O

O

O

I

O

I

I/O

I

I

I/O

O

Power

Supply

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

Notes

1

1

—

9

1

2, 4

OV

DD

OV

DD

LV

DD

LV

DD

LV

DD

LV

DD

LV

DD

LV

DD

LV

DD

LV

DD

LV

DD

LV

DD

LV

DD

LV

DD

LV

DD

5, 9

—

—

LV

DD

LV

DD

LV

DD

LV

DD

LV

DD

LV

DD

—

5, 9, 18

11

—

—

—

—

—

—

—

—

9, 18

11

—

—

—

—

—





Signal Package Pin Number

TSEC2_CRS

TSEC2_COL

TSEC2_RXD[7:0]

TSEC2_RX_DV

TSEC2_RX_ER

TSEC2_RX_CLK

UART_CTS[0,1]

UART_RTS[0,1]

UART_SIN[0,1]

UART_SOUT[0,1]

D9

F8

F9, E9, C9, B9, A9, H9, G10, F10

H8

A8

E10

DUART

Y2, Y3

Y1, AD1

P11, AD5

N6, AD2

I

2

C interface

IIC_SDA

IIC_SCL

HRESET

HRESET_REQ

SRESET

CKSTP_IN

CKSTP_OUT

TRIG_IN

TRIG_OUT/READY

MSRCID[0:1]

MSRCID[2:3]

MSRCID4

MDVAL

N12

G2

J9, G3

F3, F5

F2

F4

SYSCLK AH21

RTC AB23

CLK_OUT AF22

Clock

AH22

AH23

System Control

AH16

AG20

AF20

M11

G1

Debug

Pin Type

I

I

I

I

I

I

I

O

I

O

I/O

I/O

I

I

I

O

O

I

I

O

O

O

I

O

O

O

Power

Supply

LV

DD

LV

DD

LV

DD

LV

DD

LV

DD

LV

DD

Notes

—

—

—

—

—

—

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

4, 19

4, 19

—

18

—

—

2, 4

OV

DD

OV

DD

OV

DD

—

—

—

—

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

—

6, 9, 18

5, 6, 9

6

6

6

—

—

—

62



Signal

THERM0

THERM1

ASLEEP

AV

DD

1

AV

DD

2

AV

DD

3

AV

DD

4

AV

DD

5

TCK

TDI

TDO

TMS

TRST

LSSD_MODE

L1_TSTCLK

L2_TSTCLK

TEST_SEL0

TEST_SEL1



Pin Type Package Pin Number

AF21

AG21

AF19

AF23

AG23

JTAG

DFT

AG19

AB22

AG22

AH20

AG26

Thermal Management

AG2

AH3

Power Management

AG18

Power and Ground Signals

AH19

—

—

—

AH18

AH17

AF28

AE28

O

I

I

I

I

I

I

I

I

I

Power

Supply

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

OV

DD

—

—

—

Power for e500

PLL (1.2 V)

Power for CCB

PLL (1.2 V)

Power for CPM

PLL (1.2 V)

Power for PCI1

PLL (1.2 V)

Power for PCI2

PLL (1.2 V)

AV

DD

1

AV

AV

AV

AV

DD

DD

DD

DD

2

3

4

5

Notes

20

20

20

3

3

—

12

11

12

12

14

14

9, 18

—

—

—

—

—




GND

GV

DD

LV

DD

MV

REF

No Connects

OV

DD

RESERVED

SENSEVDD

SENSEVSS

V

DD

PA[8:31]

Signal


Package Pin Number Pin Type

A12, A17, B3, B14, B20, B26, B27, C2, C4, C11,C17,

C19, C22, C27, D8, E3, E12, E24, F11, F18, F23, G9,

G12, G25, H4, H12, H14, H17, H20, H22, H27, J19,

J24, K5, K9, K18, K23, K28, L6, L20, L25, M4, M12,

M14, M16, M22, M27, N2, N13, N15, N17, P12, P14,

P16, P23, R13, R15, R17, R20, R26, T3, T8, T10,

T12, T14, T16, U6, U13, U15, U16, U17, U21, V7,

V10, V26, W5, W18, W23, Y8, Y16, AA6, AA13, AB4,

AB11, AB19, AC6, AC9, AD3, AD8, AD17, AF2, AF4,

AF10, AF13, AF15, AF27, AG3, AG7

—

A14, A20, A25, A26, A27, A28, B17, B22, B28, C12,

C28, D16, D19, D21, D24, D28, E17, E22, F12, F15,

F19, F25, G13, G18, G20, G23, G28, H19, H24, J12,

J17, J22, J27, K15, K20, K25, L13, L23, L28, M25,

N21

Power for DDR

DRAM I/O

Voltage

(2.5 V)

A4, C5, E7, H10

N27

AA24, AA25, AA3, AA4, AA7 AA8, AB24, AB25,

AC24, AC25, AD23, AD24, AD25, AE23, AE24,

AE25, AE26, AE27, AF24, AF25, H1, H2, J1, J2, J3,

J4, J5, J6, M1, N1, N10, N11, N4, N5, N7, N8, N9,

P10, P8, P9, R10, R11, T24, T25, U24, U25, V24,

V25, W24, W25, W9, Y24, Y25, Y5, Y6, Y9, AH26,

AH28, AG28, AH1, AG1, AH2, B1, B2, A2, A3

Reference

Voltage;

Three-Speed

Ethernet I/O

(2.5 V, 3.3 V)

Reference

Voltage Signal;

DDR

—

D1, E4, H3, K4, K10, L7, M5, N3, P22, R19, R25, T2,

T7, U5, U20, U26, V8, W4, W13, W19, W21, Y7, Y23,

AA5, AA12, AA16, AA20, AB7, AB9, AB26, AC5,

AC11, AC17, AD4, AE1, AE8, AE10, AE15, AF7,

AF12, AG27, AH4

PCI, 10/100

Ethernet, and other Standard

(3.3 V)

C1, T11, U11, AF1

L12

—

Power for Core

(1.2 V)

— K12

M13, M15, M17, N14, N16, P13, P15, P17, R12, R14,

R16, T13, T15, T17, U12, U14

Power for Core

(1.2 V)

CPM

J7, J8, K8, K7, K6, K3, K2, K1, L1, L2, L3, L4, L5, L8,

L9, L10, L11, M10, M9, M8, M7, M6, M3, M2

I/0

Power

Supply

—

GV

LV

MV

—

OV

V

V

DD

DD

REF

—

DD

—

DD

OV

DD

DD

Notes

—

—

—

—

16

—

—

15

13

13

—

64





Signal Package Pin Number Pin Type

Power

Supply

Notes

PB[18:31]

PC[0, 1, 4–29]

PD[7, 14–25, 29–31]

P7, P6, P5, P4, P3, P2, P1, R1, R2, R3, R4, R5, R6,

R7

R8, R9, T9, T6, T5, T4, T1, U1, U2, U3, U4, U7, U8,

U9, U10, V9, V6, V5, V4, V3, V2, V1, W1, W2, W3,

W6, W7, W8

Y4, AA2, AA1, AB1, AB2, AB3, AB5, AB6, AC7, AC4,

AC3, AC2, AC1, AD6, AE3, AE2

I/0

I/0

I/0

OV

OV

OV

DD

DD

DD

—

—

—

Notes:

1. All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the

Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as

DMA_REQ2.

2. Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OV

DD

.

3. TEST_SEL0 must be pulled-high, TEST_SEL1 must be tied to ground.

4. This pin is an open drain signal.

5. This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the MPC8555E is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. If an external device connected to this pin might pull it down during reset, then a pull-up or active driver is needed if the signal is intended to be high during reset.

6. Treat these pins as no connects (NC) unless using debug address functionality.

7. The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down resistors. See

Section 15.2, “Platform/System PLL Ratio .”

8. The value of LALE and LGPL2 at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ pull-up or pull-down resistors. See the

Section 15.3, “e500 Core PLL Ratio .”

9. Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or because it has other manufacturing test functions. This pin therefore is described as an I/O for boundary scan.

10. This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit

PCI device. Refer to the PCI Specification.

11. This output is actively driven during reset rather than being three-stated during reset.

12. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

13. These pins are connected to the V

DD

/GND planes internally and may be used by the core power supply to improve tracking and regulation.

14. Internal thermally sensitive resistor.

15. No connections should be made to these pins.

16. These pins are not connected for any functional use.

17. PCI specifications recommend that a weak pull-up resistor (2–10 kΩ) be placed on the higher order pins to OV

DD when using 64-bit buffer mode (pins PCI_AD[63:32] and PCI2_C_BE[7:4]).

18. If this pin is connected to a device that pulls down during reset, an external pull-up is required to that is strong enough to pull this signal to a logic 1 during reset.

19. Recommend a pull-up resistor (~1 kΩ) be placed on this pin to OV

DD

.

20. These are test signals for factory use only and must be pulled up (100Ω το 1kΩ) to OV

DD for normal machine operation.

21. If this signal is used as both an input and an output, a weak pull-up (~10kΩ) is required on this pin.

22. MSYNC_IN and MSYNC_OUT should be connected together for proper operation.



Clocking

15 Clocking

This section describes the PLL configuration of the MPC8555E. Note that the platform clock is identical to the CCB clock.

15.1

Clock Ranges

Table 44

provides the clocking specifications for the processor core and

Table 44

provides the clocking specifications for the memory bus.

Table 44. Processor Core Clocking Specifications

Maximum Processor Core Frequency

600 MHz 667 MHz 833 MHz Characteristic 533 MHz 1000 MHz Unit Notes

Min Max Min Max Min Max Min Max Min Max

e500 core processor frequency

400 533 400 600 400 667 400 833 400 1000 MHz 1, 2, 3

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating frequencies. Refer to

Section 15.2, “Platform/System PLL Ratio

,” and Section 15.3, “e500 Core PLL Ratio

,” for ratio settings.

2.)The minimum e500 core frequency is based on the minimum platform frequency of 200 MHz.

3. 1000 MHz frequency supports only a 1.3 V core.

Table 45. Memory Bus Clocking Specifications

Characteristic

Maximum Processor Core

Frequency

533, 600, 667, 883, 1000 MHz

Unit Notes

Min Max

Memory bus frequency 100 166 MHz 1, 2, 3

Notes:

1. Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating frequencies. Refer to

Section 15.2, “Platform/System PLL

Ratio ,” and

Section 15.3, “e500 Core PLL Ratio ,” for ratio settings.

2. The memory bus speed is half of the DDR data rate, hence, half of the platform clock frequency.

3. 1000 MHz frequency supports only a 1.3 V core.

66



Clocking

15.2

Platform/System PLL Ratio

The platform clock is the clock that drives the L2 cache, the DDR SDRAM data rate, and the e500 core complex bus (CCB), and is also called the CCB clock. The values are determined by the binary value on

LA[28:31] at power up, as shown in

Table 46 .

There is no default for this PLL ratio; these signals must be pulled to the desired values.

For specifications on the PCI_CLK, refer to the PCI 2.2 Specification.

Table 46. CCB Clock Ratio

Binary Value of

LA[28:31] Signals

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

Ratio Description

16:1 ratio CCB clock: SYSCLK (PCI bus)

Reserved






Reserved




Reserved


Reserved

Reserved

Reserved



Clocking

15.3

e500 Core PLL Ratio

Table 47

describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This ratio is determined by the binary value of LALE and LGPL2 at power up, as shown in

Table 47 .

Table 47. e500 Core to CCB Ratio

Binary Value of LALE, LGPL2 Signals Ratio Description

00

01

10

11

2:1 e500 core:CCB

5:2 e500 core:CCB

3:1 e500 core:CCB

7:2 e500 core:CCB

9

10

6

8

12

16

4

5

2

3

15.4

Frequency Options

Table 48

shows the expected frequency values for the platform frequency when using a CCB to SYSCLK ratio in comparison to the memory bus speed.

Table 48. Frequency Options with Respect to Memory Bus Speeds

CCB to SYSCLK

Ratio

SYSCLK (MHz)

17

200

267

25 33 42 67 83 100 111 133

Platform/CCB Frequency (MHz)

200

267 333

200 222 267

250 300 333

333

200

200

267

225 300

208

250

333

250 333

300

68



Thermal

16 Thermal

This section describes the thermal specifications of the MPC8555E.

16.1

Thermal Characteristics

Table 49

provides the package thermal characteristics for the MPC8555E.

Table 49. Package Thermal Characteristics

Characteristic Symbol Value Unit Notes

Junction-to-ambient Natural Convection on four layer board (2s2p)

Junction-to-ambient (@200 ft/min or 1.0 m/s) on four layer board (2s2p)

Junction-to-ambient (@400 ft/min or 2.0 m/s) on four layer board (2s2p)

Junction-to-board thermal

R

θJMA

R

θJMA

R

θJMA

R

θJB

17

14

13

10

°C/W

°C/W

°C/W

°C/W

1, 2

1, 2

1, 2

3

Junction-to-case thermal R

θJC

0.96

°C/W 4

Notes

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance

2. Per JEDEC JESD51–6 with the board horizontal.

3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1). Cold plate temperature is used for case temperature; measured value includes the thermal resistance of the interface layer.

16.2

Thermal Management Information

This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal interface material. The recommended attachment

method to the heat sink is illustrated in Figure 43

. The heat sink should be attached to the printed-circuit board with the spring force centered over the die. This spring force should not exceed 10 pounds force.



Thermal

Heat Sink

Heat Sink

Clip

Thermal Interface Material

Lid

Die

FC-PBGA Package

Printed-Circuit Board

Figure 43. Package Exploded Cross-Sectional View with Several Heat Sink Options

The system board designer can choose between several types of heat sinks to place on the MPC8555E.

There are several commercially-available heat sinks from the following vendors:

Aavid Thermalloy

80 Commercial St.

Concord, NH 03301

Internet: www.aavidthermalloy.com

Alpha Novatech

473 Sapena Ct. #15

Santa Clara, CA 95054

Internet: www.alphanovatech.com

603-224-9988

408-749-7601

International Electronic Research Corporation (IERC) 818-842-7277

413 North Moss St.

Burbank, CA 91502

Internet: www.ctscorp.com

Millennium Electronics (MEI)

Loroco Sites

671 East Brokaw Road

San Jose, CA 95112

Internet: www.mei-millennium.com

408-436-8770

800-522-6752 Tyco Electronics

Chip Coolers™

P.O. Box 3668

Harrisburg, PA 17105-3668

Internet: www.chipcoolers.com

Wakefield Engineering

33 Bridge St.

Pelham, NH 03076

Internet: www.wakefield.com

603-635-5102

70



Thermal

Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Several heat sinks offered by Aavid Thermalloy, Alpha Novatech, IERC, Chip Coolers, Millennium Electronics, and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, that allows the

MPC8555E to function in various environments.

16.2.1

Recommended Thermal Model

For system thermal modeling, the MPC8555E thermal model is shown in Figure 44 . Five cuboids are used

to represent this device. To simplify the model, the solder balls and substrate are modeled as a single block

29x29x1.6 mm with the conductivity adjusted accordingly. The die is modeled as 8.7 x 9.3 mm at a thickness of 0.75 mm. The bump/underfill layer is modeled as a collapsed resistance between the die and substrate assuming a conductivity of 4.4 W/m•K in the thickness dimension of 0.07 mm. The lid attach adhesive is also modeled as a collapsed resistance with dimensions of 8.7 x 9.3 x 0.05 mm and the conductivity of 1.07 W/m•K. The nickel plated copper lid is modeled as 11 x 11 x 1 mm.

Conductivity Value Unit

Lid

(11 × 11 × 1 mm) k x k y k z

360

360

360

Lid Adhesive—Collapsed resistance

(8.7 × 9.3 × 0.05 mm) k z

1.07

Die

(8.7 × 9.3 × 0.75 mm)

Bump/Underfill—Collapsed resistance

(8.7 × 9.3 × 0.07 mm) k z

4.4

Substrate and Solder Balls

(25 × 25 × 1.6 mm) k x k y k z

14.2

14.2

1.2

W/(m × K)

Lid z

Die

Substrate and solder balls

Side View of Model (Not to Scale)

Adhesive

Bump/underfill x

Substrate

Heat Source y

Top View of Model (Not to Scale)

Figure 44. MPC8555E Thermal Model



Thermal

16.2.2

Internal Package Conduction Resistance

For the packaging technology, shown in Table 49

, the intrinsic internal conduction thermal resistance paths are as follows:

• The die junction-to-case thermal resistance

• The die junction-to-board thermal resistance

Figure 45

depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board.

External Resistance Radiation Convection

Heat Sink

Internal Resistance

Printed-Circuit Board

Thermal Interface Material

Die/Package

Die Junction

Package/Leads

External Resistance

Radiation Convection

(Note the internal versus external package resistance)

Figure 45. Package with Heat Sink Mounted to a Printed-Circuit Board

The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is conducted through the silicon and through the lid, then through the heat sink attach material (or thermal interface material), and finally to the heat sink. The junction-to-case thermal resistance is low enough that the heat sink attach material and heat sink thermal resistance are the dominant terms.

16.2.3

Thermal Interface Materials

A thermal interface material is required at the package-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism,

Figure 46

shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.

As shown, the performance of these thermal interface materials improves with increasing contact pressure.

The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a thermal resistance approximately six times greater than the thermal grease joint.

Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see

Figure 42

). Therefore, the synthetic grease offers the best thermal performance, especially at the low interface pressure.

When removing the heat sink for re-work, it is preferable to slide the heat sink off slowly until the thermal interface material loses its grip. If the support fixture around the package prevents sliding off the heat sink,

72



Thermal

the heat sink should be slowly removed. Heating the heat sink to 40–50

°

C with an air gun can soften the interface material and make the removal easier. The use of an adhesive for heat sink attach is not recommended.

2

Silicone Sheet (0.006 in.)

Bare Joint

Floroether Oil Sheet (0.007 in.)

Graphite/Oil Sheet (0.005 in.)

Synthetic Grease

1.5

1

0.5

0

0 10 20 30 40

Contact Pressure (psi)

50 60 70

Figure 46. Thermal Performance of Select Thermal Interface Materials

80

The system board designer can choose between several types of thermal interface. There are several commercially-available thermal interfaces provided by the following vendors:

781-935-4850 Chomerics, Inc.

77 Dragon Ct.

Woburn, MA 01888-4014

Internet: www.chomerics.com

Dow-Corning Corporation

Dow-Corning Electronic Materials

2200 W. Salzburg Rd.

Midland, MI 48686-0997

Internet: www.dowcorning.com

Shin-Etsu MicroSi, Inc.

10028 S. 51st St.

Phoenix, AZ 85044

Internet: www.microsi.com

The Bergquist Company

18930 West 78 th

St.

800-248-2481

888-642-7674

800-347-4572



Thermal

Chanhassen, MN 55317

Internet: www.bergquistcompany.com

Thermagon Inc.

4707 Detroit Ave.

Cleveland, OH 44102

Internet: www.thermagon.com

888-246-9050

16.2.4

Heat Sink Selection Examples

The following section provides a heat sink selection example using one of the commercially available heat sinks.

16.2.4.1

Case 1

For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:

T

J

= T

I

+ T

R

+ ( θ

JC

+ θ

INT

+ θ

SA

) × P

D where

T

J is the die-junction temperature

T

I

is the inlet cabinet ambient temperature

T

R

is the air temperature rise within the computer cabinet

θ

JC

is the junction-to-case thermal resistance

θ

INT is the adhesive or interface material thermal resistance

θ

SA is the heat sink base-to-ambient thermal resistance

P

D

is the power dissipated by the device. See Table 4 and

Table 5 .

During operation the die-junction temperatures (T

J

) should be maintained within the range specified in

Table 2

. The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T

A

) may range from 30 ° to 40°C. The air temperature rise within a cabinet (T

R

10

°C. The thermal resistance of some thermal interface material (θ

INT

) may be in the range of 5 ° to

) may be about 1

°C/W. For the purposes of this example, the θ

JC value given in

Table 49

that includes the thermal grease interface and is documented in note 4 is used. If a thermal pad is used, θ

INT

must be added.

Assuming a T

I

of 30°C, a T

R of 5°C, a FC-PBGA package

θ

JC

= 0.96, and a power consumption (P

8.0 W, the following expression for T

J

is obtained:

D

) of

Die-junction temperature: T

J

= 30 °C + 5°C + (0.96°C/W + θ

SA

) × 8.0 W

The heat sink-to-ambient thermal resistance ( θ

SA

) versus airflow velocity for a Thermalloy heat sink

#2328B is shown in

Figure 47

.

Assuming an air velocity of 2 m/s, we have an effective θ

SA+

of about 3.3°C/W, thus

T

J

= 30°C + 5°C + (0.96°C/W + 3.3°C/W) × 8.0 W, resulting in a die-junction temperature of approximately 69°C which is well within the maximum operating temperature of the component.

74



Thermal

6

5

8

7

4

Thermalloy #2328B Pin-fin Heat Sink

(25 × 28 × 15 mm)

3

2

1

0 0.5

1 1.5

2

Approach Air Velocity (m/s)

2.5

3 3.5

Figure 47. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity

16.2.4.2

Case 2

Every system application has different conditions that the thermal management solution must solve. As an alternate example, assume that the air reaching the component is 85 °C with an approach velocity of 1 m/sec. For a maximum junction temperature of 105 °C at 8 W, the total thermal resistance of junction to case thermal resistance plus thermal interface material plus heat sink thermal resistance must be less than

2.5 °C/W. The value of the junction to case thermal resistance in

Table 49

includes the thermal interface resistance of a thin layer of thermal grease as documented in footnote 4 of the table. Assuming that the heat sink is flat enough to allow a thin layer of grease or phase change material, then the heat sink must be less than 1.5 °C/W.

Millennium Electronics (MEI) has tooled a heat sink MTHERM-1051 for this requirement assuming a compactPCI environment at 1 m/sec and a heat sink height of 12 mm. The MEI solution is illustrated in

Figure 48

and Figure 49 . This design has several significant advantages:

• The heat sink is clipped to a plastic frame attached to the application board with screws or plastic inserts at the corners away from the primary signal routing areas.

• The heat sink clip is designed to apply the force holding the heat sink in place directly above the die at a maximum force of less than 10 lbs.

• For applications with significant vibration requirements, silicone damping material can be applied between the heat sink and plastic frame.



Thermal

The spring mounting should be designed to apply the force only directly above the die. By localizing the force, rocking of the heat sink is minimized. One suggested mounting method attaches a plastic fence to the board to provide the structure on which the heat sink spring clips. The plastic fence also provides the opportunity to minimize the holes in the printed-circuit board and to locate them at the corners of the package.

Figure 48 and provide exploded views of the plastic fence, heat sink, and spring clip.

Figure 48. Exploded Views (1) of a Heat Sink Attachment using a Plastic Fence

76



Thermal

Figure 49. Exploded Views (2) of a Heat Sink Attachment using a Plastic Force

The die junction-to-ambient and the heat sink-to-ambient thermal resistances are common figure-of-merits used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature is not only a function of the component-level thermal resistance, but the system level design and its operating conditions. In addition to the component’s power consumption, a number of factors affect the final operating die-junction temperature: airflow, board population (local heat flux of adjacent components), system air temperature rise, altitude, etc.

Due to the complexity and the many variations of system-level boundary conditions for today’s microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation convection and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the boards, as well as, system-level designs.



System Design Information

17 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC8555E.

17.1

System Clocking

The MPC8555E includes five PLLs.

1. The platform PLL (AV

DD

1

) generates the platform clock from the externally supplied SYSCLK input. The frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in

Section 15.2, “Platform/System PLL Ratio .”

2. The e500 Core PLL (AV

DD

2

) generates the core clock as a slave to the platform clock. The frequency ratio between the e500 core clock and the platform clock is selected using the e500

PLL ratio configuration bits as described in Section 15.3, “e500 Core PLL Ratio .”

3. The CPM PLL (AV

DD

3) is slaved to the platform clock and is used to generate clocks used internally by the CPM block. The ratio between the CPM PLL and the platform clock is fixed and not under user control.

4. The PCI1 PLL (AV

DD

4) generates the clocking for the first PCI bus.

5. The PCI2 PLL (AV

DD

5) generates the clock for the second PCI bus.

17.2

PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins (AV

DD

AV

DD

2, AV

DD

3, AV

DD

4, and AV

DD

5 respectively). The AV

DD

level should always be equivalent to V

1,

DD

, and preferably these voltages are derived directly from V

DD

through a low frequency filter scheme such as the following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide five independent filter circuits as illustrated in Figure 50

, one to each of the five AV

DD

pins. By providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor.

Each circuit should be placed as close as possible to the specific AV

DD

pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV

DD pin, which is on the periphery of the 783 FC-PBGA footprint, without the inductance of vias.

78



Figure 50

shows the PLL power supply filter circuit.

10 Ω

V

DD

2.2 µF

AV

DD

(or L2AV

DD

)

2.2 µF

GND

Low ESL Surface Mount Capacitors

Figure 50. PLL Power Supply Filter Circuit


17.3

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the MPC8555E can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the MPC8555E system, and the

MPC8555E itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each V

DD

, OV

DD

, GV

DD

, and LV

DD

pins of the MPC8555E. These decoupling capacitors should receive their power from separate V

DD

, OV

DD

,

GV

DD

, LV

DD

, and GND power planes in the PCB, utilizing short traces to minimize inductance.

Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part.

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the V

DD

, OV

DD

, GV

DD

, and LV

DD

planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo

OSCON).

17.4

Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OV

DD

, GV

DD

, or LV

DD

as required. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external V

DD

, GV

DD

, LV

DD

, OV

DD

, and GND pins of the MPC8555E.

17.5

Output Buffer DC Impedance

The MPC8555E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I

2

C).

To measure Z

0

for the single-ended drivers, an external resistor is connected from the chip pad to OV

DD or GND. Then, the value of each resistor is varied until the pad voltage is OV

DD

/2 (see

Figure 51

). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices.




When data is held high, SW1 is closed (SW2 is open) and R

P

is trimmed until the voltage at the pad equals

OV

DD

/2. R

P

then becomes the resistance of the pull-up devices. R

P other in value. Then, Z

0

= (R

P

+ R

N

)/2.

and R

N

are designed to be close to each

OV

DD

R

N

SW2

Pad

Data

SW1

R

P

OGND

Figure 51. Driver Impedance Measurement

The value of this resistance and the strength of the driver’s current source can be found by making two measurements. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V

1

= R source

× I source

. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value R term

. The measured voltage is V

2

× (V

1

/V

2

= 1/(1/R

1

+ 1/R

2

)) × I source

– 1). The drive current is then I source

= V

. Solving for the output impedance gives R

1

/R source

.

source

= R term

Table 50

summarizes the signal impedance targets. The driver impedance are targeted at minimum V

DD

, nominal OV

DD

, 105 °C.

Table 50. Impedance Characteristics

Impedance

Local Bus, Ethernet, DUART, Control, Configuration, Power

Management

R

N

R

P

Differential

43 Target

43 Target

NA

Note: Nominal supply voltages. See

Table 1 , T

j

= 105°C.

PCI DDR DRAM Symbol Unit

25 Target 20 Target

25 Target 20 Target

NA NA

Z

0

Z

0

Z

DIFF

Ω

Ω

Ω

80




17.6

Configuration Pin Multiplexing

The MPC8555E provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k Ω on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped with an on-chip gated resistor of approximately 20 k Ω. This value should permit the 4.7-kΩ resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and for platform/system clocks after HRESET deassertion to ensure capture of the reset value). When the input receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with minimal signal quality or delay disruption. The default value for all configuration bits treated this way has been encoded such that a high voltage level puts the device into the default state and external resistors are needed only when non-default settings are required by the user.

Careful board layout with stubless connections to these pull-down resistors coupled with the large value of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured.

The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up devices.

17.7

Pull-Up Resistor Requirements

The MPC8555E requires high resistance pull-up resistors (10 k

Ω is recommended) on open drain type pins.

Correct operation of the JTAG interface requires configuration of a group of system control pins as

demonstrated in Figure 53 . Care must be taken to ensure that these pins are maintained at a valid deasserted

state under normal operating conditions as most have asynchronous behavior and spurious assertion give unpredictable results.

TSEC1_TXD[3:0] must not be pulled low during reset. Some PHY chips have internal pulldowns that could cause this to happen. If such PHY chips are used, then a pullup must be placed on these signals strong enough to restore these signals to a logical 1 during reset.

Refer to the PCI 2.2 specification for all pull-ups required for PCI.

17.8

JTAG Configuration Signals

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the

IEEE 1149.1 specification, but is provided on all processors that implement the Power Architecture. The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not interfere with normal chip operation. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, generally systems assert TRST during the power-on reset flow. Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the common on-chip processor (COP) function.




The COP function of these processors allow a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic.

The arrangement shown in

Figure 52

allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well.

The COP interface has a standard header, shown in Figure 52

, for connection to the target system, and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key.

The COP header adds many benefits such as breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features. An inexpensive option can be to leave the COP header unpopulated until needed.

There is no standardized way to number the COP header; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as

with an IC). Regardless of the numbering, the signal placement recommended in Figure 52

is common to all known emulators.

COP_TDO

COP_TDI

NC

COP_TCK

COP_TMS

COP_SRESET

COP_HRESET

COP_CHKSTP_OUT

3

13

15

5

7

9

11 12

KEY

No pin

16

6

8

10

2

4

NC

COP_TRST

COP_VDD_SENSE

COP_CHKSTP_IN

NC

NC

GND

Figure 52. COP Connector Physical Pinout

82




17.8.1 Termination of Unused Signals

If the JTAG interface and COP header are not used, Freescale recommends the following connections:

• TRST should be tied to HRESET through a 0 k Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during the power-on reset flow. Freescale recommends that the COP header be designed into the system as shown in

Figure 53

. If this is not possible, the isolation resistor allows future access to TRST in case a JTAG interface may need to be wired onto the system in future debug situations.

• Tie TCK to OV

DD

through a 10 k

Ω resistor. This prevents TCK from changing state and reading incorrect data into the device.

• No connection is required for TDI, TMS, or TDO.




From Target

Board Sources

(if any)

SRESET

HRESET

10 kΩ

10 kΩ

OV

DD

SRESET

6

HRESET

1

13

11

COP_HRESET

COP_SRESET

10 kΩ

10 kΩ

5

10 kΩ

10 kΩ

COP_TRST TRST

1

2

4

3

5

7

4

6

8

COP_VDD_SENSE

2

6

5

15

NC

COP_CHKSTP_OUT

10 Ω

CKSTP_OUT

9 10

10 kΩ

14

3

11 12

13

KEY

No pin

15 16

COP Connector

Physical Pinout

2

10

8

COP_CHKSTP_IN

COP_TMS

9

COP_TDO

1

COP_TDI

3

COP_TCK

7

NC

NC

12

16

4

10 kΩ

10 kΩ

CKSTP_IN

TMS

TDO

TDI

TCK

Notes:

1. The COP port and target board should be able to independently assert HRESET and TRST to the processor

in order to fully control the processor as shown here.

2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.

3. The KEY location (pin 14) is not physically present on the COP header.

4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity.

5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.

6. Asserting SRESET causes a machine check interrupt to the e500 core.

Figure 53. JTAG Interface Connection

84



Document Revision History

18 Document Revision History

Table 51

provides a revision history for this hardware specification.

Table 51. Document Revision History

Rev. No.

4.2

4.1

4

3.2

3.1

3

2

1

0

Date

Substantive Change(s)

1/2008 Added “Note: Rise/Fall Time on CPM Input Pins” and following note text to

Section 10.2, “CPM AC

Timing Specifications

.”

Inserted

Figure 3 , ““Maximum AC Waveforms on PCI interface for 3.3-V Signaling.”

7/2007

12/2006

Updated

Section 2.1.2, “Power Sequencing.”

Updated back page information.

11/2006

Updated

Section 2.1.2, “Power Sequencing.”

Replaced

Section 17.8, “JTAG Configuration Signals.”

10/2005

Added footnote 2 about junction temperature in

Table 4

.

Added max. power values for 1000 MHz core frequency in

Table 4 .

Removed Figure 3 , “Maximum AC Waveforms on PCI Interface for 3.3-V Signaling.”

Modified note to t

LBKSKEW

from 8 to 9 in Table 30 .

Changed t

LBKHOZ1 and t

LBKHOV2 values in

Table 30

.

Added note 3 to t

LBKHOV1 in

Table 30 .

Modified note 3 in

Table 30 and

Table 31

.

Added note 3 to t

LBKLOV1

in Table 31 .

Modified values for t

LBKHKT

, t

LBKLOV1

, t

LBKLOV2

, t

LBKLOV3

, t

LBKLOZ1

, and t

LBKLOZ2 in

Table 31

.

Changed Input Signals: LAD[0:31]/LDP[0:3] in

Figure 21

.

Modified note for signal CLK_OUT in

Table 43 .

PCI1_CLK and PCI2_CLK changed from I/O to I in

Table 43

.

Added column for Encryption Acceleration in

Table 52

.

8/2005

Modified max. power values in Table 4

.

Modified notes for signals TSEC1_TXD[3:0], TSEC2_TXD[3:0], TRIG_OUT/READY, MSRCID4,

CLK_OUT, and MDVAL in

Table 43

.

8/2005

6/2005

6/2005

Previous revision’s history listed incorrect cross references. Table 2 is now correctly listed as

Table 27

and Table 38 is now listed as Table 31

.

Added note 2 in Table 7

.

Modified min and max values for t

DDKHMP

in

Table 14

.

Changed LV dd

to OV dd

for the supply voltage Ethernet management interface in

Table 27

.

Modified footnote 4 and changed typical power for the 1000 MHz core frequency in Table 4 .

Corrected symbols for body rows 9–15, effectively changing them from a high state to a low state

in Table 31 .

Initial release.



Device Nomenclature

19 Device Nomenclature

Ordering information for the parts fully covered by this specification document is provided in

Section 19.1, “Nomenclature of Parts Fully Addressed by this Document.”

19.1

Nomenclature of Parts Fully Addressed by this Document

Table 52

provides the Freescale part numbering nomenclature for the MPC8555E. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number.

Table 52. Part Numbering Nomenclature

MPC nnnn t pp aa a r

Product

Code

Part

Identifier

Encryption

Acceleration

Temperature

Range

1

Package

2

Processor

Frequency

3

Platform

Frequency

Revision

Level

4

MPC 8555 Blank = not included

E = included

Blank = 0 to 105°C

C = –40 to 105°C

PX = FC-PBGA

VT = FC-PBGA

(lead free)

AJ = 533 MHz

AK = 600 MHz

AL = 667 MHz

AP = 833 MHz

AQ = 1000 MHZ

D = 266 MHz

E = 300 MHz

F = 333 MHz

Notes:

1. For Temperature Range=C, Processor Frequency is limited to 667 MHz with a Platform Frequency selector of 333 MHz,

Processor Frequency is limited to 533 MHz with a Platform Frequency selector of 266 MHz.

2. See

Section 14, “Package and Pin Listings ,” for more information on available package types.

3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other maximum core frequencies.

4. Contact you local Freescale field applications engineer (FAE).

86



19.2

Part Marking

Parts are marked as the example shown in

Figure 54

.

Notes

:

85xx

FC-PBGA

Figure 54. Part Marking for FC-PBGA Device

Device Nomenclature



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© Freescale Semiconductor, Inc., 2008. All rights reserved.

Document Number: MPC8555EEC

Rev. 4.2

1/2008

datasheet for KMPC8555EVTAPF by Freescale

Freescale Semiconductor

Technical Data

MPC8555E PowerQUICC™ III

Integrated Communications Processor

Hardware Specification

1 Overview

1.1

Key Features

2 Electrical Characteristics

2.1

Overall DC Electrical Characteristics

2.1.1

Absolute Maximum Ratings

2.1.2

Power Sequencing

2.1.3

Recommended Operating Conditions

2.1.4

Output Driver Characteristics

3 Power Characteristics

4 Clock Timing

4.1

System Clock Timing

4.2

TSEC Gigabit Reference Clock Timing

4.3

Real Time Clock Timing

5 RESET Initialization

6 DDR SDRAM

6.1

DDR SDRAM DC Electrical Characteristics

6.2

DDR SDRAM AC Electrical Characteristics

6.2.1

DDR SDRAM Input AC Timing Specifications

6.2.2

DDR SDRAM Output AC Timing Specifications

7 DUART

7.1

DUART DC Electrical Characteristics

7.2

DUART AC Electrical Specifications

8 Ethernet: Three-Speed, MII Management

8.1

Three-Speed Ethernet Controller (TSEC)

(10/100/1000 Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical

Characteristics

8.1.1

TSEC DC Electrical Characteristics

8.2

GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications

8.2.1

GMII AC Timing Specifications

8.2.2

GMII Transmit AC Timing Specifications

8.2.3

MII AC Timing Specifications

8.2.4

TBI AC Timing Specifications

8.2.5

RGMII and RTBI AC Timing

8.3

Ethernet Management Interface Electrical Characteristics

8.3.1

MII Management DC Electrical Characteristics

8.3.2

MII Management AC Electrical Specifications

9 Local Bus

9.1

Local Bus DC Electrical Characteristics

9.2

Local Bus AC Electrical Specifications

10 CPM

10.1

CPM DC Electrical Characteristics

10.2

CPM AC Timing Specifications

NOTE

10.3