datasheet for SYS1664FKE by Apta Group

datasheet for SYS1664FKE by Apta Group
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
64K x 16 SRAM MODULE
SYS1664FKE-70/85/10/12
Elm Road, West Chirton Industrial Estate, North Shields,
NE29 8SE, ENGLAND. TEL +44 191 2930519. FAX +44 191 2590997
Issue 1.1 : May 1996
Description
Features
The SYS1664FKE is a plastic 1Mbit Static RAM
Module housed in a standard 40 pin Dual-In-Line
package organised as 64K x 16 with access times
of 70, 85,100, or 120 ns. The device has on-board
decoding and supply decoupling capacitors.
•
•
The module is constructed using four 32Kx8 SRAMs
in SOP packages mounted onto both sides of an
FR4 epoxy substrate. This offers an extremely high
PCB packing density.
The device is offered in standard and low power
versions, with the -L module having a low voltage
data retention mode for battery backed applications.
Block Diagram
Pin Definition
D8-D15
D0-D7
A0 - A14
WE
OE
32K X 8
SRAM
•
•
•
•
•
•
•
•
Access Times of 70/85/100/120 ns.
Low Power Disapation:
Operating
805 mW (Max)
Standby -L version
2.2 mW (Max)
Address & control inputs appear as a single load
Completely Static Operation.
Equal Access and Cycle Times.
Low Voltage VCC Data Retention -L version.
Directly TTL Compatible.
5 Volt Supply ± 10%.
EPROM Compatible Pinout.
Battery back-up capability.
32K X 8
SRAM
A15
CS
32K X 8
SRAM
DECODER
Pin Functions
Address Inputs
A0 - A15
Data Input/Output
D0 - D15
Chip Select
CS
Write Enable
WE
Output Enable
OE
No Connect
NC
Power (+5V)
VCC
Ground
GND
32K
32K X
X 88
SRAM
SRAM
NC
CS
D15
D14
D13
D12
D11
D10
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
OE
1
2
3
4
5
6
7
8
9
10 TOP VIEW
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
Package Details
Plastic 40 Pin 0.6" DIP
Vcc
WE
NC
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
ISSUE 1.1 May 1996
SYS1664FKE-70/85/10/12
Absolute Maximum Ratings (1)
Voltage on any pin relative to VSS
Power Dissipation
Storage Temperature
VT
PT
TSTG
-0.5V to +7.0 V
2.0
W
-55 to +125 °C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of The device at those or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
(2) Pulse Width: -3.0V for less than 50ns
Recommended Operating Conditions
Parameter
Symbol
Supply Voltage
VCC
Input High Voltage
VIH
Input Low Voltage
VIL
Operating Temperature
TA
TAI
min
4.5
2.2
-0.3
0
-40
typ
5.0
-
max
Unit
5.5
V
VCC+0.3 V
0.8
V
°
70
C
°
85
C (1664I)
DC Electrical Characteristics (TA=-40 to +85°C,V CC=5V±10%,)
Parameter
Symbol
Input Leakage Current
Output Leakage Current
IIL
IOL
Average Supply Current
Standby Supply Current
(-L part)
ICC1
ISB1
ISB2
Output LowVoltage
Output HighVoltage
VOL
VOH
Test Condition
min
typ
max
Unit
VIN=0V to VCC
-2
VI/O=Gnd to Vcc
-1
-
2
1
µA
µA
Min. Cycle,duty=100%,II/O=0mA
CS>VCC-0.2V, VIN>0V
-
-
CS>VCC-0.2V, VIN>0V
-
-
146
12
400
mA
mA
µA
2.4
-
0.40
-
V
V
typ
-
max
10
10
Unit
pF
pF
IOL=2.1mA
IOH=-400µA
Capacitance (VCC=5V±10%,TA=25oC)
Parameter
Input Capacitance:
I/O Capacitance:
Note:
Symbol
CIN
CI/O
Test Condition
VIN = 0V
VI/O= 0V
This parameter is calculated not measured.
AC Test Conditions
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: 1 TTL gate + 100pF
* VCC=5V±10%
2
SYS1664FKE-70/85/10/12
ISSUE 1.1 May 1996
OperationTruth Table
CS
OE
WE
Mode
Outputs
Supply Current
H
L
L
L
X
L
X
H
X
H
L
H
Standby
Read
Write
Output Disable
High Z (D0-D15)
Dout (0-15)
Din (0-15)
High Z (D0-D15)
ISB1, ISB2
Icc
Icc
Icc
Notes : H = VIH : L = VIL : X = VIH or VIL
Low VCC Data Retention Characteristics - L Version Only
Parameter
VCC for Data Retention
Data Retention Current
Chip Deselect to
Data Retention Time
Operation Recovery
Time
Symbol
Test Condition
min
typ
max
Unit
VDR
ICCDR1
ICCDR2
CS>VCC-0.2V
2.0
-
280
-
380
460
V
µA
µA
tCDR
See Retention Waveform
0
-
-
ns
tR
See Retention Waveform
tRC(1)
-
-
ns
VCC=3.0V,CS>2.8V,TOP=TA
VCC=3.0V,CS>2.8V,TOP=TAI
Notes: (1) tRC=Read Cycle Time
3
ISSUE 1.1 May 1996
SYS1664FKE-70/85/10/12
AC OPERATING CONDITIONS
Read Cycle
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
Output Disable to Output in High Z
Symbol
tRC
tAA
tACS
tOE
tOH
tCLZ
tOLZ
tCHZ
tOHZ
min
70
5
5
5
0
0
-70
max
70
70
40
30
30
-85
min max
85
85
85
45
5
5
5
0
30
0
30
-10
min max
100
100
100
50
10
10
5
0
40
0
40
-12
min max
120
120
120
60
10
10
5
0
50
0
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Symbol
-70
min max
-85
min max
-10
min max
-12
min max
Unit
70
65
65
0
55
5
0
30
0
0
5
85
75
75
0
65
5
0
40
0
0
5
100
80
80
0
70
5
0
40
0
0
5
120
100
100
0
80
5
0
50
0
0
5
Write Cycle
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
Output Active from End of Write
tWC
tCW
tAW
tAS
tWP
tWR
tWHZ
tDW
tDH
tOHZ
tOW
4
25
30
-
30
30
-
40
40
-
50
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYS1664FKE-70/85/10/12
ISSUE 1.1 May 1996
Read Cycle Timing Waveform (1,2)
t RC
Address
t AA
OE
t OE
t OH
t OLZ
CS
t ACS
Don't
care.
t OHZ (3)
t CLZ (4,5)
Dout
Data Valid
t CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not
referenced to output voltage levels.
(4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform(1,4)
tWC
Address
t WR(7)
OE
t AS(6)
t AW
t CW
CS
Don't
Care
WE
t OHZ(3,9)
tOW
t WP(2)
High-Z
Dout
t DW
Din
High-Z
t DH
Data Valid
5
(8)
ISSUE 1.1 May 1996
SYS1664FKE-70/85/10/12
Write Cycle No.2 Timing Waveform (1,5)
tWC
Address
t AS(6)
t CW
t WR(7)
CS
t AW
t WP(2)
WE
tOH
t WHZ(3,9)
t OW
High-Z
Dout
t DW
(8)
(4)
Don't
Care
t DH
High-Z
Din
Data Valid
AC Write Characteristics Notes
(1) All write cycle timing is referenced from the last valid address to the first transition address.
(2) All writes occur during the overlap of CS and WE low.
(3) If OE, CS, and WE are in the Read mode during this period, the I/O pins are low impedance state.
Inputs of opposite phase to the output must not be applied because bus contention can occur.
(4) Dout is the Read data of the new address.
(5) OE is continuously low.
(6) Address is valid prior to or coincident with CS and WE low, too avoid inadvertant writes.
(7) CS or WE must be high during address transitions.
(8) When CS is low : I/O pins are in the output state. Input signals of opposite phase leading to the
output should not be applied.
(9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
Data Retention Waveform
DATA RETENTION MODE
Vcc
4.5V
4.5V
t CDR
tR
2.2V
2.2V
V DR
CS
CS > Vcc -0.2V
0V
6
SYS1664FKE-70/85/10/12
Package Details.
ISSUE 1.1 May 1996
Dimensions in mm
40 Pin 0.6" Dual-In-Line Package.
51.05 max.
15.92 max
2.54 typ.
15.24 typ.
typ.
3.50 +/-0.50
7.20 max.
Ordering Information
SYS1664FKELI-10
Speed
70
85
10
12
= 70 ns
= 85 ns
= 100 ns
= 120 ns
Temperature range
Blank = Commercial Temp.
I = Industrial Temp.
Power Consumption
Blank = Standard Part
L = Low Power Part
Package
FKE = Plastic 40 Pin 0.6" DIP
Organisation
1664 = 64K x 16
Memory Type
SYS = Static RAM
Note : This document may be wholly or partially subject to change without notice. Syntaq Ltd devices are not authorised for use as
critical components in life support devices.
7
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