Datasheet ds1306
DS1306
Serial Alarm Real Time Clock (RTC)
www.dalsemi.com
FEATURES
PIN ASSIGNMENT
Real time clock counts seconds, minutes,
hours, date of the month, month, day of the
week, and year with leap year compensation
valid up to 2100
96-byte nonvolatile RAM for data storage
Two Time of Day Alarms - programmable on
combination of seconds, minutes, hours, and
day of the week
1 Hz and 32.768 kHz clock outputs
Serial interface supports Motorola Serial
Peripheral Interface (SPI) serial data ports or
standard 3-wire interface
Burst Mode for reading/writing successive
addresses in clock/RAM
Dual power supply pins for primary and
backup power supplies
Optional trickle charge output to backup
supply
2.0 - 5.5V operation
Optional industrial temperature range
-40°C to +85°C
Available in space-efficient 20-pin TSSOP
package
Recognized by Underwriters Laboratory
ORDERING INFORMATION
DS1306
DS1306N
DS1306E
DS1306EN
16-Pin DIP
16-Pin DIP (Industrial)
20-Pin TSSOP
20-Pin TSSOP (Industrial)
1
2
3
4
5
6
7
8
9
10
VCC2
VBAT
X1
NC
X2
NC
INT0
INT1
1 Hz
GND
20
19
18
17
16
15
14
13
12
11
VCC1
NC
32 kHz
VCCIF
SDO
SDI
SCLK
NC
CE
SERMODE
DS1306 20-Pin TSSOP (173 mil)
1
16
VCC1
VBAT
2
15
32 kHz
X1
3
14
VCCIF
X2
4
13
SDO
5
12
SDI
INT1
6
11
SCLK
1 Hz
7
10
CE
GND
8
9
VCC2
INT0
SERMODE
DS1306 16-Pin DIP (300 mil)
PIN DESCRIPTION
VCC1
VCC2
VBAT
VCCIF
GND
X1, X2
INT0
INT1
SDI
SDO
CE
SCLK
SERMODE
1 Hz
32 kHz
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– Primary Power Supply
– Backup Power Supply
– +3V Battery Input
– Interface Logic Power Supply
Input
– Ground
– 32.768 kHz Crystal Connection
– Interrupt 0 Output
– Interrupt 1 Output
– Serial Data In
– Serial Data Out
– Chip Enable
– Serial Clock
– Serial Interface Mode
- 1 Hz Output
- 32.768 kHz Output
070900
DS1306
DESCRIPTION
The DS1306 Serial Alarm Real Time Clock provides a full BCD clock calendar which is accessed via a
simple serial interface. The clock/calendar provides seconds, minutes, hours, day, date, month, and year
information. The end of the month date is automatically adjusted for months with less than 31 days,
including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with
AM/PM indicator. In addition 96 bytes of nonvolatile RAM are provided for data storage.
An interface logic power supply input pin (VCCIF) allows the DS1306 to drive SDO and 32 kHz pins to a
level that is compatible with the interface logic. This allows an easy interface to 3-volt logic in mixed
supply systems. The DS1306 offers dual power supplies as well as a battery input pin. The dual power
supplies support a programmable trickle charge circuit which allows a rechargeable energy source (such
as a super cap or rechargeable battery) to be used for a backup supply. The VBAT pin allows the device to
be backed up by a non-rechargeable battery. The DS1306 is fully operational from 2.0 to 5.5 volts.
Two programmable time of day alarms are provided by the DS1306. Each alarm can generate an
interrupt on a programmable combination of seconds, minutes, hours, and day. “Don’t care” states can be
inserted into one or more fields if it is desired for them to be ignored for the alarm condition. A 1 Hz and
a 32 kHz clock output are also available.
The DS1306 supports a direct interface to Motorola SPI serial data ports or standard 3-wire interface. An
easy-to-use address and data format is implemented in which data transfers can occur 1 byte at a time or
in multiple-byte burst mode.
OPERATION
The block diagram in Figure 1 shows the main elements of the Serial Alarm RTC. The following
paragraphs describe the function of each pin.
DS1306 BLOCK DIAGRAM Figure 1
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DS1306
SIGNAL DESCRIPTIONS
VCC1 - DC power is provided to the device on this pin. VCC1 is the primary power supply.
VCC2 - This is the secondary power supply pin. In systems using the trickle charger, the rechargeable
energy source is connected to this pin.
VBAT - Battery input for any standard 3-volt lithium cell or other energy source.
VCCIF (Interface Logic Power Supply Input) - The VCCIF pin allows the DS1306 to drive SDO and
32 kHz output pins to a level that is compatible with the interface logic, thus allowing an easy interface to
3-volt logic in mixed supply systems. This pin is physically connected to the source connection of the pchannel transistors in the output buffers of the SDO and 32 kHz pins.
SERMODE (Serial Interface Mode Input) - The SERMODE pin offers the flexibility to choose
between two serial interface modes. When connected to GND, standard 3-wire communication is
selected. When connected to VCC, Motorola SPI communication is selected.
SCLK (Serial Clock Input) - SCLK is used to synchronize data movement on the serial interface for
either the SPI or 3-wire interface.
SDI (Serial Data Input) - When SPI communication is selected, the SDI pin is the serial data input for
the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDO pin (the SDI and
SDO pins function as a single I/O pin when tied together).
SDO (Serial Data Output) - When SPI communication is selected, the SDO pin is the serial data output
for the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDI pin (the SDI
and SDO pins function as a single I/O pin when tied together).
CE (Chip Enable) - The Chip Enable signal must be asserted high during a read or a write for both
3-wire and SPI communication. This pin has an internal 55k pull-down resistor (typical).
INT0 (Interrupt 0 Output) - The INT0 pin is an active low output of the DS1306 that can be used as an
interrupt input to a processor. The INT0 pin can be programmed to be asserted by Alarm 0. The INT0
pin remains low as long as the status bit causing the interrupt is present and the corresponding interrupt
enable bit is set. The INT0 pin operates when the DS1306 is powered by VCC1, VCC2, or VBAT. The INT0
pin is an open drain output and requires an external pullup resistor.
1 Hz (1 Hz Clock Output) - The 1 Hz pin provides a 1 Hz squarewave output. This output is active
when the 1 Hz bit in the control register is a logic 1.
Both INT0 and 1 Hz pins are open drain outputs. The interrupt, 1 Hz signal, and the internal clock
continue to run regardless of the level of VCC (as long as a power source is present).
INT1 (Interrupt 1 Output) - The INT1 pin is an active high output of the DS1306 that can be used as an
interrupt input to a processor. The INT1 pin can be programmed to be asserted by alarm 1. When an
alarm condition is present, the INT1 pin generates a 62.5 ms active high pulse. The INT1 pin operates
only when the DS1306 is powered by VCC2 or VBAT. When active, the INT1 pin is internally pulled up to
VCC2 or VBAT. When inactive, the INT1 pin is internally pulled low.
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DS1306
32 kHz (32.768 kHz Clock Output) - The 32 kHz pin provides a 32.768 kHz output. This signal is
always present.
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator is designed for
operation with a crystal having a specified load capacitance of 6 pF. For more information on crystal
selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations
with Dallas Real Time Clocks.” The DS1306 can also be driven by an external 32.768 kHz oscillator. In
this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.
RTC AND RAM ADDRESS MAP
The address map for the RTC and RAM registers of the DS1306 is shown in Figure 2. Data is written to
the RTC by writing to address locations 80h to 9Fh and is written to the RAM by writing to address
locations A0h to FFh. RTC data is read by reading address locations 00h to 1Fh and RAM data is read by
reading address locations 20h to 7Fh.
ADDRESS MAP Figure 2
00H
CLOCK/CALENDAR
1FH
READ ADDRESSES ONLY
20H
96-BYTES USER RAM
7FH
80H
READ ADDRESSES ONLY
CLOCK/CALENDAR
9FH
A0H
WRITE ADDRESSES ONLY
96-BYTES USER RAM
FFH
WRITE ADDRESSES ONLY
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DS1306
CLOCK, CALENDAR, AND ALARM
The time and calendar information is obtained by reading the appropriate register bytes. The real time
clock registers are illustrated in Figure 3. The time, calendar, and alarm are set or initialized by writing
the appropriate register bytes. Note that some bits are set to 0. These bits will always read 0 regardless
of how they are written. Also note that registers 12h to 1Fh (read) and registers 92h to 9Fh are reserved.
These registers will always read 0 regardless of how they are written. The contents of the time, calendar,
and alarm registers are in the Binary-Coded Decimal (BCD) format.
RTC REGISTERS Figure 3
RTC REGISTERS DS1306
HEX ADDRESS
READ WRITE
00H
80H
01H
81H
02H
82H
Bit7
0
0
0
03H
04H
05H
06H
83H
84H
85H
86H
0
0
0
07H
08H
09H
87H
88H
89H
M
M
M
0AH
8AH
M
0BH
0CH
0DH
8BH
8CH
8DH
M
M
M
0EH
8EH
M
0FH
10H
11H
12-1FH
8FH
90H
91H
92-9FH
Bit6
Bit5
Bit4
Bit3
10 SEC
10 MIN
12/2
10
10 HR
4
P/A
0
0
0
0
0
10 DATE
0
10 MONTH
10 YEAR
Alarm 0
10 SEC ALARM
10 MIN ALARM
12/2
10
10 HR
4
P/A
0
0
0
0
Alarm 1
10 SEC ALARM
10 MIN ALARM
12/2
10
10 HR
4
P/A
0
0
0
0
Bit2
Bit1
Bit0
SEC
MIN
HOURS
DAY
DATE
MONTH
YEAR
SEC ALARM
MIN ALARM
HOUR ALARM
DAY ALARM
SEC ALARM
MIN ALARM
HOUR ALARM
DAY ALARM
CONTROL REGISTER
STATUS REGISTER
TRICKLE CHARGER REGISTER
RESERVED
NOTE:
Range for alarm registers does not include mask’m’ bits.
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RANGE
00-59
00-59
01-12 + P/A
00-23
01-07
1-31
01-12
00-99
00-59
00-59
01-12 + P/A
00-23
01-07
00-59
00-59
01-12 + P/A
00-23
01-07
DS1306
The DS1306 can be run in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the
12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is
the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23
hours).
The DS1306 contains two time of day alarms. Time of Day Alarm 0 can be set by writing to registers
87h to 8Ah. Time of Day Alarm 1 can be set by writing to registers 8Bh to 8Eh. Bit 7 of each of the time
of day alarm registers are mask bits (Table 1). When all of the mask bits are logic 0, a time of day alarm
will only occur once per week when the values stored in timekeeping registers 00h to 03h match the
values stored in the time of day alarm registers. An alarm will be generated every day when bit 7 of the
day alarm register is set to a logic 1. An alarm will be generated every hour when bit 7 of the day and
hour alarm registers is set to a logic 1. Similarly, an alarm will be generated every minute when bit 7 of
the day, hour, and minute alarm registers is set to a logic 1. When bit 7 of the day, hour, minute, and
seconds alarm registers is set to a logic 1, an alarm will occur every second.
TIME OF DAY ALARM MASK BITS Table 1
ALARM REGISTER MASK BITS (BIT 7)
SECONDS MINUTES
HOURS
DAYS
1
1
1
1
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Alarm once per second
Alarm when seconds match
Alarm when minutes and seconds match
Alarm when hours, minutes, and seconds match
Alarm when day, hours, minutes, and seconds
match
SPECIAL PURPOSE REGISTERS
The DS1306 has three additional registers (Control Register, Status Register, and Trickle Charger
Register) that control the real time clock, interrupts, and trickle charger.
CONTROL REGISTER (READ 0FH, WRITE 8FH)
BIT7
0
BIT6
WP
BIT5
0
BIT4
0
BIT3
0
BIT2
1 Hz
BIT1
AIE1
BIT0
AIE0
WP (Write Protect) - Before any write operation to the clock or RAM, this bit must be logic 0. When
high, the write protect bit prevents a write operation to any register, including bits 0, 1, and 2 of the
control register. Upon initial power up, the state of the WP bit is undefined. Therefore the WP bit should
be cleared before attempting to write to the device.
1 Hz (1 Hz output enable) - This bit controls the 1 Hz output. When this bit is a logic 1, the 1 Hz output
is enabled. When this bit is a logic 0, the 1 Hz output is high Z.
AIE0 (Alarm Interrupt Enable 0) - When set to a logic 1, this bit permits the Interrupt 0 Request Flag
(IRQF0) bit in the status register to assert INT0 . When the AIE0 bit is set to logic 0, the IRQF0 bit does
not initiate the INT0 signal.
AIE1 (Alarm Interrupt Enable 1) - When set to a logic 1, this bit permits the Interrupt 1 Request Flag
(IRQF1) bit in the status register to assert INT1. When the AIE1 bit is set to logic 0, the IRQF1 bit does
not initiate an interrupt signal, and the INT1 pin is set to a logic 0 state.
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DS1306
STATUS REGISTER (READ 10H)
BIT7
0
BIT6
0
BIT5
0
BIT4
0
BIT3
0
BIT2
0
BIT1
IRQF1
BIT0
IRQF0
IRQF0 (Interrupt 0 Request Flag) - A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the Alarm 0 registers. If the AIE0 bit is also a logic 1, the INT0 pin will go low.
IRQF0 is cleared when any of the Alarm 0 registers are read or written.
IRQF1 (Interrupt 1 Request Flag) - A logic 1 in the Interrupt Request Flag bit indicates that the current
time has matched the Alarm 1 registers. If the AIE1 bit is also a logic 1, the INT1 pin will generate a
62.5- ms active high pulse. IRQF1 is cleared when any of the Alarm 1 registers are read or written.
TRICKLE CHARGE REGISTER (READ 11H, WRITE 91H)
This register controls the trickle charge characteristics of the DS1306. The simplified schematic of
Figure 4 shows the basic components of the trickle charger. The trickle charge select (TCS) bits (bits
4-7) control the selection of the trickle charger. In order to prevent accidental enabling, only a pattern of
1010 will enable the trickle charger. All other patterns will disable the trickle charger. The DS1306
powers up with the trickle charger disabled. The diode select (DS) bits (bits 2-3) select whether one
diode or two diodes are connected between VCC1 and VCC2. If DS is 01, one diode is selected. If DS is
10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled independently of TCS. The
RS bits select the resistor that is connected between VCC1 and VCC2. The resistor is selected by the
resistor select (RS) bits as shown in Table 2.
PROGRAMMABLE TRICKLE CHARGER Figure 4
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DS1306
TRICKLE CHARGER RESISTOR SELECT Table 2
RS BITS
00
01
10
11
RESISTOR
None
R1
R2
R3
TYPICAL VALUE
None
2 kΩ
4 kΩ
8 kΩ
If RS is 00, the trickle charger is disabled independently of TCS.
Diode and resistor selection is determined by the user according to the maximum current desired for
battery or super cap charging. The maximum charging current can be calculated as illustrated in the
following example. Assume that a system power supply of 5 volts is applied to VCC1 and a super cap is
connected to VCC2. Also assume that the trickle charger has been enabled with one diode and resister R1
between VCC1 and VCC2. The maximum current I MAX would therefore be calculated as follows:
IMAX = (5.0V - diode drop)/R1
~ (5.0V - 0.7V)/2 kΩ
~ 2.2 mA
Obviously, as the super cap charges, the voltage drop between VCC1 and VCC2 will decrease and therefore
the charge current will decrease.
POWER CONTROL
Power is provided through the VCC1, VCC2, and VBAT pins. Three different power supply configurations
are illustrated in Figure 5. Configuration 1 shows the DS1306 being backed up by a non-rechargeable
energy source such as a lithium battery. In this configuration, the system power supply is connected to
VCC1 and VCC2 is grounded. The DS1306 will be write-protected if VCC1 is less than VBAT.
Configuration 2 illustrates the DS1306 being backed up by a rechargeable energy source. In this case, the
VBAT pin is grounded, VCC1 is connected to the primary power supply, and VCC2 is connected to the
secondary supply (the rechargeable energy source). The DS1306 will operate from the larger of VCC1 or
VCC2. When VCC1 is greater than VCC2 + 0.2 volt (typical), VCC1 will power the DS1306. When VCC1 is
less than VCC2, VCC2 will power the DS1306. The DS1306 does not write-protect itself in this
configuration.
Configuration 3 shows the DS1306 in battery operate mode where the device is powered only by a single
battery. In this case, the VCC1 and VBAT pins are grounded and the battery is connected to the VCC2 pin.
Only these three configurations are allowed. Unused supply pins must be grounded.
SERIAL INTERFACE
The DS1306 offers the flexibility to choose between two serial interface modes. The DS1306 can
communicate with the SPI interface or with a standard 3-wire interface. The interface method used is
determined by the SERMODE pin. When this pin is connected to VCC, SPI communication is selected.
When this pin is connected to ground, standard 3-wire communication is selected.
SERIAL PERIPHERAL INTERFACE (SPI)
The serial peripheral interface (SPI) is a synchronous bus for address and data transfer and is used when
interfacing with the SPI bus on specific Motorola microcontrollers such as the 68HC05C4 and the
68HC11A8. The SPI mode of serial communication is selected by tying the SERMODE pin to VCC.
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DS1306
Four pins are used for the SPI. The four pins are the SDO (Serial Data Out), SDI (Serial Data In), CE
(Chip Enable), and SCLK (Serial Clock). The DS1306 is the slave device in an SPI application, with the
microcontroller being the master.
The SDI and SDO pins are the serial data input and output pins for the DS1306, respectively. The CE
input is used to initiate and terminate a data transfer. The SCLK pin is used to synchronize data
movement between the master (microcontroller) and the slave (DS1306) devices.
The shift clock (SCLK), which is generated by the microcontroller, is active only during address and data
transfer to any device on the SPI bus. The inactive clock polarity is programmable in some
microcontrollers. The DS1306 offers an important feature in that the level of the inactive clock is
determined by sampling SCLK when CE becomes active. Therefore either SCLK polarity can be
accommodated. Input data (SDI) is latched on the internal strobe edge and output data (SDO) is shifted
out on the shift edge (see Table 3 and Figure 6). There is one clock for each bit transferred. Address and
data bits are transferred in groups of eight.
POWER SUPPLY CONFIGURATIONS FOR THE DS1306 Figure 5
Configuration 1: Backup Supply is a Non-Rechargeable Lithium Battery
Configuration 2: Backup Supply is a Rechargeable Battery or Super Capacitor
Configuration 3: Battery Operate Mode
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DS1306
FUNCTION TABLE Table 3
MODE
Disable Reset
Write
Read
CE
L
H
H
SCLK
Input Disabled
CPOL=1*
SDI
Input Disabled
Data Bit Latch
SDO
High Z
High Z
CPOL=0
CPOL=1
X
Next data bit
shift**
CPOL=0
* CPOL is the “Clock Polarity” bit that is set in the control register of the microcontroller.
** SDO remains at High Z until 8 bits of data are ready to be shifted out during a read.
NOTE:
CPHA bit polarity (if applicable) may need to be set accordingly.
SERIAL CLOCK AS A FUNCTION OF MICROCONTROLLER
CLOCK POLARITY (CPOL) Figure 6
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DS1306
ADDRESS AND DATA BYTES
Address and data bytes are shifted MSB first into the serial data input (SDI) and out of the serial data
output (SDO). Any transfer requires the address of the byte to specify a write or read to either a RTC or
RAM location, followed by 1 or more bytes of data. Data is transferred out of the SDO for a read
operation and into the SDI for a write operation (see figures 7 and 8).
SPI SINGLE-BYTE WRITE Figure 7
SPI SINGLE-BYTE READ Figure 8
* SCLK can be either polarity.
The address byte is always the first byte entered after CE is driven high. The most significant bit (A7) of
this byte determines if a read or write will take place. If A7 is 0, one or more read cycles will occur. If
A7 is 1, one or more write cycles will occur.
Data transfers can occur 1 byte at a time or in multiple-byte burst mode. After CE is driven high an
address is written to the DS1306. After the address, 1 or more data bytes can be written or read. For a
single-byte transfer 1 byte is read or written and then CE is driven low. For a multiple-byte transfer,
however, multiple bytes can be read or written to the DS1306 after the address has been written. Each
read or write cycle causes the RTC register or RAM address to automatically increment. Incrementing
continues until the device is disabled. When the RTC is selected, the address wraps to 00h after
incrementing to 1Fh (during a read) and wraps to 80h after incrementing to 9Fh (during a write). When
the RAM is selected, the address wraps to 20h after incrementing to 7Fh (during a read) and wraps to
A0h after incrementing to FFh (during a write).
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DS1306
SPI MULTIPLE-BYTE BURST TRANSFER Figure 9
3-WIRE INTERFACE
The 3-wire interface mode operates similar to the SPI mode. However, in 3-wire mode there is one I/O
instead of separate data in and data out signals. The 3-wire interface consists of the I/O (SDI and SDO
pins tied together), CE, and SCLK pins. In 3-wire mode, each byte is shifted in LSB first unlike SPI
mode where each byte is shifted in MSB first.
As is the case with the SPI mode, an address byte is written to the device followed by a single data byte
or multiple data bytes. Figure 10 illustrates a read and write cycle. In 3-wire mode, data is input on the
rising edge of SCLK and output on the falling edge of SCLK.
3-WIRE SINGLE BYTE TRANSFER Figure 10
SINGLE BYTE READ
RST
SCLK
I/O
A0
A1
A2
A3
A4
A5
A6 A7
SINGLE BYTE WRITE
RST
SCLK
I/O
A0 A1
A2
A3 A4
A5 A6 A7
D0
D1
D2
D3
D4
D5
D6 D7
I/O is SDI and SDO tied together
In burst mode, RST is kept high and additional SCLK cycles are sent until the end of the burst.
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DS1306
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
-0.5V to +7.0V
0°C to 70°C or –40°C to +85°C for Industrial (IND)
-55°C to +125°C
260°C for 10 seconds (DIP)
See IPC/JEDEC Standard J-STD-020A for
Surface Mount Devices
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0°C to 70°C or –40° to +85°C)
PARAMETER
Supply Voltage VCC1, VCC2
Logic 1 Input
Logic 0 Input
VBAT Battery Voltage
VCCIF Supply Voltage
SYMBOL
VCC1,
VCC2
VIH
VCC=2.0V
VIL
VCC=5V
VBAT
VCCIF
MIN TYP
2.0
2.0
-0.3
-0.3
2.0
2.0
MAX
5.5
VCC+0.3
+0.3
+0.8
5.5
5.5
UNITS NOTES
V
1, 8
V
1
V
1
V
V
1
14
DC ELECTRICAL CHARACTERISTICS
(0°C to 70°C or –40°C to +85°C; VCC = 2.0 to 5.5V*)
PARAMETER
Input Leakage
Output Leakage
ILI
ILO
Logic 0 Output
VOL
Logic 1 Output
VOH
Logic 1 Output Current (INT1 pin)
SYMBOL
IOH,
INT1
VCC1 Active Supply Current
ICC1A
VCC1 Timekeeping Current
ICC1T
VCC2 Active Supply Current
ICC2A
VCC2 Timekeeping Current
ICC2T
VCC=2.0
VCC=5V
VCCIF=2.0V
VCCIF=5V
(VCC2, VBAT)
-0.3V
VCC1=2.0V
VCC1=5V
VCC1=2.0V
VCC1=5V
VCC2=2.0V
VCC2=5V
VCC2=2.0V
VCC2=5V
*Unless otherwise noted.
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MIN TYP
-100
-1
MAX
+500
1
0.4
0.4
UNITS NOTES
µA
µA
V
2
1.6
2.4
V
12
-100
µA
0.425
1.28
25.3
81
0.4
1.2
0.4
1
mA
4, 9
µA
3,9
mA
4, 10
µA
3, 10
DS1306
DC ELECTRICAL CHARACTERISTICS (cont’d)
(0°C to 70°C or –40°C to +85°C; VCC = 2.0 to 5.5V*)
PARAMETER
Battery Timekeeping Current
Battery Timekeeping Current (IND)
Trickle Charge Resistors
Trickle Charger Diode Voltage
Drop
SYMBOL
IBATT
VBAT=3V
IBATT
VBAT=3V
R1
R2
R3
VTD
MIN TYP
MAX
550
800
2
4
8
0.7
UNITS NOTES
nA
12
nA
12
kΩ
kΩ
kΩ
V
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
Crystal Capacitance
(tA = 25°C)
SYMBOL
CI
CO
CX
CONDITION
TYP
10
15
6
MAX
UNITS
pF
pF
pF
NOTES
3-WIRE AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C or –40°C to +85°C; VCC = 2.0V to 5.5V*)
PARAMETER
Data to CLK Setup
CLK to Data Hold
CLK to Data Delay
CLK Low Time
CLK High Time
CLK Frequency
CLK Rise and Fall
CE to CLK Setup
CLK to CE Hold
CE Inactive Time
CE to Output High Z
SCLK to Output High Z
SYMBOL
VCC=2.0V
tDC
VCC=5V
VCC=2.0V
tCDH
VCC=5V
VCC=2.0V
tCDD
VCC=5V
VCC=2.0V
tCL
VCC=5V
VCC=2.0V
tCH
VCC=5V
VCC=2.0V
tCLK
VCC=5V
VCC=2.0V
tR , t F
VCC=5V
VCC=2.0V
tCC
VCC=5V
VCC=2.0V
tCCH
VCC=5V
VCC=2.0V
tCWH
VCC=5V
VCC=2.0V
tCDZ
VCC=5V
VCC=2.0V
tCCZ
VCC=5V
*Unless otherwise noted.
14 of 20
MIN TYP
200
50
280
70
MAX
800
200
1000
250
1000
250
DC
0.6
2.0
2000
500
4
1
240
60
4
1
280
70
280
70
UNITS NOTES
ns
5, 6
ns
5, 6
ns
5, 6, 7
ns
6
ns
6
MHz
6
ns
µs
6
ns
6
µs
6
ns
5, 6
ns
5, 6
DS1306
TIMING DIAGRAM: 3-WIRE READ DATA TRANSFER Figure 12
TIMING DIAGRAM: 3-WIRE WRITE DATA TRANSFER Figure 13
15 of 20
DS1306
SPI AC ELECTRICAL CHARACTERISTICS
(0°C to 70°C or –40°C to +85°C; VCC = 2.0 to 5.5V*)
PARAMETER
Data to CLK Setup
CLK to Data Hold
CLK to Data Delay
CLK Low Time
CLK High Time
CLK Frequency
CLK Rise and Fall
CE to CLK Setup
CLK to CE Hold
CE Inactive Time
CE to Output High Z
SYMBOL
VCC=2.0V
tDC
VCC=5V
VCC=2.0V
tCDH
VCC=5V
VCC=2.0V
tCDD
VCC=5V
VCC=2.0V
tCL
VCC=5V
VCC=2.0V
tCH
VCC=5V
VCC=2.0V
tCLK
VCC=5V
VCC=2.0V
tR , t F
VCC=5V
VCC=2.0V
tCC
VCC=5V
VCC=2.0V
tCCH
VCC=5V
VCC=2.0V
tCWH
VCC=5V
VCC=2.0V
tCDZ
VCC=5V
*Unless otherwise noted.
16 of 20
MIN TYP
200
50
280
70
MAX
800
200
1000
250
1000
250
DC
0.6
2.0
2000
500
4
1
240
60
4
1
280
70
UNITS NOTES
ns
5, 6
ns
5, 6
ns
5, 6, 7
ns
6
ns
6
MHz
6
ns
µs
6
ns
6
µs
6
ns
5, 6
DS1306
TIMING DIAGRAM: SPI READ DATA TRANSFER Figure 14
TIMING DIAGRAM: SPI WRITE DATA TRANSFER Figure 15
SCLK can be either polarity, timing shown for CPOL = 1.
17 of 20
DS1306
NOTES:
1. All voltages are referenced to ground.
2. Logic 0 voltages are specified at a sink current of 4 mA at VCC=5V and 1.5 mA at VCC=2.0V,
VOL=GND for capacitive loads.
3. ICC1T and ICC2T are specified with CE set to a logic 0.
4. ICC1A and ICC2A are specified with CE= VCC, SCLK=2 MHz (0-VCC) at VCC=5V; SCLK=500 kHz
(0-VCC) at VCC=2.0V.
5. Measured at VIH=2.0V or VIL=0.8V and 10 ms maximum rise and fall time.
6. Measured with 50 pF load.
7. Measured at VOH=2.4V or VOL=0.4V.
8. VCC=VCC1, when VCC1>VCC2+0.2V (typical); VCC=VCC2, when VCC2>VCC1.
9. VCC2=0V.
10. VCC1=0V.
11. VCC1<VBAT.
12. Logic 1 voltages are specified at a source current of 1 mA at VCC=5V and 0.4 mA at 2.0V,
VOH=VCC for capacitive loads.
13. VCCIF must be less than or equal to the largest of VCC1, VCC2, and VBAT.
18 of 20
DS1306
DS1306 16-PIN DIP (300-mil)
PKG
DIM
A IN.
MM
B IN.
MM
C IN.
MM
D IN.
MM
E IN.
MM
F IN.
MM
G IN.
MM
H IN.
MM
J IN.
MM
K IN.
MM
16-PIN
MIN
MAX
0.740
0.780
18.80
19.81
0.240
0.260
6.10
6.60
0.120
0.140
3.05
3.56
0.300
0.325
7.62
8.26
0.015
0.040
0.38
1.02
0.120
0.140
3.04
3.56
0.090
0.110
2.29
2.79
0.320
0.370
8.13
9.40
0.008
0.012
0.20
0.30
0.015
0.021
0.38
0.53
19 of 20
DS1306
DS1306 20-PIN TSSOP
DIM
A MM
A1 MM
A2 MM
C MM
L MM
e1 MM
B MM
D MM
E MM
G MM
H MM
phi
MIN
MAX
1.10
0.05
0.75
1.05
0.09
0.18
0.50
0.70
0.65 BSC
0.18
0.30
6.40
6.90
4.40 NOM
0.25 REF
6.25
6.55
0°
8°
20 of 20
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