Pdf Document English
MARC 4 MIDI
Hardware
Documentation
Version 1.0
Last Update 05-28-2002
© 05/2002 MARIAN. No part of this documentation may be reproduced or transmitted in any form or by any means without permission in
writing from Marian GbR.
Introduction........................................................................................................................... 2
Memory Ranges .................................................................................................................... 2
PLX Register (Memory Range 0, Read + Write).................................................................. 2
RAM (Memory Range 1, Read + Write)................................................................................ 2
FPGA WR Register (Memory Range 2, Write Only)............................................................ 3
Control (Base + 0x00) .......................................................................................................................................3
1) Play/Capture Enable ..................................................................................................................................3
2) Counter Reset ............................................................................................................................................4
3) Clock Generator Range .............................................................................................................................4
4) Clear Interrupt ............................................................................................................................................4
5) SyncBus Clock Mode .................................................................................................................................4
6) Run.............................................................................................................................................................4
7) Codec Select..............................................................................................................................................4
Internal Clock Generator (Base + 0x08)..........................................................................................................5
Codec Control (Base +0x08)............................................................................................................................5
Monitor Control (Base + 0x0C) ........................................................................................................................5
1) Input Select ................................................................................................................................................5
2) Playback/Monitoring...................................................................................................................................5
Midi Out 1 and Midi Out 2 (Base + 0x10 and Base + 0x14) ...........................................................................5
SyncBus Start/Stop Mode................................................................................................................................6
FPGA RD Register (Memory Range 2, Read Only)............................................................. 6
Counter (Base + 0x00) ......................................................................................................................................6
Status (Base + 0x08).........................................................................................................................................6
1) Midi Out Buffer Full ....................................................................................................................................6
2) Midi In Buffer Overlow................................................................................................................................7
3) Midi In Data Available.................................................................................................................................7
MIDI In 1 and Midi In 2 (Base + 0x08 und Base + 0x0C) ................................................................................7
FPGA Load (Memory Range 3, after Power Up or Local Reset) ....................................... 7
Initializing the Hardware....................................................................................................... 8
Contact the Developers........................................................................................................ 9
MARIAN Marc 4 Midi Hardware Documentation
2/9
Introduction
This document contains all technical information which are required to develop driver software for digital audio
processing based on the technical properties of the “MARC 4 Midi“.
Memory Ranges
The MARC 4 Midi provides 4 memory ranges, which are of interest for the audio functionality of the card.
The access to these memory ranges has to be done by DWORD accesses only.
Nr.
0
1
2
3
Length (Bytes)
128
131072
1024
512
Area
PLX-Register
RAM
FPGA WRRegister
FPGA RDRegister
FPGA Load
Use
Commentary
Configuration of the PCI-Bridge
Play and Capture Data
Control Register
All Write Only
Status Register
All Read Only
Loading the FPGA
Only available after:
Power Up or
local Reset
PLX Register (Memory Range 0, Read + Write)
This memory range provides the access to the registers of the PLX PCI-Bridge-Controllers. The memory address
of a register can be calculated by: base address of the memory range + register number.
The registers 0x4C and 0x50 are of main interest regarding interrupt and reset control. For further information
about the functionality of these registers please see the manufacturers documentation ‘plx.pdf'.
RAM (Memory Range 1, Read + Write)
The RAM occupies a memory range of 0x20000 bytes (128k) and serves for the exchange of the audio data
between card and driver software.
Address
0x00000000
0x00004000
0x00008000
0x0000C000
0x00010000
0x00014000
0x00018000
0x0001C000
Hardware Audio Buffer
Analog Play Channel 1
Analog Play Channel 2
Analog Play Channel 3
Analog Play Channel 4
Analog Record Channel 1
Analog Record Channel 2
Analog Record Channel 3
Analog Record Channel 4
The hardware audio buffer of each channel has a length of 16 Kbytes and is 32 bit mono sample aligned.
Only the Bits 0..23 of any 32 Bit mono sample can be used for the audio data.
Samples are always to write and read MSB justified (highest bit = D23).
You will find sample code for audio data transfer in file „transfer.pas“.
MARIAN Marc 4 Midi Hardware Documentation
3/9
FPGA WR Register (Memory Range 2, Write Only)
All signals are general H-active. After the FPGA initialization all registers are set to 0.
Address
Register
(Base + n)
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
Control
Internal Clock Generator
Codec Control
Monitor Control
MIDI Out 1
MIDI Out 2
SyncBus Start/Stop Mode
Control (Base + 0x00)
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Analog Play
Analog Capture
Analog Play
Analog Capture
Clock Generator
“
Clear Interrupt
SyncBus
Analog Play
Analog Capture
Codec
''
-
Enable
''
Counter Reset
''
Range
''
Clock Mode
''
Run
''
Select
''
1)
2)
3)
4)
5)
6)
7)
1) Play/Capture Enable
Setting the respective bits causes the activation of the appropriate devices. Since the SyncBus–Feature is
available, Play/Capture Enable will NOT start recording or playing of the devices. The device will remain in a kind
of „standby“ mode and gets started only if the Run-Bit is set or a start is signaled by the SyncBus (when in
SyncBus-Slave-Mode.)
Resetting the respective bits disables the appropriate devices. A running recording or playback stops even if
there is no stop signaled via „Run“ or SyncBus.
„Enable“ and „Run“/“Start of the SyncBus“ are always logical AND combined.
For sample code see the file „control.pas“ under „_EnablePlay“, „_EnableRec“.
MARIAN Marc 4 Midi Hardware Documentation
4/9
2) Counter Reset
To set the sample Counter of the respective devices to zero, the appropriate bit has to be set.
The counter receives the value 0 and will be blocked until the appropriate bit is set again.
For sample code see the file „control.pas“ under „_Reset“.
3) Clock Generator Range
Depending on the required sample rate, first the appropriate operating range has to be set for the internal clock
generator.
Bit
1
1
1
0
0
0
1
0
1
0
6..14 kHz
12..29 kHz
24..58 kHz
47..115 kHz
For sample code see the file „control.pas“ under „SetDcoRate“.
4) Clear Interrupt
After an interrupt occurred, your interrupt service routine has to clear it on the card. It will be cleared after setting
and subsequently resetting this bit. For sample code see the file „isr.asm“
5) SyncBus Clock Mode
The SyncBus ensures that several MARIAN SyncBus compatible audio cards run synchronously. These Bits
allow the configuration of the cards clock behavior towards the SyncBus.
The software must ensure, that while operating several cards parallel, only one of them outputs a clock to the
SyncBus. If there is at least one card configured as clock slave, one other card has to be configured as clock
master.
Bit
10
00
01
11
Autonomous (SyncBus clock independently)
Slave (clock is determined by the SyncBus clock)
Master (internal clock is the master clock for the SyncBus)
6) Run
These bits together with the Enable-Bit start the recording or playback of a device. Within the SyncBus-MasterMode the start signal will be generated on the SyncBus, in such a way as to enable the pending slave devices
with active Enable-Bit to start.
For sample code see the data „control.pas“ under „_Start“.
7) Codec Select
Before writing any control sequences to the codecs, the destination codec(s) has to be determined. That’s the
task of these bits.
Bit
3210
0 0 0 1 Codec 1 (Channels 1-2)
0 0 1 0 Codec 2 (Channels 3-4)
MARIAN Marc 4 Midi Hardware Documentation
5/9
Internal Clock Generator (Base + 0x08)
These settings determine the frequency of the internal clock generator. This generator produces the master clock
for the given sample rate.
Bit 0..15
Master Frequency Value
This values has to be calculated:
Master Frequency Value = Sample Rate * 0.0524288
Additionally the appropriate operating range has to be set for internal clock generator. (see Clock Generator
Range).
For sample code see the data „control.pas“ under „SetDcoRate“.
Codec Control (Base +0x08)
By use of this control register you have access to the internal registers of the codecs (AK4524). Writing into this
register initiates a serialization and transmission process of the given value for a given register. The control
sequence consists of a dword with the following structure:
Bit
0..7
8..11
12
13
14
15
16..31
Value for Codec Register
Codec Register Number
0
1
0
1
0
The destination codec(s) will be determined by the Codec Select Bits.
Between two writes accesses a pause of minimum 4µs must be ensured.
The documentation of all codec registers can be found in the manufacturers documentation „4524.pdf“.
Monitor Control (Base + 0x0C)
This register determines the signal source for the audio outputs.
Bit
0..1
2
3..4
5
Output 1-2
Output 1-2
Output 3-4
Output 3-4
Input select
Playback/Monitoring
Input select
Playback/Monitoring
1)
2)
1) Input Select
These bits determine the input channel pair, which will be monitored at the appropriate output in case of
monitoring is active.
Bit
01
00
01
Input 1-2
Input 3-4
2) Playback/Monitoring
Setting this bit causes the appropriate output to monitor the chosen input channel pair. Otherwise, the playback
signal can be heard at the output.
Midi Out 1 and Midi Out 2 (Base + 0x10 and Base + 0x14)
These two registers are the out ports for midi interface 1 (Base+0x10) and for midi interface 2 (Base+0x14).
Bit
7..0
Midi out data
MARIAN Marc 4 Midi Hardware Documentation
6/9
All midi out data are buffered by the hardware through a FIFO. Before a byte is written to an out register, the
state of the FIFO buffer should be checked.
SyncBus Start/Stop Mode
The SyncBus ensures that several MARIAN SyncBus compatible audio cards run synchronously. Through this
register, the devices start/stop behavior towards the SyncBus can be configured. For further information about
the configuration of the cards behavior towards the SyncBus please see SyncBus Clock/Mode.
Bit
0
1
2
3
Play Slave
Record Slave
Play Master
Record Master
If a device is configured as Slave and the Enable-Bit is set, it will start only if the SyncBus detects a start signal.
If a device is configured as Master, the setting of the appropriate Run-Bits will lead to a start signal at the
SyncBus.
A device has to be configured as Master and Slave, if you want to generate a SyncBus start signal and start the
device simultaneously.
If a device is configured neither as Master nor as Slave, it will be autonomous. For start and stop only the bits
Enable and Run will be used.
FPGA RD Register (Memory Range 2, Read Only)
Address
(Base + n)
0x00
0x04
0x08
0x0C
Register
Counter
Status
MIDI In 1
MIDI In 2
Counter (Base + 0x00)
By reading these counters you can get the current playback respectively record positions in relation to the base
memory address of the respective playback respectively record device.
Bit
9..0
19..10
Analog Play Counter
Analog Capture Counter
The counters represent the upper 10 bit of the internal 12 bit wide dword-counter. One step of this internal
counter represents a progress of one 32 bit mono sample. One step of the counters in this register represent a
progress of four 32 Bit mono samples.
Status (Base + 0x08)
Bit
0
1
2
3
4
5
6
7
Midi 1 Out Buffer Full
Midi 2 Out Buffer Full
Midi In 1 Buffer Overflow
Midi In 1 Data Available
Midi In 2 Buffer Overflow
Midi In 2 Data Available
1)
1)
2)
3)
2)
3)
1) Midi Out Buffer Full
This bit signals whether or not the output buffer is full. If it is set, then no midi output data should be written to the
appropriate midi output register. This bit should be read twice before assuming that it is valid.
MARIAN Marc 4 Midi Hardware Documentation
7/9
2) Midi In Buffer Overlow
This bit signals whether or not the midi input buffer has an overflow. If this bit is set, then it should be handled as
a midi input error. This occurs, if the software is not able to read the midi input register as fast as the midi data
come in. This bit becomes inactive if the next byte is read from the appropriate input buffer.
3) Midi In Data Available
This bit is set, if the midi input buffer is not empty. That means for the driver software, that midi in data can be
read from the appropriate midi input register.
MIDI In 1 and Midi In 2 (Base + 0x08 und Base + 0x0C)
By reading these registers, the midi input data can be received from the midi interface 1 (Base+0x08) or midi
interface 2 (Base+0x0C). All midi in data are buffered by the hardware through a FIFO. The state of this FIFO
should be considered before reading these registers and to recognize an error situation.
FPGA Load (Memory Range 3, after Power Up or Local Reset)
To give the MARC 4 Midi a functionality besides PnP, you have to load a control design into the FPGA. The
control design is stored in so-called BIT-Data files. The loading of a control design happens through a bit-serial
data stream at D0 of the FPGA Load address. You will find the control design for the “Marc 4 Midi” in the file
„marc4m.bit“.
For sample code to FPGA-Loading see the file “init.pas”
MARIAN Marc 4 Midi Hardware Documentation
8/9
Initializing the Hardware
Subsequently you will find the steps to initialize the hardware successfully. Afterwards the card will be ready for
recording and playback. For sample code see the file „init.pas“.
1.
Initialize the PCI Controller (see „InitPciController“)
2.
Release the reset of the hardware, initialize the FPGA (see „WriteConfigData“)
3.
Verify the success of the initialization (see „FpgaInitialized“)
4.
Set the Internal Clock Generator to a sample rate (i.e. 44100Hz)
5.
Initialize the analog codecs (see „InitADDA“). A description of all codec registers contains the manufacturer
documentation „4524.pdf“.
6.
Set the Output Routing for the devices. The software should provide the possibility to determine the Output
Routing. After restarting the system the software should restore these settings
7.
Define the volume settings for the devices (see „volume.pas“). The software should provide the possibility to
define the volume settings. After restarting the system the software should restore these settings.
8.
Define the SyncBus-Clock and SyncBus-Start/Stop settings. The software should provide the possibility to
define these settings. After restarting the system the software should restore these settings.
MARIAN Marc 4 Midi Hardware Documentation
Contact the Developers
Should you have any problems or questions please do not hesitate to contact:
Elektronik & Software Entwicklung
Eisenacher Strasse 72
04155 Leipzig
Email: [email protected]
9/9
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement