Mobile Intel 915 and 910 Express Chipset Family of Products ®

Mobile Intel 915 and 910 Express Chipset Family of Products ®
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Mobile Intel® 915 and 910 Express
Chipset Family of Products
Datasheet
April 2007
Document Number: 305264-002
Introduction
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Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Introduction
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Contents
1
Introduction ....................................................................................................................... 29
1.1
1.2
1.3
2
Overview............................................................................................................... 29
1.1.1
System Memory Interface..................................................................... 30
1.1.2
PCI Express* Based Graphics and Intel SDVO Interface..................... 30
1.1.3
Display Interface ................................................................................... 30
1.1.4
SDVO Interface..................................................................................... 30
1.1.5
DMI ....................................................................................................... 30
Terminology.......................................................................................................... 31
Reference Documents.......................................................................................... 34
Signal Description ............................................................................................................. 35
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Host Interface ....................................................................................................... 36
2.1.1
Host Interface Signals........................................................................... 36
2.1.2
Host Interface Reference and Compensation ...................................... 38
DDR DRAM Interface ........................................................................................... 39
2.2.1
DDR / DDR2 SDRAM Channel A Interface .......................................... 39
2.2.2
DDR / DDR2 SDRAM Channel B Interface .......................................... 41
2.2.3
DDR / DDR2 Common Signals............................................................. 43
2.2.4
DDR SDRAM Reference and Compensation....................................... 44
2.2.4.1
DDR / DDR2 Common Signal Mapping .............................. 44
PCI Express Based Graphics Interface Signals................................................... 45
2.3.1
Serial DVO and PCI Express Based Graphics Signal Mapping........... 46
DMI ....................................................................................................................... 47
Integrated Graphics Interface Signals.................................................................. 47
2.5.1
CRT DAC Signals ................................................................................. 47
2.5.2
Analog TV-out Signals .......................................................................... 48
2.5.3
LVDS Signals........................................................................................ 49
2.5.4
Serial DVO Interface............................................................................. 50
2.5.5
Display Data Channel (DDC) and GMBUS Support............................. 51
PLL Signals .......................................................................................................... 52
Reset and Miscellaneous Signals ........................................................................ 53
Power and Ground ............................................................................................... 54
Reset States and Pull-Up / Pull-Downs................................................................ 55
2.9.1
Host Interface Signals........................................................................... 56
2.9.2
Host Interface Reference and Compensation ...................................... 57
2.9.3
DDR / DDR2 SDRAM Channel A Interface .......................................... 57
2.9.4
DDR / DDR2 SDRAM Channel B Interface .......................................... 58
2.9.5
DDR / DDR2 Common Signals............................................................. 58
2.9.6
DDR SDRAM Reference and Compensation....................................... 59
2.9.7
PCI Express Based Graphics Interface Signals ................................... 59
2.9.8
DMI ....................................................................................................... 60
2.9.9
CRT DAC SIGNALS ............................................................................. 60
2.9.10 Analog TV-out Signals .......................................................................... 61
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
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Introduction
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2.9.11
2.9.12
2.9.13
2.9.14
3
GMCH Register Description.............................................................................................. 65
3.1
3.2
4
4
Configuration Process and Registers................................................................... 66
3.1.1
Platform Configuration Structure .......................................................... 66
3.1.2
General Routing Configuration Accesses ............................................ 67
3.1.3
Standard PCI Bus Configuration Mechanism ....................................... 67
3.1.4
Logical PCI Bus 0 Configuration Mechanism ....................................... 68
3.1.5
Primary PCI and Downstream Configuration Mechanism .................... 68
3.1.6
PCI Express Enhanced Configuration Mechanism .............................. 69
3.1.7
GMCH Configuration Cycle Flow Chart................................................ 71
I/O Mapped Registers .......................................................................................... 72
3.2.1
CONFIG_ADDRESS—Configuration Address Register ...................... 72
3.2.2
CONFIG_DATA—Configuration Data Register.................................... 73
Host Bridge Device 0 - Configuration Registers (D0:F0).................................................. 75
4.1
5
LVDS Signals........................................................................................ 62
Display Data Channel (DDC) and GMBUS Support............................. 63
PLL Signals........................................................................................... 63
Reset and Miscellaneous Signals......................................................... 64
Host Bridge Device 0 Configuration Register Space ........................................... 75
4.1.1
VID—Vendor Identification ................................................................... 76
4.1.2
DID—Device Identification.................................................................... 76
4.1.3
PCICMD—PCI Command .................................................................... 76
4.1.4
PCISTS—PCI Status ............................................................................ 77
4.1.5
RID—Revision Identification ................................................................. 78
4.1.6
CC—Class Code .................................................................................. 79
4.1.7
MLT—Master Latency Timer ................................................................ 80
4.1.8
HDR—Header Type.............................................................................. 80
4.1.9
SVID—Subsystem Vendor Identification .............................................. 80
4.1.10 SID—Subsystem Identification ............................................................. 81
4.1.11 CAPPTR—Capabilities Pointer ............................................................ 81
4.1.12 EPBAR—Egress Port Base Address.................................................... 82
4.1.13 MCHBAR—GMCH Register Range Base Address.............................. 83
4.1.14 PCIEXBAR—PCI Express Register Range Base Address .................. 84
4.1.15 DMIBAR—DMI Root Complex Register Range Base Address............ 85
4.1.16 GGC-GMCH Graphics Control Register (Device 0) ............................. 86
4.1.17 DEVEN—Device Enable....................................................................... 87
4.1.18 PAM0—Programmable Attribute Map 0 ............................................... 88
4.1.19 PAM1—Programmable Attribute Map 1 ............................................... 89
4.1.20 PAM2—Programmable Attribute Map 2 ............................................... 90
4.1.21 PAM3—Programmable Attribute Map 3 ............................................... 91
4.1.22 PAM4—Programmable Attribute Map 4 ............................................... 92
4.1.23 PAM5—Programmable Attribute Map 5 ............................................... 93
4.1.24 PAM6—Programmable Attribute Map 6 ............................................... 94
4.1.25 LAC—Legacy Access Control .............................................................. 95
4.1.26 TOLUD—Top of Low Used DRAM Register ........................................ 96
4.1.27 SMRAM—System Management RAM Control ..................................... 97
4.1.28 ESMRAMC—Extended System Management RAM Control................ 98
4.1.29 ERRSTS—Error Status ........................................................................ 99
4.1.30 ERRCMD—Error Command............................................................... 100
4.1.31 SKPD—Scratchpad Data (D0:F0) ...................................................... 101
4.1.32 CAPID0—Capability Identifier............................................................. 101
Device #0 Memory Mapped I/O Register........................................................................ 102
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Introduction
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5.1
5.2
5.3
5.4
MCHBAR Registers Device #0 .......................................................................... 102
Device #0 MCHBAR Chipset Control Register Space ....................................... 102
5.2.1
HIC Host Interface Configuration Register ......................................... 104
5.2.2
HIT1—Host Interface Test_1 .............................................................. 104
5.2.3
C0DRB0—Channel 0 DRAM Rank Boundary 0................................. 105
5.2.4
C0DRB1—Channel 0 DRAM Rank Boundary 1................................. 105
5.2.5
C0DRB2—Channel 0 DRAM Rank Boundary 2................................. 105
5.2.6
C0DRB3—Channel 0 DRAM Rank Boundary 3................................. 106
5.2.7
C0DRA0—Channel 0 DRAM Rank 0,1 Attribute................................ 106
5.2.8
C0DRA2—Channel 0 DRAM Rank 2,3 Attribute................................ 107
5.2.9
C0DCLKDIS—Channel 0 DRAM Clock Disable................................. 107
5.2.10 C0BNKARC—Channel 0 DRAM Bank Architecture........................... 108
5.2.11 C0DRT0—Channel 0 DRAM Timing Register 0................................. 109
5.2.12 C0DRT1—Channel 0 DRAM Timing Register 1................................. 113
5.2.13 C0DRT2—Channel 0 DRAM Timing Register 2................................. 115
5.2.14 C0DRC0––Channel 0 DRAM Controller Mode 0 ............................... 116
5.2.15 C0DRC1––Channel 0 DRAM Controller Mode 1 ............................... 118
5.2.16 C0DRC2––Channel 0 DRAM Controller Mode 2 ............................... 119
5.2.17 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 .................. 119
5.2.18 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 .................. 119
5.2.19 C1DRB2—Channel 1 DRAM Rank Boundary Address 2 .................. 119
5.2.20 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 .................. 120
5.2.21 C1DRA0—Channel 1 Dram Rank 0,1 Attribute.................................. 120
5.2.22 C1DRA2—Channel 1 Dram Rank 2,3 Attribute.................................. 120
5.2.23 C1DCLKDIS—Channel 1 DRAM Clock Disable................................. 120
5.2.24 C1BNKARC—Channel 1 Bank Architecture ...................................... 120
5.2.25 C1DRT0—Channel 1 DRAM Timing Register 0................................. 121
5.2.26 C1DRT1—Channel 1 DRAM Timing Register 1................................. 121
5.2.27 C1DRT2—Channel 1 DRAM Timing Register 2................................. 121
5.2.28 C1DRC0—Channel 1 DRAM Controller Mode 0................................ 121
5.2.29 C1DRC1—Channel 1 DRAM Controller Mode 1................................ 121
5.2.30 C1DRC2––Channel 1 DRAM Controller Mode 2 ............................... 122
5.2.31 DCC—DRAM Channel Control........................................................... 122
5.2.32 Device #0 MCHBAR Clock Controls................................................... 123
5.2.33 CLKCFG—Clocking Configuration ..................................................... 123
5.2.34 CPCTL—CPunit Control ..................................................................... 123
Device #0 MCHBAR ACPI Power Management Controls ................................. 124
5.3.1
PMSLFRFC—Dram Self Refresh Control .......................................... 124
5.3.2
DSDLLPDC—Dram Slave DLL Power Down Control ........................ 124
5.3.3
DMDLLPDC—Dram Master DLL Power Down Control ..................... 126
5.3.4
PMCFG—Power Management Configuration .................................... 127
5.3.5
PMSTS—Power Management Status ................................................ 128
5.3.6
DMICC—DMI Countdown Control...................................................... 129
DMI RCRB.......................................................................................................... 130
5.4.1
DMI Register Summary ...................................................................... 130
5.4.2
DMIVCECH—DMI Virtual Channel Enhanced Capability Header ..... 131
5.4.3
DMIPVCCAP1—DMI Port VC Capability Register 1 .......................... 131
5.4.4
DMIPVCCAP2—DMI Port VC Capability Register 2 .......................... 132
5.4.5
DMIPVCCTL—DMI Port VC Control .................................................. 132
5.4.6
DMIVC0RCAP—DMI VC0 Resource Capability ................................ 133
5.4.7
DMIVC0RCTL0—DMI VC0 Resource Control ................................... 134
5.4.8
DMIVC0RSTS—DMI VC0 Resource Status....................................... 134
5.4.9
DMIVC1RCAP—DMI VC1 Resource Capability ................................ 135
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
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Introduction
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5.4.10
5.4.11
5.4.12
5.4.13
5.4.14
5.4.15
5.4.16
5.4.17
5.4.18
5.4.19
5.4.20
5.4.21
6
PCI Express Graphics Device 1 Configuration Registers (D1:F0) ................................. 144
6.1
6.2
6
DMIVC1RCTL1—DMI VC1 Resource Control ................................... 135
DMIVC1RSTS—DMI VC1 Resource Status....................................... 136
DMILCAP—DMI Link Capabilities ...................................................... 136
DMILCTL—DMI Link Control .............................................................. 137
DMILSTS—DMI Link Status ............................................................... 138
Egress Port (EP) RCRB...................................................................... 138
EP Register Summary ........................................................................ 138
EPESD—EP Element Self Description............................................... 140
EPLE1D—EP Link Entry 1 Description .............................................. 140
EPLE1A—EP Link Entry 1 Address ................................................... 141
EPLE2D—EP Link Entry 2 Description .............................................. 141
E2A—EP Link Entry 2 Address .......................................................... 142
PEG Device 1 Configuration Register Summary ............................................... 145
PEG Device 1 Configuration Register Details.................................................... 147
6.2.1
VID1—Vendor Identification ............................................................... 147
6.2.2
DID1—Device Identification................................................................ 147
6.2.3
PCICMD1—PCI Command ................................................................ 148
6.2.4
PCISTS1—PCI Status ........................................................................ 150
6.2.5
RID1—Revision Identification ............................................................. 151
6.2.6
CC1—Class Code .............................................................................. 151
6.2.7
CL1—Cache Line Size ....................................................................... 152
6.2.8
HDR1—Header Type.......................................................................... 152
6.2.9
PBUSN1—Primary Bus Number ........................................................ 152
6.2.10 SBUSN1—Secondary Bus Number ................................................... 153
6.2.11 SUBUSN1—Subordinate Bus Number............................................... 153
6.2.12 IOBASE1—I/O Base Address............................................................. 154
6.2.13 IOLIMIT1—I/O Limit Address.............................................................. 154
6.2.14 SSTS1—Secondary Status ................................................................ 155
6.2.15 MBASE1—Memory Base Address ..................................................... 156
6.2.16 MLIMIT1—Memory Limit Address ...................................................... 157
6.2.17 PMBASE1—Prefetchable Memory Base Address ............................. 158
6.2.18 PMLIMIT1—Prefetchable Memory Limit Address .............................. 159
6.2.19 CAPPTR1—Capabilities Pointer ........................................................ 159
6.2.20 INTRLINE1—Interrupt Line................................................................. 160
6.2.21 INTRPIN1—Interrupt Pin .................................................................... 160
6.2.22 BCTRL1—Bridge Control ................................................................... 161
6.2.23 PM_CAPID1—Power Management Capabilities................................ 163
6.2.24 PM_CS1—Power Management Control/Status ................................. 164
6.2.25 SS_CAPID—Subsystem ID and Vendor ID Capabilities.................... 165
6.2.26 SS—Subsystem ID and Subsystem Vendor ID.................................. 166
6.2.27 MSI_CAPID—Message Signaled Interrupts Capability ID ................. 166
6.2.28 MC—Message Control ....................................................................... 167
6.2.29 MA—Message Address ...................................................................... 167
6.2.30 MD—Message Data ........................................................................... 168
6.2.31 PEG_CAPL—PCI Express Based Graphics Capability List............... 168
6.2.32 PEG_CAP—PCI Express*Based Graphics Capabilities .................... 169
6.2.33 DCAP—Device Capabilities................................................................ 169
6.2.34 DCTL—Device Control ....................................................................... 170
6.2.35 DSTS—Device Status ........................................................................ 171
6.2.36 LCAP—Link Capabilities..................................................................... 172
6.2.37 LCTL—Link Control ............................................................................ 173
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Introduction
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6.2.38
6.2.39
6.2.40
6.2.41
6.2.42
6.2.43
6.2.44
6.2.45
6.2.46
6.2.47
6.2.48
6.2.49
6.2.50
6.2.51
6.2.52
6.2.53
6.2.54
6.2.55
6.2.56
6.2.57
6.2.58
6.2.59
7
LSTS—Link Status ............................................................................. 174
SLOTCAP—Slot Capabilities.............................................................. 175
SLOTCTL—Slot Control ..................................................................... 176
SLOTSTS—Slot Status ...................................................................... 177
RCTL—Root Control........................................................................... 178
RSTS—Root Status............................................................................ 179
PEGLC—PCI Express* Based Graphics Legacy Control .................. 180
VCECH—Virtual Channel Enhanced Capability Header.................... 181
PVCCAP1—Port VC Capability Register 1 ........................................ 181
PVCCAP2—Port VC Capability Register 2 ........................................ 182
PVCCTL—Port VC Control................................................................. 182
VC0RCAP—VC0 Resource Capability............................................... 183
VC0RCTL—VC0 Resource Control.................................................... 183
VC0RSTS—VC0 Resource Status..................................................... 184
VC1RCAP—VC1 Resource Capability............................................... 184
VC1RCTL—VC1 Resource Control.................................................... 185
VC1RSTS—VC1 Resource Status..................................................... 186
RCLDECH—Root Complex Link Declaration Enhanced Capability
Header ................................................................................................ 186
ESD—Element Self Description ......................................................... 187
LE1D—Link Entry 1 Description ......................................................... 188
LE1A—Link Entry 1 Address .............................................................. 188
PEGSSTS—PCI Express Graphics Sequence Status ....................... 189
Internal Graphics Device #2 Configuration Register (D2:F0) ......................................... 190
7.1
7.2
Device #2: Function 0 Register Summary.......................................................... 191
Device #2: Function 0 Configuration Register Details ....................................... 191
7.2.1
VID2—Vendor Identification ............................................................... 193
7.2.2
DID2—Device Identification................................................................ 193
7.2.3
PCICMD2—PCI Command ................................................................ 194
7.2.4
PCISTS2—PCI Status ........................................................................ 195
7.2.5
RID2—Revision Identification ............................................................. 196
7.2.6
CC—Class Code ................................................................................ 196
7.2.7
CLS—Cache Line Size ....................................................................... 197
7.2.8
MLT2—Master Latency Timer ............................................................ 197
7.2.9
HDR2—Header Type.......................................................................... 198
7.2.10 MMADR—Memory Mapped Range Address ..................................... 198
7.2.11 IOBAR—I/O Base Address................................................................. 199
7.2.12 GMADR—Graphics Memory Range Address .................................... 200
7.2.13 GTTADR—Graphics Translation Table Range Address.................... 201
7.2.14 SVID2—Subsystem Vendor Identification .......................................... 201
7.2.15 SID2—Subsystem Identification ......................................................... 202
7.2.16 ROMADR—Video BIOS ROM Base Address .................................... 202
7.2.17 CAPPOINT—Capabilities Pointer....................................................... 203
7.2.18 INTRLINE—Interrupt Line................................................................... 203
7.2.19 INTRPIN—Interrupt Pin ...................................................................... 203
7.2.20 MINGNT—Minimum Grant ................................................................. 204
7.2.21 MAXLAT—Maximum Latency............................................................. 204
7.2.22 MCAPPTR—Mirror of Dev0 Capability Pointer (Mirrored_D0_34)..... 204
7.2.23 MCAPID—Mirror of Dev0 Capability Identification (Mirrored_D0_E0)204
7.2.24 MGGC—Mirror of Dev0 GMCH Graphics Control (Mirrored_D0_52) 205
7.2.25 MDEVENdev0f0—Mirror of Dev0 Device Enable (Mirrored_D0_54) . 205
7.2.26 BSM—Base of Stolen Memory ........................................................... 205
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
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Introduction
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7.3
8
System Address Map ...................................................................................................... 224
8.1
8.2
8
7.2.27 MSAC—Multi Size Aperture Control................................................... 206
7.2.28 GDRST—Graphics Debug Reset (D2:F0).......................................... 206
7.2.29 PMCAPID—Power Management Capabilities ID ............................... 207
7.2.30 PMCAP—Power Management Capabilities ....................................... 207
7.2.31 PMCS—Power Management Control/Status...................................... 208
7.2.32 SWSMI—Software SMI ...................................................................... 208
7.2.33 GCFGC—Graphics Clock Frequency and Gating Control ................. 209
7.2.34 LBB—Legacy Backlight Brightness .................................................... 210
7.2.35 ASLS—ASL Storage........................................................................... 211
7.2.36 Device #2 Function 1 Configuration Register Details......................... 212
7.2.37 VID2—Vendor Identification ............................................................... 213
7.2.38 DID2—Device Identification................................................................ 213
7.2.39 PCICMD2—PCI Command ................................................................ 214
7.2.40 PCISTS2—PCI Status ........................................................................ 215
7.2.41 RID2—Revision Identification ............................................................. 216
7.2.42 CC—Class Code Register .................................................................. 216
7.2.43 CLS—Cache Line Size ....................................................................... 216
7.2.44 MLT2—Master Latency Timer ............................................................ 216
7.2.45 HDR2—Header Type Register ........................................................... 217
7.2.46 MMADR—Memory Mapped Range Address ..................................... 217
7.2.47 SVID2—Subsystem Vendor Identification .......................................... 217
7.2.48 SID2—Subsystem Identification ......................................................... 218
7.2.49 ROMADR—Video BIOS ROM Base Address .................................... 218
7.2.50 CAPPOINT—Capabilities Pointer....................................................... 218
7.2.51 MINGNT—Minimum Grant Register................................................... 218
7.2.52 MAXLAT—Maximum Latency............................................................. 218
7.2.53 MCAPPTR—Mirror of Dev0 Capability Pointer (Mirrored_D0_34)..... 219
7.2.54 MCAPID—Mirror of Dev0 Capability Identification (Mirrored_D0_E0)219
7.2.55 MGGC—Mirror of Dev0 GMCH Graphics Control (Mirrored_D0_52) 219
7.2.56 MDEVENdev0f0—Mirror of Dev0 Device Enable (Mirrored_D0_54) . 219
7.2.57 BSM—Base of Stolen Memory Register ............................................ 219
7.2.58 PMCAPID—Power Management Capabilities ID ............................... 220
7.2.59 PMCAP—Power Management Capabilities ....................................... 220
7.2.60 PMCS—Power Management Control/Status...................................... 220
7.2.61 SWSMI—Software SMI ...................................................................... 221
7.2.62 LBB—Legacy Backlight Brightness .................................................... 221
7.2.63 ASLS—ASL Storage........................................................................... 221
Device #2 – PCI I/O Registers ........................................................................... 221
7.3.1
MMIO Index—MMIO Address Register .............................................. 222
7.3.2
MMIO Data—MMIO Data Register..................................................... 222
Legacy Address Range ...................................................................................... 226
8.1.1
DOS Range (0h – 9_FFFFh) .............................................................. 227
8.1.2
Legacy Video Area (A_0000h-B_FFFFh) ........................................... 227
8.1.3
Expansion Area (C_0000h-D_FFFFh)................................................ 228
8.1.4
Extended System BIOS Area (E_0000h-E_FFFFh)........................... 228
8.1.5
System BIOS Area (F_0000h-F_FFFFh)............................................ 229
8.1.6
Programmable Attribute Map (PAM) Memory Area Details................ 229
Main Memory Address Range (1 MB to TOLUD) .............................................. 230
8.2.1
ISA Hole (15 MB-16 MB) .................................................................... 230
8.2.2
TSEG .................................................................................................. 231
8.2.3
Pre-allocated Memory......................................................................... 231
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Introduction
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8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
9
Host Interface.................................................................................................................. 242
9.1
9.2
9.3
9.4
9.5
9.6
9.7
10
PCI Express Memory Address Range (TOLUD – 4GB) .................................... 232
8.3.1
APIC Configuration Space (FEC0_0000h-FECF_FFFFh) ................. 234
8.3.2
HSEG (FEDA_0000h-FEDB_FFFFh)................................................. 234
8.3.3
FSB Interrupt Memory Space (FEE0_0000-FEEF_FFFF) ................. 234
8.3.4
High BIOS Area .................................................................................. 234
PCI Express Configuration Address Space ....................................................... 235
8.4.1
PCI Express Graphics Attach ............................................................. 235
8.4.2
AGP DRAM Graphics Aperture .......................................................... 235
Graphics Memory Address Ranges (Intel Integrated Graphics Chipsets Only) 236
System Management Mode (SMM) ................................................................... 236
8.6.1
SMM Space Definition ........................................................................ 237
SMM Space Restrictions .................................................................................... 237
8.7.1
SMM Space Combinations ................................................................. 238
8.7.2
SMM Control Combinations................................................................ 238
8.7.3
SMM Space Decode and Transaction Handling ................................ 238
8.7.4
CPU WB Transaction to an Enabled SMM Address Space ............... 238
Memory Shadowing............................................................................................ 239
I/O Address Space ............................................................................................. 239
8.9.1
PCI Express I/O Address Mapping..................................................... 240
GMCH Decode Rules and Cross-Bridge Address Mapping .............................. 240
8.10.1 Legacy VGA and I/O Range Decode Rules ....................................... 240
FSB Source Synchronous Transfers.................................................................. 242
FSB IOQ Depth .................................................................................................. 242
FSB OOQ Depth ................................................................................................ 242
FSB GTL+ Termination ...................................................................................... 242
FSB Dynamic Bus Inversion............................................................................... 243
FSB Interrupt Overview ...................................................................................... 243
APIC Cluster Mode support................................................................................ 243
Functional Description .................................................................................................... 244
10.1
10.2
Host Interface ..................................................................................................... 244
10.1.1 FSB GTL+ Termination....................................................................... 244
10.1.2 FSB Dynamic Bus Inversion ............................................................... 244
10.1.3 APIC Cluster Mode support ................................................................ 245
System Memory Controller................................................................................. 245
10.2.1 Memory Channel Organization Modes ............................................... 247
10.2.1.1 Interleaved (Symmetric) Mode .......................................... 247
10.2.1.2 Asymmetric Mode.............................................................. 247
10.2.1.3 DRAM Address Mapping................................................... 248
10.2.2 DRAM Technologies and Organization .............................................. 252
10.2.2.1 Supported SO-DIMM types ............................................... 252
10.2.2.2 Rules for Populating SO-DIMM Slots................................ 253
10.2.2.3 Pin Connectivity for Single and Dual Channel Modes ...... 253
10.2.3 System Memory Configuration Registers Overview........................... 254
10.2.4 DRAM Clock Generation .................................................................... 254
10.2.5 DDR2 On-Die Termination.................................................................. 255
10.2.6 DDR2 Off Chip Driver Impedance Calibration.................................... 255
10.2.7 DRAM Power Management ................................................................ 255
10.2.7.1 Dynamic Row Power Down Operation.............................. 255
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10.3
10.4
10.5
10.6
10.7
10.8
10
PCI Express Interface (Intel® 915GM/915GME/915PM Only) ........................... 256
10.3.1 Layering Overview .............................................................................. 256
10.3.2 Transaction Layer ............................................................................... 256
10.3.3 Data Link Layer................................................................................... 256
10.3.4 Physical Layer..................................................................................... 257
Intel® Serial Digital Video Output (SDVO) (Intel
915GM/915GME/910GML/910GMLE/915GMS Only) ....................................... 257
10.4.1 Intel® SDVO Capabilities .................................................................... 257
10.4.2 Intel® SDVO Modes ............................................................................ 258
Integrated Graphics Controller
(Intel® 915GM/915GME/910GML/915GMS Only).............................................. 258
10.5.1 Integrated Graphics Engine Overview................................................ 259
3D Engine (Intel® 915GM/915GME/910GML/910GMLE/ 915GMS Only) ......... 259
10.6.1 Setup Engine ...................................................................................... 259
10.6.1.1 3D Primitives and Data Formats Support.......................... 259
10.6.1.2 Pixel Accurate “Fast” Scissoring and Clipping Operation . 260
10.6.1.3 Depth Bias ......................................................................... 260
10.6.1.4 Backface Culling................................................................ 260
10.6.1.5 Scan Converter ................................................................. 260
10.6.1.6 Pixel Rasterization Rules .................................................. 260
10.6.2 Texture Engine.................................................................................... 260
10.6.2.1 Perspective Correct Texture Support................................ 261
10.6.2.2 Texture Formats and Storage ........................................... 261
10.6.2.3 Texture Decompression .................................................... 261
10.6.2.4 Texture ChromaKey .......................................................... 261
10.6.2.5 Anti-Aliasing....................................................................... 261
10.6.2.6 Texture Map Filtering ........................................................ 262
10.6.2.7 Multiple Texture Composition............................................ 262
10.6.2.8 Bi-Cubic Filter (4x4 Programmable Texture Filter) ........... 262
10.6.2.9 Cubic Environment Mapping ............................................. 263
10.6.3 Raster Engine ..................................................................................... 263
10.6.3.1 Texture Map Blending ....................................................... 263
10.6.3.2 Combining Intrinsic and Specular Color Components ...... 263
10.6.3.3 Color Shading Modes........................................................ 264
10.6.3.4 Color Dithering .................................................................. 264
10.6.3.5 Vertex and Per Pixel Fogging............................................ 264
10.6.3.6 Alpha Blending (Frame Buffer).......................................... 264
10.6.3.7 Microsoft Direct X* API and SGI OpenGL Logic Ops ....... 265
10.6.3.8 Color Buffer Formats: 8-, 16-, or 32-bits per pixel
(Destination Alpha)............................................................ 265
10.6.3.9 Depth Buffer ...................................................................... 265
10.6.3.10 Stencil Buffer ..................................................................... 266
10.6.3.11 Projective Textures............................................................ 266
2D Engine (Intel® 915GM/915GME/910GML/910GMLE/ 915GMS Only) ......... 266
10.7.1 GMCH VGA Registers ........................................................................ 266
10.7.2 2D Functionality .................................................................................. 266
10.7.2.1 Block Level Transfer (BLT) Function................................ 266
10.7.2.2 Logical 128-bit Fixed BLT and 256-bit Fill Engine ............ 267
Video Engine (Intel® 915GM/915GME/910GML/ 910GMLE/915GMS Only)..... 268
10.8.1 Hardware Motion Compensation ........................................................ 268
10.8.2 Sub-Picture Support ........................................................................... 268
10.8.3 De-interlacing Support ........................................................................ 268
10.8.3.1 Dynamic Bob and Weave.................................................. 269
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10.9
Display Interfaces
(Intel® 915GM/915GME/910GML/ 910GMLE/915GMS Only) ........................... 269
10.9.1 Display Overview ................................................................................ 269
10.9.2 Planes ................................................................................................. 270
10.9.2.1 Display Plane..................................................................... 270
10.9.2.2 Cursor A/B Plane............................................................... 270
10.9.2.3 Cursor Color Formats........................................................ 270
10.9.2.4 Popup Cursor .................................................................... 271
10.9.2.5 Overlay Plane .................................................................... 271
10.9.2.6 Dynamic Bob and Weave.................................................. 272
10.9.2.7 VGA Plane......................................................................... 273
10.9.3 Display Pipes ...................................................................................... 273
10.9.4 Clock Generator Units (DPLL)............................................................ 273
10.10 Display Ports (Intel® 915GM/915GME/910GML/ 910GMLE/915GMS Only) ..... 274
10.10.1 Analog Display Port Characteristics ................................................... 275
10.10.1.1 Integrated RAMDAC.......................................................... 275
10.10.1.2 Sync Signals...................................................................... 275
10.10.1.3 VESA/VGA Mode .............................................................. 275
10.10.1.4 DDC (Display Data Channel) ............................................ 276
10.10.2 Dedicated TV Out Port........................................................................ 276
10.10.2.1 Connectors ........................................................................ 276
10.10.2.2 Composite Video Connector ............................................. 276
10.10.2.3 S-Video Connector ............................................................ 277
10.10.2.4 Component Analog YUV connector .................................. 277
10.10.2.5 Content Protection............................................................. 277
10.10.3 Dedicated LFP LVDS Port .................................................................. 277
10.10.4 LVDS panel support............................................................................ 278
10.10.5 LVDS Interface Signals....................................................................... 278
10.10.6 LVDS Data Pairs and Clock Pairs ...................................................... 279
10.10.7 LVDS Pair States ................................................................................ 280
10.10.8 Single Channel versus Dual Channel Mode....................................... 280
10.10.9 LVDS Channel Skew .......................................................................... 280
10.10.10 LVDS PLL ........................................................................................... 280
10.10.11 SSC Support ....................................................................................... 280
10.10.12 Panel Power Sequencing ................................................................... 281
10.10.12.1 Panel Power Sequence States ......................................... 281
10.10.12.2 Back Light Inverter Control................................................ 283
10.10.13 SDVO Digital Display Port .................................................................. 283
10.10.13.1 TMDS Capabilities............................................................. 284
10.10.13.2 LVDS Capabilities ............................................................. 284
10.10.13.3 TV-Out Capabilities
(not supported by the Intel 915GME/Intel 910GMLE)....... 284
10.10.14 Control Bus ......................................................................................... 285
10.10.15 Intel SDVO Modes .............................................................................. 285
10.11 Multiple Display Configurations.......................................................................... 286
10.12 Power Management ........................................................................................... 286
10.12.1 Power Management Overview ........................................................... 286
10.12.2 ACPI States Overview ........................................................................ 286
10.12.2.1 System............................................................................... 286
10.12.2.2 CPU ................................................................................... 287
10.12.2.3 Internal Graphics Display Device Control ......................... 287
10.12.2.4 Internal Graphics Adapter ................................................. 287
10.12.2.5 PCI Express Link States.................................................... 287
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10.13 Thermal Management ........................................................................................ 288
10.13.1 Internal Thermal Sensor ..................................................................... 288
10.13.1.1 Trip Points ......................................................................... 289
10.13.1.2 Thermometer ..................................................................... 289
10.13.2 Sample Programming Model .............................................................. 289
10.13.2.1 Setting the “Hot” Temperature Trip Point .......................... 289
10.13.3 Trip Point Temperature Targets ......................................................... 290
10.13.4 Thermal Sensor Accuracy .................................................................. 290
10.13.5 Thermal Throttling Options ................................................................. 291
10.13.6 THRMTRIP Operation ........................................................................ 291
10.14 Clocking.............................................................................................................. 291
10.14.1 Overview ............................................................................................. 291
10.14.2 GMCH Reference Clocks ................................................................... 292
10.14.3 Host/Memory/Graphics Core Clock Frequency Support .................... 292
10.14.3.1 Intel 915GM Host/Memory/Graphics Clock Support ......... 292
10.14.3.2 Intel 915GMS Host/Memory/Graphics Clock Support....... 292
10.14.3.3 Intel 910GML Host/Memory/Graphics Clock Support ....... 292
11
Electrical Characteristics................................................................................................. 293
11.1
11.2
11.3
11.4
12
GMCH Strap Pins............................................................................................................ 309
12.1
13
Mobile Intel 915 and 910 Express Chipset Family Strapping Configuration...... 309
Ballout and Package Information .................................................................................... 311
13.1
13.2
13.3
13.4
13.5
13.6
13.7
12
Absolute Maximum Ratings................................................................................ 293
Power Characteristics ........................................................................................ 296
Signal Groups..................................................................................................... 299
DC Characteristics ............................................................................................. 303
11.4.1 General DC Characteristics................................................................ 303
11.4.2 CRT DAC DC Characteristics............................................................. 307
11.4.3 TV DAC DC Characteristics
(not supported on the Intel 915GME/Intel 910GMLE chipsets).......... 307
Intel 915GM, 915GME, 915PM, 910GML and 910GMLE
Express Chipset GMCH Ballout List .................................................................. 313
GMCH Signal Name Ordering Ball list ............................................................... 329
13.2.1 GMCH Numerical Order Ball List........................................................ 329
Mobile Intel 915GMS Express Chipset Ballout Diagram.................................... 329
Mobile Intel 915GMS Series Express Chipset Family Ballout List..................... 329
13.4.1 Mobile Intel 915GMS Express Chipset Family Ball-Out
Numerical Order Ball List.................................................................... 329
Mobile Intel 915GMS Express Chipset Family Signal Name Ordering Ball List 329
Mobile Intel 91xM Series Express Chipset Family Package
Mechanical Information ...................................................................................... 329
13.6.1 Intel 915PM/GM/GME and 910GML/GMLE Package
Mechanical Information....................................................................... 329
Mobile Intel 915GMS Express Chipset Package Mechanical Information......... 329
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Figures
Figure 3-1. Conceptual Platform PCI Configuration Diagram........................................... 66
Figure 3-2. DMI Type 0 Configuration Address Translation ............................................. 68
Figure 3-3. DMI Type 1 Configuration Address Translation ............................................. 69
Figure 3-4. Memory Map to PCI Express Device Configuration Space ........................... 70
Figure 3-5. GMCH Configuration Cycle Flow Chart ......................................................... 71
Figure 5-1. Link Declaration Topology............................................................................ 139
Figure 8-1. System Address Ranges.............................................................................. 225
Figure 8-2. DOS Legacy Address Range ....................................................................... 226
Figure 8-3. Main Memory Address Range...................................................................... 230
Figure 8-4. PCI Express Memory Address Range ......................................................... 233
Figure 10-1. System Memory Styles............................................................................... 248
Figure 10-2. GMCH Graphics Controller Block Diagram................................................ 258
Figure 10-3. LVDS Swing Voltage .................................................................................. 279
Figure 10-4. LVDS Clock and Data Relationship ........................................................... 279
Figure 10-5. Panel Power Sequencing ........................................................................... 281
Figure 13-1. Intel 915GM, 915GME, 915PM, 910GML, 910GMLE Express
Chipset GMCH Ballout Diagram (Top Left) ............................................................. 311
Figure 13-2. Intel 915GM, 915GME, 915PM, 910GML, 910GMLE Express
Chipset GMCH Ballout Diagram (Top Right)........................................................... 312
Figure 13-3. Intel 915GMS GMCH Ballout Diagram....................................................... 329
Figure 13-4. Intel 915GMS GMCH Ballout Diagram....................................................... 329
Figure 13-5. Mobile Intel 915PM/GM/GME/GL and 910GMLE Express
Chipset Package Micro-FCBGA .............................................................................. 329
Figure 13-6. Mobile Intel 915PM/GM/GME/GL and 910GMLE Express
Chipset Package Ball Grid Array ............................................................................. 329
Figure 13-7. Mobile Intel 915PM/GM/GME/GL and 910GMLE Express
Chipset Package Top View...................................................................................... 329
Figure 13-8. Mobile Intel 915PM/GM/GME/GL and 910GMLE Express
Chipset Package Side View..................................................................................... 329
Figure 13-9. Mobile Intel 915PM/GM/GME/GL and 910GMLE Express
Chipset Package Details B & K ............................................................................... 329
Figure 13-10. Recommended Via Stack Up for Platform (Standard Chipset Package). 329
Figure 13-11. Mobile Intel 915GMS Express Chipset Package Micro-FCBGA.............. 329
Figure 13-12. Mobile Intel 915GMS Express Chipset Package Ball Grid Array............. 329
Figure 13-13. Mobile Intel 915GMS Express Chipset Package Top View ..................... 329
Figure 13-14. Mobile Intel 915GMS Express Chipset Package Side View .................... 329
Figure 13-15. Mobile Intel 915GMS Express Chipset Package Details B & C............... 329
Figure 13-16. Recommended Via Stack Up for Platform
(Small Factor Chipset Package).............................................................................. 329
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Tables
Table 2-1. Single Channel Mode Signal Mapping for DDR/DDR2 ................................... 44
Table 2-2. Dual Channel Mode Signal Mapping for DDR/DDR2...................................... 45
Table 2-3. SDVO and PCI Express Based Graphics Port Signal Mapping ...................... 46
Table 3-1. Register Terminology....................................................................................... 65
Table 3-2. Device Number Assignment for Internal GMCH Devices................................ 67
Table 5-1. Device #0 MCHBAR Clock/Thermal Sensor Controls................................... 123
Table 5-2. DMI Register Summary Table ....................................................................... 130
Table 6-1. PCI Express Graphics Port Configuration Register Summary ...................... 145
Table 7-1. Device #2: Function 0 Configuration Register Summary Table .................... 191
Table 7-2. Device #2 Function 1 Configuration Register Summary Table ..................... 212
Table 8-1. Expansion Area Memory Segments .............................................................. 228
Table 8-2. Extended System BIOS Area Memory Segments......................................... 228
Table 8-3. System BIOS Area Memory Segments ......................................................... 229
Table 8-4. Pre-allocated Memory Example for 64-MB Dram, 1-MB VGA,
and 1-MB TSEG....................................................................................................... 231
Table 8-5. SMM Space Definition Summary................................................................... 237
Table 8-6. SMM Space Table ......................................................................................... 238
Table 8-7. SMM Control Table........................................................................................ 238
Table 10-1. System Memory Organization Support for DDR ......................................... 246
Table 10-2. System Memory Organization Support for DDR2 ....................................... 246
Table 10-3. DDR / DDR2 Supported Configurations ...................................................... 246
Table 10-4. Sample System Memory Organization with Symmetric Channels .............. 247
Table 10-5. Sample System Memory Organization with Asymmetric Channels ............ 247
Table 10-6. DRAM Device Configurations –Dual Channel Asymmetric Mode /
Single Channel Mode .............................................................................................. 249
Table 10-7. DRAM Device Configurations – Dual Channel Symmetric Mode................ 251
Table 10-8. Single Channel Mode Signal Mapping for DDR/DDR2 ............................... 253
Table 10-9. Dual Channel Mode Signal Mapping for DDR/DDR2.................................. 253
Table 10-10. Display Port Characteristics ...................................................................... 274
Table 10-11. Analog Port Characteristics ....................................................................... 275
Table 10-12. LVDS Panel support .................................................................................. 278
Table 10-13. LVDS Wide Panel support......................................................................... 278
Table 10-14. Panel Power Sequencing Timing Parameters........................................... 282
Table 10-15: Recommended Programming for Available Trip Points ............................ 290
Table 10-16. Intel 915GM Graphics Clock Frequency Support...................................... 292
Table 10-17. Intel 915GMS Graphics Clock Frequency Support ................................... 292
Table 10-18. Intel 910GML Graphics Clock Frequency Support.................................... 292
Table 11-1. Absolute Maximum Ratings......................................................................... 294
Table 11-2. Non-Memory Power Characteristics............................................................ 296
Table 11-3. DDR (333 MTs) Power Characteristics ....................................................... 297
Table 11-4. DDR 2 (400 MTs/533 MTs) Power Characteristics ..................................... 298
Table 11-5. Signal Groups .............................................................................................. 300
Table 11-6. DC Characteristics....................................................................................... 303
Table 11-7. CRT DAC DC Characteristics: Functional Operating Range
(VCCADAC = 2.5 V ±5%) ........................................................................................ 307
Table 11-8.
TV DAC DC Characteristics: Functional Operating Range
(VCCATVDAC[A,B,C] = 3.3 V ±5%) ........................................................................ 307
Table 12-1. Mobile Intel 915 Express Chipset Family Strapping Signals
and Configuration .................................................................................................... 309
Table 13-1. PLL Signal Group ........................................................................................ 313
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Table 13-2.Host Address Signal Group .......................................................................... 313
Table 13-3. Host Control Signal Group........................................................................... 314
Table 13-4. Host Data Signal Group............................................................................... 314
Table 13-5. DDR / DDR2 SDRAM Common Signal Group Ball List .............................. 315
Table 13-6. DDR / DDR2 SDRAM Channel a Command Signal Group Ball List........... 315
Table 13-7. DDR / DDR2 SDRAM Channel A Data Signal Group Ball List.................... 316
Table 13-8.DDR / DDR2 SDRAM Channel B Signal Group Ball List ............................. 317
Table 13-9. DDR / DDR2 SDRAM Channel B Signal Group Ball List ............................ 317
Table 13-10. Analog CRT Signal Group ......................................................................... 318
Table 13-11. Analog TV Signal Group............................................................................ 318
Table 13-12. LVDS Display Interface Signal Group ....................................................... 318
Table 13-13. LVDS Power Sequencing and Backlight Control Signal Group ................ 318
Table 13-14. DDC / GMBUS Signal Group..................................................................... 318
Table 13-15. DMI Serial Interface Signal Group............................................................ 318
Table 13-16. PCI Express Based Graphics / Serial Digital Video Out Receive
Signal Group ............................................................................................................ 319
Table 13-17. PCI Express Based Graphics / Serial Digital Video Out Transmit
Signal Group ............................................................................................................ 319
Table 13-18. Thermal and Power Sequencing Signal Group ......................................... 319
Table 13-19. No Connect Signal Group.......................................................................... 320
Table 13-20. Configuration & Reserved Signal Group ................................................... 320
Table 13-21. Voltage Reference and Compensation Signal Groups ............................. 320
Table 13-22. Power Signal Group .................................................................................. 321
Table 13-23. System Memory Analog Power Signal Group ........................................... 321
Table 13-24. System Memory Power Signal Group ....................................................... 322
Table 13-25. VTT Power Signal Group........................................................................... 322
Table 13-26. GMCH Core Voltage Power Signal Group ................................................ 323
Table 13-27. GMCH Ground Signal Group..................................................................... 324
Table 13-28. VCC Core Non-Critical to Function Signal Group ..................................... 327
Table 13-29. VTT Core Non-Critical to Function Signal Group ...................................... 327
Table 13-30. VCCSM Non-Critical to Function Signal Group......................................... 328
Table 13-31. VSS Non-Critical to Function Signal Group............................................... 328
Table 13-32. GMCH Signal Name Ordering Ball List ..................................................... 329
Table 13-33. GMCH Numerical Order Ball List............................................................... 329
Table 13-34. PLL Signal Group ...................................................................................... 329
Table 13-35.Host Address Signal Group ........................................................................ 329
Table 13-36. Host Control Signal Group......................................................................... 329
Table 13-37. Host Data Signal Group............................................................................. 329
Table 13-38. DDR2 SDRAM Common Signal Group Ball List ....................................... 329
Table 13-39. DDR2 SDRAM Channel a Command Signal Group Ball List................... 329
Table 13-40. DDR2 SDRAM Channel A Data Signal Group Ball List ............................ 329
Table 13-41. DDR2 SDRAM Channel B Signal Group Ball List ..................................... 329
Table 13-42. Analog CRT Signal Group ......................................................................... 329
Table 13-43. Analog TV Signal Group............................................................................ 329
Table 13-44. LVDS Display Interface Signal Group ....................................................... 329
Table 13-45. LVDS Power Sequencing and Backlight Control Signal Group ................ 329
Table 13-46. LVDS Power Sequencing and Backlight Control Signal Group ................ 329
Table 13-47. DDC / GMBUS Signal Group..................................................................... 329
Table 13-48. DMI Serial Interface Signal Group............................................................. 329
Table 13-49. Serial Digital Video Out Receive Signal Group ......................................... 329
Table 13-50. Serial Digital Video Out Transmit Signal Group ........................................ 329
Table 13-51. Thermal and Power Sequencing Signal Group ......................................... 329
Table 13-52. No Connect Signal Group.......................................................................... 329
Table 13-53. Configuration & Reserved Signal Group ................................................... 329
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Table 13-54. Voltage Reference and Compensation Signal Groups ............................. 329
Table 13-55. Power Signal Group .................................................................................. 329
Table 13-56. System Memory Analog Power Signal Group ........................................... 329
Table 13-57. System Memory Power Signal Group ....................................................... 329
Table 13-58. VTT Power Signal Group........................................................................... 329
Table 13-59. GMCH Core Voltage Power Signal Group ................................................ 329
Table 13-60. GMCH Ground Signal Group..................................................................... 329
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Revision History
Document No.
Version.
Description
®
Date
305264
002
Added Intel 915GME and 910GMLE chipsets.
April 2007
305264
001
Initial Release
January 2005
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Mobile Intel 915PM Express Chipset
Product Features
ƒ The Intel® Pentium® M Processor with 2-MB L2 Cache processor support
⎯ 533-MHz processor system bus support
ƒ Intel®® Pentium®® M Processor Low Voltage support
ƒ Intel Pentium M Processor Ultra Low Voltage support
⎯ 400-MHz processor system bus support
⎯ Source Synchronous Double-pumped (2×) Address
⎯ Source Synchronous Quad-pumped (4×) Data
⎯ Supports front side bus (FSB) interrupt delivery
⎯ Host bus dynamic bus inversion HDVIN (DBI) support
⎯ 32-bit host bus addressing support
⎯ 12-deep in-order queue support
⎯ AGTL+ bus driver technology with integrated termination resistors supported
⎯ DPWR# signal to processor for FSB power management
⎯ BSEL pins for BCLK frequency select
⎯ Enhanced Intel SpeedStep® technology
®
ƒ Intel® Celeron®® M 90 nm processor support
ƒ Intel Celeron M 90 nm processor ULV support
⎯ 400-MHz processor system bus support
⎯ Source Synchronous Double-pumped (2×) Address
⎯ Source Synchronous Quad-pumped (4×) Data
⎯ Supports front side bus (FSB) interrupt delivery
⎯ Host bus dynamic bus inversion HDVIN (DBI) support
⎯ 32-bit host bus addressing support
⎯ 12-deep in-order queue support
⎯ AGTL+ bus driver technology with integrated termination resistors supported
⎯ DPWR# signal to processor for FSB power management
⎯ BSEL pins for BCLK frequency select
ƒ System Memory Support
⎯ DDR or DDR2 SDRAM channels (64-bits wide) are supported.
⎯ Supports SO-DIMM’s of the same type (i.e. all DDR or all DDR2), not mixed.
⎯ 256-Mb, 512-Mb and 1-Gb technology supported using x8 or x16 devices.
⎯ Supports High Density memory Package for DDR or DDR2 type devices
⎯ Minimum memory supported is 128 MB
⎯ Maximum memory supported is 2 GB.
⎯ Supports configurations defined in the JEDEC* DDR / DDR2 SO-DIMM specification only
⎯ DDR feature support:
⎯ DDR – 333 MHz memory device
⎯ DDR2 feature support:
⎯ DDR2 - 400 MHz memory devices
⎯ DDR2 - 533 MHz memory devices
⎯ Supports On Die Termination (ODT) for DDR2
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⎯ One memory channel organizations is supported for DDR
⎯ Single Channel Mode
⎯ Two memory channel organizations are supported for DDR2:
⎯ Dual Channel Symmetric Mode
⎯ Dual Channel Asymmetric Mode
⎯ Single channel configuration supports: One, two, three or four ranks supported
⎯ Dual channel configuration: One or two ranks supported on each channel
⎯ Supports a max of two, double-sided unbuffered SO-DIMM’s (4 rows populated)
⎯ Burst length of 4 or 8 (configured by BIOS at boot time)
⎯ Supports opportunistic refresh scheme
⎯ Supports “Fast Chip Select” mode
⎯ Supports Partial Writes to memory using Data Mask signals (DM)
⎯ Two memory throttling schemes supported to selectively throttle reads and/or writes per rank.
⎯ Throttling can be triggered by on-die thermal sensor
⎯ Throttling can be triggered by preset read/write bandwidth limits
ƒ PCI Express* Based Graphics Interface
⎯ PCI Express Architecture support for external graphics devices
⎯ PCI Express Based Graphics interface only supported at core voltage at 1.05V
⎯ One 16-lane PCI Express port (x16 PCI Express port) intended for Graphics Attach
⎯ Fully compliant to the PCI Express Base Specification revision 1.0a
⎯ Base PCI Express frequency support of 2.5 GB/s only
⎯ Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a raw bandwidth per pair of 250 MB/s given
the 8b/10b encoding used to transmit data across this interface
⎯ Automatic discovery, negotiation, and training of link out of reset
⎯ Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
⎯ Supports traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)
⎯ Hierarchical PCI-compliant configuration mechanism for downstream devices (i.e., normal PCI 2.3
Configuration space as a PCI-to-PCI bridge
⎯ PCI Express Graphics Extended Configuration Space.
⎯ The first 256 bytes of configuration space alias directly to the PCI Compatibility configuration
space.
⎯ The remaining portion of the fixed 4 kB block of memory-mapped space above that (starting
at 100h) is known as extended configuration space.
⎯ PCI Express Enhanced Addressing Mechanism.
⎯ Accessing the device configuration space in a flat memory mapped fashion.
⎯ Uses a 100Mhz differential reference clock
⎯ PCI Express power management support
⎯ Supports both Native and Legacy Hot Plug and PME functions.
ƒ PCI Express x1 Port Support
⎯ One general PCI Express x1 port supported
⎯ PCI Express Based Graphics interface and SDVO are not functional in this mode
* Other names and brands may be claimed as the property of others
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ƒ Direct Media Interface (DMI)
⎯ Chip-to-chip interface between GMCH and ICH6-M
⎯ Configurable as x2 or x4 DMI lanes.
⎯ 2 GB/s point-to-point DMI to ICH6 (1 GB/s each direction)
⎯ 100 MHz reference clock (shared with PCI Express Graphics Attach).
⎯ 32-bit downstream addressing
⎯ APIC and MSI interrupt messaging support.
⎯ Message Signaled Interrupt (MSI) messages
⎯ SMI, SCI and SERR error indication
ƒ System Interrupts
⎯ Supports both 8259 and Pentium M processor FSB interrupt delivery mechanisms.
ƒ Power Management
⎯ SMRAM space remapping to A0000h (128 kB)
⎯ Supports extended SMRAM space above 256 MB, additional 1 MB TSEG from top of memory,
cacheable (cache ability controlled by CPU)
⎯ Supports Suspend to System Memory (S3-Hot and S3-Cold supported), Suspend to Disk (S4) and
Soft Off (S5)
⎯ ACPI 1.0b, 2.0 support
ƒ Package
⎯ Micro – FCBGA
⎯ Package size: 37.5mm x 40mm
⎯ Die size: 395 x 395 mils
⎯ Ball pitch: 42 mil
⎯ Ball count: 1257
20
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Mobile Intel 915GM Express Chipset
Features
Note: All features for the Mobile Intel 915PM Express Chipset are supported on the Mobile Intel
915GM. Only additional integrated graphics features will be shown here.
ƒ Integrated Display Interface support
⎯ Analog CRT DAC interface support
⎯ Supports max DAC frequency up to 400 MHz
⎯ 24-bit RAMDAC support
⎯ DDC2B compliant
⎯ Up to 2048 x 1536 mode support
⎯ Digital LVDS interface support
⎯ Compliant with ANSI/TIA/EIA -644-2001 spec
⎯ Integrated dual channel LVDS interface supported on Display Pipe B only
⎯ Supports 25 to 112 MHz single/dual channel LVDS interface:
⎯ Single channel LVDS interface support: 1 x 18 bpp
⎯ Dual channels LVDS interface support: 2 x 18 bpp
⎯ TFT panel type supported
⎯ Maximum Panel size supported up to UXGA
⎯ Maximum Wide panel size supported up to WUXGA
⎯ Ambient Light Sense support for automatic backlight brightness adjustments
⎯ Intel Display Power Savings Technology 2.0 support
⎯ Supports Single pipe simultaneous display with the CRT DAC and the LVDS ports under the
following conditions:
⎯ Timings must match for both display
⎯ Panel Fitting. Panning, and Center mode supported
⎯ Spatial Dithering support to emulate up to 16 million colors for 18bpp TFT panels.
⎯ Spread spectrum clocking (SSC) supported
⎯ Supports down and center SSC via an SSC clock from an external SSC clock chip.
⎯ Supports down spread of – 2.5% or center spread of ± -1.25% in reference 30-50 kHz
modulation rate
⎯ SSC must be disabled for LVDS port and CRT DAC single pipe simultaneous display
mode.
⎯ Panel Power Sequencing support
⎯ Power down state can be either zero volt or high impedance
⎯ Integrated PWM interface for LCD Backlight Inverter Control
⎯ Analog TV-Out Interface support
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⎯
⎯
⎯
⎯
⎯
⎯
⎯
Integrated TV-out device supported on Display pipe A and pipe B.
Three Integrated 10 bit DAC
NTSC/PAL encoder standard formats supported
Up to 1024x768 resolution supported for NTSC/PAL
HDTV graphics resolutions support
480p/720p/1080i/1080p modes supported
Multiplexed Output interface:
⎯ Composite Video
⎯ S-Video
⎯ Component Video (YprPb)
⎯ Combination: (Composite & S-Video)
⎯ Macrovision support
⎯ Overscan Scaling Support
⎯ Serial Digital Video Output (SDVO) support
⎯ Two SDVO ports are supported
⎯ Supports a variety display devices such as DVI, TV Out, LVDS, etc.
⎯ Compliant with DVO specification 1.0 when combined with a DVI compliant external device
and connector.
⎯ Data sourced from either display Pipe A or Pipe B
⎯ Supports single pipe simultaneous display with the DAC or LVDS ports
⎯ Timings must match for both display
⎯ Single pipe not supported with SSC on LVDS port
⎯ Each SDVO Port support display pixel rates up to 200 MP/s (600MB/s)
⎯ Fast point-to-point GMBUS is provided for SDVO device control
⎯ Supports Hot Plug and Display
⎯ Support for HDCP SDVO devices
ƒ Internal Graphics Features
⎯ DVMT 3.0 support
Max memory allocation support based on total system memory
1-MB or 8 MB of pre-allocated memory supported
⎯ Intel® Dual-Frequency Graphics Technology
⎯ Intel® Smart 2D Display Technology
⎯ Asynchronous Display core and Render core clocks supported
⎯ 2D Display core frequency required to be equal or greater than 3D Render Core Frequency.
⎯ 2D Display core frequency at 133 or 190/200 MHz @ Vcc=1.05 V depending on the
host/memory configurations
⎯ 3D Render core frequency at 133, 160/166 or 190/200 MHz @ Vcc=1.05 V depending on
the host/memory configurations
⎯ 2D Display core frequency at 133, 200 or 333MHz @ Vcc=1.5 V depending on the
host/memory configurations
⎯ 3D Render core frequency at 133, 160/166, 200 or 333 MHz @ Vcc=1.5 V depending on the
host/memory configurations
⎯ Dual Independent display pipes.
⎯ 32 bit Hardware cursor supported
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⎯ 2D graphics engine
⎯ Optimized 256-bit BLT engine
⎯ Alpha Stretch Blitter
⎯ Anti-aliased Lines
⎯ 32-bit Alpha Blended Cursor
⎯ Color Space Conversion
⎯ Programmable 3-Color Transparent Cursor
⎯ 8-, 16- and 32-bit per pixel color
⎯ 8 ROP support
⎯ High Quality 3D Setup and Render Engine
⎯ Setup matching processor geometry delivery rates
⎯ Triangle lists, strips and fans
⎯ Indexed vertex and flexible vertex formats
⎯ Vertex cache
⎯ Pixel accurate fast scissoring and clipping operation
⎯ Backface culling
⎯ Supports D3D and OGL pixelization rules
⎯ Sprite points
⎯ Shadow maps
⎯ Double-sided stencil
⎯ Zone Rendering 2.0 support
⎯ High Quality Texture Engine
⎯ 533 MegaTexel/Sec Performance – 266 Mpixel/Sec fill rate up to 2 bilinear
textures
⎯ Hardware Pixel Shader 2.0
⎯ Per-pixel perspective corrected texture mapping
⎯ 2/10/10/10 texture format
⎯ Bi-cubic filtering
⎯ Single-pass quad texture compositing
⎯ Enhanced texture blending functions
⎯ 12 levels of detail mip map sizes from 1x1 to 2Kx2K
⎯ All texture formats including 32-bit RGBA and 8-bit palettes
⎯ Alpha and luminance maps
⎯ Texture color-keying/chromakeying
⎯ Bilinear, trilinear and anisotropic mip-mapped filtering
⎯ Cubic environment reflection mapping
⎯ Embossed and DOT3 bump-mapping
⎯ DXTn and FXT1 texture decompression
⎯ Non-power of 2 texture
⎯ Render to texture
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⎯ 3D Graphics Rendering Enchantments
⎯ 1.3 Dual Texture GigaPixel/Sec Fill Rate
⎯ Flat and Gouraud Shading
⎯ Color Alpha Blending for Transparency
⎯ Vertex and Programmable Pixel Fog and Atmospheric Effects
⎯ Color Specular Lighting
⎯ Z Bias Support
⎯ Dithering
⎯ Anti-Aliased Lines
⎯ 16- and 24-bit Z Buffering
⎯ 8-bit Stencil Buffering
⎯ Double and Triple Render Buffer Support
⎯ 16- and 32-bit Color
⎯ Destination Alpha
⎯ Maximum 3D Resolution Supported: 1600x1200x32
⎯ Fast Clear Support
⎯ Video DVD / PC-VCR support
⎯ HW Motion Compensation for MPEG2
⎯ Dynamic Bob and Weave Support for Video Streams
⎯ Resolution up to 1920x1080 with 2 vertical taps
⎯ Source Software DVD At 30 fps, Full Screen
⎯ Supports 720x480 DVD Quality Encoding at low CPU Utilization for PC-VCR or home
movie recording and editing
⎯ Video Overlay
⎯ Process Amplifier Color Control
⎯ Single High Quality Scalable Overlay
⎯ Multiple Overlay Functionality provided via Stretch Blitter (PIP, Video Conferencing, etc.)
⎯ 5-tap Horizontal, 2-tap Vertical Filtered Scaling
⎯ Independent Gamma Correction
⎯ Independent Brightness/Contrast/Saturation
⎯ Independent Tint/Hue Support
⎯ Destination Color-keying
⎯ Source Chroma-keying
⎯ Maximum Source Resolution: 720x480x32
⎯ Video Mixer Render (VMR)
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Mobile Intel 915GMS Express Chipset
Features
Note: All features for Mobile Intel 915GM Express Chipset is supported on Mobile Intel 915GMS.
The differences are noted in this section.
ƒ Intel®® Pentium®® M Processor Low Voltage support
ƒ Intel® Pentium® M Processor Ultra Low Voltage support
ƒ Intel Celeron M 90 nm processor ULV support
⎯ 400 MHz processor system bus support only
ƒ System Memory Support
⎯ DDR2 memory channels (64-bits wide) are supported.
⎯ No DDR support
⎯ DDR2 feature support:
⎯ DDR2 – 400 memory devices
⎯ One memory channel organizations is supported:
⎯ Single Channel mode
ƒ PCI Express* Based Graphics Interface not supported
ƒ Integrated Display Interface support
⎯ Digital LVDS interface support
⎯ Integrated single channel LVDS interface supported on Display Pipe B only
⎯ Supports 25 to 112 MHz single channel LVDS interface:
⎯ Single channel LVDS interface support: 1 x 18 bpp
⎯ Maximum Panel size supported up to SXGA+ (single channel only)
⎯ Wide panel size supported up to WXGA (single channel only)
⎯ Serial Digital Video Output (SDVO) support
⎯ One SDVO port is supported
⎯ SDVO B
ƒ Internal Graphics Features
⎯ Graphics core voltage support’s 1.05 V only
⎯ 2D Display core frequency at 133 or 200 MHz @ Vcc = 1.05 V
⎯ 3D Render core frequency at 133 or 160 MHz @ Vcc = 1.05 V
ƒ Package
⎯ Micro – FCBGA
⎯ Package size: 27 x 27 mm
⎯ Die size: 395 x 395 mils
⎯ Ball pitch: See the mechanical drawing
⎯ Ball count: 840
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Mobile Intel 910GML Express Chipset
Product Features
Note: All features for the Mobile Intel 915GM Chipset are supported on the Intel 910GML unless
otherwise noted in this section.
ƒ Intel®® Celeron®® M 90 nm processor support
ƒ Intel Celeron M 90 nm processor ULV support
⎯ 400 MHz processor system bus support only
ƒ System Memory Support
⎯ DDR or DDR2 SDRAM channels (64-bits wide) are supported.
⎯ DDR - 333 MHz memory device
⎯ Single Channel Memory support for DDR 333
⎯ DDR2 - 400 MHz memory devices
⎯ Dual Channel Memory configuration support for DDR2 400
ƒ PCI Express* Based Graphics Interface not supported
ƒ Integrated Display Interface support
⎯ Digital LVDS interface support
⎯ Max Panel size supported is SXGA+
⎯ Analog TV-Out Interface support
⎯ HDTV graphics mode is not supported.
ƒ Internal Graphics Features
⎯ 2D Display core frequency support from 133 MHz & 190/200 MHz @ Vcc = 1.05 / 1.5 V
depending on Host/Memory configuration
⎯ 3D Render core frequency support from 133 MHz & 160/166 MHz @ Vcc = 1.05 / 1.5 V
depending on Host/Memory configuration
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Mobile Intel 915GME Express Chipset
Features
Note: All features for the Mobile Intel 915GM Express Chipset are supported on the Intel 915GME
unless otherwise noted in this section.
ƒ Macrovision copy protection technology has been disabled on the Intel 915GME.
ƒ The TV-out port has been disabled on the Intel 915GME. Please ensure platform design guide
recommendations for TV-out disabling have been followed.
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Mobile Intel 910GMLE Express Chipset
Features
Note: All features for the Mobile Intel 910GML Express Chipset are supported on the Intel
910GMLE unless otherwise noted in this section.
ƒ Macrovision copy protection technology has been disabled on the Intel 910GMLE.
ƒ The TV-out port has been disabled on the Intel 910GMLE. Please ensure platform design guide
recommendations for TV-out disabling have been followed.
§
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Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
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1
Introduction
This document is the datasheet for the Mobile Intel® 915GM/PM/GMS/GME and 910GML/GMLE
Express chipset families.
1.1
Overview
The Mobile Intel 915GM/PM/GMS/GME & 910GML/GMLE Express chipset family is a graphics
memory controller hub (GMCH) designed for use with the Intel Pentium M Processor with 2 MB L2
Cache and Intel® Celeron® M processor 90 nm. The family includes the following chipsets:
• Mobile Intel 915GM Express chipset supports Intel Graphics Media Accelerator 900 and PCI
Express* based Graphics
• Mobile Intel 915PM Express chipset supports PCI Express based Graphics only
• Mobile Intel 915GMS Express chipset supports Intel Graphics Media Accelerator 900 in small
form factor package
• Mobile Intel 910GML Express chipset supports Intel Graphics Media Accelerator 900
• Mobile Intel 915GME Express chipset supports Intel Graphics Media Accelerator 900 and
PCIExpress* based graphics with TV-out and Macrovision copy protection technology disabled.
• Mobile Intel 910GMLE Express chipset supports Intel Graphics Media Accelerator 900 with TVout and Macrovision copy protection technology disabled.
Note: Intel 915GMS may have notes in GRAY-20% shade throughout this document. This is to
point out differences which may be specific only for this chipset.
The GMCH provides high-performance, integrated graphics and manages the flow of information. The
Intel 915GM chipset adds enhancements for the following areas:
• System Memory (DDR / DDR2)
• PCI Express Based Graphics (discrete graphics devices)
• Intel Graphics enhancements:
⎯ DVMT 3.0 support
⎯ Zone Rendering 2.0 support
⎯ Quad pixel pipe rendering engine
⎯ Pixel Shader 2.0 support
⎯ 4x Faster Setup Engine
• Serial Digital Video Output (SDVO)
• TV Out Support
⎯ HDTV resolution support
• LVDS support
⎯ Wide panel support
⎯ Ambient Light Sense support for automatic backlight brightness adjustments
⎯ Intel Display Power Savings Technology 2.0 support
⎯ Integrated PWM interface for LCD Backlight Inverter Control
• Direct Media Interface (DMI)
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1.1.1
System Memory Interface
The GMCH integrates a system memory DDR/DDR2 controller with two, 64-bit wide interfaces. Only
Double Data Rate (DDR / DDR2) memory is supported; consequently, the buffers support DDR
SSTL_2 and DDR2 SSTL_18 signaling interfaces. The memory controller interface is fully
configurable through a set of control registers.
Three system memory modes of operation supported are:
• Single Channel mode
• Dual Channel Asymmetric mode
• Dual Channel Symmetric mode
1.1.2
PCI Express* Based Graphics and Intel SDVO Interface
The GMCH multiplexes a PCI Express Graphics interface with two Intel SDVO ports. The SDVO
ports can each support a single-channel SDVO device. If both ports are active in single-channel mode,
they can have different display timing and data. Alternatively the SDVO ports can combine to support
dual channel devices, supporting higher resolutions and refresh rates.
PCI Express Based Graphics Interface
The GMCH contains one 16-lane (x16) PCI Express port intended for an external PCI Express Based
graphics card. The PCI Express port is fully compliant to the PCI Express Base Specification revision
1.0a. The x16 port operates at a data rate of 2.5 GB/s while employing 8b/10b encoding. This allows a
maximum theoretical bandwidth of 40 GB/s each direction. Intel 915GM/ PM may also be configured
as PCI Express x1 port.
1.1.3
Display Interface
Note: Analog TV interface not supported on the Intel 915GME and Intel 910GMLE chipsets.
The GMCH is capable of driving a CRT, LCD panel, Analog TV and/or two SDVO devices (SDVO
ports are muxed with PCI Express).
The display is the defining portion of a graphics controller. The display converts a set of source images
or surfaces, combines them and sends them out at the proper timing to an output interface connected to
a display device. Along the way, the data can be converted from one format to another, stretched or
shrunk, and color corrected or gamma converted.
1.1.4
SDVO Interface
The GMCH supports two SDVO ports multiplexed with PCI Express Graphics interface. The SDVO
ports are capable of driving a variety of external TV-Out, TMDS, and LVDS transmitter devices.
SDVO devices are capable of driving a standard progressive scan analog monitor with resolutions up to
2048x1536 at 75 Hz. This interface may be configured for as PCI Express x1 port also.
1.1.5
DMI
DMI is a point -to- point connection from the GMCH to the ICH6-M.
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1.2
Terminology
Term
Description
AGTL+
Advanced Gunning Transceiver Logic + (AGTL+) bus
AGP
Accelerated Graphics Port refers to the AGP/PCI interface in previous generation chipset. It have
been replaced by PCI Express * based graphics interface
ALS
Ambient Light Sensor
GMCH
Refers to the Graphics Memory Controller Hub chipset component for Intel 910GML and Intel
915GM Chipset.
MCH
Refers to the Memory Controller Hub chipset component for Intel 915PM MCH Chipset. Any
references to GMCH will also apply to MCH unless otherwise noted.
bpp
Bit per pixel
Beacon
30 kHz–500 MHz signal used by PCI Express to exit the L2 power state.
Bit Clock
The nominal data rate that information is passed on an Interface. Note that in the PCI Express
interface this clock is embedded within the data and is not a separate signal.
BLI
Backlight Inverter
Bridge
A Device which virtually or actually connects a PCI/PCI Express segment or PCI Express Port
with an internal Component interconnect or another PCI/PCI-X segment or PCI Express Port. A
Bridge must include a software configuration interface as described in this document.
Core
The internal base logic in the Mobile Intel 915 Express Chipset Family
CPU
Central Processing Unit
®
CRT
Cathode Ray Tube
DBL
Display Brightness Link
DDC
Display Data Channel (VESA standard)
DDR
Double Data Rate SDRAM memory technology
DDR2
Second generation Double Data Rate SDRAM memory technology
DINV (DBI)
Dynamic Bus inversion
DMI
Direct Media Interface.
The chip-to-chip inter-connect between the Mobile Intel 915 Express Chipset Family GMCH and
the ICH6-M, is an Intel Proprietary interface.
DPMS
Display Power Management Signaling (standard created by VESA)
DPST
Intel Display Power Savings Technology
DVI*
Digital Visual Interface is the interface specified by the DDWG (Digital Display Working Group)
DVI Spec. Rev. 1.0
®
DVMT
Dynamic Video Memory Technology
EDID
Extended Display Identification Data
EIST
Enhanced Intel SpeedStep technology
FSB
Front Side Bus, synonymous with Host or CPU bus.
Full Reset
A Full GMCH Reset is defined in this document when RSTIN# is asserted.
GTL+
Gunning Transceiver Logic + (GTL+) bus
Host
This term is used synonymously with processor
HDTV
High Definition Television
I2C
Inter-IC (a two wire serial bus created by Philips)
Intel ICH6-M
The Intel I/O Controller Hub component that contains the primary PCI interface, LPC interface,
USB2, ATA-100, and other I/O functions. It communicates with the GMCH over a proprietary
interconnect called DMI.
IGD
Integrated Graphics Device
®
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Term
Description
INTx
An interrupt request signal where X stands for interrupts A,B,C and D
IPI
Inter Processor Interrupt
LCD
Liquid Crystal Display.
LFP
Local Flat Panel
LVDS
Low Voltage Differential Signaling: -
MSI
Message Signaled Interrupt.
NCTF
Non-Critical to Function:
A high speed, low power data transmission standard used for display connections to LCD panels.
MSI allow a device to request interrupt service via a standard memory write transaction instead of
through a hardware signal. A transaction initiated outside the host, conveying interrupt information
to the receiving agent through the same path that normally carries read and write commands.
As a function of Intel's continuous improvement goals, we have identified package level
modifications that add to the overall solder joint strength and reliability of our component. Through
our research and development, we have concluded that adding non-critical to function (NCTF)
solder balls to our packages can improve the overall package-to-board solder joint strength and
reliability.
Ball locations/signal ID's followed with the suffix of “NCTF” have been designed into the package
footprint to enhance the package to board solder joint strength/reliability of this product by
absorbing some of the stress introduced by the Characteristic Thermal Expansion (CTE)
mismatch of the Die to package interface.
It is expected that in some cases, where board stresses are excessive, these balls may crack
partially or completely, however, cracks in the NCTF balls will have no impact to our product
performance or reliability. Intel has added these balls primarily to serve as stress absorbers.
NTSC
National Television Standards Committee
PAL
Phase Alternate Line
SDTV
Standard Definition Television
PCI Express*
PCI Express* Interface is based on the PCI Express Specification 1.0a
PCI Express
Based
Graphics
Primary PCI
FSB
PCI Express Based Graphics. External Graphics using PCI Express* Architecture.
A high-speed serial interface whose configuration is software compatible with the existing PCI
specifications. The specific PCI Express implementation intended for connecting the GMCH to an
external graphics controller is an x16 link and replaces AGP.
The physical PCI bus that is driven directly by the ICH component. Communication between
Primary PCI and the GMCH occurs over DMI. Note that the Primary PCI bus is not PCI Bus 0
from a configuration standpoint.
Processor System Bus.
®
Connection between Mobile Intel 915 Express Chipset Family GMCH and the CPU. Also known
as the Host interface
32
PWM
Pulse Width Modulation
Rank
A unit of DRAM corresponding 4 to 8 devices in parallel, ignoring ECC. These devices are
usually, but not always, mounted on a single side of a SO-DIMM.
SCI
System Control Interrupt. Used in ACPI protocol.
SDVO
Serial Digital Video Out (SDVO).
Digital display channel that serially transmits digital display data to an external SDVO device. The
SDVO device accepts this serialized format and then translates the data into the appropriate
display format (i.e., TMDS, LVDS, TV-Out). This interface is not electrically compatible with the
®
previous digital display channel - DVO. For Mobile Intel 915 Express Chipset Family, it will be
multiplexed on a portion of the x16 graphics PCI Express interface.
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Term
Description
SDVO Device
Third party codec that utilizes SDVO as an input. May have a variety of output formats, including
DVI, LVDS, HDMI, TV-out, etc.
SERR
An indication that an unrecoverable system error has occurred on an I/O bus.
SMI
System Management Interrupt.
SSC
Spread Spectrum Clocking
TMDS
Transition Minimized Differential Signaling. Signaling interface from Silicon Image that is used in
DVI and HDMI.
TOLM
Top Of Low Memory. The highest address below 4GB for which a CPU initiated memory read or
write transaction will create a corresponding cycle to DRAM on the memory interface.
UMA
Unified Memory Architecture. Describes Mobile Intel 915 Express Chipset Family GMCH using
system memory for its graphics frame buffers.
VCO
Voltage Controlled Oscillator
Used to indicate any of several system conditions such as thermal sensor events, throttling
activated, access to System Management RAM, chassis open, or other system state related
activity.
®
VDL
Video Data Link
×1
Refers to a Link or Port with one Physical Lane.
x8
Refers to a Link or Port with eight Physical Lanes.
xN
Refers to a Link with “N” Physical Lanes.
VRM
Video Render Mixer
VTT
Processor Side Bus power supply (VCCP)
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1.3
Reference Documents
Document
Location
®
®
http://developer.intel.com
®
®
http://developer.intel.com
®
®
http://developer.intel.com
Intel Pentium M Processor with 2 MB L2 Cache and 533
MHz Front Side Bus Datasheet
Intel Pentium M Processor on 90 nm Process with 2 MB
L2 Cache Datasheet
Intel Celeron M Processor on 90 nm Process Datasheet
PCI Express Base Specification 1.0a
http://www.pcisig.org/
http://www.vesa.org
VESA Specifications
PCI Local Bus Specification 2.3
http://www.pcisig.com
Advanced Configuration and Power Management(ACPI)
Specification 1.0b & 2.0
http://www.teleport.com/~acpi/
JEDEC Double Data Rate (DDR) SDRAM Specification
http://www.jedec.com
JEDEC Double Data Rate 2 (DDR2) SDRAM Specification
34
Intel Developer website link for DDR validation information
http://developer.intel.com/technology/memory/
Intel Developer website link for PCI Express* Architecture
http://www.intel.com/technology/pciexpress/devnet/
mobile.htm
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2
Signal Description
This section describes the GMCH signals. These signals are arranged in functional groups according to
their associated interface. The following notations are used to describe the signal type:
I
Input pin
O
Output pin
I/O Bi-directional Input/Output pin
The signal description also includes the type of buffer used for the particular signal:
AGTL+
Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete
details. (VCCP)
PCIE
PCI Express interface signals. These signals are compatible with PCI Express Base
Specification 1.0a Electrical Signal Specifications. The buffers are not 3.3-V tolerant.
Differential voltage spec = (|D+ - D-|) * 2 = 1.2 V max. Single-ended maximum = 1.5 V.
Single-ended minimum = 0 V. Please refer to the PCIE specification.
CMOS
CMOS buffers. 1.5 V tolerant
HVCMOS
CMOS buffers. 2.5 V tolerant
COD
CMOS Open Drain buffers. 2.5 V tolerant
DDR
DDR system memory (2.5 V CMOS buffers)
DDR2
DDR2 system memory (1.8 V CMOS buffers)
SSTL-2
2.5 V Stub Series Termination Logic
SSTL-1.8
1.8 V Stub Series Termination Logic
A
Analog reference or output. May be used as a threshold voltage or for buffer
compensation
LVDS
Low Voltage Differential Signal interface
Ref
Voltage reference signal
Note: System Address and Data Bus signals are logically inverted signals. The actual values are
inverted of what appears on the system bus. This must be considered and the addresses and data bus
signals must be inverted inside the GMCH. All processor control signals follow normal convention: A
0 indicates an active level (low voltage), and a 1 indicates an active level (high voltage).
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2.1
Host Interface
Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination
voltage of the host bus (VCCP).
Note: Host interfaces signal group is supported on the Intel 915GM, Intel 915PM, Intel 915GMS,
Intel 915GME, Intel 910GML and Intel 910GMLE chipsets.
2.1.1
Host Interface Signals
Signal Name
HADS#
HBNR#
HBPRI#
HBREQ0#
Type
Description
I/O
AGTL+
Host Address Strobe:
I/O
AGTL+
Host Block Next Request:
O
AGTL+
Host Bus Priority Request:
I/O
AGTL+
Host Bus Request 0#:
The system bus owner asserts HADS# to indicate the first of two cycles of a request
phase. The GMCH can also assert this signal for snoop cycles and interrupt
messages.
Used to block the current request bus owner from issuing a new request. This signal
is used to dynamically control the CPU bus pipeline depth.
The GMCH is the only Priority Agent on the system bus. It asserts this signal to
obtain the ownership of the address bus. This signal has priority over symmetric bus
requests and will cause the current symmetric owner to stop issuing new
transactions unless the HLOCK# signal was asserted.
The GMCH pulls the processor bus HBREQ0# signal low during HCPURST#. The
signal is sampled by the processor on the active-to-inactive transition of
HCPURST#.
HBREQ0# should be tri-stated after the hold time requirement has been satisfied.
HCPURST#
O
AGTL+
Host CPU Reset:
The CPURST# pin is an output from the GMCH. The GMCH asserts HCPURST#
while RSTIN# is asserted and for approximately 1 ms after RSTIN# is deasserted.
HCPURST# allows the processor to begin execution in a known state.
HDBSY#
HDEFER#
HDINV[3:0]#
I/O
AGTL+
Host Data Bus Busy:
O
AGTL+
Host Defer:
I/O
AGTL+
Host Dynamic Bus Inversion:
Used by the data bus owner to hold the data bus for transfers requiring more than
one cycle.
Signals that the GMCH will terminate the transaction currently being snooped with
either a deferred response or with a retry response.
Driven along with the HFD[63:0]# signals. Indicates if the associated signals are
inverted or not. HDINVF[3:0]# are asserted such that the number of data bits driven
electrically low (low voltage) within the corresponding 16-bit group never exceeds 8.
HDINV#
HDRDY#
I/O
AGTL+
36
Data Bits
HDINV[3]#
HD[63:48]#
HDINV[2]#
HD[47:32]#
HDINV[1]#
HD[31:16]#
HDINV[0]#
HD[15:0]#
Host Data Ready:
Asserted for each cycle that data is transferred.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
Signal Name
HA[31:3]#
Type
I/O
AGTL+
2X
Description
Host Address Bus:
HA[31:3]# connects to the CPU address bus. During processor cycles the HA[31:3]#
are inputs. The GMCH drives HA[31:3]# during snoop cycles on behalf of DMI.
HA[31:3]# are transferred at 2x rate.
Note that the address is inverted on the CPU bus.
HADSTB[1:0]#
I/O
AGTL+
2X
Host Address Strobe:
HA[31:3]# connects to the CPU address bus. During CPU cycles, the source
synchronous strobes are used to transfer HA[31:3]# and HREQ[4:0]# at the 2x
transfer rate.
Strobe
HD[63:0]#
I/O
AGTL+
4X
Address Bits
HADSTB[0]#
HA[16:3]#, HREQ[4:0]#
HADSTB[1]#
HA[31:17]#
Host Data:
These signals are connected to the CPU data bus. HD[63:0]# are transferred at 4x
rate.
Note that the data signals are inverted on the CPU bus depending on the
HDINV[3:0]# signals.
HDSTBP[3:0]#
HDSTBN[3:0]#
I/O
AGTL+
4X
HHIT#
I/O
AGTL+
Host Differential Host Data Strobes:
The differential source synchronous strobes are used to transfer HD[63:0]# and
HDINV[3:0]# at the 4x transfer rate.
Strobe
Data Bits
HDSTBP[3]#, HDSTBN[3]#
HD[63:48]#, HDINV[3]#
HDSTBP[2]#, HDSTBN[2]#
HD[47:32]#, HDINV[2]#
HDSTBP[1]#, HDSTBN[1]#
HD[31:16]#, HDINV[1]#
HDSTBP[0]#, HDSTBN[0]#
HD[15:00]#, HDINV[0]#
Host Hit:
Indicates that a caching agent holds an unmodified version of the requested line.
Also, driven in conjunction with HITM# by the target to extend the snoop window.
HHITM#
I/O
AGTL+
Host Hit Modified:
Indicates that a caching agent holds a modified version of the requested line and
that this agent assumes responsibility for providing the line.
Also, driven in conjunction with HIT# to extend the snoop window.
HLOCK#
HREQ[4:0]#
I
AGTL+
I/O
AGTL+
2X
HTRDY#
O
AGTL+
Host Lock:
All CPU bus cycles sampled with the assertion of HLOCK# and HADS#, until the
negation of HLOCK# must be atomic, i.e. PCI Express graphics access to System
Memory is allowed when HLOCK# is asserted by the CPU.
Host Request Command:
Defines the attributes of the request. HREQ[4:0]# are transferred at 2x rate.
Asserted by the requesting agent during both halves of the Request Phase. In the
first half the signals define the transaction type to a level of detail that is sufficient to
begin a snoop request. In the second half the signals carry additional information to
define the complete transaction type.
Host Target Ready:
Indicates that the target of the processor transaction is able to enter the data
transfer phase.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
37
Signal Description
R
Signal Name
HRS[2:0]#
Type
O
AGTL+
Description
Host Response Status:
Indicates the type of response according to the following the table:
Response type
HRS[2:0]#
HDPWR#
O
O
001
Retry response
010
Deferred response
011
Reserved (not driven by GMCH)
100
Hard Failure (not driven by GMCH)
101
No data response
110
Implicit Write back
111
Normal data response
Used by GMCH to indicate that a data return cycle is pending within 2 HCLK cycles
or more. CPU use’s this signal during a read-cycle to activate the data input buffers
in preparation for HDRDY# and the related data.
Host CPU Sleep:
CMOS
2.1.2
Idle state
Host Data Power:
AGTL+
HCPUSLP#
000
When asserted in the Stop-Grant state, causes the processor to enter the Sleep
state. During Sleep state, the processor stops providing internal clock signals to all
units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this
state will not recognize snoops or interrupts.
Host Interface Reference and Compensation
Signal Name
HVREF
HXRCOMP
Type
Description
I
Host Reference Voltage:
A
Reference voltage input for the Data, Address, and Common clock signals of the
Host AGTL+ interface.
I/O
A
Host X RCOMP:
Used to calibrate the Host AGTL+ I/O buffers.
This signal is powered by the Host Interface termination rail (VCCP).
HXSCOMP
HXSWING
HYRCOMP
I/O
Slew Rate Compensation for the Host Interface
I
Host X Voltage Swing:
A
These signals provide reference voltages used by the HXRCOMP circuits.
I/O
A
HYSCOMP
HYSWING
38
Host X SCOMP:
A
I/O
Host Y RCOMP:
Used to calibrate the Host AGTL+ I/O buffers.
Host Y SCOMP:
A
Slew Rate Compensation for the Host Interface
I
Host Y Voltage Swing:
A
These signals provide reference voltages used by the HYRCOMP circuitry.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
2.2
DDR DRAM Interface
1.
2.
2.2.1
DDR DRAM interfaces signal group is supported the Intel 915PM, Intel 915GM, Intel 915GMS
Intel 915GME, Intel 910GML and Intel 910GMLE chipsets, unless otherwise noted.
Intel 915GMS supports single channel only, therefore some signals may not be applicable.
DDR / DDR2 SDRAM Channel A Interface
Signal Name
SA_DQ[63:0]
Type
I/O
SSTL1.8 / 2
2x
Description
Data Bus:
DDR / DDR2 Channel A data signal interface to the SDRAM data
bus.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A
SA_DM[7:0]
O
SSTL1.8 / 2
2X
Data Mask:
These signals are used to mask individual bytes of data in the case
of a partial write, and to interrupt burst writes.
When activated during writes, the corresponding data groups in the
SDRAM are masked. There is one SA_DM[7:0] for every data byte
lane.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A
SA_DQS[7:0]
I/O
SSTL1.8
2x
Data Strobes:
DDR: The rising and falling edges of SA_DQS[7:0] are used for
capturing data during read and write transactions.
DDR2: SA_DQS[7:0] and its complement signal group make up a
differential strobe pair. The data is captured at the crossing point of
SA_DQS[7:0] and its SA_DQS[7:0]# during read and write
transactions.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A
SA_DQS[7:0]#
I/O
SSTL1.8
2x
Data Strobe Complements
DDR1: No Connect. These signals are not used for DDR devices
DDR2 : These are the complementary DDR2 strobe signals.
Single channel mode: Route to SO-DIMM 0 & SO-DIMM1
Dual channel mode: Route to SO-DIMM A
SA_MA[13:0]
O
SSTL1.8 / 2
Memory Address:
These signals are used to provide the multiplexed row and column
address to the SDRAM.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
Note: SA_MA13 is for support of 1 Gb devices.
SA_BS[2:0]
O
SSTL1.8 / 2
Bank Select:
These signals define which banks are selected within each SDRAM
rank.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
Note: SA_BS2 is for support for DDR2 only for 8 bank devices.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
39
Signal Description
R
Signal Name
SA_RAS#
Type
O
SSTL1.8 / 2
Description
RAS Control signal:
Used with SA_CAS# and SA_WE# (along with SM_CS#) to define
the SDRAM commands.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SA_CAS#
O
SSTL1.8 / 2
CAS Control signal:
Used with SA_RAS# and SA_WE# (along with SM_CS#) to define
the SDRAM commands.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SA_WE#
O
SSTL1.8 / 2
Write Enable Control signal:
Used with SA_RAS# and SA_CAS# (along with SM_CS#) to define
the SDRAM commands.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SA_RCVENIN#
I
SSTL1.8 / 2
Clock Input:
Used to emulate source-synch clocking for reads. Connects
internally to SA_RCVENOUT#.
Leave as No Connect.
SA_RCVENOUT#
O
SSTL1.8 / 2
Clock Output:
Used to emulate source-synch clocking for reads. Connects
internally to SA_RCVENIN#.
Leave as No Connect.
40
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
2.2.2
DDR / DDR2 SDRAM Channel B Interface
Signal Name
SB_DQ[63:0]
Type
I/O
SSTL1.8 / 2
2x
Description
Data Lines:
DDR / DDR2 Channel B data signal interface to the SDRAM data
bus.
Single Channel mode: No connect.
Dual channel mode: Route to SO-DIMM B
NOTE: Signals do not exist in Intel 915GMS.
SB_DM[7:0]
O
SSTL1.8 / 2
2X
Data Mask:
When activated during writes, the corresponding data groups in
the SDRAM are masked. There is one SB_DM[7:0] for every
data byte lane. These signals are used to mask individual bytes
of data in the case of a partial write, and to interrupt burst writes.
Single Channel mode: No connect.
Dual channel mode: Route to SO-DIMM B
NOTE: Signals do not exist in Intel 915GMS.
SB_DQS[7:0]
I/O
SSTL1.8 / 2
2x
Data Strobes:
DDR: The rising and falling edges of SB_DQS[7:0] are used for
capturing data during read and write transactions.
DDR2: SB_DQS[7:0] and its complement signal group make up
a differential strobe pair. The data is captured at the crossing
point of SB_DQS[7:0] and its SB_DQS[7:0]# during read and
write transactions.
Single Channel mode: No connect.
Dual channel mode: Route to SO-DIMM B
NOTE: Signals do not exist in Intel 915GMS.
SB_DQS[7:0]#
I/O
SSTL1.8
2x
Data Strobe Complements (DDR2 only):
DDR1: No Connect. These signals are not used for DDR devices
DDR2 : These are the complementary DDR2 strobe signals.
Single Channel mode: No connect.
Dual channel mode: Route to SO-DIMM B
NOTE: Signals do not exist in Intel 915GMS.
SB_MA[13:0]
O
SSTL1.8 / 2
Memory Address:
These signals are used to provide the multiplexed row and
column address to the SDRAM.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
NOTE: SB_MA13 is for support of 1 Gb devices.
SB_BS[2:0]
O
SSTL1.8 / 2
Bank Select:
These signals define which banks are selected within each
SDRAM rank.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
NOTE: SB_BS2 is for DDR2 support only.
SB_RAS#
O
SSTL1.8 / 2
RAS Control signal:
Used with SB_CAS# and SB_WE# (along with SM_CS#) to
define the SDRAM commands.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
41
Signal Description
R
Signal Name
SB_CAS#
Type
O
SSTL1.8 / 2
Description
CAS Control signal:
Used with SB_RAS# and SB_WE# (along with SM_CS#) to
define the SDRAM commands.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
SB_WE#
O
SSTL1.8 / 2
Write Enable Control signal:
Used with SB_RAS# and SB_CAS# (along with SM_CS#) to
define the SDRAM commands.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
SB_RCVENIN#
I
SSTL1.8 / 2
Clock Input:
Used to emulate source-synch clocking for reads.
Leave as No Connect.
NOTE: Signals do not exist in Intel 915GMS.
SB_RCVENOUT#
O
SSTL1.8 / 2
Clock Output:
Used to emulate source-synch clocking for reads.
Leave as No Connect.
NOTE: Signals do not exist in Intel 915GMS.
42
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
2.2.3
DDR / DDR2 Common Signals
Signal Name
Type
Description
SDRAM Differential Clock:
The crossing of the positive edge of SM_CKx and the negative edge of its
complement SM_CKx# are used to sample the command and control
signals on the SDRAM.
SM_CK[1:0],
SM_CK[4:3]
O
SSTL1.8 / 2
SM_CK[0:1] and its complement SM_CK[1:0]# signal make a differential
clock pair output.
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SM_CK[4:3] and its complement SM_CK[4:3]# signal make a differential
clock pair output.
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
NOTE: SM_CK2 and SM_CK5 are reserved and not supported.
SM_CK[1:0]#,
O
SM_CK[4:3]#
SSTL1.8 / 2
SDRAM Inverted Differential Clock:
These are the complementary Differential DDR2 Clock signals.
NOTE: SM_CK2# and SM_CK5# are reserved and not supported.
SM_CS[3:0]#
O
SSTL1.8 / 2
Chip Select: (1 per Rank):
These signals select particular SDRAM components during the active
state. There is one Chip Select for each SDRAM rank
SM_CS[1:0]# :
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SM_CS[3:2]# :
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
SM_CKE[3:0]
O
SSTL1.8 / 2
Clock Enable: (1 per Rank):
SM_CKE[3:0] is used:
⎯ To initialize the SDRAMs during power-up
⎯ To power-down SDRAM ranks
⎯ To place all SDRAM ranks into and out of self-refresh during STR.
SM_CKE[1:0]:
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SM_CKE[3:2]:
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
SM_ODT[3:0]
O
SSTL1.8
On Die Termination: Active Termination Control. (DDR2 only)
SM_ODT[1:0]:
Single channel mode: Route to SO-DIMM 0
Dual channel mode: Route to SO-DIMM A
SM_ODT[3:2]:
Single channel mode: Route to SO-DIMM 1
Dual channel mode: Route to SO-DIMM B
DDR: Leave as no connects. Not used for DDR devices.
DDR2: On-die termination for DDR2 devices.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
43
Signal Description
R
2.2.4
DDR SDRAM Reference and Compensation
Signal Name
Type
SMRCOMPN
I/O
A
Description
System Memory RCOMP N:
Buffer compensation
This signal is powered by the System Memory rail
(2.5 V for DDR, 1.8 V for DDR2).
SMRCOMPP
I/O
A
System Memory RCOMP P:
Buffer compensation
This signal is powered by the System Memory rail
SMXSLEWIN
I
X Buffer Slew Rate Input control.
A
SMXSLEWOUT
O
X Buffer Slew Rate Output control.
A
SMYSLEWIN
I
Y Buffer Slew Rate Input control.
A
SMYSLEWOUT
O
Y Buffer Slew Rate Output control.
A
SMVREF[1:0]
I
SDRAM Reference Voltage:
A
Reference voltage inputs for each DQ, DQS, & RCVENIN#.
Also used during ODT RCOMP.
SMOCDCOMP[1:0]
2.2.4.1
I
On-Die DRAM OCD driver compensation
A
OCD compensation
DDR / DDR2 Common Signal Mapping
Table 2-1. Single Channel Mode Signal Mapping for DDR/DDR2
Single Channel Signal Mapping
SO-DIMM 0
SO-DIMM 1
SM_CK [1:0]
SM_CK [4:3]
SM_CK# [1:0]
SM_CK# [4:3]
SM_CS# [1:0]
SM_CS# [3:2]
SM_CKE [1:0]
SM_CKE [3:2]
SM_ODT[1:0]
SM_ODT [3:2]
(DDR2 support only)
(DDR2 support only)
SA_BS [2:0]
SB_BS[2:0]
SA_MA[13:0]
SB_MA [13:0]
SA_RAS#
SB_RAS#
SA_CAS#
SB_CAS#
SA_WE#
SB_WE#
SA_DQ [63:0]
SA_DQS [7:0]
SA_DQS#[7:0]
SA_DM[7:0]
44
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
Table 2-2. Dual Channel Mode Signal Mapping for DDR/DDR2
Dual Channel Mode
Channel A
Channel B
SODIMM A
SODIMM B
SM_CK[1:0]
SM_CK[1:0]
NA
SM_CK[1:0]#
SM_CK[1:0]#
NA
SM_CK[4:3]
NA
SM_CK[4:3]
SM_CK[4:3]#
NA
SM_CK[4:3]#
SM_CS[1:0]#
SM_CS[1:0]#
NA
SM_CKE[1:0]
SM_CKE[1:0]
NA
SM_ODT[1:0]
SM_ODT[1:0]
NA
(DDR2 support)
(DDR2 support)
SM_CS[3:2]#
NA
SM_CS[3:2]#
SM_CKE[3:2]
NA
SM_CKE[3:2]
SM_ODT[3:2]
NA
(DDR2 support)
2.3
SM_ODT[3:2]
(DDR2 support)
PCI Express Based Graphics Interface Signals
Unless otherwise specified, these signals are AC coupled.
PCI Express Based Graphics is supported for Intel 915GM, Intel 915GME and Intel 915PM chipsets.
Signal Name
Type
Description
EXP_RXN[15:0]
I
PCI Express Receive Differential Pair
EXP_RXP[15:0]
PCIE
EXP_TXN[15:0]
O
EXP_TXP[15:0]
PCIE
EXP_ICOMPO
I
PCI Express Transmit Differential Pair
PCI Express Output Current and Resistance Compensation
A
EXP_COMPI
I
PCI Express Input Current Compensation
A
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
45
Signal Description
R
2.3.1
Serial DVO and PCI Express Based Graphics Signal Mapping
SDVO and PCI Express Interface for graphics architecture are muxed together. The following table
shows the signal mapping.
SDVOB and SDVOC interfaces are supported for Intel 915GM, Intel 915GME, Intel 910GML and
Intel 910GMLE chipsets.
SDVOB interface is supported for Intel 915GMS chipset as highlighted in GREY-20%.
Table 2-3. SDVO and PCI Express Based Graphics Port Signal Mapping
46
SDVO MODE
PCI Express MODE
SDVOB_RED#
EXP_TXN0
SDVOB_RED
EXP_TXP0
SDVOB_GREEN#
EXP_TXN1
SDVOB_GREEN
EXP_TXP1
SDVOB_BLUE#
EXP_TXN2
SDVOB_BLUE
EXP_TXP2
SDVOB_CLKN
EXP_TXN3
SDVOB_CLKP
EXP_TXP3
SDVOC_RED#
EXP_TXN4
SDVOC_RED
EXP_TXP4
SDVOC_GREEN#
EXP_TXN5
SDVOC_GREEN
EXP_TXP5
SDVOC_BLUE#
EXP_TXN6
SDVOC_BLUE
EXP_TXP6
SDVOC_CLKN
EXP_TXN7
SDVOC_CLKP
EXP_TXP7
SDVO_TVCLKIN#
EXP_RXN0
SDVO_TVCLKIN
EXP_RXP0
SDVOB_INT#
EXP_RXN1
SDVOB_INT
EXP_RXP1
SDVO_FLDSTALL#
EXP_RXN2
SDVO_FLDSTALL
EXP_RXP2
SDVOC_INT#
EXP_RXN5
SDVOC_INT
EXP_RXP5
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
2.4
DMI
DMI x2 or x4 is supported for Intel 915GM, Intel 915PM, Intel 915GME, Intel 910GML and Intel
910GMLE chipsets.
Signal Name
Type
DMI_RXP[3:0]
I
DMI_RXN[3:0]
PCIE
DMI_TXP[3:0]
O
DMI_TXN[3:0]
PCIE
Description
DMI input from ICH6-M:
Direct Media Interface receive differential pair
DMI output to ICH6-M:
Direct Media Interface transmit differential pair
DMI x2 is supported for Intel 915GMS chipset
Signal Name
2.5
Type
DMI_RXP[1:0]
I
DMI_RXN[1:0]
PCIE
DMI_TXP[1:0]
O
DMI_TXN[1:0]
PCIE
Description
DMI input from ICH6-M:
Direct Media Interface receive differential pair
DMI output to ICH6-M:
Direct Media Interface transmit differential pair
Integrated Graphics Interface Signals
The Integrated Graphics Interface signals in Section 2.5 are supported for the Intel 915GM, Intel
915GMS, Intel 915GME, Intel 910GML and the Intel 910GMLE chipsets. These signals are reserved
for the Intel 915PM chipset.
Note: Please refer to the platform design guide for details for recommendation for these signal
groups.
Note:
2.5.1
Signals in section 2.5.2 are not supported on Intel 915GME and Intel 910GMLE chipsets.
CRT DAC Signals
Signal
Name
RED
RED#
GREEN
GREEN#
BLUE
BLUE#
REFSET
Type
Description
O
RED Analog Video Output:
A
This signal is a CRT Analog video output from the internal color palette DAC.
O
RED# Analog Output:
A
This signal is an analog video output from the internal color palette DAC. This
signal is used to provide noise immunity.
O
GREEN Analog Video Output:
A
This signal is a CRT Analog video output from the internal color palette DAC.
O
GREEN# Analog Output:
A
This signal is an analog video output from the internal color palette DAC. This
signal is used to provide noise immunity.
O
BLUE Analog Video Output:
A
This signal is a CRT Analog video output from the internal color palette DAC.
O
BLUE# Analog Output:
A
This signal is an analog video output from the internal color palette DAC. This
signal is used to provide noise immunity.
O
Resistor Set:
A
Set point resistor for the internal color palette DAC. A 256-Ω ± 1% resistor is
required between REFSET and motherboard ground.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
47
Signal Description
R
Signal
Name
HSYNC
Type
O
CRT Horizontal Synchronization:
HVCMOS
VSYNC
O
This signal is used as the horizontal sync (polarity is programmable) or “sync
interval”.
CRT Vertical Synchronization:
HVCMOS
2.5.2
Description
This signal is used as the vertical sync (polarity is programmable).
Analog TV-out Signals
Note: Analog TV-out signals are not supported on the Intel 915GME and Intel 910GMLE chipsets.
Please follow design guide recommendations to properly terminate these signals on the motherboard.
Signal Name
TVDAC_A
Type
Description
O
TVDAC Channel A Output:
A
TVDAC_A supports the following:
Composite: CVBS signal
Component: Chrominance (Pb) analog signal
TVDAC_B
O
TVDAC Channel B Output:
A
TVDAC_B supports the following:
S-Video: Luminance analog signal
Component: Luminance (Y) analog signal
TVDAC_C
O
TVDAC Channel C Output:
A
TVDAC_C supports the following:
S-Video: Chrominance analog signal
Component: Chrominance (Pr) analog signal
TV_IRTNA
TV_IRTNB
TV_IRTNC
TV_REFSET
48
O
Current Return for TVDAC Channel A:
A
Connect to ground on board
O
Current Return for TVDAC Channel B:
A
Connect to ground on board
O
Current Return for TVDAC Channel C:
A
Connect to ground on board
O
TV Resistor set:
A
TV Reference Current uses an external resistor to set internal reference voltage
levels. A 5-kΩ ± 0.5% resistor is required between REFSET and motherboard
ground.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
2.5.3
LVDS Signals
Note:
LVDS Channel B interface is not supported and do not exist for Intel 915GMS.
Signal Name
Type
Description
LDVS Channel A
LADATAP[2:0]
I/O
Channel A differential data output - positive
LVDS
LADATAN[2:0]
I/O
Channel A differential data output –negative
LVDS
LACLKP
I/O
Channel A differential clock output – positive
LVDS
LACLKN
I/O
Channel A differential clock output – negative
LVDS
LDVS Channel B
LBDATAP[2:0]
LBDATAN[2:0]
LBCLKP
LBCLKN
I/O
Channel B differential data output – positive
LVDS
NOTE: Signals do not exist in Intel 915GMS.
I/O
Channel B differential data output –negative
LVDS
NOTE: Signals do not exist in Intel 915GMS.
I/O
Channel B differential clock output – positive
LVDS
NOTE: Signals do not exist in Intel 915GMS.
I/O
Channel B differential clock output – negative
LVDS
NOTE: Signals do not exist in Intel 915GMS.
LFP Panel power and backlight control
LVDD_EN
O
HVCMOS
LBKLT_EN
O
HVCMOS
LBKLT_CRTL
O
HVCMOS
LVDS panel power enable: Panel power control enable control.
This signal is also called VDD_DBL in the CPIS specification and is
used to control the VDC source to the panel logic.
LVDS backlight enable: Panel backlight enable control.
This signal is also called ENA_BL in the CPIS specification and is used
to gate power into the backlight circuitry.
Panel backlight brightness control: Panel brightness control.
This signal is also called VARY_BL in the CPIS specification and is
used as the PWM Clock input signal.
LVDS Reference signals
LIBG
LVREFH
I/O
LVDS Reference Current. –
Ref
1.5 kΩ Pull down resistor needed
I
Reserved. - No connect.
Ref
LVREFL
I
Reserved. - No connect.
Ref
LVBG
O
Reserve. - No connect
A
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
49
Signal Description
R
2.5.4
Serial DVO Interface
All of the pins in this section are multiplexed with the upper eight lanes of the PCI Express interface.
SDVOB and SDVOC interfaces are supported for Intel 915GM, Intel 915GME, Intel 910GML and
Intel 910GMLE chipsets. SDVOB interface is supported for Intel 915GMS chipset as highlighted in
GREY-20%.
Signal Name
Type
Description
SDVO B Interface
SDVOB_CLKP
O
PCIE
SDVOB_CLKN
O
PCIE
SDVOB_RED
O
PCIE
SDVOB_RED#
O
PCIE
SDVOB_GREEN
O
PCIE
SDVOB_GREEN#
O
PCIE
SDVOB_BLUE
O
PCIE
SDVOB_BLUE#
O
PCIE
Serial Digital Video B Clock.
Multiplexed with EXP_TXP_3.
Serial Digital Video B Clock Complement.
Multiplexed with EXP_TXN_3.
Serial Digital Video B Red Data.
Multiplexed with EXP_TXP_0.
Serial Digital Video B Red Data Complement.
Multiplexed with EXP_TXN_0.
Serial Digital Video B Green Data.
Multiplexed with EXP_TXP_1.
Serial Digital Video B Green Data Complement.
Multiplexed with EXP_TXN_1.
Serial Digital Video B Blue Data.
Multiplexed with EXP_TXP_2.
Serial Digital Video B Blue Data Complement.
Multiplexed with EXP_TXN_2.
SDVO C Interface
SDVOC_RED
O
PCIE
Serial Digital Video C Red Data / SDVO B Alpha.
Multiplexed with EXP_TXP_4.
NOTE: Signals do not exist in Intel 915GMS.
SDVOC_RED#
O
PCIE
Serial Digital Video C Red Complement / Alpha Complement.
Multiplexed with EXP_TXN_4.
NOTE: Signals do not exist in Intel 915GMS.
SDVOC_GREEN
O
PCIE
Serial Digital Video C Green.
Multiplexed with EXP_TXP_5.
NOTE: Signals do not exist in Intel 915GMS.
SDVOC_GREEN#
O
PCIE
Serial Digital Video C Green Complement.
Multiplexed with EXP_TXN_5.
NOTE: Signals do not exist in Intel 915GMS.
SDVOC_BLUE
O
PCIE
Serial Digital Video Channel C Blue.
Multiplexed with EXP_TXP_6.
NOTE: Signals do not exist in Intel 915GMS.
SDVOC_BLUE#
O
PCIE
Serial Digital Video C Blue Complement.
Multiplexed with EXP_TXN_6.
NOTE: Signals do not exist in Intel 915GMS.
50
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
Signal Name
SDVOC_CLKP
Type
O
Description
Serial Digital Video C Clock.
PCIE
Multiplexed with EXP_TXP_7.
NOTE: Signals do not exist in Intel 915GMS.
SDVOC_CLKN
O
Serial Digital Video C Clock Complement.
PCIE
Multiplexed with EXP_TXN_7.
NOTE: Signals do not exist in Intel 915GMS.
SDVO Common Signals
SDVO_TVCLKIN
I
Serial Digital Video TVOUT Synchronization Clock.
PCIE
SDVO_TVCLKIN#
SDVO_FLDSTALL
SDVO_FLDSTALL#
I
Serial Digital Video TV-out Synchronization Clock Complement.
PCIE
Multiplexed with EXP_RXN_0.
I
Serial Digital Video Field Stall.
PCIE
Multiplexed with EXP_RXP_2.
I
Serial Digital Video Field Stall Complement.
PCIE
SDVOB_INT
I
I
I
I
Multiplexed with EXP_RXP_5.
Serial Digital Video Input Interrupt Complement.
PCIE
2.5.5
Multiplexed with EXP_RXN_1.
Serial Digital Video Input Interrupt.
PCIE
SDVOC_INT#
Multiplexed with EXP_RXP_1.
Serial Digital Video Input Interrupt Complement.
PCIE
SDVOC_INT
Multiplexed with EXP_RXN_2.
Serial Digital Video Input Interrupt.
PCIE
SDVOB_INT#
Multiplexed with EXP_RXP_0.
Multiplexed with EXP_RXN_5.
Display Data Channel (DDC) and GMBUS Support
Signal Name
LCTLA_CLK
Type
I/O
COD
LCTLB_DATA
I/O
COD
DDCCLK
I/O
Description
I2C Based control signal (Clock) for External SSC clock chip
control –
I2C Based control signal (Data) for External SSC clock chip control
–
CRT DDC clock monitor control support
COD
DDCDATA
I/O
CRT DDC Data monitor control support
COD
LDDC_CLK
I/O
EDID support for flat panel display
COD
LDDC_DATA
I/O
EDID support for flat panel display
COD
SDVOCTRL_CLK
I/O
I2C Based control signal (Clock) for SDVO device
COD
SDVOCTRL_DATA
I/O
I2C Based control signal (Data) for SDVO device
COD
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
51
Signal Description
R
2.6
PLL Signals
Note: PLL interfaces signal group are supported on the Mobile Intel 915GM/PM/GMS/GME and
Intel 910GML/GMLE Express chipsets, unless otherwise noted.
Signal Name
HCLKP
Type
I
Diff Clk
HCLKN
I
Description
Differential Host Clock In:
Differential clock input for the Host PLL. Used for phase cancellation for FSB
transactions. This clock is used by all of the GMCH logic that is in the Host clock
domain. Also used to generate core and system memory internal clocks. This is
a low voltage differential signal and runs at ¼ the FSB data rate.
Differential Host Clock Input Complement:
Diff Clk
GCLKP
I
Diff Clk
GCLKN
I
Differential PCI Express based Graphics / DMI Clock In:
These pins receive a differential 100 MHz Serial Reference clock from the
external clock synthesizer. This clock is used to generate the clocks necessary
for the support of PCI Express.
Differential PCI Express based Graphics / DMI Clock In complement
Diff Clk
DREF_CLKP
DREF_CLKN
I
Diff Clk
Display PLL Differential Clock In, no SSC support –
I
Display PLLA Differential Clock In Complement –
Diff Clk
DREF_SSCLKP
Display PLLA Differential Clock In –
I
Diff Clk
Display PLL Differential Clock In Complement - no SSC support
Display PLLB Differential Clock In –
Optional Display PLL Differential Clock In for SSC support –
NOTE: Differential Clock input for optional SSC support for LVDS display.
DREF_SSCLKN
I
Diff Clk
Display PLLB Differential Clock In complement –
Optional Display PLL Differential Clock In Complement for SSC support
NOTE: Differential Clock input for optional SSC support for LVDS display.
52
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
2.7
Reset and Miscellaneous Signals
Reset and Miscellaneous interfaces signal group is supported the Mobile Intel 915GM/PM/GMS/GME
and Intel 910GML/GMLE Express chipsets, unless otherwise noted.
Signal Name
RSTIN#
Type
I
HVCMOS
PWROK
I
HVCMOS
Description
Reset In:
When asserted this signal will asynchronously reset the GMCH logic. This signal
is connected to the PLT_RST# output of the ICH6-M. This input has a Schmitt
trigger to avoid spurious resets. This input buffer is 3.3-V tolerant.
Power OK:
When asserted, PWROK is an indication to the GMCH that core power has been
stable for at least 10 µs.
This input buffer is 3.3-V tolerant.
H_BSEL [2:0]
(CFG[2:0])
I
HVCMOS
Host Bus Speed Select:
At the deassertion of RSTIN#, the value sampled on these pins determines the
expected frequency of the bus.
External pull-ups are required.
CFG[17:3]
I
AGTL+
HW straps:
CFG [17:3] has internal pull up.
NOTE: Not all CFG Balls are supported for Intel 915GMS.
CFG[20:18]
I
HW straps:
HVCMOS
CFG [20:18] has internal pull down
O
GMCH Integrated Graphics Busy:
NOTE: Not all CFG Balls are supported for Intel 915GMS.
BM_BUSY#
HVCMOS
THRMTRIP#
O
COD
EXT_TS[1:0]#
I
HVCMOS
Indicates to the ICH that the integrated graphics engine within the MCH is busy
and transitions to low power states should not be attempted until that is no
longer the case.
GMCH Thermal Trip:
Assertion of THERMTRIP# (Thermal Trip) indicates the GMCH junction
temperature has reached a level beyond which damage may occur. Upon
assertion of THERMTRIP#, the GMCH will shut off its internal clocks (thus
halting program execution) in an attempt to reduce the GMCH core junction
temperature. To protect GMCH, its core voltage (Vcc) must be removed
following the assertion of THERMTRIP#. Once activated, THERMTRIP# remains
latched until RSTIN# is asserted. While the assertion of the RSTIN# signal will
deassert THERMTRIP#, if the GMCH’s junction temperature remains at or
above the trip level, THERMTRIP# will again be asserted.
External Thermal Sensor Input:
If the system temperature reaches a dangerously high value then this signal can
be used to trigger the start of system memory throttling.
NOTE: EXT_TS1# functionality is not supported in 915GMS. A pull up is
required on this pin
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
53
Signal Description
R
2.8
Power and Ground
Interface
Ball Name
Description
Host
VTT (VCCP)
FSB power supply (1.05 V) - (VCCP)
DRAM
VCCA_SM
VCCASM is the Analog power supply for SM data buffers used for DLL &
other logic (1.5 V)
VCCSM
System memory power supply (DDR=2.5 V; DDR2=1.8 V)
VCC3G
PCI Express / DMI Analog power supply (1.5 V)
PCI Express
Based
Graphics /
DMI
PLL Analog
VCCA_3GBG
PCI Express / DMI band gap power supply (2.5 V)
VSSA_3GBG
PCI Express / DMI band gap ground
VCCA_HPLL
Power supply for the Host VCO in the host/mem/core PLL (1.5 V)
VCCA_MPLL
Power supply for the mem VCO in the host/mem/core PLL (1.5 V)
VCCD_HMPLL
Power Supply for the digital dividers in the HMPLL (1.5 V)
VCCA_3GPLL
Power supply for the 3GIO PLL (1.5 V)
VCCA_DPLLA
Display A PLL power supply (1.5 V)
VCCA_DPLLB
Display B PLL power supply (1.5 V)
High Voltage
Interfaces
VCCHV
Power supply for the HV buffers (2.5 V)
CRT DAC
VCCA_CRTDAC
Analog power supply for the DAC (2.5 V)
VSSA_CRTDAC
Analog ground for the DAC
VCC_SYNC
Power supply for HSYNC/ VSYNC (2.5 V)
LVDS
TVDAC
VCCD_LVDS
Digital power supply (1.5 V)
VCCTX_LVDS
Data/Clk Tx power supply (2.5 V)
VCCA_LVDS
LVDS analog power supply (2.5 V)
VSSALVDS
LVDS analog VSS
VCCA_TVBG
TV DAC Band Gap Power (3.3 V)
VSSA_TVBG
TV DAC Band Gap VSS
VCCD_TVDAC
Dedicated Power Supply for TVDAC (1.5 V)
VCCDQ_TVDAC
Power Supply for Digital Quiet TVDAC (1.5 V)
VCCA_TVDACA
Power Supply for TV Out Channel A (3.3 V)
VCCA_TVDACB
Power Supply for TV Out Channel B (3.3 V)
VCCA_TVDACC
Power Supply for TV Out Channel C (3.3 V)
Core
VCC
Core VCC – (1.05 V or 1.5 V)
Ground
VSS
Ground
NCTF
Non-Critical To Function power signals:
“NCTF” (Non-Critical To Function) have been designed into the package footprint to enhance the
Solder Joint Reliability of our products by absorbing some of the stress introduced by the
Characteristic Thermal Expansion (CTE) mismatch of the Die to package interface. It is expected
that in some cases, these balls may crack partially or completely, however, this will have no
impact to our product performance or reliability. Intel has added these balls primarily to serve as
sacrificial stress absorbers.
NOTE: Signals do not exist in Intel 915GMS.
54
VTT_NCTF
NCTF FSB power supply (1.05 V or 1.2 V)
VCC_NCTF
NTCF Core VCC – (1.05 V or 1.5 V)
VCCSM_NCTF
NTCF System memory power supply (DDR=2.5 V; DDR2=1.8 V)
VSS_NCTF
NTCF Ground
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
2.9
Reset States and Pull-Up / Pull-Downs
This section describes the expected states of the GMCH I/O buffers during and immediately after the
assertion of RSTIN#. This table only refers to the contributions on the interface from the GMCH and
does not reflect any external influence (such as external pull-up/pull-down resistors or external drivers.
Legend:
DRIVE:
Strong drive (to normal value supplied by the core logic if not otherwise stated)
TERM:
Normal termination devices are turned on
LV:
Low voltage
HV:
High voltage
IN:
Input buffer enabled
ISO:
Isolate input buffer so that it doesn’t oscillate if input left floating.
TRI:
Tri-state
PU:
Weak internal pull-up
PD:
Weak internal pull-down
STRAP:
Strap input sampled during assertion or on the deasserting edge of RSTIN#
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
55
Signal Description
R
2.9.1
Host Interface Signals
Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination
voltage of the host bus (VCCP).
Signal Name
Type
State during
RSTIN# Assertion
State after RSTIN#
Deassertion
S3
HADS#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HBNR#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HBPRI#
O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HBREQ0#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
O
DRIVE LV
TERM HV after ~ 1ms
TRI
(No VTT)
HCPURST#
CMOS
HDBSY#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HDEFER#
O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HDINV[3:0]#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
I/O
TERM HV
TERM HV
TRI
(No VTT)
HDRDY#
AGTL+
HA[31:3]#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HADSTB[1:0]#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HD[63:0]#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HDSTBP[3:0]#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HDSTBN[3:0]#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HHIT#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HHITM#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HLOCK#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HREQ[4:0]#
I/O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HTRDY#
O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
HRS[2:0]#
O
AGTL+
TERM HV
TERM HV
TRI
(No VTT)
O
TERM HV
TERM HV
TRI
(No VTT)
IN
IN
HDPWR#
AGTL+
HCPUSLP#
O
PU/PD
CMOS
56
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
2.9.2
Host Interface Reference and Compensation
Signal
Name
HVREF
Type
State during
RSTIN# Assertion
State after RSTIN#
Deassertion
S3
I
IN
IN
TRI
TRI
TRI after RCOMP
TRI
TRI
TRI after RCOMP
TRI
IN
IN
TRI
TRI after RCOMP
TRI
TRI
TRI after RCOMP
TRI
IN
IN
PU/PD
A
HXRCOMP
I/O
A
HXSCOMP
I/O
A
HXSWING
I
A
HYRCOMP
I/O
A
HYSCOMP
I/O
A
HYSWING
I
A
2.9.3
DDR / DDR2 SDRAM Channel A Interface
Signal Name
SA_DQ[63:0]
Type
State during RSTIN#
Assertion
State after RSTIN#
Deassertion
I/O
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
IN
IN
HV
HV
S3
PU/PD
SSTL1.8 / 2
SA_DM[7:0]
O
SSTL1.8 / 2
SA_DQS[7:0]
I/O
SSTL1.8
SA_DQS[7:0]#
I/O
SSTL1.8
SA_MA[13:0]
O
SSTL1.8 / 2
SA_BS[2:0]
O
SSTL1.8 / 2
SA_RAS#
O
SSTL1.8 / 2
SA_CAS#
O
SSTL1.8 / 2
SA_WE#
O
SSTL1.8 / 2
SA_RCVENIN#
I
SSTL1.8 / 2
SA_RCVENOUT#
O
SSTL1.8 / 2
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
57
Signal Description
R
2.9.4
DDR / DDR2 SDRAM Channel B Interface
Signal Name
Type
State during
RSTIN# Assertion
State after RSTIN#
Deassertion
I/O
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
IN
IN
HV
HV
SB_DQ[63:0]
S3
PU/PD
SSTL1.8 / 2
SB_DM[7:0]
O
SSTL1.8 / 2
SB_DQS[7:0]
I/O
SSTL1.8 / 2
SB_DQS[7:0]#
I/O
SSTL1.8
SB_MA[13:0]
O
SSTL1.8 / 2
SB_BS[2:0]
O
SSTL1.8 / 2
SB_RAS#
O
SSTL1.8 / 2
SB_CAS#
O
SSTL1.8 / 2
SB_WE#
O
SSTL1.8 / 2
SB_RCVENIN#
I
SSTL1.8 / 2
SB_RCVENOUT#
O
SSTL1.8 / 2
2.9.5
DDR / DDR2 Common Signals
Signal Name
Type
State during
RSTIN# Assertion
State after RSTIN#
Deassertion
SM_CK[1:0],
O
TRI
TRI
SM_CK[4:3]
SSTL1.8 / 2
TRI
TRI
TRI
TRI
LV
LV
0
LV
SM_CK[1:0]#,
O
SM_CK[4:3]#
SSTL1.8 / 2
SM_CS[3:0]#
O
S3
PU/PD
SSTL1.8 / 2
SM_CKE[3:0]
O
SSTL1.8 / 2
SM_ODT[3:0]
O
SSTL1.8
58
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
2.9.6
DDR SDRAM Reference and Compensation
Signal Name
SMRCOMPN
Type
State during
RSTIN# Assertion
State after RSTIN#
Deassertion
I/O
TRI
TRI after RCOMP
TRI
TRI after RCOMP
IN
IN
TRI
TRI after RCOMP
IN
IN
TRI
TRI after RCOMP
IN
IN
TRI
TRI
S3
PU/PD
A
SMRCOMPP
I/O
A
SMXSLEWIN
I
A
SMXSLEWOUT
O
A
SMYSLEWIN
I
A
SMYSLEWOUT
O
A
SMVREF[1:0]
I
A
SMOCDCOMP[1:0]
I
A
2.9.7
PCI Express Based Graphics Interface Signals
Signal Name
EXP_RXN[15:0]
Type
State during
RSTIN# Assertion
State after RSTIN#
Deassertion
I
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
S3
PU/PD
PCIE
EXP_RXP[15:0]
I
PCIE
EXP_TXN[15:0]
O
PCIE
EXP_TXP[15:0]
O
PCIE
EXP_ICOMPO
I
A
EXP_COMPI
I
A
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
59
Signal Description
R
2.9.8
DMI
Signal Name
Type
State during
RSTIN#
Assertion
State after RSTIN#
Deassertion
I
TRI
TRI
TRI
TRI
TRI
TRI
TRI
TRI
DMI_RXN[3:0]
S3
PU/PD
PCIE
DMI_RXP[3:0]
I
PCIE
DMI_TXN[3:0]
O
PCIE
DMI_TXP[3:0]
O
PCIE
2.9.9
CRT DAC SIGNALS
Signal
Name
RED
Type
State during
RSTIN# Assertion
O
LV
State after RSTIN#
Deassertion
S3
PU/PD
A
RED#
O
LV
A
GREEN
O
LV
A
GREEN#
O
LV
A
BLUE
O
LV
A
BLUE#
O
LV
A
REFSET
O
TRI
A
HSYNC
O
0.5 x Bandgap
255 ohm 1%
resistor to
ground
LV
HVCMOS
VSYNC
O
LV
HVCMOS
60
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
2.9.10
Analog TV-out Signals
Note:
These signals are not supported on the Intel 915GME and Intel 910GMLE chipsets.
Signal Name
TVDAC_A
TVDAC_B
TVDAC_C
TV_IRTNA
TV_IRTNB
TV_IRTNC
TV_REFSET
Type
State during
RSTIN# Assertion
State after RSTIN#
Deassertion
S3
PU/PD
O
A
O
A
O
A
O
A
O
A
O
A
O
A
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
61
Signal Description
R
2.9.11
LVDS Signals
Signal Name
Type
State during
RSTIN# Assertion
State after RSTIN#
Deassertion
I/O
Drive VSS
Drive VSS
Drive VSS
Drive VSS
Drive VSS
Drive VSS
Drive VSS
Drive VSS
Drive VSS
Drive VSS
Drive VSS
Drive VSS
Drive VSS
Drive VSS
Drive VSS
Drive VSS
TRI
TRI
TRI
TRI
TRI
TRI
IN
IN
IN
IN
S3
PU/PD
LDVS Channel A
LADATAP[2:0]
LVDS
LADATAN[2:0]
I/O
LVDS
LACLKP
I/O
LVDS
LACLKN
I/O
LVDS
LDVS Channel B
LBDATAP[2:0]
I/O
LVDS
LBDATAN[2:0]
I/O
LVDS
LBCLKP
I/O
LVDS
LBCLKN
I/O
LVDS
LFP Panel
control signal
LVDD_EN
O
HVCMOS
LBKLT_EN
O
HVCMOS
LBKLT_CRTL
O
HVCMOS
LVDS Reference
signal
LVREFH
I
Ref
LVREFL
I
Ref
62
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Signal Description
R
2.9.12
Display Data Channel (DDC) and GMBUS Support
Signal Name
LCTLA_CLK
Type
State during
RSTIN# Assertion
State after RSTIN#
Deassertion
I/O
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
PU
STRAP
PU
S3
PU/PD
S3
PU/PD
COD
LCTLB_DATA
I/O
COD
DDCCLK
I/O
COD
DDCDATA
I/O
COD
LDDC_CLK
I/O
COD
LDDC_DATA
I/O
COD
SDVOCTRL_CLK
I/O
COD
SDVOCTRL_DATA
I/O
COD
2.9.13
PLL Signals
Signal Name
HCLKP
Type
State during RSTIN#
Assertion
State after RSTIN#
Deassertion
I
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Diff Clk
HCLKN
I
Diff Clk
GCLKP
I
Diff Clk
GCLKN
I
Diff Clk
DREF_CLKP
I
Diff Clk
DREF_CLKN
I
Diff Clk
DREF_SSCLKP
I
Diff Clk
DREF_SSCLKN
I
Diff Clk
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
63
Signal Description
R
2.9.14
Reset and Miscellaneous Signals
Signal Name
RSTIN#
Type
State during RSTIN#
Assertion
State after RSTIN#
Deassertion
I
IN
IN
HV
HV
HV STRAP
HV
IN
IN
S3
PU/PD
HVCMOS
PWROK
I
HVCMOS
H_BSEL [2:0]
(CFG[2:0])
CFG[17:3]
I
HVCMOS
I
AGTL+
CFG[20:18]
I
HVCMOS
BM_BUSY#
O
HVCMOS
THRMTRIP#
O
COD
EXT_TS[1:0]#
I
HVCMOS
§
64
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
GMCH Register Description
R
3
GMCH Register Description
Table 3-1 shows the register-related terminology that is used.
Table 3-1. Register Terminology
RO
Read Only bit(s). Writes to these bits have no effect.
RS/WC
Read Set / Write Clear bit(s). These bits are set to 1 when read and then will continue to remain set
until written. A write of 1 clears (sets to 0) the corresponding bit(s) and a write of 0 has no effect.
R/W
Read / Write bit(s). These bits can be read and written.
R/WC
Read / Write Clear bit(s). These bits can be read. Internal events may set this bit. A write of 1 clears
(sets to 0) the corresponding bit(s) and a write of 0 has no effect.
R/WC/S
Read / Write Clear / Sticky bit(s). These bits can be read. Internal events may set this bit. A write of 1
clears (sets to 0) the corresponding bit(s) and a write of 0 has no effect. Bits are not cleared by
"warm" reset, but will be reset with a cold/complete reset (for PCI Express* related bits a cold reset is
“Power Good Reset” as defined in the PCI Express spec).
R/W/L
Read / Write / Lockable bit(s). These bits can be read and written. Additionally there is a bit (which
may or may not be a bit marked R/W/L) that, when set, prohibits this bit field from being writeable (bit
field becomes Read Only).
R/W/S
Read / Write / Sticky bit(s). These bits can be read and written. Bits are not cleared by "warm" reset,
but will be reset with a cold/complete reset (for PCI Express related bits a cold reset is “Power Good
Reset” as defined in the PCI Express spec).
R/WSC
Read / Write Self Clear bit(s). These bits can be read and written. When the bit is 1, hardware may
clear the bit to 0, based upon internal events, possibly sooner than any subsequent read could
retrieve a 1.
R/WSC/L
Read / Write Self Clear / Lockable bit(s). These bits can be read and written. When the bit is 1,
hardware may clear the bit to 0, based upon internal events, possibly sooner than any subsequent
read could retrieve a 1. Additionally there is a bit (which may or may not be a bit marked R/W/L) that,
when set, prohibits this bit field from being writeable (bit field becomes Read Only).
R/WC
Read Write Clear bit(s). These bits can be read and written. However, a write of 1 clears (sets to 0)
the corresponding bit(s) and a write of 0 has no effect.
R/WO
Write Once bit(s). Once written, bits with this attribute become Read Only. These bits can only be
cleared by a Reset.
W
Write Only. Whose bits may be written, but will always-return 0’s when read. They are used for write
side effects. Any data written to these registers cannot be retrieved.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
65
GMCH Register Description
R
3.1
Configuration Process and Registers
3.1.1
Platform Configuration Structure
In platforms that support DMI (e.g., this GMCH) the configuration structure is significantly different
from previous Hub architectures. The DMI physically connects the GMCH and the ICH6; so, from a
configuration standpoint, the DMI is logically PCI bus 0. As a result, all devices internal to the GMCH
and the ICH6 appear to be on PCI bus 0. The system’s primary PCI expansion bus is physically
attached to the ICH6 and, from a configuration perspective, appears to be a hierarchical PCI bus behind
a PCI-to-PCI bridge and therefore has a programmable PCI bus number. The PCI Express Graphics
Attach appears to system software to be a real PCI bus behind a PCI-to-PCI bridge that is a device
resident on PCI bus 0.
Note: That a physical PCI bus 0 does not exist and that DMI and the internal devices in the GMCH
and ICH6 logically constitute PCI Bus 0 to configuration software. This is shown in the following
figure.
Figure 3-1. Conceptual Platform PCI Configuration Diagram
Processor
Intel® 915M
Express Chipset
PCI Configuration in I/O
DRAM
Interface Bus
0 Device 0
PCI Express* x16 Bus
0 Device 1 (excludes
the Intel® 915GMS
and 910GML)
Bus 0 Device 2
(excludes Intel® 915PM)
DMI
The GMCH contains three PCI devices within a single physical component. The configuration registers
for the three devices are mapped as devices residing on PCI bus 0.
• Device 0: Host Bridge/DRAM Controller. Logically this appears as a PCI device residing on PCI
bus 0. Device 0 contains the standard PCI header registers, PCI Express base address register,
DRAM control (including thermal/throttling control), and other GMCH specific registers.
• Device 1: Host-PCI Express Bridge. Logically this appears as a “virtual” PCI-to-PCI bridge
residing on PCI bus 0 and is compliant with PCI Express Specification rev 1.0. Device 1 contains
the standard PCI-to-PCI bridge registers and the standard PCI Express/PCI configuration registers
(including the PCI Express memory address mapping). It also contains Isochronous and Virtual
Channel controls in the PCI Express extended configuration space.
• Device 2: Internal Graphics Control. Logically, this appears as a PCI device residing on PCI bus 0.
Physically, device 2 contains the configuration registers for 3D, 2D, and display functions.
66
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
GMCH Register Description
R
Table 3-2. Device Number Assignment for Internal GMCH Devices
GMCH Function
3.1.2
Device#
Host Bridge / DRAM Controller
Device 0
Host-to-PCI Express* Bridge (virtual PCI-to-PCI)
Device 1
Internal Graphics Control
Device 2
General Routing Configuration Accesses
The GMCH supports two PCI related interfaces: DMI and PCI Express. PCI and PCI Express
configuration cycles are selectively routed to one of these interfaces. The GMCH is responsible for
routing configuration cycles to the proper interface. Configuration cycles to the ICH6 internal devices
and Primary PCI (including downstream devices) are routed to the ICH6 via DMI. Configuration
cycles to both the PCI Express Graphics PCI compatibility configuration space and the PCI Express
Graphics extended configuration space are routed to the PCI Express Graphics port.
A detailed description of the mechanism for translating CPU I/O bus cycles to configuration cycles is
described below.
3.1.3
Standard PCI Bus Configuration Mechanism
The PCI bus defines a slot based configuration space that allows each device to contain up to eight
functions with each function containing up to 256, 8-bit configuration registers. The PCI specification
defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration
Write. Memory and I/O spaces are supported directly by the CPU. Configuration space is supported by
a mapping mechanism implemented within the GMCH.
The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at I/O address
0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh though 0CFFh). To
reference a configuration register a DW I/O write cycle is used to place a value into
CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the device
and a specific configuration register of the device function being accessed. CONFIG_ADDRESS [31]
must be 1 to enable a configuration cycle. CONFIG_DATA then becomes a window into the four bytes
of configuration space specified by the contents of CONFIG_ADDRESS. Any read or write to
CONFIG_DATA will result in the GMCH translating the CONFIG_ADDRESS into the appropriate
configuration cycle.
The GMCH is responsible for translating and routing the CPU’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH configuration registers, DMI
or PCI Express.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
67
GMCH Register Description
R
3.1.4
Logical PCI Bus 0 Configuration Mechanism
The GMCH decodes the Bus Number (bits 23:16) and the Device Number fields of the
CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the configuration
cycle is targeting a PCI Bus 0 device. The Host-DMI Bridge entity within the GMCH is hardwired as
Device 0 on PCI Bus 0. The Host-PCI Express Bridge entity within the GMCH is hardwired as Device
1 on PCI Bus 0. Device 2 contains the control registers for the Integrated Graphics Controller. The
ICH6 decodes the Type 0 access and generates a configuration access to the selected internal device.
3.1.5
Primary PCI and Downstream Configuration Mechanism
If the Bus Number in the CONFIG_ADDRESS is non-zero, and falls outside the range claimed by the
Host-PCI Express bridge (not between lower bound in device’s SUBORDINATE BUS NUMBER
register and upper bound in device’s SECONDARY BUS NUMBER register), the GMCH would
generate a Type 1 DMI Configuration Cycle. This DMI configuration cycle will be sent over the DMI.
If the cycle is forwarded to the ICH6 via the DMI, the ICH6 compares the non-zero Bus Number with
the SECONDARY BUS NUMBER and SUBORDINATE BUS NUMBER registers of its PCI-to-PCI
bridges to determine if the configuration cycle is meant for Primary PCI, one of the ICH’s devices, the
DMI, or a downstream PCI bus.
Figure 3-2. DMI Type 0 Configuration Address Translation
Configuration_Adddress
31
30
1
Bus
Number
Reserved
11 10
16 15
24 23
Device Number
87
Function
21
Double Word
0
XX
DMI Type 0 Configuration Address Extension
30
31
1
68
0CFB
Reserved
24 23
0CFA
Bus
Number
16 15
0CF9
11 10
Device Number
87
Function
0CF8
Double Word
21
0
00
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
GMCH Register Description
R
Figure 3-3. DMI Type 1 Configuration Address Translation
Configuration_Adddress
31
30
1
Bus
Number
Reserved
11 10
16 15
24 23
Device Number
87
Function
21
Double Word
0
XX
DMI Type1 Configuration Address Extension
30
31
1
3.1.6
0CFB
Reserved
24 23
0CFA
Bus
Number
16 15
0CF9
11 10
Device Number
87
Function
0CF8
Double Word
21
0
01
PCI Express Enhanced Configuration Mechanism
PCI Express extends the configuration space to 4096 bytes per device/function as compared to
256 bytes allowed by PCI Specification Revision 2.3. PCI Express configuration space is divided into a
PCI 2.3 compatible region, which consists of the first 256 bytes of a logical device’s configuration
space and a PCI Express extended region, which consists of the remaining configuration space.
The PCI compatible region can be accessed using either the mechanism defined in the previous section
or using the enhanced PCI Express configuration access mechanism described in this section. The
extended configuration registers may only be accessed using the enhanced PCI Express configuration
access mechanism. To maintain compatibility with PCI configuration addressing mechanisms, system
software must access the extended configuration space using 32-bit operations (32-bit aligned) only.
These 32-bit operations include byte enables allowing only appropriate bytes within the DWORD to be
accessed. Locked transactions to the PCI Express memory mapped configuration address space are not
supported. All changes made using either access mechanism are equivalent.
The enhanced PCI Express configuration access mechanism utilizes a flat memory-mapped address
space to access device configuration registers. This address space is reported by the system firmware to
the operating system. PCIEXBAR defines the base address for the 256-MB block of addresses below
the top of addressable memory (currently 4 GB) for the configuration space associated with all devices
and functions that are potentially a part of the PCI Express root complex hierarchy. The PCI Express
Configuration Transaction Header includes an additional 4 bits (Extended Register Address[3:0])
between the Function Number and Register Address fields to provide indexing into the 4 KB of
configuration space allocated to each potential device. For PCI Compatible Configuration Requests, the
Extended Register Address field must be all 0’s.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
69
GMCH Register Description
R
Figure 3-4. Memory Map to PCI Express Device Configuration Space
0xFFFFFFF
0xFFF
0x7FFF
0xFFFFF
Bus 255
Device 31
Function 7
PCI Express
Extended
Conf iguration
Space
0xFF
0xFFFF
0x1FFFFF
0x1FFF
Device 1
Bus 1
0x7FFF
0xFFFFF
Function 1
Device 0
Bus 0
0x3F
0xFFF
Function 0
0
PCI Compatible
Conf iguration
Space
PCI Compatible
Conf iguration
Space Header
Located by
PCI Express Base
Address
Just the same as with PCI devices, each device is selected based on decoded address information that is
provided as a part of the address portion of Configuration Request packets. A PCI Express device will
decode all address information fields (bus, device, function and extended address numbers) to provide
access to the correct register.
To access this space (steps 1, 2, 3 are done only once by BIOS),
1. Use the PCI compatible configuration mechanism to enable the PCI Express enhanced
configuration mechanism by writing 1 to bit 31 of the DEVEN register.
2. Use the PCI compatible configuration mechanism to write an appropriate PCI Express base
address into the PCIEXBAR register.
3. Calculate the host address of the register you wish to set using (PCI Express base + (bus number *
1 MB) + (device number * 32 kB) + (function number * 4 kB) + (1 B * offset within the function)
= host address).
4. Use a memory write or memory read cycle to the calculated host address to write to or read from
that register.
31
28 27
Base
20 19
Bus
15 14
Device
12 11
Func.
Extended
8
7
2
Register Number
1
0
x
x
PCI Express Configuration Writes:
• Internally the host interface unit will translate writes to PCI Express extended configuration space
to configurations on the backbone.
• Writes to extended space are posted on the FSB, but non-posted on the PEG or DMI pins (i.e.,
translated to config writes).
See the PCI Express specification for more information on both the PCI 2.3 compatible and PCI
Express enhanced configuration mechanism and transaction rules.
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Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
GMCH Register Description
R
3.1.7
GMCH Configuration Cycle Flow Chart
Figure 3-5. GMCH Configuration Cycle Flow Chart
DW I/O Write to
CONFIG_ADDRESS
with bit 31 = 1
I/O Read/Write to
CONFIG_DATA
Bus# = 0
Yes
No
GMCH Generates
Type 1 Access
to PCI Express
Yes
Bus# > SEC BUS
Bus# SUB BUS
in GMCH Dev 1
Device# = 0 &
Function# = 0
No
Yes
Bus# =
SECONDARYBUS
in GMCH Dev 1
GMCH Claims
Yes
GMCH Claims
No
Device# = 1 &
Dev#1 Enabled &
Function # = 0
No
GMCH Generates
DMI Type 1
Configuration Cycle
Yes
No
Device# = 2 &
Dev#2 Enabled &
Function# = 0 or 1
Yes
GMCH Claims
No
Device# = 0
Yes
GMCH Generates
Type 0 Access
to PCI Express
No
GMCH Generates
Master Abort
GMCH Generates
DMI Type 0
Configuration Cycle
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
71
GMCH Register Description
R
3.2
I/O Mapped Registers
The GMCH contains two registers that reside in the CPU I/O address space − the Configuration
Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The
Configuration Address Register enables/disables the configuration space and determines what portion
of configuration space is visible through the Configuration Data window.
3.2.1
CONFIG_ADDRESS—Configuration Address Register
I/O Address:
Size:
0CF8h Accessed as a DW
32 bits
CONFIG_ADDRESS is a 32 bit register that can be accessed only as a DW. A Byte or Word reference
will "pass through" the Configuration Address Register and DMI onto the PCI_A bus as an I/O cycle.
The CONFIG_ADDRESS register contains the Bus Number, Device Number, Function Number, and
Register Number for which a subsequent configuration access is intended.
Bit
31
30:24
Access
&
Default
R/W
Description
0b
Configuration Enable (CFGE) - When this bit is set to 1, accesses to PCI configuration
space are enabled. If this bit is reset to 0, accesses to PCI configuration space are
disabled.
RO
Reserved
00h
23:16
R/W
00h
Bus Number - If the Bus Number is programmed to 00h the target of the Configuration
Cycle is a PCI Bus #0 agent. If this is the case and the GMCH is not the target (i.e. the
device number is >= 3 and not equal to 7), then a DMI Type 0 Configuration Cycle is
generated.
If the Bus Number is non-zero, and does not fall within the ranges enumerated by device
#1’s SECONDARY BUS NUMBER or SUBORDINATE BUS NUMBER Register, then a
DMI Type 1 Configuration Cycle is generated.
If the Bus Number is non-zero and matches the value programmed into the SECONDARY
BUS NUMBER Register of device #1, a Type 0 PCI configuration cycle will be generated
on PCI Express Graphics.
If the Bus Number is non-zero, greater than the value in the SECONDARY BUS NUMBER
register of device #1 and less than or equal to the value programmed into the
SUBORDINATE BUS NUMBER Register of device #1 a Type 1 PCI configuration cycle
will be generated on PCI Express Graphics.
This field is mapped to byte 8 [7:0] of the request header format during PCI Express
Configuration cycles and A[23:16] during the DMI Type 1 configuration cycles.
15:11
R/W
00h
Device Number - This field selects one agent on the PCI bus selected by the Bus
Number. When the Bus Number field is “00” the GMCH decodes the Device Number field.
The GMCH is always Device Number 0 for the Host bridge entity, Device Number 1 for
the Host-PCI Express entity. Therefore, when the Bus Number =0 and the Device Number
equals 0,1, 2 or 7 the internal GMCH devices are selected.
This field is mapped to byte 6 [7:3] of the request header format during PCI Express and
DMI Configuration cycles.
10:8
R/W
Function Number
000b
This field allows the configuration registers of a particular function in a multi-function
device to be accessed. The GMCH ignores configuration cycles to it’s internal Devices if
the function number is not equal to 0 or 1.
This field is mapped to byte 6 [2:0] of the request header format during PCI Express and
DMI Configuration cycles.
72
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
GMCH Register Description
R
Bit
Access
&
Default
7:2
Description
R/W
Register Number
00h
This field selects one register within a particular Bus, Device, and Function as specified
by the other fields in the Configuration Address Register.
This field is mapped to byte 7 [7:2] of the request header format for during PCI Express
and DMI Configuration cycles.
1:0
RO
Reserved
00b
3.2.2
CONFIG_DATA—Configuration Data Register
I/O Address:
Size:
0CFCh
32 bits
CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of configuration
space that is referenced by CONFIG_DATA is determined by the contents of CONFIG_ADDRESS.
Bit
31:0
Access &
Default
R/W
0000 0000 h
Description
Configuration Data Window (CDW)
If bit 31 of CONFIG_ADDRESS is 1, any I/O access to the CONFIG_DATA register will
produce a configuration transaction using the contents of CONFIG_ADDRESS to
determine the bus, device, function, and offset of the register to be accessed.
§
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
73
GMCH Register Description
R
74
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4
Host Bridge Device 0 Configuration Registers (D0:F0)
Warning: Address locations that are not listed are considered Reserved registers locations. Reads to Reserved
registers may return non-zero values. Writes to reserved locations may cause system failures.
4.1
Host Bridge Device 0 Configuration Register Space
All registers that are defined in the PCI 2.3 specification, but are not necessary or implemented in this
component are simply not included in this document. The reserved/unimplemented space in the PCI
configuration header space is not documented as such in this summary.
Address
Offset
Register
Symbol
Register Name
Default Value
Access
00-01h
VID
Vendor Identification
8086h
RO
02-03h
DID
Device Identification
2590h
RO
04-05h
PCICMD
PCI Command
0006h
RO, R/W
06-07h
PCISTS
PCI Status
0090h
RO, R/WC
08h
RID
Revision Identification
00h See register
description
RO
09-0Bh
CC
Class Code
060000h
RO
0Ch
Reserved
0Dh
MLT
Master Latency Timer
00h
RO
0Eh
HDR
Header Type
00h
RO
0F-2Bh
Reserved
2C-2Dh
SVID
Subsystem Vendor Identification
0000h
R/WO
2E-2Fh
SID
Subsystem Identification
0000h
R/WO
E0h
RO
EP Root Complex MMIO Base
Address
00000000h
RO, R/W
30-33h
34-34h
Reserved
CAPPTR
35-3Fh
Capabilities Pointer
Reserved
40-43h
EPBAR
44-47h
MCHBAR
MCH MMIO Base Address
00000000h
RO, R/W
48-4Bh
PCIEXBAR
PCI Express MMIO Base Address
E0000000h
RO, R/W
4C-4Fh
DMIBAR
DMI Root Complex MMIO Base
Address
00000000h
RO, R/W
Graphics Control Register
82915GM/GML/GMS only
0030h
RO, R/W
Device Enable
00000019h
RO, R/W, R/W/L
50-51h
Reserved
52-53h
GGC
54-57h
DEVEN
58-8Fh
Reserved
90h
PAM0
Programmable Attribute Map 0
00h
RO, R/W
91h
PAM1
Programmable Attribute Map 1
00h
RO, R/W
92h
PAM2
Programmable Attribute Map 2
00h
RO, R/W
93h
PAM3
Programmable Attribute Map 3
00h
RO, R/W
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
75
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
94h
PAM4
Programmable Attribute Map 4
00h
RO, R/W
95h
PAM5
Programmable Attribute Map 5
00h
RO, R/W
96h
PAM6
Programmable Attribute Map 6
00h
RO, R/W
97h
LAC
Legacy Access Control
00h
RO, R/W
98-9Bh
Reserved
9Ch
TOLUD
Top of Low Used Dram
08h
RO, R/W
9Dh
SMRAM
System Management RAM Control
02h
RO, R/W/L
9Eh
ESMRAMC
Extended System Management RAM
Control
38h
RO, R/W, R/WC,
R/W/L
C8-C9h
ERRSTS
Error Status
0000h
RO, R/W/C
CA-CBh
ERRCMD
Error Command
0000h
RO, R/W
xxxxxxxxxxxx90
009h
RO
9F-C7h
Reserved
CC-DFh
E0-E8h
Reserved
CAPID0
E9-FFh
4.1.1
Capability Identifier
Reserved
VID—Vendor Identification
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
00h
8086h
RO
16 bits
This register combined with the Device Identification register uniquely identifies any PCI device.
Bit
15:0
Access
RO
8086h
4.1.2
Description
Vendor Identification Number (VID):
PCI standard identification for Intel.
DID—Device Identification
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
02h
2590h
RO
16 bits
This register combined with the Vendor Identification register uniquely identifies any PCI device.
Bit
Access
& Default
15:0
RO
2590 h
4.1.3
Device Identification Number (DID):
Identifier assigned to the GMCH core/primary PCI device.
PCICMD—PCI Command
PCI Device:
Address Offset:
Default Value:
76
Description
0
04h
0006h
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
Access:
Size:
RO, R/W
16 bits
GMCH Device #0 does not physically reside on PCI_A many of the bits are not implemented.
Bit
15:10
Access
&
Default
RO
Description
Reserved
00h
9
8
RO
Fast Back-to-Back Enable (FB2B):
0b
This bit controls whether or not the master can do fast back-to-back write. Since device
0 is strictly a target this bit is not implemented and is hardwired to 0. Writes to this bit
position have no affect.
R/W
SERR Enable (SERRE):
0b
This bit is a global enable bit for Device 0 SERR messaging. The GMCH does not
have an SERR signal. The GMCH communicates the SERR condition by sending an
SERR message over GMCH ICH Serial Interface (DMI) to the ICH.
If this bit is set to a 1, the GMCH is enabled to generate SERR messages over DMI for
specific Device 0 error conditions that are individually enabled in the ERRCMD
register. The error status is reported in the ERRSTS and PCISTS registers.
If SERRE is clear, then the SERR message is not generated by the GMCH for Device
0. Note that this bit only controls SERR messaging for the Device 0. Device 1 has its
own SERRE bits to control error reporting for error conditions occurring on their
respective devices. The control bits are used in a logical OR manner to enable the
SERR DMI message mechanism.
7
6
5
4
3
2
1
0
4.1.4
RO
Address/Data Stepping Enable (ADSTEP):
0b
Address/data stepping is not implemented in the GMCH, and this bit is hardwired to 0.
Writes to this bit position have no effect.
RO
Parity Error Enable (PERRE):
0b
PERRB is not implemented by the GMCH and this bit is hardwired to 0. Writes to this
bit position have no effect.
RO
VGA Palette Snoop Enable (VGASNOOP):
0b
The GMCH does not implement this bit and it is hardwired to a 0. Writes to this bit
position have no effect.
RO
Memory Write and Invalidate Enable (MWIE):
0b
The GMCH will never issue memory write and invalidate commands. This bit is
therefore hardwired to 0. Writes to this bit position will have no effect.
RO
Special Cycle Enable (SCE):
0b
The GMCH does not implement this bit and it is hardwired to a 0. Writes to this bit
position have no effect.
RO
Bus Master Enable (BME):
1b
The GMCH is always enabled as a master on DMI. This bit is hardwired to a 1. Writes
to this bit position have no effect.
RO
Memory Access Enable (MAE):
1b
The GMCH always allows access to main memory. This bit is not implemented and is
hardwired to 1. Writes to this bit position have no effect.
RO
I/O Access Enable (IOAE):
0b
This bit is not implemented in the GMCH and is hardwired to a 0. Writes to this bit
position have no effect.
PCISTS—PCI Status
PCI Device:
0
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
77
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
Address Offset:
Default Value:
Access:
Size:
06h
0090h
RO, R/WC
16 bits
This status register reports the occurrence of error events on Device 0’s PCI interface. Since the
GMCH Device 0 does not physically reside on PCI_A many of the bits are not implemented.
Bit
Access &
Default
15
RO
Detected Parity Error (DPE):
0b
The GMCH does not implement this bit and it is hardwired to a 0. Writes to this bit
position have no effect.
14
R/W/C
0b
13
R/W/C
0b
12
R/W/C
11
10:9
8
7
6:5
Description
Signaled System Error (SSE):
This bit is set to 1 when the GMCH Device 0 generates an SERR message over DMI for
any enabled Device 0 error condition. Device 0 error conditions are enabled in the
PCICMD and ERRCMD registers. Device 0 error flags are read/reset from the PCISTS or
ERRSTS registers. Software clears this bit by writing a 1 to it.
Received Unsupported Request (RURS):
This bit is set when the MCH generates a DMI request that receives a Unsupported
request completion. Software clears this bit by writing a 1 to it.
Received Completion Abort Status (RCAS):
0b
This bit is set when the MCH generates a DMI request that receives a completion abort.
Software clears this bit by writing a 1 to it. If ERRCMD bit 6 is set, an SERR special cycle
is generated on the DMI.
RO
Signaled Target Abort Status (STAS):
0b
The GMCH will not generate a Target Abort DMI completion packet or Special Cycle.
This bit is not implemented in the GMCH and is hardwired to a 0. Writes to this bit
position have no effect.
RO
DEVSEL Timing (DEVT):
00 b
These bits are hardwired to "00". Writes to these bit positions have no affect. Device 0
does not physically connect to PCI_A. These bits are set to "00" (fast decode) so that
optimum DEVSEL timing for PCI_A is not limited by the GMCH.
RO
Master Data Parity Error Detected (DPD):
0b
PERR signaling and messaging are not implemented by the GMCH therefore this bit is
hardwired to 0. Writes to this bit position have no effect.
RO
Fast Back-to-Back (FB2B):
1b
This bit is hardwired to 1. Writes to these bit positions have no effect. Device 0 does not
physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-back capability)
so that the optimum setting for PCI_A is not limited by the GMCH.
RO
Reserved
00 b
4
3:0
RO
Capability List (CLIST):
1b
This bit is hardwired to 1 to indicate to the configuration software that this device/function
implements a list of new capabilities. A list of new capabilities is accessed via register
CAPPTR at configuration address offset 34h. Register CAPPTR contains an offset
pointing to the start address within configuration space of this device where the
Capability standard register resides.
RO
Reserved
0h
4.1.5
RID—Revision Identification
PCI Device:
78
0
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
Address Offset:
Default Value:
Access:
Size:
08h
xxh
RO
8 bits
This register contains the revision number of the GMCH Device #0.
Bit
7:0
4.1.6
Access &
Default
Description
RO
Revision Identification Number (RID):
00 h
This is an 8-bit value that indicates the revision identification number for the
GMCH Device 0..
CC—Class Code
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
09h
060000h
RO
24 bits
This register identifies the basic function of the device, a more specific sub-class, and a registerspecific programming interface.
Bit
23:16
15:8
7:0
Access &
Default
Description
RO
Base Class Code (BCC) –
06 h
This is an 8-bit value that indicates the base class code for the GMCH. This code has the
value 06h, indicating a Bridge device.
RO
Sub-Class Code (SUBCC) –
00 h
This is an 8-bit value that indicates the category of Bridge into which the GMCH falls.
The code is 00h indicating a Host Bridge.
RO
Programming Interface (PI) –
00 h
This is an 8-bit value that indicates the programming interface of this device. This value
does not specify a particular register set layout and provides no practical use for this
device.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
79
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.7
MLT—Master Latency Timer
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
0Dh
00h
RO
8 bits
Device #0 in the GMCH is not a PCI master. Therefore this register is not implemented.
Bit
7:0
Access &
Default
RO
Description
Reserved.
00 h
4.1.8
HDR—Header Type
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
0Eh
00h
RO
8 bits
This register identifies the header layout of the configuration space. No physical register exists at this
location.
Bit
7:0
4.1.9
Access &
Default
Description
RO
PCI Header (HDR):
00 h
This field always returns 0 to indicate that the GMCH is a single function device with
standard header layout. Reads and writes to this location have no effect.
SVID—Subsystem Vendor Identification
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
2Ch
0000h
R/WO
16 bits
This value is used to identify the vendor of the subsystem.
Bit
15:0
80
Access &
Default
Description
R/WO
Subsystem Vendor ID (SUBVID):
0000 h
This field should be programmed during boot-up to indicate the vendor of the system
board. After it has been written once, it becomes read only.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.10
SID—Subsystem Identification
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
2Eh
0000h
R/WO
16 bits
This value is used to identify a particular subsystem.
Bit
15:0
4.1.11
Access &
Default
Description
R/WO
Subsystem ID (SUBID):
0000 h
This field should be programmed during BIOS initialization. After it has been written
once, it becomes read only.
CAPPTR—Capabilities Pointer
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
34h
E0h
RO
8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device capability in the
capability list.
Bit
7:0
Access &
Default
Description
RO
Pointer to the offset of the first capability ID register block:
E0 h
In this case the first capability is the product-specific Capability Identifier
(CAPID0).
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
81
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.12
EPBAR—Egress Port Base Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
40h
00000000h
RO, R/W
32 bits
This is the base address for the Egress Port Root Complex MMIO configuration space. This window
of addresses contains the Egress Port Root Complex Register set for the PCI Express Hierarchy
associated with the GMCH. There is no physical memory within this 4-kB window that can be
addressed. The
4 kB reserved by this register does not alias to any PCI2.3 compliant memory
mapped space.
On reset, this register is disabled and must be enabled by writing a 1 to RCBAREN [Dev 0, offset 54h,
bit 27]
Bit
31:12
Access &
Default
R/W
0000 0 h
Description
Egress Port RCRB Base Address –
This field corresponds to bits 31 to 12 of the base address Egress port RCRB
MMIO configuration space.
BIOS will program this register resulting in a base address for a 4KB block of
contiguous memory address space. This register ensures that a naturally
aligned 4KB space is allocated within total addressable memory space of 4GB.
System Software uses this base address to program the Egress Port RCRB and
associated registers.
11:0
82
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.13
MCHBAR—GMCH Register Range Base Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
44h
00000000h
RO, R/W
32 bits
This is the base address for the GMCH MMIO Configuration space. There is no physical memory
within this 16-kB window that can be addressed. The 16KB reserved by this register does not alias to
any PCI2.3 compliant memory mapped space.
On reset, this register is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0, offset
54h, bit 28].
Bit
31:14
Access &
Default
Description
R/W
MCHBAR Base Address –
0000 h
This field corresponds to bits 31 to 14 of the base address MCHBAR
configuration space.
BIOS will program this register resulting in a base address for a 16-kB block of
contiguous memory address space. This register ensures that a naturally
aligned 16KB space is allocated within total addressable memory space of 4 GB.
System Software uses this base address to program the GMCH register set.
13:0
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
83
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.14
PCIEXBAR—PCI Express Register Range Base Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
48h
E0000000h
RO, R/W
32 bits
This is the base address for the PCI Express configuration space. This window of addresses contains
the 4 kB of configuration space for each PCI Express device that can potentially be part of the PCI
Express Hierarchy associated with the GMCH. There is no actual physical memory within this 256MB window that can be addressed. Each PCI Express Hierarchies requires a PCI Express BASE
register. The GMCH supports one PCI Express hierarchy.
The 256 MB reserved by this register does not alias to any PCI2.3 compliant memory mapped space.
For example, MCHBAR reserves a 16-KB space and reserves a 4-KB space both outside of
PCIEXBAR space. They cannot be overlaid on the space reserved by PCIEXBAR for Device 0.
On reset, this register is disabled and must be enabled by writing a 1 to PCIEXBAREN [Dev 0, offset
54h, bit 31]
If the PCI Express Base address [bits 31:28] were set to Fh, an overlap with the High BIOS area, APIC
ranges would result. Software must guarantee that these ranges do not overlap. The PCI Express Base
Address cannot be less than the maximum address written to the TOP of physical memory register
(TOLUD).
Bit
31:28
Access &
Default
R/W
1110 b
Description
PCI Express Base Address –
This field corresponds to bits 31 to 28 of the base address for PCI Express
enhanced configuration space.
BIOS will program this register resulting in a base address for a 256 MB block of
contiguous memory address space. Having control of those particular 4 bits
insures that this base address will be on a 256-MB boundary, above the lowest
256 MB and still within total addressable memory space, currently 4 GB.
Configuration software will read this register to determine where the 256 MB
range of addresses resides for this particular host bridge.
The address used to access the PCI Express configuration space for a specific
device can be determined as follows:
PCI Express Base Address + Bus Number * 1MB + Device Number * 32 kB +
Function Number * 4 kB
The address used to access the PCI Express configuration space for Device 1 in
this component would be as follows.
PCI Express Base Address + 0 * 1 MB + 1 * 32 kB + 0 * 4 kB = PCI Express
Base Address + 32 kB.
NOTE: This address is at the beginning of the 4 kB space that contains both the
PCI compatible configuration space and the PCI Express extended
configuration space.
27:0
84
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.15
DMIBAR—DMI Root Complex Register Range Base Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
4Ch
00000000h
RO, R/W
32 bits
This is the base address for the DMI Root Complex MMIO configuration space. This window of
addresses contains the DMI Root Complex Register set for the PCI Express Hierarchy associated with
the GMCH. There is no physical memory within this 4KB window that can be addressed. The 4 kB
reserved by this register does not alias to any PCI2.3 compliant memory mapped space.
On reset, this register is disabled and must be enabled by writing a 1 to RCBAREN [Dev 0, offset 54h,
and bit 29].
Bit
31:12
Access &
Default
Description
R/W
DMI root complex MMIO register set Base Address –
0000 0 h
This field corresponds to bits 31 to 12 of the base address DMI RCRB MMIO
configuration space.
BIOS will program this register resulting in a base address for a 4KB block of
contiguous memory address space. This register ensures that a naturally aligned
4KB space is allocated within total addressable memory space of 4GB.
System Software uses this base address to program the DMI RCRB registers.
11:0
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
85
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.16
GGC-GMCH Graphics Control Register (Device 0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
Access & Default
15:7
6:4
0
52-53h
0030h
RO, R/W
16 bits
Descriptions
Reserved
R/W
Graphics Mode Select (GMS).
011 b
This field is used to select the amount of Main Memory that is preallocated to support the Internal Graphics device in VGA (non-linear)
and Native (linear) modes.
Stolen Memory Bases is located between (TOLUD – SMSize) to
TOUD.
000 =
No memory pre-allocated. Device 2 (IGD) does not claim
VGA cycles (Mem and IO), and the Sub-Class Code field within
Device 2 function 0 Class Code register is 80.
001 =
DVMT (UMA) mode, 1 MB of memory pre-allocated for
frame buffer.
010 =
Reserved
011 =
DVMT (UMA) mode, 8 MB of memory pre-allocated for
frame buffer.
100 : 111 =
Reserved
Note: This register is locked and becomes Read Only when the
D_LCK bit in the SMRAM register is set. If IGD is disabled, this field
should be set to 000b
3:2
1
Reserved
R/W/L
IGD VGA Disable (IVD).
0b
0: Enable (Default). Device 2 (IGD) claims VGA memory and IO
cycles, the Sub-Class Code within Device 2 Class Code register is 00.
1: Disable. Device 2 (IGD) does not claim VGA cycles (Mem and IO),
and the Sub-Class Code field within Device 2 function 0 Class Code
register is 80.
0
86
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.17
DEVEN—Device Enable
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
54h
00000019h
RO, R/W, R/W/L
32 bits
This register allows for enabling/disabling of PCI devices and functions that are within the GMCH.
This table describes the behavior of all combinations of transactions to devices controlled by this
register.
Bit
31
30
29
Access &
Default
R/W
0b
R/W/L
0b
28
R/W/L
0b
27
R/W/L
0b
26:5
4
3
2
1
0
R/W/L
1b
R/W/L
1b
R/W/L
1b
RO
1b
Description
82915GM / 82915GME / 82915PM GMCH:
PCIEXBAR Enable (PCIEXBAREN):
0: The PCIEXBAR register is disabled. Memory read and write transactions proceed
as if there were no PCIEXBAR register.
1: The PCIEXBAR register is enabled. Memory read and write transactions whose
address bits 31:28 match PCIEXBAR 31:28 will be translated to configuration reads and
writes within the GMCH.
82910GML / 82910GMLE / 82915GMS: Reserved
Reserved
DMIBAR Enable (DMIBAREN):
0: DMIBAR is disabled and does not claim any memory.
1: DMIBAR memory mapped accesses are claimed and decoded appropriately.
MCHBAR Enable (MCHBAREN):
0: MCHBAR is disabled and does not claim any memory.
1: MCHBAR memory mapped accesses are claimed and decoded appropriately.
EPBAR Enable (EPBAREN):
0: EPBAR is disabled and does not claim any memory.
1: EPBAR memory mapped accesses are claimed and decoded appropriately.
Reserved.
82915GM / 82915GME / 82910GML / 82910GMLE / 82915GMS :
Internal Graphics Engine Function 1 (D2F1EN):
0: Bus 0 Device 2 Function 1 is disabled and hidden
1: Bus 0 Device 2 Function 1 is enabled and visible
NOTE: If Device 2 Function 0 is disabled and hidden, then Device 2 Function 1 is also
disabled and hidden independent of the state of this bit.
82915PM:
Reserved.
82915GM / 82915GME / 82910GML / 82910GMLE / 82915GMS :
Internal Graphics Engine Function 0 (D2F0EN):
0: Bus 0 Device 2 Function 0 is disabled and hidden
1: Bus 0 Device 2 Function 0 is enabled and visible
NOTE: If this GMCH does not have internal graphics capability (CAPID0[38] = 1) then
Device 2 Function 0 is disabled and hidden independent of the state of this bit.
82915PM:
Reserved.
Reserved
82915GM / 82915GME / 82915PM:
PCI Express Graphics Attach (D1EN):
0: Bus 0 Device 1 Function 0 is disabled and hidden
1: Bus 0 Device 1 Function 0 is enabled and visible
The SDVO Presence HW strap determines default value. Device 1 is Disabled on Reset
when the SDVO Presence strap is sampled high, and is enabled otherwise.
82915GMS / 82910GML / 82910GMLE:
Reserved.
Host Bridge: Bus 0 Device 0 Function 0 may not be disabled and is therefore hardwired
to 1.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
87
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.18
PAM0—Programmable Attribute Map 0
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
90h
00h
RO, R/W
8 bits
This register controls the read, write, and shadowing attributes of the BIOS area from 0F0000h0FFFFFh
The GMCH allows programmable memory attributes on 13 Legacy memory segments of various sizes
in the 640 kB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers are used to
support these features. Cacheability of these areas is controlled via the MTRR registers in the
processor. Two bits are used to specify memory attributes for each memory segment. These bits apply
to both host accesses and PCI initiator accesses to the PAM areas. These attributes are:
RE - Read Enable. When RE = 1, the CPU read accesses to the corresponding memory segment are
claimed by the GMCH and directed to main memory. Conversely, when RE = 0, the host read accesses
are directed to PCI_A.
WE - Write Enable. When WE = 1, the host write accesses to the corresponding memory segment are
claimed by the GMCH and directed to main memory. Conversely, when WE = 0, the host write
accesses are directed to PCI_A.
The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or
disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only.
Each PAM Register controls two regions, typically 16 kB in size.
Bit
Access &
Default
7:6
5:4
Description
Reserved.
R/W
0F0000-0FFFFF Attribute (HIENABLE):
00 b
This field controls the steering of read and write cycles that address the BIOS area from
0F0000 to 0FFFFF.
00 = DRAM Disabled: All accesses are directed to DMI.
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
3:0
Reserved
Warning: The GMCH may hang if a PCI Express Graphics Attach or DMI originated access to Read Disabled or
Write Disabled PAM segments occur (due to a possible IWB to non-DRAM). For these reasons the
following critical restriction is placed on the programming of the PAM regions:
At the time that a DMI or PCI Express Graphics Attach accesses to the PAM region may occur, the
targeted PAM segment must be programmed to be both readable and writeable.
88
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.19
PAM1—Programmable Attribute Map 1
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
91h
00h
RO, R/W
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0C0000h0C7FFFh.
Bit
Access &
Default
7:6
5:4
Description
Reserved.
R/W
0C4000-0C7FFF Attribute (HIENABLE):
00 b
This field controls the steering of read and write cycles that address the BIOS area from
0C4000 to 0C7FFF.
00:DRAM Disabled:
Accesses are directed to DMI.
01:Read Only:
All reads are serviced by DRAM. All writes are forwarded to DMI.
10:Write Only:
All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
3:2
1:0
Reserved.
R/W
0C0000-0C3FFF Attribute (LOENABLE):
00 b
This field controls the steering of read and write cycles that address the BIOS area from
0C0000 to 0C3FFF.
00:DRAM Disabled:
Accesses are directed to DMI.
01:Read Only:
DMI.
All reads are serviced by DRAM. All writes are forwarded to
10:Write Only:
All writes are sent to DRAM. Reads are serviced by DMI.
11:Normal DRAM Operation: All reads and writes are serviced by DRAM.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
89
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.20
PAM2—Programmable Attribute Map 2
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
92h
00h
RO, R/W
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0C8000h0CFFFFh.
Bit
Access &
Default
Reserved.
7:6
5:4
Description
R/W
00 b
0CC000-0CCFFF Attribute (HIENABLE):
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
0C8000-0CBFFF Attribute (LOENABLE):
00 b
This field controls the steering of read and write cycles that address the BIOS area from
0C8000 to 0CBFFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
90
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.21
PAM3—Programmable Attribute Map 3
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
93h
00h
RO, R/W
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0D0000h0D7FFFh.
Bit
Access &
Default
Reserved
7:6
5:4
Description
R/W
0D4000-0D7FFF Attribute (HIENABLE):
00 b
This field controls the steering of read and write cycles that address the BIOS area
from 0D4000 to 0D7FFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
0D0000-0D3FFF Attribute (LOENABLE):
00 b
This field controls the steering of read and write cycles that address the BIOS area
from 0D0000 to 0D3FFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
91
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.22
PAM4—Programmable Attribute Map 4
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
94h
00h
RO, R/W
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0D8000h0DFFFFh.
Bit
Access &
Default
7:6
5:4
Description
Reserved
R/W
0DC000-0DFFFF Attribute (HIENABLE):
00 b
This field controls the steering of read and write cycles that address the BIOS area from
0DC000 to 0DFFFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
3:2
1:0
Reserved
R/W
0D8000-0DBFFF Attribute (LOENABLE):
00 b
This field controls the steering of read and write cycles that address the BIOS area from
0D8000 to 0DBFFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
92
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.23
PAM5—Programmable Attribute Map 5
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
95h
00h
RO, R/W
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0E0000h0E7FFFh.
Bit
Access &
Default
Reserved
7:6
5:4
Description
R/W
0E4000-0E7FFF Attribute (HIENABLE):
00 b
This field controls the steering of read and write cycles that address the BIOS area from
0E4000 to 0E7FFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
Reserved
3:2
1:0
R/W
0E0000-0E3FFF Attribute (LOENABLE):
00 b
This field controls the steering of read and write cycles that address the BIOS area from
0E0000 to 0E3FFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
93
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.24
PAM6—Programmable Attribute Map 6
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
96h
00h
RO, R/W
8 bits
This register controls the read, write, and shadowing attributes of the BIOS areas from 0E8000h0EFFFFh.
Bit
Access &
Default
7:6
5:4
Description
Reserved
R/W
0EC000-0EFFFF Attribute (HIENABLE):
00 b
This field controls the steering of read and write cycles that address the BIOS area from
0E4000 to 0E7FFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
3:2
1:0
Reserved
R/W
0E8000-0EBFFF Attribute (LOENABLE):
00 b
This field controls the steering of read and write cycles that address the BIOS area from
0E0000 to 0E3FFF.
00: DRAM Disabled: Accesses are directed to DMI.
01: Read Only: All reads are serviced by DRAM. All writes are forwarded to DMI.
10: Write Only: All writes are sent to DRAM. Reads are serviced by DMI.
11: Normal DRAM Operation: All reads and writes are serviced by DRAM.
94
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.25
LAC—Legacy Access Control
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
97h
00h
RO, R/W
8 bits
This 8-bit register controls a fixed DRAM hole from 15-16 MB.
Bit
Access
&
Default
Description
7
R/W
Hole Enable (HEN):
0b
This field enables a memory hole in DRAM space. The DRAM that lies "behind" this
space is not remapped.
0: No memory hole.
1: Memory hole from 15 MB to 16 MB.
Reserved.
6:1
0
R/W
0b
MDA Present (MDAP):
This bit works with the VGA Enable bits in the BCTRL register of device 1 to control the
routing of CPU initiated transactions targeting MDA compatible I/O and memory address
ranges.
This bit should not be set if device 1's VGA Enable bit is not set. If device 1's VGA enable
bit is not set, then accesses to IO address range x3BCh-x3BFh are forwarded to DMI.
If the VGA enable bit is set and MDA is not present, then accesses to IO address range
x3BCh-x3BFh are forwarded to PCI Express Graphics if the address is within the
corresponding IOBASE and IOLIMIT, otherwise they are forwarded to DMI.
MDA resources are defined as the following:
Memory:
0B0000h - 0B7FFFh
I/O:
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not used in decode)
Any I/O reference that includes the I/O locations listed above, or their aliases, will be
forwarded to DMI even if the reference includes I/O locations not listed above.
The following table shows the behavior for all combinations of MDA and VGA:
VGAEN
0
MDAP
0
Description
All References to MDA and VGA space are routed to
HI
0
1
Illegal combination
1
0
All VGA and MDA references are routed to PCI
Express Graphics Attach.
1
1
All VGA references are routed to PCI Express
Graphics Attach. MDA references are routed to HI
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
95
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.26
TOLUD—Top of Low Used DRAM Register
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
9Ch
08h
RO, R/W
8 bits
This 8-bit register defines the Top of Usable DRAM (TOLUD). Graphics Stolen Memory and TSEG
are within dram space defined under TOLUD. From the top of low used DRAM, GMCH claims 1 to 64
MB of dram for internal graphics if enabled and 1, 2 or 8 MB of DRAM for TSEG if enabled.
Bit
Access
&
Default
7:3
R/W
01 h
Description
Top of Low Usable Dram (TOUD)-R/W
This register contains bits 31 to 27 of an address one byte above the maximum
DRAM memory that is usable by the operating system. Address bits 31 to 27
programmed to a “01h” implies a minimum memory size of 128 MB.
Configuration software must set this value to the smaller of the following two
choices:
- Maximum amount of memory in the system plus one byte
- Minimum address allocated for PCI memory
Address bits 26:0 are assumed to be 000_0000h for the purposes of address
comparison. The Host interface positively decodes an address towards dram if the
incoming address is less than that value programmed in this register.
This register must not be set to 0000 0 b.
Note that the Top of Usable Dram is the lowest address above both Graphics Stolen
memory and TSEG. The host interface determines the base of Graphics Stolen
memory by subtracting the graphics stolen memory size from TOLUD and further
decrements by TSEG size to determine base of TSEG.
2:0
Reserved.
Programming Example (for 82915GM, 82915GMS, 82915GME, 82910GML, 82910GMLE
GMCH only):
• C1DRB7 is set to 4 GB
• TSEG is enabled and TSEG size is set to 1 MB
• Internal Graphics is enabled and Graphics Mode Select is set to 32 MB
• BIOS knows the OS requires 1G of PCI space
The BIOS also knows the range from FEC0_0000h to FFFF_FFFFh is not usable by the system. This
20-MB range at the very top of addressable memory space is lost to APIC.
According to the above equation, TOLUD is originally calculated to: 4 GB = 1_0000_0000h
The system memory requirements are:
4 GB (max addressable space) – 1 GB (PCI space) - 20 MB (lost memory) = 3 GB - 128 MB
(minimum granularity) = B800_0000h
Since B800_0000h (PCI and other system requirements) is less than 1_0000_0000h; TOLUD should
be programmed to B8h.
96
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.27
SMRAM—System Management RAM Control
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
9Dh
02h
RO, R/W/L
8 bits
The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are
treated. The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the
OPEN bit must be reset before the LOCK bit is set.
Bit
Access &
Default
7
6
Description
Reserved.
R/W/L
0b
SMM Space Open (D_OPEN):
(When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made visible even
when SMM decode is not active.
This is intended to help BIOS initialize SMM space. Software should ensure that
D_OPEN=1 and D_CLS=1 are not set at the same time.
5
R/W/L
0b
SMM Space Closed (D_CLS):
When D_CLS = 1 SMM space DRAM is not accessible to data references, even if
SMM decode is active. Code references may still access SMM space DRAM.
This will allow SMM software to reference through SMM space to update the
display even when SMM is mapped over the VGA range. Software should ensure
that D_OPEN=1 and D_CLS=1 are not set at the same time. Note that the D_CLS
bit only applies to Compatible SMM space.
4
3
2:0
R/W/L
SMM Space Locked (D_LCK):
0b
When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK, D_OPEN,
C_BASE_SEG, H_SMRAM_EN, TSEG_SZ and TSEG_EN become read only.
D_LCK can be set to 1 via a normal configuration space write but can only be
cleared by a Full Reset. The combination of D_LCK and D_OPEN provide
convenience with security. The BIOS can use the D_OPEN function to initialize
SMM space and then use D_LCK to "lock down" SMM space in the future so that
no application software (or BIOS itself) can violate the integrity of SMM space,
even if the program has knowledge of the D_OPEN function.
R/W
Global SMRAM Enable (G_SMRARE):
0b
If set to a 1, then Compatible SMRAM functions are enabled, providing 128 KB of
DRAM accessible at the A0000h address while in SMM (ADSB with SMM decode).
To enable Extended SMRAM function this bit has be set to 1. Refer to the section
on SMM for more details. Once D_LCK is set, this bit becomes read only.
RO
Compatible SMM Space Base Segment (C_BASE_SEG):
010 b
This field indicates the location of SMM space. SMM DRAM is not remapped. It is
simply made visible if the conditions are right to access SMM space, otherwise the
access is forwarded to DMI. Since the GMCH supports only the SMM space
between A0000 and BFFFF, this field is hardwired to 010.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
97
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.28
ESMRAMC—Extended System Management RAM Control
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
9Eh
38h
RO, R/W, R/WC, R/W/L
8 bits
The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended
SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above
1 MB.
Bit
Access
&
Default
Description
7
R/W
0b
6
R/W/C
0b
5
RO
1b
RO
1b
RO
1b
R/W
00 b
Enable High SMRAM (H_SMRAME):
Controls the SMM memory space location (i.e. above 1 MB or below 1 MB) when
G_SMRAME is 1 and H_SMRAME this bit is set to 1, the high SMRAM memory space is
enabled.
SMRAM accesses within the range 0FEDA0000h to 0FEDBFFFFh are remapped to
DRAM addresses within the range 000A0000h to 000BFFFFh.
Once D_LCK has been set, this bit becomes read only.
Invalid SMRAM Access (E_SMERR):
This bit is set when CPU has accessed the defined memory ranges in Extended SMRAM
(High Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0. It is
software’s responsibility to clear this bit.
The software must write a 1 to this bit to clear it.
SMRAM Cacheable (SM_CACHE):
This bit is forced to 1 by the GMCH .
L1 Cache Enable for SMRAM (SM_L1):
This bit is forced to 1 by the GMCH.
L2 Cache Enable for SMRAM (SM_L2):
This bit is forced to 1 by the GMCH.
TSEG Size (TSEG_SZ):
Selects the size of the TSEG memory block if enabled. Memory from the top of DRAM
space is partitioned away so that it may only be accessed by the processor interface and
only then when the SMM bit is set in the request packet. Non-SMM accesses to this
memory region are sent to DMI when the TSEG memory block is enabled.
00 - 1MB TSEG.
(TOLUD – Graphics Stolen Memory Size – 1M) to (TOLUD – Graphics Stolen Memory
Size).
01 - 2MB TSEG
(TOLUD – Graphics Stolen Memory Size – 2M) to (TOLUD – Graphics Stolen Memory
Size).
10 - 8 MB TSEG
(TOLUD – Graphics Stolen Memory Size – 8M) to (TOLUD – Graphics Stolen Memory
Size).
11 - Reserved.
Once D_LCK has been set, these bits becomes read only.
TSEG Enable (T_EN):
4
3
2:1
0
R/W/L
0b
Enabling of SMRAM memory for Extended SMRAM space only.
When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the
appropriate physical address space.
Note that once D_LCK is set, this bit becomes read only.
98
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.29
ERRSTS—Error Status
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
C8h
0000h
RO, R/WC
16 bits
This register is used to report various error conditions via the SERR messaging mechanism. An SERR
message is generated on a zero to one transition of any of these flags (if enabled by the ERRCMD and
PCICMD registers). These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked by clearing the
appropriate status bit by software writing a 1 to it.
Bit
Access
&
Default
Reserved
15:13
12
R/WC
0b
11
R/WC
0b
R/WC
0b
8
R/WC
0b
7
R/WC
0b
6:0
GMCH Software Generated Event for SMI:
This indicates the source of the SMI was a Device 2 Software Event.
GMCH Thermal Sensor Event for SMI/SCI/SERR:
Indicates that a GMCH Thermal Sensor trip has occurred and an SMI, SCI, or SERR
has been generated. The status bit is set only if a message is sent based on Thermal
event enables in Error command, SMI command and Sci command registers. A trip
point can generate one of SMI, SCI, or SERR interrupts (two or more per event is
illegal). Multiple trip points can generate the same interrupt, if software chooses this
mode, subsequent trips may be lost. If this bit is already set, then an interrupt message
will not be sent on a new thermal sensor event.
Reserved
10
9
Description
LOCK to non-DRAM Memory Flag (LCKF):
When this bit is set to 1, the GMCH has detected a lock operation to memory space
that did not map into DRAM.
Received Refresh Timeout Flag(RRTOF):
This bit is set when 1024 memory core refreshes are enqueued.
DRAM Throttle Flag (DTF):
1:
Indicates that a DRAM Throttling condition occurred.
0:
Software has cleared this flag since the most recent throttling event
Reserved.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
99
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.30
ERRCMD—Error Command
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
CAh
0000h
RO, R/W
16 bits
This register controls the GMCH responses to various system errors. Since the GMCH does not have
an SERRB signal, SERR messages are passed from the GMCH to the ICH over DMI. When a bit in
this register is set, a SERR message will be generated on DMI whenever the corresponding flag is set
in the ERRSTS register. The actual generation of the SERR message is globally enabled for Device #0
via the PCI Command register.
Bit
Access
&
Default
15:12
11
Description
Reserved
R/W
SERR on GMCH Thermal Sensor Event (TSESERR):
0b
1: The GMCH generates a SERR when bit 11 of the ERRSTS is set. The SERR
must not be enabled at the same time as the SMI for the same thermal sensor event.
0:
10
R/W
Reporting of this condition via SERR messaging is disabled.
Reserved
0b
9
R/W
SERR on LOCK to non-DRAM Memory (LCKERR):
0b
1: The GMCH will generate a SERR special cycle whenever a CPU lock cycle is
detected that does not hit DRAM.
R/W
SERR on DRAM Refresh Timeout (DRTOERR):
0b
1: The GMCH generates an SERR special cycle when a DRAM Refresh timeout
occurs.
0:
8
0:
7
100
Reporting of this condition via SERR messaging is disabled.
R/W
SERR on DRAM Throttle Condition (DTCERR):
0b
1: The GMCH generates an SERR DMI special cycle when a DRAM Read or Write
Throttle condition occurs.
0:
6:0
Reporting of this condition via SERR messaging is disabled.
Reporting of this condition via SERR messaging is disabled.
Reserved.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Host Bridge Device 0 - Configuration Registers (D0:F0)
R
4.1.31
SKPD—Scratchpad Data (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
0
DCh
00000000h
R/W
32 bits
This register holds 32 writable bits with no functionality behind them. It is for the convenience of
BIOS and graphics drivers.
Bit
Access &
Default
31:0
R/W
Description
Scratchpad Data: 1 DWORD of data storage.
00000000 h
4.1.32
CAPID0—Capability Identifier
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
71:24
23:16
15:8
7:0
0
E0h
xxxxxxxxxxxx90009h
RO
72 bits
Access
&
Default
Description
RO
Intel Reserved
RO
CAPID Length:
09 h
This field has the value 09h to indicate the structure length (9 bytes).
RO
Next Capability Pointer:
00 h
This field is hardwired to 00h indicating the end of the capabilities linked list.
RO
CAP_ID:
09 h
This field has the value 1001b to identify the CAP_ID assigned by the PCI SIG for
vendor dependent capability pointers.
§
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
101
Device #0 Memory Mapped I/O Register
R
5
Device #0 Memory Mapped I/O
Register
Note: All accesses to the Memory Mapped registers must be made as a single DWORD (4 bytes) or
less. Access must be aligned on a natural boundary.
5.1
MCHBAR Registers Device #0
A variety of timing & control registers have been moved to MMR space of Device 0 due to space
constraints.
To simplify the read/write logic to the SRAM, BIOS is required to write and read 32-b aligned Double
Words. The SRAM includes a separate Write Enable for every Double Word.
The BIOS read/write cycles are performed in a memory mapped IO range that is setup for this purpose
in the PCI configuration space, via std. PCI range scheme.
5.2
Device #0 MCHBAR Chipset Control Register Space
Address
Offset (h)
Register
Symbol
000-039h
040h
Default
Value
Access
Reserved
HIC
Host Interface Configuration
041-0FFh
Reserved
100h
C0DRB0
Ch0 DRAM Rank Boundary Address 0
00h
R/W
101h
C0DRB1
Ch0 DRAM Rank Boundary Address 1
00h
R/W
102h
C0DRB2
Ch0 DRAM Rank Boundary Address 2
00h
R/W
103h
C0DRB3
Ch0 DRAM Rank Boundary Address 3
00h
R/W
Ch0 DRAM Rank 0,1 Attribute
00h
RO, R/W
Ch0 DRAM Rank 2,3 Attribute
00h
RO, R/W
00h
RO, R/W
0000h
RO, R/W
104-107h
Reserved
108h
C0DRA0
109h
C0DRA2
10A-10Bh
10Ch
Reserved
C0DCLKDIS
10Dh
10E-10Fh
Ch0 DRAM Clock Disable
Reserved
C0BNKARC
Ch0 Bank Architecture
110-113h
C0DRT0
Ch0 DRAM Timing Register 0
A96000E8h
RO, R/W
114-117h
C0DRT1
Ch0 DRAM Timing Register 1
00006111h
RO, R/W
118-11Bh
C0DRT2
Ch0 DRAM Timing Register2
000003FFh
RO, R/W
00000000h
RO, R/W
11C-11Fh
120-123h
102
Register Name
Reserved
C0DRC0
Ch0 DRAM Controller Mode Register 0
124-127h
C0DRC1
Ch0 DRAM Controller Mode Register 1
00000000h
RO, R/W
138-13Bh
C0DRC2
Ch0 DRAM Controller Mode Register 2
00000000h
RO, R/W
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
Address
Offset (h)
Register
Symbol
13C-157h
158-15Bh
Register Name
Default
Value
Access
00000000h
RO, R/L, R/W/L
Reserved
C0DTC
15C-17Fh
Ch0 DRAM Throttling Control
Reserved
180h
C1DRB0
Channel 1 DRAM Rank Boundary Address
0
00h
R/W
181h
C1DRB1
Channel 1 DRAM Rank Boundary Address
1
00h
R/W
182h
C1DRB2
Channel 1 DRAM Rank Boundary Address
2
00h
R/W
183h
C1DRB3
Channel 1 DRAM Rank Boundary Address
3
00h
R/W
184-187h
Reserved
188h
C1DRA0
Channel 1 Dram Rank 0,1 Attribute
00h
RO, R/W
189h
C1DRA2
Channel 1 Dram Rank 2,3 Attribute
00h
RO, R/W
00h
RO, R/W
18A-18Bh
18Ch
Reserved
C1DCLKDIS
18Dh
Channel 1 DRAM Clock Disable
Reserved
18E-18Fh
C1BNKARC
Channel 1 Bank Architecture
0000h
RO, R/W
190-193h
C1DRT0
Channel 1 DRAM Timing Register 0
A96000E8h
RO, R/W
194-197h
C1DRT1
Channel 1 DRAM Timing Register 1
00006111h
RO, R/W
198-19Bh
C1DRT2
Channel 1 DRAM Timing Register 2
000003FFh
RO, R/W
19C-19Fh
Reserved
1A0-1A3h
C1DRC0
Channel 1 DRAM Controller Mode 0
40002801h
RO, R/W
1A4-1A5h
C1DRC1
Channel 1 DRAM Controller Mode 1
00000000h
RO, R/W
00000000h
RO, R/W
00000000h
RO, R/L, R/W/L
00000000h
RO, R/W
1A6-1A7h
1A8-1AFh
Reserved
C1DRC2
1B0-1D7h
1D8-1DBh
Reserved
C1DTC
1DC-1FFh
200-203h
204-27Fh
Channel 1 DRAM Controller Mode 2
Channel 1 DRAM Throttling Control
Reserved
DCC
DRAM Channel Control
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
103
Device #0 Memory Mapped I/O Register
R
5.2.1
HIC Host Interface Configuration Register
PCI Device:
Address Offset:
Size:
Bit
Access &
Default
Description
Reserved
31:9
8
MCHBAR
040h
32 bits
RO
0b
PCI Express Graphics / SDVO strap bit –
Specifies the use of the PCI Express bus for external graphics muxed with DVO.
0: SDVO disabled. PCI Express is available.
1: SDVO enabled. PCI Express is disabled.
Reserved
7:2
1
RW
0b
Dispatch Disable:
0: Enables dispatch of qualified CPU-to-DRAM read requests in FSB.
1: Dispatch occurs no sooner than T3.
Note: BIOS must set this bit to a 1 before starting DRAM initialization. BIOS
can set this bit to 0 after DRAM initialization is complete.
Reserved
0
5.2.2
HIT1—Host Interface Test_1
PCI Device:
Address Offset:
Size:
Bit
Access &
Default
31:6
5
MCHBAR
044h
32 bits
Description
Reserved
R/W
0b
Front Side Bus Power Management Enable.
0 = FSB Power Management Disabled (Default).
1 = FSB Power Management Enabled.
4
R/W
0b
C2 FSB Power Management Enable
0 = C2 FSB Power Management Disabled.
1 = C2 FSB Power Management Enabled.
3:0
104
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.2.3
C0DRB0—Channel 0 DRAM Rank Boundary 0
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
100h
00h
R/W
8 bits
The DRAM Rank Boundary Register defines the upper boundary address of each DRAM rank with a
granularity of 128 MB (256 Mbit, X16 devices). Each rank has its own single-byte DRB register.
These registers are used to determine which chip select will be active for a given address.
Channel and rank map:
ch0 rank0:
100h
ch0 rank1:
101h
ch0 rank2:
102h
ch0 rank3:
103h
Reserved:
104h to 107h
In all modes, if a SO-DIMM is single-sided it appears as a populated rank and an empty rank. A DRB
must be programmed appropriately for each.
Each Rank is represented by a byte. Each byte has the following format.
Bit
Access &
Default
7:0
Channel 0 DRAM Rank Boundary Address:
R/W
00 h
5.2.4
Description
This 8 bit value defines the upper and lower addresses for each DRAM rank. Bits 6:2 are
compared against Address 31:27 to determine the upper address limit of a particular rank.
Bits 1:0 must be 0s. Bit 7 may be programmed to a 1 in the highest DRB (DRB3) if 4 GB of
memory is present.
C0DRB1—Channel 0 DRAM Rank Boundary 1
PCI Device:
MCHBAR
Address Offset:
101h
Default Value:
00h
Access:
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRB0.
5.2.5
C0DRB2—Channel 0 DRAM Rank Boundary 2
PCI Device:
MCHBAR
Address Offset:
102h
Default Value:
00h
Access:
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRB0.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
105
Device #0 Memory Mapped I/O Register
R
5.2.6
C0DRB3—Channel 0 DRAM Rank Boundary 3
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
103h
00h
R/W
8 bits
The operation of this register is detailed in the description for register C0DRB0.
5.2.7
C0DRA0—Channel 0 DRAM Rank 0,1 Attribute
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
108h
00h
RO, R/W
8 bits
The DRAM Rank Attribute Registers define the page sizes to be used when accessing different
ranks. These registers should be left with their default value (all zeros) for any rank that is
unpopulated, as determined by the corresponding CxDRB registers. Each byte of information in the
CxDRA registers describes the page size of a pair of ranks.
Channel and rank map:
Ch0 Rank0, 1: 108h
Ch0 Rank2, 3: 109h
Reserved. 10Ah, 10Bh:
Bit
Access &
Default
7
Description
Reserved
6:4
Channel 0 DRAM odd Rank Attribute:
This 3-bit field defines the page size of the corresponding rank.
000: Unpopulated.
R/W
001: Reserved
000 b
010: 4 kB
011: 8 kB
100: 16 kB
Others: Reserved
3
Reserved
2:0
Channel 0 DRAM even Rank Attribute: This 3-bit field defines the page size of the
corresponding rank.
000: Unpopulated.
R/W
001: Reserved
000 b
010: 4 kB
011: 8 kB
100: 16 kB
Others: Reserved
106
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.2.8
C0DRA2—Channel 0 DRAM Rank 2,3 Attribute
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
109h
00h
RO, R/W
8 bits
The operation of this register is detailed in the description for register C0DRA0.
5.2.9
C0DCLKDIS—Channel 0 DRAM Clock Disable
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
10Ch
00h
RO, R/W
8 bits
This register can be used to disable the System Memory Clock signals to each SO-DIMM slot, which
can significantly reduce EMI and Power concerns for clocks that go to unpopulated SO-DIMM s.
Clocks should be enabled based on whether a slot is populated.
Bit
Access &
Default
7:3
RO
Description
Reserved
00 b
R/W
2
0b
R/W
1
0b
R/W
0
0b
DIMM clock gate enable pair 2 - (Reserved)
0:
Tri-state the corresponding clock pair.
1:
Reserved
DIMM clock gate enable pair 1
0:
Tri-state the corresponding clock pair.
1:
Enable the corresponding clock pair.
DIMM clock gate enable pair 0
0:
Tri-state the corresponding clock pair.
1:
Enable the corresponding clock pair.
Note: Since there are multiple clock signals assigned to each rank of a SO-DIMM , it is important to
clarify exactly which rank width field affects which clock signal:
Channel
Rank
Clocks Affected
0
0 or 1
SM_CK[2:0] / SM_CK#[1:0]
1
2 or 3
SM_CK[4:3] / SM_CK#[4:3]
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
107
Device #0 Memory Mapped I/O Register
R
5.2.10
C0BNKARC—Channel 0 DRAM Bank Architecture
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
0
10Eh
0000h
RO, R/W
16 bits
This register is used to program the bank architecture for each Rank
Bit
Access &
Default
15:8
RO
Description
Reserved
00 h
7:6
R/W
00 b
Rank 3 Bank Architecture
00: 4 Banks.
01: 8 Banks.
1X: Reserved
5:4
R/W
00 b
Rank 2 Bank Architecture
00: 4 Banks.
01: 8 Banks.
1X: Reserved
3:2
R/W
00 b
Rank 1 Bank Architecture
00: 4 Banks.
01: 8 Banks.
1X: Reserved
1:0
R/W
00 b
Rank 0 Bank Architecture
00: 4 Banks.
01: 8 Banks.
1X: Reserved
108
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.2.11
C0DRT0—Channel 0 DRAM Timing Register 0
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
110h
A96000E8
RO, R/W
32 bits
This 32-bit register defines the timing parameters for all devices in this channel. The BIOS programs
this register with the "least common denominator" values for each channel after reading configuration
registers of each device in each channel.
Bit
Access
&
Default
Description
Back To Back Write To Precharge Command Spacing (Same bank):
This field determines the number of clocks between write command and a subsequent
pre-charge command to the same bank.
The minimum number of clocks is calculated based on this formula:
DDR 2 :- CL – 1 + BL/2 + tWR
DDR
31:28
:-
1 + BL/2 + tWR
R/W
0000 – 0100: Reserved
Ah
1110 – 1111 Reserved
NOTE: Write Recovery time (tWR).
Write recovery time is a standard DDR/DDR 2 timing parameter that determines
minimum time between a write command and a subsequent precharge command to
the same bank. This parameter is programmable on DDR 2 SO-DIMM s and the value
used above must match the largest delay programmed in any SO-DIMM in the
system. Minimum recommended values are documented below.
tWR (on CK)
3 Clocks – DDR 333 or DDR 2 400
4 Clocks – DDR 2 533
Back To Back Write To Read Command Spacing (Same rank):
This field determines the number of clocks between write command and a subsequent
read command to the same rank.
The minimum number of clocks is calculated based on this formula
DDR 2 :- CL – 1 + BL/2 + tWTR
DDR
27:24
:- 1 + BL/2 + tWTR
R/W
0000 – 0011 Reserved
9h
1100 – 1111 Reserved
NOTE: Write to Read Command delay (tWTR).
The tWTR is a standard DDR timing parameter with a value of 1 clock for DDR CL=2
or CL=2.5 and a value of 2 clocks for DDR CL=1.5 or any CL for DDR 2 400/533.
The tWTR is used to time a RD command after a WR command to the same row.
1 Clocks – CL = 2 or CL = 2.5 for DDR 333
2 Clocks – CL = 1.5 or DDR2 400, DDR2 533
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
109
Device #0 Memory Mapped I/O Register
R
Bit
Access
&
Default
Description
Back To Back Write-Read Command Spacing (Different Rank):
This field determines the number of turn-around clocks on the data bus needs to be
inserted between write command and a subsequent read command.
The minimum spacing of commands is calculated based on the formula
DDR 2 = BL/2 + TA –1
(Derived from: DDR 2 = BL/2 + TA (wr-rd) + WL – CL
DDR 2 = BL/2 + TA + CL –1 – CL)
DDR = Ceiling( DQSS + BL/2 + TA (wr-rd) - CL);
23:22
R/W
01 b
DQSS: is the time from the write command to the associated data
and is always 1 CK in DDR
BL: is the burst length 8
TA: is the required write to read DQ turn-around on the bus
can be set to 1, 2, or 3 CK using this register.
CL: is CAS latency
Encoding
BL8 CMD Spacing
00:
6
01:
5
10:
4
11:
3 (DDR only)
Back To Back Read-Write Command Spacing:
This field determines the # of turn-around clocks between the read command and a
subsequent write command
The minimum spacing of commands is calculated based on the formula
DDR 2 :- BL/2 + TA +1
(DDR 2 :- CL + BL/2 + TA (wr-rd) – WL
DDR 2 :- CL + BL/2 + TA – CL +1)
DDR :- Ceiling (CL + BL/2 + TA – 1)
BL: is the burst length 8
21:20
R/W
TA: is the required read to write DQ turn-around on the bus
can be set to 1, 2, 3, 4 CK for DDR 2
10 b
and can be set to 1, 2, 3 CK for DDR
CL: is CAS latency
Encoding
00:
BL8 CMD Spacing
9
01:
8
10:
7
11:
6
The bigger turn-around are used in large configurations, where the difference in total
channel delay between the fastest and slowest SO-DIMM is large.
Back To Back Write Command Spacing:
This field controls the turnaround time on the DQ bus for WR-WR sequence to
different ranks in one channel.
19:18
R/W
The minimum spacing of commands is calculated based on the formula
00 b
DDR 2 and DDR = BL/2 + TA
Encoding
110
Turn-Around
BL8 CMD Spacing
00:
2 turnaround clocks on DQ
6
01:
1 turnaround clocks on DQ
5
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
Bit
Access
&
Default
Description
10:
0 turnaround clocks on DQ
11:
Reserved
4
The bigger turn-around are used in large configurations, where the difference in total
channel delay between the fastest and slowest SO-DIMM is large.
17
RO
Reserved
0b
Back To Back Read Command Spacing:
This field controls the turnaround time on the DQ bus for RD-RD sequence to
different ranks in one channel.
The minimum spacing of commands is calculated based on the formula
16
R/W
DDR 2 and DDR = BL/2 + TA
0b
Encoding
Turn-Around
BL8 CMD Spacing
0:
2 turnaround clocks on DQ
6
1:
1 turnaround clocks on DQ
5
The bigger turn-around are used in large configurations, where the difference in total
channel delay between the fastest and slowest SO-DIMM is large.
Read Delay (tRD).
tRD is the number of memory clocks from CS# assert to HDRDY# assertion on the
FSB.
The following tRD values are supported:
00000 – 00010:
15:11
R/W
00 h
Reserved.
00011:
3 mclks
00100:
4 mclks
00101:
5 mclks
00110:
6 mclks
00111:
7 mclks
01000:
8 mclks
01001:
9 mclks
01010:
10 mclks
...
10:9
RO
11110:
30 mclks
11111:
31 mclks
Reserved
00 b
8:4
R/W
01111 b
3:0
R/W
Write Auto pre-charge to Activate (Same bank)
This field determines the clock spacing between write command with Auto pre-charge
and a subsequent Activate command to the same bank.
The minimum spacing is calculated based on this formula:
DDR 2 = CL -1 + BL/2 + tWR + tRP
DDR = 1 + BL/2 + tWR + tRP
00000 - 00011: Reserved
00100 – 10011: Allowed
10100 – 11111: Reserved.
Note: tWR is a Dram Parameter.
Read Auto pre-charge to Activate (Same bank)
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
111
Device #0 Memory Mapped I/O Register
R
Bit
Access
&
Default
8h
Description
This field determines the clock spacing between read command with Auto pre-charge
and a subsequent Activate command to the same bank.
The minimum spacing is calculated based on this formula:
DDR 2 = tRTPC + tRP
DDR = tRTPC + tRP
Note tRTPC is defined in XXDRT1 bits 29:28.
112
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.2.12
C0DRT1—Channel 0 DRAM Timing Register 1
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
31:30
29:28
R/W
00 b
27:24
23:20
MCHBAR
114h
00006111h
RO, R/W
32 bits
R/W
6h
19:18
17
R/W
0b
16
R/W
0b
Description
Reserved
Read to Pre-charge (tRTPC).
These bits control the number of clocks that are inserted between a read command
to a row pre-charge command to the same rank.
Encoding
tRP
00:
BL/2
01 - 11:
Reserved
Reserved
Activate to Precharge delay (tRAS).
This bit controls the number of DRAM clocks for tRAS. Minimum recommendations
are beside their corresponding encodings.
Recommended values:
7h DDR 333
9h DDR 2 400
Ch DDR 2 533
Reserved
Activate to Activate delay:
Control Act to Act delay between the different banks of the same rank. Trr is
specified in “ns”. 10ns for 2KB page size and 7.5 ns for 1KB page
0 = 2 Clock
1 = 3 Clock
Pre-All to Activate Delay (tRPALL).
This is applicable only to 8 bank architectures.
Must be set to 1 if any Rank is populated with 8 bank device technology.
0: tRPALL = tRP
1: tRPALL = tRP + 1
Refresh Cycle Time (tRFC).
Refresh cycle time is measured from a Refresh command (REF) until the first
Activate command (ACT) to the same rank, required to perform a read or write.
DDR 2 tRFC spec
tRFC
256Mb
512Mb
1Gb
DDR2 400
(5ns)
15:11
10
R/W
01100 b
RO
DDR2 533
(3.75ns)
75 ns = 15
clks
75 ns = 20
clks
105 ns = 21 clks
127.5 ns = 26 clks
105 ns = 28 clks
127.5 ns = 34clks
DDR 1 tRFC spec
tRFC
64Mb -512Mb
1Gb
DDR 333
75 ns = 13 clks
120 ns = 20 clks
(6ns)
00000b – 11111b Zero Clocks to Thirty-one Clocks respectively
Actual clocks period depends on DDR clock frequency.
Bios should round up. If the required clock count exceeds as allowed by this
register, the bios should set this register to the max value and set
corresponding bits in SDBUP.
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
113
Device #0 Memory Mapped I/O Register
R
Bit
Access &
Default
9:8
R/W
01 b
7
RO
6:4
R/W
001 b
3
RO
Description
CASB Latency (tCL).
This value is programmable on DDR 2 SO-DIMM’s. The value programmed here
must match the CAS Latency of every DDR 2 SO-DIMM in the system.
Encoding
DDR CL
DDR 2 CL
00:
3
5
01:
2.5
4
10:
Reserved
3
11:
Reserved
Reserved
Reserved
DRAM RASB to CASB Delay (tRCD).
This bit controls the number of clocks inserted between a row activate command and
a read or write command to that row.
Encoding
tRCD
000:
2 DRAM Clocks
001:
3 DRAM Clocks
010:
4 DRAM Clocks
011:
5 DRAM Clocks
100 - 111:
Reserved
Reserved
DRAM RASB Precharge (tRP).
This bit controls the number of clocks that are inserted between a row precharge
command and an activate command to the same rank.
2:0
R/W
001 b
Encoding
2 DRAM Clocks
001:
3 DRAM Clocks
010:
4 DRAM Clocks
011:
5 DRAM Clocks
100 - 111:
114
tRP
000:
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.2.13
C0DRT2—Channel 0 DRAM Timing Register 2
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
31:30
Access &
Default
R/W
00 b
29:18
17:16
15:10
MCHBAR
118h
0000003FFh
RO, R/W
32 bits
RW
00 b
RO
00 h
9:8
R/W
11 b
7:5
R/W
111 b
Description
CKE Deassert Duration
00 = 1 clk (DDR)
01 = Reserved
10 = 3 clk (DDR2)
11 = Reserved
Must be set to 10 for DDR2
Reserved
Reserved
Reserved
Power Down Exit to CS# active time (tXPDN).
Power down exit time is tracked from the clock in which we sample CKE active,
after exit from dynamic power down, until the clock which we drive a command
(ACT/PRE/RD/WR).
Exit time must be set to 1 clock for DDR and 2 for DDR2.
Option to set exit time to 2 clocks for DDR is provided.
00 = Reserved.
01 = Reserved
10 = Power Down Exit time is set to 2 clocks
11 = Power Down Exit time is set to 1 clock
DRAM Page Close Idle Timer:
This field determines the number of clocks a bank needs to remain unaccessed
before dram controller considers it for pre-charge.
001 8 DRAM clocks
111 Infinite, Pages are left open.
Other
Reserved
DRAM Power down Idle Timer:
This field determines the number of clocks a rank remains unaccessed before the
controller powers down that rank (CKE de-asserted).
4:0
R/W
11111 b
01000b
Recommended setting when using DDR2-533 MHz memory.
10000b
Recommended setting when using DDR2-400 MHz memory.
11111b
Infinite, CKE is not de-asserted based on the timer.
Other
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
115
Device #0 Memory Mapped I/O Register
R
5.2.14
C0DRC0––Channel 0 DRAM Controller Mode 0
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
MCHBAR
120h
40002801h
RO, R/W
32 bits
Access
&
Default
31:30
Description
Reserved.
Initialization Complete (IC):
29
R/W
0b
28
This bit is used for communication of software state between the memory controller
and the BIOS. BIOS sets this bit to 1 after initialization of the DRAM memory array is
complete.
Reserved
Active SDRAM Ranks: Implementations may use this field to limit the maximum
number of SDRAM ranks that may be active at once.
0000: All ranks allowed to be in the active state
27:24
R/W
0h
0001: One Rank
0010: Two Ranks
0011: Three Ranks
Others: Reserved.
If this field is set to a non-zero value, then bits CXDRT2(4:0) should be set to the
minimum value as described by the formula, else the system hangs.
23:16
Reserved
CMD copy enable (Single channel only)
In a single channel mode, the CMD pins (MA, BS, RAS, CAS, WE) on both channels
are driven and are physical copies of each other.
15
R/W
0b
Setting this bit disables the CMD pins on channel B. Having the additional copy of
CMD pins helps reduce loading on these pins, since in a two SO-DIMM system, each
copy can be routed up to separate SO-DIMM. In a single DIMM system, the second
copy can be disabled to eliminate unnecessary toggling of these pins.
If this bit needs to be set, BIOS should do that before memory init sequence.
This bit should not be set in a dual channel system
14:11
Reserved
Refresh Mode Select (RMS):
10:8
R/W
000 b
This field determines whether refresh is enabled and, if so, at what rate refreshes will
be executed.
000:
Refresh disabled
001:
Refresh enabled. Refresh interval 15.6 µs
010:
Refresh enabled. Refresh interval 7.8 µs
Other:
7
6:4
RO
Reserved
Reserved
0b
R/W
Mode Select (SMS).
000 b
These bits select the special operational mode of the DRAM interface. The special
modes are intended for initialization at power up.
000:
Post Reset state – When the GMCH exits reset (power-up or otherwise), the
mode select field is cleared to 000.
During any reset sequence, while power is applied and reset is active, the GMCH deasserts all CKE signals. After internal reset is de-asserted, CKE signals
116
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
Bit
Access
&
Default
Description
remain de-asserted until this field is written to a value different than “000”.
On this event, all CKE signals are asserted.
During suspend, GMCH internal signal triggers DRAM controller to flush pending
commands and enter all ranks into Self-Refresh mode. As part of resume
sequence, GMCH will be reset – which will clear this bit field to “000” and
maintain CKE signals de-asserted. After internal reset is de-asserted, CKE
signals remain de-asserted until this field is written to a value different than
“000”. On this event, all CKE signals are asserted.
During entry to other low power states (C3, S1), GMCH internal signal triggers DRAM
controller to flush pending commands and enter all ranks into Self-Refresh
mode. During exit to normal mode, GMCH signal triggers DRAM controller
to exit Self-Refresh and resume normal operation without S/W involvement.
001:
NOP Command Enable – All CPU cycles to DRAM result in a NOP
command on the DRAM interface.
010:
All Banks Pre-charge Enable – All CPU cycles to DRAM result in an “all
banks precharge” command on the DRAM interface.
011:
Mode Register Set Enable – All CPU cycles to DRAM result in a “mode
register” set command on the DRAM interface. Host address lines are
mapped to DRAM address lines in order to specify the command sent.
Host address lines [12:3] are mapped to MA[9:0], and HA[13] is mapped to
MA[11].
101:
Reserved
110:
CBR
CBR Refresh Enable – In this mode all CPU cycles to DRAM result in a
cycle on the DRAM interface
111:
3
Normal operation
Reserved
Burst Length (BL):
2
R/W
0b
The burst length is the number of QWORDS returned by a SO-DIMM per read
command, when not interrupted. This bit is used to select the DRAM controller’s Burst
Length operation mode. It must be set to match to the behavior of the SO-DIMM.
0:
Burst Length of 4
1:
Burst Length of 8
DRAM Type (DT)
Used to select between supported SDRAM types.
1:0
RO
00:
Reserved
01 b
01:
Dual Data Rate
10:
Dual Data Rate 2 (DDR 2) SDRAM
11:
Reserved
(DDR)
SDRAM
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
117
Device #0 Memory Mapped I/O Register
R
5.2.15
C0DRC1––Channel 0 DRAM Controller Mode 1
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
Access
& Default
31:20
19:16
R/W
0h
15:13
12
R/W
0b
11
R/W
0b
10:9
8
7:0
118
R/W
0b
MCHBAR
124h
00000000h
RO, R/W
32 bits
Description
Reserved
CKE Tri-state Enable Per Rank.
Bit 16 corresponds to rank 0
Bit 17 corresponds to rank 1
Bit 18 corresponds to rank 2
Bit 19 corresponds to rank3
0 = CKE is not tri-stated.
1 = CKE is tri-stated. This is set only if the Rank is physically not populated.
Reserved
CS# Tri-state enable (CSBTRIEN):When set to a 1, the DRAM controller will tri-state CS# when the corresponding CKE
is deasserted.
0:
Address Tri-state Disabled
1:
Address Tri-state Enabled
Address Tri-state enable (ADRTRIEN):When set to a 1, the DRAM controller will tri-state the MA, CMD, and CSB (CSB if
lines only when all CKEs are deasserted. CKEs deassert based on Idle timer or max
rank count control.
0:
Address Tri-state Disabled
1:
Address Tri-state Enabled
Reserved
DRAM Channel IO-Buffers Activate:
This bit is cleared to 0 during reset and remains inactive until it is set to 1 by BIOS. In
addition, this bit can be cleared and set during debug procedures.
While 0, the DRAM controller core logic forces the state of the IO-buffers in this
channel to “reset” or “preset”,
While 1, the DRAM controller core logic enables the DRAM IO-buffers in this
channel to operate normally.
BIOS initialization Procedure:
This bit is cleared (0) during reset. It remains 0 after reset. BIOS is expected to use
to following sequence:
During and after platform reset, the DRAM controller core logic drives CKE to 0 and
toggles clock output (drive strength and slew rate are set based on default values).
After reset, BIOS detects DRAM configuration, through Serial Presence Detect.
BIOS sets appropriate RCOMP values, then it performs initial RCOMP.
BIOS enables the RCVEN, DQS and optionally CK DLL’s
BIOS sets this bit (1), to enable normal operations. MA/BA/command are driven to
default, CSB I driven inactive (data related outputs remain tri-stated, CKE remain 0
while clocks are toggled).
Perform DRAM initialization, through SMS bit field (CKE is activated).
Enable refresh.
Enable periodic RCOMP.
Both this bit must be 1 and SMS must be different than 000 for CKE to be activated.
It is sufficient to clear this bit to 0 for CKE to go inactive.
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.2.16
C0DRC2––Channel 0 DRAM Controller Mode 2
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
MCHBAR
128h
00000000h
RO, R/W
32 bits
Access
& Default
Description
Reserved
31:28
Dram ODT Tristate Enable Per Rank: DDR 2
Bit 24 corresponds to rank 0
27:24
R/W
0h
Bit 25 corresponds to rank 1
Bit 26 corresponds to rank 2
Bit 27 corresponds to rank 3
0 = ODT is not tri-stated.
1 = ODT is tri-stated. This is set only if the Rank is physically not populated.
23:0
5.2.17
Reserved
C1DRB0—Channel 1 DRAM Rank Boundary Address 0
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
180h
00h
R/W
8 bits
The operation of this register is detailed in the description for register C0DRB0.
5.2.18
C1DRB1—Channel 1 DRAM Rank Boundary Address 1
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
181h
00h
R/W
8 bits
The operation of this register is detailed in the description for register C0DRB0.
5.2.19
C1DRB2—Channel 1 DRAM Rank Boundary Address 2
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
182h
00h
R/W
8 bits
The operation of this register is detailed in the description for register C0DRB0.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
119
Device #0 Memory Mapped I/O Register
R
5.2.20
C1DRB3—Channel 1 DRAM Rank Boundary Address 3
MMIO Range:
MCHBAR
Address Offset:
183h
Default Value:
00h
Access:
R/W
Size:
8 bits
The operation of this register is detailed in the description for register C0DRB0.
5.2.21
C1DRA0—Channel 1 Dram Rank 0,1 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
188h
00h
RO, R/W
8 bits
The operation of this register is detailed in the description for register C0DRA0.
5.2.22
C1DRA2—Channel 1 Dram Rank 2,3 Attribute
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
189h
00h
RO, R/W
8 bits
The operation of this register is detailed in the description for register C0DRA0.
5.2.23
C1DCLKDIS—Channel 1 DRAM Clock Disable
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
18Ch
00h
RO, R/W
8 bits
The operation of this register is detailed in the description for register C0DCLKDIS.
5.2.24
C1BNKARC—Channel 1 Bank Architecture
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
18Eh
0000h
RO, R/W
16 bits
The operation of this register is detailed in the description for register C0BNKARC.
120
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.2.25
C1DRT0—Channel 1 DRAM Timing Register 0
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
190h
A96000E8h
RO, R/W
32 bits
The operation of this register is detailed in the description for register C0DRT0.
5.2.26
C1DRT1—Channel 1 DRAM Timing Register 1
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
194h
00006111h
RO, R/W
32 bits
The operation of this register is detailed in the description for register C0DRT1.
5.2.27
C1DRT2—Channel 1 DRAM Timing Register 2
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
198h
000003FFh
RO, R/W
32 bits
The operation of this register is detailed in the description for register C0DRT2.
5.2.28
C1DRC0—Channel 1 DRAM Controller Mode 0
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
1A0h
40002801h
RO, R/W
32 bits
The operation of this register is detailed in the description for register C0DRC0.
5.2.29
C1DRC1—Channel 1 DRAM Controller Mode 1
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
1A4h
00000000h
RO, R/W
16 bits
The operation of this register is detailed in the description for register C0DRC1.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
121
Device #0 Memory Mapped I/O Register
R
5.2.30
C1DRC2––Channel 1 DRAM Controller Mode 2
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
1A8h
00000000h
RO, R/W
32 bits
The operation of this register is detailed in the description for register C0DRC2.
5.2.31
DCC—DRAM Channel Control
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
200h
00000000h
RO, R/W
32 bits
This register controls how the DRAM channels work together. It affects how the CxDRB registers are
interpreted and allows them to steer transactions to the correct channel.
Bit
Access
&
Default
31:20
Description
Reserved
19
R/W
18:16
R/W
Initialization Complete (IC): See register description in C0DRC0[29]
0b
Mode Select (SMS): See register description in C0DRC0[6:4]
000 b
15:3
Reserved
Single Channel Selector (SCS):
2
R/W
When in Single Channel mode, this is the populated channel.
0b
0:
Channel 0 (Default)
1:
Channel 1 (Reserved)
DRAM Addressing Mode Control (DAMC):
1:0
122
R/W
00 b
00:
Single Channel
01:
Dual Channel Asymmetric
10:
Dual Channel Symmetric
11:
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.2.32
Device #0 MCHBAR Clock Controls
Table 5-1. Device #0 MCHBAR Clock/Thermal Sensor Controls
Address
Offset (h)
Register
Symbol
Register Name
Default Value
Access
C00-C03h
CLKCFG
GMCH Clock Configuration
00000000h
RO, R/W
C04-CEAh
5.2.33
Reserved
CLKCFG—Clocking Configuration
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
C00h
00000000h
RO, R/W
32 bits
These register bits are used for setting and changing DDR frequency, initializing GMCH memory
clocks.
Bit
Access &
Default
R/W
0b
R/W
0000h
31:29
29:17
15:7
6:4
3
Reserved.
R/W
0b
RW
strap
dependent
RO
0b
2:0
5.2.34
Reserved
R/W
0b
16
RO
Description
Memory Core Clock control
0 = DDR333, DDR400 (Default) (DDR533 @ Vcc = 1.5 V)
®
®
1 = DDR533 (for Intel Pentium M processor 90 nm, 2 MB L2 Cache,
533 MHz FSB support at Vcc =1.05 V)
®
Please refer to the Mobile Intel 915 Express Chipset Family BIOS Spec
for details on programming the DDR PLL VCO Change Sequence.
Reserved
Memory Frequency Select.
Reserved
Reserved
CPCTL—CPunit Control
PCI Device:
Address Offset:
Size:
Bit
15
MCHBAR
C16h
16 bits
Access &
Default
Descriptions
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
123
Device #0 Memory Mapped I/O Register
R
Bit
Access &
Default
14
R/W/S
0b
Descriptions
MCHBAR register warm reset control
0: All MCHBAR registers in the GMCH are reset to their default values upon
RSTIN# assertion initiated by a “warm reset”
1: MCHBAR registers in the GMCH are NOT reset to defaults on a warm reset
assertion; .
Reserved.
13:0
5.3
Device #0 MCHBAR ACPI Power Management
Controls
5.3.1
PMSLFRFC—Dram Self Refresh Control
PCI Device:
Address Offset:
Size:
Bit
Access &
Default
15
RO
MCHBAR
F08h
16 bits
Description
Reserved
0b
14:13
R/W
Reserved
00 b
12:7
RO
Reserved
000000 b
6:4
R/W
Self-refresh CPU State Dependency
000 b
Defines when self-refresh is allowed based on the CPU’s ACPI C state. This field
only defines the CPU state conditions that must be met to use dynamic selfrefresh.
000 = Not allowed in C0, C1, C2, C3, or C4
001 = Reserved
010 = Reserved
011 = Reserved
100 = Reserved
101 = Reserved
110 = Allowed in C3 and C4 only
111 = Reserved
3:0
R/W
Reserved
0h
5.3.2
DSDLLPDC—Dram Slave DLL Power Down Control
PCI Device:
Address Offset:
Size:
124
MCHBAR
F0Ah
16 bits
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
Bit
Access &
Default
15
RO
Description
Reserved
0b
14:13
R/W
Reserved
00 b
12:7
RO
Reserved
000000 b
6:4
R/W
000 b
Slave DLL Power-down CPU State Dependency
Defines when slave DLL power down is allowed based on the CPU’s ACPI C
state. This field only defines the CPU state conditions that must be met to use
dynamic slave DLL power down.
000 = Not allowed in C0, C1, C2, C3, or C4
001 = Reserved
010 = Reserved
011 = Reserved
100 = Reserved
101 = Reserved
110 = Allowed in C3 and C4 only
111 = Reserved
3:0
R/W
Reserved
0h
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
125
Device #0 Memory Mapped I/O Register
R
5.3.3
DMDLLPDC—Dram Master DLL Power Down Control
PCI Device:
Address Offset:
Size:
Bit
Access &
Default
15
RO
MCHBAR
F0Ch
16 bits
Description
Reserved
0b
14:13
R/W
Reserved
00 b
12:7
RO
Reserved
000000 b
6:4
R/W
000 b
Master DLL Power-down CPU State Dependency
Defines when master DLL power-down is allowed based on the CPU’s ACPI C
state. This field only defines the CPU state conditions that must be met to use
dynamic master DLL power-down.
000 = Not allowed in C0, C1, C2, C3, or C4
001 = Reserved
010 = Reserved
011 = Reserved
100 = Reserved
101 = Reserved
110 = Allowed in C3 and C4 only
111 = Reserved
3:0
R/W
Reserved
0h
126
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.3.4
PMCFG—Power Management Configuration
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
31
R/W
MCHBAR
F10h
00000000h
RO, R/W
32 bits
Description
Reserved
0b
30
R/W
Reserved
0b
29:5
RO
Reserved
0000000 h
4
R/W
0b
3
R/W
0b
Enhanced Power Management Features Enable
0 = Legacy power management mode
1 = Enhanced power management
Enhanced Power Management Snoop-detect Behavior
0 = Snoop detection causes a request to the ICH6 for C2
1 = Snoop detection causes a request to the ICH6 for C0
Recommended setting = 0
2
R/W
Reserved
0b
1:0
R/W
00 b
Enhanced Power Management Mode
00 = All enhanced power management functions allowed (Default)
01 = Disable the C2 to C3 transition. Never go past C2.
10 = Disable the C3 to C4 transition. Never go past C3.
11 = Reserved
Recommended Setting = 00
Field is ignored if the Enhanced Power Management Feature Enable bit = 0
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
127
Device #0 Memory Mapped I/O Register
R
5.3.5
PMSTS—Power Management Status
PCI Device:
Address Offset:
Default Value:
Access:
Size:
MCHBAR
F14h
00000000h
RO, R/WC
32 bits
This register is Reset by PWROK only.
Bit
Access &
Default
31:2
RO
Description
Reserved
00000000 h
1
R/WC
0b
Channel 1 (B) in Self-refresh
Set by power management hardware after Channel 1 is placed in self refresh as a
result of a Power State or a Reset Warn sequence,
Cleared by Power management hardware before starting Channel 1 self refresh
exit sequence initiated by a power management exit.
Cleared by the Bios by writing a 1 in a warm reset (Reset# asserted while pwrok is
asserted) exit sequence.
0 = Channel 1 not guaranteed to be in self-refresh.
1 = Channel 1 in Self-Refresh.
0
R/WC
0b
Channel 0 (A)in Self-refresh
Set by power management hardware after Channel 0 is placed in self refresh as a
result of a Power State or a Reset Warn sequence,
Cleared by Power management hardware before starting Channel 0 self refresh
exit sequence initiated by a power management exit.
Cleared by the Bios by writing a 1 in a warm reset (Reset# asserted while pwrok is
asserted) exit sequence.
0 = Channel 0 not guaranteed to be in self refresh.
1 = Channel 0 in Self Refresh.
128
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.3.6
DMICC—DMI Countdown Control
MMIO Range:
Address Offset:
Size:
DMIBAR
208h
32 bits
PCI Express configuration and control of various time related parameters that are not required by the
PCI Express spec.
Bit
31:24
Access &
Default
R/W
Description
Reserved
00 h
23:22
RO
Reserved
0h
21
R/W
Aggressive L0s Entry Enable
0b
Once this bit is set, PCI Express Initialization unit will use aggressive L0s entry
th
policy where 1/4 of the normally waited IDLE time is required
0 : Initialization Unit waits for “#FTS_required *4ns“ of IDLE time to initiate the
transition from L0 to L0s
1: Initialization Unit waits for “#FTS_required *4ns / 4“ of IDLE time to initiate
the transition from L0 to L0s
Note : These bits can be updated by BIOS during run time
20:19
RO
Reserved
00 b
18:11
R/W
Reserved
0F h
10:0
R/W
Reserved
4B0 h
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
129
Device #0 Memory Mapped I/O Register
R
5.4
DMI RCRB
This section describes the mapped registers for the DMI. The DMIBAR register, described in Section
4.1.15 provides the base address for these registers.
This Root Complex Register Block (RCRB) controls the GMCH-ICH6-M serial interconnect that is
based on the PCI Express 1.0 specification. An RCRB is required for configuration and control of
elements that are located internal to a root complex that are not directly associated with a PCI Express
device. The base address of this space is programmed in DMIBAR in device #0 config space.
Note: All RCRB register spaces needs to remain organized as they are here. The VC capabilities (or
at least the first PCI Express Extended Capability) must begin at the 0h offset of the 4K area pointed to
by the associated BAR. This is a PCI Express 1.0 specification requirement.
5.4.1
DMI Register Summary
Table 5-2. DMI Register Summary Table
Address
Offset (h)
Register
Symbol
Default
Value:
Access:
000-003h
DMIVCECH
DMI Virtual Channel Enhanced
Capability Header
04010002h
RO
004-007h
DMIPVCCAP1
DMI Port VC Capability Register 1
00000001h
RO, R/WO
008-00Bh
DMIPVCCAP2
DMI Port VC Capability Register 2
00000001h
RO
00C-00Dh
DMIPVCCTL
DMI Port VC Control
0000h
RO, R/W
00E-00Fh
Reserved
010-013h
DMIVC0RCAP
DMI VC0 Resource Capability
00000001h
RO
014-017h
DMIVC0RCTL0
DMI VC0 Resource Control
800000FFh
RO, R/W
01A-01Bh
DMIVC0RSTS
DMI VC0 Resource Status
0002h
RO
01C-01Fh
DMIVC1RCAP
DMI VC1 Resource Capability
00010001h
RO
020-023h
DMIVC1RCTL1
DMI VC1 Resource Control
01000000h
RO, R/W
0002h
RO
00002689h
RO
018-019h
Reserved
024-025h
026-027h
Reserved
DMIVC1RSTS
DMI VC1 Resource Status
028-03Fh
Reserved
040-083h
Reserved
084-087h
DMILCAP
DMI Link Capabilities
088-089h
DMILCTL
DMI Link Control
0000h
RO, R/W
08A-08Bh
DMILSTS
DMI Link Status
0001h
RO
08C-FFFh
130
Register Name
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.4.2
DMIVCECH—DMI Virtual Channel Enhanced Capability Header
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
DMIBAR
000h
04010002h
RO
32 bits
Indicates DMI Virtual Channel capabilities.
Bit
31:20
Access &
Default
Description
RO
Pointer to Next Capability This field contains the offset to the next item in the list.
040 h
19:16
15:0
RO
PCI Express Virtual Channel Capability Version
1h
This field indicate compliances with the version 1 capability.
RO
Extended Capability ID
0002 h
5.4.3
Value of 0002 h indicates this is the Virtual Channel capability item.
DMIPVCCAP1—DMI Port VC Capability Register 1
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
DMIBAR
004h
00000001h
RO, R/WO
32 bits
Describes the configuration of PCI Express Virtual Channels associated with this port.
Bit
Access &
Default
31:7
11:10
9:8
Reserved
00 b
RO
Port Arbitration Table Entry Size (PATS): This field indicates the size of the port
arbitration table is 4 bits (to allow up to 8 ports)
RO
Reference Clock (RC)
00 b
Fixed at 10ns.
7
6:4
Reserved
RO
000 b
3
Description
RO
Low Priority Extended VC Count
Indicates that there are no additional VCs of low priority with extended capabilities.
Reserved
0b
2:0
R/WO
Extended VC Count
001 b
Indicates the number of (extended) Virtual Channels in addition to the default VC
supported by the device.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
131
Device #0 Memory Mapped I/O Register
R
5.4.4
DMIPVCCAP2—DMI Port VC Capability Register 2
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
DMIBAR
008h
00000001h
RO
32 bits
Describes the configuration of PCI Express Virtual Channels associated with this port.
Bit
31:24
Access &
Default
RO
00 h
23:8
7:0
VC Arbitration Table Offset (ATO)
Indicates that no table is present for VC arbitration since it is fixed.
Reserved
RO
01 h
5.4.5
Description
VC Arbitration Capability
Indicates that the VC arbitration is fixed in the root complex.
VC1 is the highest priority and VC0 is the lowest priority.
DMIPVCCTL—DMI Port VC Control
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
0
132
Description
Reserved
15:4
3:1
DMIBAR
00Ch
0000h
RO, R/W
16 bits
R/W
VC Arbitration Select
000 b
Indicates which VC should be programmed in the VC arbitration table. The root
complex takes no action on the setting of this field since there is no arbitration table.
RO
Load VC Arbitration Table (LAT)
0b
Indicates that the table programmed should be loaded into the VC arbitration table.
This bit is defined as read/write with always returning 0 on reads.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.4.6
DMIVC0RCAP—DMI VC0 Resource Capability
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
Bit
31:24
DMIBAR
010h
00000001h
RO
32 bits
Access &
Default
Description
RO
Port Arbitration Table Offset (AT)
00 h
This VC implements no port arbitration table since the arbitration is fixed.
23
Reserved
22:16
RO
00 h
15
RO
0b
14
Reject Snoop Transactions
This VC must be able to take snoopable transactions.
RO
Advanced Packet Switching (APS):
0h
This VC is capable of all transactions, not just advanced packet switching
transactions.
Reserved
13:8
7:0
Maximum Time Slots (MTS)
This VC implements fixed arbitration, and therefore this field is not used.
RO
Port Arbitration Capability
01 h
Having only bit 0 set indicates that the only supported arbitration scheme for this VC is
non-configurable hardware-fixed.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
133
Device #0 Memory Mapped I/O Register
R
5.4.7
DMIVC0RCTL0—DMI VC0 Resource Control
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
DMIBAR
014h
800000FFh
RO, R/W
32 bits
Controls the resources associated with PCI Express Virtual Channel 0.
Bit
Access &
Default
31
RO
Virtual Channel 0 Enable
1b
Enables the VC when set. Disables the VC when cleared.
30:27
26:24
Reserved
RO
000 b
23:20
19:17
16
Indicates the ID used for this virtual channel
R/W
Port Arbitration Select
0h
Indicates which port table is being programmed. The root complex takes no action
on this setting since the arbitration is fixed and there is no arbitration for this virtual
channel
RO
Load Port Arbitration Table (LAT):
0b
The root complex does not implement an arbitration table for this virtual channel.
Reserved
R/W
1111111
b
0
5.4.8
Virtual Channel 0 ID
Reserved
15:8
7:1
Description
Transaction Class / Virtual Channel Map (TVM)
This field indicates which transaction classes are mapped to this virtual channel.
When a bit is set, this transaction class is mapped to the virtual channel.
Reserved
DMIVC0RSTS—DMI VC0 Resource Status
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
DMIBAR
01Ah
0002h
RO
16 bits
Reports the Virtual Channel specific status.
Bit
Access &
Default
Reserved
15:2
1
RO
1b
0
RO
0b
134
Description
VC Negotiation Pending:
0: The VC negotiation is complete.
1: The VC resource is still in the process of negotiation (initialization or disabling).
Port Arbitration Tables Status (ATS):
There is no port arbitration table for this VC, so this bit is reserved at 0.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.4.9
DMIVC1RCAP—DMI VC1 Resource Capability
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
Bit
31:24
Access &
Default
Description
RO
Port Arbitration Table Offset (AT)
00 h
Indicates the location of the port arbitration table in the root complex. A value of 3h
indicates the table is at offset 30h.
23
Reserved
22:16
15
14
RO
Maximum Time Slots (MTS)
00 h
This value is updated by platform BIOS based upon the determination of the
number of time slots available in the platform.
RO
Reject Snoop Transactions (RTS):
1b
All snoopable transactions on VC1 are rejected. This VC is for isochronous
transfers only.
RO
Advanced Packet Switching (APS)
0b
This VC is capable of all transactions, not just advanced packet switching
transactions.
13:8
7:0
5.4.10
DMIBAR
01Ch
00010001h
RO
32 bits
Reserved
RO
Port Arbitration Capability
01 h
This field indicates the port arbitration capability is time-based WRR of 128 phases.
DMIVC1RCTL1—DMI VC1 Resource Control
MMIO Range:
DMIBAR
Address Offset:
020h
Default Value:
01000000h
Access:
RO, R/W
Size:
32 bits
Controls the resources associated with PCI Express Virtual Channel 1.
Bit
Access &
Default
Description
31
R/W
Virtual Channel 1 Enable
0b
0: Virtual Channel is disabled.
1: Virtual Channel is enabled.
30:27
26:24
Reserved
R/W
Virtual Channel 1 ID
001 b
Assigns a VC ID to the VC resource. This field can not be modified when the
VC is already enabled.
Reserved
23:20
19:17
R/W
Port Arbitration Select
000 b
This field indicates which port table is being programmed. The only permissible
value of this field is 4h for the time-based WRR entries.
Reserved
16:8
7:1
R/W
00h
0
Transaction Class / Virtual Channel Map (TVM)
The Field indicates which transaction classes are mapped to this virtual channel.
When a bit is set, this transaction class is mapped to the virtual channel.
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
135
Device #0 Memory Mapped I/O Register
R
5.4.11
DMIVC1RSTS—DMI VC1 Resource Status
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
DMIBAR
026h
0002h
RO
16 bits
Reports the Virtual Channel specific status
Bit
Access &
Default
15:2
1
Description
Reserved
RO
VC1 Negotiation Pending
1b
0: The VC negotiation is complete.
1: The VC resource is still in the process of negotiation (initialization or disabling).
0
5.4.12
Reserved
DMILCAP—DMI Link Capabilities
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
DMIBAR
084h
00012C41h
RO, R/WO
32 bits
Indicates DMI specific capabilities.
Bit
Access &
Default
31:18
Description
Reserved
17:15
R/WO
L1 Exit Latency
010 b
L1 not supported on DMI
14:12
R/WO
L0s Exit Latency
010 b
Indicates the length of time this Port requires to complete the transition from L0s to
L0. The value 010 b indicates the range of 128 ns to less than 256 ns.
11:10
RO
Active State Link PM Support (APMS)
11 b
This field indicates that L0s is supported on DMI.
Note: ICH6 does not support L1 entry on DMI interface
9:4
RO
000100 b
3:0
RO
0001 b
136
Max Link Width (MLW)
This field indicates the maximum link width is either x2 (2h) or X4. (4h)
Maximum Link Speed (MLS)
This field indicates the link speed is 2.5 Gb/s.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.4.13
DMILCTL—DMI Link Control
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
DMIBAR
088h
0000h
RO, R/W
16 bits
Allows control of DMI.
Bit
Access &
Default
15:8
RO
Description
Reserved
00 h
7
R/W
0h
6:2
00000 b
1:0
R/W
00 b
Extended Synch
0: Standard Fast Training Sequence (FTS).
1 = Forces extended transmission of FTS ordered sets when exiting L0s prior to
entering L0 and extra TS1 sequences at exit from L1 to entering L0.
Reserved
Active State PM
Controls the level of active state power management supported on the given link.
00: Disabled
01: L0s Entry Enabled
10: Reserved
11: Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
137
Device #0 Memory Mapped I/O Register
R
5.4.14
DMILSTS—DMI Link Status
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
DMIBAR
08Ah
0001h
RO
16 bits
Indicates DMI status.
Bit
Access &
Default
15:10
RO
Description
Reserved
000000 b
9:4
Negotiated Width
RO
Indicates negotiated link width
00 h
3:0
00h: Reserved
01h: Reserved
02h: X2
04h: X4
All other encodings are reserved.
Negotiated Speed
RO
Indicates negotiated link speed.
1h
1h:
2.5 Gb/s
All other encodings are reserved.
5.4.15
Egress Port (EP) RCRB
This Root Complex Register Block (RCRB) controls the port arbitration that is based on the PCI
Express 1.0 specification. Port arbitration is done for all PCI Express based isochronous requests
(always on Virtual Channel 1) before being submitted to the main memory arbiter. The base address of
this space is programmed in EPBAR in device #0 config space.
5.4.16
EP Register Summary
Address
Offset (h)
Register
Symbol
000-043h
044-047h
EPESD
EPLE1D
00000201h
RO, RWO
EP Link Entry 1 Description
01000000h
RO, R/WO
000…
RO, R/WO
02000002h
RO, R/WO
000…
RO
Reserved
EPLE1A
EP Link Entry 1 Address
060-063h
EPLE2D
EP Link Entry 2 Description
064-067h
138
EP Element Self Description
058-05Fh
070-FFFh
Access
Reserved
054-057h
068-06Fh
Default Value
Reserved
048-04Fh
050-053h
Register Name
Reserved
EPLE2A
EP Link Entry 2 Address
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
Figure 5-1. Link Declaration Topology
GMCH
x16
PEG
Port #2
Egress Port
Port #0
DMI
Port #1
x4
ICH6-M
Egress Port
Port #0
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
139
Device #0 Memory Mapped I/O Register
R
5.4.17
EPESD—EP Element Self Description
MMIO Range:
EPBAR
Address Offset:
044h
Default Value:
00000201h
Access:
RO, R/WO
Size:
32 bits
Provides information about the root complex element containing this Link Declaration Capability.
Bit
Access &
Default
31:24
RO
00 h
23:16
R/WO
00 h
15:8
RO
02 h
7:0
5.4.18
Description
Port Number. –
This field specifies the port number associated with this element with respect to the
component that contains this element.
Value of 00 h indicates to configuration software that this is the default egress port.
Component ID –
Identifies the physical component that contains this Root Complex Element.
Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
Number of Link Entries –
Indicates the number of link entries following the Element Self Description. This
field reports 2 (one each for PCI Express* Based Graphics and DMI).
Reserved
EPLE1D—EP Link Entry 1 Description
MMIO Range:
EPBAR
Address Offset:
050h
Default Value:
01000000h
Access:
RO, R/WO
Size:
32 bits
First part of a Link Entry which declares an internal link to another Root Complex Element.
Bit
Access &
Default
31:24
RO
01 h
23:16
R/WO
00 h
Description
Target Port Number –
Specifies the port number associated with the element targeted by this link entry
(DMI). The target port number is with respect to the component that contains this
element as specified by the target component ID.
Target Component ID –
Identifies the physical or logical component that is targeted by this link entry. A
value of 0 is reserved; Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
Reserved
15:2
1
0
RO
Link Type –
0b
Indicates that the link points to memory-mapped space (for RCRB). The link
address specifies the 64-bit base address of the target RCRB.
R/WO
0b
140
Link Valid
0: Link Entry is not valid and will be ignored.
1: Link Entry specifies a valid link.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
5.4.19
EPLE1A—EP Link Entry 1 Address
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
EPBAR
058h
0000000000000000h
RO, R/WO
64 bits
Second part of a Link Entry which declares an internal link to another Root Complex Element.
Bit
Access &
Default
Reserved
63:32
31:12
R/WO
0 0000 h
Link Address
Memory mapped base address of the RCRB that is the target element (DMI) for
this link entry.
Reserved
11:0
5.4.20
Description
EPLE2D—EP Link Entry 2 Description
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
EPBAR
060h
0200002h
RO, R/WO
32 bits
First part of a Link Entry which declares an internal link to another Root Complex Element.
Bit
Access &
Default
Description
31:24
RO
02 h
23:16
R/WO
00 h
Target Port Number
Specifies the port number associated with the element targeted by this link entry (PEG). The
target port number is with respect to the component that contains this element as specified
by the target component ID.
Target Component ID
Identifies the physical or logical component that is targeted by this link entry. A value of 0 is
reserved; Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it will be
reflected everywhere that it is mirrored.
Reserved
Link Type
Indicates that the link points to configuration space of the integrated device which controls
the x16 root port. The link address specifies the configuration address (segment, bus,
device, function) of the target root port.
15:2
1
0
RO
1b
R/WO
0b
Link Valid
0: Link Entry is not valid and will be ignored.
1: Link Entry specifies a valid link.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
141
Device #0 Memory Mapped I/O Register
R
5.4.21
E2A—EP Link Entry 2 Address
MMIO Range:
Address Offset:
Default Value:
Access:
Size:
EPBAR
068h
0000000000008000h
RO
64 bits
Second part of a Link Entry which declares an internal link to another Root Complex Element.
Bit
Access &
Default
Reserved
63:28
27:20
Description
Bus Number
RO
00 h
19:15
Device Number
RO
0 0001 b
14:12
RO
Target for this link is PCI Express x16 port (Device 1).
Function Number
000 b
11:0
Reserved
§
142
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Device #0 Memory Mapped I/O Register
R
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
143
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6
PCI Express Graphics Device 1
Configuration Registers (D1:F0)
Note:
Excludes Mobile Intel® 915GMS, 910GML and 910GMLE Express Chipsets.
Device #1 contains the controls associated with the x16 root port that is the intended attach point for
external graphics. It is typically referred to as PEG (PCI Express Graphics) port. It also functions as
the virtual PCI-to-PCI Bridge that was previously associated with AGP.
Warning: When reading the PCI Express "conceptual" registers such as this, you may not get a valid value unless
the register value is stable.
The PCI Express Specification defines two types of reserved bits:
• Reserved and Preserved: Reserved for future RW implementations; software must preserve value
read for writes to bits.
• Reserved and Zero: Reserved for future R/WC/S implementations; software must use 0 for writes
to bits.
Unless explicitly documented as Reserved and Zero, all bits marked as Reserved are part of the
Reserved and Preserved type which has historically been the typical definition for Reserved.
Most (if not all) control bits in this device cannot be modified unless the link is down. Software is
required to first disable the link, then program the registers, then re-enable the link (which will cause a
full-retrain with the new settings).
Note: Register information for the PCI Express Based x16 Graphics Port is NOT relative to the
Mobile Intel® 82915GMS, 82910GML and 82910GMLE Express Chipsets.
Note: Register information for the Integrated Graphics Device is NOT relative to the Mobile Intel
82915PM Express Chipset.
144
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.1
PEG Device 1 Configuration Register Summary
Table 6-1. PCI Express Graphics Port Configuration Register Summary
Register
Offset (h)
00-01h
Register
Symbol
VID1
Register Name
Access
Default Value
Vendor Identification
8086h
RO
RO
02-03h
DID1
Device Identification
2591h
04-05h
PCICMD1
PCI Command
0000h
RO, R/W
06-07h
PCISTS1
PCI Status
0010h
RO, R/WC
08h
RID1
Revision Identification
00h
RO
09-0Bh
CC1
Class Code
060400h
RO
0Ch
CL1
Cache Line Size
00h
R/W
01h
RO
00h
RO
0Dh
0Eh
Reserved
HDR1
0F-17h
18h
Header Type
Reserved
PBUSN1
Primary Bus Number
19h
SBUSN1
Secondary Bus Number
00h
R/W
1Ah
SUBUSN1
Subordinate Bus Number
00h
R/W
1Ch
IOBASE1
I/O Base Address
F0h
RO,R/W
1Dh
IOLIMIT1
I/O Limit Address
00h
RO, R/W
1E-1Fh
SSTS1
Secondary Status
0000h
RO, R/WC
20-21h
MBASE1
Memory Base Address
FFF0h
RO, R/W
22-23h
MLIMIT1
Memory Limit Address
0000h
RO, R/W
24-25h
PMBASE1
Prefetchable Memory Base
Address
FFF0h
RO, R/W
26-27h
PMLIMIT1
Prefetchable Memory Limit
Address
0000h
RO, R/W
88h
RO
1Bh
Reserved
28-33h
34h
Reserved
CAPPTR1
35-3Bh
Capabilities Pointer
Reserved
3Ch
INTRLINE1
Interrupt Line
00h
R/W
3Dh
INTRPIN1
Interrupt Pin
01h
RO
3E-3Fh
BCTRL1
Bridge Control
0000h
RO, R/W
40-7Fh
Reserved
80-83h
PM_CAP1
Power Management Capabilities
1902 / A001h
RO
84-87h
PM_CS1
Power Management
Control/Status
00000000h
RO, R/W/S
88-8Bh
SS_CAPID
Subsystem ID and Vendor ID
Capabilities
0000800Dh
RO
8C-8Fh
SS
Subsystem ID and Subsystem
Vendor ID
00008086h
R/WO
90-91h
MSI_CAPID
Message Signaled Interrupts
Capability ID
A005h
RO
92-93h
MC
Message Control
0000h
RO, R/W
94-97h
MA
Message Address
0000000h
RO, R/W
98-99h
MD
Message Data
0000h
R/W
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
145
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
Register
Offset (h)
Register
Symbol
9A-9Fh
Access
Default Value
Reserved
A0-A1h
PEG_CAPL
PCI Express Capability List
0010h
RO
A2-A3h
PEG_CAP
A4-A7h
DCAP
PCI Express Capabilities
0141h
RO
Device Capabilities
00000000h
A8-A9h
RO
DCTL
Device Control
0000h
RO, R/W
AA-ABh
DSTS
Device Status
0000h
RO, R/WC
AC-AFh
LCAP
Link Capabilities
02012801h
RO, R/WO
B0-B1h
LCTL
Link Control
0000h
RO, R/W
B2-B3h
LSTS
Link Status
1001h
RO
B4-B7H
SLOTCAP
Slot Capabilities
00000000h
RO, R/WO
B8-B9h
SLOTCTL
Slot Control
01C0h
RO, R/W
BA-BBh
SLOTSTS
Slot Status
0000h
RO, R/WC
BC-BDh
RCTL
Root Control
0000h
RO, R/W
00000000h
RO, R/W/C
BE-BFh
C0-C3h
Reserved
RSTS
Root Status
C4-FFh
Reserved
100-103h
VCECH
Virtual Channel Enhanced
Capability Header
14010002h
RO
104-107h
PVCCAP1
Port VC Capability Register 1
00000001h
RO, R/WO
108-10Bh
PVCCAP2
Port VC Capability Register 2
00000000h
RO
10C-10Dh
PVCCTL
Port VC Control
0000h
RO, R/W
10E-10Fh
Reserved
110-113h
VC0RCAP
VC0 Resource Capability
00000000h
RO
114-117h
VC0RCTL
VC0 Resource Control
800000FFh
FO, R/W
11A-11Bh
VC0RSTS
VC0 Resource Status
0000h
RO
11C-11Fh
VC1RCAP
VC1 Resource Capability
00008000h
RO
120-123h
VC1RCTL
VC1 Resource Control
01000000h
RO, R/W
0000h
RO
Root Complex Link Declaration
Enhanced Capability Header
00010005h
RO
Element Self Description
02000100h
RO, R/WO
00000000h
RO, R/WO
00000000000000
00h
RO, R/WO
0000000000000F
FFh
RO
118-119h
Reserved
124-125h
126-127h
Reserved
VC1RSTS
128-13Fh
140-143h
RCLDECH
144-147h
ESD
150-153h
Reserved
LE1D
Link Entry 1 Description
154-157h
158-15Fh
Reserved
LE1A
Link Entry 1 Address
160-217h
218-21Fh
220-2FFh
VC1 Resource Status
Reserved
148-14Fh
146
Register Name
Reserved
PEGSSTS
PCI Express Graphics Sequence
Status
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2
PEG Device 1 Configuration Register Details
6.2.1
VID1—Vendor Identification
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
00h
8086h
RO
16 bits
This register combined with the Device Identification register uniquely identifies any PCI device.
Bit
Access &
Default
15:0
RO
8086 h
6.2.2
Description
Vendor Identification (VID1)
PCI standard identification for Intel.
DID1—Device Identification
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
02h
2591h
RO
16 bits
This register combined with the Vendor Identification register uniquely identifies any PCI device.
Bit
Access &
Default
15:0
RO
2591h
Description
Device Identification Number (DID1)
Identifier assigned to the GMCH device #1 (virtual PCI-to-PCI bridge, PCI Express
Graphics port). .
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
147
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.3
PCICMD1—PCI Command
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
Description
Reserved.
15:11
10
1
04h
0000h
RO, R/W
16 bits
R/W
0b
INTA Assertion Disable
0: This device is permitted to generate INTA interrupt messages.
1: This device is prevented from generating interrupt messages.
Any INTA emulation interrupts already asserted must be deasserted when this bit
is set.
Only affects interrupts generated by the device (PCI INTA from a PME or Hot
Plug event) controlled by this command register. It does not affect upstream
MSI’s, upstream PCI INTA-INTD assert and deassert messages.
9
RO
0b
8
R/W
0b
Fast Back-to-Back Enable (FB2B)
Not Applicable or Implemented. Hardwired to 0.
SERR Message Enable (SERRE1)
This bit is an enable bit for Device #1 SERR messaging. The GMCH
communicates the SERRB condition by sending an SERR message to the ICH.
This bit, when set, enables reporting of non-fatal and fatal errors to the Root
Complex. Note that errors are reported if enabled either through this bit or
through the PCI-Express specific bits in the Device Control Register
0: The SERR message is generated by the GMCH for Device #1 only under
conditions enabled individually through the Device Control Register.
1: The GMCH is enabled to generate SERR messages which will be sent to the
ICH for specific Device #1 error conditions that are individually enabled in the
BCTRL1 register and for all non-fatal and fatal errors generated on the primary
side of the virtual PCI to PCI-Express bridge (not those received by the
secondary side). The error status is reported in the PCISTS1 register.
Reserved.
7
6
R/WO
0b
Parity Error Enable (PERRE)
Controls whether or not the Master Data Parity Error bit in the PCI Status register
can bet set.
0: Master Data Parity Error bit in PCI Status register cannot be set.
1: Master Data Parity Error bit in PCI Status register can be set.
5
RO
0b
4
RO
0b
3
RO
0b
148
VGA Palette Snoop
Not Applicable or Implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE)
Not Applicable or Implemented. Hardwired to 0.
Special Cycle Enable (SCE)
Not Applicable or Implemented. Hardwired to 0.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
Bit
Access &
Default
Description
2
R/W
Bus Master Enable (BME)
0b
0: This device is prevented from making memory or IO requests to its primary
bus.
Note that according to PCI Specification, as MSI interrupt messages are in-band
memory writes, disabling the bus master enable bit prevents this device from
generating MSI interrupt messages or passing them from its secondary bus to its
primary bus. Upstream memory writes/reads, IO writes/reads, peer writes/reads,
and MSI's will all be treated as illegal cycles. Writes are forwarded to memory
address 0 with byte enables deasserted. Reads will be forwarded to memory
address 0 and will return Unsupported Request status (or Master abort) in its
completion packet.
1: This device is allowed to issue requests to its primary bus. Completions for
previously issued memory read requests on the primary bus will be issued when
the data is available.
This bit does not affect forwarding of Completions from the primary interface to
the secondary interface.
1
R/W
0b
0
R/W
0b
Memory Access Enable (MAE)
0: All of device #1’s memory space is disabled.
1: Enable the Memory and Pre-fetchable memory address ranges defined in the
MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.
IO Access Enable (IOAE)
0: All of device #1’s I/O space is disabled.
1: Enable the I/O address range defined in the IOBASE1, and IOLIMIT1
registers.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
149
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.4
PCISTS1—PCI Status
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
06h
0010h
RO, R/WC
16 bits
This register reports the occurrence of error conditions associated with primary side of the “virtual”
Host-PCI Express bridge embedded within the GMCH.
Bit
Access &
Default
Description
15
RO
0b
14
R/WC
0b
13
RO
0b
12
RO
0b
11
RO
0b
10:9
RO
00 b
8
RO
0b
7
RO
0b
Detected Parity Error (DPE)
Hardwired to 0. Parity (generating poisoned TLPs) is not supported on the
primary side of this device.
Signaled System Error (SSE)
This bit is set when this Device sends an SERR due to detecting an ERR_FATAL
or ERR_NONFATAL condition and the SERR Enable bit in the Command
register is 1. Both received (if enabled by BCTRL1[1]) and internally detected
error messages do not affect this field.
Received Master Abort Status (RMAS)
Not Applicable or Implemented. Hardwired to 0. The concept of a master abort
does not exist on primary side of this device.
Received Target Abort Status (RTAS)
Not Applicable or Implemented. Hardwired to 0. The concept of a target abort
does not exist on primary side of this device.
Signaled Target Abort Status (STAS)
Not Applicable or Implemented. Hardwired to 0. The concept of a target abort
does not exist on primary side of this device.
DEVSELB Timing (DEVT)
This device is not the subtractively decoded device on bus 0. This bit field is
therefore hardwired to 00 to indicate that the device uses the fastest possible
decode.
Master Data Parity Error (PMDPE)
Because the primary side of the PCI Express* x16 Graphics Interface’s virtual
P2P bridge is integrated with the MCH functionality there is no scenario where
this bit will get set. Because hardware will never set this bit, it is impossible for
software to have an opportunity to clear this bit or otherwise test that it is
implemented. The PCI specification defines it as a R/WC, but for our
implementation an RO definition behaves the same way and will meet all
Microsoft testing requirements.
This bit can only be set when the Parity Error Enable bit in the PCI Command
register is set.
Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hardwired to 0.
Reserved.
66/60 MHz capability (CAP66)
Not Applicable or Implemented. Hardwired to 0.
Capabilities List
Indicates that a capabilities list is present. Hardwired to 1.
INTA Status
Indicates that an interrupt message is pending internally to the device. Only
PME and Hot Plug sources feed into this status bit (not PCI INTA-INTD assert
and deassert messages). The INTA Assertion Disable bit, PCICMD1[10], has no
effect on this bit.
Reserved.
6
5
4
3
2:0
150
RO
0b
RO
1b
RO
0b
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.5
RID1—Revision Identification
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
08h
00h
RO
8 bits
This register contains the revision number of the GMCH device #1. These bits are read only and writes
to this register have no effect.
Bit
7:0
6.2.6
Access &
Default
Description
RO
Revision Identification Number (RID1)
00 h
Indicates the number of times that this device in this component has been
“stepped” through the manufacturing process. It is always the same as the RID
values in all other devices in this component.
CC1—Class Code
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
09h
060400h
RO
24 bits
This register identifies the basic function of the device, a more specific sub-class, and a registerspecific programming interface.
Bit
23:16
15:8
7:0
Access &
Default
Description
RO
Base Class Code (BCC)
06 h
Indicates the base class code for this device. This code has the value 06h,
indicating a Bridge device.
RO
Sub-Class Code (SUBCC)
04 h
Indicates the sub-class code for this device. The code is 04h indicating a PCI to
PCI Bridge.
RO
Programming Interface (PI)
00 h
Indicates the programming interface of this device. This value does not specify a
particular register set layout and provides no practical use for this device.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
151
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.7
CL1—Cache Line Size
PCI Device:
Address Offset:
Default Value:
Access:
Size:
6.2.8
1
0Ch
00h
R/W
8 bits
Bit
Access &
Default
Description
7:0
R/W
Cache Line Size (Scratch pad)
00 h
Implemented by PCI Express devices as a read-write field for legacy compatibility
purposes but has no impact on any PCI Express device functionality.
HDR1—Header Type
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
0Eh
01h
RO
8 bits
This register identifies the header layout of the configuration space. No physical register exists at this
location.
Bit
Access &
Default
7:0
RO
01 h
6.2.9
Description
Header Type Register (HDR)
Returns 01 to indicate that this is a single function device with bridge header layout.
PBUSN1—Primary Bus Number
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
18h
00h
RO
8 bits
This register identifies that this “virtual” Host-PCI Express bridge is connected to PCI bus #0.
Bit
Access &
Default
7:0
RO
00 h
152
Description
Primary Bus Number (BUSN)
Configuration software typically programs this field with the number of the bus on
the primary side of the bridge. Since device #1 is an internal device and its primary
bus is always 0, these bits are read only and are hardwired to 0.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.10
SBUSN1—Secondary Bus Number
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
19h
00h
R/W
8 bits
This register identifies the bus number assigned to the second bus side of the “virtual” bridge i.e. to
PCI Express Graphics. This number is programmed by the PCI configuration software to allow
mapping of configuration cycles to PCI Express Graphics.
6.2.11
Bit
Access &
Default
Description
7:0
R/W
Secondary Bus Number (BUSN)
00 h
This field is programmed by configuration software with the bus number assigned to
PCI Express Graphics.
SUBUSN1—Subordinate Bus Number
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
1Ah
00h
R/W
8 bits
This register identifies the subordinate bus (if any) that resides at the level below PCI Express
Graphics. This number is programmed by the PCI configuration software to allow mapping of
configuration cycles to PCI Express Graphics.
Bit
Access &
Default
7:0
R/W
00 h
Description
Subordinate Bus Number (BUSN)
This register is programmed by configuration software with the number of the
highest subordinate bus that lies behind the device #1 bridge. When only a single
PCI device resides on the PCI Express Graphics segment, this register will contain
the same value as the SBUSN1 register.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
153
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.12
IOBASE1—I/O Base Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
1Ch
F0h
RO, R/W
8 bits
This register controls the CPU to PCI Express Graphics I/O access routing based on the following
formula:
IO_BASE=< address =<IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are treated
as 0. Thus the bottom of the defined I/O address range will be aligned to a 4-kB boundary.
Bit
Access &
Default
7:4
R/W
Fh
3:0
RO
Description
I/O Address Base (IOBASE)
Corresponds to A[15:12] of the I/O addresses passed by bridge 1 to PCI
Express-Graphics interface. BIOS must not set this register to 00h otherwise
0CF8h/0CFCh accesses will be forwarded to the PCI Express hierarchy
associated with this device.
Reserved.
0h
6.2.13
IOLIMIT1—I/O Limit Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
1Dh
00h
RO, R/W
8 bits
This register controls the CPU to PCI Express Graphics I/O access routing based on the following
formula:
IO_BASE=< address =<IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits A[11:0] are
assumed to be FFFh. Thus, the top of the defined I/O address range will be at the top of a 4-kB aligned
address block.
Bit
Access &
Default
7:4
R/W
0h
3:0
RO
Description
I/O Address Limit (IOLIMIT)
Corresponds to A[15:12] of the I/O address limit of device #1. Devices between this
upper limit and IOBASE1 will be passed to the PCI Express hierarchy associated
with this device.
Reserved.
0h
154
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.14
SSTS1—Secondary Status
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
1Eh
0000h
RO, R/WC
16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with
secondary side (i.e. PCI Express Graphics side) of the “virtual” PCI-PCI Bridge embedded within
GMCH.
Bit
Access &
Default
Reserved.
15
14
R/WC
0b
13
R/WC
0b
12
R/WC
0b
11
RO
0b
10:9
RO
00 b
Received System Error (RSE)
This bit is set when the secondary side sends an ERR_FATAL or ERR_NONFATAL
message due to an error detected by the secondary side, and the SERR Enable bit
in the Bridge Control register is 1.
Received Master Abort (RMA)
This bit is set when the Secondary Side for Type 1 Configuration Space Header
Device (for requests initiated by the Type 1 Header Device itself) receives a
Completion with Unsupported Request Completion Status.
Received Target Abort (RTA)
This bit is set when the Secondary Side for Type 1 Configuration Space Header
Device (for requests initiated by the Type 1 Header Device itself) receives a
Completion with Completer Abort Completion Status.
Signaled Target Abort (STA)
Not Applicable or Implemented. Hardwired to 0. The GMCH does not generate
Target Aborts (the GMCH will never complete a request using the Completer Abort
Completion status).
DEVSELB Timing (DEVT)
Not Applicable or Implemented. Hardwired to 0.
Reserved
8
7
Description
RO
Fast Back-to-Back (FB2B) Hardwired to 0.
0b
Reserved.
6
5
RO
66/60 MHz capability (CAP66) Hardwired to 0.
0b
4:0
Reserved.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
155
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.15
MBASE1—Memory Base Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
20h
FFF0h
RO, R/W
16 bits
This register controls the CPU to PCI Express Graphics non-prefetchable memory access routing based
on the following formula:
MEMORY_BASE=< address =<MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32 bit address. The bottom 4 bits of this register are read-only and return zeroes when read. This
register must be initialized by the configuration software. For the purpose of address decode address
bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be
aligned to a 1-MB boundary.
Bit
Access &
Default
15:4
R/W
FFF h
3:0
RO
Description
Memory Address Base (MBASE)
Corresponds to A[31:20] of the lower limit of the memory range that will be passed
to PCI Express Graphics.
Reserved.
0h
156
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.16
MLIMIT1—Memory Limit Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
22h
0000h
RO, R/W
16 bits
This register controls the CPU to PCI Express Graphics non-prefetchable memory access routing based
on the following formula:
MEMORY_BASE=< address =<MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of
the 32 bit address. The bottom 4 bits of this register are read-only and return zeroes when read. This
register must be initialized by the configuration software. For the purpose of address decode address
bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at
the top of a 1MB aligned memory block.
Note: Memory range covered by MBASE and MLIMIT registers are used to map non-prefetchable
PCI Express Graphics address ranges (typically where control/status memory-mapped I/O data
structures of the graphics controller will reside) and PMBASE and PMLIMIT are used to map
prefetchable address ranges (typically graphics local memory). This segregation allows application of
USWC space attribute to be performed in a true plug-and-play manner to the prefetchable address
range for improved CPU-PCI Express memory access performance.
Note also that configuration software is responsible for programming all address range registers
(prefetchable, non-prefetchable) with the values that provide exclusive address ranges i.e. prevent
overlap with each other and/or with the ranges covered with the main memory. There is no provision in
the GMCH hardware to enforce prevention of overlap and operations of the system in the case of
overlap are not guaranteed.
Bit
15:4
3:0
Access &
Default
Description
R/W
Memory Address Limit (MLIMIT)
000 h
Corresponds to A[31:20] of the upper limit of the address range passed to PCI
Express Graphics.
RO
Reserved
0h
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
157
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.17
PMBASE1—Prefetchable Memory Base Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
24h
FFF0h
RO, R/W
16 bits
This register in conjunction with the corresponding Upper Base Address register controls the CPU to
PCI Express Graphics prefetchable memory access routing based on the following formula:
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit
address. The lower 8 bits of the Upper Base Address register are read/write and correspond to address
bits A[39:32] of the 40-bit address. This register must be initialized by the configuration software. For
the purpose of address decode address bits A[19:0] are assumed to be 0. Thus, the bottom of the
defined memory address range will be aligned to a 1-MB boundary.
Bit
15:4
Access &
Default
R/W
FFF h
3:0
158
Description
Prefetchable Memory Base Address (MBASE)
Corresponds to A[31:20] of the lower limit of the memory range that will be passed
to PCI Express Graphics.
RO
64-bit Address Support
0h
Indicates the bridge supports only 32 bit addresses.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.18
PMLIMIT1—Prefetchable Memory Limit Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
26h
0000h
RO, R/W
16 bits
This register in conjunction with the corresponding Upper Limit Address register controls the CPU to
PCI Express Graphics prefetchable memory access routing based on the following formula:
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits A[31:20] of the 40-bit
address. The lower 8 bits of the Upper Limit Address register are read/write and correspond to address
bits A[39:32] of the 40-bit address. This register must be initialized by the configuration software. For
the purpose of address decode address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the
defined memory address range will be at the top of a 1-MB aligned memory block. Note that
prefetchable memory range is supported to allow segregation by the configuration software between
the memory ranges that must be defined as UC and the ones that can be designated as a USWC (i.e.
prefetchable) from the CPU perspective.
Bit
15:4
3:0
6.2.19
Access &
Default
Description
R/W
Prefetchable Memory Address Limit (PMLIMIT)
000 h
Corresponds to A[31:20] of the upper limit of the address range passed to PCI
Express Graphics.
RO
64-bit Address Support
0h
Indicates the bridge supports only 32 bit addresses.
CAPPTR1—Capabilities Pointer
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
34h
88h
RO
8 bits
The capabilities pointer provides the address offset to the location of the first entry in this device’s
linked list of capabilities.
Bit
Access &
Default
7:0
RO
88h
Description
First Capability (CAPPTR1)
The first capability in the list is the Subsystem ID and Subsystem Vendor ID Capability.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
159
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.20
INTRLINE1—Interrupt Line
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
3Ch
00h
R/W
8 bits
This register contains interrupt line routing information. The device itself does not use this value, rather
it is used by device drivers and operating systems to determine priority and vector information.
Bit
7:0
6.2.21
Access &
Default
Description
R/W
Interrupt Connection.
00 h
Used to communicate interrupt line routing information. POST software writes the
routing information into this register as it initializes and configures the system. The
value in this register indicates which input of the system interrupt controller this
device’s interrupt pin is connected to.
INTRPIN1—Interrupt Pin
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
3Dh
01h
RO
8 bits
This register specifies which interrupt pin this device uses.
Bit
7:0
160
Access &
Default
Description
RO
Interrupt Pin.
01 h
As a single function device, the PCI Express device specifies INTA as its interrupt
pin.
01h=INTA.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.22
BCTRL1—Bridge Control
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
3Eh
0000h
RO, R/W
16 bits
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI bridges. The
BCTRL provides additional control for the secondary interface (i.e. PCI Express Graphics) as well as
some bits that affect the overall behavior of the “virtual” Host-PCI Express bridge embedded within
GMCH, e.g. VGA compatible address ranges mapping.
Bit
Access &
Default
15:12
RO
0h
RO
0b
RO
0b
RO
0b
RO
0b
RO
0b
R/W
0b
11
10
9
8
7
6
5
RO
0b
4
R/W
0b
3
R/W
0b
Description
Reserved
Discard Timer SERR Enable
Not Applicable or Implemented. Hardwired to 0.
Discard Timer Status
Not Applicable or Implemented. Hardwired to 0.
Secondary Discard Timer
Not Applicable or Implemented. Hardwired to 0.
Primary Discard Timer
Not Applicable or Implemented. Hardwired to 0.
Fast Back-to-Back Enable (FB2BEN)
Not Applicable or Implemented. Hardwired to 0.
Secondary Bus Reset (SRESET)
Setting this bit triggers a hot reset on the corresponding PCI Express Port. This
will force the LTSSM to transition to the Hot Reset state (via Recovery) from L0,
L0s, or L1 states
Master Abort Mode (MAMODE)
When acting as a master, unclaimed reads that experience a master abort
returns all 1’s and any writes that experience a master abort completes normally
and the data is thrown away. Hardwired to 0.
VGA 16-bit Decode
Enables the PCI-to-PCI bridge to provide 16-bit decoding of VGA I/O address
precluding the decoding of alias addresses every 1 KB. This bit only has
meaning if bit 3 (VGA Enable) of this register is also set to 1, enabling VGA I/O
decoding and forwarding by the bridge.
0 : Execute 10-bit address decodes on VGA I/O accesses.
1 : Execute 16-bit address decodes on VGA I/O accesses.
VGA Enable (VGAEN)
Controls the routing of CPU initiated transactions targeting VGA compatible I/O
and memory address ranges. See the VGAEN/MDAP table in device 0, offset
97h[0].
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
161
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
Bit
Access &
Default
Description
2
R/W
0b
1
R/W
0b
0
RO
ISA Enable (ISAEN)
Needed to exclude legacy resource decode to route ISA resources to legacy
decode path. Modifies the response by the GMCH to an I/O access issued by
the CPU that target ISA I/O addresses. This applies only to I/O addresses that
are enabled by the IOBASE and IOLIMIT registers.
0: All addresses defined by the IOBASE and IOLIMIT for CPU I/O transactions
will be mapped to PCI Express Graphics.
1: GMCH will not forward to PCI Express Graphics any I/O transactions
addressing the last 768 bytes in each 1KB block even if the addresses are within
the range defined by the IOBASE and IOLIMIT registers. Instead of going to PCI
Express Graphics these cycles will be forwarded to DMI where they can be
subtractively or positively claimed by the ISA bridge.
SERR Enable (SERREN)
0: No forwarding of error messages from secondary side to primary side that
could result in an SERR.
1: ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR
message when individually enabled by the Root Control register.
Parity Error Response Enable (PEREN)
0b
Controls whether or not the Master Data Parity Error bit in the Secondary Status
register is set when the MCH receives across the link (upstream) a Read Data
Completion Poisoned TLP
0: Master Data Parity Error bit in Secondary Status register cannot be set.
1: Master Data Parity Error bit in Secondary Status register can be set..
162
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.23
PM_CAPID1—Power Management Capabilities
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
31:27
RO
19 h
1
80h
1902A001
RO
32 bits
Description
PME Support
This field indicates the power states in which this device may indicate PME wake
via PCI Express messaging. D0, D3hot & D3cold. This device is not required to do
anything to support D3hot & D3cold, it simply must report that those states are
supported.
Refer to the PCI Power Management 1.1 specification for encoding explanation and
other power management details.
26
RO
0b
25
RO
0b
24:22
RO
000 b
21
20
Hardwired to 0 to indicate that special initialization of this device is NOT required
before generic class device driver is to use it.
RO
Auxiliary Power Source (APS)
RO
RO
RO
90h / A0h
7:0
Hardwired to 0 to indicate that there are no 3.3Vaux auxiliary current requirements.
0b
010 b
15:8
Auxiliary Current
Device Specific Initialization (DSI)
0b
18:16
D1 - Hardwired to 0 to indicate that the D1 power management state is NOT
supported.
RO
0b
19
D2 - Hardwired to 0 to indicate that the D2 power management state is NOT
supported.
Hardwired to 0.
PME Clock
Hardwired to 0 to indicate this device does NOT support PME# generation.
PCI PM CAP Version
Hardwired to 02h to indicate there are 4 bytes of power management registers
implemented and that this device complies with revision 1.1 of the PCI Power
Management Interface Specification.
Pointer to Next Capability
This contains a pointer to the next item in the capabilities list.
This contains a pointer to the next item in the capabilities list. If MSICH (CAPL[0]
@ 7Fh) is 0, then the next item in the capabilities list is the Message Signaled
Interrupts (MSI) capability at 90h. If MSICH (CAPL[0] @ 7Fh) is 1, then the next
item in the capabilities list is the PCI Express capability at A0h.
RO
Capability ID
01 h
Value of 01h identifies this linked list item (capability structure) as being for PCI
Power Management registers.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
163
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.24
PM_CS1—Power Management Control/Status
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
31:16
RO
1
84h
00000000h
RO, R/W/S
32 bits
Description
Reserved -
0000 h
15
RO
0b
14:13
RO
00 b
12:9
RO
0h
8
R/W/S
0b
PME Status
Indicates that this device does not support PME# generation from D3-cold.
Data Scale
Indicates that this device does not support the power management data register.
Data Select
Indicates that this device does not support the power management data register.
PME Enable
Indicates that this device does not generate PME# assertion from any D-state.
0: PME# generation not possible from any D State
1: PME# generation enabled from any D State
The setting of this bit has no effect on hardware.
See PM_CAP[15:11]
Reserved
7:2
1:0
R/W
00 b
Power State
Indicates the current power state of this device and can be used to set the device
into a new power state. If software attempts to write an unsupported state to this
field, write operation must complete normally on the bus, but the data is discarded
and no state change occurs.
00:
D0
01:
D1 (Not supported in this device.)
10:
D2 (Not supported in this device.)
11:
D3
Support of D3cold does not require any special action.
While in the D3hot state, this device can only act as the target of PCI
configuration transactions (for power management control). This device also
cannot generate interrupts or respond to MMR cycles in the D3 state. The
device must return to the D0 state in order to be fully-functional.
There is no hardware functionality required to support these Power States.
164
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.25
SS_CAPID—Subsystem ID and Vendor ID Capabilities
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
88h
0000800Dh
RO
32 bits
This capability is used to uniquely identify the subsystem where the PCI device resides. Because this
device is an integrated part of the system and not an add-in device, it is anticipated that this capability
will never be used. However, it is necessary because Microsoft will test for its presence.
Bit
Access &
Default
Reserved
31:16
15:8
7:0
Description
RO
Pointer to Next Capability
80h
This contains a pointer to the next item in the capabilities list which is the PCI
Power Management capability.
RO
Capability ID
0D h
Value of 0Dh identifies this linked list item (capability structure) as being for
SSID/SSVID registers in a PCI-to-PCI Bridge.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
165
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.26
SS—Subsystem ID and Subsystem Vendor ID
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
8Ch
00008086h
R/WO
32 bits
System BIOS can be used as the mechanism for loading the SSID/SVID values. These values must be
preserved through power management transitions and a hardware reset.
Bit
Access &
Default
31:16
R/WO
0000 h
15:0
6.2.27
Description
Subsystem ID (SSID)
Identifies the particular subsystem and is assigned by the vendor.
R/WO
Subsystem Vendor ID (SSVID)
8086 h
Identifies the manufacturer of the subsystem and is the same as the vendor ID
which is assigned by the PCI Special Interest Group.
MSI_CAPID—Message Signaled Interrupts Capability ID
PCI Device:
1
Address Offset:
90h
Default Value:
A005h
Access:
RO
Size:
16 bits
When a device supports MSI it can generate an interrupt request to the processor by writing a
predefined data item (a message) to a predefined memory address.
In that case walking this linked list will skip this capability and instead go directly from the PCI PM
capability to the PCI Express capability.
166
Bit
Access &
Default
15:8
RO
A0 h
7:0
RO
05 h
Description
Pointer to Next Capability
This contains a pointer to the next item in the capabilities list which is the PCI
Express capability.
Capability ID
05h = identifies this linked list item (capability structure) as being for MSI
registers.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.28
MC—Message Control
PCI Device:
1
Address Offset:
92h
Default Value:
0000h
Access:
RO, R/W
Size:
16 bits
System software can modify bits in this register, but the device is prohibited from doing so.
If the device writes the same message multiple times, only one of those messages is guaranteed to be
serviced. If all of them must be serviced, the device must not generate the same message again until
the driver services the earlier one.
Bit
15:8
7
6.2.29
Access &
Default
RO
0b
Description
Reserved
64-bit Address Capable
Hardwired to 0 to indicate that the function does not implement the upper 32 bits
of the Message Address register and is incapable of generating a 64-bit memory
address.
Multiple Message Enable (MME)
System software programs this field to indicate the actual number of messages
allocated to this device. This number will be equal to or less than the number
actually requested.
000: 1 Messages allocated
001 - 111:
Reserved
6:4
R/W
000 b
3:1
RO
000 b
Multiple Message Capable (MMC)
System software reads this field to determine the number of messages being
requested by this device.
000: 1 Messages Requested
001 - 111: Reserved
0
R/W
0b
MSI Enable (MSIEN) Controls the ability of this device to generate MSI's.
0: MSI will not be generated.
1: MSI will be generated when we receive PME or HotPlug messages. INTA will
not be generated and INTA Status (PCISTS1[3]) will not be set.
MA—Message Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
94h
00000000h
RO, R/W
32 bits
A read from this register produces undefined results.
Bit
31:2
Access &
Default
R/W
00000000 h
Description
Message Address
Used by system software to assign an MSI address to the device.
The device handles an MSI by writing the padded contents of the MD register to
this address.
1:0
RO
Force DWORD Align
00 b
Hardwired to 0 so that addresses assigned by system software are always
aligned on a DWORD address boundary.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
167
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.30
MD—Message Data
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:0
R/W
0000 h
1
98h
0000h
R/W
16 bits
Description
Message Data
Base message data pattern assigned by system software and used to handle an
MSI from the device.
When the device must generate an interrupt request, it writes a 32-bit value to the
memory address specified in the MA register. The upper 16 bits are always set to
0. The lower 16 bits are supplied by this register.
6.2.31
PEG_CAPL—PCI Express Based Graphics Capability List
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
A0h
0010h
RO
16 bits
Enumerates the PCI Express capability structure.
Bit
Access &
Default
15:8
RO
00 h
7:0
168
Description
Pointer to Next Capability
This value terminates the capabilities list. The Virtual Channel capability and any
other PCI Express specific capabilities that are reported via this mechanism are in
a separate capabilities list located entirely within PCI Express Extended
Configuration Space.
RO
Capability ID
10 h
Identifies this linked list item (capability structure) as being for PCI Express
registers.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.32
PEG_CAP—PCI Express*Based Graphics Capabilities
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
A2h
0141h
RO
16 bits
Indicates PCI Express device capabilities.
Bit
Access &
Default
Reserved
15:14
13:9
Description
RO
Interrupt Message Number Hardwired to 0.
00000 b
8
R/WO
1b
Slot Implemented
0: The PCI Express Link associated with this port is connected to an integrated
component or is disabled.
1: The PCI Express Link associated with this port is connected to a slot.
BIOS must initialize this field appropriately if a slot connection is not implemented.
7:4
RO
4h
3:0
RO
1h
6.2.33
Device/Port Type
Hardwired to 0100 to indicate root port of PCI Express Root Complex.
PCI Express Capability Version
Hardwired to 1 as it is the first version.
DCAP—Device Capabilities
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
A4h
00000000h
RO
32 bits
This register indicates PCI Express link capabilities.
Bit
Access &
Default
Reserved Hardwired to 0.
31:6
5
RO
0b
4:3
Description
RO
Extended Tag Field Supported
Hardwired to indicate support for 5-bit Tags as a Requestor.
Phantom Functions Supported.
Hardwired to 0.
00 b
2:0
RO
000 b
Max Payload Size
Hardwired to indicate 128B max supported payload for Transaction Layer Packets
(TLP).
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
169
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.34
DCTL—Device Control
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
A8h
0000h
RO, R/W
16 bits
Provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not errors messages
received across the link. The reporting of error messages (ERR_CORR, ERR_NONFATAL,
ERR_FATAL) received by Root Port is controlled exclusively by Root Port Command Register.
Bit
Access &
Default
Reserved
15:8
7:5
Description
R/W
000 b
Max Payload Size
000: 128B max supported payload for Transaction Layer Packets (TLP). As a
receiver, the Device must handle TLPs as large as the set value; as transmitter,
the Device must not generate TLPs exceeding the set value.
Note: All other encodings are reserved.
Reserved
4
3
R/W
0b
Unsupported Request Reporting Enable
0 = Disabled.
1 = Enabled. Unsupported Requests will be reported.
Note that reporting of error messages received by Root Port is controlled
exclusively by Root Control register.
2
R/W
0b
1
R/W
0b
0
R/W
0b
170
Fatal Error Reporting Enable
0 = Disabled
1 = Enabled. Fatal errors will be reported. For a Root Port, the reporting of fatal
errors is internal to the root. No external ERR_FATAL message is generated.
Non-Fatal Error Reporting Enable
0 = Disabled.
1 = Enabled. Non-fatal errors will be reported. For a Root Port, the reporting of
non-fatal errors is internal to the root. No external ERR_NONFATAL message is
generated. Uncorrectable errors can result in degraded performance.
Correctable Error Reporting Enable
0 = Disabled.
1 = Enabled. Correctable errors will be reported. For a Root Port, the reporting
of correctable errors is internal to the root. No external ERR_CORR message is
generated.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.35
DSTS—Device Status
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
AAh
0000h
RO, R/WC
16 bits
Reflects status corresponding to controls in the Device Control register.
The error reporting bits are in reference to errors detected by this device, not errors messages received
across the link.
Bit
Access &
Default
Reserved
15:6
5
Description
RO
Transactions Pending
0b
0: All pending transactions (including completions for any outstanding non-posted
requests on any used virtual channel) have been completed.
1: Indicates that the device has transaction(s) pending (including completions for
any outstanding non-posted requests for all used Traffic Classes).
Reserved
4
3
R/WC
0b
2
R/WC
0b
1
R/WC
0b
0
R/WC
0b
Unsupported Request Detected
When set this bit indicates that the Device received an Unsupported Request.
Errors are logged in this register regardless of whether error reporting is enabled
or not in the Device Control Register.
Fatal Error Detected
When set this bit indicates that fatal error(s) were detected. Errors are logged in
this register regardless of whether error reporting is enabled or not in the Device
Control register.
Non-Fatal Error Detected
When set this bit indicates that non-fatal error(s) were detected. Errors are logged
in this register regardless of whether error reporting is enabled or not in the Device
Control register.
Correctable Error Detected
When set this bit indicates that correctable error(s) were detected.
Errors are logged in this register regardless of whether error reporting is enabled
or not in the Device Control register.
Note: The GMCH may report a false 8B/10B Receiver Error when exiting L0s. This
is reported thru the Correctable Error Detected bit CESTS device 1, offset 1D0h,
Bit [0]. This will reduce the value of Receiver Error detection when L0s is enabled.
Disable L0s for accurate Receiver Error reporting.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
171
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.36
LCAP—Link Capabilities
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
ACh
02012801h
RO, R/WO
32 bits
Indicate PCI Express device specific capabilities.
Bit
Access &
Default
31:24
RO
Port Number
02 h
Indicates the PCI Express port number for the given PCI Express link. Matches
the value in Element Self Description [31:24].
Reserved
23:18
17:15
Description
R/WO
L1 Exit Latency
010 b
Indicates the length of time this Port requires to complete the transition from L1 to
L0.
The value 010 b indicates the range of 2 µs to less than 4 µs. If this field is
required to be any value other than the default, BIOS must initialize it accordingly.
Both bytes of this register that contain a portion of this field must be written
simultaneously in order to prevent an intermediate (and undesired) value from
ever existing.
14:12
R/WO
L0s Exit Latency
010 b
Indicates the length of time this Port requires to complete the transition from L0s
to L0.
The value 010 b indicates the range of 128 ns to less than 256 ns.
Note: The default value for this field assumes a Common Clock Configuration. If
the link is not in Common Clock, then System BIOS will need to program 100b
(652 ns, which falls into the "512 ns to less than 1 us" range) in this field.
11:10
W/RO
11 b
9:4
RO
010000 b
3:0
RO
1h
172
Active State Link PM Support
L0s & L1 entry supported.
Max Link Width
Hardwired to indicate X16.
When X1 mode is enabled on this PCI Express x16 Graphics interface device, this
field reflects X1 (01h).
Max Link Speed
Hardwired to indicate 2.5 Gb/s.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.37
LCTL—Link Control
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
B0h
0000h
RO, R/W
16 bits
Allows control of PCI Express link.
Bit
Access &
Default
15:8
7
Description
Reserved
R/W
Extended Synch
0h
0: Standard Fast Training Sequence (FTS).
1: Reserved
6
R/W
Common Clock Configuration
0b
0: Indicates that this component and the component at the opposite end of this
Link are operating with asynchronous reference clock.
1: Indicates that this component and the component at the opposite end of this
Link are operating with a distributed common reference clock.
Components utilize this common clock configuration information to report the
correct L0s and L1 Exit Latencies.
5
R/W
0b
Retrain Link
0: Normal operation
1: Full Link retraining is initiated by directing the Physical Layer LTSSM from L0,
L0s, or L1 states to the Recovery state.
This bit always returns 0 when read. This bit is cleared automatically (no need to
write a 0).
4
R/W
Link Disable
0b
0: Normal operation
1: Link is disabled
Link retraining happens automatically on 1 to 0 transition, just like when coming
out of reset. Writes to this bit are immediately reflected in the value read from the
bit, regardless of actual Link state.
3
2
RO
Read Completion Boundary (RCB)
0b
Hardwired to 0 to indicate 64 byte.
RO
Reserved
0b
1:0
R/W
Active State PM
00 b
Controls the level of active state power management supported on the given link.
00: Disabled
01: L0s Entry Supported
10: L1 Entry Supported (Only)
11: L0s and L1 Entry Supported
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
173
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.38
LSTS—Link Status
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
B2h
1001h
RO
16 bits
Indicates PCI Express link status.
Bit
Access &
Default
Reserved
15:13
12
Description
RO
Slot Clock Configuration
1b
0: The device uses an independent clock irrespective of the presence of a
reference on the connector.
1: The device uses the same physical reference clock that the platform provides
on the connector.
11
10
9:4
RO
Link Training
0b
Indicates that the Physical Layer LTSSM is in the Configuration or Recovery state,
or that 1b was written to the Retrain Link bit but Link training has not yet begun.
Hardware clears this bit when the LTSSM exits the Configuration/Recovery state
once Link training is complete.
RO
Training Error
0b
This bit is set by hardware upon detection of unsuccessful training of the Link to
the L0 Link state.
RO
Negotiated Width
000000 b
Indicates negotiated link width. This field is valid only when the link is in the L0,
L0s, or L1 states (after link width negotiation is successfully completed).
00h:
01h:
04h:
08h:
10h:
Reserved
X1
Reserved
Reserved
X16
All other encodings are reserved.
3:0
RO
Negotiated Speed
1h
Indicates negotiated link speed.
1h:
2.5 Gb/s
All other encodings are reserved.
174
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.39
SLOTCAP—Slot Capabilities
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
B4h
00000000h
RO, R/WO
32 bits
PCI Express Slot related registers allow for the support of Hot Plug.
Bit
31:19
Access &
Default
Description
R/WO
Physical Slot Number
0000 h
Indicates the physical slot number attached to this Port.
This field must be initialized by BIOS to a value that assigns a slot number that
is globally unique within the chassis.
18:17
16:15
Reserved
R/WO
00 b
Slot Power Limit Scale
Specifies the scale used for the Slot Power Limit Value.
00 = 1.0x
01 = 0.1x
10 = 0.01x
11 = 0.001x
If this field is written, the link sends a Set_Slot_Power_Limit message.
14:7
R/WO
00 h
Slot Power Limit Value
In combination with the Slot Power Limit Scale value, specifies the upper limit
on power supplied by slot. Power limit (in Watts) is calculated by multiplying
the value in this field by the value in the Slot Power Limit Scale field.
If this field is written, the link sends a Set_Slot_Power_Limit message.
6
R/WO
0b
5
R/WO
0b
4
R/WO
0b
3
R/WO
0b
Indicates that this slot is capable of supporting Hot-plug operations.
Hot-plug Surprise
Indicates that a device present in this slot might be removed from the system
without any prior notification.
Power Indicator Present
Indicates that a Power Indicator is implemented on the chassis for this slot.
Attention Indicator Present
Indicates that an Attention Indicator is implemented on the chassis for this slot.
Reserved
2:1
0
Hot-plug Capable
R/WO
0b
Attention Button Present
Indicates that an Attention Button is implemented on the chassis for this slot.
The Attention Button allows the user to request hot-plug operations.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
175
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.40
SLOTCTL—Slot Control
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
B8h
01C0
RO, R/W
16 bits
PCI Express Slot related registers allow for the support of Hot Plug.
Bit
Access &
Default
15:10
9:8
Description
Reserved
R/W
Power Indicator Control
01 b
Reads to this register return the current state of the Power Indicator.
Writes to this register set the Power Indicator and cause the Port to send the
appropriate POWER_INDICATOR_* messages.
00: Reserved
01: On
10: Blink
11: Off
7:6
R/W
Attention Indicator Control
11 b
Reads to this register return the current state of the Attention Indicator.
Writes to this register set the Attention Indicator and cause the Port to send the
appropriate ATTENTION_INDICATOR_* messages.
00: Reserved
01: On
10: Blink
11: Off
5
4
3
R/W
Hot plug Interrupt Enable
0b
When set enables generation of hot plug interrupt on enabled hot plug events.
R/W
Command Completed Interrupt Enable
0b
When set enables the generation of hot plug interrupt when a command is
completed by the Hot plug controller.
R/W
Presence Detect Changed Enable
0b
When set enables the generation of hot plug interrupt or wake message on a
presence detect changed event.
Reserved
2:1
0
176
R/W
Attention Button Pressed Enable
0b
When set enables the generation of hot plug interrupt or wake message on an
attention button pressed event.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.41
SLOTSTS—Slot Status
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
BAh
0000h
RO, R/WC
16 bits
PCI Express Slot related registers allow for the support of Hot Plug.
Bit
Access &
Default
15:7
RO
Description
Reserved
000 h
6
RO
Xb
R/WC
0b
3
R/WC
0b
0 : Slot Empty
1 : Card Present in slot.
Command Completed
Set when the hot plug controller completes an issued command.
Presence Detect Changed
Set when a Presence Detect change is detected.
This corresponds to an edge on the signal that corresponds to bit 6 of this
register (Presence Detect State).
Reserved
2:1
0
Indicates the presence of a card in the slot.
Reserved
5
4
Presence Detect State
R/WC
0b
Attention Button Pressed
Set when the Attention Button is pressed.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
177
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.42
RCTL—Root Control
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
BCh
0000h
RO, R/W
16 bits
Allows control of PCI Express Root Complex specific parameters. The system error control bits in this
register determine if corresponding SERRs are generated when our device detects an error (reported in
this device’s Device Status register) or when an error message is received across the link. Reporting of
SERR as controlled by these bits takes precedence over the SERR Enable in the PCI Command
Register.
Bit
Access &
Default
Reserved
15:4
3
R/W
0b
2
Description
R/W
0b
PME Interrupt Enable
0: No interrupts are generated as a result of receiving PME messages.
1: Enables interrupt generation upon receipt of a PME message as reflected in
the PME Status bit of the Root Status Register. A PME interrupt is also
generated if the PME Status bit of the Root Status Register is set when this bit is
set from a cleared state.
System Error on Fatal Error Enable
Controls the Root Complex’s response to fatal errors.
0: No SERR generated on receipt of fatal error.
1: Indicates that an SERR should be generated if a fatal error is reported by any
of the devices in the hierarchy associated with this Root Port, or by the Root Port
itself.
1
R/W
0b
System Error on Non-Fatal Uncorrectable Error Enable
Controls the Root Complex’s response to non-fatal errors.
0: No SERR generated on receipt of non-fatal error.
1: Indicates that an SERR should be generated if a non-fatal error is reported by
any of the devices in the hierarchy associated with this Root Port, or by the Root
Port itself.
0
R/W
0b
System Error on Correctable Error Enable
Controls the Root Complex’s response to correctable errors.
0: No SERR generated on receipt of correctable error.
1: Indicates that an SERR should be generated if a correctable error is reported
by any of the devices in the hierarchy associated with this Root Port, or by the
Root Port itself.
178
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.43
RSTS—Root Status
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
C0h
00000000h
RO, R/W/C
32 bits
Provides information about PCI Express Root Complex specific parameters.
Bit
Access &
Default
Reserved
31:18
17
RO
0b
16
R/W/C
0b
15:0
Description
RO
0000 h
PME Pending
Indicates that another PME is pending when the PME Status bit is set.
When the PME Status bit is cleared by software; the PME is delivered by hardware
by setting the PME Status bit again and updating the Requestor ID appropriately.
The PME pending bit is cleared by hardware if no more PME's are pending.
PME Status
Indicates that PME was asserted by the requestor ID indicated in the PME
Requestor ID field. Subsequent PME’s are kept pending until the status register is
cleared by writing a 1 to this field.
PME Requestor ID
Indicates the PCI requestor ID of the last PME requestor.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
179
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.44
PEGLC—PCI Express* Based Graphics Legacy Control
PCI Device:
Address Offset:
Default Value
Access:
Size:
1
ECh
00000000h
RO, R/W
32 bits
Controls functionality that is needed by Legacy (non-PCI Express aware) OS’s during run time.
Bit
31:3
Access &
Default
RO
Description
Reserved
0000 0000h
2
R/W
PME GPE Enable (PMEGPE)
0b
0: Do not generate GPE PME message when PME is received.
1: Generate a GPE PME message when PME is received (Assert_PMEGPE
and Deassert_PMEGPE messages on DMI). This enables the MCH to support
PMEs on the PEG port under legacy OSs.
1
R/W
Hot-Plug GPE Enable (HPGPE)
0b
0: Do not generate GPE Hot-Plug message when Hot-Plug event is received.
1: Generate a GPE Hot-Plug message when Hot-Plug Event is received
(Assert_HPGPE and Deassert_HPGPE messages on DMI). This enables the
MCH to support Hot-Plug on the PEG port under legacy OSs.
0
R/W
General Message GPE Enable (GENGPE)
0b
0: Do not forward received GPE assert/deassert messages.
1: Forward received GPE assert/deassert messages. These general GPE
message can be received via the PEG port from an external Intel device (i.e.
PxH) and will be subsequently forwarded to the ICH (via Assert_GPE and
Deassert_GPE messages on DMI). For example, a PxH might send this
message if a PCI Express device is hot plugged into a PxH downstream port.
180
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.45
VCECH—Virtual Channel Enhanced Capability Header
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
100h
14010002h
RO
32 bits
Indicates PCI Express device Virtual Channel capabilities.
Note that extended capability structures for PCI Express devices are located in PCI Express extended
configuration space and have different field definitions than standard PCI capability structures.
Bit
Access &
Default
31:20
RO
140 h
19:16
15:0
Pointer to Next Capability
The Link Declaration Capability is the next in the PCI Express extended capabilities
list.
RO
PCI Express Virtual Channel Capability Version
1h
Hardwired to 1 to indicate compliances with the 1.0 version of the PCI Express
specification.
RO
Extended Capability ID
0002 h
6.2.46
Description
Value of 0002 h identifies this linked list item (capability structure) as being for PCI
Express Virtual Channel registers.
PVCCAP1—Port VC Capability Register 1
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
104h
00000001h
RO, R/WO
32 bits
Describes the configuration of PCI Express Virtual Channels associated with this port.
Bit
Access &
Default
Reserved
31:7
6:4
Description
RO
000 b
Low Priority Extended VC Count
Indicates the number of (extended) Virtual Channels in addition to the default VC
belonging to the low-priority VC (LPVC) group that has the lowest priority with
respect to other VC resources in a strict-priority VC Arbitration.
The value of 0 in this field implies strict VC arbitration.
Reserved
3
2:0
R/WO
Extended VC Count
001 b
Indicates the number of (extended) Virtual Channels in addition to the default VC
supported by the device.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
181
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.47
PVCCAP2—Port VC Capability Register 2
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
108h
00000000h
RO
32 bits
Describes the configuration of PCI Express Virtual Channels associated with this port.
Bit
Access &
Default
31:24
RO
00 h
VC Arbitration Table Offset
Indicates the location of the VC Arbitration Table.
This field contains the zero-based offset of the table in DQWORDS (16 bytes) from
the base address of the Virtual Channel Capability Structure. A value of 0 indicates
that the table is not present (due to fixed VC priority).
Reserved
23:8
7:0
Description
RO
VC Arbitration Capability
01 h
Indicates that the only possible VC arbitration scheme is hardware fixed (in the root
complex).
VC1 is the highest priority, VC0 is the lowest priority.
6.2.48
PVCCTL—Port VC Control
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
Description
Reserved
15:4
3:1
1
10Ch
0000h
RO, R/W
16 bits
R/W
VC Arbitration Select
000 b
This field will be programmed by software to the only possible value as indicated in
the VC Arbitration Capability field.
This field can not be modified when more than one VC in the LPVC group is
enabled.
0
182
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.49
VC0RCAP—VC0 Resource Capability
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
Description
Reserved
31:16
15
1
110h
00000000h
RO
32 bits
RO
Reject Snoop Transactions
0b
0: Transactions with or without the No Snoop bit set within the TLP header are
allowed on this VC.
1: Any transaction without the No Snoop bit set within the TLP header will be
rejected as an Unsupported Request.
Reserved
14:0
6.2.50
VC0RCTL—VC0 Resource Control
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
114h
800000FF
RO, R/W
32 bits
Controls the resources associated with PCI Express Virtual Channel 0.
Bit
Access &
Default
31
RO
VC0 Enable
1b
For VC0 this is hardwired to 1 and read only as VC0 can never be disabled.
30:27
26:24
Reserved
RO
000 b
23:8
7:1
VC0 ID
Assigns a VC ID to the VC resource. For VC0 this is hardwired to 0 and read only.
Reserved
R/W
1111111
b
0
Description
TC/VC0 Map
Indicates the TCs (Traffic Classes) that are mapped to the VC resource.
Bit locations within this field correspond to TC values. For example, when bit 7 is
set in this field, TC7 is mapped to this VC resource. When more than one bit in this
field is set, it indicates that multiple TCs are mapped to the VC resource. In order to
remove one or more TCs from the TC/VC Map of an enabled VC, software must
ensure that no new or outstanding transactions with the TC labels are targeted at
the given Link.
RO
TC0/VC0 Map
1b
Traffic Class 0 is always routed to VC0.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
183
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.51
VC0RSTS—VC0 Resource Status
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
11Ah
0000h
RO
16 bits
Reports the Virtual Channel specific status.
Bit
Access &
Default
Reserved
15:2
1
Description
RO
1b
VC0 Negotiation Pending
0: The VC negotiation is complete.
1: The VC resource is still in the process of negotiation (initialization or disabling).
This bit indicates the status of the process of Flow Control initialization. It is set by
default on Reset, as well as whenever the corresponding Virtual Channel is
Disabled or the Link is in the DL_Down state. It is cleared when the link successfully
exits the FC_INIT2 state
Before using a Virtual Channel, software must check whether the VC Negotiation
Pending fields for that Virtual Channel are cleared in both Components on a Link.
Reserved
0
6.2.52
VC1RCAP—VC1 Resource Capability
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
Description
Reserved
31:16
15
1
11Ch
00008000h
RO
32 bits
RO
Reject Snoop Transactions
1b
0: Transactions with or without the No Snoop bit set within the TLP header are
allowed on this VC.
1: Any transaction without the No Snoop bit set within the TLP header will be
rejected as an Unsupported Request.
14:0
184
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.53
VC1RCTL—VC1 Resource Control
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
120h
01000000h
RO, R/W
32 bits
Controls the resources associated with PCI Express Virtual Channel 1.
Bit
Access &
Default
31
R/W
0b
Description
VC1 Enable
0: Virtual Channel is disabled.
1: Virtual Channel is enabled.
See exceptions in note below.
Software must use the VC Negotiation Pending bit to check whether the VC
negotiation is complete. When VC Negotiation Pending bit is cleared, a 1 read from
this VC Enable bit indicates that the VC is enabled (Flow Control Initialization is
completed for the PCI Express port); a 0 read from this bit indicates that the Virtual
Channel is currently disabled.
NOTES:
R/W
001 b
R/W
0000000
b
0
2.
To disable a Virtual Channel, the VC Enable bits for that Virtual Channel must
be cleared in both Components on a Link.
3.
Software must ensure that no traffic is using a Virtual Channel at the time it is
disabled.
4.
Software must fully disable a Virtual Channel in both Components on a Link
before re-enabling the Virtual Channel.
VC1 ID
Assigns a VC ID to the VC resource. Assigned value must be non-zero.
This field can not be modified when the VC is already enabled.
Reserved
23:8
7:1
To enable a Virtual Channel, the VC Enable bits for that Virtual Channel must
be set in both Components on a Link.
Reserved
30:27
26:24
1.
RO
0b
TC/VC1 Map
Indicates the TCs (Traffic Classes) that are mapped to the VC resource. Bit
locations within this field correspond to TC values. For example, when bit 7 is set in
this field, TC7 is mapped to this VC resource. When more than one bit in this field
is set, it indicates that multiple TCs are mapped to the VC resource. In order to
remove one or more TCs from the TC/VC Map of an enabled VC, software must
ensure that no new or outstanding transactions with the TC labels are targeted at
the given Link.
TC0/VC1 Map
Traffic Class 0 is always routed to VC0.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
185
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.54
VC1RSTS—VC1 Resource Status
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
126h
0000h
RO
16 bits
Reports the Virtual Channel specific status.
Bit
Access &
Default
Reserved
15:2
1
Description
RO
1b
VC1 Negotiation Pending
0: The VC negotiation is complete.
1: The VC resource is still in the process of negotiation (initialization or disabling).
Software may use this bit when enabling or disabling the VC. This bit indicates the
status of the process of Flow Control initialization. It is set by default on Reset, as
well as whenever the corresponding Virtual Channel is Disabled or the Link is in the
DL_Down state. It is cleared when the link successfully exits the FC_INIT2 state
Before using a Virtual Channel, software must check whether the VC Negotiation
Pending fields for that Virtual Channel are cleared in both Components on a Link.
Reserved
0
6.2.55
RCLDECH—Root Complex Link Declaration Enhanced
Capability Header
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
140h
00010005h
RO
32 bits
This capability declares links from this element (PEG) to other elements of the root complex
component to which it belongs. See PCI Express specification for link/topology declaration
requirements.
Bit
Access &
Default
31:20
RO
000 h
19:16
15:0
Pointer to Next Capability
This is the last capability in the PCI Express extended capabilities
RO
Link Declaration Capability Version
1h
Hardwired to 1 to indicate compliances with the 1.0 version of the PCI Express
specification.
RO
Extended Capability ID
0005 h
186
Description
Value of 0005 h identifies this linked list item (capability structure) as being for PCI
Express Link Declaration Capability.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.56
ESD—Element Self Description
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
144h
02000100h
RO, R/WO
32 bits
Provides information about the root complex element containing this Link Declaration Capability.
Bit
Access &
Default
31:24
RO
02 h
23:16
R/WO
00 h
Description
Port Number
Specifies the port number associated with this element with respect to the
component that contains this element. This port number value is utilized by the
egress port of the component to provide arbitration to this Root Complex Element.
Component ID
Identifies the physical component that contains this Root Complex Element.
Component IDs start at 1.
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
15:8
RO
01 h
Indicates the number of link entries following the Element Self Description. This
field reports 1 (to Egress port only as we don’t report any peer-to-peer capabilities in
our topology).
Reserved
7:4
3:0
Number of Link Entries
RO
0h
Element Type
Indicates the type of the Root Complex Element.
Value of 0 h represents a root port.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
187
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.57
LE1D—Link Entry 1 Description
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
150h
00000000h
RO, R/WO
32 bits
First part of a Link Entry which declares an internal link to another Root Complex Element.
Bit
Access &
Default
31:24
RO
Description
Target Port Number
Specifies the port number associated with the element targeted by this link entry
(Egress Port). The target port number is with respect to the component that
contains this element as specified by the target component ID.
00 h
23:16
Target Component ID
R/WO
Identifies the physical or logical component that is targeted by this link entry. A
value of 0 is reserved; Component IDs start at 1.
00 h
This value is a mirror of the value in the Component ID field of all elements in this
component. The value only needs to be written in one of the mirrored fields and it
will be reflected everywhere that it is mirrored.
Reserved
15:2
1
0
RO
Link Type
0b
Indicates that the link points to memory-mapped space (for RCRB). The link
address specifies the 64-bit base address of the target RCRB.
Link Valid
R/WO
0: Link Entry is not valid and will be ignored.
0b
6.2.58
1: Link Entry specifies a valid link.
LE1A—Link Entry 1 Address
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
158h
0000000000000000h
RO, R/WO
64 bits
Second part of a Link Entry which declares an internal link to another Root Complex Element.
Bit
Access &
Default
Reserved
63:32
31:12
R/WO
0 0000 h
11:0
188
Description
Link Address
Memory mapped base address of the RCRB that is the target element (Egress
Port) for this link entry.
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
R
6.2.59
PEGSSTS—PCI Express Graphics Sequence Status
PCI Device:
Address Offset:
Default Value:
Access:
Size:
1
218h
0000000000000FFFh
RO
64 bits
PCI Express status reporting that is required by the PCI Express spec.
Bit
Access &
Default
Reserved
63:60
59:48
RO
000 h
RO
000 h
RO
000 h
Next Transmitted Sequence Number
This is the sequence number to be applied to and pre-pended to the next outgoing
TLP. This value is taken from the outlet of the Retry Buffer (the current sequence
number being transmitted on the PCI Express Link).
Next Receive Sequence Number
This is the sequence number associated with the TLP that is expected to be
received next.
Reserved
15:12
11:0
This is the sequence number to be applied to and pre-pended to the next TLP being
placed into the Retry Buffer at the Transaction Layer/Data Link Layer interface.
Reserved
31:28
27:16
Next Retry Buffer Entry Sequence Number
Reserved
47:44
43:32
Description
RO
FFF h
Last Acknowledged Sequence Number
This is the sequence number associated with the last acknowledged TLP.
§
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
189
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7
Internal Graphics Device #2
Configuration Register (D2:F0)
Note:
Excludes Mobile Intel® 915PM Express Chipset.
Device #2 contains registers for the internal graphics functions. The table below lists the PCI
configuration registers in order of ascending offset address.
Function #0 can be VGA compatible or not, this is selected through bit 1 of GGC register (Device #0,
offset 52h)
The following sections describe Device 2 PCI configuration registers only.
Note: Register information for the PCI Express* Based Graphics Port is NOT relative to the Intel®
915GMS , 910GML and 910GMLE Express Chipsets.
Note: Register information for the Integrated Graphics Device is NOT relative to the Mobile Intel®
915PM Express Chipset.
190
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.1
Device #2: Function 0 Register Summary
7.2
Device #2: Function 0 Configuration Register Details
Table 7-1. Device #2: Function 0 Configuration Register Summary Table
Address Start
(h)
Register Symbol
Register Name
Default Value
Access
00-01h
VID2
Vendor Identification
8086h
RO
02-03h
DID2
Device Identification
2592h
RO
04-05h
PCICMD2
PCI Command
00h
RO, R/W
06-07h
PCISTS2
PCI Status
0090h
RO, R/WC
08h
RID2
Revision Identification
00h
RO
09-0Bh
CC
Class Code
030000h
RO
0Ch
CLS
Cache Line Size
00h
RO
0Dh
MLT2
Master Latency Timer
00h
RO
0Eh
HDR2
Header Type
80h
RO
0Fh
Reserved
10-13h
MMADR
Memory Mapped Range
Address
00000000h
RO, R/W
14-17h
IOBAR
I/O Base Address
00000001h
RO, R/W
18-1Bh
GMADR
Graphics Memory Range
Address
00000000h
RO, R/W,
R/W/L
1C-1Fh
GTTADR
Graphics Translation Table
Range Address
00000000h
RO, R/W
20-2Bh
Reserved
2C-2Dh
SVID2
Subsystem Vendor
Identification
0000h
R/WO
2E-2Fh
SID2
Subsystem Identification
0000h
R/WO
30-33h
ROMADR
Video BIOS ROM Base
Address
00000000h
RO
34h
CAPPOINT
Capabilities Pointer
D0h
RO
35-3Bh
Reserved
3Ch
INTRLINE
Interrupt Line
00h
R/W
3Dh
INTRPIN
Interrupt Pin
01h
RO
3Eh
MINGNT
Minimum Grant
00h
RO
3Fh
MAXLAT
Maximum Latency
00h
RO
40-43h
44h
45-47h
Reserved
MCAPPTR
Mirror of Dev0 Capability
Pointer
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
191
Internal Graphics Device #2 Configuration Register (D2:F0)
R
Address Start
(h)
48-50h
Register Symbol
MCAPID
51h
MGGC
Mirror of Dev0 GMCH
Graphics Control
54-57h
MDEVENdev0f0
Mirror of Dev0 Device Enable
07800000h
RO
00h
RO, R/W
Reserved
BSM
60-61h
62h
Access
Mirror of Dev0 Capability
Identification
52-53h
5C-5Fh
Default Value
Reserved
58-5Bh
Base of Stolen Memory
Reserved
MSAC
63-CFh
Multi Size Aperture Control
Reserved
D0-D1h
PMCAPID
Power Management
Capabilities ID
0001h
RO
D2-D3h
PMCAP
Power Management
Capabilities
0022h
RO
D4-D5h
PMCS
Power Management
Control/Status
0000h
RO, R/W
0000h
R/W
00000000h
R/W
D6-DFh
E0-E1h
Reserved
SWSMI
E2-E3h
E4-E7
Software SMI
Reserved
ASLE
E9-EFh
192
Register Name
System Display Event
Reserved
F0-F1h
GCFGC
Graphics Clock Frequency
and Gating Control
0000h
RO, R/W
F2-F3h
GCPLLC
Graphics Clock PLL Control
3464h
RO, R/W
F4-FBh
ASLE
ASL Event /Legacy Backlight
Brightness
00000000h
R/W
FC-FFh
ASLS
ASL Storage
00000000h
R/W
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.1
VID2—Vendor Identification
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
00h
8086h
RO
16 bits
This register combined with the Device Identification register uniquely identifies any PCI device.
Bit
Access &
Default
15:0
RO
Description
Vendor Identification Number (VID): PCI standard identification for Intel.
8086 h
7.2.2
DID2—Device Identification
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
02h
2592h
RO
16 bits
This register combined with the Vendor Identification register uniquely identifies any PCI device.
Bit
Access
& Default
15:0
RO
2592 h
Description
Device Identification Number (DID): Identifier assigned to the GMCH core/primary
PCI device.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
193
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.3
PCICMD2—PCI Command
PCI Device:
2
Function:
0
Address Offset:
04h
Default Value:
00h
Access:
RO, R/W
Size:
16 bits
This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The
PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory.
Bit
Access &
Default
15:11
10
Description
Reserved.
R/W
Interrupt Disable:
0b
This bit disables the device from asserting INTx#.
0:
Enable the assertion of this device’s INTx# signal.
1: Disable the assertion of this device’s INTx# signal. DO_INTx messages
will not be sent to DMI.
9
8
RO
Fast Back-to-Back (FB2B):
0b
Not Implemented. Hardwired to 0.
RO
SERR Enable (SERRE):
0b
Not Implemented. Hardwired to 0.
7
RO
Address/Data Stepping Enable (ADSTEP):
0b
Not Implemented. Hardwired to 0.
6
RO
Parity Error Enable (PERRE):
0b
Not Implemented. Hardwired to 0.
Since the IGD belongs to the category of devices that does not corrupt programs or
data in system memory or hard drives, the IGD ignores any parity error that it
detects and continues with normal operation.
5
RO
This bit is hardwired to 0 to disable snooping.
4
RO
Memory Write and Invalidate Enable (MWIE):
0b
Hardwired to 0. The IGD does not support memory write and invalidate commands.
3
RO
Special Cycle Enable (SCE):
0b
This bit is hardwired to 0. The IGD ignores Special cycles.
2
R/W
Bus Master Enable (BME):
0b
1
0
0:
Disable IGD bus mastering.
1:
Enable the IGD to function as a PCI compliant master.
R/W
Memory Access Enable (MAE):
0b
This bit controls the IGD’s response to memory space accesses.
R/W
0b
194
Video Palette Snooping (VPS):
0b
0:
Disable.
1:
Enable.
I/O Access Enable (IOAE):
This bit controls the IGD’s response to I/O space accesses.
0:
Disable.
1:
Enable.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.4
PCISTS2—PCI Status
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
06h
0090h
RO, R/WC
16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI
compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD.
Bit
Access &
Default
15
RO
0b
14
RO
0b
13
RO
0b
12
RO
0b
11
RO
0b
10:9
RO
00 b
8
7
6
The IGD never asserts SERR#, therefore this bit is hardwired to 0.
Received Master Abort Status (RMAS):
The IGD never gets a Master Abort, therefore this bit is hardwired to 0.
Received Target Abort Status (RTAS):
The IGD never gets a Target Abort, therefore this bit is hardwired to 0.
Signaled Target Abort Status (STAS):
Hardwired to 0. The IGD does not use target abort semantics.
DEVSEL Timing (DEVT):
N/A. These bits are hardwired to 00.
Since Parity Error Response is hardwired to disabled (and the IGD does not do any
parity detection), this bit is hardwired to 0.
RO
Fast Back-to-Back (FB2B):
1b
Hardwired to 1. The IGD accepts fast back-to-back when the transactions are not
to the same agent.
RO
User Defined Format (UDF).
RO
RO
R/WC
0b
2:0
Signaled System Error (SSE):
0b
1b
3
Since the IGD does not detect parity, this bit is always hardwired to 0.
Master Data Parity Error Detected (DPD):
0b
4
Detected Parity Error (DPE):
RO
0b
5
Description
Hardwired to 0.
66 MHz PCI Capable (66C).
N/A - Hardwired to 0.
Capability List (CLIST):
This bit is set to 1 to indicate that the register at 34h provides an offset into the
function’s PCI Configuration Space containing a pointer to the location of the first
item in the list.
Interrupt Status:
This bit reflects the state of the interrupt in the device. Only when the Interrupt
Disable bit in the command register is a 0 and this Interrupt Status bit is a 1, will the
devices INTx# signal be asserted. Setting the Interrupt Disable bit to a 1 has no
effect on the state of this bit.
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
195
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.5
RID2—Revision Identification
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
08h
00h
RO
8 bits
This register contains the revision number for Device #2 Functions 0 and 1
7.2.6
Bit
Access &
Default
Description
7:0
RO
Revision Identification Number (RID):
00 h
This is an 8-bit value that indicates the revision identification number for the
GMCH.
CC—Class Code
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
09h
030000h
RO
24 bits
This register contains the device programming interface information related to the Sub-Class Code and
Base Class Code definition for the IGD. This register also contains the Base Class Code and the
function sub-class in relation to the Base Class Code.
Bit
Access &
Default
23:16
RO
Base Class Code (BCC)
03 h
This is an 8-bit value that indicates the base class code for the GMCH. This code
has the value 03h, indicating a Display Controller.
RO
Sub-Class Code (SUBCC):
00 h
Based on Device #0 DAFC[VGA Disable], which is also mirrored in device #2
MDAFCdev0f0[VGA Disable]
15:8
Description
00h: VGA compatible
80h: Non VGA
7:0
RO
00 h
196
Programming Interface (PI)
00h: Hardwired as a Display controller.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.7
CLS—Cache Line Size
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
0Ch
00h
RO
8 bits
The IGD does not support this register as a PCI slave.
Bit
Access &
Default
7:0
RO
00 h
7.2.8
Description
Cache Line Size (CLS)
This field is hardwired to 0s. The IGD as a PCI compliant master does not use the
Memory Write and Invalidate command and, in general, does not perform
operations based on cache line size.
MLT2—Master Latency Timer
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
0Dh
00h
RO
8 bits
The IGD does not support the programmability of the master latency timer because it does not perform
bursts.
Bit
Access &
Default
7:0
RO
00 h
Description
Master Latency Timer Count Value
Hardwired to 0s.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
197
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.9
HDR2—Header Type
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
0Eh
80h
RO
8 bits
This register contains the Header Type of the IGD.
Bit
Access &
Default
7
RO
1b
6:0
RO
0000000 b
7.2.10
Description
Multi Function Status (MFunc)
Indicates if the device is a Multi-Function Device. The Value of this register is
determined by Device #0, offset 54h, DEVEN[4].. If Device #0 DEVEN[4] is set,
the MFunc bit is also set.
Header Code (H)
This is an 7-bit value that indicates the Header Code for the IGD. This code has the
value 00h, indicating a type 0 configuration space format.
MMADR—Memory Mapped Range Address
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
10h
00000000h
RO, R/W
32 bits
This register requests allocation for the IGD registers and instruction ports. The allocation is for 512 kB
and the base address is defined by bits [31:19].
Bit
Access &
Default
31:19
R/W
0000 h
18:4
RO
0000 h
3
RO
0b
2:1
RO
00 b
0
RO
0b
198
Description
Memory Base Address:
Set by the OS, these bits correspond to address signals [31:19].
Address Mask:
Hardwired to 0s to indicate 512 KB address range.
Prefetchable Memory:
Hardwired to 0 to prevent pre-fetching.
Memory Type:
Hardwired to 0s to indicate 32-bit address.
Memory / IO Space:
Hardwired to 0 to indicate memory space.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.11
IOBAR—I/O Base Address
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
14h
00000001h
RO, R/W
32 bits
This register provides the Base offset of the I/O registers within Device #2. Bits 15:3 are programmable
allowing the I/O Base to be located anywhere in 16bit I/O Address Space. Bits 2:1 are fixed and return
zero, bit 0 is hardwired to a one indicating that 8 bytes of I/O space are decoded.
Access to the 8Bs of IO space is allowed in PM state D0 when IO Enable (PCICMD bit 0) set. Access
is disallowed in PM states D1-D3 or if IO Enable is clear or if Device #2 is turned off or if Internal
graphics is disabled. Note that access to this IO BAR is independent of VGA functionality within
Device #2. Also note that this mechanism in available only through function 0 of Device#2 and is not
duplicated in function #1.
If accesses to this IO bar are allowed then the GMCH claims all 8, 16 or 32 bit IO cycles from the CPU
that falls within the 8B claimed.
Bit
Access &
Default
Reserved.
31:16
15:3
R/W
0000 h
2:1
RO
00 b
0
Description
RO
1b
IO Base Address:
Set by the OS, these bits correspond to address signals [15:3].
Memory Type:
Hardwired to 0s to indicate 32-bit address.
Memory / IO Space:
Hardwired to 1 to indicate I/O space.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
199
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.12
GMADR—Graphics Memory Range Address
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
18h
00000000h
RO, R/W, R/W/L
32 bits
IGD graphics memory base address is specified in this register.
Bit
Access &
Default
31:28
R/W
0h
27
R/W/L
0b
26:4
RO
000000 h
3
RO
1b
2:1
RO
00 b
0
RO
0b
200
Description
Memory Base Address:
Set by the OS, these bits correspond to address signals [31:28].
256 MB Address Mask:
This bit is either part of the Memory Base Address (R/W) or part of the Address
Mask (RO), depending on the value of MSAC[1]. See MSAC (Dev 2, Func 0, offset
62) for details.
Address Mask:
Hardwired to 0s to indicate at least 128 B address range
Prefetchable Memory:
Hardwired to 1 to enable prefetching
Memory Type:
Hardwired to 0 to indicate 32-bit address.
Memory/IO Space:
Hardwired to 0 to indicate memory space.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.13
GTTADR—Graphics Translation Table Range Address
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
1Ch
00000000h
RO, R/W
32 bits
This register requests allocation for Graphics Translation Table Range. The allocation is for 256 kB
and the base address is defined by bits [31:18].
Bit
Access &
Default
31:18
R/W
0000 h
17:4
RO
0000 h
3
RO
0b
2:1
RO
00 b
0
RO
0b
7.2.14
Description
Memory Base Address:
Set by the OS, these bits correspond to address signals [31:18].
Address Mask:
Hardwired to 0s to indicate 256 kB address range.
Prefetchable Memory:
Hardwired to 0 to prevent prefetching.
Memory Type:
Hardwired to 0s to indicate 32-bit address.
Memory/IO Space:
Hardwired to 0 to indicate memory space.
SVID2—Subsystem Vendor Identification
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
Bit
Access
&
Default
15:0
R/WO
0000 h
2
0
2Ch
0000h
R/WO
16 bits
Description
Subsystem Vendor ID.
This value is used to identify the vendor of the subsystem. This register should
be programmed by BIOS during boot-up. Once written, this register becomes
Read Only. This register can only be cleared by a Reset.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
201
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.15
SID2—Subsystem Identification
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:0
R/WO
0000 h
7.2.16
2
0
2Eh
0000h
R/WO
16 bits
Description
Subsystem Identification.
This value is used to identify a particular subsystem. This field should be
programmed by BIOS during boot-up. Once written, this register becomes Read
Only. This register can only be cleared by a Reset.
ROMADR—Video BIOS ROM Base Address
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
30h
00000000h
RO
32 bits
The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0s.
Bit
Access &
Default
31:18
RO
Description
ROM Base Address: Hardwired to 0’s.
0000 h
17:11
RO
Address Mask: Hardwired to 0s to indicate 256 KB address range.
00 h
Reserved.
10:1
0
RO
ROM BIOS Enable: 0 = ROM not accessible.
0b
202
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.17
CAPPOINT—Capabilities Pointer
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
7:0
RO
D0 h
7.2.18
2
0
34h
D0h
RO
8 bits
Description
Capabilities Pointer Value.
This field contains an offset into the function’s PCI Configuration Space for the first
item in the New Capabilities Linked List, the Power Management Capabilities ID
registers at address D0h.
INTRLINE—Interrupt Line
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
7:0
R/W
00 h
7.2.19
2
0
3Ch
00h
R/W
8 bits
Description
Interrupt Connection.
Used to communicate interrupt line routing information. POST software writes the
routing information into this register as it initializes and configures the system. The
value in this register indicates which input of the system interrupt controller that the
device’s interrupt pin is connected to.
INTRPIN—Interrupt Pin
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
7:0
RO
01 h
2
0
3Dh
01h
RO
8 bits
Description
Interrupt Pin.
As a single function device, the IGD specifies INTA# as its interrupt pin.
01h: INTA#.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
203
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.20
MINGNT—Minimum Grant
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
7:0
RO
00 h
7.2.21
Description
Minimum Grant Value.
The IGD does not burst as a PCI compliant master.
MAXLAT—Maximum Latency
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
7.2.22
2
0
3Eh
00h
RO
8 bits
2
0
3Fh
00h
RO
8 bits
Bit
Access &
Default
Description
7:0
RO
Maximum Latency Value.
00 h
The IGD has no specific requirements for how often it needs to access the PCI
bus.
MCAPPTR—Mirror of Dev0 Capability Pointer
(Mirrored_D0_34)
PCI Device:
Function:
Address Offset:
Size:
2
0
44h
8 bits
This register is a Read-Only copy of Device 0, Offset 34h register.
7.2.23
MCAPID—Mirror of Dev0 Capability Identification
(Mirrored_D0_E0)
PCI Device:
Function:
Address Offset:
Size:
2
0
48h
72 bits
This register is a Read-Only copy of Device 0, Offset E0h register.
204
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.24
MGGC—Mirror of Dev0 GMCH Graphics Control
(Mirrored_D0_52)
PCI Device:
Function:
Address Offset:
Size:
2
0
52h
16 bits
This register is a Read-Only copy of Device 0, Offset 52h register.
7.2.25
MDEVENdev0f0—Mirror of Dev0 Device Enable
(Mirrored_D0_54)
PCI Device:
Function:
Address Offset:
Size:
2
0
54h
32 bits
This register is a Read-Only copy of Device 0, Offset 54h register.
7.2.26
BSM—Base of Stolen Memory
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
5Ch
07800000h
RO
32 bits
Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From the top of
low used DRAM, GMCH claims 1 to 64MBs of DRAM for internal graphics if enabled.
Bit
Access &
Default
31:20
RO
078 h
19:0
Description
Base of Stolen Memory (BSM):
This register contains bits 31 to 20 of the base address of stolen DRAM memory.
The host interface determines the base of Graphics Stolen memory by subtracting
the graphics stolen memory size from TOLUD. See Device 0 TOLUD for more
explanation.
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
205
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.27
MSAC—Multi Size Aperture Control
PCI Device:
Function:
Address Offset:
Default Address:
Access:
Size:
2
0
62h
00h
RO, R/W
8 bits
This register determines the size of the graphics memory aperture in function 0 and in the trusted space.
By default, the aperture size is 256 MB (bit 27 read only). If bit 1 is set to a 1, then the aperture size is
limited to 128 MB. Only the system BIOS will write this register based on pre-boot address allocation
efforts, but the graphics may read this register to determine the correct aperture size. System BIOS
needs to save this value on boot so that it can reset it correctly during S3 resume.
Bit
Access &
Default
7:4
R/W
0h
3:2
1
R/W
0b
0
7.2.28
Description
Scratch Bits Only -- Have no physical effect on hardware
Reserved
256MB Aperture Disable
0: Bit 27 of GMADR and the equivalent trusted memory aperture is read-only,
allowing 256 MB of address space to be mapped.
1: Bit 27 of GMADR and the equivalent trusted memory aperture is readwrite, limiting the address space to 128 MB.
Reserved
GDRST—Graphics Debug Reset (D2:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
Description
Reserved
7:2
1
2
C0h
00h
RO, R/W
8 bits
RO
0b
Graphics Reset Status
0:
Graphics subsystem not in Reset.
1:
Graphics Subsystem in Reset as a result of Graphics Debug Reset.
This bit gets is set to a ‘1’ when Graphics debug reset bit is set to a ‘1’ and the
Graphics hardware has completed the debug reset sequence and all Graphics assets
are in reset. This bit is cleared when Graphics Debug Reset bit is set to a ‘0’.
0
R/W
0b
Graphics Debug Reset:
1 = assert display and render domain reset
0 = de-assert display and render domain reset
Render and Display clock domain resets should be asserted for at least 20 μsecs.
Once this bit is set to a “1” all GFX core MMIO registers are returned to power on
default state. Device 2 IO registers are not available.
Device 2 Config registers are available when Graphics debug reset is asserted.
206
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.29
PMCAPID—Power Management Capabilities ID
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
Bit
15:8
7:0
7.2.30
2
0
D0h
0001h
RO
16 bits
Access &
Default
Description
RO
NEXT_PTR.
00 h
This contains a pointer to next item in capabilities list. This is the final capability in
the list and must be set to 00h.
RO
CAP_ID.
01 h
SIG defines this ID is 01h for power management.
PMCAP—Power Management Capabilities
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
Bit
15:11
Access &
Default
RO
00000 b
10
9
4
3
PME Support.
This field indicates the power states in which the IGD may assert PME#. Hardwired
to 0 to indicate that the IGD does not assert the PME# signal.
D2.
0b
The D2 power management state is not supported. This bit is hardwired to 0.
RO
D1.
0b
Hardwired to 0 to indicate that the D1 power management state is not supported.
Reserved
RO
Device Specific Initialization (DSI).
1b
Hardwired to 1 to indicate that special initialization of the IGD is required before
generic class device driver is to use it.
RO
Auxiliary Power Source.
0b
Hardwired to 0.
RO
0b
2:0
Description
RO
8:6
5
2
0
D2h
0022h
RO
16 bits
RO
010 b
PME Clock.
Hardwired to 0 to indicate IGD does not support PME# generation.
Version.
Hardwired to 010b to indicate that there are 4 bytes of power management
registers implemented and that this device complies with revision 1.1 of the PCI
Power Management Interface Specification
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
207
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.31
PMCS—Power Management Control/Status
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15
RO
0b
14:9
8
Description
PME_Status:
This bit is 0 to indicate that IGD does not support PME# generation from D3 (cold).
Reserved
RO
0b
7:2
1:0
2
0
D4h
0000h
RO, R/W
16 bits
PME_En:
This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
Reserved
R/W
PowerState:
00 b
This field indicates the current power state of the IGD and can be used to set the
IGD into a new power state. If software attempts to write an unsupported state to
this field, write operation must complete normally on the bus, but the data is
discarded and no state change occurs.
On a transition from D3 to D0 the graphics controller is optionally reset to initial
values. Behavior of the graphics controller in supported states is detailed in the
power management section.
Bits[1:0] Power state
7.2.32
00
D0 Default
01
D1 Not Supported
10
D2 Not Supported
11
D3
SWSMI—Software SMI
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
E0h
0000h
R/W
16 bits
As long as there is the potential that DVO port legacy drivers exist which expect this register at this
address, Dev#2F0address E0h-E1h must be reserved for this register.
Bit
Access &
Default
15:8
R/W
00 h
R/W
00 h
R/W
0b
7:1
0
208
Description
SW scratch bits
Software Flag
Used to indicate caller and SMI function desired, as well as return result
GMCH Software SMI Event
When Set this bit will trigger an SMI.
Software must write a 0 to clear this bit
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.33
GCFGC—Graphics Clock Frequency and Gating Control
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
Bit
Access &
Default
15:14
R/W
2
0
F0h
0000h
RO, R/W
16 bits
Description
Reserved
0b
13
R/W
GFX GVL low frequency Enable.
0b
0 = Do not Use GFX GVL low frequency target for Render Clock.
1 = Use GFX GVL low frequency target for Render Clock.
12
R/W
GFX GVL low frequency target.
0b
0 = 133 MHz (Default Value).
1 = Reserved.
11
10
9
8
7
R/W
Gate Core Render Clock (GCRC):
0b
0:
Core render clock (crclk) is running
1:
Core render clock (crclk) is gated
R/W
Asynchronously Change Core Render Clock (ACCRC):
0b
A 0 to 1 transition on this bit will immediately load new pre- and post-divider values
for the crclk and crx2clk. Writing 1 to 1, 1 to 0, and 0 to 0 have no effect.
R/W
Gate Core Display Clock (GCRC):
0b
0:
Core display clock (cdclk) is running
1:
Core display clock (cdclk) is gated
R/W
Asynchronously Change Core Display Clock (ACCDC):
0b
A 0 to 1 transition on this bit will immediately load new pre- and post-divider values
for the cdclk. Writing 1 to 1, 1 to 0, and 0 to 0 have no effect.
R/W
Core Display Low Frequency Enable
0b
0 = Do not Use low frequency target (133 MHz) for Display Clock.
1 = Use low frequency target (133 MHz) for Display Clock.
NOTE: If using 133 MHz cdclk,, Please refer to the PRD for max display resolution
6:4
R/W
Graphics Core Display Clock Select.
000 b
000 = 190/200 MHz (Intel 915GM / 915GME / 915GMS & Intel 910GML /
910GMLE)
001 - 011 = Reserved
100 = 333 MHz (Intel 915GM / 915GME @ 1.5 V only)
101 - 111 = Reserved
3
2:0
Reserved
R/W
Graphics Core Render Clock Select.
000 b
000 = 160/166 MHz (Intel 915GM / 915GME / 915GMS & Intel 910GML /
910GMLE)
001 = 190/200 MHz (Intel 915GM)
010 – 011 = Reserved
100 = 333 MHz (Intel 915GM / 915GME @ 1.5 V only)
101 - 111 = Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
209
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.34
LBB—Legacy Backlight Brightness
PCI Device:
Function:
Address Offset:
Size:
2
0
F4h
32 bits
This register can be accessed by either Byte, Word, or Dword PCI config cycles. A write to this register
will cause the Backlight Event (Display B Interrupt) if enabled.
Bit
Description
31:24
LBPC Scratch Trigger 3 –
When written, this scratch byte triggers an interrupt when LBEE is enabled in the
Pipe B Status register and the Display B Event is enabled in IER and unmasked in
IMR etc. If written as part of a 16-bit or 32-bit write, only one interrupt is generated
in common.
23-16
LBPC Scratch Trigger 2 –
When written, this scratch byte triggers an interrupt when LBEE is enabled in the
Pipe B Status register and the Display B Event is enabled in IER and unmasked in
IMR etc. If written as part of a 16-bit or 32-bit write, only one interrupt is generated
in common.
15-8
LBPC Scratch Trigger 1 –
When written, this scratch byte triggers an interrupt when LBEE is enabled in the
Pipe B Status register and the Display B Event is enabled in IER and unmasked in
IMR etc. If written as part of a 16-bit or 32-bit write, only one interrupt is generated
in common.
7:0
Legacy Backlight Brightness
The value of zero is the lowest brightness setting and 255 is the brightest.
210
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.35
ASLS—ASL Storage
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
0
FCh
00000000h
R/W
32 bits
This software scratch register only needs to be read/write accessible. The exact bit register usage must
be worked out in common between System BIOS and driver software, but storage for
switching/indicating up to 6 devices is possible with this amount. For each device, the ASL control
method with require two bits for _DOD (BIOS detectable yes or no, VGA/NonVGA), one bit for
_DGS (enable/disable requested), and two bits for _DCS (enabled now/disabled now, connected or
not).
Bit
Access &
Default
31:0
R/W
Description
RW according to a software controlled usage to support device switching
00000000 h
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
211
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.36
Device #2 Function 1 Configuration Register Details
Table 7-2. Device #2 Function 1 Configuration Register Summary Table
Address
offset (h)
Register
Symbol
Default
Value
Access
00-01h
VID2
Vendor Identification
02-03h
DID2
Device Identification
04-05h
PCICMD2
PCI Command
0000h
RO, R/W
06-07h
PCISTS2
PCI Status
0090h
RO
08h
RID2
Revision Identification
09-0Bh
CC
Class Code Register
038000h
RO
0Ch
CLS
Cache Line Size
0Dh
MLT2
Master Latency Timer
0Eh
HDR2
Header Type Register
00000000h
RO, R/W
0Fh
10-13h
Reserved (1 B)
MMADR
14-2Bh
Memory Mapped Range Address
Reserved (24 B)
2C-2Dh
SVID2
Subsystem Vendor Identification
2E-2Fh
SID2
Subsystem Identification
30-33h
ROMADR
Video BIOS ROM Base Address
34h
CAPPOINT
Capabilities Pointer
35-3Dh
Reserved (9 B)
3Eh
MINGNT
Minimum Grant Register
3Fh
MAXLAT
Maximum Latency
40-43h
44h
Reserved (4 B)
MCAPPTR
45-47h
48-50h
Mirror of Dev0 Capability Pointer
Reserved
MCAPID
51h
Mirror of Dev0 Capability Identification
Reserved
52-53h
MGGC
Mirror of Dev0 GMCH Graphics Control
54-57h
MDEVENdev
0f0
Mirror of Dev0 Device Enable
58-5Bh
5C-5Fh
212
Register Name
Reserved
BSM
Base of Stolen Memory Register
60-C0h
Reserved
C1-C2h
Reserved
C3-CFh
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
Address
offset (h)
Register
Symbol
D0-D1h
PMCAPID
Power Management Capabilities ID
D2-D3h
PMCAP
Power Management Capabilities
D4-D5h
PMCS
Power Management Control/Status
D6-DFh
E0-E1h
Default
Value
Access
0000h
RO, R/W
00000000h
R/W
Reserved
SWSMI
E2-F3h
7.2.37
Register Name
Software SMI
Reserved
F4-F7h
LBB
Legacy Backlight Brightness
FC-FFh
ASLS
ASL Storage
VID2—Vendor Identification
PCI Device:
Function:
Address Offset:
Size:
2
1
00h
16 bits
This register is a Read Only copy of Function 0. Write attributes as D2:F0. It is implemented as
common hardware with two access addresses.
7.2.38
DID2—Device Identification
PCI Device:
Function:
Address Offset:
Size:
2
1
02h
16 bits
This register is unique in Function 1 (the Function 0 DID is separate). This difference in Device ID is
necessary for allowing distinct Plug and Play enumeration of function 1 when both function 0 and
function 1 have the same class code.
Bit
15:0
Access
&
Default
Description
RO
Device Identification Number (DID): This is a 16 bit value assigned to the GMCH
Graphic device Function 1
2790h
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
213
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.39
PCICMD2—PCI Command
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
1
04h
0000h
RO, R/W
16 bits
This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The
PCICMD Register in the IGD disables the IGD PCI compliant master accesses to main memory.
Bit
Access &
Default
Reserved.
15:10
9
RO
0b
8
RO
0b
7
RO
0b
6
RO
0b
5
RO
0b
4
RO
0b
3
RO
0b
2
R/W
0b
1
R/W
0b
0
R/W
0b
214
Description
Fast Back-to-Back (FB2B):
Not Implemented. Hardwired to 0.
SERR Enable (SERRE):
Not Implemented. Hardwired to 0.
Address/Data Stepping Enable (ADSTEP):
Not Implemented. Hardwired to 0.
Parity Error Enable (PERRE):
Not Implemented. Hardwired to 0.
Since the IGD belongs to the category of devices that does not corrupt programs or
data in system memory or hard drives, the IGD ignores any parity error that it
detects and continues with normal operation.
VGA Palette Snoop Enable (VGASNOOP):
This bit is hardwired to 0 to disable snooping.
Memory Write and Invalidate Enable (MWIE):
Hardwired to 0. The IGD does not support memory write and invalidate commands.
Special Cycle Enable (SCE):
This bit is hardwired to 0. The IGD ignores Special cycles.
Bus Master Enable (BME):
Set to 1 to enable the IGD to function as a PCI compliant master.
Set to 0 to disable IGD bus mastering.
Memory Access Enable (MAE):
This bit controls the IGD’s response to memory space accesses.
0:
Disable.
1:
Enable.
I/O Access Enable (IOAE):
This bit controls the IGD’s response to I/O space accesses.
0:
Disable.
1:
Enable.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.40
PCISTS2—PCI Status
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
1
06h
0090h
RO
16 bits
PCISTS is a 16-bit status register that reports the occurrence of a PCI compliant master abort and PCI
compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD.
Bit
Access &
Default
15
RO
0b
14
RO
0b
13
RO
0b
12
RO
0b
11
RO
0b
10:9
RO
00 b
8
7
6
The IGD never asserts SERR#, therefore this bit is hardwired to 0.
Received Master Abort Status (RMAS):
The IGD never gets a Master Abort, therefore this bit is hardwired to 0.
Received Target Abort Status (RTAS):
The IGD never gets a Target Abort, therefore this bit is hardwired to 0.
Signaled Target Abort Status (STAS):
Hardwired to 0. The IGD does not use target abort semantics.
DEVSEL Timing (DEVT):
These bits are hardwired to "00".
Since Parity Error Response is hardwired to disabled (and the IGD does not do any
parity detection), this bit is hardwired to 0.
RO
Fast Back-to-Back (FB2B):
1b
Hardwired to 1. The IGD accepts fast back-to-back when the transactions are not
to the same agent.
RO
User Defined Format (UDF).
RO
RO
RO
0b
2:0
Signaled System Error (SSE):
0b
1b
3
Since the IGD does not detect parity, this bit is always hardwired to 0.
Master Data Parity Error Detected (DPD):
0b
4
Detected Parity Error (DPE):
RO
0b
5
Description
Hardwired to 0.
66 MHz PCI Capable (66C).
N/A - Hardwired to 0.
Capability List (CLIST):
This bit is set to 1 to indicate that the register at 34h provides an offset into the
function’s PCI Configuration Space containing a pointer to the location of the first
item in the list.
Interrupt Status:
Hardwired to 0.
Reserved
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
215
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.41
RID2—Revision Identification
PCI Device:
Function:
Address Offset:
Size:
2
1
08h
8 bits
This register is a copy of Function 0. It has the same Read, Write attributes as Function 0. It is
implemented as common hardware with two access addresses.
7.2.42
CC—Class Code Register
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
1
09h
038000h
RO
24 bits
This register contains the device programming interface information related to the Sub-Class Code and
Base Class Code definition for the IGD. This register also contains the Base Class Code and the
function sub-class in relation to the Base Class Code.
Bit
Access &
Default
23:16
RO
Base Class Code (BCC)
03 h
This is an 8-bit value that indicates the base class code for the GMCH. This code
has the value 03h, indicating a Display Controller.
RO
Sub-Class Code (SUBCC)
15:8
80 h
7:0
RO
00 h
7.2.43
Description
80h: Non VGA
Programming Interface (PI)
00h: Hardwired as a Display controller.
CLS—Cache Line Size
PCI Device:
Function:
Address Offset:
Size:
2
1
0Ch
8 bits
This register is a Read Only copy of Function 0.
7.2.44
MLT2—Master Latency Timer
PCI Device:
Function:
Address Offset:
Size:
2
1
0Dh
8 bits
This register is a Read Only copy of Function 0.
216
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Internal Graphics Device #2 Configuration Register (D2:F0)
R
7.2.45
HDR2—Header Type Register
PCI Device:
Function:
Address Offset:
Size:
2
1
0Eh
8 bits
This register is a Read Only copy of Function 0.
7.2.46
MMADR—Memory Mapped Range Address
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
1
10h
00000000h
RO, R/W
32 bits
This register requests allocation for the IGD registers and instruction ports. The allocation is for 512 kB
and the base address is defined by bits [31:19].
Bit
Access &
Default
31:19
R/W
0000 h
18:4
RO
0000 h
3
RO
0b
2:1
RO
00 b
0
RO
0b
7.2.47
Description
Memory Base Address:
Set by the OS, these bits correspond to address signals [31:19].
Address Mask:
Hardwired to 0s to indicate 512 kB address range.
Prefetchable Memory:
Hardwired to 0 to prevent prefetching.
Memory Type:
Hardwired to 0s to indicate 32-bit address.
Memory / IO Space:
Hardwired to 0 to indicate memory space.
SVID2—Subsystem Vendor Identification
PCI Device:
Function:
Address Offset:
Size:
2
1
2Ch
16 bits
This register is a Read Only copy of Function 0. It has the same Read-Write attributes as D2:F0. It is
implemented as common hardware with two access addresses.
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7.2.48
SID2—Subsystem Identification
PCI Device:
Function:
Address Offset:
Size:
2
1
2Eh
16 bits
This register is a Read Only copy of Function 0.
7.2.49
ROMADR—Video BIOS ROM Base Address
PCI Device:
Function:
Address Offset:
Size:
2
1
30h
32 bits
This register is a Read Only copy of Function 0. It has the same Read-Write attributes as D2:F0. It is
implemented as common hardware with two access addresses.
7.2.50
CAPPOINT—Capabilities Pointer
PCI Device:
Function:
Address Offset:
Size:
2
1
34h
8 bits
This register is a Read Only copy of Function 0. It has the same Read-Write attributes as D2:F0. It is
implemented as common hardware with two access addresses.
7.2.51
MINGNT—Minimum Grant Register
PCI Device:
Function:
Address Offset:
Size:
2
1
3Eh
8 bits
This register is a Read Only copy of Function 0. It has the same Read-Write attributes as D2:F0. It is
implemented as common hardware with two access addresses.
7.2.52
MAXLAT—Maximum Latency
PCI Device:
Function:
Address Offset:
Size:
2
1
3Fh
8 bits
This register is a Read Only copy of Function 0. It has the same Read-Write attributes as D2:F0. It is
implemented as common hardware with two access addresses.
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Internal Graphics Device #2 Configuration Register (D2:F0)
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7.2.53
MCAPPTR—Mirror of Dev0 Capability Pointer
(Mirrored_D0_34)
PCI Device:
Function:
Address Offset:
Size:
2
1
44h
8 bits
This register is a Read-Only copy of Device 0, Offset 34h register.
7.2.54
MCAPID—Mirror of Dev0 Capability Identification
(Mirrored_D0_E0)
PCI Device:
Function:
Address Offset:
Size:
2
1
48h
72 bits
This register is a Read-Only copy of Device 0, Offset E0h register.
7.2.55
MGGC—Mirror of Dev0 GMCH Graphics Control
(Mirrored_D0_52)
PCI Device:
Address Offset:
Size:
2
52h
16 bits
This register is a Read-Only copy of Device 0, Offset 52h register.
7.2.56
MDEVENdev0f0—Mirror of Dev0 Device Enable
(Mirrored_D0_54)
PCI Device:
Function:
Address Offset:
Size:
2
1
54h
32 bits
This register is a Read-Only copy of Device 0, Offset 54h register.
7.2.57
BSM—Base of Stolen Memory Register
PCI Device:
Function:
Address Offset:
Size:
2
1
5Ch
32 bits
This register is a Read Only copy of Function 0
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7.2.58
PMCAPID—Power Management Capabilities ID
PCI Device:
Function:
Address Offset:
Size:
2
1
D0h
16 bits
This register is a copy of Function 0. It has the same Read, Write attributes as Function 0. It is
implemented as common hardware with two access addresses.
7.2.59
PMCAP—Power Management Capabilities
PCI Device:
Function:
Address Offset:
Size:
2
1
D2h
16 bits
This register is a copy of Function 0. It has the same Read, Write attributes as Function 0. It is
implemented as common hardware with two access addresses.
7.2.60
PMCS—Power Management Control/Status
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
1
D4h
0000h
RO, R/W
16 bits
Bit
Access &
Default
Description
15
RO
PME_Status:
0b
This bit is 0 to indicate that IGD does not support PME# generation from D3
(cold).
Reserved:
14:9
The IGD does not support data register. This bit always returns 0 when read, write
operations have no effect.
8
RO
0b
This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
Reserved.
7:2
1:0
PME_En:
R/W
00 b
PowerState:
This field indicates the current power state of the IGD and can be used to set the
IGD into a new power state. If software attempts to write an unsupported state to
this field, write operation must complete normally on the bus, but the data is
discarded and no state change occurs.
On a transition from D3 to D0 the graphics controller is optionally reset to initial
values.
Bits[1:0] Power state
220
00
D0 Default
01
D1 Not Supported
10
D2 Not Supported
11
D3
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Internal Graphics Device #2 Configuration Register (D2:F0)
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7.2.61
SWSMI—Software SMI
PCI Device:
Function:
Address Offset:
Size:
2
1
E0h
16 bits
This register is a copy of Function 0. It has the same Read, Write attributes as Function 0. It is
implemented as common hardware with two access addresses.
7.2.62
LBB—Legacy Backlight Brightness
PCI Device:
Function:
Address offset:
Size:
2
1
F4h
32 bits
This register is a copy of Function 0. It has the same Read, Write attributes as Function 0. It is
implemented as common hardware with two access addresses.
7.2.63
ASLS—ASL Storage
PCI Device:
Function:
Address Offset:
Default Value:
Access:
Size:
2
1
FCh
00000000h
R/W
32 bits
This software scratch register only needs to be read/write accessible. The exact bit register usage must
be worked out in common between System BIOS and driver software, but storage for
switching/indicating up to 6 devices is possible with this amount. For each device, the ASL control
method with require two bits for _DOD (BIOS detectable yes or no, VGA/NonVGA), one bit for
_DGS (enable/disable requested), and two bits for _DCS (enabled now/disabled now, connected or
not).
Bit
Access &
Default
31:0
R/W
Description
R/W according to a software controlled usage to support device switching
00000000 h
7.3
Device #2 – PCI I/O Registers
The following are not PCI config registers; they are I/O registers. This mechanism allows access to
internal graphics MMIO registers must not be used to access VGA IO registers which are mapped
through the MMIO space. VGA registers must be accessed directly through the dedicated VGA IO
ports.
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7.3.1
MMIO Index—MMIO Address Register
I/O Address:
Default Value:
Access:
Size:
IOBAR + 0h
00000000h
R/W
32 bits
MMIO_INDEX: A 32 bit IO write to this port loads the offset of the MMIO register that needs to be
accessed. An IO Reads returns the current value of this register. An 8/16 bit IO write to this register is
completed by the GMCH but does not update this register. This mechanism allows access to internal
graphics MMIO registers must not be used to access VGA IO registers which are mapped through the
MMIO space. VGA registers must be accessed directly through the dedicated VGA IO ports.
Bit
Access &
Default
31:2
R/W
Register/GTT Offset:
00000000 h
1:0
Description
This field selects any one of the DWORD registers within the MMIO
register space of Device #2.
Reserved
R/W
00 b
7.3.2
MMIO Data—MMIO Data Register
I/O Address:
Default Value:
Access:
Size:
IOBAR + 4h
00000000h
R/W
32 bits
MMIO_DATA A 32 bit IO write to this port is re-directed to the MMIO register location pointed to by
the MMIO-index register. A 32 bit IO read to this port is re-directed to the MMIO register address
pointed to by the MMIO-index register regardless of the target selection in MMIO_INDEX(1:0). 8-bit
or 16-bit IO writes are completed by the GMCH and may have un-intended side effects, hence must not
be used to access the data port. 8-bit or 16-bit IO reads are completed normally.
Bit
Access &
Default
31:0
R/W
Description
MMIO data window
00000000 h
§
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8
System Address Map
The GMCH supports 4 GB of addressable memory space and 64 kB+3 of addressable I/O space. There
is a programmable memory address space under the 1-MB region which is divided into regions which
can be individually controlled with programmable attributes such as Disable, Read/Write, Write Only,
or Read Only. Attribute programming is described in the Register Description section. This section
focuses on how the memory space is partitioned and what the separate memory regions are used for.
I/O address space has simpler mapping and is explained near the end of this section.
Addressing of memory ranges larger than 4 GB is NOT supported. The HREQ [4:3] FSB pins are
decoded to determine whether the access is above or below 4 GB.
The GMCH does not support the PCI Dual Address Cycle (DAC) Mechanism, PCI Express 64-bit
prefetchable memory transactions, or any other addressing mechanism that allows addressing of greater
than 4 GB on either the DMI or PCI Express interface. The GMCH does not limit DRAM space in
hardware. There is no hardware lock to stop someone from inserting more memory than is addressable.
In the following sections, it is assumed that all of the compatibility memory ranges reside on the DMI.
The exception to this rule is VGA ranges, which may be mapped to PCI Express, DMI, or to the
internal graphics device (IGD). In the absence of more specific references, cycle descriptions
referencing PCI should be interpreted as the DMI/PCI, while cycle descriptions referencing PCI
Express or IGD are related to the PCI Express bus or the internal graphics device respectively. The
GMCH does not remap APIC or any other memory spaces above TOLUD (Top of Low Usable
DRAM). The TOLUD register is set to the appropriate value by BIOS.
The Address Map includes a number of programmable ranges:
Device 0:
EPBAR
Egress port registers. Necessary for setting up VC1 as an isochronous channel. (4 kB
window)
MCHBAR Memory mapped range for internal GMCH registers. For example, memory buffer
register controls. (16 kB window)
PCIEXBAR Flat memory-mapped address spaced to access device configuration registers. This
mechanism can be used to access PCI configuration space (0-FFh) and Extended configuration
space (100h-FFFh) for PCI Express devices. This enhanced configuration access mechanism
is defined in the PCI Express specification. (256-MB window).
DMIBAR This window is used to access registers associated with the MCH/ICH (DMI) register
memory range. (4 kB window)
GGC – GMCH graphics control register. Used to select the amount of main memory that is preallocated to support the internal graphics device in VGA (non-linear) and Native (linear)
modes. (0-64 MB options).
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Device 1, Function 0:
MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window.
PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window.
IOBASE1/IOLIMIT1 – PCI Express port IO access window.
Device 2, Function 0:
MMADR – IGD registers and internal graphics instruction port. (512 kB window)
IOBAR – I/O access window for internal graphics. Through this window address/data register
pair, using I/O semantics, the IGD and internal graphics instruction port registers can be
accessed.
GMADR – Internal graphics translation window. (256-MB window)
GTTADR – Internal graphics translation table location. (256 kB window).
Device 2, Function 1:
MMADR – Function 1 IGD registers and internal graphics instruction port. (512 kB window)
IOBAR – Function 1 IO access window for internal graphics.
The rules for the above programmable ranges are:
1. ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or system
designer’s responsibility to limit memory population so that adequate PCI, PCI Express, High
BIOS, PCI Express Memory Mapped space, and APIC memory space can be allocated.
2. In the case of overlapping ranges with memory, the memory decode will be given priority.
3. There are NO Hardware Interlocks to prevent problems in the case of overlapping ranges.
4. Accesses to overlapped ranges may produce indeterminate results.
5. The only peer-to-peer cycles allowed below the top of memory (register TOLUD) are DMI to PCI
Express VGA range writes. Note that peer to peer cycles to the Internal Graphics VGA range are
not supported.
The following figure represents system memory address map in a simplified form.
Figure 8-1. System Address Ranges
4 GB
PCI Memory
Address
Range
(subtractively
Decoded)o
Device 0
BARS
(EPBAR,
MCHBAR,
PCIEXBAR,
DMIBAR
Device 1
Device 2
(MBASE1/
MLIMIT1,
PMBASE1/
PMLIMIT1)
(MMADR,
GMADR,
GTTADR, )
TOLUD
Main
Memory
Address
Rang e
Device 0
GGC
(Graphics
Stolen
Memory)
Independently Programmable
Non - Overlapping
Windows
1 MB
Legacy
Address
Range
0
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8.1
Legacy Address Range
This area is divided into the following address regions:
0 - 640 kB – DOS Area
640 - 768 kB – Legacy Video Buffer Area
768 - 896 kB in 16 kB sections (total of eight sections) – Expansion Area
896 -960 kB in 16 kB sections (total of four sections) – Extended System BIOS Area
960 kB - 1 MB memory – system BIOS Area
Figure 8-2. DOS Legacy Address Range
1MB
000F_FFFFh
System BIOS (Upper)
000F_0000h
64KB
000E_FFFFh
Extended System BIOS (Lower)
000E_0000h
64KB (16KBx4)
960KB
896KB
000D_FFFFh
Expansion Area
128KB (16KBx8)
000C_0000h
768KB
000 B_FFFFh
Legacy Video Area
(SMM Memory)
128KB
000A_0000h
640KB
0009_FFFFh
DOS Area
0000_0000h
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8.1.1
DOS Range (0h – 9_FFFFh)
The DOS area is 640 kB (0000_0000h – 0009_FFFFh) in size and is always mapped to the main
memory controlled by the GMCH.
8.1.2
Legacy Video Area (A_0000h-B_FFFFh)
The legacy 128 kB VGA memory range, frame buffer, (000A_0000h – 000B_FFFFh) can be mapped
to IGD (Device #2), to PCI Express (Device #1), and/or to the DMI. The appropriate mapping depends
on which devices are enabled and the programming of the VGA steering bits. Based on the VGA
steering bits, priority for VGA mapping is constant. The GMCH always decodes internally mapped
devices first. Internal to the GMCH, decode precedence is always given to IGD. The GMCH always
positively decodes internally mapped devices, namely the IGD and PCI Express. Subsequent decoding
of regions mapped to PCI Express or the DMI depends on the Legacy VGA configuration bits (VGA
Enable and MDAP). This region is also the default for SMM space.
Compatible SMRAM Address Range (A_0000h-B_FFFFh)
When compatible SMM space is enabled, SMM-mode CPU accesses to this range are routed to
physical system DRAM at 000A 0000h - 000B FFFFh. Non-SMM-mode CPU accesses to this range
are considered to be to the Video Buffer Area as described above. PCI Express and DMI originated
cycles to enabled SMM space are not allowed and are considered to be to the Video Buffer Area if IGD
is not enabled as the VGA device. PCI Express and DMI initiated cycles are attempted as Peer cycles,
and will master abort on PCI if no external VGA device claims them.
Monochrome Adapter (MDA) Range (B_0000h-B_7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome) in the system.
Accesses in the standard VGA range are forwarded to IGD, PCI Express, or the DMI (depending on
configuration bits). Since the monochrome adapter may be mapped to any one of these devices, the
GMCH must decode cycles in the MDA range (000B_0000h - 000B_7FFFh) and forward either to
IGD, PCI Express, or the DMI. This capability is controlled by a VGA steering bits and the legacy
configuration bit (MDAP bit). In addition to the memory range B0000h to B7FFFh, the GMCH
decodes IO cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards them to the either IGD,
PCI Express, and/or the DMI.
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8.1.3
Expansion Area (C_0000h-D_FFFFh)
This 128 kB ISA Expansion region (000C_0000h – 000D_FFFFh) is divided into eight 16 KB
segments. Each segment can be assigned one of four Read/Write states: read-only, write-only,
read/write, or disabled. Typically, these blocks are mapped through GMCH and are subtractively
decoded to ISA space. Memory that is disabled is not remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to DRAM.
Table 8-1. Expansion Area Memory Segments
8.1.4
Memory Segments
Attributes
Comments
0C0000H - 0C3FFFH
W/R
Add-on BIOS
0C4000H - 0C7FFFH
W/R
Add-on BIOS
0C8000H - 0CBFFFH
W/R
Add-on BIOS
0CC000H - 0CFFFFH
W/R
Add-on BIOS
0D0000H - 0D3FFFH
W/R
Add-on BIOS
0D4000H - 0D7FFFH
W/R
Add-on BIOS
0D8000H - 0DBFFFH
W/R
Add-on BIOS
0DC000H - 0DFFFFH
W/R
Add-on BIOS
Extended System BIOS Area (E_0000h-E_FFFFh)
This 64 kB area (000E_0000h – 000E_FFFFh) is divided into four, 16 kB segments. Each segment can
be assigned independent read and write attributes so it can be mapped either to main DRAM or to DMI.
Typically, this area is used for RAM or ROM. Memory segments that are disabled are not remapped
elsewhere.
Non-snooped accesses from PCI Express or DMI to this region are always sent to DRAM.
Table 8-2. Extended System BIOS Area Memory Segments
228
Memory Segments
Attributes
Comments
0E0000H - 0E3FFFH
W/R
BIOS Extension
0E4000H - 0E7FFFH
W/R
BIOS Extension
0E8000H - 0EBFFFH
W/R
BIOS Extension
0EC000H - 0EFFFFH
W/R
BIOS Extension
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8.1.5
System BIOS Area (F_0000h-F_FFFFh)
This area is a single 64 kB segment (000F_0000h – 000F_FFFFh). This segment can be assigned read
and write attributes. It is by default (after reset) Read/Write disabled and cycles are forwarded to DMI.
By manipulating the Read/Write attributes, the GMCH can “shadow” BIOS into the main DRAM.
When disabled, this segment is not remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to DRAM.
Table 8-3. System BIOS Area Memory Segments
8.1.6
Memory Segments
Attributes
Comments
0F0000H - 0FFFFFH
WE RE
BIOS Area
Programmable Attribute Map (PAM) Memory Area Details
The 13 sections from 768 kB to 1 MB comprise what is also known as the PAM Memory Area.
The GMCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all memory
residing on DMI should be set as non-cacheable, there normally will not be IWB cycles targeting DMI.
However, DMI becomes the default target for CPU and DMI originated accesses to disabled segments
of the PAM region. If the MTRRs covering the PAM regions are set to WB or RC it is possible to get
IWB cycles targeting DMI. This may occur for DMI originated cycles to disabled PAM regions.
For example, say that a particular PAM region is set for “Read Disabled” and the MTRR associated
with this region is set to WB. A DMI master generates a memory read targeting the PAM region. A
snoop is generated on the FSB and the result is an IWB. Since the PAM region is “Read Disabled” the
default target for the Memory Read becomes DMI. The IWB associated with this cycle will cause the
GMCH to hang.
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8.2
Main Memory Address Range (1 MB to TOLUD)
This address range extends from 1 MB to the top of physical memory that is permitted to be accessible
by the GMCH (as programmed in the TOLUD register). All accesses to addresses within this range
will be forwarded by the GMCH to the DRAM unless they fall into the optional TSEG, optional ISA
Hole, or optional IGD stolen VGA memory.
The GMCH provides a maximum DRAM address decode space of 4 GB. The GMCH does not remap
APIC or PCI Express memory space. This means that as the amount of physical memory populated in
the system reaches 4 GB, there will be physical memory that exists yet is non-addressable and therefore
unusable by the system.
The GMCH does not limit DRAM address space in hardware.
Figure 8-3. Main Memory Address Range
8.2.1
ISA Hole (15 MB-16 MB)
Legacy ISA based video accelerators originally used this hole. A hole can be created at 15 MB-16 MB
as controlled by the fixed hole enable in Device 0 space. Accesses within this hole are forwarded to
the DMI. The range of physical DRAM memory disabled by opening the hole is not remapped to the
top of the memory – that physical DRAM space is not accessible. This 15 MB-16 MB hole is an
optionally enabled ISA hole.
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8.2.2
TSEG
TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below IGD stolen memory, which is at the
top of physical memory. SMM-mode CPU accesses to enabled TSEG access the physical DRAM at the
same address. Non-CPU originated accesses are not allowed to SMM space. PCI Express, DMI, and
Internal Graphics originated cycles to enabled SMM space are handled as invalid cycle type with reads
and writes to location 0 and byte enables turned off for writes. When the extended SMRAM space is
enabled, CPU accesses to the TSEG range without SMM attribute or without WB attribute are also
forwarded to memory as invalid accesses. Non-SMM-mode Write Back cycles that target TSEG space
are completed to DRAM for cache coherency. When SMM is enabled the maximum amount of
memory available to the system is equal to the amount of physical DRAM minus the value in the TSEG
register which is fixed at 1 MB, 2 MB or 8 MB.
8.2.3
Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and reside within system
memory address range (< TOLUD) are created for SMM-mode and legacy VGA graphics
compatibility. It is the responsibility of BIOS to properly initialize these regions. The following
table details the location and attributes of the regions. How to enable and disable these ranges are
described in the GMCH Control Register Device #0 (GCC).
Table 8-4. Pre-allocated Memory Example for 64-MB Dram, 1-MB VGA, and 1-MB TSEG
Memory Segments
Attributes
0000_0000h – 03DF_FFFFh
R/W
03E0_0000h – 03EF_FFFFh
SMM Mode Only CPU Reads
03F0_0000h – 03FF_FFFFh
R/W
Comments
Available System Memory 62 MB
TSEG Address Range & Pre-allocated Memory
Pre-allocated Graphics VGA memory.
1MB (or 4/8/16/32/64 MB) when IGD is enabled.
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8.3
PCI Express Memory Address Range (TOLUD – 4GB)
This address range, from the top of physical memory to 4 GB (top of addressable memory space
supported by the GMCH) is normally mapped via the DMI to PCI.
Exceptions to this mapping include the BAR memory mapped regions, which include: EPBAR,
MCHBAR, DMIBAR.
In the PCI Express port, there are two exceptions to this rule:
1. Addresses decoded to the PCI Express Memory Window defined by the MBASE1, MLIMIT1,
PMBASE1, and PMLIMIT1 registers are mapped to PCI Express.
2. Addresses decoded to PCI Express Configuration Space are mapped based on Bus, Device, and
Function number. (PCIEXBAR range).
Note:
AGP Aperture no longer exists with PCI Express.
In an internal graphics configuration, there are three exceptions to this rule:
3. Addresses decoded to the Graphics Memory Range. (GMADR range)
4. Addresses decoded to the Graphics Translation Table range (GTTADR range).
5. Addresses decoded to the Memory Mapped Range of the Internal Graphics Device (MMADR
range). There is a MMADR range for device 2 function 0 and a MMADR range for device 2
function 1. Both ranges are forwarded to the internal graphics device.
Note: The exceptions listed above for internal graphics and the PCI Express ports MUST NOT
overlap with APCI Configuration Space, FSB Interrupt Space and High BIOS Address Range.
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Figure 8-4. PCI Express Memory Address Range
FFFF_FFFFh
4GB
High BIOS
FFE0_0000h
4GB - 2MB
DMI Interface
(subtractive decode)
4GB - 17MB
FEF0_0000h
FSB Interrupts
FEE0_0000h
FED0_0000h
DMI Interface
(subtractive decode)
Local (CPU) APIC
FEC8_0000h
I/O APIC
FEC0_0000h
4GB - 18MB
4GB - 19MB
Optional HSEG
FEDA_0000h to
FEDB_FFFFh
4GB - 20MB
DMI Interface
(subtractive decode)
F000_0000h
4GB - 256MB
PCI Express Configuration
Space
E000_0000h
Possible
address
range
4GB - 512MB
DMI Interface
(subtractive decode)
Internal Graphics ranges
PCI Express Port
TOLUD
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8.3.1
APIC Configuration Space (FEC0_0000h-FECF_FFFFh)
This range is reserved for APIC configuration space which includes the default I/O APIC configuration
space from FEC0_0000h to FEC7_0FFFh. The default Local (CPU) APIC configuration space goes
from FEC8_0000h to FECF_FFFFh.
CPU accesses to the Local APIC configuration space do not result in external bus activity since the
Local APIC configuration space is internal to the CPU. However, an MTRR must be programmed to
make the Local APIC range uncacheable (UC). The Local APIC base address in each CPU should be
relocated to the FEC0_0000h (4 GB-20 MB) to FECF_FFFFh range so that one MTRR can be
programmed to 64 kB for the Local and I/O APICs. The I/O APIC(s) usually reside in the ICH portion
of the chip set or as a stand-alone component(s).
I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/O APIC will
be located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h where x is I/O APIC unit
number 0 through F(hex). This address range will normally be mapped to DMI.
Note:
8.3.2
There is no provision to support an I/O APIC device on PCI Express.
HSEG (FEDA_0000h-FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window to SMM
memory. It is sometimes called the High SMM memory space. SMM-mode CPU accesses to the
optionally enabled HSEG are remapped to 000A_0000h - 000B_FFFFh. Non-SMM mode CPU
accesses to enabled HSEG are considered invalid and are terminated immediately on the FSB. The
exceptions to this rule are Non-SMM mode Write Back cycles which are remapped to SMM space to
maintain cache coherency. PCI Express and DMI originated cycles to enabled SMM space are not
allowed. Physical DRAM behind the HSEG transaction address is not remapped and is not accessible.
All Cacheline writes with WB attribute or implicit write backs to the HSEG range are completed to
DRAM like an SMM cycle.
8.3.3
FSB Interrupt Memory Space (FEE0_0000-FEEF_FFFF)
The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any device on PCI
Express or DMI may issue a Memory Write to 0FEEx_xxxxh. The GMCH will forward this Memory
Write along with the data to the FSB as an Interrupt Message Transaction. The GMCH terminates the
FSB transaction by providing the response and asserting HTRDY#. This Memory Write cycle does not
go to DRAM.
8.3.4
High BIOS Area
The top 2 MB (FFE0_0000h -FFFF_FFFFh) of the PCI Memory Address Range is reserved for System
BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the system BIOS. The CPU
begins execution from the High BIOS after reset. This region is mapped to DMI so that the upper
subset of this region aliases to the 16 MB-256 kB range. The actual address space required for the
BIOS is less than 2 MB but the minimum CPU MTRR range for this region is 2 MB so that full 2 MB
must be considered.
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8.4
PCI Express Configuration Address Space
There is a Device 0 register (PCIEXBAR), that defines the base address for the 256-MB block of
addresses below top of addressable memory (currently 4 GB) for the configuration space associated
with all devices and functions that are potentially a part of the PCI Express root complex hierarchy.
This range will be aligned to a 256-MB boundary. BIOS must assign this address range such that it
will not conflict with any other address ranges.
See the configuration portion of this document for more details.
8.4.1
PCI Express Graphics Attach
The GMCH can be programmed to direct memory accesses to the PCI Express interface when
addresses are within either of two ranges specified via registers in GMCH’s Device #1 configuration
space.
• The first range is controlled via the Memory Base Register (MBASE) and Memory Limit Register
(MLIMIT) registers.
• The second range is controlled via the Prefetchable Memory Base (PMBASE) and Prefetchable
Memory Limit (PMLIMIT) registers.
The GMCH positively decodes memory accesses to PCI Express memory address space as defined by
the following equations:
Memory_Base_Address ≤ Address ≤ Memory_Limit_Address
Prefetchable_Memory_Base_Address ≤ Address ≤ Prefetchable_Memory_Limit_Address
It is essential to support a separate Prefetchable range in order to apply USWC attribute (from the
processor point of view) to that range. The USWC attribute is used by the processor for write
combining.
Note that the GMCH Device #1 memory range registers described above are used to allocate memory
address space for any PCI Express devices sitting on PCI Express that require such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In other words,
the memory access enable bit must be set in the device 1 PCICMD1 register to enable the memory
base/limit and prefetchable base/limit windows.
8.4.2
AGP DRAM Graphics Aperture
Unlike AGP, PCI Express has no concept of aperture for PCI Express devices. As a result, there is no
need to translate addresses from PCI Express. Therefore, the GMCH has no APBASE and APSIZE
registers.
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8.5
Graphics Memory Address Ranges (Intel Integrated
Graphics Chipsets Only)
The GMCH can be programmed to direct memory accesses to IGD when addresses are within any of
three ranges specified via registers in GMCH’s Device #2 configuration space.
• The Memory Map Base Register (MMADR) is used to access graphics control registers.
• The Graphics Memory Aperture Base Register (GMADR) is used to access graphics memory
allocated via the graphics translation table.
• The Graphics Translation Table Base Register (GTTADR) is used to access the translation table.
Normally these ranges will reside above the Top-of-Main-DRAM and below High BIOS and APIC
address ranges. They normally reside above the top of memory (TOLUD) so they do not steal any
physical DRAM memory space.
GMADR is a Prefetchable range in order to apply USWC attribute (from the processor point of view)
to that range. The USWC attribute is used by the processor for write combining.
8.6
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SMM RAM). The
GMCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of Memory
Segment (TSEG). System Management RAM space provides a memory area that is available for the
SMI handlers and code and data storage. This memory resource is normally hidden from the system
OS so that the processor has immediate access to this memory space upon entry to SMM. GMCH
provides three SMRAM options:
• Below 1-MB option that supports compatible SMI handlers.
• Above 1-MB option that allows new SMI handlers to execute with write-back cacheable SMRAM.
• Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. The TSEG area lies below IGD stolen
memory.
The above 1-MB solutions require changes to compatible SMRAM handlers code to properly execute
above 1 MB.
Note:
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8.6.1
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The addressed SMM
space is defined as the range of bus addresses used by the CPU to access SMM space. DRAM SMM
space is defined as the range of physical DRAM memory locations containing the SMM code. SMM
space can be accessed at one of three transaction address ranges: Compatible, High and TSEG.
The Compatible and TSEG SMM space is not remapped and therefore the addressed and DRAM SMM
space is the same address range. Since the High SMM space is remapped the addressed and DRAM
SMM space are different address ranges. Note that the High DRAM space is the same as the
Compatible Transaction Address space. The table below describes three unique address ranges:
• Compatible Transaction Address (Adr C)
• High Transaction Address (Adr H)
• TSEG Transaction Address (Adr T)
These abbreviations are used later in the table describing SMM Space Transaction Handling.
Table 8-5. SMM Space Definition Summary
SMM Space Enabled
8.7
Transaction Address Space
DRAM Space (DRAM)
Compatible (C)
000A_0000h to 000B_FFFFh
000A_0000h to 000B_FFFFh
High (H)
FEDA_0000h to FEDB_FFFFh
000A_0000h to 000B_FFFFh
TSEG (T)
(TOLUD-STOLEN-TSEG) to TOLUDSTOLEN
(TOLUD-STOLEN-TSEG) to TOLUDSTOLEN
SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are unpredictable and may
cause the system to hang:
• The Compatible SMM space must not be set-up as cacheable.
• High or TSEG SMM transaction address space must not overlap address space assigned to system
DRAM, or to any “PCI” devices (including DMI, PCI Express, and graphics devices). This is a
BIOS responsibility.
• Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
• When TSEG SMM space is enabled, the TSEG space must not be reported to the OS as available
DRAM. This is a BIOS responsibility.
• Any address translated through the GMADR must not target DRAM from A_0000-F_FFFF.
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8.7.1
SMM Space Combinations
When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1) the Compatible SMM space is
effectively disabled. CPU originated accesses to the Compatible SMM space are forwarded to PCI
Express if VGAEN=1 (also depends on MDAP), otherwise they are forwarded to the DMI. PCI
Express and DMI originated accesses are never allowed to access SMM space.
Table 8-6. SMM Space Table
8.7.2
Global Enable
G_SMRAME
High Enable
H_SMRAM_EN
TSEG Enable
TSEG_EN
Compatible
(C) Range
High (H)
Range
TSEG (T)
Range
0
X
X
Disable
Disable
Disable
1
0
0
Enable
Disable
Disable
1
0
1
Enable
Disable
Enable
1
1
0
Disabled
Enable
Disable
1
1
1
Disabled
Enable
Enable
SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit allows software
to write to the SMM ranges without being in SMM mode. BIOS software can use this bit to initialize
SMM code at powerup. The D_LCK bit limits the SMM range access to only SMM mode accesses.
The D_CLS bit causes SMM data accesses to be forwarded to the DMI or PCI Express. The SMM
software can use this bit to write to video memory while running SMM code out of DRAM.
Table 8-7. SMM Control Table
G_SMRAME
8.7.3
D_LCK
D_CLS
0
x
X
1
0
X
D_OPEN
CPU in
SMM Mode
SMM Code
Access
SMM Data
Access
x
x
Disable
Disable
0
0
Disable
Disable
Enable
1
0
0
0
1
Enable
1
0
0
1
x
Enable
Enable
1
0
1
0
1
Enable
Disable
1
0
1
1
x
Invalid
Invalid
1
1
X
x
0
Disable
Disable
1
1
0
x
1
Enable
Enable
1
1
1
x
1
Enable
Disable
SMM Space Decode and Transaction Handling
Only the CPU is allowed to access SMM space. PCI Express and DMI originated transactions are not
allowed to SMM space.
8.7.4
CPU WB Transaction to an Enabled SMM Address Space
CPU Writeback transactions (REQ[1]# = 0) to enabled SMM address space must be written to the
associated SMM DRAM even though D_OPEN=0 and the transaction is not performed in SMM mode.
This ensures SMM space cache coherency when cacheable extended SMM space is used.
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8.8
Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be “shadowed” into
GMCH DRAM memory. Typically this is done to allow ROM code to execute more rapidly out of
main DRAM. ROM is used as read-only during the copy process while DRAM at the same time is
designated write-only. After copying, the DRAM is designated read-only so that ROM is shadowed.
CPU bus transactions are routed accordingly.
8.9
I/O Address Space
The GMCH does not support the existence of any other I/O devices beside itself on the CPU bus. The
GMCH generates either DMI or PCI Express bus cycles for all CPU I/O accesses that it does not claim.
Within the host bridge the GMCH contains two internal registers in the CPU I/O space, Configuration
Address Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA).
These locations are used to implement a configuration space access mechanism.
The CPU allows 64 k+3 bytes to be addressed within the I/O space. The GMCH propagates the CPU
I/O address without any translation on to the destination bus and therefore provides addressability for
64 k+3 byte locations. Note that the upper three locations can be accessed only during I/O address
wrap-around when CPU bus HAB_16 address signal is asserted. HAB_16 is asserted on the CPU bus
whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. HAB_16 is also
asserted when an I/O access is made to 2 bytes from address 0FFFFh.
A set of I/O accesses (other than ones used for configuration space access) are consumed by the
internal graphics device if it is enabled. The mechanisms for internal graphics I/O decode and the
associated control is explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded normally to the
DMI bus unless they fall within the PCI Express I/O address range as defined by the mechanisms
explained below. I/O writes are NOT posted. Memory writes to ICH or PCI Express are posted. The
PCICMD1 register can disable the routing of I/O cycles to PCI Express.
The GMCH responds to I/O cycles initiated on PCI Express or DMI with a UR status. Upstream I/O
cycles and configuration cycles should never occur. If one does occur, the request will route as a read
to memory address 0h so a completion is naturally generated (whether the original request was a read
or write). The transaction will complete with a UR completion status.
For Intel Pentium M Processor with 2 MBL2 Cache processor, I/O reads that lie within 8-byte
boundaries but cross 4-byte boundaries are issued from the CPU as 1 transaction. The GMCH will
break this into two separate transactions. This has not been done on previous chipsets. I/O writes that
lie within 8-byte boundaries but cross 4-byte boundaries are assumed to be split into two transactions
by the CPU.
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8.9.1
PCI Express I/O Address Mapping
The GMCH can be programmed to direct non-memory (I/O) accesses to the PCI Express bus interface
when CPU initiated I/O cycle addresses are within the PCI Express I/O address range. This range is
controlled via the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT) registers in GMCH
Device #1 configuration space.
8.10
GMCH Decode Rules and Cross-Bridge Address
Mapping
VGAA = 000A_0000 – 000A_FFFF
MDA = 000B_0000 – 000B_7FFF
VGAB = 000B_8000 – 000B_FFFF
MAINMEM = 0100_0000 to TOLUD
8.10.1
Legacy VGA and I/O Range Decode Rules
The legacy 128 kB VGA memory range 000A_0000h-000B_FFFFh can be mapped to IGD (Device
#2), to PCI Express (Device #1), and/or to the DMI depending on the programming of the VGA
steering bits. Priority for VGA mapping is constant in that the GMCH always decodes internally
mapped devices first. Internal to the GMCH, decode precedence is always given to IGD. The GMCH
always positively decodes internally mapped devices, namely the IGD and PCI Express. Subsequent
decoding of regions mapped to PCI Express or the DMI depends on the Legacy VGA configurations
bits (VGA Enable and MDAP).
§
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9
Host Interface
9.1
FSB Source Synchronous Transfers
The GMCH supports the Intel Pentium M Processor with 2 MBL2 Cache processor subset of the
Enhanced Mode Scaleable Bus. The cache line size is 64 bytes. Source synchronous transfer is used for
the address and data signals. The address signals are double pumped and a new address can be
generated every other bus clock. At 100 MHz and 133 MHz bus clock the address signals run at 200,
266 and 400 MT/s for a maximum address queue rate of 66 M and 100 M addresses/sec. The data is
quad pumped and an entire 64B cache line can be transferred in two bus clocks. At 100 MHz and 133
MHz bus clock the data signals run at 400 and 533 for a maximum bandwidth of 3.2, 4.3, and 6.4 GB/s
respectively.
9.2
FSB IOQ Depth
The Scalable Bus supports up to 12 simultaneous outstanding transactions.
9.3
FSB OOQ Depth
The GMCH supports only one outstanding deferred transaction on the FSB.
9.4
FSB GTL+ Termination
The GMCH integrates GTL+ termination resistors on die.
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9.5
FSB Dynamic Bus Inversion
The GMCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data from the
CPU. DBI limits the number of data signals that are driven to a low voltage on each quad pumped data
phase. This decreases the worst-case power consumption of the GMCH. HDINV#_3:0 indicate if the
corresponding 16 bits of data are inverted on the bus for each quad pumped data phase:
HDINVB_3:0
Data Bits
HDINV0#
HD15:0#
HDINV1#
HD31:16#
HDINV2#
HD47:32#
HDINV3#
HD63:48#
Whenever the processor or the GMCH drives data, each 16-bit segment is analyzed. If more than 8 of
the 16 signals would normally be driven low on the bus the corresponding HDINV# signal will be
asserted and the data will be inverted prior to being driven on the bus. Whenever the CPU or the
GMCH receives data it monitors HDINV# [3:0] to determine if the corresponding data segment should
be inverted.
9.6
FSB Interrupt Overview
The Intel Pentium M Processor with 2 MBL2 Cache processor supports FSB interrupt delivery. They
do not support the APIC serial bus interrupt delivery mechanism. Interrupt related messages are
encoded on the FSB as “Interrupt Message Transactions”. FSB interrupts may originate from the CPUs
on the FSB, or from a downstream device on the DMI or PCI Express Graphics Attach. In the later
case, the GMCH drives the “Interrupt Message Transaction” on the FSB.
In the IOxAPIC environment, an interrupt is generated from the IOxAPIC to a CPU in the form of an
upstream Memory Write. The ICH contains IOxAPICs, and its interrupts are generated as upstream
DMI Memory Writes. Furthermore, the PCI 2.3 specification and PCI Express Specifications define
MSI’s (Message Signaled Interrupts) that are also in the form of Memory Writes. A PCI device may
generate an interrupt as an MSI cycle on it’s PCI bus instead of asserting a hardware signal to the
IOxAPIC. The MSI may be directed to the IOxAPIC. The IOxAPIC in turn generates an interrupt as
an upstream DMI Memory Write. Alternatively, the MSI may directly route to the FSB. The target of
an MSI is dependent on the address of the interrupt Memory Write. The GMCH forwards upstream
DMI and PCI Express Graphics Attach low priority Memory Writes to address 0FEEx_xxxxh to the
FSB as “Interrupt Message Transactions”.
The GMCH also broadcasts EOI cycles generated by a CPU downstream to the PCI Express Port and
DMI interfaces.
9.7
APIC Cluster Mode support
This is required for backwards compatibility with existing software, including various OS’s. As one
example, beginning with Microsoft* Windows* 2000 there is a mode (boot.ini) that allows an end user
to enable the use of cluster addressing support of the APIC.
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10
Functional Description
This chapter describes the GMCH interfaces and major functional units
10.1
Host Interface
The GMCH supports the Intel Pentium M Processor with 2 MBL2 Cache processor subset of the
Enhanced Mode Scaleable Bus. The cache line size is 64 bytes. Source synchronous transfer is used for
the address and data signals. The address signals are double pumped and a new address can be
generated every other bus clock. At 100 MHz and 133 MHz bus clock the address signals run at 200,
266 and 400 MT/s for a maximum address queue rate of 66 M and 100 M addresses/sec. The data is
quad pumped and an entire 64B cache line can be transferred in two bus clocks. At 100 MHz and 133
MHz bus clock the data signals run at 400 and 533 for a maximum bandwidth of 3.2, 4.3, and 6.4 GB/s
respectively.
The Scalable Bus supports up to 12 simultaneous outstanding transactions. The GMCH supports only
one outstanding deferred transaction on the FSB.
10.1.1
FSB GTL+ Termination
The GMCH integrates GTL+ termination resistors on die.
10.1.2
FSB Dynamic Bus Inversion
The GMCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data from the
CPU. DBI limits the number of data signals that are driven to a low voltage on each quad pumped data
phase. This decreases the worst-case power consumption of the GMCH. HDINV#_3:0 indicate if the
corresponding 16 bits of data are inverted on the bus for each quad pumped data phase:
HDINVB_3:0
Data Bits
HDINV0#
HD15:0#
HDINV1#
HD31:16#
HDINV2#
HD47:32#
HDINV3#
HD63:48#
Whenever the processor or the GMCH drives data, each 16-bit segment is analyzed. If more than 8 of
the 16 signals would normally be driven low on the bus the corresponding HDINV# signal will be
asserted and the data will be inverted prior to being driven on the bus. Whenever the CPU or the
GMCH receives data it monitors HDINV# [3:0] to determine if the corresponding data segment should
be inverted.
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10.1.3
APIC Cluster Mode support
This is required for backwards compatibility with existing software, including various OS’s. As one
example, beginning with Microsoft* Windows* 2000 there is a mode (boot.ini) that allows an end user
to enable the use of cluster addressing support of the APIC.
The (G)MCH supports three types of interrupt re-direction:
• Physical
• Flat-Logical
• Clustered-Logical
10.2
System Memory Controller
This section describes the GMCH system memory interface for both DDR memory and DDR2
memory. The GMCH supports both DDR and DDR2 memory and either one or two DIMMs per
channel.
The Intel 915GM/GME/PM and Intel 910GML/GMLE GMCH DRAM sub-system supports DDR and
DDR2 devices.
The Intel 915GMS GMCH DRAM sub-system support only DDR2 devices.
The Mobile Intel® 915GM/GME/PM Express Chipset supports three memory channel organizations:
• Single Channel configuration for DDR 333 MHz devices
• Dual Channel Asymmetric for DDR2 400/533 MHz devices
• Dual Channel Symmetric for DDR2 400/533 MHz devices
The Mobile Intel 910GML/GMLE Express chipset supports three memory channel organizations:
• Single Channel configuration for DDR 333 MHz devices
• Dual Channel Asymmetric for DDR2 400 MHz devices
• Dual Channel Symmetric for DDR2 400 MHz devices
The Intel 915GMS chipset only supports one memory channel organization:
• Single Channel configuration for DDR2 400 MHz devices
If configured as a single channel system, that channel can have one, two, three, or four ranks populated.
If configured as a dual channel system, each channel can have one or two ranks populated. So in either
case there can be a maximum of 4 ranks (2 double sided SO-DIMMs) populated.
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Table 10-1. System Memory Organization Support for DDR
DDR
Width
Page
Size
Banks
Smallest
Increments
Largest
Increments
256 Mb
X8
8k
4
256 MB
512 MB
1 GB
256 Mb
X16
4k
4
128 MB
256 MB
512 MB
512 Mb
X8
8k
4
512 MB
1 GB
2 GB
512 Mb
X16
8k
4
256 MB
512 MB
1 GB
1 GB
X16
8k
4
512 MB
1 GB
2 GB
Tech
Maximum Capacity
(2 DS SO-DIMMs)
Table 10-2. System Memory Organization Support for DDR2
DDR2
Width
Page
Size
Banks
Smallest
Increments
Largest
Increments
256 Mb
X8
8k
4
256 MB
512 MB
1 GB
256 Mb
X16
4k
4
128 MB
256 MB
512 MB
Tech
Maximum Capacity
(2 DS SO-DIMMs)
512 Mb
X8
8k
4
512 MB
1 GB
2 GB
512 Mb
X16
8k
4
256 MB
512 MB
1 GB
1 GB
X16
8k
8
512 MB
1 GB
2 GB
Table 10-3. DDR / DDR2 Supported Configurations
246
Technology
Configuration
# of Row
Address Bits
# of Column
Address Bits
# of Bank
Address Bits
Page
Size
Rank Size
256 Mbit
16M X 16
13
9
2
4k
128 MB
256 Mbit
32M X 8
13
10
2
8k
256 MB
512 Mbit
32M X 16
13
10
2
8v
256 MB
512 Mbit
64M X 8
13
11
2
16 k
512 MB
512 Mbit
64M X 8
14
10
2
8k
512 MB
512 MB
1 Gbit
64M X 16
14
10
2
8k
1 Gbit
128M X 8
14
11
2
16 k
1 GB
1 Gbit
64M X 16
13
10
3
8k
512 MB
1 Gbit
128M X 8
14
10
3
8k
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10.2.1
Memory Channel Organization Modes
The system memory controller supports three styles of memory organization (Symmetric, Asymmetric
and Single Channel) and two modes of operation (DDR and DDR2). Rules for populating SO-DIMM
slots are included in this chapter.
10.2.1.1
Interleaved (Symmetric) Mode
This mode provides maximum performance on real applications. Addresses are ping-ponged between
the channels, and the switch happens after each cache line (64-byte boundary) if a second request sits
behind the first, and that request is to an address on the second channel, that request can be sent before
data from the first request has returned. Due to this feature, some progress is made even furthering page
conflict scenarios. If two consecutive cache lines are requested, both may be retrieved simultaneously,
since they are guaranteed to be on opposite channels. The drawbacks of Symmetric mode are that the
system designer must populate both channels of memory so they have equal capacity, but the
technology and device width may vary from one channel to the other.
Table 10-4. Sample System Memory Organization with Symmetric Channels
10.2.1.2
Channel A
population
DRBs in
Channel A
Channel B
population
DRBs in
Channel B
Rank 1
512 MB
1024 MB
512 MB
1024 MB
Rank 0
512 MB
512 MB
512 MB
512 MB
Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode, addresses start
in channel A and stay there until the end of the highest rank in channel A, and then addresses continue
from the bottom of channel B to the top. Real world applications are unlikely to make requests that
alternate between addresses that sit on opposite channels with this memory organization, so in most
cases, bandwidth will be limited to that of a single channel. The system designer is free to populate or
not to populate any rank on either channel, including either degenerate single channel case.
Table 10-5. Sample System Memory Organization with Asymmetric Channels
Channel A
population
DRBs in
Channel A
Channel B
population
Rank 1
1024 MB
1536 MB
512 MB
768 MB
Rank 0
512 MB
512 MB
256 MB
256 MB
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Figure 10-1. System Memory Styles
sin g le ch an n e l
CL
TOM
du al ch an n el in terleav ed
ch an n els d on ’t h ave to m atch
du al ch an n el asym m etric
ch an n els d on ’t h ave to m atch
CL
CL
CH1
CH0
TOM
TOM
CH1
C H 0 -top
DRB
C H 0 or C H 1
CH0
CH1
CH0
CH1
0
CH0
0
0
C h ann el se lec tor con tro lle d b y
D C C [10 :9 ]
10.2.1.3
DRAM Address Mapping
In the tables below, r indicates a Row address bit, b indicates a bank select bit, and c indicates a column
address bit. h indicates a channel select bit, and s indicates that the bit is part of the decode for a chip
select (rank select) bit, but since different ranks may use different technologies or organizations, the
only way to be sure to which channel and rank an address belongs is to check the DRB register
programming. Both s and h are provided for the example of a homogenous population only. Column bit
10 is always used for an AutoPrecharge indication. An asterisk (*) indicates that row address bit 4 will
always be driven to 0.
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Table 10-6. DRAM Device Configurations –Dual Channel Asymmetric Mode / Single Channel Mode
Technology (Mb)
256X16
256
512
512
512
512
1024
1024
1024
1024
Row bits
13
13
13
13
13
14
14
14
13
14
column bits
9
10
10
11
10
10
10
11
10
10
bank bits
2
2
2
2
2
2
2
2
3
3
width (b)
16
8
16
8
16
8
16
8
16
8
Rows
8192
8192
8192
8192
8192
16384
16384
16384
8192
16384
Columns
512
1024
1024
2048
1024
1024
1024
2048
1024
1024
Banks
4
4
4
4
4
4
4
4
8
8
Page Size (KB)
4
8
8
16
8
8
8
16
8
8
devices per rank
4
8
4
8
4
8
4
8
4
8
Rank Size (MB)
128
256
256
512
256
512
512
1024
512
1024
Depth (M)
16
32
32
64
32
64
64
128
64
128
Addr bits [n:0]
26
27
27
28
27
28
28
29
28
29
available in DDR
yes
yes
yes
yes
no
no
yes
yes
no
no
available in DDR2
yes
yes
no
no
yes
yes
no
no
yes
yes
Host Address bit
Memory
Address bit
31
-
-
-
-
-
-
-
-
-
-
30
-
-
-
-
-
-
-
-
-
-
29
-
-
-
-
-
-
-
r 13
-
r 13
28
-
-
-
r 11
-
r 13
r 13
r 11
r 11
r 11
27
-
r 12
r 12
r 12
r 12
r 12
r 12
r 12
r 12
r 12
26
r 10
r 10
r 10
r 10
r 10
r 10
r 10
r 10
r 10
r 10
25
r9
r9
r9
r9
r9
r9
r9
r9
r9
r9
24
r8
r8
r8
r8
r8
r8
r8
r8
r8
r8
23
r7
r7
r7
r7
r7
r7
r7
r7
r7
r7
22
r6
r6
r6
r6
r6
r6
r6
r6
r6
r6
21
r5
r5
r5
r5
r5
r5
r5
r5
r5
r5
20
r4
r4
r4
r4
r4
r4
r4
r4
r4
r4
19
r3
r3
r3
r3
r3
r3
r3
r3
r3
r3
18
r2
r2
r2
r2
r2
r2
r2
r2
r2
r2
17
r1
r1
r1
r1
r1
r1
r1
r1
r1
r1
16
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
15
r 11
r 11
r 11
b0
r 11
r 11
r 11
b0
b0
b0
14
r 12
b1
b1
b1
b1
b1
b1
b1
b1
b1
13
b0
b0
b0
c 11
b0
b0
b0
c 11
b2
b2
12
b1
c9
c9
c9
c9
c9
c9
c9
c9
c9
11
c8
c8
c8
c8
c8
c8
c8
c8
c8
c8
10
c7
c7
c7
c7
c7
c7
c7
c7
c7
c7
9
c6
c6
c6
c6
c6
c6
c6
c6
c6
c6
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R
Host Address bit
Memory
Address bit
8
c5
c5
c5
c5
c5
c5
c5
c5
c5
c5
7
c4
c4
c4
c4
c4
c4
c4
c4
c4
c4
6
c3
c3
c3
c3
c3
c3
c3
c3
c3
c3
5
c2
c2
c2
c2
c2
c2
c2
c2
c2
c2
4
c1
c1
c1
c1
c1
c1
c1
c1
c1
c1
3
c0
c0
c0
c0
c0
c0
c0
c0
c0
c0
NOTES:
1. b – ‘bank’ select bit
2. c – ‘column’ address bit
3. r – ‘row’ address bit
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Table 10-7. DRAM Device Configurations – Dual Channel Symmetric Mode
Technology (Mb)
256
256
512
512
512
512
1024
1024
1024
1024
Row bits
13
13
13
13
13
14
14
14
13
14
column bits
9
10
10
11
10
10
10
11
10
10
bank bits
2
2
2
2
2
2
2
2
3
3
width (b)
16
8
16
8
16
8
16
8
16
8
Rows
8192
8192
8192
8192
8192
16384
16384
16384
8192
16384
Columns
512
1024
1024
2048
1024
1024
1024
2048
1024
1024
Banks
4
4
4
4
4
4
4
4
8
8
Page Size (KB)
4
8
8
16
8
8
8
16
8
8
devices per rank
4
8
4
8
4
8
4
8
4
8
Rank Size (MB)
128
256
256
512
256
512
512
1024
512
1024
Depth (M)
16
32
32
64
32
64
64
128
64
128
Addr bits [n:0]
26
27
27
28
27
28
28
29
28
29
available in DDR
yes
yes
yes
yes
no
no
yes
yes
no
no
available in DDR2
yes
yes
no
no
yes
yes
no
no
yes
yes
Host Address bit
31
Mem
Addr-bit
-
-
-
-
-
-
-
-
-
-
30
-
-
-
-
-
-
-
r 13
-
r 13
29
-
-
-
r 11
-
r 13
r 13
r 11
r 11
r 11
28
-
r 12
r 12
r 12
r 12
r 12
r 12
r 12
r 12
r 12
27
r 10
r 10
r 10
r 10
r 10
r 10
r 10
r 10
r 10
r 10
26
r9
r9
r9
r9
r9
r9
r9
r9
r9
r9
25
r8
r8
r8
r8
r8
r8
r8
r8
r8
r8
24
r7
r7
r7
r7
r7
r7
r7
r7
r7
r7
23
r6
r6
r6
r6
r6
r6
r6
r6
r6
r6
22
r5
r5
r5
r5
r5
r5
r5
r5
r5
r5
21
r4
r4
r4
r4
r4
r4
r4
r4
r4
r4
20
r3
r3
r3
r3
r3
r3
r3
r3
r3
r3
19
r2
r2
r2
r2
r2
r2
r2
r2
r2
r2
18
r1
r1
r1
r1
r1
r1
r1
r1
r1
r1
17
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
16
r 11
r 11
r 11
b0
r 11
r 11
r 11
b0
b0
b0
15
r 12
b1
b1
b1
b1
b1
b1
b1
b1
b1
14
b0
b0
b0
c 11
b0
b0
b0
c 11
b2
b2
13
b1
c9
c9
c9
c9
c9
c9
c9
c9
c9
12
c8
c8
c8
c8
c8
c8
c8
c8
c8
c8
11
c7
c7
c7
c7
c7
c7
c7
c7
c7
c7
10
c6
c6
c6
c6
c6
c6
c6
c6
c6
c6
9
c5
c5
c5
c5
c5
c5
c5
c5
c5
c5
8
c4
c4
c4
c4
c4
c4
c4
c4
c4
c4
7
c3
c3
c3
c3
c3
c3
c3
c3
c3
c3
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6
h
h
h
h
h
h
h
h
h
h
5
c2
c2
c2
c2
c2
c2
c2
c2
c2
c2
4
c1
c1
c1
c1
c1
c1
c1
c1
c1
c1
3
c0
c0
c0
c0
c0
c0
c0
c0
c0
c0
NOTES:
1. b – ‘bank’ select bit
2. c – ‘column’ address bit
3. h – channel select bit
4. r – ‘row’ address bit
10.2.2
DRAM Technologies and Organization
All standard 256 Mb, 512 Mb, and 1 Gb technologies and addressing are supported for x16 and x8
devices.
The GMCH supports various page sizes. Page size is individually selected for every rank; 4 kB, 8 kB,
and 16 kB for asymmetric, Symmetric, or single channel modes.
The DRAM sub-system supports single or dual channels, 64-bit wide per channel.
A maximum of four ranks (2 double sided SO-DIMMs) populated:
• If configured as a single channel system, that channel can have one, two, three or four ranks
populated.
• If configured as a dual channel system, each channel can have one or two ranks populated.
Mixed mode Double-Sided SO-DIMMs (x8 and x16 on the same SO-DIMM) are not supported.
By using 1-Gb technology, the largest memory capacity is 2 GB.
By using 256-Mb technology, the smallest memory capacity is 128 MB (16M x 16b x 4 devices x 1
ranks = 128 MB).
10.2.2.1
Supported SO-DIMM types
DDR
GMCH = supports DDR 200 pin up-buffered SO-DIMM’s specified in the JEDEC DDR SO-DIMM
specification
• Non ECC, Single Sided, x16 width
• Non ECC, Single Sided, x8 width
• Non ECC, Double Sided, x16 width
• Non ECC, Double Sided, x8 width (stacked)
DDR2
GMCH supports DDR2-SDRAM 200 pin up-buffered SO-DIMM’s specified in the JEDEC DDR2 SODIMM specification
• Non ECC, Single Sided, x16 width
• Non ECC, Single Sided, x8 width
• Non ECC, Double Sided, x16 width
• Non ECC, Double Sided, x8 width (stacked)
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10.2.2.2
Rules for Populating SO-DIMM Slots
In all modes, the frequency of System Memory will be the lowest frequency of all SO-DIMMs in the
system, as determined through the SPD registers on the SO-DIMMs.
• In the Single Channel modes, any SO-DIMM slot within the channel may be populated in any
order. Either channel may be used. To save power, any unused channel should be powered down.
• In Dual Channel Asymmetric mode, any SO-DIMM slot may be populated in any order.
• In Dual Channel Symmetric mode, any SO-DIMM slot may be populated in any order, but the total
memory in each channel must be the same.
10.2.2.3
Pin Connectivity for Single and Dual Channel Modes
Table 10-8. Single Channel Mode Signal Mapping for DDR/DDR2
Single Channel Signal Mapping
SO-DIMM 0
SO-DIMM 1
SM_CK [1:0]
SM_CK [4:3]
SM_CK# [1:0]
SM_CK# [4:3]
SM_CS# [1:0]
SM_CS# [3:2]
SM_CKE [1:0]
SM_CKE [3:2]
SM_ODT[1:0]
SM_ODT [3:2]
(DDR2 support only)
(DDR2 support only)
SA_BS [2:0]
SB_BS[2:0]
SA_MA[13:0]
SB_MA [13:0]
SA_RAS#
SB_RAS#
SA_CAS#
SB_CAS#
SA_WE#
SB_WE#
SA_DQ [63:0]
SA_DQS [7:0]
SA_DQS#[7:0]
SA_DM[7:0]
Table 10-9. Dual Channel Mode Signal Mapping for DDR/DDR2
Dual Channel Mode
Channel A
Channel B
SODIMM A
SODIMM B
SM_CK[1:0]
SM_CK[1:0]
NA
SM_CK[1:0]#
SM_CK[1:0]#
NA
SM_CK[4:3]
NA
SM_CK[4:3]
SM_CK[4:3]#
NA
SM_CK[4:3]#
SM_CS[1:0]#
SM_CS[1:0]#
NA
SM_CKE[1:0]
SM_CKE[1:0]
NA
SM_ODT[1:0]
SM_ODT[1:0]
NA
(DDR2 support)
(DDR2 support)
SM_CS[3:2]#
NA
SM_CS[3:2]#
SM_CKE[3:2]
NA
SM_CKE[3:2]
SM_ODT[3:2]
NA
(DDR2 support)
SM_ODT[3:2]
(DDR2 support)
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10.2.3
System Memory Configuration Registers Overview
The configuration registers located in the PCI configuration space of the GMCH control the System
Memory operation. Following is a brief description of configuration registers used by GMCH for
proper operation of the memory subsystem.
DRAM Rank Boundary (CxDRBy)
The x represents a channel, A or B. The y represents a rank, 0 through 1. DRB registers define the
upper addresses for a rank of DRAM devices in a channel. When the GMCH is configured in
asymmetric mode, each register represents a single rank. When the GMCH is configured in a dual
Symmetric mode, each register represents a pair of corresponding ranks in opposing channels. There
are four DRB registers for each channel.
DRAM Rank Architecture (CxDRAy)
The x represents a channel, A or B. The y represents a rank, 0 through 1. DRA registers specify the
architecture features of each rank of devices in a channel. The only architecture feature specified is
page size. When GMCH is configured in asymmetric mode, each DRA represents a single rank in a
single channel. When GMCH is configured in a dual-channel lock-step or Symmetric mode, each DRA
represents a pair of corresponding ranks in opposing channels. There are four DRA registers per
channel. Each requires only 3 bits, so there are two DRAs packed into a byte.
Clock Configuration (CLKCFG)
Specifies DRAM frequency. The same clock frequency will be driven to all SO-DIMMs.
DRAM Timing (CxDRTy)
The x represents a channel, A or B. This register grew too large for a single 32-bit access, so a second
register was added, differentiated by y, A or B. The DRT registers define the timing parameters for all
devices in a channel. The BIOS programs this register with “least common denominator” values after
reading the SPD registers of each SO-DIMM in the channel.
DRAM Control (CxDRCy)
The x represents a channel, A or B. This register grew too large for a single 32 bit access, so a second
register was added, differentiated by y, 0 or 1. DRAM refresh mode, rate, and other controls are
selected here.
10.2.4
DRAM Clock Generation
The GMCH PLL generates two differential 166 MHz, 200 MHz or 266 MHz clock pairs for every
supported SODIMM. There are total of 4 clock pairs driven directly by GMCH to the 2 SO-DIMMs.
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10.2.5
DDR2 On-Die Termination
On die termination (ODT) is a feature that allows a DRAM to turn on/off internal termination
resistance for each DQ, DM, DQS, and DQS# signal for x8 and x16 configurations via the ODT
control signals.
The ODT feature is designed to improve signal integrity of the memory channel by allowing the
termination resistance for the DQ, DM, DQS, and DQS# signals to be located inside the DRAM
devices themselves instead of on the motherboard. The GMCH drives out the required ODT signals,
based on memory configuration and which rank is being written to or read from, to the DRAM devices
on a targeted SO-DIMM rank to enable or disable their termination resistance.
10.2.6
DDR2 Off Chip Driver Impedance Calibration
The OCD impedance adjustment mode allows the GMCH to measure and adjust the pull-up and pulldown strength of the DRAM devices. It uses a series of EMRS commands to guide the DRAM through
measurement and calibration cycles. This feature is described in more detail in the JEDEC DDR2
device specification.
The algorithm and sequence of the adjustment cycles is handled by software. The GMCH adjusts the
DRAM driver impedance by issuing OCD commands to the SO-DIMM and looking at the analog
voltage on the DQ lines.
10.2.7
DRAM Power Management
GMCH implements extensive support for power management on the SDRAM interface. GMCH will
drive the CKE pins to perform these SDRAM power management operations. During Suspend to RAM
(S3) states, the SDRAM are put into self-refresh state to conserve power by asserting the CKE pin. In
addition, a “dynamic row power down” function is implemented, by which the SDRAM devices can be
put in a power down state when they are idle.
10.2.7.1
Dynamic Row Power Down Operation
GMCH implements CKE control to dynamically put the DRAM devices in a power down state. If
dynamic power down is enabled, all ranks are powered up before doing a refresh cycle and all ranks are
powered down at the end of refresh.
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10.3
PCI Express Interface (Intel® 915GM/915GME/915PM
Only)
See system overview chapter in this document for list of PCI Express features. See the PCI Express
Specification for further details.
This GMCH is part of a PCI Express root complex. This means it connects a host CPU/memory
subsystem to a PCI Express Hierarchy. The control registers for this functionality are located in device
#1 configuration space and two Root Complex Register Blocks (RCRBs).
The PCI Express architecture is specified in layers. Compatibility with the PCI addressing model (a
load-store architecture with a flat address space) is maintained to ensure that all existing applications
and drivers operate unchanged. The PCI Express configuration uses standard mechanisms as defined
in the PCI Plug-and-Play specification. The initial speed of 2.5 GHz (250 MHz internally) results in
2.5 Gb/s/direction which provides a 250 MB/s communications channel in each direction (500 MB/s
total) that is close to twice the data rate of classic PCI per lane.
10.3.1
Layering Overview
The representation of layers in the PCI Express architecture: the Transaction Layer, the Data Link
Layer, and the Physical Layer is to simplify the understanding of the high-level functionality.
PCI Express uses packets to communicate information between components. Packets are formed in the
Transaction and Data Link Layers to carry the information from the transmitting component to the
receiving component. As the transmitted packets flow through the other layers, they are extended with
additional information necessary to handle packets at those layers. At the receiving side the reverse
process occurs and packets get transformed from their Physical Layer representation to the Data Link
Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by
the Transaction Layer of the receiving device.
10.3.2
Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The Transaction Layer’s
primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are
used to communicate transactions, such as read and write, as well as certain types of events. The
Transaction Layer also manages flow control of TLPs.
Note: If the (G)MCH receives two back-to-back malformed packets, the second malformed packet is
not trapped or logged. The (G)MCH will not log or identify the second malformed packet. However,
the 1st malformed TLP is logged, and is considered a Fatal Error. Link behavior is not guaranteed at
that point whether a 2nd malformed TLP is detected or not.
10.3.3
Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an intermediate stage
between the Transaction Layer and the Physical Layer. Responsibilities of Data Link Layer include link
management, error detection, and error correction.
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10.3.4
Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and input buffers,
parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance matching circuitry.
10.4
Intel® Serial Digital Video Output (SDVO) (Intel
915GM/915GME/910GML/910GMLE/915GMS Only)
The SDVO description is located here because it is muxed onto the PCI Express x16 port pins. PCI
Express and SDVO simultaneous operation is NOT supported even though SDVO does not require all
of the PCI Express lanes. The AC/DC specifications are identical to the PCI Express Graphics
interface.
The Intel SDVO port is the second generation of digital video output from compliant Intel GMCHs.
The electrical interface is based on the PCI Express interface, though the protocol and timings are
completely unique. Whereas PCI Express runs at a fixed frequency, the frequency of the SDVO
interface is dependant upon the active display resolution and timing. The port can be dynamically
configured in several modes to support display configurations.
Essentially, an SDVO port will transmit display data in a high-speed, serial format across differential
AC coupled signals. An SDVO port consists of a sideband differential clock pair and a number of
differential data pairs.
10.4.1
Intel® SDVO Capabilities
SDVO ports can support a variety of display types including LVDS, DVI, HDMI, TV-Out, and
external CE type devices. The GMCH utilizes an external SDVO device to translate from SDVO
protocol and timings to the desired display format and timings. The Internal Graphics controller can
have one or two SDVO ports multiplexed on the x16 PCI Express interface. .
The SDVO port defines a two-wire point-to-point communication path between the SDVO device and
GMCH. The SDVO Control Clock and Data provide similar functionality to I2C. However unlike I2C,
this interface is intended to be point-to-point (from the GMCH to the SDVO device) and will require
the SDVO device to act as a switch and direct traffic from the SDVO Control bus to the appropriate
receiver. Additionally, this Control bus will be able to run at faster speeds (up to 1 MHz) than a
traditional I2C interface would.
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10.4.2
Intel® SDVO Modes
The port can be dynamically configured in several modes:
• Standard – Baseline SDVO functionality. Supports Pixel Rates between 25 and 200 MP/s.
Utilizes three data pairs to transfer RGB data.
• Extended – Adds Alpha support to data stream. Supports Pixel Rates between 25 and 200 MP/s.
Utilizes four data channels and is only supported on SDVO B. Leverages channel C (SDVO C)
Red pair as the Alpha pair for channel B (SDVO B).
• Dual Standard – Utilizes Standard data streams across both SDVO B and SDVO C. Both channels
can only run in Standard mode (3 data pairs) and each channel supports Pixel Rates between 25
and 200 MP/s.
• Dual Independent Standard - In Dual Independent Standard mode, each SDVO channel will see a
different pixel stream. The data stream across SDVO B will not be the same as the data stream
across SDVO C.
• Dual Simultaneous Standard - In Dual Simultaneous Standard mode, both SDVO channels will see
the same pixel stream. The data stream across SDVO B will be the same as the data stream across
SDVO C. The display timings will be identical, but the transfer timings may not be - i.e. B Clocks
and Data may not be perfectly aligned with SDVO C Clock and Data as seen at the SDVO
device(s). Since this utilizes just a single data stream, it utilizes a single pixel pipeline within the
GMCH.
10.5
Integrated Graphics Controller (Intel®
915GM/915GME/910GML/915GMS Only)
The GMCH provides a highly integrated graphics accelerator and chipset while allowing a flexible
integrated system graphics solution.
Figure 10-2. GMCH Graphics Controller Block Diagram
DAC (Analog)
Video Engine
M
e
m
o
r
y
TV-Out (Analog)
2D Engine
Display
Engine
Port
Mux
Control
LVDS (Digital)
SDVOB & C
3D Engine
Gfx_Blk_Dia
High bandwidth access to data is provided through the graphics and system memory ports. The GMCH
can access graphics data located in system memory at 4.2 GB/s – 8.5 GB/s (depending on memory
configuration). The GMCH uses Intel’s Direct Memory Execution model to fetch textures from system
memory.
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10.5.1
Integrated Graphics Engine Overview
GMCH’s Internal Graphics Device (IGD) contains several types of components.
The GMCH has a 3D/2D Instruction Processing unit to control the graphics engines. The IGD’s 3D
and 2D engines are fed with data through the memory controller. The output of the engines are
processed as surfaces and sent to memory, which are then retrieved and processed by GMCH’s display
planes.
The IGD graphics engine can be broken down into three components:
• 3D Engine
• 2D Engine
• Video Engine
The entire IGD is fed with data from its memory controller. The graphics performance is directly
related to the amount of bandwidth available. If the engines are not receiving data fast enough from the
memory controller (e.g., single-channel DDR333), the rest of the IGD will also be affected.
10.6
3D Engine (Intel® 915GM/915GME/910GML/910GMLE/
915GMS Only)
The 3D engine of GMCH has been designed with a deep pipelined architecture, where performance is
maximized by allowing each stage of the pipeline to simultaneously operate on different primitives or
portions of the same primitive. GMCH supports Perspective-Correct Texture Mapping, Multitextures,
Bump-Mapping, Cubic Environment Maps, Bilinear, Trilinear and Anisotropic MIP mapped filtering,
Gouraud shading, Alpha-blending, Vertex, and Per Pixel Fog and Z/W Buffering.
The 3D pipeline subsystem performs the 3D rendering acceleration. The main blocks of the pipeline are
the Setup Engine, Scan Converter, Texture Pipeline, and Raster Pipeline. A typical programming
sequence would be to send instructions to set the state of the pipeline followed by rending instructions
containing 3D primitive vertex data.
The engines’ performance is dependent on the memory bandwidth available. Systems that have more
bandwidth available will outperform systems with less bandwidth. The engines’ performance is also
dependent on the core clock frequency. The higher the frequency, the more data is processed.
10.6.1
Setup Engine
The setup stage of the pipeline takes the input data associated with each vertex of a 3D primitive and
computes the various parameters required for scan conversion. In formatting this data, GMCH
maintains sub-pixel accuracy.
10.6.1.1
3D Primitives and Data Formats Support
The 3D primitives rendered by GMCH are points, lines, discrete triangles, line strips, triangle strips,
triangle fans and polygons. In addition to this, GMCH supports the Microsoft DirectX* Flexible Vertex
Format (FVF), which enables the application to specify a variable length of parameter list obviating the
need for sending unused information to the hardware. Strips, Fans and Indexed Vertices as well as
FVF, improve the vertex rate delivered to the setup engine significantly.
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10.6.1.2
Pixel Accurate “Fast” Scissoring and Clipping Operation
The GMCH supports 2D clipping to a scissor rectangle within the drawing window. Objects are
clipped to the scissor rectangle, avoiding processing pixels that fall outside the rectangle. The GMCH’s
clipping and scissoring in hardware reduce the need for software to clip objects, and thus improve
performance. During the setup stage, GMCH clips objects to the scissor window.
A scissor rectangle accelerates the clipping process by allowing the driver to clip to a bigger region
than the hardware renders to. The scissor rectangle needs to be pixel accurate, and independent of line
and point width. GMCH will support a single scissor box rectangle, which can be enabled or disabled.
The rectangle is defined as an Inclusive box. Inclusive is defined as “draw the pixel if it is inside the
scissor rectangle”.
10.6.1.3
Depth Bias
The GMCH supports source Depth Biasing in the Setup Engine. The Depth Bias value is specified in
the vertex command packet on a per primitive basis. The value ranges from -1 to 1. The Depth Bias
value is added to the z or w value of the vertices. This is used for coplanar polygon priority. If two
polygons are to be rendered which are coplanar, due to the inherent precision differences induced by
unique x, y and z values, there is no guarantee which polygon will be closer or farther. By using Depth
Bias, it is possible to offset the destination z value (compare value) before comparing with the new z
value.
10.6.1.4
Backface Culling
As part of the setup, the GMCH discards polygons from further processing, if they are facing away
from or towards the user’s viewpoint. This operation, referred to as “Back Face Culling” is
accomplished based on the “clockwise” or “counter-clockwise” orientation of the vertices on a
primitive. This can be enabled or disabled by the driver.
10.6.1.5
Scan Converter
Working on a per-polygon basis, the Scan Converter uses the vertex and edge information is used to
identify all pixels affected by features being rendered.
10.6.1.6
Pixel Rasterization Rules
The GMCH supports both OpenGL and D3D pixel rasterization rules to determine whether a pixel is
filled by the triangle or line. For both D3D and OpenGL modes, a top-left filling convention for filling
geometry will be used. Pixel rasterization rule on rectangle primitive is also supported using the top-left
fill convention.
10.6.2
Texture Engine
The GMCH allows an image, pattern, or video to be placed on the surface of a 3D polygon.
The texture processor receives the texture coordinate information from the setup engine and the texture
blend information from the scan converter. The texture processor performs texture color or ChromaKey
matching, texture filtering (anisotropic, trilinear and bilinear interpolation), and YUV to RGB
conversions.
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10.6.2.1
Perspective Correct Texture Support
A textured polygon is generated by mapping a 2D texture pattern onto each pixel of the polygon. A
texture map is like wallpaper pasted onto the polygon. Since polygons are rendered in perspective, it is
important that texture be mapped in perspective as well. Without perspective correction, texture is
distorted when an object recedes into the distance.
10.6.2.2
Texture Formats and Storage
The GMCH supports up to 32 bits of color for textures.
10.6.2.3
Texture Decompression
DirectX supports Texture Compression to reduce the bandwidth required to deliver textures. As the
textures’ average size gets larger with higher color depth and multiple textures become the norm, it
becomes increasingly important to provide a mechanism for compressing textures. Texture
decompression formats supported include DXT1, DXT2, DXT3, DXT4, DXT5 and FXT1.
10.6.2.4
Texture ChromaKey
ChromaKey describes a method of removing a specific color or range of colors from a texture map
before it is applied to an object. For “nearest” texture filter modes, removing a color simply makes
those portions of the object transparent (the previous contents of the back buffer show through). For
“linear” texture filtering modes, the texture filter is modified if only the non-nearest neighbor texels
match the key (range).
10.6.2.5
Anti-Aliasing
Aliasing is one of the artifacts that degrade image quality. In its simplest manifestation, aliasing causes
the jagged staircase effects on sloped lines and polygon edges. Another artifact is the moiré patterns
which occur as a result of a very small number of pixels available on screen to contain the data of a
high resolution texture map. More subtle effects are observed in animation, where very small primitives
blink in and out of view.
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10.6.2.6
Texture Map Filtering
The GMCH supports many texture mapping modes. Perspective correct mapping is always performed.
As the map is fitted across the polygon, the map can be tiled, mirrored in either the U or V directions,
or mapped up to the end of the texture and no longer placed on the object (this is known as clamp
mode). The way a texture is combined with other object attributes is also definable.
The GMCH supports up to 12 Levels-of-Detail (LODs) ranging in size from 2048x2048 to 1x1 texels.
Textures need not be square. Included in the texture processor is a texture cache, which provides
efficient MIP mapping.
The GMCH supports seven types of texture filtering:
1. Nearest (Point Filtering): Texel with coordinates nearest to the desired pixel is used. (This is used
if only one LOD is present.)
2. Linear (Bilinear Filtering): A weighted average of a 2x2 area of texels surrounding the desired
pixel is used. (This is used if only one LOD is present.)
3. Nearest MIP Nearest (Point Filtering): This is used if many LODs are present. The nearest LOD is
chosen and the texel with coordinates nearest to the desired pixel is used.
4. Linear MIP Nearest (Bilinear MIP Mapping): This is used if many LODs are present. The nearest
LOD is chosen and a weighted average of a 2x2 area of texels surrounding the desired pixel is used
(four texels). This is also referred to as Bilinear MIP Mapping.
5. Nearest MIP Linear (Point MIP Mapping): This is used if many LODs are present. Two
appropriate LODs are selected and within each LOD the texel with coordinates nearest to the
desired pixel is selected. The Final texture value is generated by linear interpolation between the
two texels selected from each of the MIP Maps.
6. Linear MIP Linear (Trilinear MIP Mapping): This is used if many LODs are present. Two
appropriate LODs are selected and a weighted average of a 2x2 area of texels surrounding the
desired pixel in each MIP Map is generated (four texels per MIP Map). The Final texture value is
generated by linear interpolation between the two texels generated for each of the MIP Maps.
Trilinear MIP Mapping is used minimize the visibility of LOD transitions across the polygon.
7. Anisotropic MIP Nearest (Anisotropic Filtering): This is used if many LODs are present. The
nearest LOD-1 level will be determined for each of four sub-samples for the desired pixel. These
four sub-samples are then bilinear filtered and averaged together.
8. Both D3D (DirectX 6.0) and OGL (Rev.1.1) allow support for all these filtering modes.
10.6.2.7
Multiple Texture Composition
The GMCH also performs multiple texture composition. This allows the combination of two or greater
MIP Maps to produce a new one with new LODs and texture attributes in a single or iterated pass.
Flexible vertex format support allows multitexturing because it makes it possible to pass more than one
texture in the vertex structure.
10.6.2.8
Bi-Cubic Filter (4x4 Programmable Texture Filter)
A bi-cubic texture filter can be selected instead of the bilinear filter. The implementation is of a 4x4
separable filter with loadable coefficients. A 4x4 filter can be used for providing high-quality up/ down
scaling of 2D or 3D rendered images
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10.6.2.9
Cubic Environment Mapping
Environment maps allow applications to render scenes with complex lighting and reflections while
significantly decreasing CPU load. There are several methods to generate environment maps such as
spherical, circular and cubic. The GMCH supports cubic reflection mapping over spherical and circular
since it is the best choice to provide real-time environment mapping for complex lighting and
reflections.
Cubic Mapping requires a texture map for each of the 6 cube faces. These can be generated by pointing
a camera with a 90-degree field-of-view in the appropriate direction. Per-vertex vectors (normal,
reflection or refraction) are interpolated across the polygon and the intersection of these vectors with
the cube texture faces is calculated. Texel values are then read from the intersection point on the
appropriate face and filtered accordingly.
10.6.3
Raster Engine
The Raster Engine is where the color data such as fogging, specular RGB, texture map blending, etc. is
processed. The final color of the pixel is calculated and the RGBA value combined with the
corresponding components resulting from the Texture Engine. These textured pixels are modified by
the specular and fog parameters. These specular highlighted, fogged, textured pixels are color blended
with the existing values in the frame buffer. In parallel, stencil, alpha and depth buffer tests are
conducted which will determine whether the Frame and Depth buffers will be updated with the new
pixel values.
10.6.3.1
Texture Map Blending
Multiple Textures can be blended together in an iterative process and applied to a primitive. The
GMCH allows up to four texture coordinates and texture maps to be specified onto the same polygon.
Also, the GMCH supports using a texture coordinate set to access multiple texture maps. State
variables in multiple texture are bound to texture coordinates, texture map or texture blending.
10.6.3.2
Combining Intrinsic and Specular Color Components
The GMCH allows an independently specified and interpolated “specular RGB” attribute to be added
to the post-texture blended pixel color. This feature provides a full RGB specular highlight to be
applied to a textured surface, permitting a high quality reflective colored lighting effect not available in
devices which apply texture after the lighting components have been combined. If specular-add state
variable is disabled, only the resultant colors from the map blending are used. If this state variable is
enabled, RGB values from the output of the map blending are added to values for RS, GS, BS on a
component by component basis.
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10.6.3.3
Color Shading Modes
The Raster Engine supports the flat and Gouraud shading modes. These shading modes are
programmed by the appropriate state variables issued through the command stream.
Flat shading is performed by smoothly interpolating the vertex intrinsic color components (Red, Green,
Blue), Specular Highlights (R,G,B), Fog, and Alpha to the pixel, where each vertex color has the same
value. The setup engine substitutes one of the vertex’s attribute values for the other two vertices
attribute values thereby creating the correct flat shading terms. This condition is set up by the
appropriate state variables issued prior to rendering the primitive.
OpenGL and D3D use a different vertex to select the flat shaded color. This vertex is defined as the
“provoking vertex”. In the case of strips/fans, after the first triangle, attributes on every vertex that
define a primitive are used to select the flat color of the primitive. A state variable is used to select the
“flat color” prior to rendering the primitive.
Gouraud shading is performed by smoothly interpolating the vertex intrinsic color components (Red,
Green, Blue). Specular Highlights (R,G,B), Fog, and Alpha to the pixel, where each vertex color has a
different value.
All the attributes can be selected independently from one of the shading modes by setting the
appropriate value state variables.
10.6.3.4
Color Dithering
Color Dithering helps to hide color quantization errors. Color Dithering takes advantage of the human
eye’s propensity to “average” the colors in a small area. Input color, alpha, and fog components are
converted from 8-bit components to 5- or 6- bit component by dithering. Dithering is performed on
blended textured pixels. In 32-bit mode, dithering is not performed on the components
10.6.3.5
Vertex and Per Pixel Fogging
Fogging is used to create atmospheric effects such as low visibility conditions in flight simulator- type
games. It adds another level of realism to computer-generated scenes. Fog can be used for depth cueing
or hiding distant objects. With fog, distant objects can be rendered with fewer details (fewer polygons),
thereby improving the rendering speed or frame rate. Fog is simulated by attenuating the color of an
object with the fog color as a function of distance. The higher the density (lower visibility for distant
objects). There are two ways to implement the fogging technique: per-vertex (linear) fogging and perpixel (non-linear) fogging. The per-vertex method interpolates the fog value at the vertices of a
polygon to determine the fog factor at each pixel within the polygon. This method provides realistic
fogging as long as the polygons are small. With large polygons (such as a ground plane depicting an
airport runway), the per-vertex technique results in unnatural fogging.
The GMCH supports both types of fog operations, vertex and per pixel or table fog. If fog is disabled,
the incoming color intensities are passed unchanged to the destination blend unit.
10.6.3.6
Alpha Blending (Frame Buffer)
Alpha Blending adds the material property of transparency or opacity to an object. Alpha blending
combines a source pixel color (RSGSBS) and alpha (AS) component with a destination pixel color
(RDGDBD) and alpha (AD) component. For example, this is so that a glass surface on top (source) of a
red surface (destination) would allow much of the red base color to show through.
Blending allows the source and destination color values to be multiplied by programmable factors and
then combined via a programmable blend function. The combined and independent selection of factors
and blend functions for color and alpha are supported.
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10.6.3.7
Microsoft Direct X* API and SGI OpenGL Logic Ops
Both APIs provide a mode to use bitwise ops in place of alpha blending. This is used for rubberbanding, i.e., draw a rubber band outline over the scene using an XOR operation. Drawing it again
restores the original image without having to do a potentially expensive redraw.
10.6.3.8
Color Buffer Formats: 8-, 16-, or 32-bits per pixel (Destination Alpha)
The Raster Engine will support 8-bit, 16-bit, and 32-bit Color Buffer Formats. The 8-bit format is used
to support planar YUV420 format, which used only in Motion Compensation and Arithmetic Stretch
format. The bit format of Color and Z will be allowed to mix.
The GMCH supports both double and triple buffering, where one buffer is the primary buffer used for
display and one or two are the back buffer(s) used for rendering.
The frame buffer of the GMCH contains at least two hardware buffers—the Front Buffer (display
buffer) and the Back Buffer (rendering buffer). While the back buffer may actually coincide with (or be
part of) the visible display surface, a separate (screen or window-sized) back buffer is used to permit
double-buffered drawing. That is, the image being drawn is not visible until the scene is complete and
the back buffer made visible (via an instruction) or copied to the front buffer (via a 2D BLT operation).
Rendering to one and displaying from the other remove the possibility of image tearing. This also
speeds up the display process over a single buffer. Additionally, triple back buffering is also supported.
The instruction set of the GMCH provides a variety of controls for the buffers (e.g., initializing, flip,
clear, etc.).
10.6.3.9
Depth Buffer
The Raster Engine will be able to read and write from this buffer and use the data in per fragment
operations that determine whether resultant color and depth value of the pixel for the fragment are to be
updated or not.
Typical applications for entertainment or visual simulations with exterior scenes require far/near ratios
of 1000 to 10000. At 1000, 98% of the range is spent on the first 2% of the depth. This can cause
hidden surface artifacts in distant objects, especially when using 16-bit depth buffers. A 24 bit Z-buffer
provides 16 million Z-values as opposed to only 64 K with a 16-bit Z buffer. With lower Z-resolution,
two distant overlapping objects may be assigned the same Z-value. As a result, the rendering hardware
may have a problem resolving the order of the objects, and the object in the back may appear through
the object in the front.
By contrast, when W (or eye-relative Z) is used, the buffer bits can be more evenly allocated between
the near and far clip planes in world space. The key benefit is that the ratio of far and near is no longer
an issue, allowing applications to support a maximum range of miles, yet still get reasonably accurate
depth buffering within inches of the eye point.
The GMCH supports a flexible format for the floating-point W buffer, wherein the number of exponent
bits is programmable. This allows the driver to determine variable precision as a function of the
dynamic range of the W (screen-space Z) parameter.
The selection of depth buffer size is relatively independent of the color buffer. A 16-bit Z/W or 24 bit
Z/W buffer can be selected with a 16-bit color buffer. Z buffer is not supported in 8-bit mode.
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10.6.3.10
Stencil Buffer
The Raster Engine will provide 8-bit stencil buffer storage in 32-bit mode and the ability to perform
stencil testing. Stencil testing controls 3D drawing on a per pixel basis, conditionally eliminating a
pixel on the outcome of a comparison between a stencil reference value and the value in the stencil
buffer at the location of the source pixel being processed. They are typically used in multipass
algorithms to achieve special effects, such as decals, outlining, shadows and constructive solid
geometry rendering.
10.6.3.11
Projective Textures
The GMCH will support two, simultaneous projective textures at full rate processing, and four textures
at half rate. These textures require three floating point texture coordinates to be included in the Flexible
Vertex Format(FVF). Projective textures enable special effects such as projecting spot light textures
obliquely onto walls, etc.
10.7
2D Engine (Intel® 915GM/915GME/910GML/910GMLE/
915GMS Only)
The GMCH contains BLT functionality, and an extensive set of 2D instructions. To take advantage of
the 3D drawing engine’s functionality, some BLT functions such as Alpha BLTs, arithmetic (bilinear)
stretch BLTs, rotations, transposing pixel maps, limited color space conversion, and DIBs make use of
the 3D renderer.
10.7.1
GMCH VGA Registers
The 2D registers are a combination of registers based on the Video Graphics Array (VGA) adapter and
others that Intel has added to support graphics modes that have color depths, resolutions, and hardware
acceleration features that go beyond the original VGA standard.
10.7.2
2D Functionality
10.7.2.1
Block Level Transfer (BLT) Function
The stretch BLT function can stretch source data in the X and Y directions to a destination larger or
smaller than the source. Stretch BLT functionality expands a region of memory into a larger or smaller
region using replication and interpolation. The stretch BLT function also provides format conversion
and data alignment.
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10.7.2.2
Logical 128-bit Fixed BLT and 256-bit Fill Engine
Use of this BLT engine accelerates the Graphical User Interface (GUI) of Microsoft Windows*
operating systems. The 128-bit GMCH BLT Engine provides hardware acceleration of block transfers
of pixel data for many common Windows operations. The term BLT refers to a block transfer of pixel
data between memory locations. The BLT engine can be used for the following:
• Move rectangular blocks of data between memory locations
• Data alignment
• Perform logical operations (raster ops)
The rectangular block of data does not change as it is transferred between memory locations. The
allowable memory transfers are between: cacheable system memory and frame buffer memory, frame
buffer memory and frame buffer memory, and within system memory. Data to be transferred can
consist of regions of memory, patterns, or solid color fills. A pattern will always be 8x8 pixels wide
and may be 8, 16, or 32 bits per pixel.
The GMCH BLT engine has the ability to expand monochrome data into a color depth of 8, 16, or 32
bits. BLTs can be either opaque or transparent. Opaque transfers move the data specified to the
destination. Transparent transfers compare destination color to source color and write according to the
mode of transparency selected.
Data is horizontally and vertically aligned at the destination. If the destination for the BLT overlaps
with the source memory location, the GMCH can specify which area in memory to begin the BLT
transfer. Hardware is included for all 256 raster operations (Source, Pattern, and Destination) defined
by Microsoft, including transparent BLT.
The GMCH has instructions to invoke BLT and stretch BLT operations, permitting software to set up
instruction buffers and use batch processing. The GMCH can perform hardware clipping during BLTs.
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10.8
Video Engine (Intel® 915GM/915GME/910GML/
910GMLE/915GMS Only)
10.8.1
Hardware Motion Compensation
The motion compensation (MC) process consists of reconstructing a new picture by predicting (either
forward, backward, or bi-directionally) the resulting pixel colors from one or more reference pictures.
The GMCH receives the video stream and implements MC and subsequent steps in hardware.
Performing MC in hardware reduces the processor demand of software-based MPEG-2 decoding, and
thus improves system performance.
The MC functionality is overloaded onto the texture cache and texture filter. The texture cache is used
to typically access the data in the reconstruction of the frames and the filter is used in the actual motion
compensation process. To support this overloaded functionality the texture cache additionally supports
the following input formats: YUV420 planar.
10.8.2
Sub-Picture Support
Sub-picture is used for two purposes, one is Subtitles for movie captions, etc. (which are superimposed
on a main picture), and menus used to provide some visual operation environments the user of a
content player.
DVD allows movie subtitles to be recorded as Sub-pictures. On a DVD disc, it is called "Subtitle"
because it has been prepared for storing captions. Since the disc can have a maximum of 32 tracks for
Subtitles, they can be used for various applications, for example, as Subtitles in different languages or
other information to be displayed.
There are two kinds of menus, the system menus and other In-Title Menus. First, the system menus are
displayed and operated at startup of or during the playback of the disc or from the stop state. Second,
In-Title menus can be programmed as a combination of Sub-picture and Highlight commands to be
displayed during playback of the disc.
The GMCH supports sub-picture for DVD and DBS by mixing the two video streams via alpha
blending. Unlike color keying, alpha blending provides a softer effect and each pixel that is displayed
is a composite between the two video stream pixels. The GMCH can utilize four methods when
dealing with sub-pictures. The flexibility enables the GMCH to work with all sub- picture formats.
10.8.3
De-interlacing Support
For display on a progressive computer monitor, interlaced data that has been formatted for display on
interlaced monitors (TV), needs to be de-interlaced. The simple approaches to de-interlacing create
unwanted display artifacts. More advanced de-interlacing techniques have a large cost associated with
them. The compromise solution is to provide a low cost but effective solution and enable both
hardware and software based external solutions. Software based solutions are enabled through a high
bandwidth transfer to system memory and back.
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10.8.3.1
Dynamic Bob and Weave
Interlaced data that originates from a video camera creates two fields that are temporally offset by 1/60
of a second. There are several schemes to de-interlace the video stream: line replication, vertical
filtering, field merging and vertical temporal filtering. Field merging takes lines from the previous field
and inserts them into the current field to construct the frame – this is known as Weaving. This is the
best solution for images with little motion however, showing a frame that consists of the two fields will
have serration or feathering of moving edges when there is motion in the scene. Vertical filtering or
“Bob” interpolates adjacent lines rather replicating the nearest neighbor. This is the best solution for
images with motion however, it will have reduced spatial resolution in areas that have no motion and
introduces jaggies. In absence of any other de-interlacing, these form the baseline and are supported by
the GMCH.
10.9
Display Interfaces (Intel® 915GM/915GME/910GML/
910GMLE/915GMS Only)
Note:
The Intel 915GME and Intel 910GMLE chipsets do not support the TV-Out display interface.
The display is the defining portion of a graphics controller. The display converts a set of source images
or surfaces, combines them and sends them out at the proper timing to an output interface connected to
a display device. Along the way, the data can be converted from one format to another, stretched or
shrunk, and color corrected or gamma converted.
The GMCH is able to drive a CRT, LCD panel, Analog TV and/or two SDVO ports (muxed with PCI
Express) capable of driving an SDVO device. External SDVO devices are capable of driving a standard
progressive scan analog monitor with resolutions up to 2048x1536 at 75 Hz. The SDVO ports are
capable of driving a variety of TV-Out, TMDS, and LVDS transmitters.
10.9.1
Display Overview
The graphics display can be broken down into three components:
• Display Planes
• Display Pipes
• Display Ports
The display planes are broken down into: primary and secondary display, overlay, sprite, primary and
secondary cursor and VGA.
The display pipe consists of the target where the display planes that will be combined meet and a
timing generator to set the graphics timing modes. The timing generator determines which time the
display occurs.
The display port is the destination for the result of the pipe. The GMCH contains five display ports,
two analog (CRT DAC and TV out) and three digital (LVDS, SDVO B and SDVO C). The ports will
be explained in more detail later in this chapter.
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10.9.2
Planes
The GMCH contains a variety of planes, such as primary and secondary display, overlay, sprite,
primary and secondary cursor and VGA. A plane consists of rectangular shaped image that has
characteristics such as source, size, position, method, and format. These planes get attached to source
surfaces, which are rectangular memory surfaces with a similar set of characteristics. They are also
associated with a particular destination pipe.
10.9.2.1
Display Plane
The primary and secondary display plane works in an indexed move, hi-color mode or a true color
mode. The true color mode allows for an 8-b alpha channel. One of the primary operations of the
display plane is the set mode operation. The set-mode operation occurs when it is desired to enable a
display, change the display timing, or source format. The secondary display plane can be used as a
primary surface on the secondary display or as a sprite planes on either the primary or secondary
display.
10.9.2.2
Cursor A/B Plane
The cursor planes are one of the simplest display planes. The cursors can operate as cursors or as a
popup. The cursors can operate in either the alpha blended mode or the AND/XOR mode. These planes
are always the top in the Z-order with the other planes. When both cursors are on the same display
pipe, cursor A is always above cursor B. With a few exceptions, the cursor plan has a fixed size of
64x64 and a fixed Z-order (top). In legacy modes, cursor can cause the display data below it to be
inverted.
10.9.2.3
Cursor Color Formats
Color data can be in an indexed format or a true color format. Indexed data uses the entries in the four
entry cursor palette to convert the two-bit index to a true color format before being passed to the
blenders. The index can optionally specify that a cursor pixel be transparent or cause an inversion of
the pixel value below it or one of two colors from the cursor palette. Blending of YUV or RGB data is
only supported with planes that have data of the same format.
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10.9.2.4
Popup Cursor
The popup cursor plane is used for control functions in mobile applications. This is not used for typical
desktop applications. Either Cursor or cursor B can be used as a popup with exceptions based on
restrictions on usage of cursor B
The requirements for the hardware icon
• 64 by 64 pixels 4 colors
• Displayable in all standard and centered VGA modes and all extended modes
• Can be positioned anywhere on the screen
• Flat memory addressing for source (can load images with a single string move instruction)
Only the hardware cursor has a higher Z-order precedence over the hardware icon. Icon should appear
over any video windows (full motion video or live video input) but should appear under the hardware
cursor if it exists.
Hardware icon memory must be protected from being overwritten by video drivers, video BIOS or the
video controller itself. This can be done through software (the video BIOS and drivers are aware of the
icon memory and do not use it).
In standard modes (non-VGA) either cursor A or cursor B can be used for a popup with the limitations
of cursor B cannot be used in double wide mode. VGA and double wide modes must use cursor A for
the popup. Popup on the VGA modes must not use the 32-bpp data format.
10.9.2.5
Overlay Plane
The overlay engine provides a method of merging either video capture data (from an external Video
Capture device) or data delivered by the CPU, with the graphics data on the screen. The source data
can be mirrored horizontally or vertically or both.
Source/Destination Color Keying/Chroma Keying
Overlay source/destination Chroma Keying enables blending of the overlay with the underlying
graphics background. Destination color keying/Chroma Keying can be used to handle occluded
portions of the overlay window on a pixel by pixel basis that is actually an underlay. Destination
Chroma Keying would only be used for YUV pass through to TV. Destination color keying supports a
specific color (8- or 15-bit) mode as well as 32-bit alpha blending.
Source color keying/Chroma Keying is used to handle transparency based on the overlay window on a
pixel by pixel basis. This is used when “blue screening” an image to overlay the image on a new
background later.
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Gamma Correction
Gamma correction is applied to the video signal to compensate for the nonlinear characteristics of the
display device and the human eye. Applying the correction at the source for digital data makes the best
use of the limited number of bits available for each of the color components. The amount of correction
applied is determined by the tube characteristics and is different for NTSC TVs (2.2), PAL TVs (2.8),
and SVGA type (1.4-2.8) monitors.
To compensate for overlay color intensity loss due to the non-linear response between display devices,
the overlay engine supports independent gamma correction. This allows the overlay data to be
converted to linear data or corrected for the display device when not blending.
YUV to RGB Conversion
The format conversion can be bypassed in the case of RGB source data. The format conversion
assumes that the YUV data is input in the 4:4:4 format and uses the full range scale.
Maximum Resolution and Frequency
The maximum frequency supported by the overlay logic is 180 MHz. The maximum resolution is
dependent on a number of variables.
Deinterlacing Support
For display on a progressive computer monitor, interlaced data that has been formatted for display on
interlaced monitors (TV), needs to be de-interlaced. The simple approaches to de-interlacing create
unwanted display artifacts. More advanced de-interlacing techniques have a large cost associated with
them. The compromise solution is to provide a low cost but effective solution and enable both
hardware and software based external solutions. Software based solutions are enabled through a high
bandwidth transfer to system memory and back.
10.9.2.6
Dynamic Bob and Weave
Weaving is done by - field merging takes lines from the previous field and inserts them into the current
field to construct the frame. This is the best solution for images with little motion however, showing a
frame that consists of the two fields will have serration or feathering of moving edges when there is
motion in the scene.
Vertical filtering or “Bob” interpolates adjacent lines rather replicating the nearest neighbor. This is the
best solution for images with motion. However, it will have reduced spatial resolution in areas that
have no motion and may introduce jagged edges. In absence of any other deinterlacing, these form the
baseline and are supported by the GMCH.
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Scaling Filter and Control
The scaling filter has three vertical taps and five horizontal taps. Arbitrary scaling (per pixel
granularity) for any video source (YUV422 or YUV420) format is supported.
The overlay logic can scale an input image up to 1600X1200 with no major degradation in the filter
used as long as the maximum frequency limitation is met. Display resolution and refresh rate
combinations where the dot clock is greater than the maximum frequency require the overlay to use
pixel replication.
10.9.2.7
VGA Plane
The VGA plane is a special plane. It is based on legacy interfaces and provides legacy support for
applications that use VGA register interface. VGA only works in indexed display modes. The VGA
plane is a special case plane. It operates in several modes and has a set of restrictions on its use. It is not
to operate with any other planes active except the pop-up plane.
10.9.3
Display Pipes
The GMCH has two independent display pipes, allowing for support of two independent display
streams. The pipe is the target of a set of combined planes (done at the Alpha blender) and a timing
generator to setup the display timing graphics modes. The timing generators provide the basic timing
information for each of the display pipes.
Pipe A can operate in a single-wide or “double-wide” mode at 2x graphics core clock though they are
effectively limited by the perspective display port. The display planes and the cursor plane will provide
a “double wide” mode to feed the pipe.
10.9.4
Clock Generator Units (DPLL)
The GMCH provides two DPLL clock generator units provide a stable frequency for driving display
pipes. It operates by converting an input reference frequency into an output frequency. The timing
generators take their input from internal DPLL devices that are programmable to generate pixel clocks
in the range of 25-400 MHz. Accuracy for VESA timing modes is required to be within ± 0.5%.
The DPLL can take a reference frequency from the external reference input (DREF_CLKINN/P),
(DREF_SSCCLKINN/P) the TV clock input (TVCLKIN).
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10.10
Display Ports (Intel® 915GM/915GME/910GML/
910GMLE/915GMS Only)
A port is the destination for the result of the pipe. The GMCH has five display ports, two analog and
three digital.
• CRT
• LVDS
• TV out (Not supported by the Intel 915GME / Intel 910GMLE)
• SDVO B
• SDVO C
The GMCH has one dedicated CRT display port, one TV out port, one LVDS port, and two SDVO
ports. SDVO ports B and C are multiplexed with the PCI Express based Graphics interface and are not
available if an external PCI Express based Graphics device is in use or a PCI Express x1 device is used.
SDVO Ports B and C can also operate in dual-channel mode, where the data bus is connected to both
display ports, allowing a single device to take data at twice the pixel rate.
Table 10-10. Display Port Characteristics
Interface Protocol
S
N
L
RGB DAC
LVDS
Port B
(Digital)
Port C
(Digital)
sDVO 1.0
sDVO 1.0
Yes
Enable/Polar
ity
Encoded during blanking codes
VSYNC
Yes
Enable/Polar
ity
Encoded during blanking codes
BLANK
No
No
Encoded
Encoded
STALL
No
No
Yes
Yes
A
S
LVDS
HSYNC
I
G
(Analog)
Field
No
No
No
No
Display_Enable
No
Yes*
Encoded
Encoded
Image Aspect Ratio
Programmable and typically 1.33:1 or 1.78:1
Pixel Aspect Ratio
Square*
Square
Voltage
RGB 0.7V pp
1.2 VDC
300 mV p-p
Scalable 1.x V
Clock
NA
7x
Differential
See sDVO clocking section: Differential
Max Rate
350 Mpixel
224 MPixel
400 Mpixel
Format
Analog RGB
Multiple
18/ 24 bpp
RGB 8:8:8 YUV 4:4:4
Control Bus
DDC1/DDC2
B
Optional
DDC
GMBUS
External Device
No
No
TMDS/LVDS Transmitter /TV Encoder
Connector
VGA/DVI-I
Special Functions
Monitor
Sense
Power
Sequence
Hot Plug
Detection
Muxed on PCI Express
Based Graphics
No
No
200/400 Mpixel
DVI/CVBS/S-Video/Component/SCART
High speed
mode
TV Sense
SCART
WSS
Yes
Yes
NOTE: Single signal software selectable between display enable and Blank#.
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10.10.1
Analog Display Port Characteristics
The GMCH’s analog port utilizes an integrated 400 MHz RAMDAC that can directly drive a standard
progressive scan analog monitor up to a resolution of 2048x1536 pixels with 32-bit color at 75 Hz.
The analog display port provides a RGB signal output along with a HSYNC and VSYNC signal. There
is an associated DDC signal pair that is implemented using GPIO pins dedicated to the analog port. The
intended target device is for a CRT based monitor with a VGA connector. Display devices such as
LCD panels with analog inputs may work satisfactory but no functionality has been added to the
signals to enhance that capability.
Table 10-11. Analog Port Characteristics
Signal
RGB
Port Characteristic
Support
Voltage Range
0.7 V p-p only
Monitor Sense
Analog Compare
Analog Copy Protection
No
Sync on Green
No
Voltage
2.5 V
Enable/Disable
Port control
HSYNC
Polarity adjust
VGA or port control
VSYNC
Composite Sync Support
No
Special Flat Panel Sync
No
DDC
10.10.1.1
Stereo Sync
No
Voltage
Externally buffered to 5V
Control
Through DDC interface
Integrated RAMDAC
The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that transforms
the digital data from the graphics and video subsystems to analog data for the CRT monitor. GMCH’s
integrated 400 MHz RAMDAC supports resolutions up to 2048 x 1536 at 75 Hz. Three, 8-bit DACs
provide the R, G, and B signals to the monitor.
10.10.1.2
Sync Signals
HSYNC and VSYNC signals are digital. External level shifting buffers are required. These signals can
be polarity adjusted and individually disabled in one of the two possible states. The sync signals should
power up disabled in the high state. No composite sync or special flat panel sync support will be
included.
10.10.1.3
VESA/VGA Mode
VESA/VGA mode provides compatibility for pre-existing software that set the display mode using the
VGA CRTC registers. Timings are generated based on the VGA register values.
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10.10.1.4
DDC (Display Data Channel)
DDC is a standard defined by VESA. Its purpose is to allow communication between the host system
and display. Both configuration and control information can be exchanged allowing Plug and Play*
systems to be realized. Support for DDC 1 and 2 is implemented. The Mobile Intel 915 Express
Chipset Family uses the CRTDDCCLK and CRTDDCDATA signals to communicate with the analog
monitor. Mobile Intel 915 Express Chipset Family will generate these signals at 2.5 V. External pull-up
resistors and level shifting circuitry should be implemented on the board.
The GMCH implements a hardware GMBus controller that can be used to control these signals
allowing for transactions speeds up to 400 kHz.
10.10.2
Dedicated TV Out Port
Note:
No feature in section 10.10.2 is supported by the Intel 915GME / Intel 910GMLE chipsets.
• Integrated TV-out device supported on Display pipe A and pipe B.
• Three Integrated 10 bit DAC
• NTSC/PAL encoder standard formats supported
• Up to 1024x768 resolution supported for NTSC/PAL
• Multiplexed Output interface:
• Composite Video
• S-Video
• Component Video (YprPb)
• Combination: (Composite & S-Video)
• Tri-level Sync signal
• Macrovision support
• Overscan Scaling Support
10.10.2.1
Connectors
The TV-Out interface support three connector types
• Composite (CVBS)
• S-Video
• Component
10.10.2.2
Composite Video Connector
Composite video is connected through a single RCA type connector. This carries the CVBS signal and
does not include audio. Audio is normally associated with the video and comes in a single (for mono)
or two RCA connectors (stereo).
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10.10.2.3
S-Video Connector
The S-Video signal and connector provide an improved quality video image over the composite image
by sending separate luminance and chrominance channels. Cross talk between chrominance and
luminance is eliminated and the horizontal resolution is increased due to the elimination of the low pass
filter in the luminance path. Both the S-Video 4-pin mini DIN connector and the SCART can support
this signal type.
10.10.2.4
Component Analog YUV connector
Newer TVs can be connected to a DVD player through an analog YUV connection. These connectors
might be labeled as YUV, Y R-Y B-Y, YCrCb, or Y Pr Pb. Three separate RCA connector/cables are
used to make the connection. The 1.0 V Y signal includes a 0.3 V sync signal and the U and V signals
are 0.7 V. If WSS information is present, it will be on the Y signal.
10.10.2.5
Content Protection
Content protection will be provided through the external encoder using Macrovision. DVD software
must verify the presence of a Macrovision TV encoder before playback continues. Simple attempts to
disable the Macrovision operation must be detected.
10.10.3
Dedicated LFP LVDS Port
The GMCH has a dedicated ANSI/TIA/EIA –644-1995 Specification compliant dual channel LFP
LVDS interface that can support TFT panel resolutions up to UXGA with a maximum pixel format of
18 bpp, and with SSC supported frequency range from 25 MHz to 112 MHz (single channel/dual
channel).
The display pipe selected by the LVDS display port is programmed with the panel timing parameters
that are determined by installed panel specifications or read from an onboard EDID ROM. The
programmed timing values are then “locked” into the registers to prevent unwanted corruption of the
values. From that point on, the display modes are changed by selecting a different source size for that
pipe, programming the VGA registers, or selecting a source size and enabling the VGA. The timing
signals will remain stable and active through mode changes. These mode changes include VGA to
VGA, VGA to HiRes, HiRes to VGA, and HiRes to HiRes.
The transmitter can operate in a variety of modes and supports several data formats. The serializer
supports 6-bit or 8-bit color and single or dual channel operating modes. The display stream from the
display pipe is sent to the LVDS transmitter port at the dot clock frequency, which is determined by the
panel timing requirements. The output of LVDS is running at a fixed multiple of the dot clock
frequency, which is determined by the mode of operation; single or dual channel.
Depending on configuration and mode, a single channel can take 18 bits of RGB pixel data plus 3 bits
of timing control (HSYNC/VSYNC/DE) and output them on three differential data pair outputs. A
dual channel interface converts 36 of color information plus the 3 bits of timing control and outputs it
on six or eight sets of differential data outputs.
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This display port is normally used in conjunction with the pipe functions of panel scaling and 6-8-bit
dither. This display port is also used in conjunction with the panel power sequencing and additional
associated functions.
When enabled, the LVDS constant current drivers consume significant power. Individual pairs or sets
of pairs can be selected to be powered down when not used. When disabled, individual or sets of pairs
will enter a low power state. When the port is disabled all pairs enters a low power mode. The panel
power sequencing can be set to override the selected power state of the drivers during power
sequencing.
For more details on using the GMCH’s LFP LVDS interface for TFT panel support, please refer to the
Common Panel Interface Specification, Rev 1.6 for details on:
10.10.4
LVDS panel support
Table 10-12. LVDS Panel support
LVDS panel
XGA
SXGA
SXGA+
UXGA
1024 x 768
1280 x 1024
1400 x 1050
1600 x 1200
X
Intel 915GM
X
X
X
Intel 915GMS *
X
X
X
Intel 910GML
X
X
X
Note:
Intel 915GMS only supports single channel LVDS panel types.
Table 10-13. LVDS Wide Panel support
LVDS panel
WXGA
WSXGA+
WUXGA
1280 x 760
1600 x 900
1920 x 1200
Intel 915GM
X
X
X
Intel 915GMS *
X
Note:
10.10.5
Intel 915GMS only supports single channel LVDS panel types.
LVDS Interface Signals
LVDS for flat panel is compatible with the ANSI/TIA/EIA-644 specification. This is an electrical
standard only defining driver output characteristics and receiver input characteristics. There are two
LVDS transmitter channels (channel A and channel B) in the LVDS interface. Each channel consists of
4-data pairs and a clock pair. The interface consists of a total of ten differential signal pairs of which
eight are data and two are clocks. The phase locked transmit clock is transmitted in parallel with the
data being sent out over the data pairs and over the LVDS clock pair.
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Each channel supports transmit clock frequency ranges from 25 MHz to 112 MHz, which provides a
throughput of up to 784 Mbps on each data output and up to 112 MP/s on the input. When using both
channels, they each operate at the same frequency each carrying a portion of the data. The maximum
pixel rate is increased to 224 MP/s but may be limited to less than that due to restrictions elsewhere in
the circuit.
The LVDS Port enable bit enables or disables the entire LVDS interface. When the port is disabled, it
will be in a low power state. Once the port is enabled, individual driver pairs will be disabled based on
the operating mode. Disabled drivers can be powered down for reduced power consumption or
optionally fixed to forced 0’s output.
10.10.6
LVDS Data Pairs and Clock Pairs
The LVDS data and clock pairs are identical buffers and differ only in the use defined for that pair.
The LVDS data pair is used to transfer pixel data as well as the LCD timing control signals. The pixel
bus data to serial data mapping options are specified elsewhere. A single or dual clock pair is used to
transfer clocking information to the LVDS receiver. A serial pattern of 1100011 represents one cycle
of the clock.
There are two LVDS transmitter channels (channel A and channel B) in the LVDS interface. Each
channel contains 1 clock pair and 3-data pair of low voltage differential swing signals. Diagram below
shows a pair of LVDS signals and swing voltage.
Figure 10-3. LVDS Swing Voltage
Vb
Va
1.425V
1.372V
1.325V
"1"
"0"
450mV
344mV
250mV
"1"
0.0mV
250mV
344mV
450mV
1.20V
1.075V
1.028V
0.975V
| Va - Vb |
"0"
NOTE: 1’s and 0’s are represented the differential voltage between the pair of signals.
Figure 10-4. LVDS Clock and Data Relationship
LVDS Clock Pair
1
1
1
0
0
0
1
1
1
LVDS Data Pair
7th
data
1st
data
2nd
data
3rd
data
4th
data
5th
data
6th
data
7th
data
1st
data
LVDS Clock and data
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10.10.7
LVDS Pair States
The LVDS pairs can be put into one of five states, powered down tri-state, powered down 0 V,
common mode, send zeros, or active. When in the active state, several data formats are supported.
When in powered down state, the circuit enters a low power state and drives out 0 V or tri-states on
both the output pins for the entire channel. The common mode tri-state is both pins of the pair set to
the common mode voltage. The common mode state only occurs on B3, A3, or CLKB. These are the
signals that optionally get used when driving either 18-bpp panels or dual channel with a single clock.
When in the send zeros state, the circuit is powered up but sends only zero for the pixel color data
regardless what the actual data is with the clock lines and timing signals sending the normal clock and
timing data.
10.10.8
Single Channel versus Dual Channel Mode
Both single channel and dual channel modes are available to allow interfacing to either single or dual
channel panel interfaces. This LVDS port can operate in single channel or dual channel mode. Dual
channel mode uses twice the number of LVDS pairs and transfers the pixel data at twice the rate of the
single channel. In general, one channel will be used for even pixels and the other for odd pixel data.
The first pixel of the line is determined by the display enable going active and that pixel will be sent
out channel A. All horizontal timings for active, sync, and blank will be limited to be on two pixel
boundaries in the two channel modes.
10.10.9
LVDS Channel Skew
When in dual channel mode, the two channels must meet the panel requirements with respect to the
inter channel skew.
10.10.10 LVDS PLL
The Display PLL is used to synthesize the clocks that control transmission of the data across the LVDS
interface. The three operations that are controlled are the pixel rate, the load rate, and the IO shift rate.
These are synchronized to each other and have specific ratios based on single channel or dual channel
mode. If the pixel clock is considered the 1x rate, a 7x or 3.5x speed IO_shift clock needed for the
high speed serial outputs setting the data rate of the transmitters. The load clock will have either a 1x
or .5x ratio to the pixel clock.
10.10.11 SSC Support
The GMCH is designed to tolerate a 0.6%-2.5% down/center spread at a modulation rate range from
30-50 kHz triangle. By using an external SSC clock synthesizer to provide the 66 MHz reference clock
into the GMCH Pipe B PLL, spectrally spread 7X, 3.5X, and 1X LVDS clocking is output from
GMCH Pipe B PLL.
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10.10.12 Panel Power Sequencing
This section provides details for the power sequence timing relationship of the panel power, the
backlight enable and the LVDS data timing delivery. In order to meet the panel power timing
specification requirements, two signals, PANELVDDEN and PANELBKLTEN are provided to control
the timing sequencing function of the panel and the backlight power supplies.
10.10.12.1 Panel Power Sequence States
A defined power sequence is recommended when enabling the panel or disabling the panel. The set of
timing parameters can vary from panel to panel vendor, provided that they stay within a predefined
range of values. The panel VDD power, the backlight on/off state and the LVDS clock and data lines
are all managed by an internal power sequencer.
A requested power-up sequence is only allowed to begin after the power cycle delay time requirement
T4 is met.
Figure 10-5. Panel Power Sequencing
T4
T1+T2
TX
T5
T3
T4
Panel
On
Panel VDD
Enable
Panel
BackLight
Enable
Off
Clock/Data Lines
Valid
Off
Power On Sequence from off state and
Power Off Sequence after full On
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Table 10-14. Panel Power Sequencing Timing Parameters
Panel Power Sequence Timing Parameters
Min
Max
Units
Name
Spec Name
T1+T2
Vdd On to LVDS Active
From
.1 Vdd
LVDS
Active
0
LVDS
Active
Backlight
on
200
Backlight
Off
LVDS off
X
X
ms
LVDS Off
Start power
off
0
50
ms
Power Off
Power On
Sequence
Start
400
X
ms
Panel Vdd must be on for a minimum time
before the LVDS data stream is enabled.
T5
Backlight
LVDS data must be enabled for a
minimum time before the backlight is
turned on.
TX
Backlight State
Backlight must be disabled for a minimum
time before the LVDS data stream is
stopped.
T3
LVDS State
Data must be off for a minimum time
before the panel VDD is turned off.
T4
Power cycle Delay
When panel VDD is turned from On to
Off, a minimum wait must be satisfied
before the panel VDD is enabled again.
282
To
60
ms
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10.10.12.2 Back Light Inverter Control
The GMCH offers integrated PWM for TFT panel Backlight Inverter brightness control. Other
methods of control are specified in the Common Panel Interface Specification.
• PWM – based Backlight Brightness Control
• SMBus-based Backlight Brightness Control
• DBL (Display Brightness Link) –to- VDL (Video Data Link) Power Sequencing
10.10.13 SDVO Digital Display Port
The GMCH’s SDVO ports are each capable of driving a 200 MP pixel rate. Each port is capable of
driving a digital display up to 1600x1200 at 60 Hz. When in dual-channel mode, GMCH can drive a
flat panel up to 2048x1536 at 60 Hz or dCRT/HDTV up to 1920x1080 at 85 Hz.
The GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant external
device and connector, the GMCH has a high speed interface to a digital display (e.g., flat panel or
digital CRT).
Each port can transmit data according to one or more protocols. The digital ports are connected to an
external device that converts one protocol to another. Examples of this are TV encoders, external
DACs, LVDS transmitters, and TMDS transmitters. Each display port has control signals that may be
used to control, configure and/or determine the capabilities of an external device.
The GMCH has several options for driving digital displays. The GMCH contains two SDVO ports that
are multiplexed on the PCI Express based Graphics interface. When an external PCI Express Based
Graphics accelerator is not present, the GMCH can use the multiplexed SDVO ports to provide extra
digital display options.
he GMCH has the capability to support digital display devices through two SDVO ports muxed with
the PCI Express BASED GRAPHICS signals. When an external graphics accelerator is utilized, these
SDVO ports are not available.
The shared SDVO ports each support a pixel clock up to 200 MHz and can support a variety of
transmission devices. When using a dual-channel external transmitter, it will be possible to pair the two
SDVO ports in dual-channel mode to support a single digital display with higher resolutions and
refresh rates. In this mode, GMCH is capable of driving pixel clock up to 330 MHz.
SDVOCTRL_DATA is an open-drain signal that will act as a strap during reset to tell the GMCH
whether the interface is a PCI Express interface or an SDVO interface. When implementing SDVO
device, a pull-up is placed on this line to signal to the GMCH to run in SDVO mode and for proper
GMBus operation.
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10.10.13.1 TMDS Capabilities
The GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant external
device and connector, the GMCH has a high speed interface to a digital display (e.g., flat panel or
digital CRT). When combining the two multiplexed SDVO ports, the GMCH can drive a flat panel up
to 2048x1536 or a dCRT/HDTV up to 1920x1080. Flat Panel is a fixed resolution display. The GMCH
supports panel fitting in the transmitter, receiver or an external device, but has no native panel fitting
capabilities. The GMCH will however, provide unscaled mode where the display is centered on the
panel.
10.10.13.2 LVDS Capabilities
The GMCH may use the multiplexed SDVO ports to drive an LVDS transmitter. Flat Panel is a fixed
resolution display. The GMCH supports panel fitting in the transmitter, receiver or an external device,
but has no native panel fitting capabilities. The GMCH will however, provide unscaled mode where the
display is centered on the panel. Mobile Intel® 915 Express Chipset Family supports scaling in the
LVDS transmitter through the SDVO stall input pair.
10.10.13.3 TV-Out Capabilities (not supported by the Intel 915GME/Intel 910GMLE)
Although traditional TVs are not digital displays, the GMCH utilizes a digital display channel to
communicate with a TV-Out transmitter. For that reason, Mobile Intel® 915 Express Chipset Family
considers a TV-Output to be a digital display. GMCH will support NTSC/PAL/SECAM standard
definition formats. The GMCH will generate the proper timing for the external encoder. The external
encoder is responsible for generation of the proper format signal. Since the multiplexed SDVO
interface is
A NTSC/PAL/SECAM display on the TV-out port can be configured to be the boot device. It is
necessary to ensure that appropriate BIOS support is provided. If EasyLink is supported in the GMCH,
then this mechanism could be used to interrogate the display device.
The TV-out interface on GMCH is addressable as a master device. This allows an external TV encoder
device to drive a pixel clock signal on SDVO_TVClk[+/-] that the GMCH uses as a reference
frequency. The frequency of this clock is dependent on the output resolution required.
Flicker Filter and Overscan Compensation
The overscan compensation scaling and the flicker filter is done in the external TV encoder chip. Care
must be taken to allow for support of TV sets with high performance de-interlacers and progressive
scan displays connected to by way of a non-interlaced signal. Timing will be generated with pixel
granularity to allow more overscan ratios to be supported.
Direct YUV from Overlay
When source material is in the YUV format and is destined for a device that can take YUV format data
in, it is desired to send the data without converting it to RGB. This avoids the truncation errors
associated with multiple color conversion steps. The common situation will be that the overlay source
data is in the YUV format and will bypass the conversion to RBG as it is sent to the TV port directly.
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Sync Lock Support
Sync lock to the TV will be done using the external encoders PLL combined with the display phase
detector mechanism. The availability of this feature will be determined which external encoder is in
use.
Analog Content Protection
Analog content protection will be provided through the external encoder using Macrovision. DVD
software must verify the presence of a Macrovision TV encoder before playback continues. Simple
attempts to disable the Macrovision operation must be detected.
Connectors
Target TV connectors support includes the CVBS, S-Video, Component, and SCART connectors. The
external TV encoder in use will determine the method of support.
10.10.14 Control Bus
Communication to SDVO registers and monitor DDCs, are accomplished by using the
SDVOCTRL_DATA and SDVOCTRL_CLK signals through the SDVO device. These signals run up
to 1MHz and connect directly to the SDVO device. The SDVO device is then responsible for routing
the DDC and PROM data streams to the appropriate location. Consult SDVO device data sheets for
level shifting requirements of these signals.
10.10.15 Intel SDVO Modes
The port can be dynamically configured in several modes:
• Standard – Baseline SDVO functionality. Supports Pixel Rates between 25 and 200 MP/s. Utilizes
three data pairs to transfer RGB data.
• Extended – Adds Alpha support to data stream. Supports Pixel Rates between 25 and 200 MP/s.
Utilizes four data channels and is only supported on SDVO B. Leverages channel C (SDVO C)
Red pair as the Alpha pair for channel B (SDVO B).
• Dual Standard – Utilizes Standard data streams across both SDVO B and SDVO C. Both channels
can only run in Standard mode (3 data pairs) and each channel supports Pixel Rates between 25
and 200 MP/s.
⎯ Dual Independent Standard - In Dual Independent Standard mode, each SDVO channel will
see a different pixel stream. The data stream across SDVO B will not be the same as the data
stream across SDVO C.
⎯ Dual Simultaneous Standard - In Dual Simultaneous Standard mode, both SDVO channels
will see the same pixel stream. The data stream across SDVO B will be the same as the data
stream across SDVO C. The display timings will be identical, but the transfer timings may not
be - i.e. SDVO B Clocks and Data may not be perfectly aligned with SDVO C Clock and Data
as seen at the SDVO device(s). Since this utilizes just a single data stream, it utilizes a single
pixel pipeline within the GMCH.
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10.11
Multiple Display Configurations
Since the GMCH has several display ports available for its two pipes, it can support up to two different
images on different display devices. Timings and resolutions for these two images may be different.
Refer to the Mobile Intel 915 Express Chipset Family software PRD for more details on synchronous
display support
The GMCH is also incapable of operating in parallel with an external PCI Express graphics device. The
GMCH can, however, work in conjunction with a PCI graphics adapter.
10.12
Power Management
Power Management capabilities of the (G)MCH include the following:
10.12.1
Power Management Overview
• ACPI 1.0b and 2.0 compliant power management
• ACPI S0, S3 (Cold and Hot states), S4, S5 states
• CPU States: C0, C1, C2, C3/C4 states
• Internal Graphics Display Device states: D0, D1, D2, D3
• Graphics Display Adapter States: D0, D3
• PCI Express Link States: L0, L0s, L1, L2, L3
10.12.2
ACPI States Overview
GMCH supports the following ACPI states:
10.12.2.1
System
• G0/S0
Full On
• G1/S1
Not supported.
• G1/S2
Not supported.
• G1/S3- Cold Suspend to RAM (STR). Context saved to memory.
• G1/S3-Hot Suspend to RAM (STR). All voltage supplies left on except the CPU Core and FSB
VTT.
286
• G1/S4
Suspend to Disk (STD). All power lost (except wakeup on ICH)
• G2/S5
Soft off. All power lost (except wakeup on ICH). Total reboot.
• G3
Mechanical off. All power (AC and battery) removed from system.
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10.12.2.2
10.12.2.3
10.12.2.4
CPU
• C0
Full On
• C1
Auto Halt
• C2
Stop Grant.
• C3
Deep Sleep.
• C4
Deeper Sleep.
Internal Graphics Display Device Control
• D0
Display active
• D1
Low power state
• D2
Suspend display
• D3
Power off display
Internal Graphics Adapter
• D0
Full on, display active
• D3 Hot
Graphics clocks off
• D3 Cold Power off
10.12.2.5
PCI Express Link States
• L0
Full on – Active transfer state
• L0s
First Active Power Management low power state – Low exit latency
• L1
Lowest Active Power Management– Long exit latency
• L2
Lower link state with power applied – Longer exit latency
• L3
Lowest power state (power off) – Longest exit latency
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10.13
Thermal Management
System level thermal management requires comprehending thermal solutions for two domains of
operation:
1. Robust Thermal Solution Design: Proper system design should include implementation of a robust
thermal solution. The system’s thermal solution should be capable of dissipating the platform’s
TDP power while keeping all components (particularly GMCH, for the purposes of this
discussion) below the relevant Tdie_max under the intended usage conditions. Such conditions
include ambient air temperature and available airflow inside the notebook.
2. Thermal Failsafe Protection Assistance: As a backup to the implemented thermal solution, the
system design should provide a method to provide additional thermal protection for the
components of concern (particularly GMCH, for purposes of this discussion). The failsafe
assistance mechanism is to help manage components from being damaged by excessive thermal
stress under situations in which the implemented thermal solution is inadequate or has failed.
This section covers the thermal failsafe assistance mechanisms that are available for the GMCH and
recommends a usage model designed to accomplish the failsafe Protection Assistance.
The GMCH provides two internal thermal sensors, plus hooks for an external thermal sensor
mechanism. These can be used for detecting the component temperature and for triggering thermal
control within the GMCH. The GMCH has implemented several silicon level thermal management
features that can lower both GMCH and DDR power during periods of high activity. These features can
help control temperature of the GMCH and DDR and thus help prevent thermally induced component
failures. These features include:
• Memory throttling triggering by memory heating
• Memory throttling triggering by GMCH heating
• THRMTRIP# support
10.13.1
Internal Thermal Sensor
The GMCH incorporates two on-die thermal sensors which may be enabled separately. When
“tripped” at various values, the thermal sensors may be programmed to cause hardware throttling
and/or software interrupts. Hardware throttling includes main memory programmable throttling
thresholds. Sensor trip points may also be programmed to be generated various interrupts, including
SCI, SMI, SERR, or an internal graphics INTR.
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10.13.1.1
Trip Points
There are three programmable temperature trip points for each of the two internal thermal sensors:
Catastrophic, Hot, and Auxiliary:
The GMCH can be programmed to generate interrupts when any of these three trip points has been
crossed in the upwards direction. In addition, the GMCH can be programmed to enable throttling of the
DDR interface when the Catastrophic and/or Hot trip points are crossed in the upwards direction.
• Crossing the Catastrophic trip point may be programmed to generate an interrupt, enable hardware
throttling, and immediately shut down the system (via Halt, or via THRMTRIP# assertion).
• Crossing the Hot trip point may be programmed to generate an interrupt and/or enable hardware
throttling.
• Crossing the Auxiliary trip point can be programmed to generate an interrupt.
The current state of all trip points (HOT/CAT/AUX) may be read by software via the Thermal
Sensor Status Registers (TSSRs). It is recommended to use Halt or THRMTRIP# assertion on
Catastrophic trip. Using an interrupt to initiate shutdown at Catastrophic temperature may be
delayed since there is no guaranteed minimum interrupt service latency.
10.13.1.2
Thermometer
The Thermometer Reading Register (TRR) is primarily useful as an indicator of die temperature
trending. The TRR value tends to decrease as the die temperature increases. Intel currently has no
recommended end user usage model for this register. It is provided solely as an indication of
temperature trending, for customer system characterization. Absolute temperature accuracy will
vary from part to part. Refer to section 10.13.4 for more details on the sensor accuracy
(Taccuracy).
10.13.2
Sample Programming Model
Intel BIOS reference code implements a thermal failsafe mechanism based upon the assumptions stated
in the beginning of this chapter. The subsections below describe the algorithms implemented in the
reference code.
10.13.2.1
Setting the “Hot” Temperature Trip Point
• Program the Thermal Hot Temperature Setting Register (THTS) as recommended in the latest
Mobile Intel® 915 Express Chipset Family BIOS spec and memory reference code.
• Program the Thermal Sensor Control Register (TSC) as recommended in the latest Mobile Intel®
915 Express Chipset Family BIOS spec and memory reference code.
• To enable Error / SMI / SCI / INTR commands for CAT/HOT/AUX trip, set the appropriate bit in
TERRCMD / TSMICMD / TSCICMD / TINTRCMD registers. Refer to latest Mobile Intel® 915
Express Chipset Family EDS and BIOS spec update for programming details.
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10.13.3
Trip Point Temperature Targets
Table 10-15 below provides recommended trip points based upon the usage model of the thermal
sensors as a thermal protection failsafe mechanism. These settings assume that the system’s thermal
solution has been designed to provide adequate cooling for a TDP power condition and that the settings
for the silicon level thermal management are only intended to provide failsafe protection of the part
beyond the capabilities of the thermal solution.
Intel’s recommended trip point settings take into account the inaccuracy of the internal thermal sensors
as described in section 10.13.4 and are intended to cause the GMCH to initiate thermal failsafe control
mechanisms at the noted temperatures under the worst case accuracy, Taccuracy. Therefore, in parts
which actually exhibit the worst case inaccuracy, failsafe control mechanisms may actually be initiated
at a temperature which is Taccuracy below the nominal trip point.
Table 10-15: Recommended Programming for Available Trip Points
Zone
Nominal Trip Points
Catastrophic
TCatastrophic = Tdie,max + 41°C - Taccuracy =
133°C
Hot
THot = Tdie,max + 3°C + Taccuracy = 121°C
OEM decision, based on OEM criteria (for
example: Taux = Temp at which an auxiliary fan
should be turned on)
Aux
Recommended action
Halt operation
Initiate throttling
OEM decision, based on OEM criteria (for
example: turn on an auxiliary fan)
Crossing a trip point in either direction may generate several types of interrupts. Each trip point has a
register which can be programmed to select the type of interrupt to be generated.
Crossing a trip point may also initiate hardware-based throttling without software intervention.
10.13.4
Thermal Sensor Accuracy
Thermal sensor accuracy, Taccuracy, for GMCH is ± 13 °C for temperature range 80 °C to 133 °C.
This value is based on product characterization and is not guaranteed by manufacturing test.
Software has the ability to program the Tcat, Thot, and Taux trip points, but these trip points should be
selected with consideration for the thermal sensor accuracy and the quality of the platform thermal
solution. Overly conservative (unnecessarily low) temperature settings may unnecessarily degrade
performance due to frequent throttling, while overly aggressive (dangerously high) temperature settings
may fail to protect the part against permanent thermal damage.
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10.13.5
Thermal Throttling Options
The GMCH has two independent mechanisms that cause system memory bandwidth throttling.
The first is GMCH thermal management to ensure that the chipset is operating within thermal limits.
The mechanism can be initiated by a thermal sensor (internal or external) trip or by GMCH usage
exceeding a programmed threshold via a weighted input averaging filter.
The second is Dram Thermal management to ensure that the dram chips are operating within thermal
limits. Throttling can be initiated by dram activity measurement exceeding a programmed threshold.
Another possible usage model targets skin temperature control near memory. Throttling can be
initiated by an external thermal sensor trip or by dram activity measurement exceeding a programmed
threshold.
10.13.6
THRMTRIP Operation
Assertion of the GMCH’s THRMTRIP# (Thermal Trip) indicates the GMCH junction temperature
has reached a level beyond which damage may occur. Upon assertion of THRMTRIP#, the GMCH will
shut off its internal clocks (thus halting program execution) in an attempt to reduce the GMCH core
junction temperature. Once activated, THRMTRIP# remains latched until RSTIN# is asserted. The
GMCH THRMTRIP# and CPU THRMMTRIP# signals connects to ICH6-M.
10.14
Clocking
10.14.1
Overview
The GMCH has a total of five PLLs providing many times that many internal clocks. The PLLs are:
• Host PLL – Generates the main core clocks in the host clock domain. Can also be used to generate
memory and internal graphics core clocks. Uses the Host clock (HCLKN/HCLKP) as a reference.
• Memory PLL – Can be used to generate memory and internal graphics core clocks, when not
generated by the Host PLL. This PLL is not needed in all configurations, but exists to provide
more flexible frequency combinations without an unreasonable VCO frequency. Uses the Host
clock (HCLKN/HCLKP) as a reference.
• PCI Express PLL – Generates all PCI Express related clocks, including the DMI that connects to
the ICH6-M. This PLL uses the 100 MHz (GCLKN/GCLKP) as a reference.
• Display PLL A – Generates the internal clocks for Display A. Uses DREF_CLKIN as a reference.
• Display PLL B – Generates the internal clocks for Display A or Display B. Also may optionally
use DREF_SSCCLKIN as a reference for SSC support for LVDS display on pipe B.
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10.14.2
GMCH Reference Clocks
Reference Input clocks
Input Frequency
Associated PLL
HCLKP / HCLKN
100 MHz / 133MHz
Host / Memory / Graphics Core
DREF_CLKN / DREF_CLKP
96 MHz / 100 MHz
Display PLL A
DREF_SSCCLKN / DREF_SSCCLKP
96 MHz / 100 MHz
Display PLL B
100 MHz
PCI Express / DMI PLL
GCLKP / GCLKN
10.14.3
Host/Memory/Graphics Core Clock Frequency Support
10.14.3.1
Intel 915GM Host/Memory/Graphics Clock Support
Table 10-16. Intel 915GM Graphics Clock Frequency Support
10.14.3.2
Host
Memory
Gfx Core Voltage
2D Display core
3D Render core
400 MHz
DDR 333
1.05 V
133, 200
133, 166, 200
533 MHz
DDR 333
1.05 V
133, 190
133, 166, 190
400 MHz
DDR2 400
1.05 V
133, 200
133, 160, 200
533 MHz
DDR2 400
1.05 V
133, 200
133, 160, 200
533 MHz
DDR2 533
1.05 V
133, 200
133, 160, 200
400 MHz
DDR2 400
1.5 V
133, 200,333
133, 160, 200, 333
533 MHz
DDR2 400
1.5 V
133, 200, 333
133, 160, 200, 333
533 MHz
DDR2 533
1.5 V
133, 200, 333
133, 160, 200, 333
Intel 915GMS Host/Memory/Graphics Clock Support
Table 10-17. Intel 915GMS Graphics Clock Frequency Support
10.14.3.3
Host
Memory
Gfx Core Voltage
2D Display core
3D Render core
400 MHz
DDR2 400
1.05 V
133, 200
133, 160
Intel 910GML Host/Memory/Graphics Clock Support
Table 10-18. Intel 910GML Graphics Clock Frequency Support
Host
Memory
Gfx Core Voltage
2D Display Core
3D Render Core
400 MHz
DDR 333
1.05 V
133, 200
133, 166
400 MHz
DDR2 400
1.05 V
133, 200
133, 160
§
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11
Electrical Characteristics
This chapter contains the absolute maximum electrical ratings, power dissipation values, and DC
characteristics.
11.1
Absolute Maximum Ratings
Table 11-1 specifies absolute maximum and minimum ratings. Within functional operating parameters,
functionality and long-term reliability can be expected.
At conditions outside functional operating parameters, but within absolute maximum and minimum
ratings, neither functionality nor long-term reliability can be expected. If a device is returned to
conditions within functional operating parameters after having been subjected to conditions outside
these parameters, but within the absolute maximum and minimum ratings, the device may be
functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional
operating parameters.
At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term
reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time
then, when returned to conditions within the functional operating parameters, it will either not function
or its reliability will be severely degraded.
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Table 11-1. Absolute Maximum Ratings
Symbol
Parameter
Tdie
Die Temperature under Bias
Tstorage
Storage Temperature
Min
Max
Unit
Notes
0
105
°C
1
-55
150
°C
2
GMCH Core
VCC
1.05 V Core Supply Voltage with respect to VSS
-0.3
1.65
V
VCC
1.5 V Core Supply Voltage with respect to VSS
-0.3
1.65
V
-0.3
1.65
V
Host Interface
VTT (FSB Vccp)
1.05 V AGTL+ buffer DC Input Voltage with
respect to VSS
DDR Interface (333 MTs)
VCCSM
2.5 V DDR System Memory Data Buffers Supply
Voltage with respect to VSS
-0.3
4.0
V
VCCA_SM
1.5 V VCCASM is the Analog power supply for
SM data buffers used for DLL & other logic
-0.3
1.65
V
DDR2 Interface (400 MTs/533 MTs)
VCCSM
1.8 V DDR2 Supply Voltage with Respect to Vss.
-0.3
4.0
V
VCCA_SM
1.5 V VCCASM is the Analog power supply for
SM data buffers used for DLL & other logic
-0.3
1.65
V
DMI /PCI Express* Graphics/SDVO Interface
VCC3G
1.5 V PCI-Express Supply Voltage with respect to
VSS
-0.3
1.65
V
VCCA_3GBG
2.5 V Analog Supply Voltage with respect to
VSSA3GBG
-0.3
2.65
V
CRT DAC Interface (8 bit DAC)
VCCA_CRTDAC
2.5 V DAC Supply Voltage with respect to
VSSA_CRTDAC
-0.3
2.65
V
VCC_SYNC
2.5 V CRT Sync Supply Voltage
-0.3
2.65
V
-0.3
2.65
V
HV CMOS Interface
VCCHV
2.5 V Supply Voltage with respect to VSS
TV OUT Interface (10 bit DAC)
VCCD_TVDAC
1.5 V TV Supply
-0.3
1.65
V
VCCA_TVDACA
3.3 V TV Analog Supply
-0.3
3.65
V
VCCA_TVBG
3.3 V TV Analog Supply
-0.3
3.65
V
VCCDQ_TVDA
C
1.5 V Quiet Supply
-0.3
1.65
V
1.5 V LVDS Digital Power Supply
-0.3
1.65
V
2.5 V LVDS Data/Clock Transmitter Supply
-0.3
2.65
V
VCCA_TVDACB
VCCA_TVDACC
LVDS Interface
VCCD_LVDS
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Symbol
Parameter
VCCTX_LVDS
Voltage with respect to VSS
VCCA_LVDS
2.5 V LVDS Analog Supply voltage with respect
to VSS
Min
Max
Unit
-0.3
2.65
V
-0.3
1.65
V
Notes
PLL Analog Power Supplies
VCCA_HPLL,
1.5 V Power Supply for various PLL
VCCA_MPLL,
VCCD_HMPLL,
VCCA_3GPLL,
VCCA_DPLLA,
VCCA_DPLLB
NOTES:
1. Functionality is not guaranteed for parts that exceed Tdie temperature above 105 ºC. Tdie is measured at
top center of the package. Full performance may be affected if the on-die thermal sensor is enabled.
2. Storage temperature is applicable to storage conditions only. In this scenario, the silicon must not receive
a clock, and no pins can be connected to a voltage bias. Storage within these limits will not affect the
long-term reliability of the device. This rating applies to the silicon and does not include any tray or
packaging. Possible damage to the GMCH may occur if the GMCH temperature exceeds 150 ºC. Intel
does not guarantee functionality for parts that have exceeded temperatures above 150 ºC due to spec
violation.
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11.2
Power Characteristics
Table 11-2. Non-Memory Power Characteristics
Symbol
Parameter
Signal Names
Min
Typ
7
Max
TDP
W
®
Intel 915GM/915GME/910GML/910GMLE
Notes
1, 2
6.0
®
5.5
®
4.8
Intel 915PM
Intel 915GMS
296
Unit
IVTT
VTT Supply Current (1.05v)
VTT
640
mA
IVCC1_05
1.05 V Core Supply Current
(External GFX)
VCC
2600
mA
IVCC1_05
1.05 V Core Supply Current
(Integrated GFX)
VCC
3700
mA
IVCC1_5
1.5 V Core Supply Current
(External GFX)
VCC
4000
mA
IVCC1_5
1.5 V Core Supply Current
(Integrated GFX)
VCC
6750
mA
IVCC3G
1.5 V PCI Express Supply
Current
VCC3G,
VCCA_3GPLL
1500
mA
IVCCA_3GBG
2.5 V PCI Express Analog
Supply Current
VCCA_3GBG
0.150
mA
IVCCD_LVDS
1.5 V LVDS (Digital) Supply
Current
VCCD_LVDS
60
mA
IVCCA_LVDS
2.5 V LVDS (Analog)
Supply Current
VCCA_LVDS
10
mA
IVCCTX_LVDS
2.5 V LVDS (I/O) Supply
Current
VCCTX_LVDS
60
mA
IVCCCRT
2.5 V CRT DAC Supply
Current (IvccADAC)
2.5V CRT Sync Supply
Current (Ivccsync)
VCCA_CRTDAC
68
mA
VCC_SYNC
2
mA
IVCCHV
2.5 V HV CMOS Supply
Current
VCCHV
2
mA
IVCCD_TVDAC
1.5 V TV Supply Current
(Ivcc_TVDAC)
1.5 V TV Quiet Supply
Current (IVccQ_TVDAC)
VCCD_TVDAC
VCCQ_TVDAC
24
mA
6
IVCCTVDAC
3.3 V TV Analog Supply
Current (IvccATVDAC)
3.3 V TV Bandgap Supply
Current (IvccATVBG)
VCCA_TVBG
VCCA_TVDACA
VCCA_TVDACB
VCCA_TVDACC
120
mA
6
IVCCAHPLL
Host PLL Supply Current
VCCA_HPLL
45
mA
4,6
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Symbol
IVCCADPLLA,B,
Parameter
Signal Names
Display PLLA Supply
Current
Display PLLB Supply
Current
VCCA_DPLLA
IVCCAMPLL
Memory PLL Supply
Current
IVCCDHMPLL
HMPLL Supply Current for
Digital Interface
Min
7
Typ
Max
Unit
40
mA
40
mA
VCCA_MPLL
45
mA
VCCD_HMPLL
150
mA
Notes
VCCA_DPLLB
NOTES:
1. This spec is the Thermal Design Power and is the estimated maximum possible expected power
generated in a component by a realistic application. It is based on extrapolations in both hardware and
software technology over the life of the component. It does not represent the expected power generated
by a power virus. Studies by Intel indicate that no application will cause thermally significant power
dissipation exceeding this specification, although it is possible to concoct higher power synthetic
workloads that write but never read. Under realistic read/write conditions, this higher power workload can
only be transient and is accounted in the Icc (max) spec. Tdie is measured at the top center of the
package.
2. Please contact your Intel Field Representative for latest TDP data.
3. Estimate is only for max current coming through the chipset’s supply balls.
4. Rail includes PLL current.
5. Iccmax is determined on a per-interface basis, and all can not happen simultaneously.
Table 11-3. DDR (333 MTs) Power Characteristics
Symbol
Max
Unit
1 Channel
1050
mA
2 Channel
2200
mA
DDR System Memory Interface
(2.5 V) Standby Supply Current
N/A
mA
DDR System Memory Interface
Reference Voltage (1.25 V) Supply
Current
10
µA/pin
ISUS_SMVREF
DDR System Memory Interface
Reference Voltage (1.25 V) Standby
Supply Current
10
µA/pin
ITTRC
DDR System Memory Interface
Resistor Compensation Voltage
(2.5 V) Supply Current
42
mA
DDR System Memory Interface
Resistor Compensation Voltage
(2.5 V) Standby Supply Current
~0
µA
(DDR)
IVCCASM
Memory DLL
mA
IVCCSM
(DDR)
ISUS_VCCSM
(DDR)
ISMVREF
(DDR)
(DDR)
ISUS_TTRC
ISUS_VCCASM
Parameter
DDR System Memory Interface
(2.5 V) Supply Current
Memory DLL (Standby)
Min
Type
1 Channel
125
2 Channel
250
1 Channel
0
2 Channel
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Table 11-4. DDR 2 (400 MTs/533 MTs) Power Characteristics
Symbol
IVCCSM
(DDR2)
IVCCSM
(DDR2)
ISUS_VCCSM
(DDR2)
ISMVREF
Parameter
Min
Type
Max
Unit
DDR2 System Memory Interface
(1.8 V, 400 MTs) Supply Current
1 Channel
950
mA
2 Channel
1900
mA
DDR2 System Memory Interface
(1.8 V, 533 MTs) Supply Current
1 Channel
1200
mA
2 Channel
2400
mA
1 Channel
~5
mA
2 Channel
~5
DDR2 System Memory Interface
(1.8 V) Standby Supply Current
DDR2 System Memory Interface
Reference Voltage (0.90 V) Supply
Current
10
µA/pin
DDR2 System Memory Interface
Reference Voltage (0.90 V) Standby
Supply Current
10
µA/pin
DDR2 System Memory Interface
Resister Compensation Voltage
(1.8 V) Supply Current
32
mA
DDR2 System Memory Interface
Resister Compensation Voltage
(1.8 V) Standby Supply Current
~0
µA
(DDR2)
IVCCASM
Memory DLL (400 MTs)
mA
(DDR2)
ISUS_SMVREF
(DDR2)
ITTRC
(DDR2)
ISUS_TTRC
IVCCASM
ISUS_VCCASM
Memory DLL (533 MTs)
Memory DLL (Standby)
1 Channel
215
2 Channel
290
1 Channel
280
2 Channel
390
1 Channel
0
2 Channel
0
Notes
Number
is same
for 400
MTs and
533MTs
mA
mA
NOTE: Standby or Sus in Table 3 and Table 4 refers to system memory in Self Refresh during S3 Cold (STR).
298
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Electrical Characteristics
R
11.3
Signal Groups
The signal description includes the type of buffer used for the particular signal:
AGTL+
Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for complete
details. (VCCP)
Analog
Analog signal interface
CMOS
CMOS buffers. 1.5 V tolerant
HVCMOS
CMOS buffers. 2.5 V tolerant
COD
CMOS Open Drain buffers. 2.5 V tolerant
DDR
DDR system memory (2.5 V CMOS buffers)
DDR2
DDR2 system memory (1.8 V CMOS buffers)
PCI Express* GFX/Serial DVO
PCI Express interface signals. These signals are compatible
with PCI Express Base Specification 1.0a Electrical Signal Specifications. The buffers are not 3.3 V
tolerant. Differential voltage spec = (|D+ - D-|) * 2 = 1.2 V max. Single-ended maximum = 1.5V.
Single-ended minimum = 0V. Please refer to the PCIE specification.
SSTL-2
2.5 V tolerant Stub Series Termination Logic
SSTL-1.8
1.8 V tolerant Stub Series Termination Logic
LVDS
Low Voltage Differential Signal interface
Ref
Voltage reference signal
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
299
Electrical Characteristics
R
Table 11-5. Signal Groups
Signal
Group
Signal Type
Signals
Notes
Host Interface Signal Groups
(a)
AGTL+
Input/Output
(b)
AGTL+
Common Clock
Outputs
(c)
(d)
CMOS Output
AGTL+
HADS#, HBNR#, HBREQ0#,HDBSY#, HDRDY#,
HDINV[3:0]#, HA[31:3]#, HADSTB[1:0]#,
HD[63:0]#,HDSTBP[3:0]#, HDSTBN[3:0]#, HHIT#,
HHITM#, HREQ[4:0]#
HBPRI#, HCPURST#, HDEFER#, HTRDY#, HRS[2:0]#,
HDPWR#
HCPUSLP#, THRMTRIP#
CMOS Type
Buffer with
Vtt
HLOCK#
Asynchronous Input
(e)
Analog Host I/F Ref
& Comp. Signals
HVREF, HXSWING, HYSWING, HXRCOMP, HXSCOMP,
HYRCOMP, HYSCOMP
Serial DVO or PCI-Express Graphics Interface Signal Groups
(f)
PCI-E GFX/SDVO
Input
PCI-E GFX Interface: EXP_RXN[15:0], EXP_RXP[15:0],
SDVO Interface: SDVO_TVCLKIN#, SDVO_TVCLKIN,
SDVOB_INT#, SDVOB_INT, SDVOC_INT#, SDVOC_INT,
SDVO_FLDSTALL#, SDVO_FLDSTALL
Please see
Signal
Description
chapter for
SDVO & PCI
Express
GFX Pin
Mapping
(g)
PCI-E GFX/SDVO
Output
PCI-E GFX Interface: EXP_TXN[15:0], EXP_TXP[15:0]
SDVO Interface: SDVOB_RED#, SDVOB_RED,
SDVOB_GREEN#, SDVOB_GREEN, SDVOB_BLUE#,
SDVOB_BLUE, SDVOB_CLKN, SDVOB_CLKP,
SDVOC_RED#/SDVOB_ALPHA#,
SDVOC_RED/SDVOB_ALPHA, SDVOC_GREEN#,
SDVOC_GREEN, SDVOC_BLUE#, SDVOC_BLUE,
SDVOC_CLKN, SDVOC_CLKP
Please see
Signal
Description
chapter for
SDVO & PCI
Express
GFX Pins
Mapping
(h)
Analog
PCI-E GFX/SDVO I/F
Compensation
Signals
EXP_ICOMP0
EXP_COMPI
DDR Interface Signal Groups
(i)
SSTL- 2
DDR CMOS I/O
(j)
SSTL – 2
DDR CMOS Output
DQ (SA_DQ[63:0], SB_DQ[63:0])
DQS (SA_DQS[7:0], SB_DQS[7:0])
DM (SA_DM[7:0], SB_DM[7:0])
MA (SA_MA[13:0], SB_MA[13:0])
BS (SA_BS[1:0], SB_BS[1:0])
RAS# (SA_RAS#, SB_RAS#)
CAS# (SA_CAS#, SB_CAS#)
WE# (SA_WE#, SB_WE#)
SM_CKE[3:0], SM_CS[3:0]#,
SM_CK[4:3,1:0], SM_CK[4:3,1:0]#
(k)
300
DDR Reference
Voltage
SMVREF(1:0)
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Electrical Characteristics
R
Signal
Group
Signal Type
Signals
Notes
DDR2 Interface Signal Groups
(l)
SSTL – 1.8
DDR2 CMOS I/O
DQ (SA_DQ[63:0], SB_DQ[63:0])
DQS (SA_DQS[7:0], SB_DQS[7:0])
DQS# (SA_DQS[7:0]#, SB_DQS[7:0]#)
(m)
SSTL – 1.8
DDR2 CMOS Output
DM (SA_DM[7:0], SB_DM[7:0])
MA (SA_MA[13:0], SB_MA[13:0])
BS (SA_BS[2:0], SB_BS[2:0])
RAS# (SA_RAS#, SB_RAS#)
CAS# (SA_CAS#, SB_CAS#)
WE# (SA_WE#, SB_WE#),
SM_ODT[3:0],
SM_CKE[3:0], SM_CS[3:0]#,
SM_CK[4:3,1:0], SM_CK[4:3,1:0]#
(n)
DDR2 Reference
Voltage
SMVREF(1:0)
LVDS Signal Groups
(o)
LVDS
LVDS Input/Output
Analog
LADATAP[2:0], LADATAN[2:0], LACLKP, LACLKN,
LBDATAP[2:0], LBDATAN[2:0], LBCLKP, LBCLKN
LIBG
Current
Mode
Reference
pin. DC
Spec. not
required
RED, RED#, GREEN, GREEN#, BLUE, BLUE#
Please refer
to Section
11.4.2
REFSET
Current
Mode
Reference
pin. DC
Spec. not
required
HSYNC, VSYNC
Please refer
to the VESA
specification
for details
LVDS Miscellaneous
CRT DAC Signal Groups
Analog Current
Outputs
Analog/Ref
DAC Miscellaneous
HVCMOS Type
TV DAC Signal Groups (these signals are not supported on the Intel 915GME / Intel 910GMLE chipsets)
Analog Current
Outputs
Analog/Ref
DAC Miscellaneous
TVDAC_A, TVDAC_B, TVDAC_C, TV_IRTNA,
TV_IRTNB, TV_IRTNC
TV_REFSET
Current
Mode
Reference
pin. DC
Spec. not
required
Clocks, Reset, and Miscellaneous Signal Groups
(p)
(q)
HVCMOS Input
Low Voltage Diff.
EXT_TS[1:0]#, CFG[20:18], CFG[2:0]
HCLKP(BCLK/BCLK0), HCLKN(BCLK#/BCLK1),
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
301
Electrical Characteristics
R
Signal
Group
Signal Type
Clock Input
Signals
Notes
DREF_CLKP, DREF_CLKN, DREF_SSCLKP,
DREF_SSCLKN, GCLKP, GCLKN
(r)
HVCMOS Output
(s)
HVCMOS I/O
BM_BUSY#, LVDD_EN, LBKLT_EN, LBKLT_CTRL
(t)
AGTL+ Input/Output
CFG[17:3], RSVD
(u)
MISC
RSTIN#, PWROK
DDCCLK, DDCDATA, LDDC_CLK, LDDC_DATA,
SDVOCTRL_CLK, SDVOCTRL_DATA, LCTLB_DATA,
LCTLA_CLK
I/O Buffer Supply Voltages
302
(v)
AGTL+ Termination
Voltage
VTT (Vccp)
(w)
SDVO, DMI, PCI
Express GFX
Voltages
(x)
2.5 V DDR Supply
Voltage
VCCSM (DDR)
(y)
1.8V DDR2 Supply
Voltage
VCCSM (DDR2)
(z)
1.5 V DDR/DDR2
Analog Supply
VCCA_SM
VCC3G, VCCA_3GBG
(aa)
GMCH Core
(ab)
HV Supply Voltage
VCC
(ac)
TV DAC Supply
Voltage
(ad)
TV DAC Band Gap
and Channel Supply
(ae)
CRT DAC Supply
Voltage
(af)
PLL Supply Voltages
(ag)
1.5 V LVDS Digital
Supply
VCCD_LVDS
(ah)
2.5 V LVDS
Data/CLK Transmitter
Supply
VCCTX_LVDS
(ai)
2.5 V LVDS Analog
Supply
VCCHV
VCCD_TVDAC, VCCDQ_TVDAC
VCCA_TVBG, VCCA_TVDACA,VCCA_TVDACB,
VCCA_TVDACC
VCCA_CRTDAC, VCC_SYNC
VCCA_HPLL, VCCA_MPLL, VCCD_HMPLL
VCCA_3GPLL, VCCA_DPLLA, VCCA_DPLLB
VCCA_LVDS
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Electrical Characteristics
R
11.4
DC Characteristics
11.4.1
General DC Characteristics
Table 11-6. DC Characteristics
Symbol
Signal
Group
Parameter
Min
Nom
Max
Unit
Notes
I/O Buffer Supply Voltage (AC Noise not included)
VCC
(aa)
1.05 V GMCH Core Supply
Voltage
1.0
1.05
1.1
V
VCC
(aa)
1.5 V GMCH Core Supply
Voltage
1.425
1.5
1.575
V
VTT
(v)
1.05 V Host AGTL+
Termination Voltage
0.9475
1.05
1.1025
V
VCCSM (DDR)
(x)
DDR I/O Supply Voltage
2.3
2.5
2.7
V
VCCSM (DDR2)
(y)
DDR2 I/O Supply Voltage
1.7
1.8
1.9
V
VCCASM (DDR)
(z)
DDR I/O Analog Supply
1.425
1.5
1.575
V
VCCASM (DDR2)
(z)
DDR2 I/O Analog Supply
1.425
1.5
1.575
V
VCC3G
(w)
DMI, SDVO, PCI Express GFX 1.425
Supply Voltage
1.5
1.575
V
VCCA_3GBG
(w)
DMI, SDVO, PCI Express GFX 2.32
Analog Voltage
2.5
2.625
V
VCCHV
(ab)
HV CMOS Supply Voltage
2.375
2.5
2.625
V
VCCD_TVDAC
(ac)
TV DAC Supply Voltage
1.425
1.5
1.575
V
VCCDQ_TVDAC
(ac)
TV DAC Quiet Supply Voltage
1.425
1.5
1.575
V
VCCA_TVDACA
VCCA_TVDACB
VCCA_TVDACC
VCCA_TVBG
(ad)
TV DAC Analog & Band Gap
Supply Voltage
3.135
3.3
3.465
V
VCCA_CRTDAC
(ae)
CRT DAC Supply Voltage
2.32
2.5
2.625
V
VCC_SYNC
(ae)
CRT DAC SYNC Supply
Voltage
2.32
2.5
2.625
V
VCCA_HPLL,
VCCA_MPLL,
VCCD_HMPLL
VCCA_3GPLL,
VCCA_DPLLA,
VCCA_DPLLB
(af)
Various PLLS Analog Supply
Voltages
1.425
1.5
1.575
V
VCCD_LVDS
(ag)
Digital LVDS Supply Voltage
1.425
1.5
1.575
V
VCCTX_LVDS
(ah)
Data/Clock Transmitter LVDS
Supply Voltage
2.375
2.5
2.625
V
2.375
2.5
2.625
V
VCCA_LVDS
(ai)
Analog LVDS Supply Voltage
1 -Ripple
Noise
spec.
Reference Voltages
HVREF
(e)
Host Address and Data
Reference Voltage
2/3 x VTT 2/3 x VTT 2/3 x VTT V
– 2%
+ 2%
HXSWING
HYSWING
(e)
Host Compensation Reference 0.3125 x 0.3125x
Voltage
VTT – 2% VTT
0.3125x
V
VTT + 2%
SMVREF (DDR)
(k)
DDR Reference Voltage
0.5VCCSM V
+ 0.05
0.5VCCS
M - 0.05
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
0.50 x
VCCSM
303
Electrical Characteristics
R
Symbol
Signal
Group
SMVREF (DDR2)
(n)
Parameter
DDR2 Reference Voltage
Min
Nom
Max
Unit
0.49 x
VCCSM
0.50 x
VCCSM
0.51 x
VCCSM
0
(2/3 x VTT) V
– 0.1
Notes
V
Host Interface
VIL_H
(a,d,t)
Host AGTL+ Input Low Voltage -0.10
VIH_H
(a,d,t)
Host AGTL+ Input High Voltage (2/3 x
VTT (1.05) VTT + 0.1 V
VTT) + 0.1
VOL_H
(a,b,t)
Host AGTL+ Output Low
Voltage
VOH_H
(a,b,t)
Host AGTL+ Output High
Voltage
IOL_H
(a,b,t)
Host AGTL+ Output Low
Current
ILEAK_H
(a,d,t)
Host AGTL+ Input Leakage
Current
20
uA
CPAD
(a,d,t)
Host AGTL+ Input Capacitance 2
3.5
pF
VOL_H
(c)
CMOS Output Low Voltage
0.1 VTT
V
IOL = 1
mA
VOH_H
(c)
CMOS Output High Voltage
VTT
V
IOH = 1
mA
VTT-0.1
(0.3125 x
VTT) + 0.1
V
VTT
V
VTTmax /
mA
(10.3125)Rtt
Rttmin=50
ohm
min
0.9VTT
VOL<Vpa
d<
Vtt
DDR Interface
VIL(DC) (DDR)
(i)
DDR Input Low Voltage
VIH(DC) (DDR)
(i)
DDR Input High Voltage
VIL(AC) (DDR)
(i)
DDR Input Low Voltage
VIH(AC) (DDR)
(i)
DDR Input High Voltage
VOL (DDR)
(i, j)
DDR Output Low Voltage
VOH (DDR)
(i, j)
DDR Output High Voltage
ILeak (DDR)
(i)
Input Leakage Current
CI/O (DDR)
(i, j)
DDR Input/Output Pin
Capacitance
VIL(DC) (DDR2)
(l)
DDR2 Input Low Voltage
VIH(DC) (DDR2)
(l)
DDR2 Input High Voltage
VIL(AC) (DDR2)
(l)
DDR2 Input Low Voltage
VIH(AC) (DDR2)
(l)
DDR2 Input High Voltage
VOL (DDR2)
(l, m)
DDR2 Output Low Voltage
VOH (DDR2)
(l, m)
DDR2 Output High Voltage
ILeak (DDR2)
(l)
SMVREF – V
0.15
SMVREF
+ 0.15
V
SMVREF – V
0.31
SMVREF
+ 0.31
V
0.4
2.1
3.0
V
2
V
2
±10
µA
6.0
pF
DDR2 Interface
304
Input Leakage Current
SMVREF – V
0.125
SMVREF
+ 0.125
V
SMVREF – V
0.250
SMVREF
+ 0.250
V
0.3
1.5
±10
V
2
V
2
uA
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Electrical Characteristics
R
Symbol
CI/O (DDR2)
Signal
Group
(l, m)
Parameter
DDR2 Input/Output Pin
Capacitance
Min
Nom
3.0
Max
Unit
Notes
6.0
pF
0.6
V
3, 4
20
mV
3
120
Ω
1.5 V PCI Express Interface 1.0a (includes PCI Express GFX and SDVO)
VTX-DIFF P-P
(f, g)
Differential Peak to Peak
Output Voltage
0.400
VTX_CM-ACp
(f, g)
AC Peak Common Mode
Output Voltage
ZTX-DIFF-DC
(f, g)
DC Differential TX Impedance
VRX-DIFF p-p
(f, g)
Differential Input Peak to Peak 0.175
Voltage
1.2
V
VRX_CM-ACp
(f, g)
AC peak Common Mode Input
Voltage
150
mV
0.8
V
±10
μA
6.0
pF
80
100
3, 4
Clocks, Reset, and Miscellaneous Signals
VIL
(p)
Input Low Voltage
VIH
(p)
Input High Voltage
ILEAK
(p)
Input Leakage Current
CIN
(p)
Input Capacitance
VIL
(q)
Input Low Voltage
VIH
(q)
Input High Voltage
0.660
VCROSS
(q)
Crossing Voltage
0.45x(VIH - 0.5x(VIH VIL)
VIL)
0.55x(VIH - V
VIL)
CIN
(q)
Input Capacitance
0.5
1.5
pF
VOL
(r, s)
Output Low Voltage (CMOS
Outputs)
0.4
V
VOH
(r, s)
Output High Voltage (CMOS
Outputs)
IOL
(r, s)
Output Low Current (CMOS
Outputs)
IOH
(r, s)
Output High Current (CMOS
Outputs)
VIL
(s)
Input Low Voltage (DC)
VIH
(s)
Input High Voltage (DC)
ILEAK
(s)
Crossing Voltage
CIN
(s)
Input Capacitance
VIL
(u)
Input Low Voltage
VIH
(u)
Input High Voltage
ILEAK
(u)
Input Leakage Current
CIN
(u)
Input Capacitance
2.0
V
3.0
0
0.710
V
0.850
2.1
V
V
1
-1
mA
@VOL_HI
max
mA
@VOH_HI
min
(Vcchv/2) - V
0.2
(vcchv/2)
+ 0.2
V
3.0
±10
uA
6.0
pF
0.8
2.0
V
V
4.690
±100
μA
5.370
pF
0<Vin<V
CC3_3
LVDS Interface: Functional Operating Range (VCC=2.5 V±5%)
VOD
(o)
Differential Output Voltage
250
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
350
450
mV
305
Electrical Characteristics
R
Symbol
Signal
Group
Parameter
ΔVOD
(o)
Change in VOD between
Complementary Output States
VOS
(o)
Offset Voltage
ΔVOS
(o)
Change in VOS between
Complementary Output States
IOs
(o)
Output Short Circuit Current
IOZ
(o)
Min
1.125
Output TRI-STATE Current
Nom
Max
Unit
50
mV
1.375
V
50
mV
-3.5
-10
mA
±1
±10
μA
1.25
Notes
NOTES:
1. Following are the noise rejection specifications for PLL supplies.
VCCA_HPLL
34 dB(A) attenuation of power supply noise in 1 MHz(f1) to 66 MHz(f2) range, <0.2 dB gain in
pass band and peak to peak noise should be limited to < 120 mV
VCCA_MPLL
34 dB(A) attenuation of power supply noise in 1 MHz(f1) to 66MHz(f2) range, <0.2 dB gain in
pass band and peak to peak noise should be limited to < 120 mV
VCCD_HMPLL
peak to peak noise should be limited to < 120 mV
VCCA_3GPLL
< 0 dB(A) in 0 to 1MHz, 20 dB(A) attenuation of power supply noise in 1 MHz(f1) to 1.25 GHz(f2)
range, <0.2 dB gain in pass band and peak to peak noise should be limited to < 40 mV
VCCA_DPLLA
20 dB(A) attenuation of power supply noise in 10 kHz(f1) to 2.5 MHz(f2) range, <0.2 dB gain in
pass band and peak to peak noise should be limited to < 100 mV
VCCA_DPLLB
20 dB(A) attenuation of power supply noise in 10 kHz(f1) to 2.5 MHz(f2) range, <0.2 dB gain in
pass band and peak to peak noise should be limited to < 100 mV
VccASM(DDR2)
30 dB(A) attenuation of power supply noise in 50 MHz (f1) to 266 MHz (f2), < 0.2 dB gain in
pass band and peak to peak noise should be limited to < 120 mv
Vcc3G
< 0 dB(A) in 0 to 1.5 MHz, 20 dB(A) attenuation of power supply noise in 1.5 MHz(f1) to 1.25
GHz(f2) range, <0.2 dB gain in pass band and peak to peak noise should be limited to < 40 mV
2. Determined with 2x GMCH DDR/DDR2 buffer strength settings into a 50 Ω to 0.5xVCCSM (DDR/DDR2)
test load.
3. Specified at the measurement point into a timing and voltage compliance test load as shown in
Transmitter compliance eye diagram of PCI Express specification and measured over any 250
consecutive TX Ul's. Specified at the measurement point and measured over any 250 consecutive ULS.
The test load shown in receiver compliance eye diagram of PCI Express specification. Should be used as
the RX device when taking measurements.
4. Low voltage PCI Express (PCI Express Graphics/SDVO) interface.
306
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Electrical Characteristics
R
11.4.2
CRT DAC DC Characteristics
Table 11-7. CRT DAC DC Characteristics: Functional Operating Range (VCCADAC = 2.5 V ±5%)
Parameter
Min
DAC Resolution
Max Luminance (full-scale)
Typical
Max
8
0.665
0.700
Units
Bits
0.770
Notes
(1)
V
(1, 2, 4) white video level voltage
Min Luminance
0.000
V
(1, 3, 4) black video level voltage
LSB Current
73.2
μA
(4, 5)
Integral Linearity (INL)
-1.0
+1.0
LSB
(1, 6)
Differential Linearity (DNL)
-1.0
+1.0
LSB
(1, 6)
6
%
Video channel-channel
voltage amplitude mismatch
Monotonicity
(7)
Guaranteed
NOTES:
1. Measured at each R, G, B termination according to the VESA Test Procedure – Evaluation of Analog
Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000).
2. Max steady-state amplitude
3. Min steady-state amplitude
4. Defined for a double 75-Ω termination.
5. Set by external reference resistor value.
6. INL and DNL measured and calculated according to VESA video signal standards.
7. Max full-scale voltage difference among R,G,B outputs (percentage of steady-state full-scale voltage).
11.4.3
TV DAC DC Characteristics (not supported on the Intel
915GME/Intel 910GMLE chipsets)
Table 11-8.
TV DAC DC Characteristics: Functional Operating Range (VCCATVDAC[A,B,C] = 3.3
V ±5%)
Parameter
Min
Typical
Max
Units
Notes
DAC Resolution
10
Bits
Measured at low-frequency
ENOB (Effective Number of
Bits)
7.5
Bits
@ NTSC/PAL Video BW
Integral Linearity (INL)
-0.5
+0.5
LSB
Note: 1
Differential Linearity (DNL)
-0.5
+0.5
LSB
Note: 1
SNR
48
Video channel-channel
voltage amplitude mismatch
-3
Monotonicity
+3
dB
RMS @ NTSC/PAL Video BW
%
Note: 2
Guaranteed
NOTES:
1. INL and DNL measured and calculated based on the method given in VESA video signal standards.
2. Max full-scale voltage difference among the outputs (percentage of steady-state full-scale voltage).
§
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
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Electrical Characteristics
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308
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
GMCH Strap Pins
R
12
GMCH Strap Pins
12.1
Mobile Intel 915 and 910 Express Chipset Family
Strapping Configuration
Only HW straps CFG{2:0} and CFG [6:5] are used for Mobile Intel 915GMS Express Chipset.
Table 12-1. Mobile Intel 915 Express Chipset Family Strapping Signals and Configuration
Pin Name
CFG[2:0]
Strap
Description
FSB Frequency
Select
Configuration
Notes
000 = Reserved
001 = FSB533
010 = Reserved
011 = Reserved
100 = Reserved
101 = FSB400
110 = Reserved
111 = Reserved
CFG[4:3]
Reserved
CFG5
DMI x2 Select
0 = DMI X2
1 = DMI X4 (Default)
CFG6
CFG7
DDR vs DDR2
select
0 = DDR2
CPU Strap
0 = Reserved
1 = DDR (Default)
1 = Intel Pentium M Processor with 2
MBL2 Cache (Default)
CFG8
Reserved
CFG9
PCI Express
Graphics Lane
Reversal
CFG[11:10]
Reserved
CFG[13:12]
XOR/ALL Z test
straps
0 = Reserve Lanes (15->0, 14->1 etc)
1 = Normal Operation (Default)
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation (Default)
CFG[15:14]
Reserved
CFG16
FSB Dynamic
ODT
0 = Dynamic ODT Disabled
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
309
GMCH Strap Pins
R
Pin Name
Strap
Description
Configuration
Notes
1 = Dynamic ODT Enabled (Default)
CFG17
Reserved
CFG18
GMCH core
VCC Select
0 = 1.05 V (Default)
CPU VTT Select
0 = 1.05 V (Default)
CFG19
1 = 1.5 V
1 = 1.2 V (Reserved)
CFG20
Reserved
SDVOCRTL_
DATA
SDVO Present
0 = No SDVO device present
(Default)
1 = SDVO device present
NOTES: All strap signals are sampled with respect to the leading edge of the Mobile Intel 915/910 Express Chipset
Family PWROK In signal.
§
310
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
13
Ballout and Package Information
Figure 13-1. Intel 915GM, 915GME, 915PM, 910GML, 910GMLE Express Chipset GMCH Ballout
Diagram (Top Left)
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311
Ballout and Package Information
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Figure 13-2. Intel 915GM, 915GME, 915PM, 910GML, 910GMLE Express Chipset GMCH Ballout
Diagram (Top Right)
312
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
13.1
Intel 915GM, 915GME, 915PM, 910GML and 910GMLE
Express Chipset GMCH Ballout List
Some signals may be RESERVED depending on which chipset configuration used. Please refer to the
signal description chapter for more details for which signals are supported for each chipset.
Table 13-1. PLL Signal Group
Ball
Signal
AB29
GCLKN
AC29
GCLKP
AB1
HCLKN
AB2
HCLKP
A24
DREF_CLKN
A23
DREF_CLKP
C37
DREF_SSCLKN
D37
DREF_SSCLKP
Table 13-2.Host Address Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
G9
HA3#
F10
HA15#
C12
HA21#
C9
HA4#
G11
HA16#
B13
HA22#
E9
HA5#
B9
HADSTB0#
A12
HA23#
B7
HA6#
A7
HREQ0#
F12
HA24#
A10
HA7#
D7
HREQ1#
G12
HA25#
F9
HA8#
B8
HREQ2#
E12
HA26#
D8
HA9#
C7
HREQ3#
C13
HA27#
B10
HA10#
A8
HREQ4#
B11
HA28#
E10
HA11#
G13
HA17#
D13
HA29#
G10
HA12#
C10
HA18#
A13
HA30#
D9
HA13#
C11
HA19#
F13
HA31#
E11
HA14#
D11
HA20#
E13
HADSTB1#
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Ballout and Package Information
R
Table 13-3. Host Control Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
F8
HADS#
C6
HDBSY#
C5
HRS1#
A5
HBNR#
E6
HDEFER#
B4
HRS2#
D5
HBPRI#
B3
HLOCK#
D4
HHIT#
B5
HTRDY#
E7
HBREQ0#
D6
HHITM#
F6
RSVD32
A11
RSVD33
G6
HDPWR#
F7
HDRDY#
A4
HRS0#
G8
HSLPCPU#
Table 13-4. Host Data Signal Group
314
Ball
Signal
Ball
Signal
E4
E1
F4
Ball
Signal
HD0#
J1
HD1#
L5
HD23#
V8
HD46#
HD24#
U6
HD2#
HD47#
K4
HD25#
T7
HDINV2#
H7
HD3#
J5
HD26#
R3
HDSTBN2#
E2
HD4#
P7
HD27#
R2
HDSTBP2#
F1
HD5#
L7
HD28#
W6
HD48#
E3
HD6#
J3
HD29#
U3
HD49#
D3
HD7#
P5
HD30#
V5
HD50#
K7
HD8#
L3
HD31#
W8
HD51#
F2
HD9#
K3
HDINV1#
W7
HD52#
J7
HD10#
K1
HDSTBN1#
U2
HD53#
J8
HD11#
K2
HDSTBP1#
U1
HD54#
H6
HD12#
U7
HD32#
Y5
HD55#
F3
HD13#
V6
HD33#
Y2
HD56#
K8
HD14#
R6
HD34#
V4
HD57#
H5
HD15#
R5
HD35#
Y7
HD58#
H8
HDINV0#
P3
HD36#
W1
HD59#
G4
HDSTBN0#
T8
HD37#
W3
HD60#
G5
HDSTBP0#
R7
HD38#
Y3
HD61#
H1
HD16#
R8
HD39#
Y6
HD62#
H2
HD17#
U8
HD40#
W2
HD63#
K5
HD18#
R4
HD41#
U5
HDINV3#
K6
HD19#
T4
HD42#
V3
HDSTBN3#
J4
HD20#
T5
HD43#
W4
HDSTBP3#
G3
HD21#
R1
HD44#
H3
HD22#
T3
HD45#
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Table 13-5. DDR / DDR2 SDRAM Common Signal Group Ball List
Ball
Signal
Ball
Signal
Ball
Signal
AM33
SM_CK0
AF6
SM_CK4
AN16
SM_CS0#
AN33
SM_CK0#
AF5
SM_CK4#
AM14
SM_CS1#
SM_CS2#
AL1
SM_CK1
AC10
RSVD30
AH15
AK1
SM_CK1#
AD10
RSVD31
AG16
SM_CS3#
AE11
RSVD28
AP21
SM_CKE0
AP14
SM_ODT0
AE10
RSVD29
AM21
SM_CKE1
AL15
SM_ODT1
AJ34
SM_CK3
AH21
SM_CKE2
AM11
SM_ODT2
AJ33
SM_CK3#
AK21
SM_CKE3
AN10
SM_ODT3
Table 13-6. DDR / DDR2 SDRAM Channel a Command Signal Group Ball List
Ball
Signal
Ball
Signal
Ball
Signal
AK15
AK16
SA_BS0
AP18
SA_MA2
AM16
SA_MA10
SA_BS1
AM17
SA_MA3
AN20
AL21
SA_MA11
SA_BS2
AN18
SA_MA4
AM20
SA_MA12
AN15
SA_CAS#
AM18
SA_MA5
AM15
SA_MA13
AP16
SA_RAS#
AL19
SA_MA6
AF29
SA_RCVENIN#
AP15
SA_WE#
AP20
SA_MA7
AF28
SA_RCVENOUT#
AL17
SA_MA0
AM19
SA_MA8
AP17
SA_MA1
AL20
SA_MA9
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
315
Ballout and Package Information
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Table 13-7. DDR / DDR2 SDRAM Channel A Data Signal Group Ball List
Ball
316
Signal
Ball
Signal
Ball
Signal
AG35
SA_DQ0
AM24
SA_DQ29
AH1
SA_DQS6#
AH35
SA_DQ1
AN22
SA_DQ30
AF3
SA_DQ56
AL35
SA_DQ2
AP22
SA_DQ31
AE3
SA_DQ57
AL37
SA_DQ3
AP24
SA_DM3
AD6
SA_DQ58
AH36
SA_DQ4
AP23
SA_DQS3
AC4
SA_DQ59
AJ35
SA_DQ5
AN23
SA_DQS3#
AF2
SA_DQ60
AK37
SA_DQ6
AM9
SA_DQ32
AF1
SA_DQ61
AL34
SA_DQ7
AL9
SA_DQ33
AD4
SA_DQ62
AJ37
SA_DM0
AL6
SA_DQ34
AD5
SA_DQ63
AK36
SA_DQS0
AP7
SA_DQ35
AD3
SA_DM7
AK35
SA_DQS0#
AP11
SA_DQ36
AE5
SA_DQS7
AM36
SA_DQ8
AP10
SA_DQ37
AE4
SA_DQS7#
AN35
SA_DQ9
AL7
SA_DQ38
AP32
SA_DQ10
AM7
SA_DQ39
AM31
SA_DQ11
AP9
SA_DM4
AM34
SA_DQ12
AM8
SA_DQS4
AM35
SA_DQ13
AN8
SA_DQS4#
AL32
SA_DQ14
AN5
SA_DQ40
AM32
SA_DQ15
AN6
SA_DQ41
AP35
SA_DM1
AN3
SA_DQ42
AP33
SA_DQS1
AP3
SA_DQ43
AP34
SA_DQS1#
AP6
SA_DQ44
AN31
SA_DQ16
AM6
SA_DQ45
AP31
SA_DQ17
AL4
SA_DQ46
AN28
SA_DQ18
AM3
SA_DQ47
AP28
SA_DQ19
AP4
SA_DM5
AL30
SA_DQ20
AM4
SA_DQS5
AM30
SA_DQ21
AM5
SA_DQS5#
AM28
SA_DQ22
AK2
SA_DQ48
AL28
SA_DQ23
AK3
SA_DQ49
AL29
SA_DM2
AG2
SA_DQ50
AN29
SA_DQS2
AG1
SA_DQ51
AN30
SA_DQS2#
AL3
SA_DQ52
AP27
SA_DQ24
AM2
SA_DQ53
AM27
SA_DQ25
AH3
SA_DQ54
AM23
SA_DQ26
AG3
SA_DQ55
AM22
SA_DQ27
AJ2
SA_DM6
AL23
SA_DQ28
AJ1
SA_DQS6
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Table 13-8.DDR / DDR2 SDRAM Channel B Signal Group Ball List
Ball
Signal
Ball
Signal
Ball
Signal
AJ15
SB_BS0
AH18
AG17
SB_BS1
AJ18
SB_MA2
AJ16
SB_MA10
SB_MA3
AG18
SB_MA11
AG21
SB_BS2
AK18
AK14
SB_RAS#
AJ19
SB_MA4
AG20
SB_MA12
SB_MA5
AG15
AH14
SB_CAS#
AK19
SB_MA6
AF15
SB_RCVENIN#
AH16
SB_WE#
AH19
SB_MA7
AF14
SB_RCVENOUT#
AH17
SB_MA0
AJ20
SB_MA8
AK17
SB_MA1
AH20
SB_MA9
SB_MA13
Table 13-9. DDR / DDR2 SDRAM Channel B Signal Group Ball List
Ball
Signal
Ball
Signal
Ball
Signal
AE31
SB_DQ0
AJ28
SB_DQS2
AJ5
SB_DQ46
AE32
SB_DQ1
AK28
SB_DQS2#
AK4
SB_DQ47
AG32
SB_DQ2
AK5
SB_DM5
AG36
SB_DQ3
AF24
SB_DQ24
AH6
SB_DQS5
AE34
SB_DQ4
AG23
SB_DQ25
AH7
SB_DQS5#
AE33
SB_DQ5
AJ22
SB_DQ26
AG5
SB_DQ48
AF31
SB_DQ6
AK22
SB_DQ27
AG4
SB_DQ49
AF30
SB_DQ7
AH24
SB_DQ28
AD8
SB_DQ50
AF32
SB_DM0
AH23
SB_DQ29
AD9
SB_DQ51
AF34
SB_DQS0
AG22
SB_DQ30
AH4
SB_DQ52
AF35
SB_DQS0#
AJ21
SB_DQ31
AG6
SB_DQ53
AK24
SB_DM3
AE8
SB_DQ54
AH33
SB_DQ8
AK23
SB_DQS3
AD7
SB_DQ55
AH32
SB_DQ9
AJ23
SB_DQS3#
AE7
SB_DM6
AK31
SB_DQ10
AG10
SB_DQ32
AF8
SB_DQS6
AG30
SB_DQ11
AG9
SB_DQ33
AF7
SB_DQS6#
AG34
SB_DQ12
AG8
SB_DQ34
AG33
SB_DQ13
AH8
SB_DQ35
AC5
SB_DQ56
AH31
SB_DQ14
AH11
SB_DQ36
AB8
SB_DQ57
AJ31
SB_DQ15
AH10
SB_DQ37
AB6
SB_DQ58
AK34
SB_DM1
AJ9
SB_DQ38
AA8
SB_DQ59
AK32
SB_DQS1
AK9
SB_DQ39
AC8
SB_DQ60
AK33
SB_DQS1#
AJ10
SB_DM4
AC7
SB_DQ61
AK30
SB_DQ16
AM10
SB_DQS4
AA4
SB_DQ62
AJ30
SB_DQ17
AL10
SB_DQS4#
AA5
SB_DQ63
AH29
SB_DQ18
AB7
SB_DM7
AH28
SB_DQ19
AJ7
SB_DQ40
AB4
SB_DQS7
AK29
SB_DQ20
AK6
SB_DQ41
AB5
SB_DQS7#
AH30
SB_DQ21
AJ4
SB_DQ42
AH27
SB_DQ22
AH5
SB_DQ43
AG28
SB_DQ23
AK8
SB_DQ44
AK27
SB_DM2
AJ8
SB_DQ45
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
317
Ballout and Package Information
R
Table 13-10. Analog CRT Signal Group
Ball
Signal
Ball
Signal
A19
RED
E21
BLUE
B19
RED#
D21
BLUE#
C20
GREEN
G21
HSYNC
B20
GREEN#
H21
VSYNC
Table 13-11. Analog TV Signal Group
Note: These signals are not supported on the Intel 915GME / Intel 910GMLE chipsets and require termination
according to the platform design guide.
Ball
Signal
Ball
Signal
Ball
A15
TVDAC_A
B16
TV_IRTNB
B15
TV_IRTNA
A17
TVDAC_C
C16
TVDAC_B
B17
TV_IRTNC
Signal
Table 13-12. LVDS Display Interface Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
B34
LA_DATAN0
A34
LA_DATAP0
C29
LB_DATAN0
C28
LB_DATAP0
B33
LA_DATAN1
A33
LA_DATAP1
D28
LB_DATAN1
D27
LB_DATAP1
B32
LA_DATAN2
B31
LA_DATAP2
C27
LB_DATAN2
C26
LB_DATAP2
B30
LA_CLKN
B29
LA_CLKP
C25
LB_CLKN
C24
LB_CLKP
Table 13-13. LVDS Power Sequencing and Backlight Control Signal Group
Ball
Signal
E25
LBKLT_CRTL
F25
LBKLT_EN
F26
LVDD_EN
Table 13-14. DDC / GMBUS Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
E24
DDCCLK
C22
LCTLB_DATA
H25
SDVOCTRL_CLK
E23
DDCDATA
F23
LDDC_CLK
C23
LCTLA_CLK
F22
LDDC_DATA
H24
SDVOCTRL_DAT
A
Table 13-15. DMI Serial Interface Signal Group
318
Ball
Signal
Ball
Signal
AA31
AB35
Ball
Signal
DMI_RXN0
AB31
DMI_RXP2
Y33
DMI_TXP0
DMI_RXN1
AC35
DMI_RXP3
AA37
DMI_TXP1
AC31
DMI_RXN2
AA33
DMI_TXN0
AB33
DMI_TXP2
AD35
DMI_RXN3
AB37
DMI_TXN1
AC37
DMI_TXP3
Y31
DMI_RXP0
AC33
DMI_TXN2
AA35
DMI_RXP1
AD37
DMI_TXN3
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Table 13-16. PCI Express Based Graphics / Serial Digital Video Out Receive Signal Group
Ball
PCI Express /
Signal
SDVO Signal
Ball
PCI Express /
Signal
SDVO Signal
E30
EXP_RXN0
SDVO_TVCLKIN#
F34
EXP_RXN1
SDVOB_INT#
D30
EXP_RXP0
SDVO_TVCLKIN
E34
EXP_RXP1
G30
EXP_RXN2
SDVO_FLDSTALL#
SDVOB_INT
F30
EXP_RXP2
SDVO_FLDSTALL
EXP_RXP3
H34
EXP_RXN3
G34
J30
EXP_RXN4
H30
EXP_RXP4
K34
EXP_RXN5
J34
EXP_RXP5
EXP_RXP6
SDVOB_INT#
L30
EXP_RXN6
K30
M34
EXP_RXN7
L34
EXP_RXP7
N30
EXP_RXN8
M30
EXP_RXP8
P34
EXP_RXN9
N34
EXP_RXP9
R30
EXP_RXN10
P30
EXP_RXP10
EXP_RXP11
T34
EXP_RXN11
R34
U30
EXP_RXN12
T30
EXP_RXP12
V34
EXP_RXN13
U34
EXP_RXP13
W30
EXP_RXN14
V30
EXP_RXP14
Y34
EXP_RXN15
W34
EXP_RXP15
SDVOB_INT
Table 13-17. PCI Express Based Graphics / Serial Digital Video Out Transmit Signal Group
Ball
PCI_E
Signal
E32
SDVO Signal
Ball
PCI_E
Signal
EXP_TXN0
D32
EXP_TXP0
EXP_TXP1
F36
EXP_TXN1
E36
G32
EXP_TXN2
F32
EXP_TXP2
H36
EXP_TXN3
G36
EXP_TXP3
J32
EXP_TXN4
H32
EXP_TXP4
K36
EXP_TXN5
J36
EXP_TXP5
L32
EXP_TXN6
K32
EXP_TXP6
M36
EXP_TXN7
L36
EXP_TXP7
N32
EXP_TXN8
M32
EXP_TXP8
P36
EXP_TXN9
N36
EXP_TXP9
R32
EXP_TXN10
P32
EXP_TXP10
EXP_TXP11
T36
EXP_TXN11
R36
U32
EXP_TXN12
T32
EXP_TXP12
V36
EXP_TXN13
U36
EXP_TXP13
W32
EXP_TXN14
V32
EXP_TXP14
Y36
EXP_TXN15
W36
EXP_TXP15
Table 13-18. Thermal and Power Sequencing Signal Group
Ball
Signal
Ball
Signal
AE29
RSTIN#
F5
THRMTRIP#
H10
HCPURST#
J21
EXT_TS0#
AD30
PWROK
H22
EXT_TS1#
SDVO
Signal
Ballout and Package Information
R
Ball
Signal
J23
BM_BUSY#
Ball
Signal
Table 13-19. No Connect Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
AP37
AN37
NC1
B37
NC9
A37
NC11
NC2
AN1
NC6
AP36
NC3
B1
NC7
AP2
NC4
A2
NC8
AP1
NC5
A36
NC10
Table 13-20. Configuration & Reserved Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
G16
CFG0
E15
CFG10
D23
CFG20
H13
CFG1
D14
CFG11
G25
RSVD21
G14
CFG2
E14
CFG12
G24
RSVD22
F16
CFG3
H12
CFG13
J17
RSVD23
F15
CFG4
C14
CFG14
A31
RSVD24
G15
CFG5
H15
CFG15
A30
RSVD25
E16
CFG6
J15
CFG16
D26
RSVD26
D17
CFG7
H14
CFG17
D25
RSVD27
J16
CFG8
G22
CFG18
D15
CFG9
G23
CFG19
Table 13-21. Voltage Reference and Compensation Signal Groups
Ball
Signal Name
System Memory
AF22
SMOCDCOMP0
AF16
SMOCDCOMP1
AK10
SMRCOMPN
AK11
SMRCOMPP
AE27
SMXSLEWIN
AE28
SMXSLEWOUT
Ball
Signal Name
C2
HXSCOMP
D1
HXSWING
T1
HYRCOMP
L1
HYSCOMP
P1
HYSWING
J11
HVREF
AF9
SMYSLEWIN
D36
EXP_COMPI
SMYSLEWOUT
D34
EXP_ICOMPO
SMVREF0
AD1
SMVREF1
Signal Name
LVDS
F28
LVREFH
F27
LVREFL
C33
LIBG
C31
LVBG
PCI Express/SDVO
AF10
AF37
Ball
CRT DAC
J20
REFSET
Host Interface
TV
C1
320
HXRCOMP
J18
TV_REFSET
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Table 13-22. Power Signal Group
Ball
Signal
PLL Signal Group
Ball
Signal
Ball
Signal
F37
VCCA_3GBG
A35
VCCA_LVDS
G37
VSSA_3GBG
B36
VSSALVDS
AA1
VCCA_HPLL
AA2
VCCA_MPLL
AC2
VCCD_HMPLL1
B22
VCCHV
AC1
VCCD_HMPLL2
B21
VCCHV
Y29
VCCA_3GPLL
A21
VCCHV
Y28
VCCA_3GPLL
Y27
VCCA_3GPLL
H20
VCC_SYNC
B23
VCCA_DPLLA
F19
VCCA_CRTDAC
D19
VCCD_TVDAC
E19
VCCA_CRTDAC
H17
VCCDQ_TVDAC
G19
VSSA_CRTDAC
F17
VCCA_TVDACA
C35
VCCA_DPLLB
PCI Express Graphics
AE37
VCC3G
W37
VCC3G
U37
VCC3G
High Voltage
CRT DAC
E17
VCCA_TVDACA
VCCD_LVDS
D18
VCCA_TVDACB
VCCD_LVDS
C18
VCCA_TVDACB
F18
VCCA_TVDACC
LVDS Signal Group
B26
B25
TV Out Signal Group
(These signals are not
supported on the Intel
915GME / Intel 910GMLE
chipsets and require
termination according to the
platform design guide.)
R37
VCC3G
A25
VCCD_LVDS
N37
VCC3G
B28
VCCTX_LVDS
E18
VCCA_TVDACC
VCCTX_LVDS
H18
VCCA_TVBG
VCCTX_LVDS
G18
VSSA_TVBG
L37
J37
VCC3G
VCC3G
A28
A27
Table 13-23. System Memory Analog Power Signal Group
Ball
Signal
AF20
VCCASM
AP19
VCCASM
AF19
VCCASM
AF18
VCCASM
Table 13-24. System Memory Power Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
AB9
VCCSM
AK13
VCCSM
AB10
VCCSM
AD28
VCCSM
AK25
VCCSM
AB11
VCCSM
AE1
VCCSM
AK26
VCCSM
AC11
VCCSM
AE12
VCCSM
AL12
VCCSM
AC27
VCCSM
AE26
VCCSM
AL13
VCCSM
AD11
VCCSM
AF12
VCCSM
AL25
VCCSM
AD27
VCCSM
AF13
VCCSM
AL26
VCCSM
AE13
VCCSM
AF25
VCCSM
AM1
VCCSM
AE14
VCCSM
AF26
VCCSM
AM12
VCCSM
AE15
VCCSM
AG12
VCCSM
AM13
VCCSM
AE16
VCCSM
AG13
VCCSM
AM25
VCCSM
AE17
VCCSM
AG25
VCCSM
AM26
VCCSM
AE18
VCCSM
AG26
VCCSM
AM37
VCCSM
AE19
VCCSM
AH12
VCCSM
AN12
VCCSM
AE20
VCCSM
AH13
VCCSM
AN13
VCCSM
AE21
VCCSM
AH25
VCCSM
AN25
VCCSM
AE22
VCCSM
AH26
VCCSM
AN26
VCCSM
AE23
VCCSM
AH37
VCCSM
AP12
VCCSM
AE24
VCCSM
AJ12
VCCSM
AP13
VCCSM
AE25
VCCSM
AJ13
VCCSM
AP25
VCCSM
AJ25
VCCSM
AP26
VCCSM
AJ26
VCCSM
AP29
VCCSM
AK12
VCCSM
AP8
VCCSM
Ball
Signal
L11
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
Table 13-25. VTT Power Signal Group
Ball
Signal
Ball
Signal
A6
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
M8
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
B2
G1
J10
J13
J9
K10
K11
K12
L9
M1
M10
M2
M3
M4
M5
M6
M7
322
M9
N1
N2
N3
N4
N5
N6
N7
N8
N9
P9
R9
U9
V1
W9
Y9
K13
M11
N10
N11
P10
P11
R10
R11
T10
T11
U10
U11
V10
V11
W10
W11
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Table 13-26. GMCH Core Voltage Power Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
G28
VCC
T18
VCC
V27
VCC
H26
VCC
T20
VCC
V28
VCC
H27
VCC
T29
VCC
K17
VCC
H28
VCC
U19
VCC
K18
VCC
J25
VCC
U20
VCC
K19
VCC
J27
VCC
V18
VCC
K20
VCC
J28
VCC
V19
VCC
K21
VCC
J29
VCC
W18
VCC
K22
VCC
K26
VCC
W20
VCC
K23
VCC
K27
VCC
P27
VCC
K24
VCC
K28
VCC
P28
VCC
K25
VCC
K29
VCC
R27
VCC
L27
VCC
L28
VCC
R28
VCC
M27
VCC
M28
VCC
T27
VCC
N27
VCC
M29
VCC
T28
VCC
N28
VCC
N29
VCC
U27
VCC
R29
VCC
U28
VCC
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
323
Table 13-27. GMCH Ground Signal Group
Ball
324
Signal
Ball
Signal
Ball
Signal
A14
VSS
AD33
VSS
AJ3
VSS
A16
VSS
AD34
VSS
AJ32
VSS
A18
VSS
AD36
VSS
AJ36
VSS
A20
VSS
AE2
VSS
AJ6
VSS
A22
VSS
AE30
VSS
AK20
VSS
A26
VSS
AE35
VSS
AK7
VSS
A29
VSS
AE36
VSS
AL11
VSS
A3
VSS
AE6
VSS
AL14
VSS
A32
VSS
AE9
VSS
AL16
VSS
A9
VSS
AF11
VSS
AL18
VSS
AA29
VSS
AF17
VSS
AL2
VSS
AA3
VSS
AF21
VSS
AL22
VSS
AA30
VSS
AF23
VSS
AL24
VSS
AA32
VSS
AF27
VSS
AL27
VSS
AA34
VSS
AF33
VSS
AL31
VSS
AA36
VSS
AF36
VSS
AL33
VSS
AA6
VSS
AF4
VSS
AL36
VSS
AA7
VSS
AG11
VSS
AL5
VSS
AA9
VSS
AG14
VSS
AL8
VSS
AB3
VSS
AG19
VSS
AM29
VSS
AB30
VSS
AG24
VSS
AN11
VSS
AB32
VSS
AG27
VSS
AN14
VSS
AB34
VSS
AG29
VSS
AN17
VSS
AB36
VSS
AG31
VSS
AN19
VSS
AC28
VSS
AG37
VSS
AN2
VSS
AC3
VSS
AG7
VSS
AN21
VSS
AC30
VSS
AH2
VSS
AN24
VSS
AC32
VSS
AH22
VSS
AN27
VSS
AC34
VSS
AH34
VSS
AN32
VSS
AC36
VSS
AH9
VSS
AN34
VSS
AC6
VSS
AJ11
VSS
AN36
VSS
AC9
VSS
AJ14
VSS
AN4
VSS
AD2
VSS
AJ17
VSS
AN7
VSS
AD29
VSS
AJ24
VSS
AN9
VSS
AD31
VSS
AJ27
VSS
AP30
VSS
AD32
VSS
AJ29
VSS
AP5
VSS
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
B12
VSS
E33
VSS
J14
VSS
B14
VSS
E35
VSS
J19
VSS
B18
VSS
E37
VSS
J2
VSS
B24
VSS
E5
VSS
J22
VSS
B27
VSS
E8
VSS
J24
VSS
B35
VSS
F11
VSS
J26
VSS
B6
VSS
F14
VSS
J31
VSS
C15
VSS
F20
VSS
J33
VSS
C17
VSS
F21
VSS
J35
VSS
C19
VSS
F24
VSS
J6
VSS
C21
VSS
F29
VSS
K37
VSS
C3
VSS
F31
VSS
K9
VSS
C30
VSS
F33
VSS
L10
VSS
C32
VSS
F35
VSS
L2
VSS
C34
VSS
G17
VSS
L29
VSS
C36
VSS
G2
VSS
L31
VSS
C4
VSS
G20
VSS
L33
VSS
C8
VSS
G26
VSS
L35
VSS
D10
VSS
G27
VSS
L4
VSS
D12
VSS
G29
VSS
L6
VSS
D16
VSS
G31
VSS
L8
VSS
D2
VSS
G33
VSS
M31
VSS
D20
VSS
G35
VSS
M33
VSS
D22
VSS
G7
VSS
M35
VSS
D24
VSS
H11
VSS
M37
VSS
D29
VSS
H16
VSS
N31
VSS
D31
VSS
H19
VSS
N33
VSS
D33
VSS
H23
VSS
N35
VSS
D35
VSS
H29
VSS
P2
VSS
E20
VSS
H31
VSS
P29
VSS
E22
VSS
H33
VSS
P31
VSS
E26
VSS
H35
VSS
P33
VSS
E27
VSS
H37
VSS
P35
VSS
E28
VSS
H4
VSS
P37
VSS
E29
VSS
H9
VSS
P4
VSS
E31
VSS
J12
VSS
P6
VSS
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
325
Ballout and Package Information
R
Ball
326
Signal
Ball
Signal
Ball
Signal
P8
VSS
V20
VSS
Y8
VSS
R31
VSS
V31
VSS
AA10
VSS
R33
VSS
V33
VSS
AA11
VSS
R35
VSS
V35
VSS
AA27
VSS
T19
VSS
V37
VSS
AA28
VSS
T2
VSS
V7
VSS
AB27
VSS
T31
VSS
V9
VSS
AB28
VSS
T33
VSS
W19
VSS
K14
VSS
T35
VSS
W29
VSS
K15
VSS
T37
VSS
W31
VSS
K16
VSS
T6
VSS
W33
VSS
K31
VSS
T9
VSS
W35
VSS
K33
VSS
U18
VSS
W5
VSS
K35
VSS
U29
VSS
Y1
VSS
U31
VSS
Y30
VSS
U33
VSS
Y32
VSS
U35
VSS
Y35
VSS
U4
VSS
Y37
VSS
V2
VSS
Y4
VSS
V29
VSS
W27
VSS
W28
VSS
Y10
VSS
Y11
VSS
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Table 13-28. VCC Core Non-Critical to Function Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
L17
VCC_NCTF
N24
VCC_NCTF
T26
VCC_NCTF
L18
VCC_NCTF
N25
VCC_NCTF
U17
VCC_NCTF
L19
VCC_NCTF
N26
VCC_NCTF
U21
VCC_NCTF
L20
VCC_NCTF
P17
VCC_NCTF
U22
VCC_NCTF
L21
VCC_NCTF
P18
VCC_NCTF
U23
VCC_NCTF
L22
VCC_NCTF
P19
VCC_NCTF
U24
VCC_NCTF
L23
VCC_NCTF
P20
VCC_NCTF
U25
VCC_NCTF
L24
VCC_NCTF
P21
VCC_NCTF
U26
VCC_NCTF
L25
VCC_NCTF
P22
VCC_NCTF
V17
VCC_NCTF
L26
VCC_NCTF
P23
VCC_NCTF
V21
VCC_NCTF
M17
VCC_NCTF
P24
VCC_NCTF
V22
VCC_NCTF
M18
VCC_NCTF
P25
VCC_NCTF
V23
VCC_NCTF
M19
VCC_NCTF
P26
VCC_NCTF
V24
VCC_NCTF
M20
VCC_NCTF
R18
VCC_NCTF
V25
VCC_NCTF
M21
VCC_NCTF
R19
VCC_NCTF
V26
VCC_NCTF
M22
VCC_NCTF
R20
VCC_NCTF
W17
VCC_NCTF
M23
VCC_NCTF
R22
VCC_NCTF
W21
VCC_NCTF
M24
VCC_NCTF
R23
VCC_NCTF
W22
VCC_NCTF
M25
VCC_NCTF
R24
VCC_NCTF
W23
VCC_NCTF
M26
VCC_NCTF
R25
VCC_NCTF
W24
VCC_NCTF
N17
VCC_NCTF
R26
VCC_NCTF
W25
VCC_NCTF
N18
VCC_NCTF
T17
VCC_NCTF
W26
VCC_NCTF
N19
VCC_NCTF
T21
VCC_NCTF
Y18
VCC_NCTF
N20
VCC_NCTF
T22
VCC_NCTF
Y19
VCC_NCTF
N21
VCC_NCTF
T23
VCC_NCTF
Y20
VCC_NCTF
N22
VCC_NCTF
T24
VCC_NCTF
N23
VCC_NCTF
T25
VCC_NCTF
Table 13-29. VTT Core Non-Critical to Function Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
L12
VTT_NCTF
P12
VTT_NCTF
U12
VTT_NCTF
L13
VTT_NCTF
P13
VTT_NCTF
U13
VTT_NCTF
M12
VTT_NCTF
R12
VTT_NCTF
V12
VTT_NCTF
M13
VTT_NCTF
R13
VTT_NCTF
V13
VTT_NCTF
N12
VTT_NCTF
T12
VTT_NCTF
W12
VTT_NCTF
N13
VTT_NCTF
T13
VTT_NCTF
W13
VTT_NCTF
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
327
Ballout and Package Information
R
Table 13-30. VCCSM Non-Critical to Function Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
AB12
VCCSM_NCTF
AC21
VCCSM_NCTF
AD17
VCCSM_NCTF
AB13
VCCSM_NCTF
AC22
VCCSM_NCTF
AD18
VCCSM_NCTF
VCCSM_NCTF
AC23
VCCSM_NCTF
AD19
VCCSM_NCTF
VCCSM_NCTF
AC12
AC13
VCCSM_NCTF
AC24
VCCSM_NCTF
AD20
AC14
VCCSM_NCTF
AC25
VCCSM_NCTF
AD21
VCCSM_NCTF
AC15
VCCSM_NCTF
AC26
VCCSM_NCTF
AD22
VCCSM_NCTF
AC16
VCCSM_NCTF
AD12
VCCSM_NCTF
AD23
VCCSM_NCTF
VCCSM_NCTF
AD24
VCCSM_NCTF
VCCSM_NCTF
AC17
VCCSM_NCTF
AD13
AC18
VCCSM_NCTF
AD14
VCCSM_NCTF
AD25
AC19
VCCSM_NCTF
AD15
VCCSM_NCTF
AD26
VCCSM_NCTF
AC20
VCCSM_NCTF
AD16
VCCSM_NCTF
Table 13-31. VSS Non-Critical to Function Signal Group
328
Ball
Signal
Ball
Signal
Ball
Signal
AA12
VSS_NCTF
AB23
VSS_NCTF
T16
VSS_NCTF
AA13
VSS_NCTF
AB24
VSS_NCTF
U14
VSS_NCTF
AA14
VSS_NCTF
AB25
VSS_NCTF
U15
VSS_NCTF
AA15
VSS_NCTF
AB26
VSS_NCTF
U16
VSS_NCTF
AA16
VSS_NCTF
L14
VSS_NCTF
V14
VSS_NCTF
AA17
VSS_NCTF
L15
VSS_NCTF
V15
VSS_NCTF
AA18
VSS_NCTF
L16
VSS_NCTF
V16
VSS_NCTF
AA19
VSS_NCTF
M14
VSS_NCTF
W14
VSS_NCTF
AA20
VSS_NCTF
M15
VSS_NCTF
W15
VSS_NCTF
AA21
VSS_NCTF
M16
VSS_NCTF
W16
VSS_NCTF
AA22
VSS_NCTF
N14
VSS_NCTF
Y12
VSS_NCTF
AA23
VSS_NCTF
N15
VSS_NCTF
Y13
VSS_NCTF
AA24
VSS_NCTF
N16
VSS_NCTF
Y14
VSS_NCTF
AA25
VSS_NCTF
P14
VSS_NCTF
Y15
VSS_NCTF
AA26
VSS_NCTF
P15
VSS_NCTF
Y16
VSS_NCTF
AB14
VSS_NCTF
P16
VSS_NCTF
Y17
VSS_NCTF
AB15
VSS_NCTF
R14
VSS_NCTF
Y21
VSS_NCTF
AB16
VSS_NCTF
R15
VSS_NCTF
Y22
VSS_NCTF
AB17
VSS_NCTF
R16
VSS_NCTF
Y23
VSS_NCTF
AB18
VSS_NCTF
R17
VSS_NCTF
AB19
VSS_NCTF
Y24
VSS_NCTF
R21
VSS_NCTF
AB20
VSS_NCTF
Y25
VSS_NCTF
T14
VSS_NCTF
AB21
VSS_NCTF
Y26
VSS_NCTF
T15
VSS_NCTF
AB22
VSS_NCTF
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
13.2
GMCH Signal Name Ordering Ball list
Table 13-32 applies to the Mobile Intel 915GM/GME/PM and Intel 910GML/GMLE Express Chipset ball-out. Some
signals may be RESERVED depending on chipset configuration used. Please refer to the signal description chapter for
more details.
Table 13-32. GMCH Signal Name Ordering Ball List
Ball
Signal
Ball
Signal
Ball
Signal
E21
BLUE
AC33
DMI_TXN2
N34
EXP_RXP9
EXP_RXP10
EXP_RXP11
D21
BLUE#
AD37
DMI_TXN3
P30
J23
BM_BUSY#
Y33
DMI_TXP0
R34
CFG0
AA37
DMI_TXP1
T30
EXP_RXP12
DMI_TXP2
U34
EXP_RXP13
G16
H13
CFG1
AB33
G14
CFG2
AC37
DMI_TXP3
V30
EXP_RXP14
F16
CFG3
A24
DREF_CLKN
W34
EXP_RXP15
F15
CFG4
A23
DREF_CLKP
E32
EXP_TXN0
G15
CFG5
C37
DREF_SSCLKN
F36
EXP_TXN1
DREF_SSCLKP
G32
EXP_TXN2
H36
EXP_TXN3
E16
CFG6
D37
D17
CFG7
D36
EXP_COMPI
J16
CFG8
D34
EXP_ICOMPO
J32
EXP_TXN4
CFG9
E30
EXP_RXN0
K36
EXP_TXN5
EXP_TXN6
EXP_TXN7
D15
E15
CFG10
F34
EXP_RXN1
L32
D14
CFG11
G30
EXP_RXN2
M36
CFG12
H34
EXP_RXN3
N32
EXP_TXN8
EXP_TXN9
EXP_TXN10
E14
CFG13
J30
EXP_RXN4
P36
C14
CFG14
K34
EXP_RXN5
R32
H15
CFG15
L30
EXP_RXN6
T36
EXP_TXN11
EXP_RXN7
U32
EXP_TXN12
EXP_RXN8
V36
EXP_TXN13
H12
J15
CFG16
M34
H14
CFG17
N30
G22
CFG18
P34
EXP_RXN9
W32
EXP_TXN14
CFG19
R30
EXP_RXN10
Y36
EXP_TXN15
EXP_RXN11
D32
EXP_TXP0
EXP_TXP1
G23
D23
CFG20
T34
E24
DDCCLK
U30
EXP_RXN12
E36
DDCDATA
V34
EXP_RXN13
F32
EXP_TXP2
DMI_RXN0
W30
EXP_RXN14
G36
EXP_TXP3
DMI_RXN1
Y34
EXP_RXN15
H32
EXP_TXP4
AC31
DMI_RXN2
D30
EXP_RXP0
J36
EXP_TXP5
AD35
DMI_RXN3
E34
EXP_RXP1
K32
EXP_TXP6
Y31
DMI_RXP0
F30
EXP_RXP2
L36
EXP_TXP7
AA35
DMI_RXP1
G34
EXP_RXP3
M32
EXP_TXP8
AB31
DMI_RXP2
H30
EXP_RXP4
N36
EXP_TXP9
AC35
DMI_RXP3
J34
EXP_RXP5
P32
EXP_TXP10
AA33
DMI_TXN0
K30
EXP_RXP6
R36
EXP_TXP11
DMI_TXN1
L34
EXP_RXP7
T32
EXP_TXP12
M30
EXP_RXP8
E23
AA31
AB35
AB37
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
329
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
U36
EXP_TXP13
AB2
HCLKP
T4
HD42#
HD43#
V32
EXP_TXP14
H10
HCPURST#
T5
W36
EXP_TXP15
G8
HCPUSLP#
R1
HD44#
J21
EXT_TS0#
E4
HD0#
T3
HD45#
HD46#
HD47#
H22
EXT_TS1#
E1
HD1#
V8
AB29
GCLKN
F4
HD2#
U6
AC29
GCLKP
H7
HD3#
W6
HD48#
C20
GREEN
E2
HD4#
U3
HD49#
B20
GREEN#
F1
HD5#
V5
HD50#
G9
HA3#
E3
HD6#
W8
HD51#
C9
HA4#
D3
HD7#
W7
HD52#
E9
HA5#
K7
HD8#
U2
HD53#
HA6#
F2
HD9#
U1
HD54#
A10
HA7#
J7
HD10#
Y5
HD55#
F9
B7
HA8#
J8
HD11#
Y2
HD56#
D8
HA9#
H6
HD12#
V4
HD57#
B10
HA10#
F3
HD13#
Y7
HD58#
E10
HA11#
K8
HD14#
W1
HD59#
HA12#
H5
HD15#
W3
HD60#
D9
HA13#
H1
HD16#
Y3
HD61#
E11
HA14#
H2
HD17#
Y6
HD62#
HD18#
W2
HD63#
C6
HDBSY#
E6
HDEFER#
H8
HDINV0#
G10
330
F10
HA15#
K5
G11
HA16#
K6
HD19#
G13
HA17#
J4
HD20#
C10
HA18#
G3
HD21#
C11
HA19#
H3
HD22#
D11
HA20#
J1
HD23#
C12
HA21#
L5
HD24#
K4
HD25#
B13
HA22#
A12
HA23#
F12
HA24#
G12
HA25#
E12
HA26#
C13
HA27#
B11
HA28#
D13
HA29#
A13
HA30#
F13
HA31#
F8
HADS#
B9
HADSTB0#
E13
HADSTB1#
A5
HBNR#
D5
HBPRI#
E7
HBREQ0#
AB1
HCLKN
K3
HDINV1#
T7
HDINV2#
U5
HDINV3#
G6
HDPWR#
J5
HD26#
P7
HD27#
F7
HDRDY#
L7
HD28#
G4
HDSTBN0#
J3
HD29#
K1
HDSTBN1#
P5
HD30#
R3
HDSTBN2#
L3
HD31#
V3
HDSTBN3#
U7
HD32#
G5
HDSTBP0#
HDSTBP1#
V6
HD33#
K2
R6
HD34#
R2
HDSTBP2#
R5
HD35#
W4
HDSTBP3#
HD36#
F6
RSVD32
P3
T8
HD37#
D4
HHIT#
R7
HD38#
D6
HHITM#
R8
HD39#
B3
HLOCK#
U8
HD40#
A11
RSVD33
R4
HD41#
A7
HREQ0#
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
D7
HREQ1#
AN37
NC2
AP32
SA_DQ10
B8
HREQ2#
AP36
NC3
AM31
SA_DQ11
C7
HREQ3#
AP2
NC4
AM34
SA_DQ12
A8
HREQ4#
AP1
NC5
AM35
SA_DQ13
A4
HRS0#
AN1
NC6
C5
HRS1#
B1
NC7
B4
HRS2#
A2
NC8
G21
HSYNC
B37
NC9
B5
HTRDY#
A36
NC10
J11
HVREF
A37
NC11
C1
HXRCOMP
AD30
PWROK
C2
HXSCOMP
A19
RED
D1
HXSWING
T1
HYRCOMP
L1
HYSCOMP
P1
HYSWING
B30
LACLKN
B29
LACLKP
B34
LADATAN0
B33
LADATAN1
B32
LADATAN2
A34
LADATAP0
A33
LADATAP1
B31
LADATAP2
C25
LBCLKN
C24
LBCLKP
C29
LBDATAN0
D28
LBDATAN1
C27
LBDATAN2
C28
LBDATAP0
D27
LBDATAP1
C26
LBDATAP2
E25
LBKLT_CRTL
F25
LBKLT_EN
C23
LCTLA_CLK
C22
LCTLB_DATA
F23
LDDC_CLK
F22
LDDC_DATA
AL32
SA_DQ14
AM32
SA_DQ15
AN31
SA_DQ16
AP31
SA_DQ17
AN28
SA_DQ18
AP28
SA_DQ19
AL30
SA_DQ20
SA_DQ21
B19
RED#
AM30
J20
REFSET
AM28
SA_DQ22
RSTIN#
AL28
SA_DQ23
G25
RSVD21
AP27
SA_DQ24
G24
RSVD22
AM27
SA_DQ25
RSVD23
AM23
SA_DQ26
A31
RSVD24
AM22
SA_DQ27
A30
AE29
J17
RSVD25
AL23
SA_DQ28
D26
RSVD26
AM24
SA_DQ29
D25
RSVD27
AN22
SA_DQ30
AK15
SA_BS0
AP22
SA_DQ31
AK16
SA_BS1
AM9
SA_DQ32
AL21
SA_BS2
AL9
SA_DQ33
AN15
SA_CAS#
AL6
SA_DQ34
AJ37
SA_DM0
AP7
SA_DQ35
AP35
SA_DM1
AP11
SA_DQ36
AL29
SA_DM2
AP10
SA_DQ37
AP24
SA_DM3
AL7
SA_DQ38
AP9
SA_DM4
AM7
SA_DQ39
AP4
SA_DM5
AN5
SA_DQ40
AJ2
SA_DM6
AN6
SA_DQ41
AD3
SA_DM7
AG35
SA_DQ0
AH35
SA_DQ1
AL35
SA_DQ2
AL37
SA_DQ3
AH36
SA_DQ4
AJ35
SA_DQ5
AN3
SA_DQ42
AP3
SA_DQ43
AP6
SA_DQ44
AM6
SA_DQ45
AL4
SA_DQ46
C33
LIBG
C31
LVBG
F26
LVDD_EN
AK37
SA_DQ6
F28
LVREFH
AL34
SA_DQ7
F27
LVREFL
AM36
SA_DQ8
AG1
SA_DQ51
AP37
NC1
AN35
SA_DQ9
AL3
SA_DQ52
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
AM3
SA_DQ47
AK2
SA_DQ48
AK3
SA_DQ49
AG2
SA_DQ50
331
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
AM2
SA_DQ53
AP15
SA_WE#
AG22
SB_DQ30
AH3
SA_DQ54
AJ15
SB_BS0
AJ21
SB_DQ31
AG3
SA_DQ55
AG17
SB_BS1
AG10
SB_DQ32
AF3
SA_DQ56
AG21
SB_BS2
AG9
SB_DQ33
AE3
SA_DQ57
AH14
SB_CAS#
AG8
SB_DQ34
AD6
SA_DQ58
AF32
SB_DM0
AH8
SB_DQ35
AC4
SA_DQ59
AK34
SB_DM1
AH11
SB_DQ36
AF2
SA_DQ60
AK27
SB_DM2
AH10
SB_DQ37
AF1
SA_DQ61
AK24
SB_DM3
AJ9
SB_DQ38
AD4
SA_DQ62
AJ10
SB_DM4
AK9
SB_DQ39
AD5
SA_DQ63
AK5
SB_DM5
AJ7
SB_DQ40
AK36
SA_DQS0
AE7
SB_DM6
AK6
SB_DQ41
AK35
SA_DQS0#
AB7
SB_DM7
AJ4
SB_DQ42
AP33
SA_DQS1
AE31
SB_DQ0
AH5
SB_DQ43
AP34
SA_DQS1#
AE32
SB_DQ1
AK8
SB_DQ44
AN29
SA_DQS2
AG32
SB_DQ2
AJ8
SB_DQ45
AN30
SA_DQS2#
AG36
SB_DQ3
AJ5
SB_DQ46
AP23
SA_DQS3
AE34
SB_DQ4
AK4
SB_DQ47
AN23
SA_DQS3#
AE33
SB_DQ5
AG5
SB_DQ48
AM8
SA_DQS4
AF31
SB_DQ6
AG4
SB_DQ49
AN8
SA_DQS4#
AF30
SB_DQ7
AD8
SB_DQ50
AM4
SA_DQS5
AH33
SB_DQ8
AM5
SA_DQS5#
AD9
SB_DQ51
AH32
SB_DQ9
AJ1
SA_DQS6
AH4
SB_DQ52
AK31
SB_DQ10
AH1
SA_DQS6#
AG6
SB_DQ53
AG30
SB_DQ11
AE8
SB_DQ54
AG34
SB_DQ12
AD7
SB_DQ55
AG33
SB_DQ13
AC5
SB_DQ56
AH31
SB_DQ14
AB8
SB_DQ57
AJ31
SB_DQ15
AB6
SB_DQ58
AK30
SB_DQ16
AA8
SB_DQ59
AJ30
SB_DQ17
AC8
SB_DQ60
AH29
SB_DQ18
AC7
SB_DQ61
AH28
SB_DQ19
AA4
SB_DQ62
AK29
SB_DQ20
AA5
SB_DQ63
AH30
SB_DQ21
AF34
SB_DQS0
AH27
SB_DQ22
AF35
SB_DQS0#
AG28
SB_DQ23
AK32
SB_DQS1
AF24
SB_DQ24
AK33
SB_DQS1#
AG23
SB_DQ25
AJ28
SB_DQS2
AJ22
SB_DQ26
AK28
SB_DQS2#
AK22
SB_DQ27
AK23
SB_DQS3
AH24
SB_DQ28
AJ23
SB_DQS3#
AH23
SB_DQ29
AM10
SB_DQS4
AE5
SA_DQS7
AE4
SA_DQS7#
AL17
SA_MA0
AP17
SA_MA1
AP18
SA_MA2
AM17
SA_MA3
AN18
SA_MA4
AM18
SA_MA5
AL19
SA_MA6
AP20
SA_MA7
AM19
SA_MA8
AL20
SA_MA9
AM16
SA_MA10
AN20
SA_MA11
AM20
SA_MA12
AM15
SA_MA13
AP16
SA_RAS#
AF29
SA_RCVENIN#
AF28
332
SA_RCVENOUT#
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
AL10
SB_DQS4#
AM14
SM_CS1#
K28
VCC
AH6
SB_DQS5
AH15
SM_CS2#
K29
VCC
AH7
SB_DQS5#
AG16
SM_CS3#
L27
VCC
SB_DQS6
AP14
SM_ODT0
L28
VCC
AF7
SB_DQS6#
AL15
SM_ODT1
M27
VCC
AB4
SB_DQS7
AM11
SM_ODT2
M28
VCC
AN10
SM_ODT3
M29
VCC
AF22
SMOCDCOMP0
N27
VCC
AF16
SMOCDCOMP1
N28
VCC
AK10
SMRCOMPN
N29
VCC
AK11
SMRCOMPP
P27
VCC
AF37
SMVREF0
AF8
AB5
SB_DQS7#
AH17
SB_MA0
AK17
SB_MA1
AH18
SB_MA2
AJ18
SB_MA3
AK18
SB_MA4
AJ19
SB_MA5
AK19
AD1
SMVREF1
SB_MA6
AE27
SMXSLEWIN
AH19
SB_MA7
AE28
SMXSLEWOUT
AJ20
SB_MA8
AF9
SMYSLEWIN
AH20
SB_MA9
AF10
SMYSLEWOUT
AJ16
SB_MA10
F5
THRMTRIP#
AG18
SB_MA11
B15
TV_IRTNA
AG20
SB_MA12
B16
TV_IRTNB
AG15
SB_MA13
B17
TV_IRTNC
J18
TV_REFSET
A15
TVDAC_A
C16
TVDAC_B
A17
TVDAC_C
G28
VCC
H26
VCC
H27
VCC
H28
VCC
J25
VCC
J27
VCC
J28
VCC
J29
VCC
K17
VCC
K18
VCC
K19
VCC
K20
VCC
K21
VCC
K22
VCC
K23
VCC
K24
VCC
K25
VCC
K26
VCC
K27
VCC
AK14
SB_RAS#
AF15
SB_RCVENIN#
AF14
SB_RCVENOUT#
AH16
SB_WE#
H25
SDVOCTRL_CLK
H24
SDVOCTRL_DATA
AM33
SM_CK0
AN33
SM_CK0#
AL1
SM_CK1
AK1
SM_CK1#
AE11
RSVD28
AE10
RSVD29
AJ34
SM_CK3
AJ33
SM_CK3#
AF6
SM_CK4
AF5
SM_CK4#
AC10
RSVD30
AD10
RSVD31
AP21
SM_CKE0
AM21
SM_CKE1
AH21
SM_CKE2
AK21
SM_CKE3
AN16
SM_CS0#
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
P28
VCC
R27
VCC
R28
VCC
R29
VCC
T18
VCC
T20
VCC
T27
VCC
T28
VCC
T29
VCC
U19
VCC
U20
VCC
U27
VCC
U28
VCC
V18
VCC
V19
VCC
V27
VCC
V28
VCC
W18
VCC
W20
VCC
L17
VCC_NCTF
L18
VCC_NCTF
L19
VCC_NCTF
L20
VCC_NCTF
L21
VCC_NCTF
L22
VCC_NCTF
L23
VCC_NCTF
L24
VCC_NCTF
L25
VCC_NCTF
L26
VCC_NCTF
M17
VCC_NCTF
M18
VCC_NCTF
M19
VCC_NCTF
M20
VCC_NCTF
333
Ballout and Package Information
R
334
Ball
Signal
Ball
Signal
Ball
Signal
M21
VCC_NCTF
U24
M22
VCC_NCTF
U25
VCC_NCTF
F17
VCCA_TVDACA
VCC_NCTF
C18
M23
VCC_NCTF
VCCA_TVDACB
U26
VCC_NCTF
D18
M24
VCCA_TVDACB
VCC_NCTF
V17
VCC_NCTF
E18
VCCA_TVDACC
M25
VCC_NCTF
V21
VCC_NCTF
F18
VCCA_TVDACC
M26
VCC_NCTF
V22
VCC_NCTF
AC2
VCCD_HMPLL1
N17
VCC_NCTF
V23
VCC_NCTF
AC1
VCCD_HMPLL2
N18
VCC_NCTF
V24
VCC_NCTF
A25
VCCD_LVDS
N19
VCC_NCTF
V25
VCC_NCTF
B25
VCCD_LVDS
N20
VCC_NCTF
V26
VCC_NCTF
B26
VCCD_LVDS
N21
VCC_NCTF
W17
VCC_NCTF
D19
VCCD_TVDAC
N22
VCC_NCTF
W21
VCC_NCTF
H17
VCCDQ_TVDAC
N23
VCC_NCTF
W22
VCC_NCTF
A21
VCCHV
N24
VCC_NCTF
W23
VCC_NCTF
B21
VCCHV
N25
VCC_NCTF
W24
VCC_NCTF
B22
VCCHV
N26
VCC_NCTF
W25
VCC_NCTF
AB9
VCCSM
P17
VCC_NCTF
W26
VCC_NCTF
AB10
VCCSM
P18
VCC_NCTF
Y18
VCC_NCTF
AB11
VCCSM
P19
VCC_NCTF
Y19
VCC_NCTF
AC11
VCCSM
P20
VCC_NCTF
Y20
VCC_NCTF
AC27
VCCSM
P21
VCC_NCTF
H20
VCC_SYNC
AD11
VCCSM
P22
VCC_NCTF
AE37
VCC3G
AD27
VCCSM
P23
VCC_NCTF
J37
VCC3G
AD28
VCCSM
P24
VCC_NCTF
L37
VCC3G
AE1
VCCSM
P25
VCC_NCTF
N37
VCC3G
AE12
VCCSM
P26
VCC_NCTF
R37
VCC3G
AE13
VCCSM
R18
VCC_NCTF
U37
VCC3G
AE14
VCCSM
R19
VCC_NCTF
W37
VCC3G
AE15
VCCSM
R20
VCC_NCTF
F37
VCCA_3GBG
AE16
VCCSM
R22
VCC_NCTF
Y29
VCCA_3GPLL
AE17
VCCSM
R23
VCC_NCTF
Y27
VCCA_3GPLL
AE18
VCCSM
R24
VCC_NCTF
Y28
VCCA_3GPLL
AE19
VCCSM
R25
VCC_NCTF
E19
VCCA_CRTDAC
AE20
VCCSM
R26
VCC_NCTF
F19
VCCA_CRTDAC
AE21
VCCSM
T17
VCC_NCTF
B23
VCCA_DPLLA
AE22
VCCSM
T21
VCC_NCTF
C35
VCCA_DPLLB
AE23
VCCSM
T22
VCC_NCTF
AA1
VCCA_HPLL
AE24
VCCSM
T23
VCC_NCTF
A35
VCCA_LVDS
AE25
VCCSM
T24
VCC_NCTF
AA2
VCCA_MPLL
AE26
VCCSM
T25
VCC_NCTF
AF18
VCCA_SM
AF12
VCCSM
T26
VCC_NCTF
AF19
VCCA_SM
AF13
VCCSM
U17
VCC_NCTF
AF20
VCCA_SM
AF25
VCCSM
U21
VCC_NCTF
AP19
VCCA_SM
AF26
VCCSM
U22
VCC_NCTF
H18
VCCA_TVBG
AG12
VCCSM
U23
VCC_NCTF
E17
VCCA_TVDACA
AG13
VCCSM
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
AG25
VCCSM
AC19
VCCSM_NCTF
AA29
VSS
AG26
VCCSM
AC20
VCCSM_NCTF
AA30
VSS
AH12
VCCSM
AC21
VCCSM_NCTF
AA32
VSS
AH13
VCCSM
VCCSM_NCTF
AA34
VSS
AH25
VCCSM
AC23
VCCSM_NCTF
AA36
VSS
AH26
VCCSM
AC24
VCCSM_NCTF
AB3
VSS
AH37
VCCSM
VCCSM_NCTF
AB27
VSS
AJ12
VCCSM
AC26
VCCSM_NCTF
AB28
VSS
AJ13
VCCSM
VCCSM_NCTF
VSS
VCCSM
AD12
AB30
AJ25
AD13
VCCSM_NCTF
AB32
VSS
AJ26
VCCSM
AD14
VCCSM_NCTF
AB34
VSS
AK12
VCCSM
AD15
VCCSM_NCTF
AB36
VSS
AK13
VCCSM
AD16
VCCSM_NCTF
AC3
VSS
AD17
VCCSM_NCTF
AC6
VSS
AD18
VCCSM_NCTF
AD19
VCCSM_NCTF
AD20
VCCSM_NCTF
AD21
VCCSM_NCTF
AD22
VCCSM_NCTF
AD23
VCCSM_NCTF
AD24
VCCSM_NCTF
AD25
VCCSM_NCTF
AD26
VCCSM_NCTF
A27
VCCTX_LVDS
A28
VCCTX_LVDS
B28
VCCTX_LVDS
A3
VSS
A9
VSS
A14
VSS
A16
VSS
A18
VSS
A20
VSS
A22
VSS
A26
VSS
A29
VSS
A32
VSS
AA3
VSS
AA6
VSS
AA7
VSS
AA9
VSS
AA10
VSS
AK25
VCCSM
AK26
VCCSM
AL12
VCCSM
AL13
VCCSM
AL25
VCCSM
AL26
VCCSM
AM1
VCCSM
AM12
VCCSM
AM13
VCCSM
AM25
VCCSM
AM26
VCCSM
AM37
VCCSM
AN12
VCCSM
AN13
VCCSM
AN25
VCCSM
AN26
VCCSM
AP8
VCCSM
AP12
VCCSM
AP13
VCCSM
AP25
VCCSM
AP26
VCCSM
AP29
VCCSM
AB12
VCCSM_NCTF
AC22
AC25
AB13
VCCSM_NCTF
AC12
VCCSM_NCTF
AC13
VCCSM_NCTF
AC14
VCCSM_NCTF
AC15
VCCSM_NCTF
AC16
VCCSM_NCTF
AA11
VSS
AC17
VCCSM_NCTF
AA27
VSS
AC18
VCCSM_NCTF
AA28
VSS
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
AC9
VSS
AC28
VSS
AC30
VSS
AC32
VSS
AC34
VSS
AC36
VSS
AD2
VSS
AD29
VSS
AD31
VSS
AD32
VSS
AD33
VSS
AD34
VSS
AD36
VSS
AE2
VSS
AE6
VSS
AE9
VSS
AE30
VSS
AE35
VSS
AE36
VSS
AF4
VSS
AF11
VSS
AF17
VSS
AF21
VSS
AF23
VSS
AF27
VSS
AF33
VSS
AF36
VSS
AG7
VSS
AG11
VSS
AG14
VSS
AG19
VSS
335
Ballout and Package Information
R
336
Ball
Signal
Ball
Signal
Ball
Signal
AG24
VSS
AN27
VSS
E35
VSS
AG27
VSS
AN32
VSS
E37
VSS
AG29
VSS
AN34
VSS
F11
VSS
AG31
VSS
AN36
VSS
F14
VSS
AG37
VSS
AP5
VSS
F20
VSS
AH2
VSS
AP30
VSS
F21
VSS
AH9
VSS
B6
VSS
F24
VSS
AH22
VSS
B12
VSS
F29
VSS
AH34
VSS
B14
VSS
F31
VSS
AJ3
VSS
B18
VSS
F33
VSS
AJ6
VSS
B24
VSS
F35
VSS
AJ11
VSS
B27
VSS
G2
VSS
AJ14
VSS
B35
VSS
G7
VSS
AJ17
VSS
C3
VSS
G17
VSS
AJ24
VSS
C4
VSS
G20
VSS
AJ27
VSS
C8
VSS
G26
VSS
AJ29
VSS
C15
VSS
G27
VSS
AJ32
VSS
C17
VSS
G29
VSS
AJ36
VSS
C19
VSS
G31
VSS
AK7
VSS
C21
VSS
G33
VSS
AK20
VSS
C30
VSS
G35
VSS
AL2
VSS
C32
VSS
H4
VSS
AL5
VSS
C34
VSS
H9
VSS
AL8
VSS
C36
VSS
H11
VSS
AL11
VSS
D2
VSS
H16
VSS
AL14
VSS
D10
VSS
H19
VSS
AL16
VSS
D12
VSS
H23
VSS
AL18
VSS
D16
VSS
H29
VSS
AL22
VSS
D20
VSS
H31
VSS
AL24
VSS
D22
VSS
H33
VSS
AL27
VSS
D24
VSS
H35
VSS
AL31
VSS
D29
VSS
H37
VSS
AL33
VSS
D31
VSS
J2
VSS
AL36
VSS
D33
VSS
J6
VSS
AM29
VSS
D35
VSS
J12
VSS
AN2
VSS
E5
VSS
J14
VSS
AN4
VSS
E8
VSS
J19
VSS
AN7
VSS
E20
VSS
J22
VSS
AN9
VSS
E22
VSS
J24
VSS
AN11
VSS
E26
VSS
J26
VSS
AN14
VSS
E27
VSS
J31
VSS
AN17
VSS
E28
VSS
J33
VSS
AN19
VSS
E29
VSS
J35
VSS
AN21
VSS
E31
VSS
K9
VSS
AN24
VSS
E33
VSS
K14
VSS
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
K15
VSS
U31
VSS
AA24
VSS_NCTF
K16
VSS
U33
VSS
AA25
VSS_NCTF
K31
VSS
U35
VSS
AA26
VSS_NCTF
K33
VSS
V2
VSS
AB14
VSS_NCTF
K35
VSS
V7
VSS
AB15
VSS_NCTF
K37
VSS
V9
VSS
AB16
VSS_NCTF
L2
VSS
V20
VSS
AB17
VSS_NCTF
L4
VSS
V29
VSS
AB18
VSS_NCTF
L6
VSS
V31
VSS
AB19
VSS_NCTF
L8
VSS
V33
VSS
AB20
VSS_NCTF
L10
VSS
V35
VSS
AB21
VSS_NCTF
L29
VSS
V37
VSS
AB22
VSS_NCTF
L31
VSS
W5
VSS
AB23
VSS_NCTF
L33
VSS
W19
VSS
AB24
VSS_NCTF
L35
VSS
W27
VSS
AB25
VSS_NCTF
M31
VSS
W28
VSS
AB26
VSS_NCTF
M33
VSS
W29
VSS
L14
VSS_NCTF
M35
VSS
W31
VSS
L15
VSS_NCTF
M37
VSS
W33
VSS
L16
VSS_NCTF
N31
VSS
W35
VSS
M14
VSS_NCTF
N33
VSS
Y1
VSS
M15
VSS_NCTF
N35
VSS
Y4
VSS
M16
VSS_NCTF
P2
VSS
Y8
VSS
N14
VSS_NCTF
P4
VSS
Y10
VSS
N15
VSS_NCTF
P6
VSS
Y11
VSS
N16
VSS_NCTF
P8
VSS
Y30
VSS
P14
VSS_NCTF
P29
VSS
Y32
VSS
P15
VSS_NCTF
P31
VSS
Y35
VSS
P16
VSS_NCTF
P33
VSS
Y37
VSS
R14
VSS_NCTF
P35
VSS
G37
VSSA_3GBG
R15
VSS_NCTF
P37
VSS
G19
VSSA_CRTDAC
R16
VSS_NCTF
R31
VSS
B36
VSSA_LVDS
R17
VSS_NCTF
R33
VSS
G18
VSSA_TVBG
R21
VSS_NCTF
R35
VSS
AA12
VSS_NCTF
T14
VSS_NCTF
T2
VSS
AA13
VSS_NCTF
T15
VSS_NCTF
T6
VSS
AA14
VSS_NCTF
T16
VSS_NCTF
T9
VSS
AA15
VSS_NCTF
U14
VSS_NCTF
T19
VSS
AA16
VSS_NCTF
U15
VSS_NCTF
T31
VSS
AA17
VSS_NCTF
U16
VSS_NCTF
T33
VSS
AA18
VSS_NCTF
T35
VSS
AA19
VSS_NCTF
V14
VSS_NCTF
T37
VSS
AA20
VSS_NCTF
V15
VSS_NCTF
U4
VSS
AA21
VSS_NCTF
U18
VSS
AA22
VSS_NCTF
U29
VSS
AA23
VSS_NCTF
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
V16
VSS_NCTF
W14
VSS_NCTF
W15
VSS_NCTF
W16
VSS_NCTF
337
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
Y12
VSS_NCTF
M4
VTT
U10
VTT
Y13
VSS_NCTF
M5
VTT
U11
VTT
Y14
VSS_NCTF
M6
VTT
V1
VTT
Y15
VSS_NCTF
M7
VTT
V10
VTT
Y16
VSS_NCTF
M8
VTT
V11
VTT
Y17
VSS_NCTF
M9
VTT
W9
VTT
Y21
VSS_NCTF
M10
VTT
W10
VTT
Y22
VSS_NCTF
M11
VTT
W11
VTT
Y23
VSS_NCTF
N1
VTT
Y9
VTT
VTT_NCTF
Y24
VSS_NCTF
N2
VTT
L12
Y25
VSS_NCTF
N3
VTT
L13
VTT_NCTF
Y26
VSS_NCTF
N4
VTT
M12
VTT_NCTF
VSYNC
N5
VTT
M13
VTT_NCTF
VTT_NCTF
H21
338
A6
VTT
N6
VTT
N12
B2
VTT
N7
VTT
N13
VTT_NCTF
G1
VTT
N8
VTT
P12
VTT_NCTF
J9
VTT
N9
VTT
P13
VTT_NCTF
J10
VTT
N10
VTT
R12
VTT_NCTF
J13
VTT
N11
VTT
R13
VTT_NCTF
K10
VTT
P9
VTT
T12
VTT_NCTF
K11
VTT
P10
VTT
T13
VTT_NCTF
K12
VTT
P11
VTT
U12
VTT_NCTF
K13
VTT
R9
VTT
L9
VTT
R10
VTT
L11
VTT
R11
VTT
M1
VTT
T10
VTT
M2
VTT
T11
VTT
M3
VTT
U9
VTT
U13
VTT_NCTF
V12
VTT_NCTF
V13
VTT_NCTF
W12
VTT_NCTF
W13
VTT_NCTF
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
13.2.1
GMCH Numerical Order Ball List
Table 13-33 applies to the Mobile Intel 915GM/GME/PM and Intel 910GML/GMLE Express Chipset ball-out. Some
signals may be RESERVED depending on chipset configuration used. Please refer to the signal description chapter for
more details.
Table 13-33. GMCH Numerical Order Ball List
Ball
Signal
Ball
Signal
Ball
Signal
A2
NC8
A3
VSS
AA1
VCCA_HPLL
AB1
HCLKN
AA2
VCCA_MPLL
AB2
HCLKP
VSS
A4
HRS0#
AA3
VSS
AB3
A5
HBNR#
AA4
SB_DQ62
AB4
SB_DQS7
A6
VTT
AA5
SB_DQ63
AB5
SB_DQS7#
A7
HREQ0#
AA6
VSS
AB6
SB_DQ58
A8
HREQ4#
AA7
VSS
AB7
SB_DM7
SB_DQ59
AB8
SB_DQ57
A9
VSS
AA8
A10
HA7#
AA9
VSS
AB9
VCCSM
A11
RSVD33
AA10
VSS
AB10
VCCSM
HA23#
AA11
VSS
AB11
VCCSM
HA30#
AA12
VSS_NCTF
AB12
VCCSM_NCTF
A14
VSS
AA13
VSS_NCTF
AB13
VCCSM_NCTF
A15
TVDAC_A
AA14
VSS_NCTF
AB14
VSS_NCTF
VSS
AA15
VSS_NCTF
AB15
VSS_NCTF
VSS_NCTF
A12
A13
A16
A17
TVDAC_C
AA16
VSS_NCTF
AB16
A18
VSS
AA17
VSS_NCTF
AB17
VSS_NCTF
RED
AA18
VSS_NCTF
AB18
VSS_NCTF
A20
VSS
AA19
VSS_NCTF
AB19
VSS_NCTF
A21
VCCHV
AA20
VSS_NCTF
AB20
VSS_NCTF
VSS
AA21
VSS_NCTF
AB21
VSS_NCTF
VSS_NCTF
A19
A22
A23
DREF_CLKP
AA22
VSS_NCTF
AB22
A24
DREF_CLKN
AA23
VSS_NCTF
AB23
VSS_NCTF
VCCD_LVDS
AA24
VSS_NCTF
AB24
VSS_NCTF
VSS_NCTF
A25
A26
VSS
AA25
VSS_NCTF
AB25
A27
VCCTX_LVDS
AA26
VSS_NCTF
AB26
VSS_NCTF
VCCTX_LVDS
AA27
VSS
AB27
VSS
VSS
AB28
VSS
GCLKN
A28
A29
VSS
AA28
RSVD25
AA29
VSS
AB29
RSVD24
AA30
VSS
AB30
VSS
VSS
AA31
DMI_RXN0
AB31
DMI_RXP2
LADATAP1
AA32
VSS
AB32
VSS
A34
LADATAP0
AA33
DMI_TXN0
AB33
DMI_TXP2
A35
VCCA_LVDS
AA34
VSS
AB34
VSS
A36
NC10
AA35
DMI_RXP1
AB35
DMI_RXN1
A37
NC11
AA36
VSS
AB36
VSS
AA37
DMI_TXP1
A30
A31
A32
A33
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
339
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
AB37
DMI_TXN1
AD8
SB_DQ50
AE16
VCCSM
AC1
VCCD_HMPLL2
AD9
SB_DQ51
AE17
VCCSM
AC2
VCCD_HMPLL1
AD10
RSVD31
AE18
VCCSM
AC3
VSS
AD11
VCCSM
AE19
VCCSM
AC4
SA_DQ59
AD12
VCCSM_NCTF
AE20
VCCSM
AC5
SB_DQ56
AD13
VCCSM_NCTF
AE21
VCCSM
VSS
AD14
VCCSM_NCTF
AE22
VCCSM
AC7
SB_DQ61
AD15
VCCSM_NCTF
AE23
VCCSM
AC8
SB_DQ60
AD16
VCCSM_NCTF
AE24
VCCSM
VSS
AD17
VCCSM_NCTF
AE25
VCCSM
RSVD30
AD18
VCCSM_NCTF
AE26
VCCSM
AC11
VCCSM
AD19
VCCSM_NCTF
AE27
SMXSLEWIN
AC12
VCCSM_NCTF
AD20
VCCSM_NCTF
AE28
SMXSLEWOUT
AC13
VCCSM_NCTF
AD21
VCCSM_NCTF
AE29
RSTIN#
AC14
VCCSM_NCTF
AD22
VCCSM_NCTF
AE30
VSS
AC15
VCCSM_NCTF
AD23
VCCSM_NCTF
AE31
SB_DQ0
AC16
VCCSM_NCTF
AD24
VCCSM_NCTF
AE32
SB_DQ1
AC17
VCCSM_NCTF
AD25
VCCSM_NCTF
AE33
SB_DQ5
VCCSM_NCTF
AD26
VCCSM_NCTF
AE34
SB_DQ4
AC19
VCCSM_NCTF
AD27
VCCSM
AE35
VSS
AC20
VCCSM_NCTF
AD28
VCCSM
AE36
VSS
AC21
VCCSM_NCTF
AD29
VSS
AE37
VCC3G
AC22
VCCSM_NCTF
AD30
PWROK
VCCSM_NCTF
VSS
SA_DQ61
AC23
AD31
AF1
VSS
SA_DQ60
VCCSM_NCTF
AD32
AF2
AC24
VCCSM_NCTF
VSS
SA_DQ56
AC25
AD33
AF3
AC26
VCCSM_NCTF
AD34
VSS
AC27
VCCSM
AD35
DMI_RXN3
AD36
VSS
AC6
AC9
AC10
AC18
340
AC28
VSS
AC29
GCLKP
AC30
VSS
AC31
DMI_RXN2
AC32
VSS
AC33
DMI_TXN2
AC34
VSS
AC35
DMI_RXP3
AC36
VSS
AC37
DMI_TXP3
AD1
SMVREF1
AD2
VSS
AD3
SA_DM7
AD4
SA_DQ62
AD5
SA_DQ63
AD6
SA_DQ58
AD7
SB_DQ55
AF4
VSS
AF5
SM_CK4#
AF6
SM_CK4
AF7
SB_DQS6#
AD37
DMI_TXN3
AE1
VCCSM
AF8
SB_DQS6
AE2
VSS
AF9
SMYSLEWIN
AE3
SA_DQ57
AF10
SMYSLEWOUT
AE4
SA_DQS7#
AF11
VSS
AE5
SA_DQS7
AF12
VCCSM
AE6
VSS
AF13
VCCSM
AE7
SB_DM6
AF14
SB_RCVENOUT#
AE8
SB_DQ54
AF15
SB_RCVENIN#
AE9
VSS
AF16
SMOCDCOMP1
AE10
RSVD29
AF17
VSS
AE11
RSVD28
AF18
VCCA_SM
AE12
VCCSM
AF19
VCCA_SM
AE13
VCCSM
AF20
VCCA_SM
AE14
VCCSM
AF21
VSS
AE15
VCCSM
AF22
SMOCDCOMP0
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
AF23
VSS
AG30
SB_DQ11
AH37
VCCSM
AF24
SB_DQ24
AG31
VSS
AJ1
SA_DQS6
AF25
VCCSM
AG32
SB_DQ2
AJ2
SA_DM6
AF26
VCCSM
AG33
SB_DQ13
AJ3
VSS
AF27
VSS
AG34
SB_DQ12
SA_DQ0
SB_DQ42
SA_RCVENOUT#
AG35
AJ4
AF28
SA_RCVENIN#
SB_DQ3
SB_DQ46
AF29
AG36
AJ5
AF30
SB_DQ7
AG37
VSS
AF31
SB_DQ6
AH1
SA_DQS6#
AF32
SB_DM0
AH2
VSS
AF33
VSS
AH3
SA_DQ54
AF34
SB_DQS0
AH4
AF35
SB_DQS0#
AF36
VSS
AF37
SMVREF0
AG1
SA_DQ51
AG2
SA_DQ50
AG3
SA_DQ55
AG4
SB_DQ49
AG5
SB_DQ48
AG6
SB_DQ53
AG7
VSS
AG8
SB_DQ34
AG9
SB_DQ33
AG10
SB_DQ32
AG11
VSS
AG12
VCCSM
AG13
VCCSM
AG14
VSS
AG15
SB_MA13
AG16
SM_CS3#
AG17
SB_BS1
AG18
SB_MA11
AG19
VSS
AG20
SB_MA12
AG21
SB_BS2
AG22
SB_DQ30
AG23
SB_DQ25
AJ6
VSS
AJ7
SB_DQ40
AJ8
SB_DQ45
AJ9
SB_DQ38
SB_DQ52
AJ10
SB_DM4
AH5
SB_DQ43
AJ11
VSS
AH6
SB_DQS5
AJ12
VCCSM
SB_DQS5#
AJ13
VCCSM
AH8
SB_DQ35
AJ14
VSS
AH9
VSS
AJ15
SB_BS0
AH10
SB_DQ37
AJ16
SB_MA10
AH11
SB_DQ36
AJ17
VSS
AH12
VCCSM
AJ18
SB_MA3
AH13
VCCSM
AJ19
SB_MA5
AH14
SB_CAS#
AJ20
SB_MA8
AH15
SM_CS2#
AJ21
SB_DQ31
AH16
SB_WE#
AJ22
SB_DQ26
AH17
SB_MA0
AJ23
SB_DQS3#
AH18
SB_MA2
AJ24
VSS
AH19
SB_MA7
AJ25
VCCSM
AH20
SB_MA9
AJ26
VCCSM
AH21
SM_CKE2
AJ27
VSS
AH22
VSS
AJ28
SB_DQS2
AH23
SB_DQ29
AJ29
VSS
AH24
SB_DQ28
AJ30
SB_DQ17
AH25
VCCSM
AJ31
SB_DQ15
AH26
VCCSM
AJ32
VSS
AH27
SB_DQ22
AH28
SB_DQ19
AJ33
SM_CK3#
AH29
SB_DQ18
AJ34
SM_CK3
AH30
SB_DQ21
AJ35
SA_DQ5
AH31
SB_DQ14
AJ36
VSS
AH32
SB_DQ9
AH7
AG24
VSS
AG25
VCCSM
AG26
VCCSM
AH33
SB_DQ8
AG27
VSS
AH34
VSS
AG28
SB_DQ23
AH35
AG29
VSS
AH36
AJ37
SA_DM0
AK1
SM_CK1#
AK2
SA_DQ48
AK3
SA_DQ49
SA_DQ1
AK4
SB_DQ47
SA_DQ4
AK5
SB_DM5
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
341
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
AK6
SB_DQ41
AL13
VCCSM
AM19
SA_MA8
AK7
VSS
AL14
VSS
AM20
SA_MA12
AK8
SB_DQ44
AL15
SM_ODT1
AM21
SM_CKE1
AK9
SB_DQ39
AL16
VSS
AM22
SA_DQ27
AK10
SMRCOMPN
AL17
SA_MA0
AM23
SA_DQ26
AK11
SMRCOMPP
AL18
VSS
AM24
SA_DQ29
AK12
VCCSM
AL19
SA_MA6
AM25
VCCSM
AK13
VCCSM
AL20
SA_MA9
AM26
VCCSM
AK14
SB_RAS#
AL21
SA_BS2
AM27
SA_DQ25
AK15
SA_BS0
AL22
VSS
AM28
SA_DQ22
AK16
SA_BS1
AL23
SA_DQ28
AM29
VSS
AK17
SB_MA1
AL24
VSS
AM30
SA_DQ21
AK18
SB_MA4
AL25
VCCSM
AM31
SA_DQ11
AK19
SB_MA6
AL26
VCCSM
AM32
SA_DQ15
AK20
VSS
AL27
VSS
AM33
SM_CK0
AK21
SM_CKE3
AL28
SA_DQ23
AM34
SA_DQ12
AK22
SB_DQ27
AL29
SA_DM2
AM35
SA_DQ13
AK23
SB_DQS3
AL30
SA_DQ20
AM36
SA_DQ8
AK24
SB_DM3
AL31
VSS
AM37
VCCSM
AK25
VCCSM
AL32
SA_DQ14
AN1
NC6
AK26
VCCSM
AL33
VSS
VSS
AK27
SB_DM2
AN2
AL34
SA_DQ7
AK28
SB_DQS2#
AN3
SA_DQ42
AL35
SA_DQ2
AK29
SB_DQ20
AN4
VSS
AL36
VSS
AK30
SB_DQ16
AN5
SA_DQ40
AL37
SA_DQ3
AK31
SB_DQ10
AN6
SA_DQ41
AK32
SB_DQS1
AM1
VCCSM
AN7
VSS
AK33
SB_DQS1#
AM2
SA_DQ53
AN8
SA_DQS4#
AK34
SB_DM1
AM3
SA_DQ47
AN9
VSS
AK35
SA_DQS0#
AM4
SA_DQS5
AN10
SM_ODT3
AK36
SA_DQS0
AM5
SA_DQS5#
AN11
VSS
AM6
SA_DQ45
AN12
VCCSM
AM7
SA_DQ39
AN13
VCCSM
AM8
SA_DQS4
AN14
VSS
AM9
SA_DQ32
AN15
SA_CAS#
AM10
SB_DQS4
AN16
SM_CS0#
AM11
SM_ODT2
AN17
VSS
AM12
VCCSM
AN18
SA_MA4
AM13
VCCSM
AN19
VSS
AM14
SM_CS1#
AN20
SA_MA11
AM15
SA_MA13
AN21
VSS
AM16
SA_MA10
AN22
SA_DQ30
AM17
SA_MA3
AN23
SA_DQS3#
AM18
SA_MA5
AN24
VSS
AK37
SA_DQ6
AL1
SM_CK1
AL2
VSS
AL3
SA_DQ52
AL4
SA_DQ46
AL5
VSS
AL6
SA_DQ34
AL7
SA_DQ38
AL8
VSS
AL9
SA_DQ33
AL10
SB_DQS4#
AL11
VSS
AL12
342
VCCSM
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
AN25
VCCSM
AP32
SA_DQ10
C2
HXSCOMP
C3
VSS
AN26
VCCSM
AP33
SA_DQS1
AN27
VSS
AP34
SA_DQS1#
C4
VSS
AN28
SA_DQ18
AP35
SA_DM1
C5
HRS1#
AN29
SA_DQS2
AP36
NC3
C6
HDBSY#
AN30
SA_DQS2#
AP37
NC1
C7
HREQ3#
AN31
SA_DQ16
B1
NC7
C8
VSS
B2
VTT
C9
HA4#
B3
HLOCK#
C10
HA18#
HRS2#
C11
HA19#
B5
HTRDY#
C12
HA21#
B6
VSS
C13
HA27#
C14
CFG14
C15
VSS
C16
TVDAC_B
C17
VSS
C18
VCCA_TVDACB
C19
VSS
C20
GREEN
C21
VSS
C22
LCTLB_DATA
C23
LCTLA_CLK
C24
LBCLKP
AN32
VSS
AN33
SM_CK0#
AN34
VSS
AN35
SA_DQ9
AN36
VSS
AN37
NC2
AP1
B4
B7
HA6#
NC5
B8
HREQ2#
AP2
NC4
B9
HADSTB0#
AP3
SA_DQ43
B10
HA10#
AP4
SA_DM5
B11
HA28#
AP5
VSS
B12
VSS
AP6
SA_DQ44
B13
HA22#
AP7
SA_DQ35
B14
VSS
AP8
VCCSM
B15
TV_IRTNA
B16
TV_IRTNB
B17
TV_IRTNC
B18
VSS
B19
RED#
B20
GREEN#
B21
VCCHV
AP9
SA_DM4
AP10
SA_DQ37
AP11
SA_DQ36
AP12
VCCSM
AP13
VCCSM
AP14
SM_ODT0
AP15
SA_WE#
AP16
SA_RAS#
AP17
SA_MA1
AP18
SA_MA2
AP19
VCCA_SM
AP20
SA_MA7
AP21
SM_CKE0
AP22
SA_DQ31
AP23
SA_DQS3
AP24
SA_DM3
AP25
VCCSM
AP26
VCCSM
AP27
SA_DQ24
AP28
SA_DQ19
AP29
VCCSM
AP30
VSS
AP31
SA_DQ17
B22
VCCHV
B23
VCCA_DPLLA
B24
VSS
B25
VCCD_LVDS
B26
VCCD_LVDS
B27
VSS
B28
VCCTX_LVDS
B29
LACLKP
B30
LACLKN
B31
LADATAP2
B32
LADATAN2
B33
LADATAN1
B34
LADATAN0
B35
VSS
B36
VSSA_LVDS
B37
NC9
C1
HXRCOMP
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
C25
LBCLKN
C26
LBDATAP2
C27
LBDATAN2
C28
LBDATAP0
C29
LBDATAN0
C30
VSS
C31
LVBG
C32
VSS
C33
LIBG
C34
VSS
C35
VCCA_DPLLB
C36
VSS
C37
DREF_SSCLKN
D1
HXSWING
D2
VSS
D3
HD7#
D4
HHIT#
D5
HBPRI#
D6
HHITM#
D7
HREQ1#
D8
HA9#
343
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
D9
HA13#
E17
VCCA_TVDACA
F25
LBKLT_EN
D10
VSS
E18
VCCA_TVDACC
F26
LVDD_EN
D11
HA20#
E19
VCCA_CRTDAC
F27
LVREFL
D12
VSS
E20
VSS
F28
LVREFH
D13
HA29#
E21
BLUE
F29
VSS
D14
CFG11
E22
VSS
F30
EXP_RXP2
D15
CFG9
E23
DDCDATA
F31
VSS
D16
VSS
E24
DDCCLK
F32
EXP_TXP2
D17
CFG7
E25
LBKLT_CRTL
F33
VSS
D18
VCCA_TVDACB
E26
VSS
F34
EXP_RXN1
D19
VCCD_TVDAC
E27
VSS
F35
VSS
D20
VSS
E28
VSS
F36
EXP_TXN1
D21
BLUE#
E29
VSS
F37
VCCA_3GBG
D22
VSS
E30
EXP_RXN0
G1
VTT
D23
CFG20
E31
VSS
G2
VSS
D24
VSS
E32
EXP_TXN0
G3
HD21#
D25
RSVD27
E33
VSS
G4
HDSTBN0#
D26
RSVD26
E34
EXP_RXP1
G5
HDSTBP0#
D27
LBDATAP1
E35
VSS
G6
HDPWR#
D28
LBDATAN1
E36
EXP_TXP1
G7
VSS
D29
VSS
E37
VSS
G8
HCPUSLP#
D30
EXP_RXP0
F1
HD5#
G9
HA3#
D31
VSS
F2
HD9#
G10
HA12#
D32
EXP_TXP0
F3
HD13#
G11
HA16#
D33
VSS
F4
HD2#
G12
HA25#
D34
EXP_ICOMPO
F5
THRMTRIP#
G13
HA17#
D35
VSS
F6
RSVD32
G14
CFG2
D36
EXP_COMPI
F7
HDRDY#
G15
CFG5
D37
DREF_SSCLKP
F8
HADS#
G16
CFG0
E1
HD1#
F9
HA8#
G17
VSS
E2
HD4#
F10
HA15#
G18
VSSA_TVBG
E3
HD6#
F11
VSS
G19
VSSA_CRTDAC
E4
HD0#
F12
HA24#
G20
VSS
E5
VSS
F13
HA31#
G21
HSYNC
E6
HDEFER#
F14
VSS
G22
CFG18
E7
HBREQ0#
F15
CFG4
G23
CFG19
E8
VSS
F16
CFG3
G24
RSVD22
E9
HA5#
F17
VCCA_TVDACA
G25
RSVD21
E10
HA11#
F18
VCCA_TVDACC
G26
VSS
HA14#
F19
VCCA_CRTDAC
G27
VSS
E12
HA26#
F20
VSS
G28
VCC
E13
HADSTB1#
F21
VSS
G29
VSS
E14
CFG12
F22
LDDC_DATA
G30
EXP_RXN2
E15
CFG10
F23
LDDC_CLK
G31
VSS
E16
CFG6
F24
VSS
G32
EXP_TXN2
E11
344
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
G33
VSS
J3
HD29#
K10
VTT
G34
EXP_RXP3
J4
HD20#
K11
VTT
G35
VSS
J5
HD26#
K12
VTT
G36
EXP_TXP3
VSS
K13
VTT
G37
VSSA_3GBG
J7
HD10#
K14
VSS
H1
HD16#
J8
HD11#
K15
VSS
H2
HD17#
VTT
K16
VSS
H3
HD22#
J10
VTT
K17
VCC
H4
VSS
J11
VCC
HD15#
HVREF
K18
H5
J12
VSS
K19
VCC
K20
VCC
K21
VCC
K22
VCC
K23
VCC
K24
VCC
K25
VCC
K26
VCC
K27
VCC
K28
VCC
J6
J9
H6
HD12#
J13
VTT
H7
HD3#
J14
VSS
J15
CFG16
J16
CFG8
J17
RSVD23
J18
TV_REFSET
J19
VSS
J20
REFSET
J21
EXT_TS0#
J22
VSS
J23
BM_BUSY#
J24
VSS
J25
VCC
J26
VSS
J27
VCC
J28
VCC
H8
HDINV0#
H9
VSS
H10
HCPURST#
H11
VSS
H12
CFG13
H13
CFG1
H14
CFG17
H15
CFG15
H16
VSS
H17
VCCDQ_TVDAC
H18
VCCA_TVBG
H19
VSS
H20
VCC_SYNC
H21
VSYNC
H22
EXT_TS1#
H23
VSS
H24
SDVOCTRL_DATA
H25
SDVOCTRL_CLK
H26
VCC
H27
VCC
H28
VCC
H29
VSS
H30
EXP_RXP4
H31
VSS
H32
EXP_TXP4
H33
VSS
H34
EXP_RXN3
H35
VSS
H36
EXP_TXN3
J29
VCC
J30
EXP_RXN4
J31
VSS
J32
EXP_TXN4
J33
VSS
J34
EXP_RXP5
J35
VSS
J36
EXP_TXP5
J37
VCC3G
K1
HDSTBN1#
K2
HDSTBP1#
K3
HDINV1#
K4
HD25#
K5
HD18#
K6
HD19#
H37
VSS
K7
HD8#
J1
HD23#
K8
HD14#
J2
VSS
K9
VSS
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
K29
VCC
K30
EXP_RXP6
K31
VSS
K32
EXP_TXP6
K33
VSS
K34
EXP_RXN5
K35
VSS
K36
EXP_TXN5
K37
VSS
L1
HYSCOMP
L2
VSS
L3
HD31#
L4
VSS
L5
HD24#
L6
VSS
L7
HD28#
L8
VSS
L9
VTT
L10
VSS
L11
VTT
L12
VTT_NCTF
L13
VTT_NCTF
L14
VSS_NCTF
L15
VSS_NCTF
L16
VSS_NCTF
L17
VCC_NCTF
345
Ballout and Package Information
R
346
Ball
Signal
Ball
Signal
Ball
Signal
L18
VCC_NCTF
M26
VCC_NCTF
N34
EXP_RXP9
L19
VCC_NCTF
M27
VCC
N35
VSS
L20
VCC_NCTF
M28
VCC
N36
EXP_TXP9
L21
VCC_NCTF
M29
VCC
N37
VCC3G
L22
VCC_NCTF
M30
EXP_RXP8
P1
HYSWING
L23
VCC_NCTF
M31
VSS
P2
VSS
L24
VCC_NCTF
M32
EXP_TXP8
P3
HD36#
L25
VCC_NCTF
M33
VSS
P4
VSS
L26
VCC_NCTF
M34
EXP_RXN7
P5
HD30#
L27
VCC
M35
VSS
P6
VSS
L28
VCC
M36
EXP_TXN7
P7
HD27#
L29
VSS
M37
VSS
P8
VSS
L30
EXP_RXN6
N1
VTT
P9
VTT
L31
VSS
N2
VTT
P10
VTT
L32
EXP_TXN6
N3
VTT
P11
VTT
L33
VSS
N4
VTT
P12
VTT_NCTF
L34
EXP_RXP7
N5
VTT
P13
VTT_NCTF
L35
VSS
N6
VTT
P14
VSS_NCTF
L36
EXP_TXP7
N7
VTT
P15
VSS_NCTF
L37
VCC3G
N8
VTT
P16
VSS_NCTF
M1
VTT
N9
VTT
P17
VCC_NCTF
M2
VTT
N10
VTT
P18
VCC_NCTF
M3
VTT
N11
VTT
P19
VCC_NCTF
M4
VTT
N12
VTT_NCTF
P20
VCC_NCTF
M5
VTT
N13
VTT_NCTF
P21
VCC_NCTF
M6
VTT
N14
VSS_NCTF
P22
VCC_NCTF
M7
VTT
N15
VSS_NCTF
P23
VCC_NCTF
M8
VTT
N16
VSS_NCTF
P24
VCC_NCTF
M9
VTT
N17
VCC_NCTF
P25
VCC_NCTF
M10
VTT
N18
VCC_NCTF
P26
VCC_NCTF
M11
VTT
N19
VCC_NCTF
P27
VCC
M12
VTT_NCTF
N20
VCC_NCTF
P28
VCC
M13
VTT_NCTF
N21
VCC_NCTF
P29
VSS
M14
VSS_NCTF
N22
VCC_NCTF
P30
EXP_RXP10
M15
VSS_NCTF
N23
VCC_NCTF
P31
VSS
M16
VSS_NCTF
N24
VCC_NCTF
P32
EXP_TXP10
M17
VCC_NCTF
N25
VCC_NCTF
P33
VSS
M18
VCC_NCTF
N26
VCC_NCTF
P34
EXP_RXN9
M19
VCC_NCTF
N27
VCC
P35
VSS
M20
VCC_NCTF
N28
VCC
P36
EXP_TXN9
M21
VCC_NCTF
N29
VCC
P37
VSS
M22
VCC_NCTF
N30
EXP_RXN8
R1
HD44#
M23
VCC_NCTF
N31
VSS
R2
HDSTBP2#
M24
VCC_NCTF
N32
EXP_TXN8
R3
HDSTBN2#
M25
VCC_NCTF
N33
VSS
R4
HD41#
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
R5
Signal
Ball
Signal
HD35#
T13
VTT_NCTF
U21
VCC_NCTF
R6
HD34#
T14
VSS_NCTF
U22
VCC_NCTF
R7
HD38#
T15
VSS_NCTF
U23
VCC_NCTF
R8
HD39#
T16
VSS_NCTF
U24
VCC_NCTF
R9
VTT
T17
VCC_NCTF
U25
VCC_NCTF
R10
VTT
T18
VCC
U26
VCC_NCTF
R11
VTT
T19
VSS
U27
VCC
R12
VTT_NCTF
T20
VCC
U28
VCC
R13
VTT_NCTF
T21
VCC_NCTF
U29
VSS
R14
VSS_NCTF
T22
VCC_NCTF
U30
EXP_RXN12
R15
VSS_NCTF
T23
VCC_NCTF
U31
VSS
R16
VSS_NCTF
T24
VCC_NCTF
U32
EXP_TXN12
R17
VSS_NCTF
T25
VCC_NCTF
U33
VSS
R18
VCC_NCTF
T26
VCC_NCTF
U34
EXP_RXP13
R19
VCC_NCTF
T27
VCC
U35
VSS
R20
VCC_NCTF
T28
VCC
U36
EXP_TXP13
R21
VSS_NCTF
T29
VCC
U37
VCC3G
R22
VCC_NCTF
T30
EXP_RXP12
V1
VTT
R23
VCC_NCTF
T31
VSS
V2
VSS
R24
VCC_NCTF
T32
EXP_TXP12
V3
HDSTBN3#
R25
VCC_NCTF
T33
VSS
V4
HD57#
R26
VCC_NCTF
T34
EXP_RXN11
V5
HD50#
R27
VCC
T35
VSS
V6
HD33#
R28
VCC
T36
EXP_TXN11
V7
VSS
R29
VCC
T37
VSS
V8
HD46#
R30
EXP_RXN10
U1
HD54#
V9
VSS
R31
VSS
U2
HD53#
V10
VTT
R32
EXP_TXN10
U3
HD49#
V11
VTT
R33
VSS
U4
VSS
V12
VTT_NCTF
R34
EXP_RXP11
U5
HDINV3#
V13
VTT_NCTF
R35
VSS
U6
HD47#
V14
VSS_NCTF
R36
EXP_TXP11
U7
HD32#
V15
VSS_NCTF
R37
VCC3G
U8
HD40#
V16
VSS_NCTF
T1
HYRCOMP
U9
VTT
V17
VCC_NCTF
T2
VSS
U10
VTT
V18
VCC
T3
HD45#
U11
VTT
V19
VCC
T4
HD42#
U12
VTT_NCTF
V20
VSS
T5
HD43#
U13
VTT_NCTF
V21
VCC_NCTF
T6
V22
VCC_NCTF
V23
VCC_NCTF
V24
VCC_NCTF
V25
VCC_NCTF
V26
VCC_NCTF
V27
VCC
V28
VCC
VSS
U14
VSS_NCTF
T7
HDINV2#
U15
VSS_NCTF
T8
HD37#
U16
VSS_NCTF
T9
VSS
U17
VCC_NCTF
T10
VTT
U18
VSS
T11
VTT
U19
VCC
T12
VTT_NCTF
U20
VCC
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
347
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
V29
VSS
V29
VSS
W19
VSS
Y10
VSS
W20
VCC
Y11
VSS
V30
V31
EXP_RXP14
W21
VCC_NCTF
Y12
VSS_NCTF
VSS
W22
VCC_NCTF
Y13
V32
VSS_NCTF
EXP_TXP14
W23
VCC_NCTF
Y14
VSS_NCTF
V33
VSS
W24
VCC_NCTF
Y15
VSS_NCTF
V34
EXP_RXN13
W25
VCC_NCTF
Y16
VSS_NCTF
VSS_NCTF
V35
VSS
W26
VCC_NCTF
Y17
V36
EXP_TXN13
W27
VSS
Y18
VCC_NCTF
V37
VSS
VSS
Y19
VCC_NCTF
VCC_NCTF
W1
HD59#
W29
VSS
Y20
W2
HD63#
W30
EXP_RXN14
Y21
VSS_NCTF
HD60#
W31
VSS
Y22
VSS_NCTF
EXP_TXN14
Y23
VSS_NCTF
W3
W4
HDSTBP3#
W32
W5
VSS
W33
VSS
Y24
VSS_NCTF
HD48#
W34
EXP_RXP15
Y25
VSS_NCTF
W7
HD52#
W35
VSS
Y26
VSS_NCTF
W8
HD51#
W36
EXP_TXP15
Y27
VCCA_3GPLL
W9
VTT
W37
VCC3G
Y28
VCCA_3GPLL
W10
VTT
Y1
VSS
Y29
VCCA_3GPLL
W11
VTT
Y2
HD56#
Y30
VSS
W12
VTT_NCTF
Y3
HD61#
Y31
DMI_RXP0
W13
VTT_NCTF
Y4
W14
VSS_NCTF
Y5
HD55#
W15
VSS_NCTF
Y6
HD62#
W16
VSS_NCTF
Y7
HD58#
W17
VCC_NCTF
Y8
VSS
W18
VCC
Y9
VTT
W6
348
W28
VSS
Y32
VSS
Y33
DMI_TXP0
Y34
EXP_RXN15
Y35
VSS
Y36
EXP_TXN15
Y37
VSS
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
13.3 Mobile Intel 915GMS Express Chipset Ballout Diagram
Figure 13-3. Intel 915GMS GMCH Ballout Diagram
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
349
Ballout and Package Information
R
Figure 13-4. Intel 915GMS GMCH Ballout Diagram
350
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
13.4
Mobile Intel 915GMS Series Express Chipset Family Ballout List
Some signals may be RESERVED depending on which Mobile Intel 915GMS Express Chipset configuration used.
Please refer to the signal description chapter for more details.
Table 13-34. PLL Signal Group
Ball
Signal
V23
GCLKN
W23
GCLKP
AA3
HCLKN
Y3
HCLKP
A22
DREF_CLKN
A21
DREF_CLKP
H31
DREF_SSCLKN
J31
DREF_SSCLKP
Table 13-35.Host Address Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
C6
HA3#
C12
HA15#
B13
HA21#
G11
HA4#
G12
HA16#
A14
HA22#
E12
HA5#
F11
HADSTB0#
C13
HA23#
HA6#
A8
HREQ0#
J15
HA24#
HA7#
B7
HREQ1#
H12
HA25#
HA8#
A9
HREQ2#
E13
HA26#
B8
C11
B11
C9
HA9#
A7
HREQ3#
C14
HA27#
A11
HA10#
J12
HREQ4#
F14
HA28#
D12
HA11#
G14
HA17#
E14
HA29#
F13
HA12#
J14
HA18#
D13
HA30#
HA13#
G13
HA19#
B14
HA31#
HA14#
H14
HA20#
H15
HADSTB1#
E11
A13
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Table 13-36. Host Control Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
G9
HADS#
E5
HDEFER#
B2
HHIT#
E8
HBNR#
C4
HLOCK#
C3
HHITM#
B3
HBPRI#
F9
HBREQ0#
G1
HDPWR#
E9
HTRDY#
A5
HRS0#
C5
HSLPCPU#
A4
HDRDY#
B5
HRS1#
F8
HDBSY#
C7
HRS2#
Table 13-37. Host Data Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
F5
F2
E2
J5
F3
G3
F4
E3
J9
F6
J7
J8
J1
F1
K9
G7
J6
G5
G4
K3
K4
P1
R2
K5
J3
J2
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HDINV0#
HDSTBN0#
HDSTBP0#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
L5
U8
K7
U9
V9
R1
K6
U3
R9
L7
K8
L9
V3
V4
R6
P5
P3
R8
P7
P9
W3
R4
R3
R5
U6
U5
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HDINV1#
HDSTBN1#
HDSTBP1#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
V5
V6
R7
U1
U2
W7
W8
W1
V2
W4
Y2
Y5
AA9
AA8
AA1
V7
AA6
Y6
Y8
W9
Y7
W5
AA4
AA5
HD46#
HD47#
HDINV2#
HDSTBN2#
HDSTBP2#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HDINV3#
HDSTBN3#
HDSTBP3#
Table 13-38. DDR2 SDRAM Common Signal Group Ball List
352
Ball
Signal
Ball
Signal
AE31
AF31
AF5
AE5
AJ29
AJ28
AH5
SM_CK0
SM_CK0#
SM_CK1
SM_CK1#
SM_CK3
SM_CK3#
SM_CK4
AJ5
AC23
AC25
AH21
AJ21
AD11
AG13
SM_CK4#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
Ball
AL14
AH12
AF12
AG12
AK13
AJ12
Signal
SM_CS2#
SM_CS3#
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
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Table 13-39. DDR2 SDRAM Channel a Command Signal Group Ball List
Ball
Signal
Ball
Signal
Ball
Signal
AE15
SA_BS0
AC19
SA_MA2
AC11
SA_MA10
AD13
SA_BS1
AD20
SA_MA3
AB23
SA_MA11
AB25
SA_BS2
AE19
SA_MA4
AB24
SA_MA12
AE12
SA_CAS#
AE20
SA_MA5
AF13
SA_MA13
AG15
SA_RAS#
AF20
SA_MA6
AC27
SA_RCVENIN#
AB26
SA_RCVENOUT#
AJ15
SA_WE#
AF21
SA_MA7
AC21
SA_MA0
AE21
SA_MA8
AC20
SA_MA1
AA24
SA_MA9
Table 13-40. DDR2 SDRAM Channel A Data Signal Group Ball List
Ball
Signal
Ball
Signal
Ball
Signal
Y27
SA_DQ0
Y28
SA_DQ1
AF24
SA_DM2
AG11
SA_DQ45
AF25
SA_DQS2
AG6
AC29
SA_DQ46
SA_DQ2
AF26
SA_DQS2#
AE6
SA_DQ47
AE29
SA_DQ3
AL25
SA_DQ24
AG7
SA_DM5
AA28
SA_DQ4
AJ25
SA_DQ25
AG9
SA_DQS5
AA29
SA_DQ5
AG27
SA_DQ26
AF9
SA_DQS5#
AB31
SA_DQ6
AG26
SA_DQ27
AL7
SA_DQ48
AC30
SA_DQ7
AK25
SA_DQ28
AK7
SA_DQ49
AA31
SA_DM0
AL24
SA_DQ29
AK2
SA_DQ50
AB29
SA_DQS0
AG23
SA_DQ30
AJ2
SA_DQ51
AA30
SA_DQS0#
AG24
SA_DQ31
AK6
SA_DQ52
AG29
SA_DQ8
AK24
SA_DM3
AJ6
SA_DQ53
AG28
SA_DQ9
AJ23
SA_DQS3
AK3
SA_DQ54
SA_DQ55
AJ26
SA_DQ10
AJ24
SA_DQS3#
AH2
AL26
SA_DQ11
AK11
SA_DQ32
AL5
SA_DM6
AG30
SA_DQ12
AL11
SA_DQ33
AH3
SA_DQS6
AG31
SA_DQ13
AJ7
SA_DQ34
AG5
SA_DQS6#
AL27
SA_DQ14
AL9
SA_DQ35
AH1
SA_DQ56
AK27
SA_DQ15
AL12
SA_DQ36
AG1
SA_DQ57
AJ30
SA_DM1
AJ11
SA_DQ37
AC6
SA_DQ58
AL28
SA_DQS1
AH9
SA_DQ38
AC7
SA_DQ59
AK28
SA_DQS1#
AJ9
SA_DQ39
AF3
SA_DQ60
AF29
SA_DQ16
AJ10
SA_DM4
AE3
SA_DQ61
AE28
SA_DQ17
AK10
SA_DQS4
AD3
SA_DQ62
AE25
SA_DQ18
AL10
SA_DQS4#
AC2
SA_DQ63
AE24
SA_DQ19
AG10
SA_DQ40
AD6
SA_DM7
AE27
SA_DQ20
AF10
SA_DQ41
AE2
SA_DQS7
AF27
SA_DQ21
AH7
SA_DQ42
AF2
SA_DQS7#
AE23
SA_DQ22
AF6
SA_DQ43
AC26
SA_DQ23
AH11
SA_DQ44
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Table 13-41. DDR2 SDRAM Channel B Signal Group Ball List
Ball
Signal
Ball
Signal
AJ14
AG14
Ball
Signal
SB_BS0
AE14
SB_BS1
AC15
SB_MA1
AL19
SB_MA8
SB_MA2
AH20
SB_MA9
AL21
SB_BS2
AD14
SB_MA3
AF14
SB_MA10
AH14
SB_RAS#
AG19
SB_MA4
AL20
SB_MA11
AJ13
SB_CAS#
AJ19
SB_MA5
AG20
SB_MA12
AK14
SB_WE#
AJ20
SB_MA6
AL13
SB_MA13
AC12
SB_MA0
AK20
SB_MA7
Table 13-42. Analog CRT Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
F21
RED
D22
GREEN#
H22
HSYNC
F22
RED#
D23
BLUE
G23
VSYNC
E22
GREEN
C23
BLUE#
Ball
Signal
Ball
Signal
Table 13-43. Analog TV Signal Group
Ball
Signal
A17
TVDAC_A
C18
TVDAC_B
A19
TVDAC_C
B17
TV_IRTNA
B18
TV_IRTNB
B19
TV_IRTNC
Table 13-44. LVDS Display Interface Signal Group
Ball
E31
Signal
LADATAP0
D30
LADATAP1
C29
LADATAP2
C27
LACLKP
F31
LADATAN0
D31
LADATAN1
D29
LADATAN2
D27
LACLKN
Table 13-45. LVDS Power Sequencing and Backlight Control Signal Group
354
Ball
Signal
G26
LBKLT_CRTL
F26
LBKLT_EN
H25
LVDD_EN
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Table 13-46. LVDS Power Sequencing and Backlight Control Signal Group
Ball
Signal
G26
LBKLT_CRTL
F26
LBKLT_EN
H25
LVDD_EN
Table 13-47. DDC / GMBUS Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
J23
DDCCLK
C26
LCTLB_DATA
G27
SDVOCTRL_CLK
J25
DDCDATA
E25
LDDC_CLK
D26
LCTLA_CLK
F25
LDDC_DATA
H27
SDVOCTRL_DAT
A
Table 13-48. DMI Serial Interface Signal Group
Ball
Signal
Ball
Signal
V24
DMI_RXN0
V26
DMI_TXN0
W29
DMI_RXN1
W31
DMI_TXN1
U24
DMI_RXP0
U26
DMI_TXP0
V29
DMI_RXP1
V31
DMI_TXP1
Table 13-49. Serial Digital Video Out Receive Signal Group
Ball
SDVO Signal
Ball
SDVO Signal
M28
P28
SDVO_TVCLKIN#
L28
SDVO_TVCLKIN
SDVOB_INT#
N28
SDVOB_INT
U28
SDVO_FLDSTALL#
R28
SDVO_FLDSTALL
Table 13-50. Serial Digital Video Out Transmit Signal Group
Ball
SDVO Signal
Ball
SDVO Signal
M30
SDVOB_RED#
L30
SDVOB_RED
N26
SDVOB_GREEN#
M26
SDVOB_GREEN
P30
SDVOB_BLUE#
N30
SDVOB_BLUE
U30
SDVOB_CLKN
R30
SDVOB_CLKP
Table 13-51. Thermal and Power Sequencing Signal Group
Ball
Signal
W25
RSTIN#
F7
HCPURST#
W27
PWROK
J26
BM_BUSY#
J18
THRMTRIP#
J27
EXT_TS0#
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Table 13-52. No Connect Signal Group
356
Ball
Signal
Ball
Signal
Ball
Signal
A10
NC
AJ31
NC
L14
NC
A2
NC
AK1
NC
L15
NC
A29
NC
AK22
NC
L16
NC
A3
NC
AK31
NC
L17
NC
A30
NC
AL1
NC
L18
NC
A31
NC
AL2
NC
L19
NC
AA10
NC
AL22
NC
L20
NC
AA11
NC
AL29
NC
L21
NC
AA12
NC
AL3
NC
L22
NC
AA13
NC
AL30
NC
M10
NC
AA14
NC
AL31
NC
M11
NC
AA15
NC
B1
NC
M12
NC
AA16
NC
B10
NC
M13
NC
AA17
NC
B31
NC
M14
NC
AA18
NC
C1
NC
M15
NC
AA19
NC
C10
NC
M16
NC
AA20
NC
C31
NC
M17
NC
AA21
NC
E10
NC
M18
NC
AA22
NC
F10
NC
M19
NC
AB1
NC
G10
NC
M20
NC
AB10
NC
J10
NC
M21
NC
AB11
NC
K10
NC
M22
EXT_TS1#
AB12
NC
K11
NC
N10
NC
AB13
NC
K12
NC
N11
NC
AB14
NC
K13
NC
N12
NC
AB15
NC
K14
NC
N13
NC
AB17
NC
K15
NC
N14
NC
AB18
NC
K17
NC
N15
NC
AB19
NC
K18
NC
N16
NC
AB2
NC
K19
NC
N17
NC
AB20
NC
K20
NC
N18
NC
AB21
NC
K21
NC
N19
NC
AB22
NC
K22
NC
N20
NC
AB3
NC
K23
NC
N21
NC
AB5
NC
K25
NC
N22
NC
AB6
NC
K26
NC
P10
NC
AB7
NC
K27
NC
P11
NC
AB9
NC
K29
NC
P12
NC
AC22
NC
K30
NC
P13
NC
AE22
NC
K31
NC
P14
NC
AF22
NC
L10
NC
NC
NC
L11
NC
P15
AG22
NC
L12
NC
P16
NC
AJ1
AJ22
NC
L13
NC
P17
NC
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
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Ball
Signal
Ball
Signal
Ball
Signal
P18
NC
U13
NC
W17
NC
P19
NC
U14
NC
W18
NC
P20
NC
U18
NC
W19
NC
P21
NC
U19
NC
W20
NC
NC
U20
NC
W21
NC
R10
NC
U21
NC
W22
NC
R11
NC
U22
NC
Y10
NC
R12
NC
V10
NC
Y11
NC
R13
NC
V11
NC
Y12
NC
R14
NC
V12
NC
Y13
NC
R18
NC
V13
NC
Y14
NC
NC
NC
Y15
NC
R19
V14
Y16
NC
R20
NC
V15
NC
V16
NC
Y17
NC
R21
NC
V17
NC
Y18
NC
R22
NC
V18
NC
Y19
NC
T11
NC
V19
NC
Y20
NC
T12
NC
V20
NC
Y21
NC
T13
NC
V21
NC
Y22
NC
T14
NC
V22
NC
T18
NC
W10
NC
T19
NC
W11
NC
T20
NC
W12
NC
T21
NC
W13
NC
U10
NC
W14
NC
U11
NC
W15
NC
U12
NC
W16
NC
P22
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Table 13-53. Configuration & Reserved Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
D15
CFG0
G17
E17
CFG1
H17
CFG5
F29
RSVD24
CFG6
E27
RSVD25
F15
CFG2
H19
RSVD23
W2
RSVD1
Table 13-54. Voltage Reference and Compensation Signal Groups
Ball
Signal Name
Ball
System Memory
Signal Name
Host Interface
AB27
SMOCDCOMP0
K1
HXRCOMP
AE9
SMOCDCOMP1
E6
HXSCOMP
AD7
SMRCOMPN
J13
HXSWING
AE7
SMRCOMPP
L1
HYRCOMP
Y24
SMXSLEWIN
K2
HYSCOMP
AA25
SMXSLEWOUT
L3
HYSWING
AC10
SMYSLEWIN
J11
HVREF
AD10
SMYSLEWOUT
Y30
SMVREF0
AE1
SMVREF1
SDVO
P26
EXP_COMPI
Ball
Signal Name
L26
EXP_ICOMPO
CRT DAC
J21
REFSET
TV
J19
TV_REFSET
LVDS
J29
LVREFH
H29
LVREFL
F30
LIBG
G30
LVBG
Table 13-55. Power Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
PLL Signal Group
C21
VCCHV
B30
VSSALVDS
C22
VCCHV
AD1
VCCA_HPLL
AC1
VCCA_MPLL
AC3
VCCD_HMPLL1
AC5
VCCD_HMPLL2
R23
VCCA_3GPLL
B21
VCCA_DPLLA
J30
VCCA_DPLLB
PCI Express Graphics
VCCD_TVDAC
VCC_SYNC
D17
VCCDQ_TVDAC
VCCA_CRTDAC
F18
VCCA_TVDACA
D21
VCCA_CRTDAC
G18
VCCA_TVDACA
D20
VSSA_CRTDAC
F19
VCCA_TVDACB
LVDS Signal Group
VCC3G
A23
VCCD_LVDS
VCC3G
B23
VCCD_LVDS
M31
VCCA_3GBG
B25
VCCD_LVDS
L31
VSSA_3GBG
A26
VCCTX_LVDS
B26
VCCTX_LVDS
B29
VCCA_LVDS
VCCHV
E18
C20
P31
High Voltage
TV Out Signal Group
H21
R31
B20
358
CRT DAC
G19
VCCA_TVDACB
F20
VCCA_TVDACC
G20
VCCA_TVDACC
E19
VCCA_TVBG
E20
VSSA_TVBG
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Table 13-56. System Memory Analog Power Signal Group
Ball
Signal
AC13
VCCASM
AC14
VCCASM
AL15
VCCASM
Table 13-57. System Memory Power Signal Group
Ball
Signal
Ball
Signal
Ball
Signal
AD18
AE17
VCCSM
AJ18
VCCSM
AG18
VCCSM
VCCSM
AK17
VCCSM
AC17
VCCSM
AE18
VCCSM
AK18
VCCSM
AC18
VCCSM
AF1
VCCSM
AK30
VCCSM
AC31
VCCSM
AF17
VCCSM
AL17
VCCSM
AD17
VCCSM
AF18
VCCSM
AL18
VCCSM
AH17
VCCSM
AL23
VCCSM
AH18
VCCSM
AL6
VCCSM
AJ17
VCCSM
AG17
VCCSM
Table 13-58. VTT Power Signal Group
Ball
Signal
A6
VTT
A12
VTT
E1
VTT
M1
VTT
M2
VTT
M3
VTT
M4
VTT
M5
VTT
M6
VTT
M7
VTT
M8
VTT
M9
VTT
N1
VTT
N2
VTT
N3
VTT
N4
VTT
N5
VTT
N6
VTT
N7
VTT
N8
VTT
N9
VTT
Y1
VTT
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Table 13-59. GMCH Core Voltage Power Signal Group
Ball
Signal
L23
VCC
L24
VCC
M24
VCC
N23
VCC
N24
VCC
P24
VCC
R15
VCC
R17
VCC
T15
VCC
T16
VCC
T17
VCC
U16
VCC
Table 13-60. GMCH Ground Signal Group
360
Ball
Signal
Ball
Signal
Ball
Signal
A15
VSS
AF15
VSS
B22
VSS
A18
VSS
AF19
VSS
B27
VSS
A20
VSS
AF23
VSS
B4
VSS
A25
VSS
AF28
VSS
B6
VSS
A27
VSS
AF30
VSS
B9
VSS
AA2
VSS
AF7
VSS
C15
VSS
AA23
VSS
AG2
VSS
C17
VSS
AA26
VSS
AG21
VSS
C19
VSS
AA27
VSS
AG25
VSS
C2
VSS
AA7
VSS
AG3
VSS
C25
VSS
AB28
VSS
AH10
VSS
C30
VSS
AB30
VSS
AH13
VSS
C8
VSS
AC24
VSS
AH15
VSS
D11
VSS
AC28
VSS
AH19
VSS
D14
VSS
AC9
VSS
AH6
VSS
D18
VSS
AD12
VSS
AJ27
VSS
D19
VSS
AD15
VSS
AJ3
VSS
D25
VSS
AD19
VSS
AK12
VSS
E15
VSS
AD2
VSS
AK15
VSS
E21
VSS
AD21
VSS
AK19
VSS
E23
VSS
AD5
VSS
AK21
VSS
E26
VSS
AD9
VSS
AK23
VSS
E29
VSS
AE10
VSS
AK26
VSS
E30
VSS
AE11
VSS
AK29
VSS
E4
VSS
AE13
VSS
AK5
VSS
E7
VSS
AE26
VSS
AK9
VSS
F12
VSS
AE30
VSS
B12
VSS
F17
VSS
AF11
VSS
B15
VSS
F23
VSS
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Ball
Signal
Ball
Signal
Ball
Signal
F27
VSS
L8
VSS
U27
VSS
G15
VSS
M23
VSS
U29
VSS
G2
VSS
M25
VSS
U31
VSS
G21
VSS
M27
VSS
U4
VSS
G22
VSS
M29
VSS
U7
VSS
G25
VSS
N25
VSS
V1
VSS
G29
VSS
N27
VSS
V25
VSS
G31
VSS
N29
VSS
V27
VSS
G6
VSS
N31
VSS
V28
VSS
G8
VSS
P2
VSS
V30
VSS
H11
VSS
P23
VSS
V8
VSS
H13
VSS
P25
VSS
W24
VSS
H18
VSS
P27
VSS
W26
VSS
H20
VSS
P29
VSS
W28
VSS
H23
VSS
P4
VSS
W30
VSS
H26
VSS
P6
VSS
W6
VSS
H30
VSS
P8
VSS
Y23
VSS
J17
VSS
R16
VSS
Y25
VSS
J20
VSS
R24
VSS
Y26
VSS
J22
VSS
R25
VSS
Y29
VSS
J4
VSS
R26
VSS
Y31
VSS
L2
VSS
R27
VSS
Y4
VSS
L25
VSS
R29
VSS
Y9
VSS
L27
VSS
U15
VSS
L29
VSS
U17
VSS
L4
VSS
U23
VSS
L6
VSS
U25
VSS
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
361
Ballout and Package Information
R
13.4.1
Mobile Intel 915GMS Express Chipset Family Ball-Out Numerical Order
Ball List
Ball
Signal
Ball
Signal
Ball
Signal
A10
NC
AA21
NC
AB30
VSS
A11
HA10#
AA22
NC
AB31
SA_DQ6
A12
VTT
AA23
VSS
AB5
NC
A13
HA14#
AA24
SA_MA9
AB6
NC
A14
HA22#
AA25
SMXSLEWOUT
AB7
NC
A15
VSS
AA26
VSS
AB9
NC
A17
TVDAC_A
AA27
VSS
AC1
VCCA_MPLL
A18
VSS
AA28
SA_DQ4
AC10
SMYSLEWIN
A19
TVDAC_C
AA29
SA_DQ5
AC11
SA_MA10
A2
NC
AA3
HCLKN
AC12
SB_MA0
A20
VSS
AA30
SA_DQS0#
AC13
VCCA_SM
A21
DREF_CLKP
AA31
SA_DM0
AC14
VCCA_SM
A22
DREF_CLKN
AA4
HDSTBN3#
AC15
SB_MA2
A23
VCCD_LVDS
AA5
HDSTBP3#
AC17
VCCSM
A25
VSS
AA6
HD59#
AC18
VCCSM
A26
VCCTX_LVDS
AA7
VSS
AC19
SA_MA2
A27
VSS
AA8
HD56#
AC2
SA_DQ63
A29
NC
AA9
HD55#
AC20
SA_MA1
A3
NC
AB1
NC
AC21
SA_MA0
A30
NC
AB10
NC
AC22
NC
A31
NC
AB11
NC
AC23
SM_CKE0
A4
HDRDY#
AB12
NC
AC24
VSS
A5
HRS0#
AB13
NC
AC25
SM_CKE1
A6
VTT
AB14
NC
AC26
SA_DQ23
A7
HREQ3#
AB15
NC
AC27
SA_RCVENIN#
A8
HREQ0#
AB17
NC
AC28
VSS
A9
HREQ2#
AB18
NC
AC29
SA_DQ2
AA1
HD57#
AB19
NC
AC3
VCCD_HMPLL1
AA10
NC
AB2
NC
Ac30
SA_DQ7
AA11
NC
AB20
NC
AC31
VCCSM
AA12
NC
AB21
NC
AC5
VCCD_HMPLL2
AA13
NC
AB22
NC
AC6
SA_DQ58
AA14
NC
AB23
SA_MA11
AC7
SA_DQ59
AA15
NC
AB24
SA_MA12
AC9
VSS
AA16
NC
AB25
SA_BS2
AD1
VCCA_HPLL
AA17
NC
AB26
SA_RCVENOUT#
AD10
SMYSLEWOUT
AA18
NC
AB27
SMOCDCOMP0
AD11
SM_CS0#
AA19
NC
AB28
VSS
AD12
VSS
AA2
VSS
AB29
SA_DQS0
AD13
SA_BS1
AA20
NC
AB3
NC
AD14
SB_MA3
362
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
AD15
VSS
AF14
SB_MA10
AG30
SA_DQ12
AD17
VCCSM
AF15
VSS
AG31
SA_DQ13
AD18
VCCSM
AF17
VCCSM
AG5
SA_DQS6#
AD19
VSS
AF18
VCCSM
AG6
SA_DQ46
AD2
VSS
AF19
VSS
AG7
SA_DM5
AD20
SA_MA3
AF2
SA_DQS7#
AG9
SA_DQS5
AD21
VSS
AF20
SA_MA6
AH1
SA_DQ56
AD3
SA_DQ62
AF21
SA_MA7
AH10
VSS
AD5
VSS
AF22
NC
AH11
SA_DQ44
AD6
SA_DM7
AF23
VSS
AH12
SM_CS3#
AD7
SMRCOMPN
AF24
SA_DM2
AH13
VSS
AD9
VSS
AF25
SA_DQS2
AH14
SB_RAS#
AE1
SMVREF1
AF26
SA_DQS2#
AH15
VSS
AE10
VSS
AF27
SA_DQ21
AH17
VCCSM
AE11
VSS
AF28
VSS
AH18
VCCSM
AE12
SA_CAS#
AF29
SA_DQ16
AH19
VSS
SA_DQ55
AE13
VSS
AF3
SA_DQ60
AH2
AE14
SB_MA1
AF30
VSS
AH20
SB_MA9
AE15
SA_BS0
AF31
SM_CK0#
AH21
SM_CKE2
AE17
VCCSM
AF5
SM_CK1
AH3
SA_DQS6
AE18
VCCSM
AF6
SA_DQ43
AH5
SM_CK4
AE19
SA_MA4
AF7
VSS
AH6
VSS
AE2
SA_DQS7
AF9
SA_DQS5#
AH7
SA_DQ42
AE20
SA_MA5
AG1
SA_DQ57
AH9
SA_DQ38
AE21
SA_MA8
AG10
SA_DQ40
AJ1
NC
AE22
NC
AG11
SA_DQ45
AJ10
SA_DM4
AE23
SA_DQ22
AG12
SM_ODT1
AJ11
SA_DQ37
AE24
SA_DQ19
AG13
SM_CS1#
AJ12
SM_ODT3
AE25
SA_DQ18
AG14
SB_BS1
AJ13
SB_CAS#
AE26
VSS
AG15
SA_RAS#
AJ14
SB_BS0
AE27
SA_DQ20
AG17
VCCSM
AJ15
SA_WE#
AE28
SA_DQ17
AG18
VCCSM
AJ17
VCCSM
AE29
SA_DQ3
AG19
SB_MA4
AJ18
VCCSM
AE3
SA_DQ61
AG2
VSS
AJ19
SB_MA5
AE30
VSS
AG20
SB_MA12
AJ2
SA_DQ51
AE31
SM_CK0
AG21
VSS
AJ20
SB_MA6
AE5
SM_CK1#
AG22
NC
AJ21
SM_CKE3
AE6
SA_DQ47
AG23
SA_DQ30
AJ22
NC
AE7
SMRCOMPP
AG24
SA_DQ31
AJ23
SA_DQS3
AE9
SMOCDCOMP1
AG25
VSS
AJ24
SA_DQS3#
AF1
VCCSM
AG26
SA_DQ27
AJ25
SA_DQ25
AF10
SA_DQ41
AG27
SA_DQ26
AJ26
SA_DQ10
AF11
VSS
AG28
SA_DQ9
AJ27
VSS
AF12
SM_ODT0
AG29
SA_DQ8
AJ28
SM_CK3#
AF13
SA_MA13
AG3
VSS
AJ29
SM_CK3
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
363
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
AJ3
VSS
AJ30
SA_DM1
AL2
NC
B9
VSS
AL20
SB_MA11
C1
NC
AJ31
AJ5
NC
AL21
SB_BS2
C10
NC
SM_CK4#
AL22
NC
C11
HA7#
AJ6
SA_DQ53
AL23
VCCSM
C12
HA15#
AJ7
SA_DQ34
AL24
SA_DQ29
C13
HA23#
AJ9
SA_DQ39
AL25
SA_DQ24
C14
HA27#
AK1
NC
AL26
SA_DQ11
C15
VSS
AK10
SA_DQS4
AL27
SA_DQ14
C17
VSS
AK11
SA_DQ32
AL28
SA_DQS1
C18
TVDAC_B
AK12
VSS
AL29
NC
C19
VSS
AK13
SM_ODT2
AL3
NC
C2
VSS
AK14
SB_WE#
AL30
NC
C20
VCCA_CRTDAC
AK15
VSS
AL31
NC
C21
VCCHV
AK17
VCCSM
AL5
SA_DM6
C22
VCCHV
AK18
VCCSM
AL6
VCCSM
C23
BLUE#
AK19
VSS
AL7
SA_DQ48
C25
VSS
LCTLB_DATA
AK2
SA_DQ50
AL9
SA_DQ35
C26
AK20
SB_MA7
B1
NC
C27
LACLKP
AK21
VSS
B10
NC
C29
LADATAP2
AK22
NC
B11
HA8#
C3
HHITM#
AK23
VSS
B12
VSS
C30
VSS
AK24
SA_DM3
B13
HA21#
C31
NC
AK25
SA_DQ28
B14
HA31#
C4
HLOCK#
AK26
VSS
B15
VSS
C5
HCPUSLP#
AK27
SA_DQ15
B17
TV_IRTNA
C6
HA3#
AK28
SA_DQS1#
B18
TV_IRTNB
C7
HRS2#
AK29
VSS
B19
TV_IRTNC
C8
VSS
AK3
SA_DQ54
B2
HHIT#
C9
HA9#
AK30
VCCSM
B20
VCCHV
D11
VSS
AK31
NC
B21
VCCA_DPLLA
D12
HA11#
AK5
VSS
B22
VSS
D13
HA30#
AK6
SA_DQ52
B23
VCCD_LVDS
D14
VSS
AK7
SA_DQ49
B25
VCCD_LVDS
D15
CFG0
AK9
VSS
B26
VCCTX_LVDS
D17
VCCDQ_TVDAC
AL1
NC
B27
VSS
D18
VSS
AL10
SA_DQS4#
B29
VCCA_LVDS
D19
VSS
AL11
SA_DQ33
B3
HBPRI#
D20
VSSA_CRTDAC
AL12
SA_DQ36
B30
VSSALVDS
D21
VCCA_CRTDAC
AL13
SB_MA13
B31
NC
D22
GREEN#
AL14
SM_CS2#
B4
VSS
D23
BLUE
AL15
VCCA_SM
B5
HRS1#
D25
VSS
AL17
VCCSM
B6
VSS
D26
LCTLA_CLK
AL18
VCCSM
B7
HREQ1#
D27
LACLKN
AL19
SB_MA8
B8
HA6#
D29
LADATAN2
364
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
D30
LADATAP1
F25
LDDC_DATA
H15
HADSTB1#
D31
LADATAN1
F26
LBKLT_EN
H17
CFG6
E1
VTT
F27
VSS
H18
VSS
E10
NC
F29
RSVD24
H19
RSVD23
E11
HA13#
F3
HD4#
H20
VSS
E12
HA5#
F30
LIBG
H21
VCC_SYNC
E13
HA26#
F31
LADATAN0
H22
HSYNC
E14
HA29#
F4
HD6#
H23
VSS
E15
VSS
F5
HD0#
H25
LVDD_EN
E17
CFG1
F6
HD9#
H26
VSS
E18
VCCD_TVDAC
F7
HCPURST#
H27
SDVOCTRL_DATA
E19
VCCA_TVBG
F8
HDBSY#
H29
LVREFL
E2
HD2#
F9
HBREQ0#
H30
VSS
E20
VSSA_TVBG
G1
HDPWR#
H31
DREF_SSCLKN
E21
VSS
G10
NC
J1
HD12#
E22
GREEN
G11
HA4#
J10
CFG12
E23
VSS
G12
HA16#
J11
HVREF
E25
LDDC_CLK
G13
HA19#
J12
HREQ4#
E26
VSS
G14
HA17#
J13
HXSWING
E27
RSVD25
G15
VSS
J14
HA18#
E29
VSS
G17
CFG5
J15
HA24#
E3
HD7#
G18
VCCA_TVDACA
J17
VSS
E30
VSS
G19
VCCA_TVDACB
J18
THRMTRIP#
E31
LADATAP0
G2
VSS
J19
TV_REFSET
E4
VSS
G20
VCCA_TVDACC
J2
HD22#
E5
HDEFER#
G21
VSS
J20
VSS
E6
HXSCOMP
G22
VSS
J21
REFSET
E7
VSS
G23
VSYNC
J22
VSS
E8
HBNR#
G25
VSS
J23
DDCCLK
E9
HTRDY#
G26
LBKLT_CRTL
J25
DDCDATA
F1
HD13#
G27
SDVOCTRL_CLK
J26
BM_BUSY#
F10
NC
G29
VSS
J27
EXT_TS0#
F11
HADSTB0#
G3
HD5#
J29
LVREFH
F12
VSS
G30
LVBG
J3
HD21#
F13
HA12#
G31
VSS
J30
VCCA_DPLLB
F14
HA28#
G4
HDSTBP0#
J31
DREF_SSCLKP
F15
CFG2
G5
HDSTBN0#
J4
VSS
F17
VSS
G6
VSS
J5
HD3#
F18
VCCA_TVDACA
G7
HD15#
J6
HDINV0#
F19
VCCA_TVDACB
G8
VSS
J7
HD10#
F2
HD1#
G9
HADS#
J8
HD11#
F20
VCCA_TVDACC
H11
VSS
J9
HD8#
F21
RED
H12
HA25#
K1
HXRCOMP
F22
RED#
H13
VSS
K10
NC
F23
VSS
H14
HA20#
K11
NC
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
365
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
K12
NC
L28
SDVO_TVCLKIN
N12
NC
K13
NC
L29
VSS
N13
NC
K14
NC
L3
HYSWING
N14
NC
K15
NC
L30
SDVOB_RED
N15
NC
K17
NC
L31
VSSA_3GBG
N16
NC
K18
NC
L4
VSS
N17
NC
K19
NC
L5
HD23#
N18
NC
K2
HYSCOMP
L6
VSS
N19
NC
K20
NC
L7
HDINV1#
N2
VTT
K21
NC
L8
VSS
N20
NC
K22
NC
L9
HDSTBP1#
N21
NC
K23
NC
M1
VTT
N22
NC
K25
NC
M10
NC
N23
VCC
K26
NC
M11
NC
N24
VCC
K27
NC
M12
NC
N25
VSS
K29
NC
M13
NC
N26
SDVOB_GREEN#
K3
HD16#
M14
NC
N27
VSS
K30
NC
M15
NC
N28
SDVOB_INT
K31
NC
M16
NC
N29
VSS
K4
HD17#
M17
NC
N3
VTT
K5
HD20#
M18
NC
N30
SDVOB_BLUE
K6
HD29#
M19
NC
N31
VSS
K7
HD25#
M2
VTT
N4
VTT
K8
HDSTBN1#
M20
NC
N5
VTT
K9
HD14#
M21
NC
N6
VTT
L1
HYRCOMP
M22
EXT_TS1#
N7
VTT
L10
NC
M23
VSS
N8
VTT
L11
NC
M24
VCC
N9
VTT
L12
NC
M25
VSS
P1
HD18#
L13
NC
M26
SDVOB_GREEN
P10
NC
L14
NC
M27
VSS
P11
NC
L15
NC
M28
SDVO_TVCLKIN#
P12
NC
L16
NC
M29
VSS
P13
NC
L17
NC
M3
VTT
P14
NC
L18
NC
M30
SDVOB_RED#
P15
NC
L19
NC
M31
VCCA_3GBG
P16
NC
L2
VSS
M4
VTT
P17
NC
L20
NC
M5
VTT
P18
NC
L21
NC
M6
VTT
P19
NC
L22
NC
M7
VTT
P2
VSS
L23
VCC
M8
VTT
P20
NC
L24
VCC
M9
VTT
P21
NC
L25
VSS
N1
VTT
P22
NC
L26
EXP_ICOMPO
N10
NC
P23
VSS
L27
VSS
N11
NC
P24
VCC
366
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
P25
VSS
T11
NC
V12
NC
P26
EXP_COMPI
T12
NC
V13
NC
P27
VSS
T13
NC
V14
NC
P28
SDVOB_INT#
T14
NC
V15
NC
P29
VSS
T15
VCC
V16
NC
P3
HD36#
T16
VCC
V17
NC
P30
SDVOB_BLUE#
T17
VCC
V18
NC
P31
VCC3G
T18
NC
V19
NC
P4
VSS
T19
NC
V2
HD51#
P5
HD35#
T20
NC
V20
NC
P6
VSS
T21
NC
V21
NC
P7
HD38#
U1
HDSTBN2#
V22
NC
P8
VSS
U10
NC
V23
GCLKN
P9
HD39#
U11
NC
V24
DMI_RXN0
R1
HD28#
U12
NC
V25
VSS
R10
NC
U13
NC
V26
DMI_TXN0
R11
NC
U14
NC
V27
VSS
R12
NC
U15
VSS
V28
VSS
R13
NC
U16
VCC
V29
DMI_RXP1
R14
NC
U17
VSS
V3
HD32#
R15
VCC
U18
NC
V30
VSS
R16
VSS
U19
NC
V31
DMI_TXP1
R17
VCC
U2
HDSTBP2#
V4
HD33#
R18
NC
U20
NC
V5
HD46#
R19
NC
U21
NC
V6
HD47#
HD58#
R2
HD19#
U22
NC
V7
R20
NC
U23
VSS
V8
VSS
R21
NC
U24
DMI_RXP0
V9
HD27#
R22
NC
U25
VSS
W1
HD50#
R23
VCCA_3GPLL
U26
DMI_TXP0
W10
NC
R24
VSS
U27
VSS
W11
NC
R25
VSS
U28
SDVO_FLDSTALL#
W12
NC
R26
VSS
U29
VSS
W13
NC
R27
VSS
U3
HD30#
W14
NC
R28
SDVO_FLDSTALL
U30
SDVOB_BLKN
W15
NC
R29
VSS
U31
VSS
W16
NC
R3
HD42#
U4
VSS
W17
NC
R30
SDVOB_BLKP
U5
HD45#
W18
NC
R31
VCC3G
U6
HD44#
W19
NC
R4
HD41#
U7
VSS
W2
RSVD1
R5
HD43#
U8
HD24#
W20
NC
R6
HD34#
U9
HD26#
W21
NC
R7
HDINV2#
V1
VSS
W22
NC
R8
HD37#
V10
NC
W23
GCLKP
R9
HD31#
V11
NC
W24
VSS
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
367
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
W25
RSTIN#
Y13
NC
Y3
HCLKP
W26
VSS
Y14
NC
Y30
SMVREF0
W27
PWROK
Y15
NC
Y31
VSS
W28
VSS
Y16
NC
Y4
VSS
W29
DMI_RXN1
Y17
NC
Y5
HD54#
W3
HD40#
Y18
NC
Y6
HD60#
W30
VSS
Y19
NC
Y7
HD63#
W31
DMI_TXN1
Y2
HD53#
Y8
HD61#
W4
HD52#
Y20
NC
Y9
VSS
W5
HDINV3#
Y21
NC
W6
VSS
Y22
NC
W7
HD48#
Y23
VSS
W8
HD49#
Y24
SMXSLEWIN
W9
HD62#
Y25
VSS
Y1
VTT
Y26
VSS
Y10
NC
Y27
SA_DQ0
Y11
NC
Y28
SA_DQ1
Y12
NC
Y29
VSS
368
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
13.5 Mobile Intel 915GMS Express Chipset Family Signal Name
Ordering Ball List
Ball
Signal
Ball
Signal
D23
BLUE
M22
C23
BLUE#
V23
Ball
Signal
EXT_TS1#
F9
HBREQ0#
GCLKN
AA3
HCLKN
J26
BM_BUSY#
W23
GCLKP
Y3
HCLKP
D15
CFG0
E22
GREEN
F7
HCPURST#
E17
CFG1
D22
GREEN#
C5
HCPUSLP#
F15
CFG2
A11
HA10#
F5
HD0#
G17
CFG5
D12
HA11#
F2
HD1#
H17
CFG6
F13
HA12#
J7
HD10#
J23
DDCCLK
E11
HA13#
J8
HD11#
J25
DDCDATA
A13
HA14#
J1
HD12#
V24
DMI_RXN0
C12
HA15#
F1
HD13#
W29
DMI_RXN1
G12
HA16#
K9
HD14#
U24
DMI_RXP0
G14
HA17#
G7
HD15#
V29
DMI_RXP1
J14
HA18#
K3
HD16#
V26
DMI_TXN0
G13
HA19#
K4
HD17#
W31
DMI_TXN1
H14
HA20#
P1
HD18#
U26
DMI_TXP0
B13
HA21#
R2
HD19#
V31
DMI_TXP1
A14
HA22#
E2
HD2#
A22
DREF_CLKN
C13
HA23#
K5
HD20#
A21
DREF_CLKP
J15
HA24#
J3
HD21#
H31
DREF_SSCLKN
H12
HA25#
J2
HD22#
J31
DREF_SSCLKP
E13
HA26#
L5
HD23#
P26
EXP_COMPI
C14
HA27#
U8
HD24#
L26
EXP_ICOMPO
F14
HA28#
K7
HD25#
M28
SDVO_TVCLKIN#
E14
HA29#
U9
HD26#
P28
SDVOB_INT#
C6
HA3#
V9
HD27#
U28
SDVO_FLDSTALL#
D13
HA30#
R1
HD28#
L28
SDVO_TVCLKIN
B14
HA31#
K6
HD29#
N28
SDVOB_INT
G11
HA4#
J5
HD3#
R28
SDVO_FLDSTALL
E12
HA5#
U3
HD30#
M30
SDVOB_RED#
B8
HA6#
R9
HD31#
N26
SDVOB_GREEN#
C11
HA7#
V3
HD32#
P30
SDVOB_BLUE#
B11
HA8#
V4
HD33#
U30
SDVOB_BLKN
C9
HA9#
R6
HD34#
L30
SDVOB_RED
G9
HADS#
P5
HD35#
M26
SDVOB_GREEN
F11
HADSTB0#
P3
HD36#
N30
SDVOB_BLUE
H15
HADSTB1#
R8
HD37#
R30
SDVOB_BLKP
E8
HBNR#
P7
HD38#
J27
EXT_TS0#
B3
HBPRI#
P9
HD39#
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
369
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
F3
HD4#
AA5
HDSTBP3#
AA13
NC
W3
HD40#
B2
HHIT#
AA14
NC
R4
HD41#
C3
HHITM#
AA15
NC
R3
HD42#
C4
HLOCK#
AA16
NC
R5
HD43#
A8
HREQ0#
AA17
NC
U6
HD44#
B7
HREQ1#
AA18
NC
U5
HD45#
A9
HREQ2#
AA19
NC
V5
HD46#
A7
HREQ3#
AA20
NC
V6
HD47#
J12
HREQ4#
AA21
NC
W7
HD48#
A5
HRS0#
AA22
NC
W8
HD49#
B5
HRS1#
AB1
NC
G3
HD5#
C7
HRS2#
AB10
NC
W1
HD50#
H22
HSYNC
AB11
NC
V2
HD51#
E9
HTRDY#
AB12
NC
W4
HD52#
J11
HVREF
AB13
NC
Y2
HD53#
K1
HXRCOMP
AB14
NC
Y5
HD54#
E6
HXSCOMP
AB15
NC
AA9
HD55#
J13
HXSWING
AB17
NC
AA8
HD56#
L1
HYRCOMP
AB18
NC
AA1
HD57#
K2
HYSCOMP
AB19
NC
V7
HD58#
L3
HYSWING
AB2
NC
AA6
HD59#
D27
LACLKN
AB20
NC
F4
HD6#
C27
LACLKP
AB21
NC
Y6
HD60#
F31
LADATAN0
AB22
NC
Y8
HD61#
D31
LADATAN1
AB3
NC
W9
HD62#
D29
LADATAN2
AB5
NC
Y7
HD63#
E31
LADATAP0
AB6
NC
E3
HD7#
D30
LADATAP1
AB7
NC
J9
HD8#
C29
LADATAP2
AB9
NC
F6
HD9#
G26
LBKLT_CRTL
AC22
NC
F8
HDBSY#
F26
LBKLT_EN
AE22
NC
E5
HDEFER#
D26
LCTLA_CLK
AF22
NC
J6
HDINV0#
C26
LCTLB_DATA
AG22
NC
L7
HDINV1#
E25
LDDC_CLK
AJ22
NC
R7
HDINV2#
F25
LDDC_DATA
AK22
NC
W5
HDINV3#
F30
LIBG
AL22
NC
G1
HDPWR#
G30
LVBG
B10
NC
A4
HDRDY#
H25
LVDD_EN
C10
NC
G5
HDSTBN0#
J29
LVREFH
E10
NC
F10
NC
K8
HDSTBN1#
H29
LVREFL
U1
HDSTBN2#
A10
NC
G10
NC
AA4
HDSTBN3#
A31
NC
J10
NC
G4
HDSTBP0#
AA10
NC
K10
NC
L9
HDSTBP1#
AA11
NC
K11
NC
U2
HDSTBP2#
AA12
NC
K12
NC
370
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
K13
NC
N17
NC
U21
NC
K14
NC
N18
NC
U22
NC
K15
NC
N19
NC
V10
NC
K17
NC
N20
NC
V11
NC
K18
NC
N21
NC
V12
NC
K19
NC
N22
NC
V13
NC
K20
NC
P10
NC
V14
NC
K21
NC
P11
NC
V15
NC
K22
NC
P12
NC
V16
NC
K23
NC
P13
NC
V17
NC
K25
NC
P14
NC
V18
NC
K27
NC
P15
NC
V19
NC
K29
NC
P16
NC
V20
NC
K30
NC
P17
NC
V21
NC
K31
NC
P18
NC
V22
NC
L10
NC
P19
NC
W10
NC
L11
NC
P20
NC
W11
NC
L12
NC
P21
NC
W12
NC
L13
NC
P22
NC
W13
NC
L14
NC
R10
NC
W14
NC
L15
NC
R11
NC
W15
NC
L16
NC
R12
NC
W16
NC
L17
NC
R13
NC
W17
NC
L18
NC
R14
NC
W18
NC
L19
NC
R18
NC
W19
NC
L20
NC
R19
NC
W20
NC
L21
NC
R20
NC
W21
NC
M11
NC
R21
NC
W22
NC
M12
NC
R22
NC
Y10
NC
M13
NC
T11
NC
Y11
NC
M14
NC
T12
NC
Y12
NC
M15
NC
T13
NC
Y13
NC
M16
NC
T14
NC
Y14
NC
M17
NC
T18
NC
Y15
NC
M18
NC
T19
NC
Y16
NC
M19
NC
T20
NC
Y17
NC
M20
NC
T21
NC
Y18
NC
M21
NC
U10
NC
Y19
NC
N10
NC
U11
NC
Y20
NC
N11
NC
U12
NC
Y21
NC
N12
NC
U13
NC
Y22
NC
N13
NC
U14
NC
AL31
NC
N14
NC
U18
NC
AK31
NC
N15
NC
U19
NC
AJ31
NC
N16
NC
U20
NC
C31
NC
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
371
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
B31
NC
AL27
SA_DQ14
AH2
SA_DQ55
AL30
NC
AK27
SA_DQ15
AH1
SA_DQ56
A30
NC
AF29
SA_DQ16
AG1
SA_DQ57
AL29
NC
AE28
SA_DQ17
AC6
SA_DQ58
A2
NC
AE25
SA_DQ18
AC7
SA_DQ59
B1
NC
AE24
SA_DQ19
AB31
SA_DQ6
A29
NC
AC29
SA_DQ2
AF3
SA_DQ60
AL3
NC
AE27
SA_DQ20
AE3
SA_DQ61
A3
NC
AF27
SA_DQ21
AD3
SA_DQ62
AL2
NC
AE23
SA_DQ22
AC2
SA_DQ63
AL1
NC
AC26
SA_DQ23
Ac30
SA_DQ7
AK1
NC
AL25
SA_DQ24
AG29
SA_DQ8
AJ1
NC
AJ25
SA_DQ25
AG28
SA_DQ9
C1
NC
AG27
SA_DQ26
AB29
SA_DQS0
W27
PWROK
AG26
SA_DQ27
AA30
SA_DQS0#
F21
RED
AK25
SA_DQ28
AL28
SA_DQS1
F22
RED#
AL24
SA_DQ29
AK28
SA_DQS1#
J21
REFSET
AE29
SA_DQ3
AF25
SA_DQS2
W25
RSTIN#
AG23
SA_DQ30
AF26
SA_DQS2#
W2
RSVD1
AG24
SA_DQ31
AJ23
SA_DQS3
K26
NC
AK11
SA_DQ32
AJ24
SA_DQS3#
L22
NC
AL11
SA_DQ33
AK10
SA_DQS4
H19
RSVD23
AJ7
SA_DQ34
AL10
SA_DQS4#
F29
RSVD24
AL9
SA_DQ35
AG9
SA_DQS5
SA_DQS5#
E27
RSVD25
AL12
SA_DQ36
AF9
M10
NC
AJ11
SA_DQ37
AH3
SA_DQS6
F10
NC
AH9
SA_DQ38
AG5
SA_DQS6#
AE15
SA_BS0
AJ9
SA_DQ39
AE2
SA_DQS7
AD13
SA_BS1
AA28
SA_DQ4
AF2
SA_DQS7#
AB25
SA_BS2
AG10
SA_DQ40
AC21
SA_MA0
AE12
SA_CAS#
AF10
SA_DQ41
AC20
SA_MA1
AA31
SA_DM0
AH7
SA_DQ42
AC11
SA_MA10
AJ30
SA_DM1
AF6
SA_DQ43
AB23
SA_MA11
AF24
SA_DM2
AH11
SA_DQ44
AB24
SA_MA12
AK24
SA_DM3
AG11
SA_DQ45
AF13
SA_MA13
AJ10
SA_DM4
AG6
SA_DQ46
AC19
SA_MA2
AG7
SA_DM5
AE6
SA_DQ47
AD20
SA_MA3
AL5
SA_DM6
AL7
SA_DQ48
AE19
SA_MA4
AD6
SA_DM7
AK7
SA_DQ49
AE20
SA_MA5
Y27
SA_DQ0
AA29
SA_DQ5
AF20
SA_MA6
Y28
SA_DQ1
AK2
SA_DQ50
AF21
SA_MA7
AJ26
SA_DQ10
AJ2
SA_DQ51
AE21
SA_MA8
AL26
SA_DQ11
AK6
SA_DQ52
AA24
SA_MA9
AG30
SA_DQ12
AJ6
SA_DQ53
AG15
SA_RAS#
AG31
SA_DQ13
AK3
SA_DQ54
AC27
SA_RCVENIN#
372
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
AB26
AJ15
SA_RCVENOUT#
AE9
SA_WE#
AD7
SMOCDCOMP1
F18
VCCA_TVDACA
SMRCOMPN
G18
AJ14
SB_BS0
VCCA_TVDACA
AE7
SMRCOMPP
F19
VCCA_TVDACB
AG14
AL21
SB_BS1
Y30
SMVREF0
G19
VCCA_TVDACB
SB_BS2
AE1
SMVREF1
F20
VCCA_TVDACC
AJ13
SB_CAS#
Y24
SMXSLEWIN
G20
VCCA_TVDACC
AC12
SB_MA0
AA25
SMXSLEWOUT
AC3
VCCD_HMPLL1
AE14
SB_MA1
AC10
SMYSLEWIN
AC5
VCCD_HMPLL2
AF14
SB_MA10
AD10
SMYSLEWOUT
A23
VCCD_LVDS
AL20
SB_MA11
J18
THRMTRIP#
B23
VCCD_LVDS
AG20
SB_MA12
B17
TV_IRTNA
B25
VCCD_LVDS
AL13
SB_MA13
B18
TV_IRTNB
E18
VCCD_TVDAC
AC15
SB_MA2
B19
TV_IRTNC
D17
VCCDQ_TVDAC
AD14
SB_MA3
J19
TV_REFSET
B20
VCCHV
AG19
SB_MA4
A17
TVDAC_A
C21
VCCHV
AJ19
SB_MA5
C18
TVDAC_B
C22
VCCHV
AJ20
SB_MA6
A19
TVDAC_C
AC17
VCCSM
AK20
SB_MA7
L23
VCC
AC18
VCCSM
AL19
SB_MA8
L24
VCC
AC31
VCCSM
AH20
SB_MA9
M24
VCC
AD17
VCCSM
AH14
SB_RAS#
N23
VCC
AD18
VCCSM
AK14
SB_WE#
N24
VCC
AE17
VCCSM
G27
SDVOCTRL_CLK
P24
VCC
AE18
VCCSM
H27
SDVOCTRL_DATA
R15
VCC
AF1
VCCSM
AE31
SM_CK0
R17
VCC
AF17
VCCSM
AF31
SM_CK0#
T15
VCC
AF18
VCCSM
AF5
SM_CK1
T16
VCC
AG17
VCCSM
AE5
SM_CK1#
T17
VCC
AG18
VCCSM
AJ29
SM_CK3
U16
VCC
AH17
VCCSM
AJ28
SM_CK3#
H21
VCC_SYNC
AH18
VCCSM
AH5
SM_CK4
P31
VCC3G
AJ17
VCCSM
AJ5
SM_CK4#
R31
VCC3G
AJ18
VCCSM
AC23
SM_CKE0
M31
VCCA_3GBG
AK17
VCCSM
AC25
SM_CKE1
R23
VCCA_3GPLL
AK18
VCCSM
AH21
SM_CKE2
C20
VCCA_CRTDAC
AK30
VCCSM
AJ21
SM_CKE3
D21
VCCA_CRTDAC
AL17
VCCSM
AD11
SM_CS0#
B21
VCCA_DPLLA
AL18
VCCSM
AG13
SM_CS1#
J30
VCCA_DPLLB
AL23
VCCSM
AL14
SM_CS2#
AD1
VCCA_HPLL
AL6
VCCSM
AH12
SM_CS3#
B29
VCCA_LVDS
A26
VCCTX_LVDS
AF12
SM_ODT0
AC1
VCCA_MPLL
B26
VCCTX_LVDS
AG12
SM_ODT1
AC13
VCCA_SM
A15
VSS
AK13
SM_ODT2
AC14
VCCA_SM
A18
VSS
AJ12
SM_ODT3
AL15
VCCA_SM
A20
VSS
AB27
SMOCDCOMP0
E19
VCCA_TVBG
A25
VSS
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
373
Ballout and Package Information
R
Ball
Signal
Ball
Signal
Ball
Signal
A27
VSS
AK23
VSS
H11
VSS
AA2
VSS
AK26
VSS
H13
VSS
AA23
VSS
AK29
VSS
H18
VSS
AA26
VSS
AK5
VSS
H20
VSS
AA27
VSS
AK9
VSS
H23
VSS
AA7
VSS
B12
VSS
H26
VSS
AB28
VSS
B15
VSS
H30
VSS
AB30
VSS
B22
VSS
J17
VSS
AC24
VSS
B27
VSS
J20
VSS
AC28
VSS
B4
VSS
J22
VSS
AC9
VSS
B6
VSS
J4
VSS
AD12
VSS
B9
VSS
L2
VSS
AD15
VSS
C15
VSS
L25
VSS
AD19
VSS
C17
VSS
L27
VSS
AD2
VSS
C19
VSS
L29
VSS
AD21
VSS
C2
VSS
L4
VSS
AD5
VSS
C25
VSS
L6
VSS
AD9
VSS
C30
VSS
L8
VSS
AE10
VSS
C8
VSS
M23
VSS
AE11
VSS
D11
VSS
M25
VSS
AE13
VSS
D14
VSS
M27
VSS
AE26
VSS
D18
VSS
M29
VSS
AE30
VSS
D19
VSS
N25
VSS
AF11
VSS
D25
VSS
N27
VSS
AF15
VSS
E15
VSS
N29
VSS
AF19
VSS
E21
VSS
N31
VSS
AF23
VSS
E23
VSS
P2
VSS
AF28
VSS
E26
VSS
P23
VSS
AF30
VSS
E29
VSS
P25
VSS
AF7
VSS
E30
VSS
P27
VSS
AG2
VSS
E4
VSS
P29
VSS
AG21
VSS
E7
VSS
P4
VSS
AG25
VSS
F12
VSS
P6
VSS
AG3
VSS
F17
VSS
P8
VSS
AH10
VSS
F23
VSS
R16
VSS
AH13
VSS
F27
VSS
R24
VSS
AH15
VSS
G15
VSS
R25
VSS
AH19
VSS
G2
VSS
R26
VSS
AH6
VSS
G21
VSS
R27
VSS
AJ27
VSS
G22
VSS
R29
VSS
AJ3
VSS
G25
VSS
U15
VSS
AK12
VSS
G29
VSS
U17
VSS
AK15
VSS
G31
VSS
U23
VSS
AK19
VSS
G6
VSS
U25
VSS
AK21
VSS
G8
VSS
U27
VSS
374
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Ball
Signal
Ball
Signal
U29
VSS
N6
VTT
U31
VSS
N7
VTT
U4
VSS
N8
VTT
U7
VSS
N9
VTT
V1
VSS
Y1
VTT
V25
VSS
V27
VSS
V28
VSS
V30
VSS
V8
VSS
W24
VSS
W26
VSS
W28
VSS
W30
VSS
W6
VSS
Y23
VSS
Y25
VSS
Y26
VSS
Y29
VSS
Y31
VSS
Y4
VSS
Y9
VSS
A31
NC
L31
VSSA_3GBG
D20
VSSA_CRTDAC
E20
VSSA_TVBG
B30
VSSALVDS
G23
VSYNC
A12
VTT
A6
VTT
E1
VTT
M1
VTT
M2
VTT
M3
VTT
M4
VTT
M5
VTT
M6
VTT
M7
VTT
M8
VTT
M9
VTT
N1
VTT
N2
VTT
N3
VTT
N4
VTT
N5
VTT
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
375
Ballout and Package Information
R
13.6
Mobile Intel 91xM Series Express Chipset Family
Package Mechanical Information
13.6.1
Intel 915PM/GM/GME and 910GML/GMLE Package
Mechanical Information
The Intel 915GMCH comes in a Micro-FCBGA package, which is similar to the mobile processor
package. The package consists of a silicon die mounted face down on an organic substrate
populated with solder balls on the bottom side. Capacitors may be placed in the area surrounding
the die. Because the die-side capacitors are electrically conductive, and only slightly shorter than
the die height, care should be taken to avoid contacting the capacitors with electrically conductive
materials. Doing so may short the capacitors and possibly damage the device or render it
inactive.
The use of an insulating material between the capacitors and any thermal solution should be
considered to prevent capacitor shorting. An exclusion, or keep out area, surrounds the die and
capacitors, and identifies the contact area for the package. Care should be taken to avoid contact
with the package inside this area.
The Intel 915 package is a 1257 ball micro-FCBGA. Unless otherwise specified, interpret the
dimensions and tolerances in accordance with ASME Y14.5-1994. The dimensions are in
millimeters.
Tolerances:
• .X - ± 0.1
• .XX - ± 0.05
• Angles - ± 1.0 degrees
• Package parameters
• Die Size: 395mm x 395mm
• Land metal diameter: 630 microns
• Solder resist opening: 560 microns
376
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Figure 13-5. Mobile Intel 915PM/GM/GME/GL and 910GMLE Express Chipset Package MicroFCBGA
Figure 13-6. Mobile Intel 915PM/GM/GME/GL and 910GMLE Express Chipset Package Ball
Grid Array
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
377
Ballout and Package Information
R
Figure 13-7. Mobile Intel 915PM/GM/GME/GL and 910GMLE Express Chipset Package Top
View
378
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Figure 13-8. Mobile Intel 915PM/GM/GME/GL and 910GMLE Express Chipset Package Side
View
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
379
Ballout and Package Information
R
Figure 13-9. Mobile Intel 915PM/GM/GME/GL and 910GMLE Express Chipset Package Details
B&K
Figure 13-10. Recommended Via Stack Up for Platform (Standard Chipset Package)
12mil Cu web
in plane
4/4/4 mil internal stripline
trace/space in breakout region
30 mil max
anti-pad size
required to
maintain gnd
reference
16mil BGA pad
42mil BGA pitch
10/22/30 via
42mil BGA pitch
42mil via pitch
380
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
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13.7
Mobile Intel 915GMS Express Chipset Package
Mechanical Information
The Mobile Intel 915GMS Express Chipset comes in a Micro-FCBGA package, which is similar
to the mobile processor package. The package consists of a silicon die mounted face down on an
organic substrate populated with solder balls on the bottom side. Capacitors may be placed in the
area surrounding the die. Because the die-side capacitors are electrically conductive, and only
slightly shorter than the die height, care should be taken to avoid contacting the capacitors with
electrically conductive materials. Doing so may short the capacitors and possibly damage the
device or render it inactive.
The use of an insulating material between the capacitors and any thermal solution should be
considered to prevent capacitor shorting. An exclusion, or keep out area, surrounds the die and
capacitors, and identifies the contact area for the package. Care should be taken to avoid contact
with the package inside this area.
The Intel 915GMS package is an 840 ball micro-FCBGA. Unless otherwise specified, interpret
the dimensions and tolerances in accordance with ASME Y14.5-1994. The dimensions are in
millimeters.
Tolerances:
• .X - ± 0.1
• .XX - ± 0.05
• Angles - ± 1.0 degrees
Note: The ball array is not uniform and it is non-orthogonal. Mobile Intel 915GMS consists of
five regions. Four regions around the periphery and one region in the center. Each region has
different pin pitch characteristics to facilitate breakout routing.
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
381
Ballout and Package Information
R
Figure 13-11. Mobile Intel 915GMS Express Chipset Package Micro-FCBGA
Figure 13-12. Mobile Intel 915GMS Express Chipset Package Ball Grid Array
7.3152
(0.8128 x 9 = 7.3152)
17.2720
(1.016 x 17 = 17.2720)
2
1
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
7.3152
(0.8128 x 9 = 7.3152)
Y
W
V
T
U
R
P
N
M
17.2720
L
(1.0160 x 17 = 17.2720)
K
(A2, B1, B2, C1 and C2
H
ball locations are different
F
Refer Details "A")
J
G
AL1
5
8
AL5
AL6
AL7
AK3
AK5
AK6
AK7
AJ2
AJ3
AJ5
AJ6
AJ7
12
10
7
AL3
AK2
AJ1
9
14
13
11
16 18
20
22 24 26 28 30
15 17
19
23 25 27 29 31
21
AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL17 AL18 AL19 AL20 AL21
AL22
AL23
AL24
AL25
AL28
AL26
AL30
AL27
AL29
AL31
AH1 AH2 AH3 AH5
AH6
AG1 AG2 AG3 AG5
AG6
AF1 AF2
AF3
AF5
AF6
AK28
AK24
AK26
AK30
AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK17 AK18 AK19 AK20 AK21 AK22
AK27
AK29
AK31
AK23
AK25
AJ9 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22
AJ28
AJ24
AJ26
AJ30
AJ27
AJ29
AJ31
AJ23
AJ25
AH7 AH9 AH10 AH11 AH12 AH13 AH14 AH15 AH17 AH18 AH19 AH20 AH21
AG28
AG22
AG24
AG26
AG30
AG27
AG29
AG31
AG23
AG25
AG7 AG9 AG10 AG11 AG12 AG13 AG14 AG15 AG17 AG18 AG19 AG20 AG21
AF22
AF24
AF26
AF28
AF30
AF27
AF7 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF17 AF18 AF19 AF20 AF21
AF23
AF25
AF29
AF31
AE1
AE3
AE7
AE5
AE6
AD1 AD2 AD3 AD5
AD6
AD7
AC1 AC2 AC3 AC5
AC6
AC7
AB1
AB6
AB7
AE2
AB2
AB3
AB5
AE28
AE24
AE26
AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE17 AE18 AE19 AE20 AE21 AE22
AE30
AE27
AE23
AE25
AE29
AE31
AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD17 AD18 AD19 AD20 AD21 AC22
AC24
AC26
AC28
AC30
AC23
AC25
AC27
AC29
AC31
AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC17 AC18 AC19 AC20 AC21
AB22
AB24
AB26
AB28
AB30
AB27
AB23
AB25
AB29
AB31
AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB17 AB18 AB19 AB20 AB21
AA22
AA24
AA26
AA28
AA30
AA27
AA29
AA31
AA23
AA25
AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10
AA1 AA2
AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21
Y1
Y3
Y5
Y7
Y9
Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31
Y10
Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21
W1 W2 W3 W4 W5 W6 W7 W8 W9 W10
W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21
W22 W23 W24 W25 W26 W27 W28 W29 W30 W31
V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21
V22 V23 V24 V25 V26 V27 V28 V29 V30 V31
V1
U1
Y2
Y4
Y6
Y8
V2
V3
V4
V5
V6
V7
V8
V9
U2
U3
U4
U5
U6
U7
U8
U9 U10
R1
R2
R3
R4
R5
R6
R7
R8
R9 R10
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21
N1
N2
N3
N4
N5
N6
N7
N8
N9 N10
N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21
M1 M2 M3
M4 M5 M6
M7
M8 M9 M10
L1
L2
L3
L4
L5
L6
L7
L8
L9 L10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
G4 G5
G6
F5
F6
G1
G2 G3
F1
F2
F3
E
E1
C
C1
C2
C3
B1
B2
B3
E2
A2
1
A
3
AL2
AK1
B
A
D
6
4
2
E3
A3
3
F4
E4
C4
B4
A4
4
E5
C5
B5
A5
5
U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21
T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21
U22 U23 U24 U25 U26 U27 U28 U29 U30 U31
R22 R23 R24 R25 R26 R27 R28 R29 R30 R31
P22 P23 P24 P25 P26 P27 P28 P29 P30 P31
N22 N23 N24 N25 N26 N27 N28 N29 N30 N31
M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21
M22 M23 M24 M25 M26 M27 M28 M29 M30 M31
L16 L17 L18 L19 L20 L21
L22 L23 L24 L25 L26 L27 L28 L29 L30 L31
L11 L12 L13 L14 L15
K20
K21
K30
K31
J11
J12
J13
J14
J15
J17
J18
J19
J20
J21
J22
J23
J25
J26
J27
J29
J30
J31
H11
H12
H13
H14
H15
H17
H18
H19
H20 H21
H22
H23
H25
H26
H27
H29
H30 H31
G7
G8 G9 G10 G11
G12
G13
G14
G15
G17
G18
G19
G20
G22
G23
G25
G26
F7
F8
E6
E7
C6
C7
B6
B7
A6
A7
6
V10
7
E8
C8
B8
A8
8
F9
E9
F10
E10
C9 C10
B9
A9
9
K11
K12
K13
K14
K15
K17
K18
K19
G21
K22
K23
K25
K26
K27
G27
K29
G29 G30
G31
F11
F12
F13
F14
F15
F17
F18
F19
F20
F21
F22
F23
F25
F26
F27
F29
F30
F31
E11
E12
E13
E14
E15
E17
E18
E19
E20
E21
E22
E23
E25
E26
E27
E29
E30
E31
D11
D12
D13
D14
D15
D17
D18
D19
D20 D21
D22
D23
D25
D26
D27
D29
D30 D31
C11
C12
C13
C14
C15
C17
C18
C19
C20 C21
C22
C23
C25
C26
C27
C29
C30 C31
B10
B11
B12
B13
B14
B15
B17
B18
B19
B20
B21
B22
B23
B25
B26
B27
B29
B30
B31
A10
A11
A12
A13
A14
A15
A17
A18
A19
A20
A21
A22
A23
A25
A26
A27
A29
A30
A31
10
7.3152
11
12
13
14
15
AL
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
17.2720
(1.016 x 17 = 17.2720)
1.0160
M
L
K
J
H
G
F
E
D
C
B
A
7.3152
(0.8128 x 9 = 7.3152)
21
17
19
23 25 27 29 31
16 18
20
22 24 26 28 30
0.6984
REF (6 Places)
17.2720
(1.016 x 17 = 17.2720)
(0.8128 x 9 = 7.3152)
BOTTOM VIEW
AA11 AA12AA13 AA14 AA15 AA16 AA17 AA18 AA19AA20AA21
Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21
W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21
(1.016)
0.800 x 2 = 1.600
D
E
C
B
A
V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21
E1
E2
E3
U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21
T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
C1
B1
C2
B2
A2
1
2
C3
B3
R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21
C4
B4
(0.8630 x 10 = 8.6300)
N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21
M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21
L11 L12 L13
A3
8.6300
P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21
1.016 x 2 = 2.032
L14 L15 L16 L17 L18
L19 L20 L21
A4
3
DETAIL "A"
SCALE 2:1
8.6300
(0.8630 x 10 = 8.6300)
Center Array
Note: The center point of the ‘center’ ball T16 coincides with the center of the package. This should be
used as reference for the center ball array.
382
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Figure 13-13. Mobile Intel 915GMS Express Chipset Package Top View
C
27.00±0.050
Ø5.200
3.250 (2x)
4
3.098
10.043
3.250 (2x)
10.043
27.00±0.050
5.080
3
2.540
3.098
2
TOP VIEW
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
383
Ballout and Package Information
R
Figure 13-14. Mobile Intel 915GMS Express Chipset Package Side View
0.2000
A
1.1700
Min 0.800
SUBSTRATE
AK30
AJ30
AH30
AF30
AE30
AD30
AB30
C
AA30
Y30
W30
V30
U30
T30
R30
P30
N30
M30
L30
K30
J30
H30
G30
DIE
F30
E30
B
D30
C30
B30
A30
(2.010)
SIDE VIEW
(UNMOUNTED PKG)
Figure 13-15. Mobile Intel 915GMS Express Chipset Package Details B & C
384
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
Ballout and Package Information
R
Figure 13-16. Recommended Via Stack Up for Platform (Small Factor Chipset Package)
12mil Cu
web in plane
4/4/4 mil stripline trace/space
in breakout region
28 mil max
antipad size
required to
maintain gnd
reference
16mil BGA pad
Breakout
32mil BGA
pitch (parallel
to breakout)
10/22/28 via
40mil BGA pitch
(perpendicular to
breakout)
For the Intel 915GMS, optimal solder joint reliability requires 16-mil diameter pads through out
the small form factor board pattern. Reducing pad diameters will have an adverse impact on
solder joint reliability and could affect component warrantee.
§
Mobile Intel® 915 and 910 Express Chipset Family of Products Datasheet
385
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