AX8052F143 D

AX8052F143

SoC Ultra-Low Power

RF-Microcontroller for RF

Carrier Frequencies in the

Range 27 - 1050 MHz

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OVERVIEW

Features

SoC Ultra−low Power Advanced Narrow−band

RF−microcontroller for Wireless Communication

Applications

QFN40 Package

Supply Range 1.8 V − 3.6 V

−40

°C to 85°C

Ultra−low Power Consumption:

CPU Active Mode 150 mA/MHz

Sleep Mode with 256 Byte RAM Retention and

Wake−up Timer running 900 nA

Sleep Mode 4 kByte RAM Retention and Wake−up

Timer running 1.5 mA

Sleep Mode 8 kByte RAM Retention and Wake−up

Timer running 2.2 mA

Radio RX−mode

6.5 mA @ 169 MHz

9.5 mA @ 868 MHz and 433 MHz

Radio TX−mode at 868 MHz

7.5 mA @ 0 dBm

16 mA @ 10 dBm

48 mA @ 16 dBm

AX8052

Ultra−low Power MCU Core Compatible with Industry

Standard 8052 Instruction Set

Down to 500 nA Wake−up Current

Single Cycle/Instruction for many Instructions

64 kByte In−system Programmable FLASH

Code Protection Lock

8.25 kByte SRAM

3−wire (1 dedicated, 2 shared) In−circuit Debug

Interface

Three 16−bit Timers with SD Output Capability

Two 16−bit Wakeup Timers

Two Input Captures

Two Output Compares with PWM Capability

10−bit 500 ksample/s Analog−to−Digital Converter

Temperature Sensor

Two Analog Comparators

Two UARTs

One General Purpose Master/Slave SPI

Two Channel DMA Controller

Multi−megabit/s AES Encryption/Decryption Engine, supports AES−128, AES−192 and AES−256 with True

Random Number Generator (TRNG)

NOTE: The AES Engine and the TRNG require

Software Enabling and Support.

Ultra−low Power 10 kHz/640 Hz Wakeup Oscillator, with Automatic Calibration against a Precise Clock

Internal 20 MHz RC Oscillator, with Automatic

Calibration against a Precise Clock for Flexible System

Clocking

Low Frequency Tuning Fork Crystal Oscillator for

Accurate Low Power Time Keeping

Brown−out and Power−on−Reset Detection

High Performance Narrow−band RF Transceiver compatible to AX5043 (FSK/MSK/4−FSK/GFSK/GMSK/

ASK/AFSK/FM/PSK)

Receiver

Carrier Frequencies from 27 to 1050 MHz

Data Rates from 0.1 kbps to 125 kbps

Optional Forward Error Correction (FEC)

Sensitivity without FEC

−135 dBm @ 0.1 kbps, 868 MHz, FSK

−126 dBm @ 1 kbps, 868 MHz, FSK

−117 dBm @ 10 kbps, 868 MHz, FSK

−107 dBm @ 100 kbps, 868 MHz, FSK

−105 dBm @ 125 kbps, 868 MHz, FSK

−138 dBm @ 0.1 kbps, 868 MHz, PSK

−130 dBm @ 1 kbps, 868 MHz, PSK

−120 dBm @ 10 kbps, 868 MHz, PSK

−109 dBm @ 100 kbps, 868 MHz, PSK

−108 dBm @ 125 kbps, 868 MHz, PSK

© Semiconductor Components Industries, LLC, 2015

November, 2015 − Rev. 3

1

Publication Order Number:

AX8052F143/D

AX8052F143

Sensitivity with FEC

−137 dBm @ 0.1 kbps, 868 MHz, FSK

−122 dBm @ 5 kbps, 868 MHz, FSK

−111 dBm @ 50 kbps, 868 MHz, FSK

High Selectivity Receiver with up to 47 dB Adjacent

Channel Rejection

0 dBm Maximum Input Power

±10% Data−rate Error Tolerance

Support for Antenna Diversity with External

Antenna Switch

Short Preamble Modes allow the Receiver to work with as little as 16 Preamble Bits

Fast State Switching Times

200 ms TX → RX Switching Time

62 ms RX → TX Switching Time

Transmitter

Carrier Frequencies from 27 to 1050 MHz

Data−rates from 0.1 kbps to 125 kbps

High Efficiency, High Linearity Integrated Power

Amplifier

Maximum Output Power

16 dBm @ 868 MHz

16 dBm @ 433 MHz

16 dBm @ 169 MHz

Power Level programmable in 0.5 dB Steps

GFSK Shaping with BT=0.3 or BT=0.5

Unrestricted Power Ramp Shaping

RF Frequency Generation

Configurable for Usage in 27 MHz −1050 MHz

Bands

RF Carrier Frequency and FSK Deviation

Programmable in 1 Hz Steps

Ultra Fast Settling RF Frequency Synthesizer for

Low−power Consumption

Fully Integrated RF Frequency Synthesizer with

VCO Auto−ranging and Band−width Boost Modes for Fast Locking

Configurable for either Fully Integrated VCO,

Internal VCO with External Inductor or Fully

External VCO

Configurable for either Fully Integrated or External

Synthesizer Loop Filter for a Large Range of

Bandwidths

Channel Hopping up to 2000 hops/s

Automatic Frequency Control (AFC)

Flexible Antenna Interface

Integrated RX/TX Switching with Differential

Antenna Pins

Mode with Differential RX Pins and Single−ended

TX Pin for Usage with External PAs and for

Maximum PA Efficiency at Low Output Power

Wakeup−on−Radio

640 Hz or 10 kHz Lowest Power Wake−up Timer

Wake−up Time Interval programmable between

98 ms and 102 s

Sophisticated Radio Controller

Antenna Diversity and RX/TX Switch Control

Fully Automatic Packet Reception and Transmission without Micro−controller Intervention

Supports HDLC, Raw, Wireless M−Bus Frames and

Arbitrary Defined Frames

Automatic Channel Noise Level Tracking ms Resolution Timestamps for Exact Timing (eg. for

Frequency Hopping Systems)

256 Byte Micro−programmable FIFO, optionally supports Packet Sizes > 256 Bytes

Three Matching Units for Preamble Byte,

Sync−word and Address

Ability to store RSSI, Frequency Offset and

Data−rate Offset with the Packet Data

Multiple Receiver Parameter Sets allow the use of more aggressive Receiver Parameters during

Preamble, dramatically shortening the Required

Preamble Length at no Sensitivity Degradation

Advanced Crystal Oscillator (RF Reference Oscillator)

Fast Start−up and Lowest Power Steady−state XTAL

Oscillator for a Wide Range of Crystals

Integrated Tuning Capacitors

Possibility of Applying an External Clock Reference

(TCXO)

Applications

27 − 1050 MHz Licensed and Unlicensed Radio Systems

Internet of Things

Automatic meter reading (AMR)

Security applications

Building automation

Wireless networks

Messaging Paging

Compatible with: Wireless M−Bus, POCSAG, FLEX,

KNX, Sigfox, Z−Wave, enocean

Regulatory Regimes: EN 300 220 V2.3.1 including the

Narrow−band 12.5 kHz, 20 kHz and 25 kHz

Definitions; EN 300 422; FCC Part 15.247; FCC Part

15.249; FCC Part 90 6.25 kHz, 12.5 kHz and 25 kHz

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2

AX8052F143

BLOCK DIAGRAM

ANTP

ANTN

ANTP1

LNA

PA diff

Mixer

IF Filter and

AGC PGAs

AX8052F143

ADC

Digital IF

Channel

Filter

Demodulator

RSSI

AGC

Modulator

PA se

Radio configuration

POR, references low power oscillator

640 Hz/ 10 kHz

Communication Controller &

Radio Interface Controller

Wake on Radio

L1

L2

FILT

CLK16P

CLK16N

VDD_ANA

VDD_IO

RF Frequency

Generation

Subsystem

F

OUT

F

XTAL

Crystal

Oscillator typ. 16MHz

Divider

Voltage

Regulator

GPIO

SYSCLK

DBG_EN

RESET_N

GND

VDD_IO wakeup oscillator

RC Oscillator tuning fork crystal oscillator

FLASH

64k

DMA

Controller

8k

256

Axsem

8052

Debug

Interface

System

Controller wakeup timer 2x

Reset, Clocks, Power

AES

Crypto Engine

ADC

Comparators

Temp Sensor

SPI master/slave

Timer

Counter 0

Timer

Counter 1

Timer

Counter 2

Output

Compare0

Output

Compare 1

Input

Capture 0

Input

Capture 1

UART 0

UART 1

I/O Multiplexer

Figure 1. Functional Block Diagram of the AX8052F143

PA0

PA1

PA2

PA3

PA4

PA5

PC0

PC1

PC2

PC3

PC4

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

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3

AX8052F143

Table 1. PIN FUNCTION DESCRIPTIONS

Symbol

PB3

PB4

PB5

PB6

PC0

PB0

PB1

PB2

PB7

DBG_EN

RESET_N

GND

VDD_IO

PA0

PA1

PA2

PA3

PA4

PA5

VDD_IO

TST1

TST2

CLK16N

CLK16P

GND

PC4

PC3

PC2

PC1

FILT

L2

L1

SYSCLK

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

GND

Pin(s)

29

30

31

32

25

26

27

28

21

22

23

24

17

18

19

20

33

34

35

36

37

38

39

40

Center pad

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

Type

I/O/PU

I/PD

I/PU

P

P

I/O/A/PU

I/O/A/PU

I/O/A/PU

I/O/PU

I/O/PU

I/O/PU

I/O/PU

I/O/PU

I/O/PU

I/O/PU

I/O/PU

I/O/A/PU

I/O/A/PU

I/O/A/PU

P

A

A

A

A

P

A

A

A

I/O/PU

I/O/PU

I/O/PU

I/O/PU

I/O/PU

P

P

A

P

A

A

P

P

Description

Analog power output, decouple to neighboring GND

Ground, decouple to neighboring VDD_ANA

Differential antenna input/output

Differential antenna input/output

Single−ended antenna output

Ground, decouple to neighboring VDD_ANA

Analog power output, decouple to neighboring GND

Ground

Optional synthesizer filter

Optional synthesizer inductor

Optional synthesizer inductor

System clock output

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO, DBG_DATA

General purpose IO, DBG_CLK

In−circuit debugger enable

Optional reset pin. If this pin is not used it must be connected to VDD_IO

Ground

Unregulated power supply

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

General purpose IO

Unregulated power supply

Must be connected to GND

Must be connected to GND

Crystal oscillator input/output (RF reference oscillator)

Crystal oscillator input/output (RF reference oscillator)

Ground on center pad of QFN, must be connected

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4

A = analog input

I = digital input signal

O = digital output signal

PU = pull−up

I/O = digital input/output signal

N = not to be connected

P = power or ground

PD = pull−down

Table 2. ALTERNATE PIN FUNCTIONS

GPIO

PB6

PB7

PC0

PC1

PB2

PB3

PB4

PB5

PA4

PA5

PB0

PB1

PA0

PA1

PA2

PA3

PC2

PC3

PC4

IC0

OC0

U0TX

U0RX

DBG_DATA

DBG_CLK

SSEL

SSCK

T0OUT

T0CLK

OC0

T1OUT

T1CLK

IC0

U1TX

U1RX

SMOSI

SMISO

COMPO1

IC1

OC1

U1RX

COMPO0

U1TX

IC1

OC1

T2OUT

T2CLK

T1CLK

T1OUT

T0OUT

T0CLK

U0TX

U0RX

ADCTRIG

AX8052F143

All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL compatible. Port A

Pins (PA0 − PA7) must not be driven above VDD_IO, all other digital inputs are 5 V tolerant. Pull−ups are programmable for all GPIO pins.

Alternate Pin Functions

GPIO Pins are shared with dedicated Input/Output signals of on−chip peripherals. The following table lists the available functions on each GPIO pin.

Alternate Functions

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

EXTIRQ0

EXTIRQ1

EXTIRQ0

COMPO1

COMPO0

EXTIRQ1

COMPI00

LPXTALP

LPXTALN

COMPI10

DSWAKE

PWRAMP

ANTSEL

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5

Pinout Drawing

AX8052F143

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

GND

1

2

3

4

5

6

7

8

40 39 38 37 36 35 34 33 32 31 30 29

AX8052F143

QFN40

9 10 11 12 13 14 15 16 17 18 19 20

28

GND

27

26

RESET_N

DBG_EN

25

24

PB7/DBG_CLK

PB6/DBG_DATA

23

22

PB5/U0RX/T1OUT

PB4/U0TX/T1CLK

21

PB3/OC0/T2CLK/EXTIRQ1/DSWAKE/

ANTSEL

Figure 2. Pinout Drawing (Top View) www.onsemi.com

6

AX8052F143

SPECIFICATIONS

Table 3. ABSOLUTE MAXIMUM RATINGS

Symbol Description Condition Min Max Units

VDD_IO

IDD

P tot

P i

Supply voltage

Supply current

Total power consumption

Absolute maximum input power at receiver input

−0.5

5.5

200

800

10

V mA mW dBm ANTP and ANTN pins in RX mode

I

I1

I

I2

I

O

V ia

DC current into any pin except ANTP, ANTN, ANTP1

DC current into pins ANTP, ANTN, ANTP1

Output Current

Input voltage ANTP, ANTN, ANTP1 pins

Input voltage digital pins

−10

−100

−0.5

−0.5

10

100

40

5.5

5.5

mA mA mA

V

V

V es

T amb

Electrostatic handling

Operating temperature

HBM −2000

−40

2000

85

V

°C

T stg

Storage temperature −65 150 °C

T j

Junction Temperature 150 °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.

1. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC Characteristics

Table 4. SUPPLIES

Sym

T

AMB

VDD

IO

VDD

IO_R1

VDD

IO_R2

Description

Operational ambient temperature

I/O and voltage regulator supply voltage

I/O voltage ramp for reset activation;

Note 1

I/O voltage ramp for reset activation;

Note 1

Condition

Ramp starts at VDD_IO ≤ 0.1 V

Ramp starts at 0.1 V < VDD_IO < 0.7 V

Min

−40

1.8

0.1

3.3

Typ

27

3.0

Max Units

85

3.6

°C

V

V/ms

V/ms

V

BOUT

I

DS

I

SL256P

I

SL256

I

SL4K

I

SL8K

I

RX

Brown−out threshold

Deep Sleep current

Sleep current, 256 Bytes RAM retained

Sleep current, 256 Bytes RAM retained

Sleep current, 4.25 kBytes RAM retained

Sleep current, 8.25 kBytes RAM retained

Current consumption RX

RF frequency generation subsystem:

Internal VCO and internal loop−fiter

Note 2

Wakeup from dedicated pin

Wakeup Timer running at 640 Hz

Wakeup Timer running at 640 Hz

Wakeup Timer running at 640 Hz

868 MHz, datarate 6 kbps

169 MHz, datarate 6 kbps

868 MHz, datarate 100 kbps

169 MHz, datarate 100 kbps

1.3

100

500

900

1.5

2.2

9.5

6.5

11

7.5

I

TX−DIFF

Current consumption TX differential

868 MHz, 16 dBm, FSK, Note 3

RF frequency generation subsystem:

Internal VCO and internal loop−filter

Antenna configuration:

Differential PA, internal RX/TX switch

48 mA

1. If VDD_IO ramps cannot be guaranteed, an external reset circuit is recommended, see the AX8052 Application Note: Power On Reset

2. Digital circuitry is functional down to typically 1 V.

3. Measured with optimized matching networks.

V nA nA nA mA mA mA

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AX8052F143

Table 4. SUPPLIES

Sym

I

RX−SE

Description

Current consumption TX single ended

Condition

868 MHz, 0 dBm, FSK, Note 3

RF frequency generation subsystem:

Internal VCO and internal loop−filter

Antenna configuration:

Single ended PA, external RX/TX switching

Min Typ

7.5

Max Units

mA

I

I

I

MCU

VSUP

LPXTAL

Microcontroller running power consumption

Voltage supervisor

Crystal oscillator current

(RF reference oscillator)

All peripherals disabled

Run and standby mode

16 MHz

150

85

160 mA/

MHz mA mA

I

I

I

LFXTAL

RCOSC

LPOSC

Low frequency crystal oscillator current

Internal oscillator current

Internal Low Power Oscillator current

32 kHz

20 MHz

10 kHz

640 Hz

700

210

650

210 nA mA nA nA

I

I

ADC

WOR

ADC current

Typical wake−on−radio duty cycle current

311 kSample/s, DMA 5 MHz

1s, 100 kbps

1.1

6 mA mA

1. If VDD_IO ramps cannot be guaranteed, an external reset circuit is recommended, see the AX8052 Application Note: Power On Reset

2. Digital circuitry is functional down to typically 1 V.

3. Measured with optimized matching networks.

For information on current consumption in complex modes of operation tailored to your application, see the software AX−RadioLab.

Note on current consumption in TX mode

To achieve best output power the matching network has to be optimized for the desired output power and frequency. As a rule of thumb a good matching network produces about

50% efficiency with the AX8052F143 power amplifier although over 90% are theoretically possible. A typical matching network has between 1 dB and 2 dB loss (P loss

).

The theoretical efficiencies are the same for the single ended

PA (ANTP1) and differential PA (ANTP and ANTN) therefore only one current value is shown in the table below.

We recommend to use the single ended PA for low output power and the differential PA for high power. The differential PA is internally multiplexed with the LNA on pins ANTP and ANTN. Therefore constraints for the RX matching have to be considered for the differential PA matching.

The current consumption can be calculated as

I

TX

[mA] +

1

PA efficiency

10

Pout[dBm])Ploss[dB]

10

B 1.8V ) I offset

I offset

is about 6 mA for the fully integrated VCO at 400

MHz to 1050 MHz, and 3 mA for the VCO with external inductor at 169 MHz. The following table shows calculated current consumptions versus output power for P

PA efficiency

= 0.5, I offset

3.5 mA at 169 MHz.

loss

= 1 dB,

= 6 mA at 868 MHz and I offset

=

11

12

13

14

15

9

10

7

8

Pout [dBm]

0

1

2

5

6

3

4

Table 5. CURRENT CONSUMPTION VS. OUTPUT

POWER

868 MHz

30.3

36.7

44.6

54.6

15.7

18.2

21.3

25.3

9.8

10.8

12.1

13.7

7.5

7.9

8.4

9.0

I txcalc

[mA]

169 MHz

27.3

33.7

41.6

51.6

12.7

15.2

18.3

22.3

6.8

7.8

9.1

10.7

4.5

4.9

5.4

6.0

Both AX8052F143 power amplifiers run from the regulated VDD_ANA supply and not directly from the battery. This has the advantage that the current and output power do not vary much over supply voltage and temperature.

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AX8052F143

Table 6. LOGIC

I

Symbol

Digital Inputs

OL

Description

I

V

T+

V

T−

V

IL

V

IH

Schmitt trigger low to high threshold point

Schmitt trigger high to low threshold point

Input voltage, low

Input voltage, high

V

IPA

V

IPBC

I

L

R

PU

Input voltage range, Port A

Input voltage range, Ports B, C

Input leakage current

Programmable Pull−Up Resistance

Digital Outputs

I

OH

OL

Output Current, high

Ports PA, PB and PC

Output Current, low

Ports PA, PB and PC

I

OH

Output Current, high

Pin SYSCLK

Output Current, low

Pin SYSCLK

I

OZ

Tri−state output leakage current

Condition

VDD_IO = 3.3 V

V

OH

= 2.4 V

V

OL

= 0.4 V

V

OH

= 2.4 V

V

OL

= 0.4 V

Min

4

4

8

8

−10

2.0

−0.5

−0.5

−10

Typ

1.55

1.25

65

Max

0.8

VDD_IO

5.5

10

10

Units

AC Characteristics

Table 7. CRYSTAL OSCILLATOR (RF REFERENCE OSCILLATOR)

Symbol

f

XTAL gm osc

C osc

Description

Crystal or frequency

Oscillator transconductance range

Programmable tuning capacitors at pins

CLK16N and CLK16P

Condition

Note 1, 2, 3

Self−regulated see note 4

AX5043_XTALCAP = 0x00 default

Min

10

0.2

Typ

16

3

Max

50

20

Units

MHz mS pF

C osc−lsb

Programmable tuning capacitors, increment per LSB of AX5043_XTALCAP

AX5043_XTALCAP = 0x01

AX5043_XTALCAP = 0xFF

AX5043_XTALCAP = 0x01

– 0xFF

8.5

40

0.5

pF pF pF f ext

External clock input (TCXO) Note 2, 3, 5 10 16 50 MHz

RIN osc

Input DC impedance 10 kW

NDIV

SYSCLK

Divider ratio f

SYSCLK

= F

XTAL

/ NDIV

SYSCLK

2

0

2

4

2

10

1. Tolerances and start−up times depend on the crystal used. Depending on the RF frequency and channel spacing the IC must be calibrated to the exact crystal frequency using the readings of the register AX5043_TRKFREQ.

2. The choice of crystal oscillator or TCXO frequency depends on the targeted regulatory regime for TX, see separate documentation on meeting regulatory requirements.

3. To avoid spurious emission, the crystal or TCXO reference frequency should be chosen so that the RF carrier frequency is not an integer multiple of the crystal or TCXO frequency.

4. The oscillator transconductance is regulated for fastest start−up time during start−up and for lowest power curing steady state oscillation.

This means that values depend on the crystal used.

5. If an external clock or TCXO is used, it should be input via an AC coupling at pin CLK16P with the oscillator powered up and

AX5043_XTALCAP = 000000. For detailed TCXO network recommendations depending on the TCXO output swing refer to the AX5043

Application Note: Use with a TCXO Reference Clock.

V

V mA kW

V

V

V

V mA mA mA mA mA

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AX8052F143

Table 8. LOW−POWER OSCILLATOR (TRANSCEIVER WAKE ON RADIO CLOCK)

Symbol

f osc−slow f osc−fast

Description

Oscillator frequency slow mode

LPOSC FAST = 0 in

AX5043_LPOSCCONFIG register

Oscillator frequency fast mode

LPOSC FAST = 1 in

AX5043_LPOSCCONFIG register

Condition

No calibration

Internal calibration vs. crystal clock has been performed

No calibration

Internal calibration vs. crystal clock has been performed

Min

480

630

7.6

9.8

Typ

640

640

10.2

10.2

Max

800

650

12.8

10.8

Units

Hz kHz

Table 9. RF FREQUENCY GENERATION SUBSYSTEM (SYNTHESIZER)

Symbol

f

REF

Description

Reference frequency

Condition

The reference frequency must be chosen so that the RF carrier frequency is not an integer multiple of the reference frequency

Dividers

NDIV ref

Reference divider ratio range

NDIV m

Main divider ratio range

Controlled directly with bits REFDIV in register AX5043_PLLVCODIV

Controlled indirectly with register

AX5043_FREQ

NDIV

RF

RF divider range Controlled directly with bit RFDIV in register AX5043_ PLLVCODIV

I

Charge Pump

CP

Charge pump current Programmable in increments of 8.5 mA via register AX5043_PLLCPI f

Internal VCO (VCOSEL = 0)

f f

RF step

RF frequency range

RF frequency step

RFDIV = 1

RFDIV = 0 f

RFDIV = 1

REF

= 16.000000 MHz

BW

T start

Synthesizer loop bandwidth

Synthesizer start−up time if crystal oscillator and reference are running

The synthesizer loop bandwidth an start−up time can be programmed with the registers AX5043_PLLLOOP and

AX5043_PLLCPI.

For recommendations see the AX5043

Programming Manual, the AX−RadioLab software and AX5043 Application Notes on compliance with regulatory regimes.

10 kHz from carrier PN868 f

Synthesizer phase noise 868 MHz

REF

= 48 MHz

PN433 f

Synthesizer phase noise 433 MHz

REF

= 48 MHz

1 MHz from carrier

10 kHz from carrier

1 MHz from carrier

VCO with external inductors (VCOSEL = 1, VCO2INT = 1)

f

RFrng_lo

RFrng_hi

PN169

RF frequency range

For choice of L ext

values as well as

VCO gains see Figure 3 and

Figure 4

Synthesizer phase noise 169 MHz

L ext

=47 nH (wire wound 0603)

AX5043_RFDIV = 0, f

REF

= 16 MHz

Note: phase noises can be improved with higher f

REF

RFDIV = 1

RFDIV = 0

10 kHz from carrier

1 MHz from carrier

Min

10

Typ

16

2

0

4.5

1

8.5

400

800

50

5

27

54

0.98

−95

−120

−105

−120

−97

−115

Max

50

2168

525

1050

500

25

262

525

2

3

66.5

2

Units

MHz mA

MHz

Hz kHz ms dBc/Hz dBc/Hz

MHz dBc/Hz

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AX8052F143

Table 9. RF FREQUENCY GENERATION SUBSYSTEM (SYNTHESIZER)

Symbol Description Condition

External VCO (VCOSEL = 1, VCO2INT = 0)

f

RF

RF frequency range fully external

VCO

V amp

Differential input amplitude at L1, L2 terminals

V inL

V ctrl

Input voltage levels at L1, L2 terminals

Control voltage range

Note: The external VCO frequency needs to be 2 x f

RF

Available at FILT in external loop filter mode

Min Typ Max Units

27

0

0

0.7

1000

1.8

1.8

MHz

V

V

V

Figure 3. VCO with External Inductors: Typical Frequency vs. L ext www.onsemi.com

11

AX8052F143

Figure 4. VCO with External Inductors: Typical K

VCO

vs. L ext

Lext [nH]

18

18

22

22

27

27

12

12

15

15

8.2

8.2

10

10

The following table shows the typical frequency ranges for frequency synthesis with external VCO inductor for different inductor values.

Table 10.

Freq [MHz]

RFDIV = 0

345

313

308

280

285

258

415

377

380

345

482

437

432

390

Freq [MHz]

RFDIV = 1

173

157

154

140

143

129

208

189

190

173

241

219

216

195

PLL Range

0

15

0

14

0

15

0

15

0

15

0

15

0

15

1

14

0

14

0

15

1

14

0

14

0

15

0

15

0

14

75

68

68

62

89

81

80

73

106

97

101

91

130

118

123

112

149

136

136

124

178

161

160

146

212

194

201

182

260

235

245

223

100

100

120

120

68

68

82

82

47

47

56

56

33

33

39

39

For tuning or changing of ranges a capacitor can be added in parallel to the inductor.

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12

AX8052F143

Table 11. TRANSMITTER

Symbol

SBR

PTX

Description

Signal bit rate

Transmitter power @ 868 MHz

Transmitter power @ 433 MHz

Transmitter power @ 169 MHz

Programming step size output power

Transmitter power variation vs.

temperature

Condition

Differential PA, 50 W single ended measurement at an

SMA connector behind the matching network, Note 2

Min

0.1

−10

−10

−10

Typ Max

125

16

16

16

0.5

Units

kbps dBm

PTX dTX step temp

Note 1

−40°C to +85°C

Note 2

± 0.5

dB dB dTX

Vdd

Transmitter power variation vs. VDD_IO 1.8 to 3.6 V

Note 2

± 0.5

dB

Padj Adjacent channel power

GFSK BT = 0.5, 500 Hz deviation,

1.2 kbps, 25 kHz channel spacing,

10 kHz channel BW

868 MHz

433 MHz

−44

−51 dBc

PTX

868−harm2

PTX

868−harm3

Emission @ 2 nd

harmonic

Emission @ 3 rd

harmonic

868 MHz, Note 2 −40

−60 dBc

PTX

433−harm2

PTX

433−harm3

Emission @ 2

Emission @ 3 nd rd

harmonic

harmonic

433 MHz, Note 2 −40

−40

1. P out

+

AX5043_TXPWRCOEFFB

2

12

*1

P max

2. 50 W single ended measurements at an SMA connector behind the matching network. For recommended matching networks see

Applications section. dBc

Table 12. RECEIVER SENSITIVITIES

The table lists typical input sensitivities (without FEC) in dBm at the SMA connector with the complete matching network for BER=10

−3 at

433 or 868 MHz.

Data rate

[kbps]

FSK h = 0.66

FSK h = 1

FSK h = 2

FSK h = 4

FSK h = 5

FSK h = 8

FSK h = 16

PSK

0.1

1

10

Sensitivity [dBm]

RX Bandwidth [kHz]

Deviation [kHz]

Sensitivity [dBm]

RX Bandwidth [kHz]

Deviation [kHz]

Sensitivity [dBm]

RX Bandwidth [kHz]

−135

0.2

0.033

−126

1.5

0.33

−117

15

−134.5

0.2

0.05

−125

2

0.5

−116

20

−132.5

0.3

0.1

−123

3

1

−113

30

10

−133

0.5

0.2

−123.5

6

2

−114

50

20

−133.5

0.6

0.25

−124

7

2.5

−113.5

60

25

−133

0.9

0.4

−123.5

11

4

−113

110

40

−132.5

2.1

0.8

−122.5

21

8

−138

0.2

−130

1

−120

10

100

Deviation [kHz]

Sensitivity [dBm]

RX Bandwidth [kHz]

Deviation [kHz]

3.3

−107

150

33

5

−105.5

200

50

−109

100

125 Sensitivity [dBm]

RX Bandwidth [kHz]

−105

187.5

−104

200

−108

125

Deviation [kHz] 42.3

62.5

1. Sensitivities are equivalent for 1010 data streams and PN9 whitened data streams.

2. RX bandwidths < 0.9 kHz cannot be achieved with an 48 MHz TCXO. A 16 MHz TCXO was used for all measurements at 0.1 kbps.

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13

AX8052F143

Table 13. RECEIVER

Symbol

SBR

IS

BER868

Description

Signal bit rate

Input sensitivity at

BER = 10

−3 for 868 MHz operation, continuous data, without FEC

Condition Min

0.1

Typ Max

125

Units

kbps dBm

IS

IS

BER868FEC

PER868

Input sensitivity at

BER = 10

−3

, for 868 MHz operation, continuous data, with FEC

Input sensitivity at

PER = 1%, for 868 MHz operation, 144 bit packet data, without FEC

FSK, h = 0.5, 100 kbps

FSK, h = 0.5, 10 kbps

FSK, 500 Hz deviation, 1.2 kbps

PSK, 100 kbps

PSK, 10 kbps

PSK, 1 kbps

FSK, h = 0.5, 50 kbps

FSK, h = 0.5, 5 kbps

FSK, 0.1 kbps

FSK, h = 0.5, 100 kbps

FSK, h = 0.5, 10 kbps

FSK, 500 Hz deviation, 1.2 kbps

FSK, h= 0.5, 100 kpbs

−106

−116

−126

−109

−120

−130

−111

−122

−137

−103

−115

−125

−102 dBm dBm

IS

IL

WOR868

CP

1dB

RSSIR

RSSIS

RSSIS

RSSIS

1

2

3

Input sensitivity at

PER = 1% for 868 MHz operation, WOR−mode, without

FEC

Maximum input level

Input referred compression point

RSSI control range

RSSI step size

RSSI step size

RSSI step size

Full selectivity

FSK, reduced selectivity

2 tones separated by 100 kHz

FSK, 500 Hz deviation,

1.2 kbps

Before digital channel filter; calculated from register AX5043_AGCCOUNTER

Behind digital channel filter; calculated from registers AX5043_AGCCOUNTER,

AX5043_TRKAMPL

Behind digital channel filter; reading register AX5043_RSSI

−126

0

10

−35

0.625

0.1

1

−46 dBm dBm dBm dB dB dB dB

SEL

BLK

R

868

868

AFC

Adjacent channel suppression

Blocking at ± 10 MHz offset

AFC pull−in range

25 kHz channels , Note 1

100 kHz channels, Note 1

Note 2

The AFC pull−in range can be programmed with the

AX5043_MAXRFOFFSET registers.

The AFC response time can be programmed with the

AX5043_FREQGAIND register.

± 15

45

47

78 dB dB

%

R

DROFF

Bitrate offset pull−in range The bitrate pull−in range can be programmed with the

AX5043_MAXDROFFSET registers.

± 10 %

1. Interferer/Channel @ BER = 10

−3

, channel level is +3 dB above the typical sensitivity, the interfering signal is CW; channel signal is modulated with shaping

2. Channel/Blocker @ BER = 10 with shaping

−3

, channel level is +3 dB above the typical sensitivity, the blocker signal is CW; channel signal is modulated

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AX8052F143

Table 14. RECEIVER AND TRANSMITTER SETTLING PHASES

Symbol

T xtal

T synth

T tx

Description

XTAL settling time

Synthesizer settling time

TX settling time

Condition

Powermodes:

POWERDOWN to STANDBY

Note that T xtal crystal used.

depends on the specific

Powermodes:

STANDBY to SYNTHTX or SYNTHRX

Powermodes:

SYNTHTX to FULLTX

T tx

is the time used for power ramping, this can be programmed to be 1 x t bit

, 2 x t bit

,

4 x t bit

Note 1

or 8 x t bit

.

T

T rx_init rx_rssi

RX initialization time

RX RSSI acquisition time

(after T rx_init

)

Powermodes:

SYNTHRX to FULLRX

T e rx_preambl

RX signal acquisition time to valid data RX at full sensitivity/selectivity

(after T rx_init

)

Modulation (G)FSK

Note 1

1. t bit depends on the datarate, e.g. for 10 kbps t bit

= 100 ms

Min

0

Typ

0.5

40

1 x t bit

8 x t bit

150

80 +

3 x t bit

9 x t bit

Max Units

ms ms ms ms ms

Table 15. OVERALL STATE TRANSITION TIMES

Symbol

T tx_on

Description

TX startup time

T rx_on

T rx_rssi

RX startup time

RX startup time to valid RSSI

Condition

Powermodes:

STANDBY to FULLTX

Note 1

Powermodes:

STANDBY to FULLRX

Powermodes:

STANDBY to FULLRX

T

T rx_data rxtx

RX startup time to valid data at full sensitivity/selectivity

RX to TX switching

Modulation (G)FSK

Note 1

Powermodes:

FULLRX to FULLTX

Powermodes:

FULLTX to FULLRX

T txrx

TX to RX switching

(to preamble start)

T hop

Frequency hop Switch between frequency defined in register

AX5043_FREQA and

AX5043_FREQB

1. t bit depends on the datarate, e.g. for 10 kbps t bit

= 100 ms

Min

40

Typ

40 + 1 x t bit

Max Units

ms

190

270 +

3 x t bit

190 +

9 x t bit

62

200

30 ms ms ms ms ms

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15

AX8052F143

Table 16. LOW FREQUENCY CRYSTAL OSCILLATOR

Symbol

f

LPXTAL gm lpxosc

Description

Crystal frequency

Transconductance oscillator

Condition

LPXOSCGM = 00110

LPXOSCGM = 01000

LPXOSCGM = 01100

LPXOSCGM = 10000

RIN lpxosc

Input DC impedance

Min

10

Table 17. INTERNAL LOW POWER OSCILLATOR

Symbol

f

LPOSC

Description

Oscillation Frequency

Condition

LPOSCFAST = 0

Factory calibration applied.

Over the full temperature and voltage range

LPOSCFAST = 1

Factory calibration applied

Over the full temperature and voltage range

Min

630

10.08

Typ

640

10.24

Typ

32

3.5

4.6

6.9

9.1

Table 18. INTERNAL RC OSCILLATOR

Symbol

f

LFRCPOSC

Description

Oscillation Frequency

Condition

Factory calibration applied.

Over the full temperature and voltage range

Min

19.8

Typ

20

Table 19. MICROCONTROLLER

Symbol

T

SYSCLKL

T

SYSCLKH

T

SYSCLKP

T

FLWR

T

FLPE

T

FLE

T

FLEND

T

FLRETroom

Description

SYSCLK Low

SYSCLK High

SYSCLK Period

FLASH Write Time

FLASH Page Erase

FLASH Secure Erase

FLASH Endurance: Erase Cycles

FLASH Data Retention

T

FLREThot

Max

150

Max

650

10.39

Max

20.2

Units

kHz ms

MW

Units

Hz kHz

Units

MHz

2 Bytes

1 kBytes

64 kBytes

Condition

25°C

See Figure 5 for the lower limit

set by the memory qualification

85°C

See Figure 5 for the lower limit

set by the memory qualification

Min

27

21

47

Typ

10 000

100

20

2

10

100 000

10

Max Units

ns ns ns ms ms ms

Cycles

Years

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16

AX8052F143

100000

10000

1000

100

10

15 25 35 45 55

Temperature [5C]

65 75 85

Figure 5. FLASH Memory Qualification Limit for Data Retention after 10k Erase Cycles

Table 20. ADC / COMPARATOR / TEMPERATURE SENSOR

Symbol

ADCSR

ADCSR_T

ADCRES

V

ADCREF

Description

ADC sampling rate GPADC mode

ADC sampling rate temperature sensor mode

ADC resolution

ADC reference voltage & comparator internal reference voltage

Z

ADC00

DNL

INL

OFF

Input capacitance

Differential nonlinearity

Integral nonlinearity

Offset

GAIN_ERR Gain error

ADC in Differential Mode

V

ABS_DIFF

Absolute voltages & common mode voltage in differential mode at each input

V

FS_DIFF01

V

FS_DIFF10

Full swing input for differential signals

ADC in Single Ended Mode

V

MID_SE

V

IN_SE00

V

FS_SE01

Comparators

V

COMP_ABS

V

COMP_COM

Mid code input voltage in single ended mode

Input voltage in single ended mode

Full swing input for single ended signals

Comparator absolute input voltage

Comparator input common mode

Condition

Gain x1

Gain x10

Gain x1

V

COMPOFF

Comparator input offset voltage

Temperature Sensor

T

RNG

T

RES

T

ERR_CAL

Temperature range

Temperature resolution

Temperature error Factory calibration applied

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17

Min

30

10

0.95

Typ

15.6

10

1

± 1

± 1

3

0.8

Max

500

30

1.05

2.5

0

0

0

0

0

−500

−50

−40

−2

0.5

0.1607

VDD_IO

500

50

VDD_IO

1

VDD_IO

VDD_IO −

0.8

20

85

2

V

V mV

°C

°C/LSB

°C

V mV mV

V

V

V

Units

kHz kHz

Bits

V pF

LSB

LSB

LSB

%

AX8052F143

CIRCUIT DESCRIPTION

The AX8052F143 is a true single chip narrow−band, ultra−low power RF−microcontroller SoC for use in licensed and unlicensed bands ranging from 70 MHz to

1050 MHz. The on−chip transceiver consists of a fully integrated RF front−end with modulator and demodulator.

Base band data processing is implemented in an advanced and flexible communication controller that enables user friendly communication.

The AX8052F143 contains a high speed microcontroller compatible to the industry standard 8052 instruction set. It contains 64 kBytes of FLASH and 8.25 kBytes of internal

SRAM.

The AX8052F143 features 3 16−bit general purpose timers with SD capability, 2 output compare units for generating PWM signals, 2 input compare units to record timings of external signals, 2 16−bit wakeup timers, a watchdog timer, 2 UARTs, a Master/Slave SPI controller, a

10−bit 500 kSample/s A/D converter, 2 analog comparators, a temperature sensor, a 2 channel DMA controller, and a dedicated AES crypto controller. Debugging is aided by a dedicated hardware debug interface controller that connects using a 3−wire protocol (1 dedicated wire, 2 shared with

GPIO) to the PC hosting the debug software.

While the radio carrier/LO synthesizer can only be clocked by the crystal oscillator (carrier stability requirements dictate a high stability reference clock in the

MHz range), the microcontroller and its peripherals provide extremely flexible clocking options. The system clock that clocks the microcontroller, as well as peripheral clocks, can be selected from one of the following clock sources: the crystal oscillator, an internal high speed 20MHz oscillator, an internal low speed 640 Hz/10 kHz oscillator, or the low frequency crystal oscillator. Prescalers offer additional flexibility with their programmable divide by a power of two capability. To improve the accuracy of the internal oscillators, both oscillators may be slaved to the crystal oscillator.

AX8052F143 can be operated from a 1.8 V to 3.6 V power supply over a temperature range of –40 °C to 85°C, it consumes 4 − 51 mA for transmitting, depending on the output power, 6.8 – 11 mA for receiving.

The AX8052F143 features make it an ideal interface for integration into various battery powered solutions such as ticketing or as transceiver for telemetric applications e.g. in sensors. As primary application, the transceiver is intended for UHF radio equipment in accordance with the European

Telecommunication Standard Institute (ETSI) specification

EN 300 220−1 and the US Federal Communications

Commission (FCC) standard Title 47 CFR part 15 as well as

Part 90. Additionally AX8052F143 is suited for systems targeting compliance with Wireless M−Bus standard EN

13757−4:2005. Wireless M−Bus frame support (S, T, R) is built−in.

The AX8052F143 sends and receives data in frames. This standard operation mode is called Frame Mode. Pre and post ambles as well as checksums can be generated automatically.

AX8052F143 supports any data rate from 0.1 kbps to

125 kbps for FSK, MSK, 4−FSK, GFSK, GMSK and ASK modulations. To achieve optimum performance for specific data rates and modulation schemes several register settings to configure the AX8052F143 are necessary, they are outlined in the following, for details see the AXSEM

RadioLab software which calculates the necessary register settings and the AX5043 Programming Manual.

The receiver supports multi−channel operation for all data rates and modulation schemes.

Microcontroller

The AX8052 microcontroller core executes the industry standard 8052 instruction set. Unlike the original 8052, many instructions are executed in a single cycle. The system clock and thus the instruction rate can be programmed freely from DC to 20 MHz.

Memory Architecture

The AX8052F143 Microcontroller features the highest bandwidth memory architecture of its class. Figure 6 shows the memory architecture. Three bus masters may initiate bus cycles:

The AX8052 Microcontroller Core

The Direct Memory Access (DMA) Engine

The Advanced Encryption Standard (AES) Engine

Bus targets include:

Two individual 4 kBytes RAM blocks located in X address space, which can be simultaneously accessed and individually shut down or retained during sleep mode

A 256 Byte RAM located in internal address space, which is always retained during sleep mode

A 64 kBytes FLASH memory located in code space.

Special Function Registers (SFR) located in internal address space accessible using direct address mode instructions

Additional Registers located in X address space

(X Registers)

The upper half of the FLASH memory may also be accessed through the X address space. This simplifies and makes the software more efficient by reducing the need for generic pointers.

NOTE: Generic pointers include, in addition to the address, an address space tag.

SFR Registers are also accessible through X address space, enabling indirect access to SFR registers. This allows driver code for multiple identical peripherals (such as

UARTs or Timers) to be shared.

The 4 word × 16 bit fully associative cache and a pre−fetch controller hide the latency of the FLASH.

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18

AES DMA

AX8052F143

X Bus

AX8052

SFR Bus IRAM Bus Code Bus

Cache

Prefetch

Arbiter

XRAM

0000−0FFF

Arbiter

XRAM

1000−1FFF

Arbiter

X Registers

4000−7FFF

Arbiter

SFR Registers

80−FF

Arbiter

IRAM

00−FF

Arbiter

FLASH

0000−FFFF

The AX8052 Memory Architecture is fully parallel. All bus masters may simultaneously access different bus targets during each system clock cycle. Each bus target includes an arbiter that resolves access conflicts. Each arbiter ensures that no bus master can be starved.

Both 4 kBytes RAM blocks may be individually retained or switched off during sleep mode. The 256 Byte RAM is always retained during sleep mode.

P (Code) Space

Figure 6. AX8052 Memory Architecture

X Space

XRAM

The AES engine accesses memory 16 bits at a time. It is therefore slightly faster to align its buffers on even addresses.

Memory Map

The AX8052, like the other industry standard 8052 compatible microcontrollers, uses a Harvard architecture.

Multiple address spaces are used to access code and data.

Figure 7 shows the AX8052 memory map.

I (internal) Space direct access indirect access

IRAM

SFR

IRAM

Address

0000−007F

0080−00FF

0100−1FFF

2000−207F

2080−3F7F

3F80−3FFF

4000−4FFF

5000−5FFF

6000−7FFF

8000−FBFF

FC00−FFFF

FLASH

Calibration Data

IRAM

SFR

RREG

RREG (nb)

XREG

FLASH

Calibration Data

Figure 7. AX8052 Memory Architecture www.onsemi.com

19

AX8052F143

The AX8052 uses P or Code Space to access its program.

Code space may also be read using the MOVC instruction.

Smaller amounts of data can be placed in the Internal (see

Note) or Data Space. A distinction is made in the upper half of the Data Space between direct accesses (MOV reg,addr;

MOV addr,reg) and indirect accesses (MOV reg,@Ri;

MOV @Ri,reg; PUSH; POP); Direct accesses are routed to the Special Function Registers, while indirect accesses are routed to the internal RAM.

NOTE: The origin of Internal versus External (X) Space is historical. External Space used to be outside of the chip on the original 8052

Microcontrollers.

Large amounts of data can be placed in the External or X

Space. It can be accessed using the

MOVX

instructions.

Special Function Registers, as well as additional

Microcontroller Registers (XREG) and the Radio Registers

(RREG) are also mapped into the X Space.

Detailed documentation of the Special Function Registers

(SFR) and additional Microcontroller Registers can be found in the AX8052 Programming Manual.

The Radio Registers are documented in the AX5043

Programming Manual. Register Addresses given in the

AX5043 Programming Manual are relative to the beginning of RREG, i.e. 0x4000 must be added to these addresses. It is recommended that the AXSEM provided ax8052f143.h

header file is used; Radio Registers are prefixed with

AX5043_

in the ax8052f143.h header file to avoid clashes of same−name Radio Registers with AX8052 registers.

Normally, accessing Radio Registers through the RREG address range is adequate. Since Radio Register accesses have a higher latency than other AX8052 registers, the

AX8052 provides a method for non−blocking access to the

Radio Registers. Accessing the RREG (nb) address range initiates a Radio Register access, but does not wait for its completion. The details of mechanism is documented in the

Radio Interface section of the AX8052 Programming

Manual.

The FLASH memory is organized as 64 pages of 1 kBytes each. Each page can be individually erased. The write word size is 16 Bits. The last 1 kByte page is dedicated to factory calibration data and should not be overwritten.

Power Management

The microcontroller power mode can be selected independently from the transceiver. The microcontroller supports the following power modes:

Table 21. POWER MANAGEMENT

PCON register

00

01

10

11

Name

RUNNING

STANDBY

SLEEP

DEEPSLEEP

Description

The microcontroller and all peripherals are running. Current consumption depends on the system clock frequency and the enabled peripherals and their clock frequency.

The microcontroller is stopped. All register and memory contents are retained. All peripherals continue to function normally. Current consumption is determined by the enabled peripherals. STANDBY is exited when any of the enabled interrupts become active.

The microcontroller and its peripherals, except GPIO and the system controller, are shut down. Their register settings are lost. The internal RAM is retained. The external RAM is split into two 4 kByte blocks.

Software can determine individually for both blocks whether contents of that block are to be retained or lost. SLEEP can be exited by any of the enabled GPIO or system controller interrupts. For most applications this will be a GPIO or wakeup timer interrupt.

The microcontroller, all peripherals and the transceiver are shut down. Only 4 bytes of scratch RAM are retained. DEEPSLEEP can only be exited by tying the PB3 pin low.

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AX8052F143

Clocking

WDT

Wakeup

Timer

Internal Reset

Interrupt

LPOSC

Calib

LPOSC

FRCOSC

Calib

FRCOSC

Prescaler

÷

1,2,4,...

System Clock

XOSC

Clock

Monitor

LPXOSC

SYSCLK

The system clock can be derived from any of the following clock sources:

The crystal oscillator (RF reference oscillator, typically

16 MHz, via SYSCLK)

The low speed crystal oscillator (typical 32 kHz tuning fork)

The internal high speed RC (20 MHz) oscillator

The internal low power (640 Hz/10 kHz) oscillator

An additional pre−scaler allows the selected oscillator to be divided by a power of two. After reset, the microcontroller starts with the internal high speed RC oscillator selected and divided by two. I.e. at start−up, the microcontroller runs with 10 MHz

± 10%. Clocks may be switched any time by writing to the CLKCON register. In order to prevent clock glitches, the switching takes approximately 2·(T

1

+T

2

), where T

1

and T

2

are the periods of the old and the new clock. Switching may take longer if the new oscillator first has to start up. Internal oscillators start up instantaneously, but crystal oscillators may take a considerable amount of time to start the oscillation.

CLKSTAT can be read to determine the clock switching status.

A programmable clock monitor resets the CLKCON register when no system clock transitions are found during

Figure 8. Clock System Diagram

a programmable time interval, thus reverts to the internal RC oscillator.

Both internal oscillators can be slaved to one of the crystal oscillators to increase the accuracy of the oscillation frequency. While the reference oscillator runs, the internal oscillator is slaved to the reference frequency by a digital frequency locked loop. When the reference oscillator is switched off, the internal oscillator continues to run unslaved with the last frequency setting.

Reset and Interrupts

After reset, the microcontroller starts executing at address

0x0000. Several events can lead to resetting the microcontroller core:

POR or hardware RESET_N pin activated and released

Leaving SLEEP or DEEPSLEEP mode

Watchdog Reset

Software Reset

The reset cause can be determined by reading the PCON register.

The microcontroller supports 22 interrupt sources. Each interrupt can be individually enabled and can be programmed to have one of two possible priorities. The interrupt vectors are located at 0x0003, 0x000B,

…,

0x00AB.

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AX8052F143

Debugging

A hardware debug unit considerably eases debugging compared to other 8052 microcontrollers. It allows to reliably stop the microcontroller at breakpoints even if the stack is smashed. The debug unit communicates with the host PC running the debugger using a 3 wire interface. One wire is dedicated (DBG_EN), while two wires are shared with GPIO pins (PB6, PB7). When DBG_EN is driven high,

PB6 and PB7 convert to debug interface pins and the GPIO functionality is no longer available. A pin emulation feature however allows bits PINB[7:6] to be set and PORTB[7:6] and DIRB[7:6] to be read by the debugger software. This allows for example switches or LEDs connected to the PB6,

PB7 pins to be emulated in the debugger software whenever the debugger is active.

In order to protect the intellectual property of the firmware developer, the debug interface can be locked using a developer−selectable 64−bit key. The debug interface is then disabled and can only be enabled with the knowledge of this

64−bit key. Therefore, unauthorized persons cannot read the firmware through the debug interface, but debugging is still possible for authorized persons. Secure erase can be initiated without key knowledge; secure erase ensures that the main

FLASH array is completely erased before erasing the key, reverting the chip into factory state.

The DebugLink peripheral looks like an UART to the microcontroller, and allows exchange of data between the microcontroller and the host PC without disrupting program execution.

Timer, Output Compare and Input Capture

The AX8052F143 features three general purpose 16−bit timers. Each timer can be clocked by the system clock, any of the available oscillators, or a dedicated input pin. The timers also feature a programmable clock inversion, a programmable prescaler that can divide by powers of two, and an optional clock synchronization logic that synchronizes the clock to the system clock. All three counters are identical and feature four different counting modes, as well as a

SD mode that can be used to output an analog value on a dedicated digital pin only employing a simple RC lowpass filter.

Two output compare units work in conjunction with one of the timers to generate PWM signals.

Two input capture units work in conjunction with one of the timers to measure transitions on an input signal.

For software timekeeping, two additional 16−bit wakeup timers with 4 16−bit event registers are provided, generating an interrupt on match events.

UART

The AX8052F143 features two universal asynchronous receiver transmitters. They use one of the timers as baud rate generator. Word length can be programmed from 5 to 9 bits.

SPI Master/Slave Controller

The AX8052F143 features a master/slave SPI controller.

Both 3 and 4 wire SPI variants are supported. In master mode, any of the on−chip oscillators or the system clock may be selected as clock source. An additional prescaler with divide by two capability provides additional clocking flexibility. Shift direction, as well as clock phase and inversion, are programmable.

ADC, Analog Comparators and Temperature Sensor

The AX8052F143 features a 10−bit, 500 kSample/s

Analog to Digital converter. Figure 9 shows the block

diagram of the ADC. The ADC supports both single ended and differential measurements. It uses an internal reference of 1 V. ×1, ×10 and ×0.1 gain modes are provided. The ADC may digitize signals on PA0 …PA7, as well as VDD_IO and an internal temperature sensor. The user can define four channels which are then converted sequentially and stored in four separate result registers. Each channel configuration consists of the multiplexer and the gain setting.

The AX8052F143 contains an on−chip temperature sensor. Built−in calibration logic allows the temperature sensor to be calibrated in °C, °F or any other user defined temperature scale.

The AX8052F143 also features two analog comparators.

Each comparator can either compare two voltages on dedicated PA pins, or one voltage against the internal 1 V reference. The comparator output can be routed to a dedicated digital output pin or can be read by software. The comparators are clocked with the system clock.

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AX8052F143

VDDIO

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Temperature

Sensor

PPP

Clock Trigger

ADC Core

Gain Ref

Single Ended

VREF

1 V

0.5 V

Free Running

One Shot

Timer 0

Timer 1

Timer 2

PC4

ADCCONV

ADC Result

NNN

ACOMP0IN ACOMP0ST/PA4/PC3

ACOMP0REF

ACOMP0INV

System Clock

ACOMP1IN

ACOMP1INV

ACOMP1REF

Figure 9. ADC Block Diagram

DMA Controller

The AX8052F143 features a dual channel DMA engine.

Each DMA channel can either transfer data from XRAM to almost any peripheral on chip, or from almost any peripheral to XRAM. Both channels may also be cross−linked for memory−memory transfers. The DMA channels use buffer descriptors to find the buffers where data is to be retrieved or placed, thus enabling very flexible buffering strategies.

The DMA channels access XRAM in a cycle steal fashion.

They access XRAM whenever XRAM is not used by the microcontroller. Their priority is lower than the microcontroller, thus interfering very little with the

ACOMP1ST/PA7/PC1 microcontroller. Additional logic prevents starvation of the

DMA controller.

AES Engine

The AX8052F143 contains a dedicated engine for the government mandated Advanced Encryption Standard

(AES). It features a dedicated DMA engine and reads input data as well as key stream data from the XRAM, and writes output data into a programmable buffer in the XRAM. The round number is programmable; the chip therefore supports

AES−128, AES−192, and AES−256, as well as higher security proprietary variants. Keystream (key expansion) is

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AX8052F143

performed in software, adding to the flexibility of the AES engine. ECB (electronic codebook), CFB (cipher feedback) and OFB (output feedback) modes are directly supported without software intervention.

Crystal Oscillator and TCXO Interface

(RF Reference Oscillator)

The AX8052F143 is normally operated with an external

TCXO, which is required by most narrow−band regulation with a tolerance of 0.5 ppm to 1.5 ppm depending on the regulation. The on−chip crystal oscillator allows the use of an inexpensive quartz crystal as the RF generation subsystem’s timing reference when possible from a regulatory point of view.

A wide range of crystal frequencies can be handled by the crystal oscillator circuit. As the reference frequency impacts both the spectral performance of the transmitter as well as the current consumption of the receiver, the choice of reference frequency should be made according to the regulatory regime targeted by the application. Application

Notes for usage of AX5043 in compliance with various regulatory regimes also apply to AX8052F143.

The crystal or TCXO reference frequency should be chosen so that the RF carrier frequency is not an integer multiple of the crystal or TCXO frequency.

The oscillator circuit is enabled by programming the

AX5043_PWRMODE register. At power−up it is enabled.

To adjust the circuit’s characteristics to the quartz crystal being used, without using additional external components, the tuning capacitance of the crystal oscillator can be programmed. The transconductance of the oscillator is automatically regulated, to allow for fastest start−up times together with lowest power operation during steady−state oscillation.

The integrated programmable tuning capacitor bank makes it possible to connect the oscillator directly to pins

CLK16N and CLK16P without the need for external capacitors. It is programmed using bits XTALCAP[5:0] in register AX5043_XTALCAP.

To synchronize the receiver frequency to a carrier signal, the oscillator frequency could be tuned using the capacitor bank however, the recommended method to implement frequency synchronization is to make use of the high resolution RF frequency generation sub−system together with the Automatic Frequency Control, both are described further down.

Alternatively a single ended reference (TXCO, CXO) may be used. The CMOS levels should be applied to

CLK16P via an AC coupling with the crystal oscillator enabled. For detailed TCXO network recommendations depending on TCXO output swing refer to the AX5043

Application Note: Use with a TCXO Reference Clock.

Low Power Oscillator and Wake on Radio (WOR) Mode

The AX8052F143 transceiver features an internal lowest power fully integrated oscillator. In default mode the frequency of oscillation is 640 Hz ± 1.5%, in fast mode it is

10.2 kHz ± 1.5%.

If Wake on Radio Mode is enabled, the receiver wakes up periodically at a user selectable interval, and checks for a radio signal on the selected channel. If no signal is detected, the receiver shuts down again. If a radio signal is detected, and a valid packet is received, the microcontroller is alerted by asserting an interrupt.

SYSCLK Output

The SYSCLK pin outputs the RF reference clock signal divided by a programmable integer. Divisions from 1 to

2048 are possible. For divider ratios > 1 the duty cycle is

50%. Bits SYSCLK[3:0] in the AX5043_PINCFG1 register set the divider ratio. The SYSCLK output can be disabled.

Power−on−Reset (POR) and RESET_N Input

AX8052F143 has an integrated power−on−reset block which is edge sensitive to VDD_IO. For many common application cases no external reset circuitry is required.

However, if VDD_IO ramps cannot be guaranteed, an external reset circuit is recommended. For detailed recommendations and requirements see the AX8052

Application Note: Power On Reset.

After POR or reset all registers are set to their default values.

The RESET_N pin contains a weak pull−up. However, it is strongly recommended to connect the RESET_N pin to

VDD_IO if not used, for additional robustness.

The AX8052F143 can be reset by software as well. The microcontroller is reset by writing 1 to the SWRESET bit of the PCON register. The transceiver can be reset by first writing 1 and then 0 to the RST bit in the

AX5043_PWRMODE register.

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AX8052F143

Ports

VDDIO

PORTx.y

DIRx.y

65 kW

Special Function

PALTx.y

INTCHGx.y

Interrupt

PINx.y

PINx read clock

ANALOGx.y

Figure 10. Port Pin Schematic

Figure 10 shows the GPIO logic. The DIR register bit determines whether the port pin acts as an output (1) or an input (0).

If configured as an output, the PALT register bit determines whether the port pin is connected to a peripheral output (1), or used as a GPIO pin (0). In the latter case, the

PORT register bit determines the port pin drive value.

If configured as an input, the PORT register bit determines whether a pull−up resistor is enabled (1) or disabled (0).

Inputs have chmitt−trigger characteristic. Port A inputs may be disabled by setting the ANALOGA register bit; this prevents additional current consumption if the voltage level of the port pin is mid−way between logic low and logic high, when the pin is used as an analog input.

Port A, B and C pins may interrupt the microcontroller if their level changes. The INTCHG register bit enables the interrupt. The PIN register bit reflects the value of the port pin. Reading the PIN register also resets the interrupt if interrupt on change is enabled.

PWRAMP and ANTSEL

PWRAMP functionality is available on PB2 if

PALTRADIO bit 6 and DIRB bit 2 are set. ANTSEL functionality is available on PB3 if PALTRADIO bit 7 and

DIRB bit 3 are set. If these pins should be set to high−impedance, it must be done by clearing the corresponding DIRB bit, not by setting

AX5043_PINFUNCPWRAMP or

AX5043_PINFUNCANTSEL to Z.

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AX8052F143

TRANSCEIVER

The transceiver block is controllable through its registers, which are mapped into the X data space of the micro−controller. The transceiver block features its own 4 word

×10 bit FIFO. The microcontroller can either be interrupted at a programmable FIFO fill level, or one of the

DMA channels can be instructed to transfer between XRAM and the transceiver FIFO.

RF Frequency Generation Subsystem

The RF frequency generation subsystem consists of a fully integrated synthesizer, which multiplies the reference frequency from the crystal oscillator to get the desired RF frequency. The advanced architecture of the synthesizer enables frequency resolutions of 1 Hz, as well as fast settling times of 5 – 50 ms depending on the settings (see section AC

Characteristics). Fast settling times mean fast start−up and fast RX/TX switching, which enables low−power system design.

For receive operation the RF frequency is fed to the mixer, for transmit operation to the power−amplifier.

The frequency must be programmed to the desired carrier frequency.

The synthesizer loop bandwidth can be programmed, this serves three purposes:

1. Start−up time optimization, start−up is faster for higher synthesizer loop bandwidths

2. TX spectrum optimization, phase−noise at

300 kHz to 1 MHz distance from the carrier improves with lower synthesizer loop bandwidths

3. Adaptation of the bandwidth to the data−rate. For transmission of FSK and MSK it is required that the synthesizer bandwidth must be in the order of the data−rate.

VCO

An on−chip VCO converts the control voltage generated by the charge pump and loop filter into an output frequency.

This frequency is used for transmit as well as for receive operation. The frequency can be programmed in 1 Hz steps in the AX5043_FREQ registers. For operation in the 433

MHz band, the RFDIV bit in the AX5043_PLLVCODIV register must be programmed.

The fully integrated VCO allows to operate the device in the frequency ranges 800 – 1050 MHz and 400 – 520 MHz.

The carrier frequency range can be extended to 54 –

525 MHz and 27 – 262 MHz by using an appropriate external inductor between device pins L1 and L2. The bits

VCO2INT and VCOSEL in the AX5043_PLLVCODIV register must be set high to enter this mode.

It is also possible to use a fully external VCO by setting bits VCO2INT = 0 and VCOSEL = 1 in the

AX5043_PLLVCODIV register. A differential input at a frequency of double the desired RF frequency must be input at device pins L1 and L2. The control voltage for the VCO can be output at device pin FILT when using external filter mode. The voltage range of this output pin is 0 – 1.8 V. This mode of operation is recommended for special applications where the phase noise requirements are not met when using the fully internal VCO or the internal VCO with external inductor.

VCO Auto−Ranging

The AX8052F143 has an integrated auto−ranging function, which allows to set the correct VCO range for specific frequency generation subsystem settings automatically. Typically it has to be executed after power−up. The function is initiated by setting the

RNG_START bit in the AX5043_PLLRANGINGA or

AX5043_PLLRANGINGB register. The bit is readable and a 0 indicates the end of the ranging process. Setting

RNG_START in the AX5043_PLLRANGINGA register ranges the frequency in AX5043_FREQA, while setting

RNG_START in the AX5043_PLLRANGINGB register ranges the frequency in AX5043_FREQB. The RNGERR bit indicates the correct execution of the auto−ranging. VCO auto−ranging works with the fully integrated VCO and with the internal VCO with external inductor.

Loop Filter and Charge Pump

The AX8052F143 internal loop filter configuration together with the charge pump current sets the synthesizer loop band width. The internal loop−filter has three configurations that can be programmed via the register bits

FLT[1:0] in registers AX5043_PLLLOOP or

AX5043_PLLLOOPBOOST the charge pump current can be programmed using register bits PLLCPI[7:0] in registers

AX5043_PLLCPI or AX5043_PLLCPIBOOST.

Synthesizer bandwidths are typically 50 – 500 kHz depending on the AX5043_PLLLOOP or

AX5043_PLLLOOPBOOST settings, for details see the section: AC Characteristics.

The AX8052F143 can be setup in such a way that when the synthesizer is started, the settings in the registers

AX5043_PLLLOOPBOOST and

AX5043_PLLCPIBOOST are applied first for a programmable duration before reverting to the settings in

AX5043_PLLLOOP and AX5043_PLLCPI

.

This feature enables automated fastest start−up.

Setting bits FLT[1:0] = 00 bypasses the internal loop filter and the VCO control voltage is output to an external loop filter at pin FILT. This mode of operation is recommended for achieving lower bandwidths than with the internal loop filter and for usage with a fully external VCO.

Registers

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Table 22. RF FREQUENCY GENERATION REGISTERS

Register

AX5043_PLLLOOP

AX5043_PLLLOOPBOOST

Bits Purpose

FLT[1:0] Synthesizer loop filter bandwidth and selection of external loop filter, recommended usage is to increase the bandwidth for faster settling time, bandwidth increases of factor 2 and 5 are possible.

AX5043_PLLCPI

AX5043_PLLCPIBOOST

AX5043_PLLVCODIV

Synthesizer charge pump current, recommended usage is to decrease the bandwidth (and improve the phase−noise) for low data−rate transmissions.

REFDIV Sets the synthesizer reference divider ratio.

RFDIV Sets the synthesizer output divider ratio.

VCOSEL Selects either the internal or the external VCO

VCO2INT Selects either the internal VCO inductor or an external inductor between pins L1 and L2

AX5043_FREQA, AX5043_FREQB

AX5043_PLLRANGINGA,

AX5043_PLLRANGINGB

Programming of the carrier frequency

Initiate VCO auto−ranging and check results

RF Input and Output Stage (ANTP/ANTN/ANTP1)

The AX8052F143 has two main antenna interface modes:

1. Both RX and TX use differential pins ANTP and

ANTN. RX/TX switching is handled internally.

This mode is recommended for highest output powers, highest sensitivities and for direct connection to dipole antennas. Also see Figure 15.

2. RX uses the differential antenna pins ANTP and

ANTN. TX uses the single ended antenna pin

ANTP1. RX/TX switching is handled externally.

This can be done either with an external RX/TX switch or with a direct tie configuration. This mode is recommended for low output powers at high efficiency Figure 18 and for usage with external power amplifiers Figure 17.

Pin PB2 can be used to control an external RX/TX switch when operating the device together with an external PA

(Figure 17). Pin PB3 can be used to control an external antenna switch when receiving with two antennas (Figure

19).

When antenna diversity is enabled, the radio controller will, when not in the middle of receiving a packet, periodically probe both antennas and select the antenna with the highest signal strength. The radio controller can be instructed to periodically write both RSSI values into the

FIFO. Antenna diversity mode is fully automatic.

LNA

The LNA amplifies the differential RF signal from the antenna and buffers it to drive the I/Q mixer. An external matching network is used to adapt the antenna impedance to the IC impedance. A DC feed to GND must be provided at the antenna pins.

PA

In TX mode the PA drives the signal generated by the frequency generation subsystem out to either the differential antenna terminals or to the single ended antenna pin. The antenna terminals are chosen via the bits TXDIFF and TXSE in register AX5043_MODECFGA.

The output power of the PA is programmed via the register

AX5043_TXPWRCOEFFB.

The PA can be digitally pre−distorted for high linearity.

The output amplitude can be shaped (raised cosine), this mode is selected with bit AMPLSHAPE in register

AX5043_MODECFGA PA ramping is programmable in increments of the bit time and can be set to 1 – 8 bit times via bits SLOWRAMP in register AX5043_MODECFGA

.

Output power as well as harmonic content will depend on the external impedance seen by the PA.

Digital IF Channel Filter and Demodulator

The digital IF channel filter and the demodulator extract the data bit−stream from the incoming IF signal. They must be programmed to match the modulation scheme as well as the data−rate. Inaccurate programming will lead to loss of sensitivity.

The channel filter offers bandwidths of 995 Hz up to

221 kHz.

The AXSEM RadioLab Software calculates the necessary register settings for optimal performance. An overview of the registers involved is given in the following table as reference, for details see the AX5043 Programming

Manual. The register setups typically must be done once at power−up of the device.

Registers

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Table 23. CHANNEL FILTER AND DEMODULATOR REGISTERS

Register

AX5043_DECIMATION

AX5043_RXDATARATE2…

AX5043_RXDATARATE0

AX5043_MAXDROFFSET2…

AX5043_MAXDROFFSET0

Remarks

This register programs the bandwidth of the digital channel filter.

These registers specify the receiver bit rate, relative to the channel filter bandwidth.

These registers specify the maximum possible data rate offset

These registers specify the maximum possible RF frequency offset

AX5043_MAXRFOFFSET2…

AX5043_MAXRFOFFSET0

AX5043_TIMEGAIN, AX5043_DRGAIN

AX5043_MODULATION

These registers specify the aggressiveness of the receiver bit timing recovery. More aggressive settings allow the receiver to synchronize with shorter preambles, at the expense of more timing jitter and thus a higher bit error rate at a given signal−to−noise ratio.

This register selects the modulation to be used by the transmitter and the receiver, i.e. whether ASK, FSK should be used.

AX5043_PHASEGAIN, AX5043_FREQGAINA,

AX5043_FREQGAINB, AX5043_FREQGAINC,

AX5043_FREQGAIND, AX5043_AMPLGAIN

AX5043_AGCGAIN

These registers control the bandwidth of the phase, frequency offset and amplitude tracking loops.

AX5043_TXRATE

AX5043_FSKDEV

This register controls the AGC (automatic gain control) loop slopes, and thus the speed of gain adjustments. The faster the bit−rate, the faster the AGC loop should be.

These registers control the bit rate of the transmitter.

These registers control the frequency deviation of the transmitter in FSK mode. The receiver does not explicitly need to know the frequency deviation, only the channel filter bandwidth has to be set wide enough for the complete modulation to pass.

Encoder

The encoder is located between the Framing Unit, the

Demodulator and the Modulator. It can optionally transform the bit−stream in the following ways:

It can invert the bit stream.

It can perform differential encoding. This means that a zero is transmitted as no change in the level, and a one is transmitted as a change in the level.

It can perform Manchester encoding. Manchester encoding ensures that the modulation has no DC content and enough transitions (changes from 0 to 1 and from 1 to 0) for the demodulator bit timing recovery to function correctly, but does so at a doubling of the data rate.

It can perform spectral shaping (also know as whitening). Spectral shaping removes DC content of the bit stream, ensures transitions for the demodulator bit timing recovery, and makes sure that the transmitted spectrum does not have discrete lines even if the transmitted data is cyclic. It does so without adding additional bits, i.e. without changing the data rate.

Spectral Shaping uses a self synchronizing feedback shift register.

The encoder is programmed using the register

AX5043_ENCODING, details and recommendations on usage are given in the AX5043 Programming Manual.

Framing and FIFO

Most radio systems today group data into packets. The framing unit is responsible for converting these packets into a bit−stream suitable for the modulator, and to extract packets from the continuous bit−stream arriving from the demodulator.

The Framing unit supports two different modes:

Packet modes

Raw modes

The microcontroller communicates with the framing unit through a 256 byte FIFO. Data in the FIFO is organized in

Chunks. The chunk header encodes the length and what data is contained in the payload. Chunks may contain packet data, but also RSSI, Frequency offset, Timestamps, etc.

The AX8052F143 contains one FIFO. Its direction is switched depending on whether transmit or receive mode is selected.

The FIFO can be operated in polled or interrupt driven modes. In polled mode, the microcontroller must periodically read the FIFO status register or the FIFO count register to determine whether the FIFO needs servicing.

In interrupt mode EMPTY, NOT EMPTY, FULL, NOT

FULL and programmable level interrupts are provided.

Interrupts are acknowledged by removing the cause for the interrupt, i.e. by emptying or filling the FIFO.

To lower the interrupt load on the microcontroller, one of the DMA channels may be instructed to transfer data

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AX8052F143

between the transceiver FIFO and the XRAM memory. This way, much larger buffers can be realized in XRAM, and interrupts need only be serviced if the larger XRAM buffers fill or empty.

Packet Modes

The AX8052F143 offers different packet modes. For arbitrary packet sizes HDLC is recommended since the flag and bit−stuffing mechanism. The AX8052F143 also offers packet modes with fixed packet length with a byte indicating the length of the packet.

In packet modes a CRC can be computed automatically.

HDLC Mode is the main framing mode of the

AX8052F143. In this mode, the AX8052F143 performs automatic packet delimiting, and optional packet correctness check by inserting and checking a cyclic redundancy check (CRC) field.

NOTE: HDLC mode follows High−Level Data Link

Control (HDLC, ISO 13239) protocol.

The packet structure is given in the following table.

Table 24. HDLC PACKET STRUCTURE

Flag

8 bit

Address

8 bit

Control

8 or 16 bit

Information

Variable length, 0 or more bits in multiples of 8

FCS

16 / 32 bit

(Optional Flag)

8 bit

HDLC packets are delimited with flag sequences of content 0x7E.

In AX8052F143 the meaning of address and control is user defined. The Frame Check Sequence (FCS) can be programmed to be CRC−CCITT, CRC−16 or CRC−32.

Table 25. WIRELESS M−BUS PACKET STRUCTURE

Preamble

variable

L

8 bit

C

8 bit

M

8 bit

A

8 bit

FCS

16 bit

The receiver checks the CRC, the result can be retrieved from the FIFO, the CRC is appended to the received data.

In Wireless M−Bus Mode, the packet structure is given in the following table.

NOTE: Wireless M−Bus mode follows EN13757−4

Optional Data Block

(optionally repeated with FCS)

8 − 96 bit

FCS

16 bit

For details on implementing a HDLC communication as well as Wireless M−Bus please use the AXSEM RadioLab software and see the AX5043 Programming Manual.

Raw Modes

In Raw mode, the AX8052F143 does not perform any packet delimiting or byte synchronization. It simply serializes transmit bytes and de−serializes the received bit−stream and groups it into bytes. This mode is ideal for implementing legacy protocols in software.

Raw mode with preamble match is similar to raw mode.

In this mode, however, the receiver does not receive anything until it detects a user programmable bit pattern

(called the preamble) in the receive bit−stream. When it detects the preamble, it aligns the de−serialization to it.

The preamble can be between 4 and 32 bits long.

RX AGC and RSSI

AX8052F143 features three receiver signal strength indicators (RSSI):

1. RSSI before the digital IF channel filter.

The gain of the receiver is adjusted in order to keep the analog IF filter output level inside the working range of the ADC and demodulator. The register AX5043_AGCCOUNTER contains the current value of the AGC and can be used as an

RSSI. The step size of this RSSI is 0.625 dB. The value can be used as soon as the RF frequency generation sub−system has been programmed.

2. RSSI behind the digital IF channel filter.

The register AX5043_RSSI contains the current value of the RSSI behind the digital IF channel filter. The step size of this RSSI is 1 dB.

3. RSSI behind the digital IF channel filter high accuracy. The demodulator also provides amplitude information in the

AX5043_TRK_AMPLITUDE register. By combining both the AX5043_AGCCOUNTER and the AX5043_TRK_AMPLITUDE registers, a high resolution (better than 0.1 dB) RSSI value can be computed at the expense of a few arithmetic operations on the micro−controller. The

AXSEM RadioLab Software calculates the necessary register settings for best performance.

Modulator

Depending on the transmitter settings the modulator generates various inputs for the PA:

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Table 26. MODULATIONS

Modulation Bit = 0

ASK PA off

FSK/MSK/GFSK/GMSK Df = −f deviation

PSK DF = 0°

Bit = 1

PA on

Df = +f deviation

DF = 180°

Main Lobe Bandwidth

BW = BITRATE

BW = (1 + h) ⋅BITRATE

BW = BITRATE

Max. Bitrate

125 kBit/s

125 kBit/s

125 kBit/s f h = modulation index. It is the ratio of the deviation compared to the bit−rate; f deviation

= 0.5

⋅h⋅BITRATE,

AX8052F143 can demodulate signals with h < 32.

ASK = amplitude shift keying

FSK = frequency shift keying

MSK= minimum shift keying; MSK is a special case of

FSK, where h = 0.5, and therefore deviation

= 0.25

⋅BITRATE; the advantage of MSK over FSK is that it can be demodulated more robustly.

PSK = phase shift keying

Table 27. 4−FSK MODULATION

Modulation

4−FSK

DiBit = 00

Df = −3f deviation

DiBit = 01

Df = −f deviation

DiBit = 11

Df = +f deviation

All modulation schemes, except 4−FSK, are binary.

Amplitude can be shaped using a raised cosine waveform.

Amplitude shaping will also be performed for constant amplitude modulation ((G)FSK, (G)MSK) for ramping up and down the PA. Amplitude shaping should always be enabled.

Frequency shaping can either be hard (FSK, MSK), or

Gaussian (GMSK, GFSK), with selectable BT = 0.3 or

BT = 0.5.

DiBit = 10

Df = +3f deviation

Main Lobe Bandwidth

BW = (1 + 3 h) ⋅BITRATE

Max. Bitrate

125 kBit/s

4−FSK Frequency shaping is always hard.

Automatic Frequency Control (AFC)

The AX8052F143 features an automatic frequency tracking loop which is capable of tracking the transmitter frequency within the RX filter band width. On top of that the

AX8052F143 has a frequency tracking register

AX5043_TRKRFFREQ to synchronize the receiver frequency to a carrier signal. For AFC adjustment, the frequency offset can be computed with the following formula:

Df +

AX5043_TRKRFFREQ

2

32 f

XTAL

PWRMODE Register

The AX8052F143 transceiver features its own independent power management, independent from the microcontroller. While the microcontroller power mode is controlled through the PCON register, the

AX5043_PWRMODE register controls which parts of the transceiver are operating.

Table 28. PWRMODE REGISTER

AX5043_PWRMODE

Register

0000

0001

0101

0110

Name Description

POWERDOWN All digital and analog functions, except the register file, are disabled. The core supply voltages are switched off to conserve leakage power. Register contents are preserved.

Access to the FIFO is not possible and the contents are not preserved. POWERDOWN mode is only entered once the FIFO is empty.

DEEPSLEEP

STANDBY

The transceiver is fully turned off. All digital and analog functions are disabled. All register contents are lost.

To leave DEEPSLEEP mode the pin SEL has to be pulled low. This will initiate startup and reset of the transceiver. Then the MISO line should be polled, as it will be held low during initialization and will rise to high at the end of the initialization, when the chip becomes ready for operation.

It is recommended to use the functions ax5043_enter_deepsleep() and ax5043_wakeup_deepsleep() provided in libmf

The crystal oscillator and the reference are powered on; receiver and transmitter are off.

Register contents are preserved and accessible.

Access to the FIFO is not possible and the contents are not preserved. STANDBY is only entered once the FIFO is empty.

FIFO The reference is powered on. Register contents are preserved and accessible.

Access to the FIFO is possible and the contents are preserved.

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Table 28. PWRMODE REGISTER

AX5043_PWRMODE

Register

1000

1001

1011

1100

1101

Name

SYNTHRX

FULLRX

WOR

SYNTHTX

FULLTX

Description

The synthesizer is running on the receive frequency. Transmitter and receiver are still off.

This mode is used to let the synthesizer settle on the correct frequency for receive.

Synthesizer and receiver are running.

Receiver wakeup−on−radio mode.

The mode the same as POWERDOWN, but the 640 Hz internal low power oscillator is running.

The synthesizer is running on the transmit frequency. Transmitter and receiver are still off.

This mode is used to let the synthesizer settle on the correct frequency for transmit.

Synthesizer and transmitter are running. Do not switch into this mode before the synthesizer has completely settled on the transmit frequency (in SYNTHTX mode), otherwise spurious spectral transmissions will occur.

Table 29. A TYPICAL AX5043_PWRMODE SEQUENCE FOR A TRANSMIT SESSION

Step

3

4

1

2

PWRMODE

POWERDOWN

STANDBY

FULLTX

POWERDOWN

Remarks

The settling time is dominated by the crystal used, typical value 3ms.

Data transmission

Table 30. A TYPICAL AX5043_PWRMODE SEQUENCE FOR A RECEIVE SESSION

Step

3

4

1

2

PWRMODE [3:0]

POWERDOWN

STANDBY

FULLRX

POWERDOWN

Remarks

The settling time is dominated by the crystal used, typical value 3ms.

Data reception

Voltage Regulator

The AX8052F143 transceiver uses its own dedicated on−chip voltage regulator system to create stable supply voltages for the internal circuitry from the primary supply

VDD_IO. The I/O level of the digital pins is VDD_IO.

Pins VDD_ANA are supplied for external decoupling of the power supply used for the on−chip PA.

The voltage regulator system must be set into the appropriate state before receive or transmit operations can be initiated. This is handled automatically when programming the device modes via the

AX5043_PWRMODE register.

Register AX5043_POWSTAT contains status bits that can be read to check if the regulated voltages are ready (bit

SVIO) or if VDD_IO has dropped below the brown−out level of 1.3 V (bit SSUM).

In power−down mode the core supply voltages for digital and analog functions are switched off to minimize leakage power. Most register contents are preserved but access to the

FIFO is not possible and FIFO contents are lost.

In deep−sleep mode all supply voltages are switched off.

All digital and analog functions are disabled. All register contents are lost.

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31

AX8052F143

APPLICATION INFORMATION

Typical Application Diagrams

Connecting to Debug Adapter

RF reference XTAL

Jumper JP1

100pF

1uF

32 kHz XTAL

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

GND

AX8052F143

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

PB3

1

6

DBG_EN

2

5

DBG_RT_N

3

GND

4

DBG_CLK

DBG_DATA

GND

7

8

DBG_VDD

Debug adapter connector

Figure 11. Typical Application Diagram with Connection to the Debug Adapter

Short Jumper JP1−1 if it is desired to supply the target board from the Debug Adapter (50 mA max). Connect the bottom exposed pad of the AX8052F143 to ground.

If the debugger is not running, PB6 and PB7 are not driven by the Debug Adapter. If the debugger is running, the PB6 and PB7 values that the software reads may be set using the

Pin Emulation feature of the debugger.

PB3 is driven by the debugger only to bring the

AX8052F143 out of Deep Sleep. It is high impedance otherwise.

The 32 kHz crystal is optional, the fast crystal at pins

CLK16N and CLK16P is used as reference frequency for the

RF RX/TX. Crystal load capacitances should be chosen according to the crystal’s datasheet. At pins CLK16N and

CLK16P they the internal programmable capacitors may be used, at pins PA3 and PA4 capacitors must be connected externally.

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32

AX8052F143

Match to 50 W for Differential Antenna Pins

(868 / 433 MHz RX / TX Operation)

LC1

CC1

CF

CM1

LB1

IC antenna pins

50 W single−ended equipment or antenna

CT1

CT2

LT1

LT 2

LF

CA CA

LC2

CC2 CM2 LB2

CB2

Optional filter stage to suppress TX harmonics

Figure 12. Structure of the Differential Antenna Interface for TX/RX Operation to 50 W Single−ended Equipment or

Antenna

Table 31. TYPICAL COMPONENT VALUES

Frequency Band

868 / 915 MHz

433 MHz

470 MHz

169 MHz

LC1,2

[nH]

18

100

100

150

CC1,2

[pF]

nc nc nc

10

CT1,2

[pF]

2.7

4.3

3.9

10

LT1,2

[nH]

18

43

33

120

CM1

[pF]

6.2

11

4.7

12

CM2

[pF]

3.6

5.6

nc nc

LB1,2

[nH]

12

27

22

68

CB2

[pF]

2.7

5.1

4.7

12

CF

[pF] optional

nc nc nc

6.8

LF

[nH] optional

0 W

0 W

0 W

30

CA

[pF] optional

nc nc nc

27

Match to 50

W for Single−ended Antenna Pin

(868 / 915 / 433 MHz TX Operation)

IC Antenna

Pin CT LT

CF1

50 W single−ended equipment or antenna

LF1

LC CC

CA1

CA2

Figure 13. Structure of the Single−ended Antenna Interface for TX Operation to 50 W Single−ended Equipment or

Antenna

Table 32. TYPICAL COMPONENT VALUES

Frequency Band LC [nH] CC [pF] CT [pF] LT [nH] CF1 [pF] LF1 [nH] CA1 [pF] CA2 [pF]

868 / 915 MHz

433 MHz

18

100 nc nc

2.7

4.3

18

43

3.6

6.8

2.2

4.7

3.6

5.6

nc nc

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33

AX8052F143

Match to 50 W for Single−ended Antenna Pin

(169 MHz TX Operation)

IC Antenna

Pin

LC

CT

CC

LT

CF1

LF1

CA1

CF2

CA2

LF2

CA3

50 W single−ended equipment or antenna

Figure 14. Structure of the Single−ended Antenna Interface for TX Operation to 50 W Single−ended Equipment or

Antenna

Table 33. TYPICAL COMPONENT VALUES

Frequency Band

169 MHz

LC

[nH]

150

CC

[pF]

2.2

CT

[pF]

22

LT

[nH]

120

CF1

[pF]

4.7

LF1

[nH]

39

CF2

[pF]

1.8

LF2

[nH]

47

CA1

[pF]

33

CA2

[pF]

47

CA3

[pF]

15

Using a Dipole Antenna and the Internal TX/RX Switch

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

GND

AX8052F143

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

PB3

Figure 15. Typical Application Diagram with Dipole Antenna and Internal TX/RX Switch www.onsemi.com

34

AX8052F143

Using a Single−ended Antenna and the Internal TX/RX Switch

50 W

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

GND

AX8052F143

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

PB3

Figure 16. Typical Application Diagram with Single−ended Antenna and Internal TX/RX Switch www.onsemi.com

35

AX8052F143

Using an External High−power PA and an External TX/RX Switch

50 W

TX/RX switch

PA

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

GND

AX8052F143

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

PB3

Figure 17. Typical Application Diagram with Single−ended Antenna, External PA and External Antenna Switch www.onsemi.com

36

Using the Single−ended PA

AX8052F143

50 W

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

GND

AX8052F143

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

PB3

Figure 18. Typical Application Diagram with Single−ended Antenna, Single−ended Internal PA, without RX/TX Switch

NOTE: For details and recommendations on implementing this configuration refer to the AX8052F143 Application

Note: 0 dBm / 8 mA TX and 9.5 mA RX Configuration for the 868 MHz Band.

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37

AX8052F143

Using Two Antenna

PB3

Antenna switch

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

GND

AX8052F143

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

PB3 PB3

Figure 19. Typical Application Diagram with Two Single−ended Antenna and External Antenna Switch www.onsemi.com

38

Using an External VCO Inductor

AX8052F143

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

GND

AX8052F143

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

PB3

LVCO

Figure 20. Typical Application Diagram with External VCO Inductor www.onsemi.com

39

Using an External VCO

AX8052F143

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

GND

AX8052F143

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

PB3

VCO

Figure 21. Typical Application Diagram with External VCO www.onsemi.com

40

Using a TCXO

EN_TCXO

TCXO

C1_TCXO

C2_TCXO

AX8052F143

PB2

VDD_ANA

GND

ANTP

ANTN

ANTP1

GND

VDD_ANA

GND

AX8052F143

GND

RESET_N

DBG_EN

PB7

PB6

PB5

PB4

PB3

PB2

Figure 22. Typical Application Diagram with a TCXO

NOTE: For detailed TCXO network recommendations depending on TCXO output swing refer to the AX5043

Application Note: Use with a TCXO Reference Clock.

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41

QFN40 PACKAGE INFORMATION

Package Outline QFN40 5 x 7 mm

ON

AX8052F143−V

AWLYYWW

AX8052F143

NOTES:

1. ‘e’ represents the basic terminal pitch

2. Datum ‘C’ is the mounting surface with which the package is in contact.

3. ‘3’ specifies the vertical shift of the flat part of each terminal from the mounting surface.

4. Dimension ‘A’ includes package warpage.

5. Dimension ‘b’ applies to the metallised terminal and is measured between 0.15 to 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension ‘b’ should not be measured in the radius are

6. Package dimension take reference from JEDEC MO−220

7. AWLYYWW is the packaging lot code

8. V is the device version

9. RoHS

Figure 23. Package Outline QFN40 5 x 7 mm www.onsemi.com

42

AX8052F143

QFN40 Soldering Profile

T

P

T

L

T sMAX

T sMIN

Preheat t s

Reflow t

P

Cooling t

L

25°C

T

25 °C to Peak

Time

Figure 24. QFN40 Soldering Profile

Table 34.

Profile Feature Pb−Free Process

Average Ramp−Up Rate

Preheat Preheat

Temperature Min

Temperature Max

Time (T sMIN

to T sMAX

)

Time 25°C to Peak Temperature

Reflow Phase t

T

T

T s sMIN sMAX

25 °C to Peak

3°C/s max.

150°C

200°C

60 – 180 sec

8 min max.

Liquidus Temperature

Time over Liquidus Temperature

Peak Temperature

Time within 5°C of actual Peak Temperature

Cooling Phase t

T

L t

L

T p p

217°C

60 – 150 s

260°C

20 – 40 s

Ramp−down rate 6°C/s max.

1. All temperatures refer to the top side of the package, measured on the the package body surface.

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43

AX8052F143

QFN40 Recommended Pad Layout

1. PCB land and solder masking recommendations

are shown in Figure 25.

A = Clearance from PCB thermal pad to solder mask opening, 0.0635 mm minimum

B = Clearance from edge of PCB thermal pad to PCB land, 0.2 mm minimum

C = Clearance from PCB land edge to solder mask opening to be as tight as possible to ensure that some solder mask remains between PCB pads.

D = PCB land length = QFN solder pad length + 0.1 mm

E = PCB land width = QFN solder pad width + 0.1 mm

Figure 25. PCB Land and Solder Mask Recommendations

2. Thermal vias should be used on the PCB thermal pad (middle ground pad) to improve thermal conductivity from the device to a copper ground plane area on the reverse side of the printed circuit board. The number of vias depends on the package thermal requirements, as determined by thermal simulation or actual testing.

3. Increasing the number of vias through the printed circuit board will improve the thermal conductivity to the reverse side ground plane and external heat sink. In general, adding more metal through the PC board under the IC will improve operational heat transfer, but will require careful attention to uniform heating of the board during assembly.

Assembly Process

Stencil Design & Solder Paste Application

1. Stainless steel stencils are recommended for solder paste application.

2. A stencil thickness of 0.125 – 0.150 mm

(5 – 6 mils) is recommended for screening.

3. For the PCB thermal pad, solder paste should be printed on the PCB by designing a stencil with an array of smaller openings that sum to 50% of the

QFN exposed pad area. Solder paste should be applied through an array of squares (or circles) as

shown in Figure 26.

4. The aperture opening for the signal pads should be between 50−80% of the QFN pad area as shown in

Figure 27.

5. Optionally, for better solder paste release, the aperture walls should be trapezoidal and the corners rounded.

6. The fine pitch of the IC leads requires accurate alignment of the stencil and the printed circuit board. The stencil and printed circuit assembly should be aligned to within + 1 mil prior to application of the solder paste.

7. No−clean flux is recommended since flux from underneath the thermal pad will be difficult to clean if water−soluble flux is used.

Figure 26. Solder Paste Application on Exposed Pad www.onsemi.com

44

Minimum 50% coverage

AX8052F143

62% coverage Maximum 80% coverage

Table 35. DEVICE VERSIONS

Device Marking

AX8052F143−1

AX8052F143−2

Figure 27. Solder Paste Application on Pins

AX8052 Version

1

1C

AX5043 Version

1

1

ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: [email protected]

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USA/Canada

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Phone: 421 33 790 2910

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Phone: 81−3−5817−1050

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45

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative

AX8052F143/D

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