AEC Q100 Grade 1 Compliant

FM25CL64B

–

Automotive Temp.

64Kb FRAM Serial 3V Memory

Features

64K bit Ferroelectric Nonvolatile RAM

 Organized as 8,192 x 8 bits

 High Endurance 10 Trillion (10

13

) Read/Writes

 NoDelay™ Writes

 Advanced High-Reliability Ferroelectric Process

Sophisticated Write Protection Scheme

 Hardware Protection

 Software Protection

Low Power Consumption

 Low Voltage Operation 3.0-3.6V

 6 A Standby Current (+85C)

Fast Serial Peripheral Interface - SPI

 Up to 16 MHz Frequency

 Direct Hardware Replacement for EEPROM

 SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1)

Industry Standard Configuration

 Automotive Temperature -40C to +125C o

Qualified to AEC Q100 Specification

 “Green”/RoHS 8-pin SOIC

Description Pin Configuration

The FM25CL64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a

RAM. It provides reliable data retention for years while eliminating the complexities, overhead, and system level reliability problems caused by

EEPROM and other nonvolatile memories.

The FM25CL64B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte has been transferred to the device. The next bus cycle may commence without the need for data polling.

The FM25CL64B is capable of supporting 10

13 read/write cycles, or 10 million times more write cycles than EEPROM.

These capabilities make the FM25CL64B ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding automotive controls where the long write time of EEPROM can cause data loss.

The FM25CL64B provides substantial benefits to users of serial EEPROM as a hardware drop-in replacement. The FM25CL64B uses the high-speed

SPI bus, which enhances the high-speed write capability of FRAM technology. Device specifications are guaranteed over the automotive temperature range of -40°C to +125°C.

WP

VSS

Pin Name

/CS

/WP

/HOLD

SCK

SI

SO

VDD

VSS

CS

SO

1

2

3

4

Function

8

7

6

5

Chip Select

Write Protect

Hold

Serial Clock

Serial Data Input

Serial Data Output

Supply Voltage

Ground

VDD

HOLD

SCK

SI

Ordering Information

FM25CL64B-GA

“Green”/RoHS 8-pin SOIC,

Automotive Grade 1

FM25CL64B-GATR

“Green”/RoHS 8-pin SOIC,

Automotive Grade 1,

Tape & Reel

This product conforms to specifications per the terms of the Ramtron standard warranty.

The product has completed Ramtron‟s internal qualification testing and has reached production status.

Rev. 3.0

Sept. 2011

Ramtron International Corporation

1850 Ramtron Drive, Colorado Springs, CO 80921

(800) 545-FRAM, (719) 481-7000 http://www.ramtron.com

Page 1 of 13

FM25CL64B - Automotive Temp.

WP

CS

HOLD

SCK

Instruction Decode

Clock Generator

Control Logic

Write Protect

1,024 x 64

FRAM Array

Instruction Register

`

Address Register

Counter

13

8

SI SO

Data I/O Register

3

Nonvolatile Status

Register

Figure 1. Block Diagram

Pin Descriptions

Pin Name

/CS

SCK

/HOLD

/WP

SI

SO

VDD

VSS

I/O Description

Input Chip Select: This active low input activates the device. When high, the device enters low-power standby mode, ignores other inputs, and all outputs are tri-stated. When low, the device internally activates the SCK signal. A falling edge on /CS must occur prior to every op-code.

Input Serial Clock: All I/O activity is synchronized to the serial clock. Inputs are latched on the rising edge and outputs occur on the falling edge. Since the device is static, the clock frequency may be any value between 0 and 16 MHz and may be interrupted at any time.

Input Hold: The /HOLD pin is used when the host CPU must interrupt a memory operation for another task. When /HOLD is low, the current operation is suspended. The device ignores any transition on SCK or /CS. All transitions on /HOLD must occur while

SCK is low.

Input Write Protect: This active low pin prevents write operations to the Status Register.

This is critical since other write protection features are controlled through the Status

Register. A complete explanation of write protection is provided below. *Note that the function of /WP is different from the FM25040 where it prevents all writes to the part.

Input Serial Input: All data is input to the device on this pin. The pin is sampled on the rising edge of SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications.

* SI may be connected to SO for a single pin data interface.

Output Serial Output: This is the data output pin. It is driven during a read and remains tristated at all other times including when /HOLD is low. Data transitions are driven on the falling edge of the serial clock.

* SO may be connected to SI for a single pin data interface.

Supply Power Supply (3.0V to 3.6V)

Supply Ground

Rev. 3.0

Sept. 2011 Page 2 of 13

Overview

The FM25CL64B is a serial FRAM memory. The memory array is logically organized as 8,192 x 8 and is accessed using an industry standard Serial

Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25CL64B and a serial EEPROM with the same pinout is the FRAM‟s superior write performance.

Memory Architecture

When accessing the FM25CL64B, the user addresses

8,192 locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op-code, and a two-byte address. The upper 3 bits of the address range are „don‟t care‟ values. The complete address of 13-bits specifies each byte address uniquely.

Most functions of the FM25CL64B either are controlled by the SPI interface or are handled automatically by on-board circuitry. The access time for memory operation is essentially zero, beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the SPI bus.

Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section.

Users expect several obvious system benefits from the FM25CL64B due to its fast write cycle and high endurance as compared with EEPROM. In addition there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an

EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle.

Note that the FM25CL64B contains no power management circuits other than a simple internal poweron reset. It is the user‟s responsibility to ensure that VDD is within datasheet tolerances to prevent incorrect operation.

Serial Peripheral Interface

– SPI Bus

The FM25CL64B employs a Serial Peripheral

Interface (SPI) bus. It is specified to operate at speeds

Rev. 3.0

Sept. 2011

FM25CL64B - Automotive Temp.

up to 16 MHz. This high-speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface.

It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The

FM25CL64B operates in SPI Mode 0 and 3.

The SPI interface uses a total of four pins: clock, data-in, data-out, and chip select. It is possible to connect the two data pins together. Figure 2 illustrates a typical system configuration using the

FM25CL64B with a microcontroller that offers an

SPI port. Figure 3 shows a similar configuration for a microcontroller that has no hardware support for the

SPI bus.

Protocol Overview

The SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25CL64B will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device will make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the

FM25CL64B supports modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked into the

FM25CL64B on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge.

The SPI protocol is controlled by op-codes. These op-codes specify the commands to the device. After

/CS is activated the first byte transferred from the bus master is the op-code. Following the op-code, any addresses and data are then transferred. Note that the

WREN and WRDI op-codes are commands with no subsequent data transfer.

Important: The /CS pin must go inactive after an operation is complete and before a new op-code can be issued. There is one valid op-code only per

active chip select.

Page 3 of 13

FM25CL64B - Automotive Temp.

SCK

MOSI

MISO

SPI

Microcontroller

SS1

SS2

HOLD1

HOLD2

SO SI SCK

FM25CL64B

CS HOLD

SO SI SCK

FM25CL64B

CS HOLD

MOSI: Master Out, Slave In

MISO: Master In, Slave Out

SS: Slave Select

Figure 2. System Configuration with SPI port

Microcontroller

SO SI SCK

FM25CL64B

CS HOLD

SPI Mode 0: CPOL=0, CPHA=0

Figure 3. System Configuration without SPI port

7

SPI Mode 3: CPOL=1, CPHA=1

6 5 4 3 2 1 0

Rev. 3.0

Sept. 2011

7 6 5 4 3 2 1 0

Figure 4. SPI Modes 0 & 3

Page 4 of 13

Data Transfer

All data transfers to and from the FM25CL64B occur in 8-bit groups. They are synchronized to the clock signal (SCK), and they transfer most significant bit

(MSB) first. Serial inputs are registered on the rising edge of SCK. Outputs are driven from the falling edge of SCK.

Command Structure

There are six commands called op-codes that can be issued by the bus master to the FM25CL64B. They are listed in the table below. These op-codes control the functions performed by the memory. They can be divided into three categories. First, there are commands that have no subsequent operations. They perform a single function such as to enable a write operation. Second are commands followed by one byte, either in or out. They operate on the Status

Register. The third group includes commands for memory transactions followed by address and one or more bytes of data.

Table 1. Op-code Commands

Name Description Op-code

WREN Set Write Enable Latch 0000 0110b

WRDI

Write Disable 0000 0100b

RDSR Read Status Register

0000 0101b

0000 0001b WRSR Write Status Register

READ

Read Memory Data 0000 0011b

WRITE Write Memory Data 0000 0010b

FM25CL64B - Automotive Temp.

WREN - Set Write Enable Latch

The FM25CL64B will power up with writes disabled. The WREN command must be issued prior to any write operation. Sending the WREN op-code will allow the user to issue subsequent op-codes for write operations. These include writing the Status

Register and writing the memory.

Sending the WREN op-code causes the internal

Write Enable Latch to be set. A flag bit in the Status

Register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted.

Attempting to write the WEL bit in the Status

Register has no effect. Completing any write operation will automatically clear the write-enable latch and prevent further writes without another

WREN command. Figure 5 below illustrates the

WREN command bus configuration.

WRDI - Write Disable

The WRDI command disables all write activity by clearing the Write Enable Latch. The user can verify that writes are disabled by reading the WEL bit in the Status Register and verifying that WEL=0.

Figure 6 illustrates the WRDI command bus configuration.

Figure 5. WREN Bus Configuration

Rev. 3.0

Sept. 2011

Figure 6. WRDI Bus Configuration

Page 5 of 13

RDSR - Read Status Register

The RDSR command allows the bus master to verify the contents of the Status register. Reading Status provides information about the current state of the write protection features. Following the RDSR opcode, the FM25CL64B will return one byte with the contents of the Status register. The Status register is described in detail in a later section.

FM25CL64B - Automotive Temp.

WRSR

– Write Status Register

The WRSR command allows the user to select certain write protection features by writing a byte to the Status register. Prior to issuing a WRSR command, the /WP pin must be high or inactive.

Note that on the FM25CL64B, /WP only prevents writing to the Status register, not the memory array.

Prior to sending the WRSR command, the user must send a WREN command to enable writes. Note that executing a WRSR command is a write operation and therefore clears the Write Enable Latch.

Figure 7. RDSR Bus Configuration

Figure 8. WRSR Bus Configuration

(WREN not shown)

Status Register & Write Protection

The write protection features of the FM25CL64B are multi-tiered. First, a WREN op-code must be issued prior to any write operation. Assuming that writes are enabled using WREN, writes to memory are controlled by the Status register. As described above, writes to the Status Register are performed using the

WRSR command and subject to the /WP pin. The

Status register is organized as follows.

Table 2. Status Register

Bit 7 6 5 4 3 2 1 0

Name WPEN 0 0 0 BP1 BP0 WEL 0

Bits 0 and 4-6 are fixed at 0 and cannot be modified.

Note that bit 0 (

“Ready” in EEPROMs) is unnecessary as the FRAM writes in real-time and is never busy. The WPEN, BP1 and BP0 control write protection features. They are nonvolatile (shaded

Rev. 3.0

Sept. 2011 yellow). The WEL flag indicates the state of the

Write Enable Latch. Attempting to directly write the

WEL bit in the Status Register has no effect on its state. This bit is internally set and cleared via the

WREN and WRDI commands, respectively.

BP1 and BP0 are memory block write protection bits. They specify portions of memory that are write protected as shown in the following table.

Table 3. Block Memory Write Protection

BP1 BP0 Protected Address Range

0 0 None

0

1

1

1

0

1

1800h to 1FFFh (upper ¼)

1000h to 1FFFh (upper ½)

0000h to 1FFFh (all)

Page 6 of 13

Rev. 3.0

Sept. 2011

The BP1 and BP0 bits and the Write Enable Latch are the only mechanisms that protect the memory from writes. The remaining write protection features protect inadvertent changes to the block protect bits.

The WPEN bit controls the effect of the hardware

/WP pin. When WPEN is low, the /WP pin is ignored. When WPEN is high, the /WP pin controls write access to the Status Register. Thus the Status register is write protected if WPEN=1 and /WP=0.

Table 4. Write Protection

WEL

0

1

1

1

WPEN

X

0

1

1

/WP

X

X

0

1

Protected Blocks

Protected

Protected

Protected

Protected

Memory Operation

The SPI interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the FRAM technology. Unlike SPI-bus

EEPROMs, the FM25CL64B can perform sequential writes at bus speed. No page register is needed and any number of sequential writes may be performed.

Write Operation

All writes to the memory array begin with a WREN op-code. The next op-code is the WRITE instruction.

This op-code is followed by a two-byte address value. The upper 3-bits of the address are ignored. In total, the 13-bits specify the address of the first data byte of the write operation. Subsequent bytes are data and they are written sequentially. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 1FFFh is reached, the counter will roll over to 0000h. Data is written MSB first. A write operation is shown in

Figure 9.

Unlike EEPROMs, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the

FM25CL64B - Automotive Temp.

This scheme provides a write protection mechanism, which can prevent software from writing the memory under any circumstances. This occurs if the

BP1 and BP0 are set to 1, the WPEN bit is set to 1, and /WP is set to 0. This occurs because the block protect bits prevent writing memory and the /WP signal in hardware prevents altering the block protect bits (if WPEN is high). Therefore in this condition, hardware must be involved in allowing a write operation. The following table summarizes the write protection conditions.

Unprotected Blocks Status Register

Protected

Unprotected

Protected

Unprotected

Unprotected

Unprotected

Protected

Unprotected

8 th

clock). The rising edge of /CS terminates a

WRITE op-code operation.

Read Operation

After the falling edge of /CS, the bus master can issue a READ op-code. Following this instruction is a twobyte address value. The upper 3-bits of the address are ignored. In total, the 13-bits specify the address of the first byte of the read operation. After the op-code and address are complete, the SI line is ignored. The bus master issues 8 clocks, with one bit read out for each. Addresses are incremented internally as long as the bus master continues to issue clocks. If the last address of 1FFFh is reached, the counter will roll over to 0000h. Data is read MSB first. The rising edge of /CS terminates a READ op-code operation.

A read operation is shown in Figure 10.

Hold

The /HOLD pin can be used to interrupt a serial operation without aborting it. If the bus master pulls the /HOLD pin low while SCK is low, the current operation will pause. Taking the /HOLD pin high while SCK is low will resume an operation. The transitions of /HOLD must occur while SCK is low, but the SCK pin can toggle during a hold state.

Page 7 of 13

CS

SCK

FM25CL64B - Automotive Temp.

SI

SO

0 1 2 3 4 5 6 7 0 1 2 3 4 5 3 4 5 6 7 0 1 2 3 4 5 6 7 op-code

0 0 0 0 0 0 1 0

13-bit Address

X X X 12 11 10

MSB

Data

4 3 2 1 0 7 6 5 4 3 2 1 0

LSB MSB LSB

Figure 9. Memory Write

(WREN not shown)

CS

0 1 2 3 4 5 6 7 0 1 2 3 4 5 3 4 5 6 7 0 1 2 3 4 5 6 7

SCK

SI op-code

0 0 0 0 0 0 1 1

13-bit Address

X X X 12 11 10

MSB

4 3 2 1 0

LSB MSB LSB

Data

7 6 5 4 3 2 1 0 SO

Figure 10. Memory Read

Endurance

The FM25CL64B devices are capable of being accessed at least 10

13

times, reads or writes. An F-

RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows and columns. Rows are defined by

64-bits each. The entire row is internally accessed once whether a single byte or all eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. The table below shows endurance calculations for 64-byte repeating loop, which includes an op-code, a starting address, and a sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop.

F-RAM read and write endurance is virtually unlimited even at 10MHz clock rate. A12-A3 and column addresses by A2-A0. See Block

Diagram (pg 2) which shows the array as 1K rows of

Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop

SCK Freq

(MHz)

10

5

1

Endurance

Cycles/sec.

18,660

9,330

1,870

Endurance

Cycles/year

5.88 x 10

11

2.94 x 10

11

5.88 x 10

10

Years to Reach

Limit

17.0

34.0

170.1

Rev. 3.0

Sept. 2011 Page 8 of 13

Electrical Specifications

Absolute Maximum Ratings

FM25CL64B - Automotive Temp.

Symbol Description Ratings

V

DD

V

IN

Power Supply Voltage with respect to V

SS

Voltage on any pin with respect to V

SS

-1.0V to +5.0V

-1.0V to +5.0V

T

STG

T

LEAD

V

ESD

Storage Temperature

Lead Temperature (Soldering, 10 seconds)

Electrostatic Discharge Voltage

- Human Body Model

(AEC-Q100-002 Rev. E)

- Charged Device Model

(AEC-Q100-011 Rev. B) and V

IN

< V

DD

+1.0V

-55

C to + 125C

260

 C

4kV

1.25kV

- Machine Model

(AEC-Q100-003 Rev. E)

300V

Package Moisture Sensitivity Level MSL-1

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.

DC Operating Conditions (T

A

= -40

 C to +125 C, V

DD

= 3.0V to 3.6V unless otherwise specified)

Symbol Parameter Min Typ Max Units Notes

V

I

DD

DD

Power Supply Voltage

VDD Supply Current

@ SCK = 1.0 MHz

@ SCK = 16.0 MHz

3.0 3.3

-

-

3.6

0.3

3

I

SB

I

LI

I

LO

V

IH

V

IL

V

OH

Standby Current

@ +85

C

@ +125

C

Input Leakage Current

Output Leakage Current

Input High Voltage

Input Low Voltage

-

-

0.75 V

DD

V

-0.3

DD

– 0.8

-

-

Output High Voltage

@ I

OH

= -2 mA

Output Low Voltage V

OL

-

V

HYS

@ I

OL

= 2 mA

Input Hysteresis 0.05 V

DD

Notes

1.

SCK toggling between V

DD

-0.3V and V

SS

, other inputs V

SS

or V

DD

-0.3V.

2.

SCK = SI = /CS=V

3.

V

SS

 V

IN

 V

DD

DD

. All inputs V

SS

or V

DD

.

and V

SS

 V

OUT

 V

DD

.

4.

Characterized but not 100% tested in production. Applies only to /CS and SCK pins.

6

20

1

1

V

DD

+ 0.3

0.25 V

DD

-

0.4

-

V mA mA

A

A

A

A

V

V

V

V

V

3

3

1

2

4

Rev. 3.0

Sept. 2011 Page 9 of 13

FM25CL64B - Automotive Temp.

AC Parameters (T

A

= -40

 C to +125 C, V

DD

= 3.0V to 3.6V unless otherwise specified)

Symbol Parameter Min Max Units Notes

f

CK t

CH t

CL t

CSU t

CSH t

OD t

ODV t

OH t

D t

R t

F t

SU t

H t

HS t

HH t

HZ t

LZ

SCK Clock Frequency

Clock High Time

Clock Low Time

Chip Select Setup

Chip Select Hold

Output Disable Time

Output Data Valid Time

Output Hold Time

Deselect Time

Data In Rise Time

Data In Fall Time

Data Setup Time

Data Hold Time

/HOLD Setup Time

/HOLD Hold Time

/HOLD Low to Hi-Z

/HOLD High to Data Active

Notes

1.

t

CH

+ t

CL

= 1/f

CK

.

2.

Characterized but not 100% tested in production.

3.

Rise and fall times measured between 10% and 90% of waveform.

Capacitance (T

A

= 25

 C, f=1.0 MHz, V

DD

= 3.3V)

Symbol Parameter

0

25

25

10

10

0

60

5

5

10

10

16

20

25

50

50

20

20

MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Min

-

-

Max

8

6

Units

pF pF

2

2

2,3

2,3

2

1

1

Notes

1

1

C

O

C

I

Output Capacitance (SO)

Input Capacitance

Notes

1.

This parameter is periodically sampled and not 100% tested.

AC Test Conditions

Input Pulse Levels

Input rise and fall times

10% and 90% of V

5 ns

DD

Power Cycle Timing

Input and output timing levels

Output Load Capacitance

0.5 V

30 pF

DD

V

DD

min

V

DD t

VR t

VF t

PD t

PU

CS

Power Cycle Timing (T

A

= -40

 C to +125 C, V

DD

= 3.0V to 3.6V unless otherwise specified)

Symbol Parameter Min Max Units

t t t

PU t

PD

VR

VF

V

DD

(min) to First Access Start

Last Access Complete to V

DD

V

V

DD

DD

Rise Time

Fall Time

(min)

10

0

30

100

-

-

-

- ms

s

s/V

s/V

Notes

1.

Slope measured at any point on V

DD

waveform.

Notes

1

1

Rev. 3.0

Sept. 2011 Page 10 of 13

Serial Data Bus Timing

tCSU tSU tH

1/fCK tODV tF tR tOH

/Hold Timing

FM25CL64B - Automotive Temp.

tCL tCH tD tCSH tOD

Data Retention (V

DD

= 3.0V to 3.6V unless otherwise specified)

Parameter Min Max Units Notes

Data Retention

@

T

@

T

A

A

= +55

C

= +105

C

@

T

A

= +125

C

17

10,000

1,000

-

-

-

Years

Hours

Hours

Note : Data retention qualification tests are accelerated tests and are performed such that all three conditions have been applied : (1) 17 years at a temperature of +55

C, (2) 10,000 hours at +105C, and (3) 1,000 hours at +125C.

Typical Grade 1 Operating Profile

Typical Grade 1 Storage Profile

1600

1400

1200

1000

800

600

400

200

0

70 75 80 85 90 95 100 105 110 115 120 125

Temperature (°C)

25000

20000

15000

10000

5000

0

0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

Temperature (°C)

Rev. 3.0

Sept. 2011 Page 11 of 13

Mechanical Drawing

8-pin SOIC (JEDEC Standard MS-012 variation AA)

Pin 1

4.90

±

0.10

FM25CL64B - Automotive Temp.

3.90

±

0.10

6.00

±

0.20

1.35

1.75

Recommended PCB Footprint

3.70

7.70

2.00

1.27

0.25

0.50

0.65

45



0.19

0.25

1.27

0.33

0.51

0.10

0.25

0.10 mm

0

- 8

0.40

1.27

Refer to JEDEC MS-012 for complete dimensions and notes.

All dimensions in millimeters.

SOIC Package Marking Scheme

XXXXXXXPT

RLLLLLLL

RICYYWW

Legend:

XXXXXX= part number, P= package type (G=SOIC),

T= temp (A=automotive grade, blank=ind.)

R=rev code, LLLLLLL= lot code

RIC=Ramtron Int‟l Corp, YY=year, WW=work week

Example: FM25CL64B

, “Green” SOIC, Automotive Temperature,

Rev A, Lot L3502G1, Year 2011, Work Week 04

25CL64BGA

AL3502G1

RIC1104

Rev. 3.0

Sept. 2011 Page 12 of 13

Revision History

Revision

1.0

1.1

3.0

Date Summary

2/18/2011 Initial release.

5/3/2011 Added ESD ratings.

9/12/2011 Changed to Production status.

FM25CL64B - Automotive Temp.

Rev. 3.0

Sept. 2011 Page 13 of 13