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TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

TMS320C6654 Fixed and Floating-Point Digital Signal Processor

1 C6654 Features and Description

1

1.1

Features

• One TMS320C66x™ DSP Core Subsystem

(CorePac) With

– 850 MHz C66x Fixed/Floating-Point CPU Core

• 27.2 GMAC/Core for Fixed Point @ 850 MHz

• 13.6 GFLOP/Core for Floating Point @ 850

MHz

– Memory

• 32K Byte L1P Per Core

• 32K Byte L1D Per Core

• 1024K Byte Local L2 Per Core

• Multicore Shared Memory Controller (MSMC)

– Memory Protection Unit for DDR3_EMIF

• Multicore Navigator

– 8192 Multipurpose Hardware Queues with

Queue Manager

– Packet-Based DMA for Zero-Overhead

Transfers

• Peripherals

– PCIe Gen2

• Single Port Supporting 1 or 2 Lanes

• Supports Up To 5 GBaud Per Lane

– Gigabit Ethernet (GbE) Subsystem

• One SGMII Port

• Supports 10/100/1000 Mbps Operation

– 32-Bit DDR3 Interface

• DDR3-1066

• 8G Byte Addressable Memory Space

– 16-Bit EMIF

– Universal Parallel Port

• Two Channels of 8 bits or 16 bits Each

• Supports SDR and DDR Transfers

– Two UART Interfaces

– Two Multichannel Buffered Serial Ports

(McBSP)

– I

2

C Interface

– 32 GPIO Pins

– SPI Interface

– Semaphore Module

– Eight 64-Bit Timers

– Two On-Chip PLLs

• Commercial Temperature:

– 0°C to 85°C

• Extended Temperature:

– - 40°C to 100°C

• Extended Low Temperature:

– - 55°C to 100°C

1.2

KeyStone Architecture

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore

Shared Memory Controller, and HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by memory access.

HyperLink provides a 40-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its lowprotocol overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

www.ti.com

1.3

Trademarks

All trademarks are the property of their respective owners.

1.4

Device Description

The C6654 DSP is a highest-performance fixed/floating-point DSP that is based on TI's KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 850 MHz. For developers of a broad range of applications, such as mission critical, medical imaging, test and automation, and other applications requiring high performance, TI's C6654 DSP offers up to 850 MHz cumulative DSP and enables a platform that is power-efficient and easy to use. In addition, it is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intra-device and inter-device communication that allows the various DSP resources to operate efficiently and seamlessly. Central to this architecture are key components such as

Multicore Navigator that allows for efficient data management between the various device components.

The TeraNet is a non-blocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating point capability and the per core raw computational performance is an industry-leading 27.2 GMACS/core and 13.6 GFLOPS/core (@850 MHz frequency). It can execute 8 single precision floating point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE754 compliant. The C66x core incorporates 90 new instructions

(compared to the C64x+ core) targeted for floating point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backwards code compatible with TI's previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C6654 DSP integrates a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, there is 1024KB of dedicated memory per core that can be configured as mapped RAM or cache. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at 1066 MHz and has ECC DRAM support.

This family supports a number of high speed standard interfaces, PCI Express Gen2, and Gigabit

Ethernet. It also includes I

2

C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port, and a 16-bit asynchronous EMIF, along with general purpose CMOS IO.

The C6654 device has a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

2

C6654 Features and Description

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1.5

Functional Block Diagram

Figure 1-1

shows the functional block diagram of the device.

Memory Subsystem

32-Bit

DDR3 EMIF

MSMC

Debug & Trace

Boot ROM

Semaphore

Timers

Power

Management

PLL

EDMA

´

2

C66x™

CorePac

32KB L1

P-Cache

32KB L1

D-Cache

1024KB L2 Cache

1 Core @ 850 MHz

TeraNet

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

C6654

Ethernet

MAC

Multicore Navigator

Queue

Manager

Packet

DMA

SGMII

Figure 1-1. Functional Block Diagram

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C6654 Features and Description

3

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

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Table of Contents

1 C6654 Features and Description

.....................

1

1.1

Features

..............................................

1

1.2

KeyStone Architecture

................................

1

1.3

Trademarks

...........................................

2

1.4

Device Description

...................................

2

1.5

Functional Block Diagram

............................

3

2 Revision History

3 Device Overview

........................................

5

.........................................

6

3.1

Device Characteristics

................................

6

3.2

DSP Core Description

................................

7

3.3

Memory Map Summary

.............................

10

3.4

Boot Sequence

......................................

14

3.5

Boot Modes Supported and PLL Settings

...........

15

3.6

PLL Boot Configuration Settings

3.7

Second-Level Bootloaders

....................

35

..........................

35

3.8

Terminals

............................................

36

3.9

Terminal Functions

..................................

41

3.10

Development and Support

..........................

63

3.11

Related Documentation from Texas Instruments

4 Device Configuration

...

65

..................................

66

4.1

Device Configuration at Device Reset

..............

66

4.2

Peripheral Selection After Device Reset

4.3

Device State Control Registers

............

67

.....................

67

4.4

Pullup/Pulldown Resistors

..........................

94

5 System Interconnect

...................................

95

5.1

Internal Buses and Switch Fabrics

..................

95

5.2

Switch Fabric Connections Matrix

5.3

TeraNet Switch Fabric Connections

..................

95

................

98

5.4

Bus Priorities

.......................................

101

6 C66x CorePac

..........................................

103

6.1

Memory Architecture

...............................

104

6.2

Memory Protection

.................................

107

6.3

Bandwidth Management

...........................

108

6.4

Power-Down Control

...............................

108

6.5

C66x CorePac Revision

...........................

109

6.6

C66x CorePac Register Descriptions

..............

109

7 Device Operating Conditions

.......................

110

7.1

Absolute Maximum Ratings

........................

110

7.2

Recommended Operating Conditions

.............

111

7.3

Electrical Characteristics

...........................

112

7.4

Power Supply to Peripheral I/O Mapping

.........

113

8 Peripheral Information and Electrical

Specifications

.........................................

114

8.1

Recommended Clock and Control Signal Transition

Behavior

............................................

114

8.2

Power Supplies

....................................

114

8.3

Power Sleep Controller (PSC)

.....................

122

8.4

Reset Controller

....................................

126

8.5

Main PLL and PLL Controller

......................

132

8.6

DDR3 PLL

..........................................

149

8.7

Enhanced Direct Memory Access (EDMA3)

Controller

...........................................

152

8.8

Interrupts

...........................................

156

8.9

Memory Protection Unit (MPU)

....................

177

8.10

DDR3 Memory Controller

..........................

192

8.11

I

2

C Peripheral

......................................

193

8.12

I

2

C Timing Requirements

.........................

196

8.13

SPI Peripheral

......................................

198

8.14

UART Peripheral

...................................

201

8.15

PCIe Peripheral

....................................

202

8.16

EMIF16 Peripheral

.................................

203

8.17

Ethernet Media Access Controller (EMAC)

........

206

8.18

Management Data Input/Output (MDIO)

...........

212

8.19

Timers

..............................................

214

8.20

General-Purpose Input/Output (GPIO)

.............

215

8.21

Semaphore2

.......................................

216

8.22

Multichannel Buffered Serial Port (McBSP)

........

216

8.23

Universal Parallel Port (uPP)

......................

221

8.24

Emulation Features and Capability

................

226

8.25

Related Links

......................................

229

9 Mechanical Data

.......................................

230

9.1

Thermal Data

......................................

230

9.2

Packaging Information

.............................

230

4

Table of Contents

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TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from September 1, 2012 to April 24, 2015 Page

• Removed Security/Key Manager from

Figure 1-1

................................................................................

3

• Removed "Secure ROM Boot" and changed "Public ROM Boot" to "ROM Boot" in

Section 3.5

.........................

15

• Added Boot Parameter Table section

............................................................................................

26

• Updated OUTPUT_DIVIDE default value and PLL clock formula in PLL Settings section

................................

35

• Clarified SmartReflex pin output type

.............................................................................................

51

• Removed SECURITY information from

Figure 3-29

............................................................................

64

• Added DDR3PLLCTL1 register to Device Status Control Registers table

...................................................

69

• Revised IPCGRH register de0scription

...........................................................................................

83

• Corrected SmartReflex peripheral I/O Buffer Type from LVCMOS category to Open drain

• Updated ”slow peripherals” in SYSCLK7 description

.............................

113

........................................................................

134

• Updated BWADJ value setting description in Main/DDR3 PLL contol registers

...........................................

146

• Updated all SerDes clocks to discrete frequencies in the Clock Input Timing Requirements table

....................

147

• Corrected differential clock rise and fall time in the PLL timing table for the clock inputs that feed into the LJCB clock buffers

........................................................................................................................

147

• Added note to DDR3 PLL initialization sequence

.............................................................................

150

• Clarified table caption and first column heading

...............................................................................

157

• Corrected MPU0 Memory Protection End Address from 0x026203FF to 0x026207FF

..................................

177

• Removed SECURITY LEVEL column from

Table 8-43

......................................................................

178

• Updated/Changed Bit 7 of

Table 8-53

from "NS" to "Reserved"

............................................................

189

• Added MPU Registers Reset Values section

..................................................................................

190

• Updated the Min/Max values of EMIF read cycle time and write cycle time

...............................................

203

• Updated Timer number description across the data manual

.................................................................

214

• Changed all footnote references from CORECLK to SYSCLK1

.............................................................

215

• Updated the descriptions of how Semaphore module is accessible

........................................................

216

• Corrected McBSP FIFO Control and Status Register address to be 0x021B6000 for McBSP0 and 0x021BA000 for McBSP1

.........................................................................................................................

217

• Corrected McBSP FIFO Data Register address to be 0x22400000 for McBSP1

.........................................

217

• Updated Trace Electrical Timing tables and Timing diagrams

...............................................................

227

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Revision History

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TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

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3 Device Overview

3.1

Device Characteristics

Table 3-1. Characteristics of the C6654 Processor

Peripheral

HARDWARE FEATURES

DDR3 Memory Controller (32-bit bus width) [1.5 V I/O]

(clock source = DDRREFCLKN|P)

DDR3 Maximum Data Rate

EDMA3 (64 independent channels) [DSP/3 clock rate]

PCIe (2 lanes)

10/100/1000 Ethernet

Management Data Input/Output (MDIO)

EMIF16

McBSP

SPI

UART uPP

I

2

C

64-Bit Timers (configurable) (internal clock source = CPU/6 clock frequency)

General-Purpose Input/Output port (GPIO)

TMS320C6654

1

1066

1

1

1

1

1

2

1

2

1

1

8 (each configurable as two 32-bit timers)

On-Chip

Memory

CorePac Memory

ROM Memory

C66x CorePac

Revision ID

Cycle Time

CorePac Revision ID Register (address location: 0181 2000h)

JTAG BSDL_ID JTAGID register (address location: 0262 0018h)

Frequency MHz ns

Core (V)

Voltage

I/O (V)

Process

Technology

µm

BGA Package 21 mm × 21mm

Product

Status

(1)

Product Preview (PP), Advance Information (AI), or Production Data (PD)

32KB L1 Program Memory [SRAM/Cache]

32KB L1 Data Memory [SRAM/Cache]

1024KB L2 Unified Memory/Cache

128KB L3 ROM

See

See

32

Section 6.5

Section 4.3.3

850 (0.85 GHz)

1.175 (0.85 GHz)

SmartReflex variable supply

1.0 V, 1.5 V, and 1.8 V

0.040 µm

625-Pin Flip-Chip Plastic BGA (CZH or GZH)

PD

(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

6

Device Overview

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TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

3.2

DSP Core Description

The C66x Digital Signal Processor (DSP) extends the performance of the C64x+ and C674x DSPs through enhancements and new features. Many of the new features target increased performance for vector processing. The C64x+ and C674x DSPs support 2-way SIMD operations for 16-bit data and 4-way

SIMD operations for 8-bit data. On the C66x DSP, the vector processing capability is improved by extending the width of the SIMD instructions. C66x DSPs can execute instructions that operate on 128-bit vectors. For example the QMPY32 instruction is able to perform the element-to-element multiplication between two vectors of four 32-bit data each. The C66x DSP also supports SIMD for floating-point operations. Improved vector processing capability (each instruction can process multiple data in parallel) combined with the natural instruction level parallelism of C6000 architecture (e.g execution of up to 8 instructions per cycle) results in a very high level of parallelism that can be exploited by DSP programmers through the use of TI's optimized C/C++ compiler.

The C66x DSP consists of eight functional units, two register files, and two data paths as shown in

Figure 3-1

. The two general-purpose register files (A and B) each contain 32 32-bit registers for a total of

64 registers. The general-purpose registers can be used for data or can be data address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, and 64-bit data. Multiplies also support 128-bit data. 40-bit-long or 64-bit-long values are stored in register pairs, with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register

(which is always an odd-numbered register). 128-bit data values are stored in register quadruplets, with the 32 LSBs of data placed in a register that is a multiple of 4 and the remaining 96 MSBs in the next 3 upper registers.

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from memory to the register file and store results from the register file into memory.

Each C66x .M unit can perform one of the following fixed-point operations each clock cycle: four 32 × 32 bit multiplies, sixteen 16 × 16 bit multiplies, four 16 × 32 bit multiplies, four 8 × 8 bit multiplies, four 8 × 8 bit multiplies with add operations, and four 16 × 16 multiplies with add/subtract capabilities. There is also support for Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as

FFTs and modems require complex multiplication. Each C66x .M unit can perform one 16 × 16 bit complex multiply with or without rounding capabilities, two 16 × 16 bit complex multiplies with rounding capability, and a 32 × 32 bit complex multiply with rounding capability. The C66x can also perform two 16

× 16 bit and one 32 × 32 bit complex multiply instructions that multiply a complex number with a complex conjugate of another number with rounding capability. Communication signal processing also requires an extensive use of matrix operations. Each C66x .M unit is capable of multiplying a [1 × 2] complex vector by a [2 × 2] complex matrix per cycle with or without rounding capability. A version also exists allowing multiplication of the conjugate of a [1 × 2] vector with a [2 × 2] complex matrix.

Each C66x .M unit also includes IEEE floating-point multiplication operations from the C674x DSP, which includes one single-precision multiply each cycle and one double-precision multiply every 4 cycles. There is also a mixed-precision multiply that allows multiplication of a single-precision value by a doubleprecision value and an operation allowing multiplication of two single-precision numbers resulting in a double-precision number. The C66x DSP improves the performance over the C674x double-precision multiplies by adding a instruction allowing one double-precision multiply per cycle and also reduces the number of delay slots from 10 down to 4. Each C66x .M unit can also perform one the following floatingpoint operations each clock cycle: one, two, or four single-precision multiplies or a complex singleprecision multiply.

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The .L and .S units can now support up to 64-bit operands. This allows for new versions of many of the arithmetic, logical, and data packing instructions to allow for more parallel operations per cycle. Additional instructions were added yielding performance enhancements of the floating point addition and subtraction instructions, including the ability to perform one double precision addition or subtraction per cycle.

Conversion to/from integer and single-precision values can now be done on both .L and .S units on the

C66x. Also, by taking advantage of the larger operands, instructions were also added to double the number of these conversions that can be done. The .L unit also has additional instructions for logical AND and OR instructions, as well as, 90 degree or 270 degree rotation of complex numbers (up to two per cycle). Instructions have also been added that allow for the computing the conjugate of a complex number.

The MFENCE instruction is a new instruction introduced on the C66x DSP. This instruction will create a

DSP stall until the completion of all the DSP-triggered memory transactions, including:

• Cache line fills

• Writes from L1D to L2 or from the CorePac to MSMC and/or other system endpoints

• Victim write backs

• Block or global coherence operations

• Cache mode changes

• Outstanding XMC prefetch requests

This is useful as a simple mechanism for programs to wait for these requests to reach their endpoint. It also provides ordering guarantees for writes arriving at a single endpoint via multiple paths, multiprocessor algorithms that depend on ordering, and manual coherence operations.

For more details on the C66x DSP and its enhancements over the C64x+ and C674x architectures, see the following documents:

C66x CPU and Instruction Set Reference Guide ( SPRUGH7 ).

C66x DSP Cache User's Guide ( SPRUGY8 ).

C66x CorePac User's Guide ( SPRUGW0 ).

Figure 3-1

shows the DSP core functional units and data paths.

8

Device Overview

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TMS320C6654

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Note

:

Default bus width is64 bits

(i.e. a register pair)

Data Path A

Data Path B

ST1

LD1

DA1

32

DA2

32

LD2

ST2

.L1

.S1

.M1

.D1

.D2

src1 src2 dst

Register

File A

(A0, A1, A2,

...A31) src1 src2 dst src1 src1_hi src2 src2_hi dst2 dst1 src1 dst src2

32

32

32

32 src2 dst src1

32

32

32

32

32

2

1

Register

File B

(B0, B1, B2,

...B31)

.M2

dst1 dst2 src2_hi src2 src1_hi src1

.S2

.L2

dst src2 src1 dst src2 src1

32

32

Control

Register

Figure 3-1. DSP Core Data Paths

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TMS320C6654

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3.3

Memory Map Summary

Table 3-2

shows the memory map address ranges of the C6654 device.

Table 3-2. Memory Map Summary

01D58000

01D58080

021B4000

021B4800

021B6000

021B6800

021B8000

021B8800

021BA000

021BA800

021C0000

01D30000

01D30080

01D38000

01D38080

01D40000

01D40080

01D48000

01D48080

01D50000

01D50080

01D08000

01D08080

01D10000

01D10080

01D18000

01D18080

01D20000

01D20080

01D28000

01D28080

LOGICAL 32-BIT ADDRESS

START END

00000000

00800000

00900000

00E00000

007FFFFF

008FFFFF

00DFFFFF

00E07FFF

00E08000

00F00000

00F08000

01800000

01C00000

01D00000

01D00080

00EFFFFF

00F07FFF

017FFFFF

01BFFFFF

01CFFFFF

01D0007F

01D07FFF

01D0807F

01D0FFFF

01D1007F

01D17FFF

01D1807F

01D1FFFF

01D2007F

01D27FFF

01D2807F

01D2FFFF

01D3007F

01D37FFF

01D3807F

01D3FFFF

01D4007F

01D47FFF

01D4807F

01D4FFFF

01D5007F

01D57FFF

01D5807F

021B3FFF

021B47FF

021B5FFF

021B67FF

021B7FFF

021B87FF

021B9FFF

021BA7FF

021BFFFF

021C03FF

PHYSICAL 36-BIT

ADDRESS

START

0 00000000

0 00800000

0 00F00000

END

0 007FFFFF

0 008FFFFF

0 00F07FFF

BYTES

8M

1M

0 00900000 0 00DFFFFF 5M

0 00E00000 0 00E07FFF 32K

0 00E08000 0 00EFFFFF 1M-32K

32K

0 00F08000 0 017FFFFF 9M-32K

0 01800000 0 01BFFFFF 4M

0 01C00000 0 01CFFFFF 1M

0 01D00000 0 01D0007F 128

0 01D00080 0 01D07FFF 32K-128

0 01D08000

0 01D08080 0 01D0FFFF 32K-128

0 01D10000 0 01D1007F 128

0 01D10080

0 01D18000

0 01D30000

0 01D38080

0 01D40000

0 01D0807F

0 01D17FFF

0 01D1807F

0 01D3007F

0 01D3FFFF

0 01D4007F

128

32K-128

128

0 01D18080 0 01D1FFFF 32K-128

0 01D20000 0 01D2007F 128

0 01D20080 0 01D27FFF 32K-128

0 01D28000 0 01D2807F 128

0 01D28080 0 01D2FFFF 32K-128

128

0 01D30080 0 01D37FFF 32K-128

0 01D38000 0 01D3807F 128

32K-128

128

0 01D40080 0 01D47FFF 32K-128

0 01D48000 0 01D4807F 128

0 01D48080 0 01D4FFFF 32K-128

0 01D50000 0 01D5007F 128

0 01D50080 0 01D57FFF 32K-128

DESCRIPTION

Reserved

Local L2 SRAM

Reserved

Local L1P SRAM

Reserved

Local L1D SRAM

Reserved

C66x CorePac Registers

Reserved

Tracer_MSMC_0 (Reserved)

Reserved

Tracer_MSMC_1 (Reserved)

Reserved

Tracer_MSMC_2 (Reserved)

Reserved

Tracer_MSMC_3 (Reserved)

Reserved

Tracer_QM_DMA

Reserved

Tracer_DDR

Reserved

Tracer_SM

Reserved

Tracer_QM_CFG

Reserved

Tracer_CFG

Reserved

Tracer_L2_0

Reserved

Reserved

Reserved

0 01D58000 0 01D5807F 128 Tracer_TNet_6P_A

0 01D58080 0 021B3FFF 4464K -128 Reserved

0 021B4000 0 021B47FF 2K McBSP0 Registers

0 021B4800 0 021B5FFF 6K

0 021B6000 0 021B67FF 2K

Reserved

McBSP0 FIFO Registers

0 021B6800 0 021B7FFF 6K

0 021B8000 0 021B87FF 2K

0 021B8800 0 021B9FFF 6K

0 021BA000 0 021BA7FF 2K

0 021BA800 0 021BFFFF 22K

0 021C0000 0 021C03FF 1K

Reserved

McBSP1 Registers

Reserved

McBSP1 FIFO Registers

Reserved

Reserved

10

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SPRS841B – MARCH 2012 – REVISED APRIL 2015

Table 3-2. Memory Map Summary (continued)

02350000

02351000

02360000

02360400

02368000

02368400

02370000

02370400

02378000

02378400

02260000

02260080

02270000

02270080

02310000

02310200

02320000

02320100

02330000

02330400

LOGICAL 32-BIT ADDRESS

START END

021C0400

021D0000

021CFFFF

021D00FF

021D0100

021D4000

021D4100

02200000

02200080

021D3FFF

021D40FF

021FFFFF

0220007F

0220FFFF

02210000

02210080

02220000

02220080

02230000

02230080

02240000

02240080

02250000

02250080

0221007F

0221FFFF

0222007F

0222FFFF

0223007F

0223FFFF

0224007F

0224FFFF

0225007F

0225FFFF

02380000

02380400

02440000

02444000

02450000

02454000

02522000

02523000

02530000

023803FF

023FFFFF

02443FFF

0244FFFF

02453FFF

02521FFF

02522FFF

0252FFFF

0253007F

02350FFF

0235FFFF

023603FF

02367FFF

023683FF

0236FFFF

023703FF

02377FFF

023783FF

0237FFFF

0226007F

0226FFFF

0227007F

0230FFFF

023101FF

0231FFFF

023200FF

0232FFFF

023303FF

0234FFFF

PHYSICAL 36-BIT

ADDRESS

START END BYTES

0 021C0400 0 021CFFFF 63K

0 021D0000 0 021D00FF 256

0 021D0100 0 021D3FFF 16K - 256

0 021D4000 0 021D40FF 256

0 021D4100 0 021FFFFF 176K - 256

0 02200000 0 0220007F 128

0 02200080 0 0220FFFF 64K-128

0 02210000 0 0221007F 128

0 02210080 0 0221FFFF 64K-128

0 02220000 0 0222007F 128

0 02220080 0 0222FFFF 64K-128

0 02230000 0 0223007F 128

0 02230080 0 0223FFFF 64K-128

0 02240000 0 0224007F 128

0 02240080 0 0224FFFF 64K-128

0 02250000 0 0225007F 128

0 02250080 0 0225FFFF 64K-128

0 02260000 0 0226007F 128

0 02260080 0 0226FFFF 64K-128

0 02270000 0 0227007F 128

0 02270080 0 0230FFFF 640K - 128

0 02310000 0 023101FF 512

0 02310200 0 0231FFFF 64K-512

0 02320000 0 023200FF 256

0 02320100 0 0232FFFF 64K-256

0 02330000 0 023303FF 1K

0 02330400 0 0234FFFF 127K

0 02350000 0 02350FFF 4K

0 02351000 0 0235FFFF 64K-4K

0 02360000 0 023603FF 1K

0 02360400 0 02367FFF 31K

0 02368000 0 023683FF 1K

0 02368400 0 0236FFFF 31K

0 02370000 0 023703FF 1K

0 02370400 0 02377FFF 31K

0 02378000 0 023783FF 1K

0 02378400 0 0237FFFF 31K

0 02380000 0 023803FF 1K

0 02380400 0 023FFFFF 511K

0 02440000 0 02443FFF 16K

0 02444000 0 0244FFFF 48K

0 02450000 0 02453FFF 16K

0 02454000 0 02521FFF 824K

0 02522000 0 02522FFF 4K

0 02523000 0 0252FFFF 52K

0 02530000 0 0253007F 128

DESCRIPTION

Reserved

Reserved

Reserved

Reserved

Reserved

Timer0

Reserved

Reserved

Reserved

Timer2

Reserved

Timer3

Reserved

Timer4

Reserved

Timer5

Reserved

Timer6

Reserved

Timer7

Reserved

PLL Controller

Reserved

GPIO

Reserved

SmartReflex

Reserved

Power Sleep Controller (PSC)

Reserved

Memory Protection Unit (MPU) 0

Reserved

Memory Protection Unit (MPU) 1

Reserved

Memory Protection Unit (MPU) 2

Reserved

Memory Protection Unit (MPU) 3

Reserved

Memory Protection Unit (MPU) 4

Reserved

DSP trace formatter 0

Reserved

Reserved

Reserved

Efuse

Reserved

I

2

C data & control

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Table 3-2. Memory Map Summary (continued)

027D0000

027D1000

027E0000

027E1000

02850000

02858000

02900000

02921000

02A00000

02B00000

02740000

02748000

02790000

02790400

02798000

02798400

027A0000

027A0400

027A8000

027A8400

LOGICAL 32-BIT ADDRESS

START END

02530080

02540000

0253FFFF

0254003F

02540400

02550000

02550040

02580000

02581000

0254FFFF

0255003F

0257FFFF

02580FFF

025FFFFF

02600000

02602000

02604000

02606000

02608000

0260A000

02620000

02620800

02640000

02640800

02601FFF

02603FFF

02605FFF

02607FFF

02609FFF

0261FFFF

026207FF

0263FFFF

026407FF

0273FFFF

02C08000

02C0C000

08000000

08010000

0BC00000

0BD00000

0C000000

0C200000

10800000

02C8BFFF

07FFFFFF

0800FFFF

0BBFFFFF

0BCFFFFF

0BFFFFFF

0C0FFFFF

107FFFFF

108FFFFF

02747FFF

0278FFFF

027903FF

02797FFF

027983FF

0279FFFF

027A03FF

027A7FFF

027A83FF

027CFFFF

027D0FFF

027DFFFF

027E0FFF

0284FFFF

02857FFF

028FFFFF

02920FFF

029FFFFF

02AFFFFF

02C07FFF

PHYSICAL 36-BIT

ADDRESS

START END BYTES

0 02530080 0 0253FFFF 64K-128

0 02540000 0 0254003F 64

0 02540400 0 0254FFFF 64K-64

0 02550000 0 0255003F 64

0 02550040 0 0257FFFF 192K-64

0 02580000 0 02580FFF 4K

0 02581000 0 025FFFFF 508K

0 02600000 0 02601FFF 8K

0 02602000 0 02603FFF 8K

0 02604000 0 02605FFF 8K

0 02606000 0 02607FFF 8K

0 02608000 0 02609FFF 8K

0 0260A000 0 0261FFFF 88K

0 02620000 0 026207FF 2K

0 02620800 0 0263FFFF 126K

0 02640000 0 026407FF 2K

0 02640800 0 0273FFFF 1022K

0 02740000 0 02747FFF 32K

0 02748000 0 0278FFFF 288K

0 02790000 0 027903FF 1K

0 02790400 0 02797FFF 31K

0 02798000 0 027983FF 1K

0 02798400 0 0279FFFF 31K

0 027A0000 0 027A03FF 1K

0 027A0400 0 027A7FFF 31K

0 027A8000 0 027A83FF 1K

0 027A8400 0 027CFFFF 159K

0 027D0000 0 027D0FFF 4K

0 027D1000 0 027DFFFF 60K

0 027E0000 0 027E0FFF 4K

0 027E1000 0 0284FFFF 444K

0 02850000 0 02857FFF 32K

0 02858000 0 028FFFFF 672K

0 02900000 0 02920FFF 132K

0 02921000 0 029FFFFF 1M-132K

0 02A00000 0 02AFFFFF 1M

0 02B00000 0 02C07FFF 1056K

0 02C08000 0 02C8BFFF 16K

0 02C0C000 0 07FFFFFF 84M - 48K

0 08000000 0 0800FFFF 64K

0 08010000 0 0BBFFFFF 60M-64K

0 0BC00000 0 0BCFFFFF 1M

0 0BD00000 0 0BFFFFFF 3M

0 0C000000 0 0C0FFFFF 1M

0 0C100000 0 107FFFFF 71 M

0 10800000 0 108FFFFF 1M

DESCRIPTION

Reserved

UART 0

Reserved

UART 1

Reserved uPP

Reserved

Chip Interrupt Controller (CIC) 0

Reserved

Chip Interrupt Controller (CIC) 1

Reserved

Reserved

Reserved

Chip-Level Registers

Reserved

Semaphore

Reserved

EDMA Channel Controller (EDMA3CC)

Reserved

EDMA3CC Transfer Controller EDMA3TC0

Reserved

EDMA3CC Transfer Controller EDMA3TC1

Reserved

EDMA3CC Transfer Controller EDMA3TC2

Reserved

EDMA3CC Transfer Controller EDMA3TC3

Reserved

TI embedded trace buffer (TETB) - CorePac0

Reserved

Reserved

Reserved

TI embedded trace buffer (TETB) — system

Reserved

Reserved

Reserved

Queue manager subsystem configuration

Reserved

EMAC subsystem configuration

Reserved

Extended memory controller (XMC) configuration

Reserved

Multicore shared memory controller (MSMC) config

Reserved

Reserved

Reserved

CorePac0 L2 SRAM

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Table 3-2. Memory Map Summary (continued)

22000000

22000100

22400000

22400100

22A00000

22A01000

22B00000

22B01000

34000000

34200000

40000000

50000000

60000000

20BF0000

20BF0400

20C00000

20C00100

21000000

21000200

21400000

21400100

21800000

21808000

LOGICAL 32-BIT ADDRESS

START END

10900000

10E00000

10DFFFFF

10E07FFF

10E08000

10F00000

10F08000

11800000

11900000

10EFFFFF

10F07FFF

117FFFFF

118FFFFF

11DFFFFF

11E00000

11E08000

11F00000

11F08000

20000000

20100000

20800000

20900000

20B00000

20B20000

11E07FFF

11EFFFFF

11F07FFF

1FFFFFFF

200FFFFF

207FFFFF

208FFFFF

20AFFFFF

20B1FFFF

20BEFFFF

20BF01FF

20BFFFFF

20C000FF

20FFFFFF

210001FF

213FFFFF

214000FF

217FFFFF

21807FFF

33FFFFFF

22000FFF

223FFFFF

22400FFF

229FFFFF

22A0FFFF

22AFFFFF

22B0FFFF

33FFFFFF

341FFFFF

3FFFFFFF

4FFFFFFF

5FFFFFFF

6FFFFFFF

PHYSICAL 36-BIT

ADDRESS

START END BYTES

0 10900000 0 10DFFFFF 5M

0 10E00000 0 10E07FFF 32K

0 10E08000 0 10EFFFFF 1M-32K

0 10F00000 0 10F07FFF 32K

0 10F08000 0 117FFFFF 9M-32K

0 11800000 0 118FFFFF 1M

0 11900000 0 11DFFFFF 5M

0 11E00000 0 11E07FFF 32K

0 11E08000 0 11EFFFFF 1M-32K

0 11F00000 0 11F07FFF 32K

0 11F08000 0 1FFFFFFF 225M-32K

0 20000000 0 200FFFFF 1M

0 20100000 0 207FFFFF 7M

0 20080000 0 208FFFFF 1M

0 20900000 0 20AFFFFF 2M

0 20B00000 0 20B1FFFF 128K

0 20B20000 0 20BEFFFF 832K

0 20BF0000 0 20BF01FF 512

0 20BF0200 0 20BFFFFF 64K -512

0 20C00000 0 20C000FF 256

0 20C00100 0 20FFFFFF 4M - 256

1 00000000 1 000001FF 512

0 21000200 0 213FFFFF 4M-512

0 21400000 0 214000FF 256

0 21400100 0 217FFFFF 4M-256

0 21800000 0 21807FFF 32K

0 21808000 0 33FFFFFF 8M-32K

0 22000000 0 22000FFF 4K

0 22000100 0 223FFFFF 4M-4K

0 22400000 0 22400FFF 4K

0 22400100 0 229FFFFF 6M-4K

0 22A00000 0 22A0FFFF 64K

0 22A01000 0 22AFFFFF 1M-64K

0 22B00000 0 22B0FFFF 64K

0 22B01000 0 33FFFFFF 277M-64K

0 34000000 0 341FFFFF 2M

0 34200000 0 3FFFFFFF 190M

0 40000000 0 4FFFFFFF 256M

0 50000000 0 5FFFFFFF 256M

0 60000000 0 6FFFFFFF 256M

DESCRIPTION

Reserved

CorePac0 L1P SRAM

Reserved

CorePac0 L1D SRAM

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

System trace manager (STM) configuration

Reserved

Reserved

Reserved

Boot ROM

Reserved

SPI

Reserved

EMIF16 configuration

Reserved

DDR3 EMIF configuration

Reserved

Reserved

Reserved

PCIe config

Reserved

McBSP0 FIFO Data

Reserved

McBSP1 FIFO Data

Reserved

Reserved

Reserved

Reserved

Reserved

Queue manager subsystem data

Reserved

Reserved

Reserved

PCIe data

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Table 3-2. Memory Map Summary (continued)

LOGICAL 32-BIT ADDRESS

START

70000000

74000000

78000000

7C000000

END

73FFFFFF

77FFFFFF

7BFFFFFF

7FFFFFFF

PHYSICAL 36-BIT

ADDRESS

START END BYTES

0 70000000 0 73FFFFFF 64M

0 74000000

0 78000000

0 7C000000

0 77FFFFFF

0 7BFFFFFF

0 7FFFFFFF

64M

64M

64M

DESCRIPTION

EMIF16 CE0 data space, supports NAND, NOR, or SRAM memory

(1)

EMIF16 CE1 data space, supports NAND, NOR, or SRAM memory

(1)

EMIF16 CE2 data space, supports NAND, NOR, or SRAM memory

(1)

EMIF16 CE3 data space, supports NAND, NOR or SRAM memory

(1)

DDR3 EMIF data

(2)

80000000 FFFFFFFF 8 00000000 8 7FFFFFFF 2G

(1) 32MB per chip select for 16-bit NOR and SRAM. 16MB per chip select for 8-bit NOR and SRAM. The 32MB and 16MB size restrictions do not apply to NAND.

(2) The memory map only shows the default MPAX configuration of DDR3 memory space. For the extended DDR3 memory space access

(up to 8GB), please refer to the MPAX configuration details in C66x CorePac User's Guide and Multicore Shared Memory Controller

(MSMC) for KeyStone Devices User's Guide in

Section 3.11

.

3.4

Boot Sequence

The boot sequence is a process by which the DSP's internal memory is loaded with program and data sections. The DSP's internal registers are programmed with predetermined values. The boot sequence is started automatically after each power-on reset, warm reset, and system reset. A local reset to an individual C66x CorePac should not affect the state of the hardware boot controller on the device. For more details on the initiators of the resets, see

Section 8.4

. The bootloader uses a section of the L2

SRAM (start address 0x008EFD00 and end address 0x008F FFFF) during initial booting of the device. For more details on the type of configurations stored in this reserved L2 section see the Bootloader for the

C66x DSP User's Guide ( SPRUGY5 ).

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3.5

Boot Modes Supported and PLL Settings

The device supports several boot processes, which leverage the internal boot ROM. Most boot processes are software driven, using the BOOTMODE[2:0] device configuration inputs to determine the software configuration that must be completed. From a hardware perspective, there are two possible boot modes:

ROM Boot - C66x CorePac0 is released from reset and begins executing from the L3 ROM base address. After performing the boot process (e.g., from I

2

C ROM, Ethernet, or RapidIO), C66x

CorePac0 then begins execution from the provided boot entry point. See the Bootloader for the C66x

DSP User's Guide ( SPRUGY5 ) for more details.

The boot process performed by the C66x CorePac0 in ROM boot is determined by the BOOTMODE[12:0] value in the DEVSTAT register. The C66x CorePac0 reads this value, and then executes the associated boot process in software.

Figure 3-2

shows the bits associated with BOOTMODE[12:0].

12 11 10

PLL Mult I

2

C /SPI Ext Dev Cfg

9 8

Figure 3-2. Boot Mode Pin Decoding

7 6

Device Configuration

5 4 3 2 1

Boot Device

0

3.5.1

Boot Device Field

The Boot Device field BOOTMODE[2:0] defines the boot device that is chosen.

Table 3-3

shows the supported boot modes.

Bit

2-0

Field

Boot Device

Table 3-3. Boot Mode Pins: Boot Device Values

Description

Device boot mode

• 0 = EMIF16 / UART / No Boot

• 1 = Reserved

• 2 = Ethernet (SGMII)

• 3 = NAND

• 4 = PCIe

• 5 = I

2

C

• 6 = SPI

• 7 = Reserved

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3.5.2

Device Configuration Field

The device configuration fields BOOTMODE[9:3] are used to configure the boot peripheral and, therefore, the bit definitions depend on the boot mode.

3.5.2.1

EMIF16 / UART / No Boot Device Configuration

9

Figure 3-3. EMIF16 / UART / No Boot Configuration Fields

8 7

Sub-Mode Specific Configuration

6 5 4

Sub-Mode

3

Bit

9-6

5-3

Field

Sub-Mode

Specific

Configuration

Sub-Mode

Table 3-4. EMIF16 / UART / No Boot Configuration Field Descriptions

Description

Configures the selected sub-mode. See

Section 3.5.2.1.1

,

Section 3.5.2.1.2

, and

Section 3.5.2.1.3

Sub mode selection.

• 0 = No boot

• 1 = UART port 0 boot

• 2 - 3 = Reserved

• 4 = EMIF16 boot

• 5 = UART port 1 boot

• 6 - 7 = Reserved

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3.5.2.1.1 No Boot Mode

9

Bit

9-6

Field

Reserved

Figure 3-4. No Boot Configuration Fields

8 7

Reserved

Description

• Reserved

Table 3-5. No Boot Configuration Field Descriptions

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SPRS841B – MARCH 2012 – REVISED APRIL 2015

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3.5.2.1.2 UART Boot Mode

9

Speed

Figure 3-5. UART Boot Configuration Fields

8 7

Parity

Bit

9-8

Field

Speed

7-6 Parity

Table 3-6. UART Boot Configuration Field Descriptions

Description

UART interface speed.

• 0 = 115200 baud

• 1 = 38400 baud

• 2 = 19200 baud

• 3 = 9600 baud

UART parity used during boot.

• 0 = None

• 1 = Odd

• 2 = Even

• 4 = None

6

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3.5.2.1.3 EMIF16 Boot Mode

9

Wait Enable

Figure 3-6. EMIF16 Boot Configuration Fields

8

Width Select

7

Chip Select

Bit

9

8

7-6

Field

Wait Enable

Width Select

Chip Select

Table 3-7. EMIF16 Boot Configuration Field Descriptions

Description

Extended Wait mode for EMIF16.

• 0 = Wait enable disabled (EMIF16 sub mode)

• 1 = Wait enable enabled (EMIF16 sub mode)

EMIF data width for EMIF16.

• 0 = 8-bit wide EMIF (EMIF16 sub mode)

• 1 = 16-bit wide EMIF (EMIF16 sub mode)

EMIF Chip Select used during EMIF 16 boot.

• 0 = CS2

• 1 = CS3

• 2 = CS4

• 4 = CS5

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3.5.2.2

Ethernet (SGMII) Boot Device Configuration

9

SerDes Clock Mult

8

Figure 3-7. Ethernet (SGMII) Device Configuration Fields

7

Ext connection

6 5 4

Device ID

Bit

9-8

7-6

5-3

Table 3-8. Ethernet (SGMII) Configuration Field Descriptions

Field Description

SerDes Clock Mult SGMII SerDes input clock. The output frequency of the PLL must be 1.25 GBs.

• 0 = ×8 for input clock of 156.25 MHz

• 1 = ×5 for input clock of 250 MHz

• 2 = ×4 for input clock of 312.5 MHz

• 3 = Reserved

Ext connection

Device ID

External connection mode

• 0 = MAC to MAC connection, master with auto negotiation

• 1 = MAC to MAC connection, slave, and MAC to PHY

• 2 = MAC to MAC, forced link

• 3 = MAC to fiber connection

This value can range from 0 to 7 is used in the device ID field of the Ethernet-ready frame.

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3.5.2.3

NAND Boot Device Configuration

9 8

Figure 3-8. NAND Device Configuration Fields

7

1 st

Block

6 5 4

I

2

C

3

Reserved

Bit

9-5

Field

1 st

Block

4

3

I

2

C

Reserved

Table 3-9. NAND Configuration Field Descriptions

Description

NAND Block to be read first by the boot ROM.

• 0 = Block 0

• ...

• 31 = Block 31

NAND parameters read from I

2

C EEPROM

• 0 = Parameters are not read from I

2

C

• 1 = Parameters are read from I

2

C

Reserved

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3.5.2.4

PCI Boot Device Configuration

Extra device configuration is provided in the PCI bits in the DEVSTAT register.

9

Ref Clock

8

Figure 3-9. PCI Device Configuration Fields

7 6 5

BAR Config

4

Reserved

3

Bit

9

8-5

4-3

BAR CFG

0b0000

0b0001

0b0010

0b0011

0b0100

0b0101

0b0110

0b0111

0b1000

0b1001

0b1010

0b1011

0b1100

0b1101

0b1110

0b1111

Field

Ref Clock

BAR Config

Reserved

BAR0

PCIe MMRs

32

16

16

32

32

4

4

64

4

BAR1

32

16

16

Table 3-10. PCI Device Configuration Field Descriptions

Description

PCIe reference clock configuration

• 0 = 100 MHz

• 1 = 250 MHz

PCIe BAR registers configuration

This value can range from 0 to 0xf. See

Table 3-11

.

Reserved

Table 3-11. BAR Config / PCIe Window Sizes

BAR5

64-BIT ADDRESS

TRANSLATION

BAR2/3 BAR4/5

32

32

32

64

128

128

128

32-BIT ADDRESS TRANSLATION

BAR2 BAR3 BAR4

32

16

32

32

16

32

32

32

32

64

32

64

64

64

64

64

64

64

128

128

128

256

64

64

128

256

128

256

256

Clone of

BAR4

256

512

1024

2048

256

512

1024

2048

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3.5.2.5

I

2

C Boot Device Configuration

3.5.2.5.1 I

2

C Master Mode

In master mode, the I

2

C device configuration uses ten bits of device configuration instead of seven as used in other boot modes. In this mode, the device will make the initial read of the I

2

C EEPROM while the

PLL is in bypass mode. The initial read will contain the desired clock multiplier, which will be set up prior to any subsequent reads.

12

Mode

11

Address

Figure 3-10. I

2

C Master Mode Device Configuration Bit Fields

10 9

Speed

8 7 6 5

Parameter Index

4 3

Bit

12

Field

Mode

11 - 10 Address

9

8-3

Speed

Parameter Index

Table 3-12. I

2

C Master Mode Device Configuration Field Descriptions

Description

I

2

C operation mode

• 0 = Master mode

• 1 = Passive mode (see

Section 3.5.2.5.2

)

I

2

C bus address configuration

• 0 = Boot from I

2

C EEPROM at I

2

C bus address 0x50

• 1 = Boot from I

2

C EEPROM at I

2

C bus address 0x51

• 2= Boot from I

2

C EEPROM at I

2

C bus address 0x52

• 3= Boot from I

2

C EEPROM at I

2

C bus address 0x53

I

2

C data rate configuration

• 0 = I

2

C slow mode. Initial data rate is SYSCLK / 5000 until PLLs and clocks are programmed

• 1 = I

2

C fast mode. Initial data rate is SYSCLK / 250 until PLLs and clocks are programmed

Identifies the index of the configuration table initially read from the I2C EEPROM

This value can range from 0 to 31.

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3.5.2.5.2 I

2

C Passive Mode

In passive mode, the device does not drive the clock, but simply acks data received on the specified address.

12

Mode

11

Figure 3-11. I

2

C Passive Mode Device Configuration Bit Fields

10 9 8

Address

7 6 5 4

Reserved

3

Bit

12

Field

Mode

11 - 5 Address

4 - 3 Reserved

Table 3-13. I

2

C Passive Mode Device Configuration Field Descriptions

Description

I

2

C operation mode

• 0 = Master mode (see

Section 3.5.2.5.1

)

• 1 = Passive mode

I

2

C bus address accepted during boot. Value may range from 0x00 to 0x7F

Reserved

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3.5.2.6

SPI Boot Device Configuration

In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as used in other boot modes.

12

Mode

11 10

4, 5 Pin

Figure 3-12. SPI Device Configuration Bit Fields

9

Addr Width

8

Chip Select

7 6 5 4

Parameter Table Index

3

Bit Field

12-11 Mode

10

9

8-7

6-3

4, 5 Pin

Addr Width

Chip Select

Parameter Table

Index

Table 3-14. SPI Device Configuration Field Descriptions

Description

Clk Pol / Phase

• 0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.

• 1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling edges. Input data is latched on the rising edge of SPICLK.

• 2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.

• 3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising edges. Input data is latched on the falling edge of SPICLK.

SPI operation mode configuration

• 0 = 4-pin mode used

• 1 = 5-pin mode used

SPI address width configuration

• 0 = 16-bit address values are used

• 1 = 24-bit address values are used

The chip select field value

Specifies which parameter table is loaded

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3.5.3

Boot Parameter Table

The ROM Bootloader (RBL) is guided by the boot parameter table to carry out the boot process. The boot parameter table is the most common format the RBL employs to determine the boot flow. These boot parameter tables have certain parameters common across all the boot modes, while the rest of the parameters are unique to the boot modes. The common entries in boot parameter table is are shown in table below.

Byte Offset

0

2

4

6

8

10

Table 3-15. Boot Parameter Table Common Values

Name

Length

Checksum

Boot Mode

Port Num

PLL config, MSW

PLL config, LSW

Description

The length of this table, including this length field, in bytes.

Identifies the device port number to boot from, if applicable. The value 0xFFFF indicates that all ports are configured (Ethernet, SRIO).

See

Table 3-16

Identifies the device port number to boot from, if applicable. The value 0xFFFF indicates that all ports are configured (Ethernet, SRIO).

PLL configuration, MSW (see

Figure 5-6

)

PLL configuration, LSW

Value

10

20

30

40

41

42

50

60

70

80

81

100

110

Table 3-16. Boot Parameter Table Boot Mode Field

Boot Mode

Ethernet (boot table)

Rapid I/O

PCIe

I2C Master

I2C Slave

I2C Master Write

SPI

Hyperlink

EMIF25

NAND

NAND I2C

SLEEP, no PLL configuration

UART

31 30

PLL Config Ctl

29

Figure 3-13. Boot Parameter Table Boot Mode Values

16 15 8

PLL Multiplier PLL Pre-Divider

7

PLL Post-Divider

0

Field Value

PLL Config Ctl 0b00

0b01

0b10

Pre-divider

Multiplier

Post-divider

0b11

0-255

0-16383

0-255

Table 3-17. PLL Configuration Field Description

Description

PLL is not configured

PLL is configured only if it is currently disabled or in bypass

PLL is configured only if it is currently disabled or in bypass

PLL is disabled and put into bypass

Input clock division. The value 0 is treated as pre-divide by 1

Multiplier. The value 0 is treated as multiply by 1

PLL output division. The value 0 is treated as post divide by 1

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3.5.3.1

Sleep / XIP Mode Parameter Table

The sleep mode parameter table has no fields in addition to the common fields described in

Section 3.5.3

.

Byte Offset

12

14

16

18

20

22

24

26

28

Table 3-18. EMIF16 XIP Parameter Table Values

Descriptions Name

Options

Type

Branch Addr, MSW

Branch Addr, LSW

CsNum memWidth waitEnable

Async config, MSW

Async config, LSW

Figure 3-14

Must be set to 0 for NOR flash

Address to branch to

The chip select number, valid values are 2-5

The bit width of the memory, valid values are 8 or 16

Extended wait is enabled if this value is 1, otherwise disabled

EMIF16 async config register value, msw

EMIF16 async config register value, lsw

Figure 3-14. EMIF16 XIP Options Fields

15

Reserved

1 0 async

Field

Async

Value

0

1

Table 3-19. EMIF16 XIP Option Field Descriptions

Description

The async config register is not changed by the boot code

The async config value in the boot parameter table is programmed in the async config register (EMIF timing values)

Byte Offset

12

14

16

18

20

30

32

34

36

38

22

24

26

28

40

42

44

46

48

3.5.3.2

SRIO Mode Boot Parameter Table

Table 3-20. SRIO Mode Boot Parameter Table

Name

Options

Lane Setup

Reserved

Node ID

SERDES ref clk

Link Rate

PF Low

PF high

Promiscuous Mask

Serdes AUX, MSW

Serdes AUX, LSW

SERDES Rx Lane 0, MSW

SERDES Rx Lane 0, LSW

SERDES Rx Lane 1, MSW

SERDES Rx Lane 1, LSW

SERDES Rx Lane 2, MSW

SERDES Rx Lane 2, LSW

SERDES Rx Lane 3, MSW

SERDES Rx Lane 3, LSW

Description

See

Figure 3-15

See

Table 3-22

Reserved

The node ID value to set for this device

The SERDES reference clock frequency, in 1/100 MHZ. Used only if PLL setup field in options is set.

Link rate, MHz. Used only if PLL setup field in options is set.

Packet forward address range, low value

Packet forward address range, high value

A bit is set for each lane/port that is configured as promiscuous.

Serdes Auxillary Register Configuration, MSW

Serdes Auxillary Register Configuration, LSW

Serdes Rx Config, Lane 0, MSW

Serdes Rx Config, Lane 0, LSW

Serdes Rx Config, Lane 1, MSW

Serdes Rx Config, Lane 1, LSW

Serdes Rx Config, Lane 2, MSW

Serdes Rx Config, Lane 2, LSW

Serdes Rx Config, Lane 3, MSW

Serdes Rx Config, Lane 3, LSW

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15

Byte Offset

50

52

54

56

58

60

62

64

Table 3-20. SRIO Mode Boot Parameter Table (continued)

Name

SERDES Tx Lane 0, MSW

SERDES Tx Lane 0, LSW

SERDES Tx Lane 1, MSW

SERDES Tx Lane 1, LSW

SERDES Tx Lane 2, MSW

SERDES Tx Lane 2, LSW

SERDES Tx Lane 3, MSW

SERDES Tx Lane 3, LSW

Serdes Tx Config, Lane 0, MSW

Serdes Tx Config, Lane 0, LSW

Serdes Tx Config, Lane 1, MSW

Serdes Tx Config, Lane 1, LSW

Serdes Tx Config, Lane 2, MSW

Serdes Tx Config, Lane 2, LSW

Serdes Tx Config, Lane 3, MSW

Serdes Tx Config, Lane 3, LSW

Description

Reserved

Figure 3-15. SRIO Boot Options

5 4 3 2 1 0

PLL QM Cfg Mailbox Tx En

Setup Bypass Bypass En

Parameter

PLL Setup

QM Bypass

Cfg Bypass

Mailbox En

Tx En

Value

0

1

2

3

4

5-0xFFFF

0

1

0

0

1

1

0

1

Value

0

1

Table 3-21. SRIO Boot Options Description

Description

Serdes Configuration registers taken without modification

Multiplier and rate fields are modified based on the reference clock and link rate fields.

Configure the QM (and cpdma)

Bypass QM configuration

Configure the SRIO

Bypass SRIO configuration

Mailbox mode disabled. SRIO boot is in Master mode

Mailbox mode enabled. SRIO boot is in message mode (master boot still works)

SRIO transmit disabled

SRIO transmit enabled

Table 3-22. SRIO Lane Setup Values

Description

SRIO configured as four 1x ports

SRIO configured as 3 ports (2x, 1x, 1x)

SRIO configured as 3 ports (1x, 1x, 2x)

SRIO configured as 2 ports (2x, 2x)

SRIO configured as 1 4x port

Reserved

3.5.3.3

2.5.3.3 Ethernet Mode Boot Parameter Table

The default multi-cast Ethernet mac address is the broadcast address.

28

Byte Offset

12

14

16

18

20

Device Overview

Table 3-23. Ethernet Boot Parameter Table Values

Name

Options

MAC High

MAC Med

MAC Low

Multi MAC High

Description

See

Figure 3-16

The 16 MSBs of the MAC address to receive during boot

The 16 middle bits of the MAC address to receive during boot

The 16 LSBs of the MAC address to receive during boot

The 16 MSBs of the multi-cast MAC address to receive during boot

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15

Name

Init Config

Skip tx

15

Byte Offset

22

24

26

28

30

32

34

44

46

48

50

52

36

38

40

42

54

56

58

60

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

Table 3-23. Ethernet Boot Parameter Table Values (continued)

Name

Multi MAC Med

Mulit MAC Low

Source Port

Dest Port

Description

The 16 middle bits of the multi-cast MAC address to receive during boot

The 16 LSBs of the multi-cast MAC address to receive during boot

The source UDP port to accept boot packets from. A value of 0 will accept packets from any UDP port

The destination port to accept boot packets on.

Device ID 12

Device ID 34

Dest MAC High

Dest MAC Med

DEST MAC Low

Sgmii Config

Sgmii Control

Sgmii Adv Abilility

Sgmii Tx Cfg High

Sgmii Tx Cfg Low

Sgmii Rx Cfg High

Sgmii Rx Cfg Low

The 1st two bytes of the device ID. This is typically a string value, and is sent in the Ethernet ready frame

The 2nd two bytes of the device ID.

The 16 MSBs of the MAC destination address used for the Ethernet ready frame.

Default is broadcast.

The 16 middle bits of the MAC destination address

The 16 LSBs of the MAC destination address

See

Figure 3-17

The SGMII control register value (if table value not used)

The SGMII ADV Ability register value (if table value not used)

The 16 MSBs of the sgmii Tx config register (if table value not used)

The 16 LSBs of the sgmii Tx config register (if table value not used)

The 16 MSBs of the sgmii Rx config register (if table value not used)

The 16 LSBs of the sgmii Rx config register (if table value not used)

Sgmii Aux Cfg High

Sgmii Aux Cfg Low

The 16 MSBs of the sgmii Aux config register (if table value not used)

The 16 LSBs of the sgmii Aux config register (if table value not used)

Pkt PLL Config, MSW The packet subsystem PLL configuration, MSW (unused in gauss)

Packet PLL Config, LSW The packet subsystem PLL configuration, LSW

Figure 3-16. Ethernet Mode Boot Parameter Options Field

Reserved

7 6 5

Init Config

4

Skip

Tx

3

Reserved

0

Value

0b00

0b01

0b10

0b11

0

1

Table 3-24. Ethernet Options Field Descriptions

Description

SERDES and SGMII are configured.

SERDES and SGMII are NOT configured

Reserved

None of the Ethernet system hardware is configured.

Ethernet ready frame is sent once when the system is first ready to receive packets, and then roughly every 3 seconds until the first boot packet is accepted.

Ethernet ready frame is not sent

Reserved

Figure 3-17. SGMII Config Bit Field

6 5 4 bypass direct

3

Index

0

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Field

Index

Direct

Bypass 0

1

2

3

Value

0

1

4-15

0

1

Table 3-25. SGMII Config Field Descriptions

Description

Configure the SGMII as a master

Configure the SGMII as a slave, or connected to a Phy

Configure the SGMII as a forced link

Configure the SGMII as mac to fiber

Reserved

Configure the SGMII as directed in the index field

Configure the SGMII using the advise ability and control fields in the boot parameter table, not based on the index field

Configure the SGMII.

Do not configure the SGMII.

3.5.3.4

NAND Mode Boot Parameter Table

Byte Offset

12

14

16

18

20

22

24

26

Table 3-26. NAND Mode Boot Parameter Table

Name

Options

I2cClkFreqKhz

I2cTargetAddr

I2cLocalAddr

I2cDataAddr

I2cWtoRDelay csNum firstBlock

Decription

See

Figure 3-18

The I2C clock frequency to use when using I2C tables

The I2C bus address of the EEPROM

The I2C bus address of the Appleton device

The address on the EEPROM of the NAND configuration table

Delay between addres writes and data reads, in I2C clock periods

The NAND chip select region (0-3)

The first block of the boot image

Figure 3-18. NAND Boot Parameter Option Fields

15

Reserved

1 0

I2C

Name

I2C

Table 3-27. NAND Boot Parameter Options Bit Field Descriptions

Value

0

1

Description

NAND configuration is NOT read from I2C

NAND configuration is read from the I2C

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32

34

36

38

40

20

22

24

26

28

30

42

44

46

48

3.5.3.5

PCIE Mode Boot Parameter Table

Byte Offset

12

14

16

18

Table 3-28. PCIe Mode Boot Parameter Table

Name

options

Address Width

Serdes Frequency

Reference clock

Window 1 Size

Window 2 Size

Window 3 Size

Window 4 Size

Window 5 Size

Vendor ID

Device ID

Class code Rev Id, MSW

Class code Rev Id, LSW

Serdes cfg msw

Serdes cfg lsw

Serdes lane 0 cfg msw

Serdes lane 0 cfg lsw

Serdes lane 1 cfg msw

Serdes lane 1 cfg lsw

Description

PCI configuration options (see

Figure 3-19

)

PCI address width, can be 32 or 64

Serdes frequency, in MBs. Currently only 2500 supported.

Reference clock frequency, in units of 10kHz. Valid values are 10000 (100MHz),

12500 (125MHz), 15625 (156.25Mhz), 25000 (250MHz) and 31250 (312.5 MHz), although other values should work.

Window 1 size, in Mbytes

Window 2 size, in Mbytes

Window 3 size, in Mbytes. Valid only if address width is 32.

Window 4 Size, in Mbytes Valid only if address width is 32.

Window 5 Size. Valid only if the address width is 32.

Vendor ID field

Device ID field (0xb006 by default for Gauss)

Class code/revision ID field

Class code/revision ID field

PCIe serdes config word, MSW

PCIe serdes config word, LSW

Serdes lane config word, msw lane 0

Serdes lane config word, lsw, lane 0

Serdes lane config word, msw, lane 1

Serdes lane config word, lsw, lane 1

Figure 3-19. PCIe Options Bit Field

15

Reserved

3 2 1 0

Serdes Cfg Reserv

Cfg Disable ed

Field

Cfg disable

Serdes Cfg

1

0

1

Value

0

Table 3-29. PCIe Options Field Descriptions

Description

PCIe peripheral is configured by the boot rom

PCIe peripheral is not configured by the boot rom

Serdes PLL multiplier and rate fields in the table are used diretly

Serdes PLL multiplier and rate fields in the serdes registers will be overwritten based on the values in the serdes frequency and reference clock parameters.

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3.5.3.6

I2C Mode Boot Parameter Table

Byte Offset

12

14

16

18

20

22

24

26

28

30

Table 3-30. I2C Mode Boot Parameter Table

Name

Options

Boot Dev Addr

Boot Dev Addr Ext

Broadcast Addr

Local Address

Device Freq

Bus Frequency

Next Dev Addr

Next Dev Addr Ext

Address Delay

Description

See

Figure 3-20

The I2C device address to boot from

Extended boot device address, or I2C bus address (typically 0x50, 0x51)

In master broadcast boot, this is the I2C address to send the boot data to

The I2C address of this device.

The operating frequency of the device (MHz). Used to compute the divide down to the I2C module

The desired I2C data rate (kHz).

The next device to boot from (used in boot config mode)

The extended next boot device address

The number of CPU cycles to delay between writing the address to an I2C eeprom and reading data. This allows the I2C eeprom time to load the data.

Figure 3-20. I2C Mode Boot Options Bitfield

15

Reserved

2 1

Mode

0

Parameter

Mode

1

2

Value

0

3

Table 3-31. Register Description

Description

Load a boot parameter table from the I2C

Load boot records from the I2C (boot tables)

Load boot config records from the I2C (boot config tables)

Perform a slave mode boot, listening on the local address specified in the table.

3.5.3.7

SPI Mode Boot Parameter Table

Byte Offset

12

14

16

18

20

22

24

26

28

30

32

34

36

38

Table 3-32. 2.5.3.7 SPI Mode Boot Parameter Table

Name

options

Address Width

NPin

Chipsel

Mode

C2T Delay

CPU Freq MHz

Bus Freq, MHz

Bus Freq, kHz

Read Addr MSW

Read Addr LSW

Next chipsel

Next read MSW

Next read LSW

Description

See

Figure 3-21

The number of bytes in the SPI device address. Can be 2 or 3 (16 or 24 bit)

The operational mode, 4 or 5 pin

The chip select used. Can be 0-3.

SPI mode, 0-3

SPI chip select active to transmit start delay value (0-255)

The speed of the CPU, in MHz

The MHz portion of the SPI bus frequency. Default = 5MHz

The kHz portion of the SPI buf frequency. Default = 0

The first address to read from, MSW (valid for 24 bit address width only)

The first address to read from, LSW

Chipsel value used after boot config table processing is complete

The next read address, MSW after config table processing is complete

The next read address, LSW after config table processing is complete

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15

The bus frequency programmed into the SPI by the boot ROM is from the table: MHz.kHz. So for a 5.1

MHz bus frequency the MHz value is 5, the kHz value is 100.

Figure 3-21. SPI Options Field Bit Map

Reserved

2 1

Mode

0

Parameter

Mode

1

2

3

Value

0

Table 3-33. SPI Options Field Description

Description

Load a boot parameter table from the SPI

Load boot records from the SPI (boot tables)

Load boot config records from the SPI (boot config tables)

Reserved

3.5.3.8

Hyperlink Mode Boot Parameter Table

Byte Offset

12

14

16

18

20

22

24

26

28

36

38

40

42

30

32

34

Table 3-34. Hyperlink Mode Boot Parameter Table

Name

Options

N lanes

Serdes Aux, MSW

Serdes Aux, LSW

Rx Lane 0, MSW

Rx Lane 0, LSW

Tx Lane 0, MSW

Tx Lane 0, LSW

Rx Lane 1, MSW

Rx Lane 1, LSW

Tx Lane 1, MSW

Tx Lane 1, LSW

Rx Lane 2, MSW

Rx Lane 2, LSW

Tx Lane 2, MSW

Tx Lane 2, LSW

Description

See

Figure 3-22

The number of lanes to configure

SERDES Aux register config value, MSW

SERDES Aux register config value, LSW

SERDES Rx Lane 0 register value, MSW

SERDES Rx Lane 0 register value, LSW

SERDES Tx Lane 0 register value, MSW

SERDES Tx Lane 0 register value, LSW

SERDES Rx Lane 1 register value, MSW

SERDES Rx Lane 1 register value, LSW

SERDES Tx Lane 1 register value, MSW

SERDES Tx Lane 1 register value, LSW

SERDES Rx Lane 2 register value, MSW

SERDES Rx Lane 2 register value, LSW

SERDES Tx Lane 2 register value, MSW

SERDES Tx Lane 2 register value, LSW

Figure 3-22. Hyperlink Options Bit Field

15

Reserved

2

Field

nonit

Value

0

1

Table 3-35. Hyperlink Options Field Descriptions

Initialize hyperlink peripheral

Do not initialize hyperlink peripheral

Description

1 0 nonit Rsvd

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3.5.3.9

UART Mode Boot Parameter Table

Byte Offset

12

14

16

18

20

22

24

26

28

30

32

34

36

38

40

Field

Rsvd

Data Format

Protocol

Initial Ping Cnt

Max Err Count

Nack timeout

Char timeout

Data bits

Parity

Stop bits x2

Oversample

Flow Control

Data Rate, MSW

Data Rate, LSW timerRefMhz

Table 3-36. UART Mode Boot Parameter Table

Description

Reserved

Only value 1, boot table format is supported

Only value 0, XMODEM is supported

Number of initial pings without reply before the boot times out

Number of consecutive errors before the boot fails

Timeout period waiting for an ack/nack, in milli-seconds

Timeout period between characters

Number of data bits. Only the value 8 is supported

0 = none, 1 = odd, 2 = even

Number of stop bits x2, (2 = 1 stop bit, 4 = 2 stop bits)

The over-sample factor. Only 13 and 16 are valid

Only 0, no flow control is supported.

The Baud rate, MSW

The Baud rate, LSW

Timer reference frequency, in MHz. In Gauss this is the frequency the device is operating at after the PLL is programmed.

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3.6

PLL Boot Configuration Settings

The PLL default settings are determined by the BOOTMODE[12:10] bits. The following table shows settings for various input clock frequencies.

Table 3-37. C66x DSP System PLL Configuration

(1)

BOOTMODE [12:10]

0b000

0b001

0b010

0b011

0b100

0b101

0b110

0b111

INPUT CLOCK FREQ (MHz)

50.00

66.67

80.00

100.00

156.25

250.00

312.50

122.88

3

0

0

1

49

4

49

5

PLLD

33

50

84

16

543

33

271

82

850 MHz DEVICE

PLLM

850

850.04

850

850

850

850

850

849.92

(1) The PLL boot configuration table above may not include all the frequency values that the device supports.

DSP ƒ

OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]. This will set the PLL to the maximum clock setting for the device (with OUTPUT_DIVIDE=2, by default).

• CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1)))

The Main PLL is controlled using a PLL controller and a chip-level MMR. The DDR3 PLL is controlled by chip level MMRs. For details on how to set up the PLL see

Section 8.5

. For details on the operation of the

PLL controller module, see the Phase Locked Loop (PLL) for KeyStone Devices User's Guide

( SPRUGV2 ).

3.7

Second-Level Bootloaders

Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader allows for any level of customization to current boot methods as well as the definition of a completely customized boot.

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3.8

Terminals

3.8.1

Package Terminals

Figure 3-23

shows the C6654 CZH and GZH ball grid area (BGA) packages (bottom view).

AE

AD

AB

AA

Y

AC

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1 3 5 7 9 11 13 15 17 19 21 23 25

2 4

6 8 10 12

14 16

18 20

22 24

Figure 3-23. CZH/GZH 625-Pin BGA Package (Bottom View)

3.8.2

Pin Map

Figure 3-25

through

Figure 3-28

show the C6654 pin assignments in four quadrants (A, B, C, and D).

A B

D

C

Figure 3-24. Pin Map Quadrants (Bottom View)

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10 11 12 13 1 2 3 4 5 6 7 8

AE

VSS

SGMII0

RXN

SGMII0

RXP

VSS RIORXN2 RIORXP2 VSS RIORXP0 RIORXN0 VSS PCIERXP0 PCIERXN0 VSS

AD

VSS VSS VSS RIORXN3 RIORXP3 VSS RIORXP1 RIORXN1 VSS PCIERXN1 PCIERXP1 VSS

SRIOSGMII

CLKP

AC

VSS

SGMII0

TXN

SGMII0

TXP

VSS RIOTXN2 RIOTXP2 VSS RIOTXP0 RIOTXN0 VSS PCIETXP0 PCIETXN0 VSS

AB

EMIFD14 VSS RSV19 RIOTXN3 RIOTXP3 V S S RIOTXN1

RIOTXP1

VSS PCIETXP1 PCIETXN1 VSS

SPIDOUT

AA

EMIFD13 EMIFD15 VDDR3 VSS VDDR4 VSS RSV17 VSS VDDR2 VSS RSV18 SPISCS0 SPICLK

Y

EMIFD09 EMIFD11 DVDD18 RSV13 RSV12 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS DVDD18

W

EMIFD06 EMIFD08 VSS EMIFD10 EMIFD12 DVDD18 VSS VDDT2 VSS VDDT2 VSS VDDT2 VSS

V

EMIFD02 EMIFD03 EMIFD04 EMIFD05 EMIFD07 VSS DVDD18 VSS CVDD VSS CVDD VSS CVDD

U

EMIFA21 EMIFA22 EMIFA23 EMIFD00 EMIFD01 DVDD18 VSS CVDD1 VSS CVDD VSS CVDD VSS

T

EMIFA19 VSS DVDD18 EMIFA18 EMIFA20 VSS DVDD18 VSS CVDD1 VSS CVDD VSS CVDD

R

EMIFA17 EMIFA16 EMIFA14 EMIFA15 EMIFA13 DVDD18 VSS VSS VSS CVDD VSS CVDD VSS

P

EMIFA12 EMIFA11 EMIFA09 EMIFA05 EMIFA03 VSS DVDD18 VSS CVDD VSS CVDD VSS CVDD

N

EMIFA10 EMIFA08 DVDD18 VSS

EMIF

WAIT0

DVDD18 VSS CVDD VSS CVDD VSS CVDD VSS

A

Figure 3-25. Upper Left Quadrant — A (Bottom View)

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TMS320C6654

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14 15 16 17 18

SRIOSGMII

CLKN

PCIECLKN UARTCTS1 TDI

19 20 21 22 23 24 25

TMS CORECLKN TIMO1 TIMI1 DX1 FSX1 CLKX1 VSS

AE www.ti.com

PCIECLKP UARTRTS1 VSS TCK CORECLKP TDO TIMI0 DR1 FSR1 CLKR1 FSR0 EMU16

AD

UARTRXD1 UARTTXD1 DVDD18 UARTCTS RSV04 TIMO0 DVDD18 CLKS1 DX0 CLKS0 EMU17 EMU13

AC

SPIDIN UARTRXD MDIO UARTRTS RSV05

TRST

VSS DR0 EMU15 DVDD18 VSS EMU12

AB

SPISCS1 UARTTXD MDCLK SCL SDA

SYSCLK

OUT

FSX0 CLKR0 RSV01 EMU14 EMU10 EMU11

AA

VSS AVDDA1 VSS DVDD18

POR RSV08 CLKX0 EMU18 EMU09 EMU07 EMU06 EMU05

Y

DVDD18 VSS DVDD18 VSS DVDD18 VSS DVDD18 GPIO14 EMU08 EMU03 EMU04 EMU02

W

VSS CVDD VSS CVDD VSS DVDD18 VSS GPIO15 GPIO13 GPIO10 EMU00 EMU01

V

CVDD VSS CVDD VSS CVDD1 VSS DVDD18 GPIO11 GPIO08 GPIO09 GPIO05 GPIO03

U

VSS CVDD VSS CVDD1 VSS DVDD18 VSS GPIO12 GPIO06 GPIO04 DVDD18 GPIO00

T

CVDD VSS CVDD VSS CVDD VSS DVDD18 GPIO07 VSS GPIO02 VSS GPIO01

R

VSS CVDD VSS CVDD VSS CVDD VSS VSS MCMTXN0 VSS MCMRXN0 VSS

P

CVDD VSS CVDD VSS CVDD VSS VDDT1 MCMTXN1 MCMTXP0 VSS MCMRXP0 MCMRXP1

N

B

Figure 3-26. Upper Right Quadrant—B (Bottom View)

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TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

C

VSS CVDD VSS CVDD VSS VDDT1 VDDR1

MCM

TXP1

VSS VSS VSS MCMRXN1

M

CVDD VSS CVDD VSS CVDD VSS VDDT1 VSS MCMTXP2 VSS MCMRXP3 VSS

L

VSS CVDD VSS CVDD1 VSS VDDT1 VSS MCMTXP3 MCMTXN2 VSS MCMRXN3 MCMRXP2

K

CVDD VSS CVDD VSS CVDD1 VSS RSV16 MCMTXN3 VSS VSS VSS MCMRXN2

J

VSS CVDD VSS CVDD VSS DVDD18 VSS VSS RSV11 VSS DVDD18 VSS

H

DVDD15 VSS DVDD15 VSS DVDD15 RSV0 A RSV0B RSV15 RSV10 VCNTL3

MCMTX

PMDAT

MCMREF

CLKOUTP

G

VSS PTV15 VSS DVDD15 VSS DVDD15 AVDDA2 RSV14 RSV20 VCNTL2

MCMTX

PMCLK

MCMREF

CLKOUTN

F

DDRODT0 DDRA03 DDRA02 DDRA15 DDRA14 DDRA10 DDRA09 DVDD18 VCNTL0 VCNTL1

MCMRX

PMCLK

MCMTX

FLCLK

E

DDRCAS DVDD15 DDRA00 DDRBA1 DDRA12 DVDD15 DDRA08 VSS

DDRSL

RATE1

RSV21

MCMRX

PMDAT

MCMTX

FLDAT

D

DDRCE1 VSS DDRA06 DVDD15 DDRBA0 VSS DDRA13 DVDD15

DDRSL

RATE0

RSV09

MCMRX

FLDAT

MCMCLKP

C

DDRCLK

OUTN0

DDRCE0 DDRRESET VSS DDRA04 DDRBA2 DDRA11

DDRCLK

OUTN1

DDRCLKN RSV06

MCMRX

FLCLK

MCMCLKN

B

DDRCLK

OUTP0

DDRRAS DDRCKE0 DDRA05 DDRA07 DDRA01 DDRCKE1

DDRCLK

OUTP1

DDRCLKP RSV07 DVDD18 VSS

A

14 15 25 16 17 18 19 20 21 22 23

Figure 3-27. Lower Right Quadrant—C (Bottom View)

24

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D

M

EMIFA07 EMIFA06 EMIFA01 EMIFWAIT1 EMIFCE3 VSS DVDD18 VSS CVDD VSS CVDD VSS CVDD

L

EMIFA04 EMIFA02

EMIFBE1 EMIFOE

EMIF

RNW

DVDD18 VSS CVDD VSS CVDD VSS CVDD VSS

K

EMIFA00 VSS DVDD18

EMIFWE EMIFCE0

VSS DVDD18 VSS CVDD1 VSS CVDD VSS CVDD

J

EMIFBE0 EMIFCE2

RSV02

RESETFULLCORESEL0 DVDD18 VSS CVDD1 VSS CVDD VSS CVDD VSS

H

NMI

RSV03

BOOT

COMPLETE

RESET RESET

STAT

VSS DVDD18 VSS CVDD VSS CVDD VSS CVDD

G

EMIFCE1

HOUT DVDD18

LRESET CORESEL1 DVDD18

VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS

F

LRESET

NMIEN

DDRD25 VSS DDRD18 DDRDQM2 VSS DVDD15 VSS DVDD15 VSS DVDD15 VSS DVDD15

E

DDRDQM3 DDRD24 DDRD31 DDRD19 DDRD16 DDRD08

DDR

DQM1

DDRD09 DDRD04 DDRD05 VSS VREFSSTL DDRWE

D

DDRD28 DVDD15 DDRD29 DVDD15 DDRD23 DDRD12 DDRD14 DVDD15 DDRD02

DDR

DQS0P

DDRCB00 DDRODT1 DVDD15

C

DDR D27 VSS DDRD30 VSS DDRD22 DVDD15 DDRD13 VSS DDRD01

DDR

DQS0N

DDRCB02 DDRDQM8 VSS

B

DDRD26

DDR

DQS3N

DDRD17

DDR

DQS2P

DDRD21 VSS

DDR

DQS1P

DDRD15 DDRD03 DVDD15 DDRD07 DDRCB01

DDR

DQS8P

A

VSS

DDR

DQS3P

DDRD20

DDR

DQS2N

DDRD11 DDRD10

DDR

DQS1N

DDR

DQM0

DDRD00 VSS DDRD06 DDRCB03

DDR

DQS8N

1 2 12 13 3 4 5 6 7 8 9 10

Figure 3-28. Lower Left Quadrant—D (Bottom View)

11

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TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

3.9

Terminal Functions

The terminal functions table ( Table 3-39

) identifies the external signal names, the associated pin (ball) numbers, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal pullup/pulldown resistors, and gives functional pin descriptions. This table is arranged by function. The power terminal functions table

(

Table 3-40

) lists the various power supply pins and ground pins and gives functional pin descriptions.

Table 3-41

shows all pins arranged by signal name.

Table 3-42

shows all pins arranged by ball number.

There are 73 pins that have a secondary function as well as a primary function. The secondary function is indicated with a dagger (†). There is one pin that has a tertiary function as well as primary and secondary functions. The tertiary function is indicated with a double dagger (‡).

For more detailed information on device configuration, peripheral selection, multiplexed/shared pins, and pullup/pulldown resistors, see

Section 4.4

.

Use the symbol definitions in

Table 3-38

when reading

Table 3-39 .

Table 3-38. I/O Functional Symbol Definitions

FUNCTIONAL

SYMBOL

IPD or IPU

A

GND

I

O

S

Z

DEFINITION

Internal 100-µA pulldown or pullup is provided for this terminal. In most systems, a 1-k Ω resistor can be used to oppose the IPD/IPU. For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see Hardware

Design Guide for KeyStone Devices ( SPRABI2 ).

Analog signal

Ground

Input terminal

Output terminal

Supply voltage

Three-state terminal or high impedance

Table 3-39

COLUMN HEADING

IPD/IPU

Type

Type

Type

Type

Type

Type

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SIGNAL NAME

LENDIAN †

BOOTMODE00 †

BOOTMODE01†

BOOTMODE02 †

BOOTMODE03 †

BOOTMODE04 †

BOOTMODE05 †

BOOTMODE06 †

BOOTMODE07 †

BOOTMODE08 †

BOOTMODE09 †

BOOTMODE10 †

BOOTMODE11 †

BOOTMODE12 †

PCIESSMODE0 †

PCIESSMODE1 †

PCIESSEN ‡

CORECLKP

CORECLKN

SRIOSGMIICLKP

SRIOSGMIICLKN

DDRCLKP

DDRCLKN

PCIECLKP

PCIECLKN

MCMCLKP

MCMCLKN

AVDDA1

AVDDA2

SYSCLKOUT

HOUT

NMI

LRESET

LRESETNMIEN

CORESEL0

CORESEL1

RESETFULL

RESET

POR

RESETSTAT

BOOTCOMPLETE

PTV15

42

Device Overview

Table 3-39. Terminal Functions — Signals and Control by Function

G5

J4

H4

Y18

H5

H3

F15

G2

H1

G4

F1

J5

I

I

I

I

O

OZ

A

I

I

I

I

OZ

AD18 I

AE19 I

AD13 I

AE14 I

A22 I

B22

AD14 I

AE15 I

I

C25

B25 I

I

Y15 P

F20 P

AA19 OZ

BALL

NO.

T22

R21

U22

U23

V23

U21

T21

T25

R25

R23

U25

T23

U24

V22 IOZ

W21 IOZ

V21 IOZ

AD20 I

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

TYPE IPD/IPU DESCRIPTION

IOZ

IOZ

UP

Down

Boot Configuration Pins

Endian configuration pin (Pin shared with GPIO[0])

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

See

Section 3.5

for more details

(Pins shared with GPIO[1:13])

PCIe Mode selection pins (Pins shared with GPIO[14:15])

PCIe module enable (Pin shared with TIMI0 and GPIO16)

Clock / Reset

Down

UP

UP

UP

UP

Down

Down

UP

UP

Core Clock Input to main PLL.

SGMII Reference Clock to drive the SGMII SerDes

DDR Reference Clock Input to DDR PLL

PCIe Clock Input to drive PCIe SerDes

Reserved

SYS_CLK PLL Power Supply Pin

DDR_CLK PLL Power Supply Pin

System Clock Output to be used as a general purpose output clock for debug purposes

Interrupt output pulse created by IPCGRH

Non-maskable Interrupt

Warm Reset

Enable for core selects

Select for the target core for LRESET and NMI. For more details see

Table 8-40

UP

Down

Full Reset

Warm Reset of non isolated portion on the IC

Power-on Reset

Reset Status Output

Boot progress indication output

PTV Compensation NMOS Reference Input. A precision resistor placed between the

PTV15 pin and ground is used to closely tune the output impedance of the DDR interface drivers to 50 Ohms. Presently, the recommended value for this 1% resistor is

45.3 Ohms.

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SPRS841B – MARCH 2012 – REVISED APRIL 2015

DDRD03

DDRD04

DDRD05

DDRD06

DDRD07

DDRD08

DDRD09

DDRD10

DDRD11

DDRD12

DDRD13

DDRD14

DDRD15

DDRD16

DDRD17

DDRD18

DDRD19

DDRD20

DDRDQM0

DDRDQM1

DDRDQM2

DDRDQM3

DDRDQM8

DDRDQS0P

DDRDQS0N

DDRDQS1P

DDRDQS1N

DDRDQS2P

DDRDQS2N

DDRDQS3P

DDRDQS3N

DDRDQS8P

DDRDQS8N

DDRCB00

DDRCB01

DDRCB02

DDRCB03

DDRD00

DDRD01

DDRD02

SIGNAL NAME

C7

D7

B8

E5

B3

F4

E4

A3

E6

E8

A6

A5

D6

B9

E9

E10

A11

B11

C11

A12

A9

C9

D9

B2

B13

A13

D11

B12

B7

A7

B4

A4

A2

A8

E7

F5

E1

C12

D10

C10

Table 3-39. Terminal Functions — Signals and Control by Function (continued)

BALL

NO.

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

OZ

OZ

OZ

IOZ

IOZ

TYPE IPD/IPU DESCRIPTION

DDR

OZ

OZ

DDR EMIF Data Masks

DDR EMIF Data Strobe

DDR EMIF Check Bits

DDR EMIF Data Bus

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DDRA02

DDRA03

DDRA04

DDRA05

DDRA06

DDRA07

DDRA08

DDRA09

DDRA10

DDRA11

DDRA12

DDRA13

DDRA14

DDRA15

DDRCAS

DDRRAS

DDRWE

DDRCKE0

DDRCKE1

DDRCLKOUTP0

DDRD29

DDRD30

DDRD31

DDRCE0

DDRCE1

DDRBA0

DDRBA1

DDRBA2

DDRA00

DDRA01

SIGNAL NAME

DDRD21

DDRD22

DDRD23

DDRD24

DDRD25

DDRD26

DDRD27

DDRD28

DDRCLKOUTN0

DDRCLKOUTP1

DDRCLKOUTN1

DDRODT0

DDRODT1

DDRRESET

DDRSLRATE0

DDRSLRATE1

VREFSSTL

Table 3-39. Terminal Functions — Signals and Control by Function (continued)

A15

E13

A16

A20

A14

D18

C20

E18

E17

D14

A18

D20

E20

E19

B20

E16

E15

B18

A17

C16

B14

A21

B21

E14

D12

B16

C22

D22

E12

C18

D17

B19

D16

A19

D3

C3

E3

B15

C14

E2

F2

B1

C1

D1

BALL

NO.

B5

C5

D5

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

I

I

OZ

P

OZ

OZ

OZ

OZ

OZ

IOZ

IOZ

IOZ

OZ

OZ

IOZ

IOZ

IOZ

IOZ

IOZ

TYPE IPD/IPU DESCRIPTION

IOZ

IOZ

IOZ

DDR EMIF Data Bus

DDR EMIF Data Bus

DDR EMIF Chip Enables

DDR EMIF Bank Address

Down

Down

DDR EMIF Address Bus

DDR EMIF Column Address Strobe

DDR EMIF Row Address Strobe

DDR EMIF Write Enable

DDR EMIF Clock Enable

DDR EMIF Clock Enable

DDR EMIF Output Clocks to drive SDRAMs (one clock pair per SDRAM)

DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs

DDR EMIF On Die Termination Outputs used to set termination on the SDRAMs

DDR Reset signal

DDR Slew rate control

Reference Voltage Input for SSTL15 buffers used by DDR EMIF (VDDS15 ÷ 2)

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SPRS841B – MARCH 2012 – REVISED APRIL 2015

EMIFA11

EMIFA12

EMIFA13

EMIFA14

EMIFA15

EMIFA16

EMIFA17

EMIFA18

EMIFA19

EMIFA20

EMIFA21

EMIFA22

EMIFA23

EMIFA00

EMIFA01

EMIFA02

EMIFA03

EMIFA04

EMIFA05

EMIFA06

EMIFA07

EMIFA08

EMIFA09

EMIFA10

SIGNAL NAME

EMIFRW

EMIFCE0

EMIFCE1

EMIFCE2

EMIFCE3

EMIFOE

EMIFWE

EMIFBE0

EMIFBE1

EMIFWAIT0

EMIFWAIT1

L5

K5

G1

J2

M5

L4

K4

J1

L3

N5

M4

Table 3-39. Terminal Functions — Signals and Control by Function (continued)

BALL

NO.

OZ

OZ

OZ

OZ

OZ

I

OZ

I

OZ

TYPE IPD/IPU DESCRIPTION

EMIF16

OZ

OZ

UP

UP

UP

UP

UP

UP

UP

UP

UP

Down

Down

EMIF16 Control Signals

EMIF16 Control Signal

This EMIF16 pin has a secondary function assigned to it as mentioned elsewhere in this table (see UPP).

R2

R1

T4

T1

T5

U1

U2

U3

P2

P1

R5

R3

R4

L1

P4

M2

M1

N2

P3

N1

K1

M3

L2

P5

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

OZ

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

EMIF16 Address

These EMIF16 pins have secondary functions assigned to them as mentioned elsewhere in this table (see uPP).

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SIGNAL NAME

EMIFD00

EMIFD01

EMIFD02

EMIFD03

EMIFD04

EMIFD05

EMIFD06

EMIFD07

EMIFD08

EMIFD09

EMIFD10

EMIFD11

EMIFD12

EMIFD13

EMIFD14

EMIFD15

UPP_2XTXCLK †

Table 3-39. Terminal Functions — Signals and Control by Function (continued)

W2

Y1

W4

Y2

W5

AA1

AB1

AA2

V2

V3

V4

W1

V5

BALL

NO.

U4

U5

V1

M4 I

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

TYPE IPD/IPU DESCRIPTION

IOZ Down

IOZ

IOZ

Down

Down

Down

Down

Down

Down

Down

EMIF16 Data

These EMIF16 pins have secondary functions assigned to them as mentioned elsewhere in this table (see uPP).

Down

Down

Down

Down

Down

IOZ

IOZ

IOZ

Down

Down

Down

Down

uPP

uPP Transmit Reference Clock (2x Transmit Rate)

UPP_CH0_CLK †

UPP_CH0_WAIT †

UPP_CH1_CLK †

UPP_CH1_WAIT †

R2

UPP_CH0_START † R1

UPP_CH0_ENABLE † T4

T1

T5

UPP_CH1_START † U1

UPP_CH1_ENABLE † U2

U3

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

Down

Down

Down

Down

Down

Down

Down

Down

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).

uPP Channel 0 Clock

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).

uPP Channel 0 Start

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).

uPP Channel 0 Enable

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).

uPP Channel 0 Wait

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).

uPP Channel 1 Clock

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).

uPP Channel 1 Start

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).

uPP Channel 1 Enable

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).

uPP Channel 1 Wait

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).

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UPPXD02 †

UPPXD03 †

UPPXD04 †

UPPXD05 †

UPPXD06 †

UPPXD07 †

UPPXD08 †

UPPXD09 †

UPPXD10 †

UPPXD11 †

UPPXD12 †

UPPXD13 †

UPPXD14 †

UPPXD15 †

SIGNAL NAME

UPPD00 †

UPPD01 †

UPPD02 †

UPPD03 †

UPPD04 †

UPPD05 †

UPPD06 †

UPPD07 †

UPPD08 †

UPPD09 †

UPPD10 †

UPPD11 †

UPPD12 †

UPPD13 †

UPPD14 †

UPPD15 †

UPPXD00 †

UPPXD01 †

Table 3-39. Terminal Functions — Signals and Control by Function (continued)

AA1

AB1

AA2

K1

M3

W2

Y1

W4

Y2

W5

V2

V3

V4

W1

V5

BALL

NO.

U4

U5

V1

M1

N2

P3

N1

P2

P1

R5

R3

R4

L2

P5

L1

P4

M2

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

TYPE IPD/IPU DESCRIPTION

IOZ Down

IOZ

IOZ

Down

Down

Down

Down

Down

Down

Down uPP Data

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down uPP Extended Data

Down

Down

Down

Down

Down

Down

Down

Down

Down

This uPP pin has a primary function assigned to it as mentioned elsewhere in this table (see EMIF16).

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EMU00

EMU01

EMU02

EMU03

EMU04

EMU05

EMU06

EMU07

EMU08

EMU09

EMU10

EMU11

EMU12

EMU13

EMU14

EMU15

EMU16

EMU17

EMU18

GPIO00

GPIO01

GPIO02

GPIO03

GPIO04

GPIO05

GPIO06

GPIO07

GPIO08

GPIO09

GPIO10

GPIO11

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16 †

SIGNAL NAME

Table 3-39. Terminal Functions — Signals and Control by Function (continued)

R21

U22

U23

V23

U21

T25

R25

R23

U25

T23

U24

T22

T21 IOZ

V22 IOZ

W21 IOZ

V21 IOZ

AD20 IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

IOZ

BALL

NO.

V24

V25

W25 IOZ

W23 IOZ

W24 IOZ

Y25

Y24

IOZ

IOZ

TYPE IPD/IPU DESCRIPTION

EMU

IOZ

IOZ

UP

UP

UP

UP

UP

UP

UP

Y23 IOZ

W22 IOZ

Y22 IOZ

AA24 IOZ

AA25 IOZ

UP

UP

UP

UP

UP

Emulation and Trace Port

AB25 IOZ

AC25 IOZ

AA23 IOZ

AB22 IOZ

AD25 IOZ

AC24 IOZ

Y21 IOZ

UP

UP

UP

UP

UP

UP

UP

General Purpose Input/Output (GPIO)

UP

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

Down

General Purpose Input/Output

These GPIO pins have secondary functions assigned to them as mentioned elsewhere in this table (see Boot Configuration Pins).

General Purpose Input/Output

GPIO17 †

GPIO18 †

GPIO19 †

AE21 IOZ

AC19 IOZ

AE20 IOZ

Down

Down

Down

This GPIO pin has a primary function assigned to it as mentioned elsewhere in this table (see Timer) and a tertiary function assigned to it as mentioned elsewhere in this table (see Boot Configuration Pins).

General Purpose Input/Output

These GPIO pins have primary functions assigned to them as mentioned elsewhere in this table (see Timer).

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TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

Table 3-39. Terminal Functions — Signals and Control by Function (continued)

SIGNAL NAME

GPIO20 †

GPIO21 †

GPIO22 †

GPIO23 †

GPIO24 †

GPIO25 †

GPIO26 †

GPIO27 †

GPIO28 †

GPIO29 †

GPIO30 †

GPIO31 †

MCMRXN0

MCMRXP0

MCMRXN1

MCMRXP1

MCMRXN2

MCMRXP2

MCMRXN3

MCMRXP3

MCMTXN0

MCMTXP0

MCMTXN1

MCMTXP1

MCMTXN2

MCMTXP2

MCMTXN3

MCMTXP3

MCMRXFLCLK

MCMRXFLDAT

MCMTXFLCLK

MCMTXFLDAT

MCMRXPMCLK

MCMRXPMDAT

MCMTXPMCLK

MCMTXPMDAT

D24

F24

G24

MCMREFCLKOUTP G25

MCMREFCLKOUTN F25

B24

C24

E25

D25

E24

M21

K22

L22

J21

K21

K24

L24

P22

N22

N21

N24

M25

N25

J25

K25

BALL

NO.

TYPE IPD/IPU DESCRIPTION

AB15 IOZ Down

AA15 IOZ

AC17 IOZ

Down

Down

General Purpose Input/Output

AB17 IOZ

AC14 IOZ

AC15 IOZ

Down

Down

Down

These GPIO pins have primary functions assigned to them as mentioned elsewhere in this table (see UART).

AE16 IOZ

AD15 IOZ

AA12 IOZ

AA14 IOZ

AB14 IOZ

AB13 IOZ

P24 I

Down

Down

Up

Up

Down

Down

General Purpose Input/Output

These GPIO pins have primary functions assigned to them as mentioned elsewhere in this table (see SPI).

I

I

I

I

I

I

I

I

I

I

I

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Down

Down

Down

Down

Down

Down

Down

Down

Reserved — leave unconnected

Reserved — leave unconnected

Reserved — leave unconnected

Reserved — leave unconnected

I

2

C

SCL

SDA

AA17

AA18

IOZ

IOZ

I

2

C Clock

I

2

C Data

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SPRS841B – MARCH 2012 – REVISED APRIL 2015

CLKR0

CLKX0

CLKS0

FSR0

FSX0

DR0

DX0

CLKR1

CLKX1

CLKS1

FSR1

FSX1

DR1

DX1

PCIERXN0

PCIERXP0

PCIERXN1

PCIERXP1

PCIETXN0

PCIETXP0

PCIETXN1

PCIETXP1

RIORXN0

RIORXP0

RIORXN1

RIORXP1

RIORXN2

RIORXP2

RIORXN3

RIORXP3

SIGNAL NAME

TCK

TDI

TDO

TMS

TRST

MDIO

MDCLK

Table 3-39. Terminal Functions — Signals and Control by Function (continued)

AE12 I

AE11 I

AD10 I

AD11 I

AC12 O

AC11 O

AB11 O

AB10 O

AE9

AE8

AD8

AD7

AE5 I

I

I

I

I

AE6

AD4

AD5 I

I

I

BALL

NO.

AD17 I

AE17 I

TYPE IPD/IPU DESCRIPTION

JTAG

Up

Up

JTAG Clock Input

JTAG Data Input

AD19 OZ

AE18 I

AB19 I

Up

Up

Down

JTAG Data Output

JTAG Test Mode Input

JTAG Reset

McBSP

McBSP Receive Clock AA21 IOZ

Y20 IOZ

AC23 IOZ

AD24 IOZ

Down

Down

Down

Down

McBSP Transmit Clock

McBSP Slow Clock

McBSP Receive Frame Sync

McBSP Transmit Frame Sync

McBSP Receive Data

AA20 IOZ

AB21 I

AC22 OZ

AD23 IOZ

AE24 IOZ

AC21 IOZ

AD22 IOZ

Down

Down

Down

Down

Down

Down

Down

McBSP Transmit Data

McBSP Receive Clock

McBSP Transmit Clock

McBSP Slow Clock

McBSP Receive Frame Sync

AE23 IOZ

AD21 I

AE22 OZ

AB16

AA16

IOZ

O

Down

Down

Down

Up

Down

McBSP Transmit Frame Sync

McBSP Receive Data

McBSP Transmit Data

MDIO Data

MDIO Clock

MDIO

PCIe

PCIexpress Receive Data (2 links)

PCIexpress Transmit Data (2 links)

Reserved — leave unconnected

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TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

SIGNAL NAME

RIOTXN0

RIOTXP0

RIOTXN1

RIOTXP1

RIOTXN2

RIOTXP2

RIOTXN3

RIOTXP3

SGMII0RXN

SGMII0RXP

SGMII0TXN

SGMII0TXP

VCNTL0

VCNTL1

VCNTL2

VCNTL3

SPISCS0

SPISCS1

Table 3-39. Terminal Functions — Signals and Control by Function (continued)

AB8

AC5

AC6

AB4

AB5

BALL

NO.

AC9

AC8

AB7

AE2

AE3

AC2

AC3

E22

E23

F23

G23

AA12

OZ

OZ

OZ

OZ

O

O

I

I

O

O

O

O

O

O

O

TYPE IPD/IPU DESCRIPTION

O

Reserved — leave unconnected

SGMII

Ethernet MAC SGMII Receive Data

Ethernet MAC SGMII Transmit Data

SmartReflex

Voltage Control Outputs to variable core power supply. These are open-drain output buffers.

OZ Up

SPI

SPI Interface Enable 0

AA14 OZ Up

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).

SPI Interface Enable 1

SPICLK

SPIDIN

SPIDOUT

TIMI0

TIMI1

TIMO0

TIMO1

UARTRXD

UARTTXD

AA13 OZ

AB14 I

AB13 OZ

AD20 I

AE21 I

AC19 OZ

AE20 OZ

AB15 I

AA15 OZ

Down

Down

Down

Down

Down

Down

Down

Down

Down

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).

SPI Clock

SPI Data In

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).

SPI Data Out

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).

Timer

Timer Inputs

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).

Timer Outputs

These Timer pins have secondary functions assigned to them as mentioned elsewhere in this table

UART

UART Serial Data In

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).

UART Serial Data Out

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).

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SIGNAL NAME

UARTCTS

Table 3-39. Terminal Functions — Signals and Control by Function (continued)

BALL

NO.

AC17 I

TYPE IPD/IPU DESCRIPTION

Down UART Clear To Send

UARTRTS

UARTRXD1

UARTTXD1

UARTCTS1

UARTRTS1

RSV12

RSV13

RSV14

RSV15

RSV16

RSV17

RSV18

RSV19

RSV20

RSV21

RSV0A

RSV0B

RSV01

RSV02

RSV03

RSV04

RSV05

RSV06

RSV07

RSV08

RSV09

RSV10

RSV11

AB17 OZ

AC14 I

AC15 OZ

AE16 I

AD15 OZ

AA22 IOZ

J3 OZ

H2 OZ

AC18 O

AB18 O

B23 O

A23

Y19

C23

G22

H22

A

A

O

OZ

OZ

Y5

Y4

F21

G21

J20

AA7 A

AA11 A

AB3 A

F22

D23

G19

G20

A

A

IOZ

IOZ

A

A

A

A

A

Down

Down

Down

Down

Down

Up

Down

Down

Down

Down

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).

UART Request To Send

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).

UART Serial Data In

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).

UART Serial Data Out

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).

UART Clear To Send

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).

UART Request To Send

This SPI pin has a secondary function assigned to it as mentioned elsewhere in this table (see GPIO).

Reserved

Reserved - pullup to DVDD18

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - connect to GND

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

Reserved - leave unconnected

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TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

Table 3-40. Terminal Functions — Power and Ground

SUPPLY

AVDDA1

AVDDA2

CVDD

CVDD1

DVDD15

DVDD18

VDDR1

VDDR2

VDDR3

VDDR4

VDDT1

VDDT2

BALL NO.

Y15

F20

J8, J18, K9, K17, T9, T17, U8, U18

VOLTS DESCRIPTION

1.8

PLL Supply - CORE_PLL

1.8

H9, H11, H13, H15, H17, J10, J12, J14, J16, K11, K13, K15, L8, L10, L12, 0.85 to

L14, L16, L18, M9, M11, M13, M15, M17, N8, N10, N12, N14, N16, N18, P9, 1.1

P11, P13, P15, P17, P19, R10, R12, R14, R16, R18, T11, T13, T15, U10,

U12, U14, U16, V9, V11, V13, V15, V17

1.0

PLL Supply - DDR3_PLL

SmartReflex core supply voltage

Fixed core supply voltage for memory array

DDR IO supply B10, C6, C17, C21, D2, D4, D8, D13, D15, D19, F7, F9, F11, F13, F17, F19, 1.5

G8, G10, G12, G14, G16, G18

1.8

A24, E21, G3, G6, H7, H19, H24, J6, K3, K7, L6, M7, N3, N6, P7, R6, R20,

T3, T7, T19, T24, U6, U20, V7, V19, W6, W14, W16, W18, W20, Y3, Y13,

Y17, AB23, AC16, AC20

M20

AA9

AA3

AA5

1.5

1.5

1.5

1.5

IO supply

Reserved — connect to DVDD15

PCIe SerDes regulator supply

SGMII SerDes regulator supply

Reserved — connect to DVDD15

K19, L20, M19, N20

W8, W10, W12, Y7, Y9, Y11

1.0

1.0

Reserved — connect to CVDD1

SGMII/PCIe SerDes termination supply

DDR3 reference voltage

Ground

VREFSSTL E12

VSS A1, A10, A25, B6, B17, C2, C4, C8, C13, C15, C19, D21, E11, F3, F6, F8,

F10, F12, F14, F16, F18, G7, G9, G11, G13, G15, G17, H6, H8, H10, H12,

H14, H16, H18, H20, H21, H23, H25, J7, J9, J11, J13, J15, J17, J19, J22,

J23, J24, K2, K6, K8, K10, K12, K14, K16, K18, K20, K23, L7, L9, L11, L13,

L15, L17, L19, L21, L23, L25, M6, M8, M10, M12, M14, M16, M18, M22, M23,

M24, N4, N7, N9, N11, N13, N15, N17, N19, N23, P6, P8, P10, P12, P14,

P16, P18, P20, P21, P23, P25, R7, R8, R9, R11, R13, R15, R17, R19, R22,

R24, T2, T6, T8, T10, T12, T14, T16, T18, T20, U7, U9, U11, U13, U15, U17,

U19, V6, V8, V10, V12, V14, V16, V18, V20, W3, W7, W9, W11, W13, W15,

W17, W19, Y6, Y8, Y10, Y12, Y14, Y16, AA4, AA6, AA8, AA10, AB2, AB6,

AB9, AB12, AB20, AB24, AC1, AC4, AC7, AC10, AC13, AD1, AD2, AD3, AD6,

AD9, AD12, AD16, AE1, AE4, AE7, AE10, AE13, AE25

0.75

GND

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DDRA00

DDRA01

DDRA02

DDRA03

DDRA04

DDRA05

DDRA06

DDRA07

DDRA08

SIGNAL NAME

AVDDA1

BALL NUMBER

Y15

AVDDA2 F20

BOOTCOMPLETE H3

BOOTMODE00 †

BOOTMODE01 †

R25

R23

BOOTMODE02 †

BOOTMODE03 †

BOOTMODE04 †

BOOTMODE05 †

BOOTMODE06 †

BOOTMODE07 †

BOOTMODE08 †

U25

T23

U24

T22

R21

U22

U23

BOOTMODE09 †

BOOTMODE10 †

BOOTMODE11 †

BOOTMODE12 †

CLKR0

CLKR1

CLKS0

CLKS1

CLKX0

CLKX1

CORECLKN

CORECLKP

CORESEL0

CORESEL1

CVDD

V23

U21

T21

V22

AA21

AD23

AC23

AC21

Y20

AE24

AE19

AD18

J5

G5

H9, H11, H13, H15,

H17, J10, J12, J14,

J16, K11, K13, K15,

L8, L10, L12, L14,

L16, L18, M9, M11,

M13, M15, M17, N8,

N10, N12, N14,

N16, N18, P9, P11,

P13, P15, P17, P19,

R10, R12, R14,

R16, R18, T11, T13,

T15, U10, U12, U14,

U16, V9, V11, V13,

V15, V17

CVDD1 J8, J18, K9, K17,

T9, T17, U8, U18

D16

A19

E16

E15

B18

A17

C16

A18

D20

Table 3-41. Terminal Functions — By Signal Name

DDRCLKOUTP0

DDRCLKOUTP1

DDRCLKP

DDRD00

DDRD01

DDRD02

DDRD03

DDRD04

DDRD05

DDRD06

DDRD07

DDRD08

DDRD09

DDRD10

DDRD11

DDRD12

DDRD13

SIGNAL NAME

DDRA09

DDRA10

DDRA11

DDRA12

DDRA13

DDRA14

DDRA15

DDRBA0

DDRBA1

DDRBA2

DDRCAS

DDRCB00

DDRCB01

DDRCB02

DDRCB03

DDRCE0

DDRCE1

DDRCKE0

DDRCKE1

DDRCLKN

DDRCLKOUTN0

DDRCLKOUTN1

DDRD14

DDRD15

DDRD16

DDRD17

DDRD18

DDRD19

DDRD20

DDRD21

D7

B8

E5

B3

F4

E4

A3

B5

D9

B9

E9

E10

A11

A14

A21

A22

A9

C9

A6

A5

D6

C7

B11

E6

E8

A16

A20

B22

B14

B21

B12

C11

A12

B15

C14

E18

E17

C18

D17

B19

D14

D11

BALL NUMBER

E20

E19

B20

D18

C20

SIGNAL NAME

DDRD22

DDRD23

DDRD24

DDRD25

DDRD26

DDRD27

DDRD28

DDRD29

DDRD30

DDRD31

DDRDQM0

DDRDQM1

DDRDQM2

DDRDQM3

DDRDQM8

DDRDQS0N

DDRDQS0P

DDRDQS1N

DDRDQS1P

DDRDQS2N

DDRDQS2P

DDRDQS3N

DDRDQS3P

DDRDQS8N

DDRDQS8P

DDRODT0

DDRODT1

DDRRAS

DDRRESET

DDRSLRATE0

DDRSLRATE1

DDRWE

DR0

DR1

DVDD15

DVDD18

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A7

B7

A4

B4

B2

F5

E1

C12

C10

D10

C1

D1

D3

C3

E3

A8

E7

BALL NUMBER

C5

D5

E2

F2

B1

A15

B16

C22

D22

E13

A2

A13

B13

E14

D12

AB21

AD21

B10, C6, C17,

C21, D2, D4, D8,

D13, D15, D19,

F7, F9, F11, F13,

F17, F19, G8,

G10, G12, G14,

G16, G18

A24, E21, G3,

G6, H7, H19,

H24, J6, K3, K7,

L6, M7, N3, N6,

P7, R6, R20, T3,

T7, T19, T24, U6,

U20, V7, V19,

W6, W14, W16,

W18, W20, Y3,

Y13, Y17, AB23,

AC16, AC20

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EMIFCE3

EMIFD00

EMIFD01

EMIFD02

EMIFD03

EMIFD04

EMIFD05

EMIFD06

EMIFD07

EMIFD08

EMIFA19

EMIFA20

EMIFA21

EMIFA22

EMIFA23

EMIFBE0

EMIFBE1

EMIFCE0

EMIFCE1

EMIFCE2

EMIFD09

EMIFD10

EMIFD11

EMIFD12

EMIFD13

EMIFD14

EMIFA09

EMIFA10

EMIFA11

EMIFA12

EMIFA13

EMIFA14

EMIFA15

EMIFA16

EMIFA17

EMIFA18

SIGNAL NAME

DX0

DX1

EMIFA00

EMIFA01

EMIFA02

EMIFA03

EMIFA04

EMIFA05

EMIFA06

EMIFA07

EMIFA08

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SPRS841B – MARCH 2012 – REVISED APRIL 2015

GPIO02

GPIO03

GPIO04

GPIO05

GPIO06

GPIO07

GPIO08

GPIO09

GPIO10

GPIO11

EMU15

EMU16

EMU17

EMU18

FSR0

FSR1

FSX0

FSX1

GPIO00

GPIO01

GPIO12

GPIO13

GPIO14

GPIO15

GPIO16 †

GPIO17 †

EMU05

EMU06

EMU07

EMU08

EMU09

EMU10

EMU11

EMU12

EMU13

EMU14

SIGNAL NAME

EMIFD15

EMIFOE

EMIFRNW

EMIFWAIT0

EMIFWAIT1

EMIFWE

EMU00

EMU01

EMU02

EMU03

EMU04

Table 3-41. Terminal Functions — By Signal Name (continued)

V3

V4

W1

V5

W2

M5

U4

U5

V1

V2

Y1

W4

Y2

W5

AA1

AB1

J1

L3

K5

G1

J2

T1

T5

U1

U2

U3

R3

R4

R2

R1

T4

P3

N1

P2

P1

R5

L1

P4

M2

M1

N2

BALL NUMBER

AC22

AE22

K1

M3

L2

P5

R21

U22

U23

V23

U21

R23

U25

T23

U24

T22

T21

V22

W21

V21

AD20

AE21

AB22

AD25

AC24

Y21

AD24

AD22

AA20

AE23

T25

R25

Y25

Y24

Y23

W22

Y22

AA24

AA25

AB25

AC25

AA23

V24

V25

W25

W23

W24

BALL NUMBER

AA2

L4

L5

N5

M4

K4

MCMREFCLKOUTP

MCMRXFLCLK

MCMRXFLDAT

MCMRXN0

MCMRXN1

MCMRXN2

MCMRXN3

MCMRXP0

MCMRXP1

MCMRXP2

MCMRXP3

MCMRXPMCLK

MCMRXPMDAT

MCMTXFLCLK

MCMTXFLDAT

MCMTXN0

MCMTXN1

MCMTXN2

MCMTXN3

MCMTXP0

MCMTXP1

MCMTXP2

MCMTXP3

MCMTXPMCLK

MCMTXPMDAT

MDCLK

SIGNAL NAME

GPIO18 †

GPIO19 †

GPIO20 †

GPIO21 †

GPIO22 †

GPIO23 †

GPIO24 †

GPIO25 †

GPIO26 †

GPIO27 †

GPIO28 †

GPIO29 †

GPIO30 †

GPIO31 †

HOUT

LENDIAN †

LRESETNMIEN

LRESET

MCMCLKN

MCMCLKP

MCMREFCLKOUTN

P22

N21

K22

J21

N22

L24

E24

D24

E25

D25

M21

L22

K21

F24

G24

AA16

J25

K24

N24

N25

K25

G25

B24

C24

P24

M25

F1

G4

B25

C25

F25

AA14

AB14

AB13

G2

T25

BALL NUMBER

AC19

AE20

AB15

AA15

AC17

AB17

AC14

AC15

AE16

AD15

AA12

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55

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

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RIOTXP1

RIOTXP2

RIOTXP3

RSV01

RSV02

RSV03

RSV04

RSV05

RSV06

RSV07

RIORXN3

RIORXP0

RIORXP1

RIORXP2

RIORXP3

RIOTXN0

RIOTXN1

RIOTXN2

RIOTXN3

RIOTXP0

RSV08

RSV09

RSV0A

RSV0B

RSV10

RSV11

SIGNAL NAME

MDIO

NMI

PCIECLKN

PCIECLKP

PCIERXN0

PCIERXN1

PCIERXP0

PCIERXP1

PCIESSEN ‡

PCIETXN0

PCIETXN1

PCIETXP0

PCIETXP1

POR

PTV15

RESETFULL

RESETSTAT

RESET

RIORXN0

RIORXN1

RIORXN2

56

Device Overview

Table 3-41. Terminal Functions — By Signal Name (continued)

AB8

AC6

AB5

AA22

J3

H2

AC18

AB18

B23

A23

Y19

C23

G19

G20

G22

H22

AC9

AB7

AC5

AB4

AC8

AD4

AE8

AD7

AE6

AD5

H5

H4

AE9

AD8

AE5

AC11

AB10

Y18

F15

J4

BALL NUMBER

AB16

H1

AE15

AD14

AE12

AD10

AE11

AD11

AD20

AC12

AB11

SIGNAL NAME

RSV12

RSV13

RSV14

RSV15

RSV16

RSV17

RSV18

RSV19

RSV20

RSV21

SCL

SDA

SGMII0RXN

SGMII0RXP

SGMII0TXN

SGMII0TXP

SPICLK

SPIDIN

SPIDOUT

SPISCS0

SPISCS1

SRIOSGMIICLKN AE14

SRIOSGMIICLKP AD13

SYSCLKOUT AA19

TCK

TDI

AD17

AE17

TDO

TIMI0

TIMI1

TIMO0

TIMO1

AD19

AD20

AE21

AC19

AE20

TMS

TRST

UARTCTS

UARTCTS1

UARTRTS

UARTRTS1

UARTRXD

UARTRXD1

UARTTXD

UARTTXD1

UPP_2XTXCLK † M4

UPP_CH0_CLK † R2

UPP_CH0_

ENABLE †

T4

AE18

AB19

AC17

AE16

AB17

AD15

AB15

AC14

AA15

AC15

AA18

AE2

AE3

AC2

AC3

AA13

AB14

AB13

AA12

AA14

BALL NUMBER

Y5

Y4

F21

G21

J20

AA7

AA11

AB3

F22

D23

AA17

UPP_CH0_

START †

R1

UPPXD00 †

UPPXD01 †

UPPXD02 †

UPPXD03 †

UPPXD04 †

UPPXD05 †

UPPXD06 †

UPPXD07 †

UPPXD08 †

UPPXD09 †

UPPXD10 †

UPPXD11 †

UPPXD12 †

UPPXD13 †

UPPXD14 †

UPPXD15 †

VCNTL0

VCNTL1

VCNTL2

VCNTL3

VDDR1

VDDR2

VDDR3

VDDR4

VDDT1

SIGNAL NAME

UPP_CH0_WAIT †

BALL NUMBER

T1

UPP_CH1_CLK † T5

UPP_CH1_ENABLE † U2

UPP_CH1_START † U1

UPP_CH1_WAIT †

UPPD00 †

U3

U4

UPPD01 †

UPPD02 †

UPPD03 †

UPPD04 †

UPPD05 †

U5

V1

V2

V3

V4

UPPD06 †

UPPD07 †

UPPD08 †

UPPD09 †

UPPD10 †

UPPD11 †

UPPD12 †

UPPD13 †

UPPD14 †

UPPD15 †

W1

V5

W2

Y1

W4

Y2

W5

AA1

AB1

AA2

R4

E22

E23

F23

G23

N1

P2

P1

R5

R3

P4

M2

M1

N2

P3

K1

M3

L2

P5

L1

M20

AA9

AA3

AA5

K19, L20, M19,

N20

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SIGNAL NAME

VDDT2

VDDT1

VDDT2

VDDT2

VDDT2

VDDT2

VDDT2

VREFSSTL

VSS

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

Table 3-41. Terminal Functions — By Signal Name (continued)

BALL NUMBER

W8, W10, W12, Y7,

Y9, Y11

N20

W10

W12

Y7

Y9

Y11

E12

A1, A10, A25, B6,

B17, C2, C4, C8,

C13, C15, C19,

D21, E11, F3, F6,

F8, F10, F12, F14,

F16, F18, G7, G9,

G11, G13, G15,

G17, H6, H8, H10,

H12, H14, H16,

H18, H20, H21,

H23, H25, J7, J9,

J11, J13, J15, J17,

J19, J22, J23, J24,

K2, K6, K8, K10,

K12, K14, K16, K18,

K20, K23, L7, L9,

L11, L13, L15, L17,

L19, L21, L23, L25,

M6, M8, M10, M12,

M14, M16, M18,

M22, M23, M24, N4,

N7, N9, N11, N13,

N15, N17, N19,

N23, P6, P8, P10,

P12, P14, P16, P18,

P20, P21, P23, P25,

R7, R8, R9, R11,

R13, R15, R17,

R19, R22, R24, T2,

T6, T8, T10, T12,

T14, T16, T18, T20,

U7, U9, U11, U13,

U15, U17, U19, V6,

V8, V10, V12, V14,

V16, V18, V20, W3,

W7, W9, W11, W13,

W15, W17, W19,

Y6, Y8, Y10, Y12,

Y14, Y16, AA4,

AA6, AA8, AA10,

AB2, AB6, AB9,

AB12, AB20, AB24,

AC1, AC4, AC7,

AC10, AC13, AD1,

AD2, AD3, AD6,

AD9, AD12, AD16,

AE1, AE4, AE7,

AE10, AE13, AE25

SIGNAL NAME BALL NUMBER SIGNAL NAME BALL NUMBER

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57

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

B13

B14

B15

B16

B17

B8

B9

B10

B11

B12

B18

B19

B20

B21

B22

B3

B4

B5

B6

B7

A23

A24

A25

B1

B2

A18

A19

A20

A21

A22

A13

A14

A15

A16

A17

A6

A7

A8

A9

A10

A11

A12

BALL NUMBER

A1

A2

A3

A4

A5

Table 3-42. Terminal Functions — By Ball Number

RSV07

DVDD18

VSS

DDRD26

DDRDQS3N

DDRD17

DDRDQS2P

DDRD21

VSS

DDRDQS1P

DDRD15

DDRD03

DVDD15

DDRD07

DDRCB01

DDRDQS8P

DDRCLKOUTN0

DDRCE0

DDRRESET

VSS

DDRA04

DDRBA2

DDRA11

DDRCLKOUTN1

DDRCLKN

SIGNAL NAME

VSS

DDRDQS3P

DDRD20

DDRDQS2N

DDRD11

DDRD10

DDRDQS1N

DDRDQM0

DDRD00

VSS

DDRD06

DDRCB03

DDRDQS8N

DDRCLKOUTP0

DDRRAS

DDRCKE0

DDRA05

DDRA07

DDRA01

DDRCKE1

DDRCLKOUTP1

DDRCLKP

D10

D11

D12

D13

D14

D5

D6

D7

D8

D9

D15

D16

D17

D18

D19

C25

D1

D2

D3

D4

C20

C21

C22

C23

C24

C15

C16

C17

C18

C19

C10

C11

C12

C13

C14

C3

C4

C5

C6

C7

C8

C9

BALL NUMBER SIGNAL NAME

B23 RSV06

B24

B25

C1

C2

MCMRXFLCLK

MCMCLKN

DDRD27

VSS

DDRD30

VSS

DDRD22

DVDD15

DDRD13

VSS

DDRD01

DDRDQS0N

DDRCB02

DDRDQM8

VSS

DDRCE1

VSS

DDRA06

DVDD15

DDRBA0

VSS

DDRA13

DVDD15

DDRSLRATE0

RSV09

MCMRXFLDAT

MCMCLKP

DDRD28

DVDD15

DDRD29

DVDD15

DDRD23

DDRD12

DDRD14

DVDD15

DDRD02

DDRDQS0P

DDRCB00

DDRODT1

DVDD15

DDRCAS

DVDD15

DDRA00

DDRBA1

DDRA12

DVDD15

F7

F8

F9

F10

F11

F2

F3

F4

F5

F6

F12

F13

F14

F15

F16

E22

E23

E24

E25

F1

E17

E18

E19

E20

E21

E12

E13

E14

E15

E16

E7

E8

E9

E10

E11

D25

E1

E2

E3

E4

E5

E6

BALL NUMBER

D20

D21

D22

D23

D24

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DDRA15

DDRA14

DDRA10

DDRA09

DVDD18

VCNTL0

VCNTL1

MCMRXPMCLK

MCMTXFLCLK

LRESETNMIEN

DDRD25

VSS

DDRD18

DDRDQM2

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

VSS

PTV15

VSS

SIGNAL NAME

DDRA08

VSS

DDRSLRATE1

RSV21

MCMRXPMDAT

MCMTXFLDAT

DDRDQM3

DDRD24

DDRD31

DDRD19

DDRD16

DDRD08

DDRDQM1

DDRD09

DDRD04

DDRD05

VSS

VREFSSTL

DDRWE

DDRODT0

DDRA03

DDRA02

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TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

H3

H4

H5

H6

H7

G23

G24

G25

H1

H2

H8

H9

H10

H11

H12

H13

G18

G19

G20

G21

G22

G13

G14

G15

G16

G17

G8

G9

G10

G11

G12

G3

G4

G5

G6

G7

F23

F24

F25

G1

G2

BALL NUMBER

F17

F18

F19

F20

F21

F22

Table 3-42. Terminal Functions — By Ball Number (continued)

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

RSV0A

RSV0B

RSV15

RSV10

VCNTL3

MCMTXPMDAT

MCMREFCLKOUTP

NMI

RSV03

BOOTCOMPLETE

RESET

RESETSTAT

VSS

DVDD18

VSS

CVDD

VSS

CVDD

VSS

CVDD

SIGNAL NAME

DVDD15

VSS

DVDD15

AVDDA2

RSV14

RSV20

VCNTL2

MCMTXPMCLK

MCMREFCLKOUTN

EMIFCE1

HOUT

DVDD18

LRESET

CORESEL1

DVDD18

VSS

DVDD15

VSS

DVDD15

VSS

DVDD15

J25

K1

K1

K2

K3

J20

J21

J22

J23

J24

K7

K8

K9

K4

K5

K6

J15

J16

J17

J18

J19

J10

J11

J12

J13

J14

J5

J6

J7

J8

J9

H25

J1

J2

J3

J4

H20

H21

H22

H23

H24

BALL NUMBER SIGNAL NAME

H14 VSS

H15

H16

H17

H18

H19

CVDD

VSS

CVDD

VSS

DVDD18

VSS

VSS

RSV11

VSS

DVDD18

VSS

EMIFBE0

EMIFCE2

RSV02

RESETFULL

CORESEL0

DVDD18

VSS

CVDD1

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

RSV16

MCMTXN3

VSS

VSS

VSS

MCMRXN2

EMIFA00

UPPXD00 †

VSS

DVDD18

EMIFWE

EMIFCE0

VSS

DVDD18

VSS

CVDD1

L19

L20

L21

L22

L23

L14

L15

L16

L17

L18

L24

L25

M1

M1

M2

M2

L9

L10

L11

L12

L13

L4

L5

L6

L7

L8

L1

L1

L2

L2

L3

K21

K22

K23

K24

K25

K16

K17

K18

K19

K20

BALL NUMBER

K10

K11

K12

K13

K14

K15

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EMIFOE

EMIFRNW

DVDD18

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

VDDT1

VSS

MCMTXP2

VSS

MCMRXP3

VSS

EMIFA07

UPPXD07 †

EMIFA06

UPPXD06 †

SIGNAL NAME

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

VDDT1

VSS

MCMTXP3

MCMTXN2

VSS

MCMRXN3

MCMRXP2

EMIFA04

UPPXD04 †

EMIFA02

UPPXD02 †

EMIFBE1

Device Overview

59

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

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M17

M18

M19

M20

M21

M12

M13

M14

M15

M16

M22

M23

M24

M25

N1

N1

M7

M8

M9

M10

M11

BALL NUMBER

M3

M3

M4

M4

M5

M6

N12

N13

N14

N15

N16

N17

N18

N19

N20

N2

N2

N3

N4

N5

N6

N7

N8

N9

N10

N11

60

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

VDDT1

EMIFA08

UPPXD08 †

DVDD18

VSS

EMIFWAIT0

DVDD18

VSS

CVDD

VSS

CVDD

VSS

Device Overview

Table 3-42. Terminal Functions — By Ball Number (continued)

SIGNAL NAME

EMIFA01

UPPXD01 †

EMIFWAIT1

UPP2XTXCLK †

EMIFCE3

VSS

DVDD18

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

VDDT1

VDDR1

MCMTXP1

VSS

VSS

VSS

MCMRXN1

EMIFA10

UPPXD10 †

P7

P8

P9

P10

P11

P4

P4

P5

P5

P6

P12

P13

P14

P15

P16

P17

P1

P2

P2

P3

P3

BALL NUMBER SIGNAL NAME

N21 MCMTXN1

N22

N23

N24

N25

P1

MCMTXP0

VSS

MCMRXP0

MCMRXP1

EMIFA12

UPPXD12 †

EMIFA11

UPPXD11 †

EMIFA09

UPPXD09 †

EMIFA05

UPPXD05 †

EMIFA03

UPPXD03 †

VSS

DVDD18

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

R23

R23

R24

R25

R25

R19

R20

R21

R21

R22

T3

T4

T4

T1

T1

T2

R14

R15

R16

R17

R18

BALL NUMBER

R8

R9

R10

R11

R12

R13

R2

R3

R3

R4

R4

R5

R5

R6

R7

P22

P23

P24

P25

R1

R1

R2

P18

P19

P20

P21

VSS

CVDD

VSS

VSS

MCMTXN0

VSS

MCMRXN0

VSS

EMIFA17

UPP_CH0_START †

EMIFA16

UPP_CH0_CLK †

EMIFA14

UPPXD14 †

EMIFA15

UPPXD15 †

EMIFA13

UPPXD13 †

DVDD18

VSS

T15

T16

T17

T18

T19

T20

T21

T21

T22

T8

T9

T10

T11

T12

T13

T14

T5

T5

T6

T7

Copyright © 2012–2015, Texas Instruments Incorporated

EMIFA20

UPP_CH1_CLK †

VSS

DVDD18

VSS

CVDD1

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

DVDD18

VSS

GPIO12

BOOTMODE11 †

GPIO06

SIGNAL NAME

VSS

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

DVDD18

GPIO07

BOOTMODE06 †

VSS

GPIO02

BOOTMODE01 †

VSS

GPIO01

BOOTMODE00 †

EMIFA19

UPP_CH0_WAIT †

VSS

DVDD18

EMIFA18

UPP_CH0_ENABLE

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TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

U23

U23

U24

U24

U25

U20

U21

U21

U22

U22

V2

V2

V3

U25

V1

V1

U15

U16

U17

U18

U19

U10

U11

U12

U13

U14

U5

U6

U7

U8

U9

U3

U3

U4

U4

U5

U1

U1

U2

U2

BALL NUMBER

T22

T23

T23

T24

T25

T25

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD1

VSS

EMIFA23

UPP_CH1_WAIT †

EMIFD00

UPPD00 †

EMIFD01

UPPD01 †

DVDD18

VSS

CVDD1

VSS

DVDD18

GPIO11

BOOTMODE10 †

GPIO08

BOOTMODE07 †

GPIO09

BOOTMODE08 †

GPIO05

BOOTMODE04 †

GPIO03

BOOTMODE02 †

EMIFD02

UPPD02 †

EMIFD03

UPPD03 †

EMIFD04

Table 3-42. Terminal Functions — By Ball Number (continued)

SIGNAL NAME

BOOTMODE05 †

GPIO04

BOOTMODE03 †

DVDD18

GPIO00

LENDIAN †

EMIFA21

UPP_CH1_START †

EMIFA22

UPP_CH1_ENABLE

W5

W6

W7

W8

W9

W2

W3

W4

W4

W5

W10

W11

W12

W13

W14

W15

V24

V25

W1

W1

W2

V21

V22

V22

V23

V23

V17

V18

V19

V20

V21

V12

V13

V14

V15

V16

V7

V8

V9

V10

V11

BALL NUMBER SIGNAL NAME

V3 UPPD04 †

V4

V4

V5

V5

V6

EMIFD05

UPPD05 †

EMIFD07

UPPD07 †

VSS

DVDD18

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

CVDD

VSS

DVDD18

VSS

GPIO15

PCIESSMODE1 †

GPIO13

BOOTMODE12 †

GPIO10

BOOTMODE09 †

EMU00

EMU01

EMIFD06

UPPD06 †

EMIFD08

UPPD08 †

VSS

EMIFD10

UPPD10 †

EMIFD12

UPPD12 †

DVDD18

VSS

VDDT2

VSS

VDDT2

VSS

VDDT2

VSS

DVDD18

VSS

Y24

Y25

AA1

AA1

AA2

Y19

Y20

Y21

Y22

Y23

AA2

AA3

AA4

AA5

AA6

AA7

Y14

Y15

Y16

Y17

Y18

Y9

Y10

Y11

Y12

Y13

Y4

Y5

Y6

Y7

Y8

Y1

Y1

Y2

Y2

Y3

W21

W22

W23

W24

W25

BALL NUMBER

W16

W17

W18

W19

W20

W21

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VDDT2

VSS

VDDT2

VSS

DVDD18

VSS

AVDDA1

VSS

DVDD18

POR

RSV08

CLKX0

EMU18

EMU09

EMU07

EMU06

EMU05

EMIFD13

UPPD13 †

EMIFD15

UPPD15 †

VDDR3

VSS

VDDR4

VSS

RSV17

SIGNAL NAME

DVDD18

VSS

DVDD18

VSS

DVDD18

GPIO14 †

PCIESSMODE0 †

EMU08

EMU03

EMU04

EMU02

EMIFD09

UPPD09 †

EMIFD11

UPPD11 †

DVDD18

RSV13

RSV12

VSS

VDDT2

VSS

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61

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

AB10

AB11

AB12

AB13

AB13

AB14

AB14

AB15

AB15

AB16

AB17

AB17

AB18

AB19

AB20

AB21

AB5

AB6

AB7

AB8

AB9

AB1

AB1

AB2

AB3

AB4

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

BALL NUMBER

AA8

AA9

AA10

AA11

AA12

AA12

AA13

AA14

AA14

AA15

AA15

Table 3-42. Terminal Functions — By Ball Number (continued)

EMIFD14

UPPD14 †

VSS

RSV19

RIOTXN3

RIOTXP3

VSS

RIOTXN1

RIOTXP1

VSS

PCIETXP1

PCIETXN1

VSS

SPIDOUT

GPIO31 †

SPIDIN

GPIO30 †

UARTRXD

GPIO20 †

MDIO

UARTRTS

GPIO23 †

RSV05

TRST

VSS

DR0

SIGNAL NAME

VSS

VDDR2

VSS

RSV18

SPISCS0

GPIO28 †

SPICLK

SPISCS1

GPIO29 †

UARTTXD

GPIO21 †

MDCLK

SCL

SDA

SYSCLKOUT

FSX0

CLKR0

RSV01

EMU14

EMU10

EMU11

AD4

AD5

AD6

AD7

AD8

AC24

AC25

AD1

AD2

AD3

AD9

AD10

AD11

AD12

AD13

AD14

AC16

AC17

AC17

AC18

AC19

AC19

AC20

AC21

AC22

AC23

AC8

AC9

AC10

AC11

AC12

AC13

AC14

AC14

AC15

AC15

AC3

AC4

AC5

AC6

AC7

BALL NUMBER SIGNAL NAME

AB22 EMU15

AB23

AB24

AB25

AC1

AC2

DVDD18

VSS

EMU12

VSS

SGMII0TXN

SGMII0TXP

VSS

RIOTXN2

RIOTXP2

VSS

RIOTXP0

RIOTXN0

VSS

PCIETXP0

PCIETXN0

VSS

UARTRXD1

GPIO24 †

UARTTXD1

GPIO25 †

EMU17

EMU13

VSS

VSS

VSS

RIORXN3

RIORXP3

VSS

RIORXP1

RIORXN1

DVDD18

UARTCTS

GPIO22 †

RSV04

TIMO0

GPIO18 †

DVDD18

CLKS1

DX0

CLKS0

VSS

PCIERXN1

PCIERXP1

VSS

SRIOSGMIICLKP

PCIECLKP

AE17

AE18

AE19

AE20

AE20

AE21

AE21

AE22

AE23

AE24

AE25

AE8

AE9

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE16

AE3

AE4

AE5

AE6

AE7

AD23

AD24

AD25

AE1

AE2

BALL NUMBER

AD15

AD15

AD16

AD17

AD18

AD19

AD20

AD20

AD20

AD21

AD22

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RIORXP0

RIORXN0

VSS

PCIERXP0

PCIERXN0

VSS

SRIOSGMIICLKN

PCIECLKN

UARTCTS1

GPIO26 †

TDI

TMS

CORECLKN

TIMO1

GPIO19 †

TIMI1

GPIO17 †

DX1

FSX1

CLKX1

VSS

SIGNAL NAME

UARTRTS1

GPIO27 †

VSS

TCK

CORECLKP

TDO

TIMI0

GPIO16 †

PCIESSEN ‡

DR1

FSR1

CLKR1

FSR0

EMU16

VSS

SGMII0RXN

SGMII0RXP

VSS

RIORXN2

RIORXP2

VSS

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TMS320C6654

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3.10 Development and Support

3.10.1 Development Support

In case the customer would like to develop their own features and software on the C6654 device, TI offers an extensive line of development tools for the TMS320C6000™ DSP platform, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The tool's support documentation is electronically available within the Code Composer Studio™ Integrated Development Environment (IDE).

The following products support development of C6000™ DSP-based applications:

Software Development Tools:

– Code Composer Studio™ Integrated Development Environment (IDE), including Editor

C/C++/Assembly Code Generation, and Debug plus additional development tools.

– Scalable, Real-Time Foundation Software (DSP/BIOS™), which provides the basic run-time target software needed to support any DSP application.

Hardware Development Tools:

– Extended Development System (XDS™) Emulator (supports C6000™ DSP multiprocessor system debug)

– EVM (Evaluation Module)

3.10.2 Device Support

3.10.2.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,

TMP, or TMS (e.g., TMX320CMH). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).

Device development evolutionary flow:

TMX: Experimental device that is not necessarily representative of the final device's electrical specifications

TMP: Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification

TMS: Fully qualified production device

Support tool development evolutionary flow:

TMDX: Development-support product that has not yet completed Texas Instruments internal qualification testing.

TMDS: Fully qualified development-support product

TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer:

"Developmental product is intended for internal evaluation purposes."

TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.

Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

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TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, CZH), the temperature range (for example, blank is the default case temperature range), and the device speed range, in Megahertz (for example, blank is 1000 MHz [1 GHz]).

For device part numbers and further ordering information for C6654 in the CZH or GZH package type, see the TI website www.ti.com or contact your TI sales representative.

Figure 3-29

provides a legend for reading the complete device name for any C66x KeyStone device.

TMX 320 C6654

PREFIX

TMX = Experimental device

TMS = Qualified device

( ) CZH ( ) ( )

DEVICE SPEED RANGE

8 = 850 MHz

DEVICE FAMILY

320 = TMS320 DSP family

DEVICE

C66x DSP: C6654

TEMPERATURE RANGE

Blank = 0°C to +85°C (default case temperature)

A = Extended temperature range

(-40°C to +100°C)

L = Extended low temperature range

(-55°C to +100°C)

SILICON REVISION

Blank = Initial Silicon 1.0

PACKAGE TYPE

CZH = 625-pin plastic ball grid array, with Pb-free die bumps and solder balls

GZH = 625-pin plastic ball grid array

Figure 3-29. C66x DSP Device Nomenclature (including the C6654)

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TMS320C6654

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3.11 Related Documentation from Texas Instruments

These documents describe the C6654 Fixed and Floating-Point Digital Signal Processor. Copies of these documents are available on the Internet at www.ti.com.

64-bit Timer (Timer 64) for KeyStone Devices User's Guide

Bootloader for the C66x DSP User's Guide

C66x CorePac User's Guide

C66x CPU and Instruction Set Reference Guide

C66x DSP Cache User's Guide

DDR3 Design Guide for KeyStone Devices

DDR3 Memory Controller for KeyStone Devices User's Guide

DSP Power Consumption Summary for KeyStone Devices

Debug and Trace for KeyStone I Devices User's Guide

Emulation and Trace Headers Technical Reference

Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices User's Guide

External Memory Interface (EMIF16) for KeyStone Devices User's Guide

General Purpose Input/Output (GPIO) for KeyStone Devices User's Guide

Gigabit Ethernet (GbE) Subsystem for KeyStone Devices User's Guide

Hardware Design Guide for KeyStone Devices

Inter Integrated Circuit (I

2

C) for KeyStone Devices User's Guide

Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide

Memory Protection Unit (MPU) for KeyStone Devices User's Guide

Multichannel Buffered Serial Port (McBSP) for KeyStone Devices User's Guide

Multicore Navigator for KeyStone Devices User's Guide

Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide

Peripheral Component Interconnect Express (PCIe) for KeyStone Devices User's Guide

Phase Locked Loop (PLL) for KeyStone Devices User's Guide

Power Sleep Controller (PSC) for KeyStone Devices User's Guide

Semaphore2 Hardware Module for KeyStone Devices User's Guide

Serial Peripheral Interface (SPI) for KeyStone Devices User's Guide

Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User's Guide

Universal Parallel Port (uPP) for KeyStone Devices User's Guide

Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded Microprocessor Systems

Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs

Using IBIS Models for Timing Analysis

SPRUGV5

SPRUGY5

SPRUGW0

SPRUGH7

SPRUGY8

SPRABI1

SPRUGV8

SPRABL4

SPRUGZ2

SPRU655

SPRUGS5

SPRUGZ3

SPRUGV1

SPRUGV9

SPRABI2

SPRUGV3

SPRUGW4

SPRUGW5

SPRUGR9

SPRUGW7

SPRUGS6

SPRUGV2

SPRUGV4

SPRUGS3

SPRUGP2

SPRUGP1

SPRA387

SPRA753

SPRA839

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4 Device Configuration

On the C6654 device, certain device configurations like boot mode and endianess, are selected at device power-on reset. The status of the peripherals (enabled/disabled) is determined after device power-on reset.

4.1

Device Configuration at Device Reset

Table 4-1

describes the device configuration pins. The logic level is latched at power-on reset to determine the device configuration. The logic level on the device configuration pins can be set by using external pullup/pulldown resistors or by using some control device (e.g., FPGA/CPLD) to intelligently drive these pins. When using a control device, care should be taken to ensure there is no contention on the lines when the device is out of reset. The device configuration pins are sampled during power-on reset and are driven after the reset is removed. To avoid contention, the control device must stop driving the device configuration pins of the DSP. And when driving by a control device, the control device must be fully powered and out of reset itself and driving the pins before the DSP can be taken out of reset.

Also, please note that most of the device configuration pins are shared with other function pins

(LENDIAN/GPIO[0], BOOTMODE[12:0]/GPIO[13:1], PCIESSMODE[1:0]/GPIO[15:14] and

PCIESSEN/TIMI0), some time must be given following the rising edge of reset in order to drive these device configuration input pins before they assume an output state (those GPIO pins should not become outputs during boot). Another caution that needs to be noted is that systems using TIMI0 (pin shared with

PCIESSEN) as a clock input must assure that the clock itself is disabled from the input until after reset is released and a control device is no longer driving that input.

NOTE

If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the internal pullup/pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the use of an external pullup/pulldown resistor. For more detailed information on pullup/pulldown resistors and situations in which external pullup/pulldown resistors are required, see

Section 4.4

.

Table 4-1. C6654 Device Configuration Pins

CONFIGURATION PIN

LENDIAN

(1) (2)

BOOTMODE[12:0]

(1) (2)

PIN NO.

T25

R25, R3, U25,

T23, U24, T22,

R21, U22,

U23, V23,

U21, T21, V22

W21, V21

IPD/IPU

IPU

IPD

(1)

FUNCTIONAL DESCRIPTION

Device endian mode (LENDIAN).

• 0 = Device operates in big endian mode

• 1 = Device operates in little endian mode

Method of boot.

Some pins may not be used by bootloader and can be used as general purpose config pins. Refer to the Bootloader for the C66x DSP User's Guide ( SPRUGY5 ) for how to determine the device enumeration ID value.

PCIESSMODE[1:0]

PCIESSEN

(1) (2)

(1) (2)

AD20

IPD

IPD

PCIe Subsystem mode selection.

• 00 = PCIe in end point mode

• 01 = PCIe legacy end point (support for legacy INTx)

• 10 = PCIe in root complex mode

• 11 = Reserved

PCIe subsystem enable/disable.

• 0 = PCIE Subsystem is disabled

• 1 = PCIE Subsystem is enabled

(1) Internal 100-µA pulldown or pullup is provided for this terminal. In most systems, a 1-k Ω resistor can be used to oppose the IPD/IPU.

For more detailed information on pulldown/pullup resistors and situations in which external pulldown/pullup resistors are required, see

Section 4.4

.

(2) These signal names are the secondary functions of these pins.

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4.2

Peripheral Selection After Device Reset

Several of the peripherals on the C6654 are controlled by the Power Sleep Controller (PSC). By default, the PCIe is held in reset and clock-gated. The memory in this module is also in a low-leakage sleep mode.

Software is required to turn this memory on. The software enables the module (turns on clocks and deasserts reset) before this module can be used.

If one of the above modules is used in the selected ROM boot mode, the ROM code will automatically enable the module.

All other modules come up enabled by default and there is no special software sequence to enable. For more detailed information on the PSC usage, see the Power Sleep Controller (PSC) for KeyStone Devices

User's Guide ( SPRUGV4 ).

4.3

Device State Control Registers

The C6654 device has a set of registers that are used to provide the status or configure certain parts of its peripherals. These registers are shown in

Table 4-2 .

Table 4-2. Device State Control Registers

ADDRESS

START

0x02620000

0x02620008

0x02620018

0x0262001C

0x02620020

0x02620024

0x02620038

0x0262003C

0x02620040

0x02620044

0x02620048

0x0262004C

0x02620050

0x02620054

0x02620058

0x0262005C

0x02620060

0x026200E0

0x02620110

0x02620118

0x02620130

0x02620134

0x02620138

0x0262013C

0x02620140

0x02620144

0x02620148

0x0262014C

0x02620150

0x02620154

ADDRESS END SIZE FIELD

0x02620007

0x02620017

8B

16B

Reserved

Reserved

0x0262001B

0x0262001F

4B

4B

JTAGID

Reserved

0x02620023

0x02620037

0x0262003B

0x0262003F

0x02620043

4B

20B

4B

4B

4B

DEVSTAT

Reserved

KICK0

KICK1

DSP_BOOT_ADDR0

0x02620047

0x0262004B

0x0262004F

0x02620053

0x02620057

0x0262005B

0x0262005F

0x026200DF

0x0262010F

0x02620117

4B

4B

4B

4B

4B

4B

4B

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

128B Reserved

48B

8B

Reserved

MACID

0x0262012F

0x02620133

0x02620137

0x0262013B

0x0262013F

0x02620143

0x02620147

0x0262014B

0x0262014F

0x02620153

0x02620157

4B

4B

4B

4B

4B

4B

24B

4B

4B

4B

4B

Reserved

LRSTNMIPINSTAT_CLR

RESET_STAT_CLR

Reserved

BOOTCOMPLETE

Reserved

RESET_STAT

LRSTNMIPINSTAT

DEVCFG

PWRSTATECTL

Reserved

DESCRIPTION

See

Section 4.3.3

See

Section 4.3.1

See

Section 4.3.4

The boot address for C66x DSP CorePac0

Reserved

See

Section 8.17

See

Section 4.3.6

See

Section 4.3.8

See

Section 4.3.9

See

Section 4.3.7

See

Section 4.3.5

See

Section 4.3.2

See

Section 4.3.10

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Table 4-2. Device State Control Registers (continued)

0x026201B8

0x026201BC

0x026201C0

0x026201C4

0x026201C8

0x026201CC

0x026201D0

0x02620200

0x02620204

0x02620208

0x0262020C

0x02620210

0x02620214

0x02620218

0x0262021C

0x02620220

0x02620240

0x02620244

0x02620248

0x0262024C

ADDRESS

START

0x02620158

0x0262015C

0x02620160

0x02620164

0x02620168

0x0262016C

0x02620170

0x02620184

0x02620190

0x02620194

0x02620198

0x0262019C

0x026201A0

0x026201A4

0x026201A8

0x026201AC

0x026201B0

0x026201B4

0x02620250

0x02620254

0x02620258

0x0262025C

0x02620260

0x0262027C

0x02620280

0x02620284

0x02620288

68

Device Configuration

0x026201BB

0x026201BF

0x026201C3

0x026201C7

0x026201CB

0x026201CF

0x026201FF

0x02620203

0x02620207

0x0262020B

0x0262020F

0x02620213

0x02620217

0x0262021B

0x0262021F

0x0262023F

0x02620243

0x02620247

0x0262024B

0x0262024F

ADDRESS END SIZE FIELD

0x0262015B 4B SMGII_SERDES_STS

0x0262015F

0x02620163

4B

4B

PCIE_SERDES_STS

Reserved

0x02620167

0x0262016B

0x0262016F

0x02620183

0x0262018F

4B

4B

4B

20B

12B

Reserved

Reserved

UPP_CLOCK

Reserved

Reserved

0x02620193

0x02620197

0x0262019B

0x0262019F

0x026201A3

0x026201A7

0x026201AB

0x026201AF

0x026201B3

0x026201B7

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

0x02620253

0x02620257

0x0262025B

0x0262025F

0x0262027B

0x0262027F

0x02620283

0x02620287

0x0262028B

4B

4B

4B

4B

4B

4B

48B

4B

4B

4B

4B

4B

4B

4B

4B

32B

4B

4B

4B

4B

4B

4B

4B

4B

28B

4B

4B

4B

4B

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

NMIGR0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IPCGR0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IPCGRH

IPCAR0

Reserved

Reserved

DESCRIPTION

See

See

See

See

See

See

Section 3.11

Section 4.3.22

Section 4.3.11

Section 4.3.12

Section 4.3.14

Section 4.3.13

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ADDRESS

START

0x0262028C

0x02620290

0x02620294

0x02620298

0x0262029C

0x026202A0

0x026202BC

0x026202C0

0x02620300

0x02620304

0x02620308

0x0262030C

0x02620310

0x02620314

0x02620318

0x0262031C

0x02620320

0x02620324

0x02620328

0x0262032C

0x02620330

0x02620334

0x02620338

0x0262033C

0x02620340

0x02620344

0x02620348

0x0262034C

0x02620350

0x02620354

0x02620358

0x0262035C

0x02620360

0x02620364

0x02620368

0x0262036C

0x02620370

0x02620374

0x02620378

0x0262037C

0x02620380

0x02620384

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

Table 4-2. Device State Control Registers (continued)

DESCRIPTION ADDRESS END SIZE FIELD

0x0262028F 4B Reserved

0x02620293

0x02620297

4B

4B

Reserved

Reserved

0x0262029B

0x0262029F

0x026202BB

4B

4B

28B

Reserved

Reserved

Reserved

0x026202BF

0x026202FF

0x02620303

0x02620307

4B

64B

4B

4B

IPCARH

Reserved

TINPSEL

TOUTPSEL

0x0262030B

0x0262030F

0x02620313

0x02620317

0x0262031B

0x0262031F

0x02620323

0x02620327

0x0262032B

0x0262032F

0x02620333

0x02620337

0x0262033B

0x0262033F

0x02620343

0x02620347

0x0262034B

0x0262034F

0x02620353

0x02620357

0x0262035B

0x0262035F

0x02620363

0x02620367

0x0262036B

0x0262036F

0x02620373

0x02620377

0x0262037B

0x0262037F

0x02620383

0x02620387

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

8B

4B

4B

4B

4B

4B

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

RSTMUX0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

MAINPLLCTL0

MAINPLLCTL1

DDR3PLLCTL0

DDR3PLLCTL1

Reserved

Reserved

SGMII_SERDES_CFGPLL

SGMII_SERDES_CFGRX0

SGMII_SERDES_CFGTX0

Reserved

Reserved

Reserved

PCIE_SERDES_CFGPLL

Reserved

See

Section 4.3.15

See

Section 4.3.16

See

Section 4.3.17

See

Section 4.3.18

See

Section 8.5

See

Section 8.6

See

Section 3.11

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ADDRESS

START

0x026203B4

0x026203B8

0x026203BC

0x026203C0

0x026203C4

0x026203C8

0x026203CC

0x026203D0

0x026203D4

0x026203D8

0x026203DC

0x026203F8

0x026203FC

0x02620400

0x02620404

0x02620468

0x02620580

0x02620584

0x02620588

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

Table 4-2. Device State Control Registers (continued)

DESCRIPTION ADDRESS END SIZE FIELD

0x026203B7 4B Reserved

0x026203BB

0x026203BF

4B

4B

Reserved

Reserved

0x026203C3

0x026203C7

0x026203CB

0x026203CF

0x026203D3

4B

4B

4B

4B

4B

Reserved

Reserved

Reserved

Reserved

Reserved

0x026203D7

0x026203DB

0x026203F7

0x026203FB

0x026203FF

0x02620403

0x02620467

0x0262057f

0x02620583

0x02620587

0x0262058B

4B

4B

28B

4B

4B

4B

100B Reserved

280B Reserved

4B

4B

4B

Reserved

Reserved

Reserved

DEVSPEED

Reserved

PKTDMA_PRI_ALLOC

PIN_CONTROL_0

PIN_CONTROL_1

EMAC_UPP_PRI_ALLOC

See

Section 4.3.19

See

Section 5.4

See

Section 4.3.20

See

Section 4.3.21

See

Section 5.4

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4.3.1

Device Status Register

The Device Status Register depicts the device configuration selected upon a power-on reset by either the

POR or RESETFULL pin. Once set, these bits will remain set until the next power-on reset. The Device

Status Register is shown in

Figure 4-1

and described in

Table 4-3 .

31

Reserved

17

Figure 4-1. Device Status Register

16

PCIESSEN

15 14

PCIESSMODE

[1:0]

R/W-xx

13

BOOTMODE[12:0]

R/W-xxxxxxxxxxxx R-0 R-x

Legend: R = Read only; RW = Read/Write; -n = value after reset

(1) x indicates the bootstrap value latched via the external pin

1 0

LENDIAN

R-x

(1)

Table 4-3. Device Status Register Field Descriptions

Bit Field

31-17 Reserved

Description

Reserved. Read only, writes have no effect.

16 PCIESSEN PCIe module enable

• 0 = PCIe module disabled

• 1 = PCIe module enabled

15-14 PCIESSMODE[1:0] PCIe Mode selection pins

• 00b = PCIe in End-point mode

• 01b = PCIe in Legacy End-point mode (support for legacy INTx)

• 10b = PCIe in Root complex mode

• 11b = Reserved

13-1 BOOTMODE[12:0] Determines the bootmode configured for the device. For more information on bootmode, refer to

Section 3.5

and see the Bootloader for the C66x DSP User's Guide ( SPRUGY5 )

0 LENDIAN Device Endian mode (LENDIAN) — Shows the status of whether the system is operating in Big Endian mode or Little Endian mode.

• 0 = System is operating in Big Endian mode

• 1 = System is operating in Little Endian mode

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4.3.2

Device Configuration Register

The Device Configuration Register is one-time writeable through software. The register is reset on all hard resets and is locked after the first write. The Device Configuration Register is shown in

Figure 4-2

and described in

Table 4-4

.

Figure 4-2. Device Configuration Register (DEVCFG)

1 31

Reserved

R-0

Legend: R = Read only; RW = Read/Write; -n = value after reset

0

SYSCLKOUTEN

R/W-1

Table 4-4. Device Configuration Register Field Descriptions

Bit Field

31-1 Reserved

0

Description

Reserved. Read only, writes have no effect.

SYSCLKOUTEN SYSCLKOUT Enable

• 0 = No clock output

• 1 = Clock output enabled (default)

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4.3.3

JTAG ID (JTAGID) Register Description

The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the device, the JTAG ID register resides at address location 0x0262 0018. The JTAG ID Register is shown in

Figure 4-3

and described in

Table 4-5

.

Figure 4-3. JTAG ID (JTAGID) Register

12 31 28 27

VARIANT

R-xxxxb

PART NUMBER

R-1011 1001 0111 1010b

Legend: RW = Read/Write; R = Read only; -n = value after reset

11

MANUFACTURER

0000 0010 111b

1 0

LSB

R-1

Table 4-5. JTAG ID Register Field Descriptions

Bit Field

31-28 VARIANT

Value

xxxxb

27-12 PART NUMBER 1011 1001 0111 1010b

11-1 MANUFACTURER 0000 0010 111b

0 LSB 1b

Description

Variant (4-Bit) value.

Part Number for boundary scan

Manufacturer

This bit is read as a 1 for C6654

NOTE

The value of the VARIANT and PART NUMBER fields depend on the silicon revision. See the Silicon Errata for details.

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4.3.4

Kicker Mechanism (KICK0 and KICK1) Register

The Bootcfg module contains a kicker mechanism to prevent any spurious writes from changing any of the

Bootcfg MMR values. When the kicker is locked (which it is initially after power on reset), none of the

Bootcfg MMRs are writable (they are only readable). On the C6654, the exceptions to this are the IPC registers such as IPCGRx and IPCARx. These registers are not protected by the kicker mechanism. This mechanism requires two MMR writes to the KICK0 and KICK1 registers with exact data values before the kicker lock mechanism is un-locked. See

Table 4-2

for the address location. Once released, then all the

Bootcfg MMRs having write permissions are writable (the read only MMRs are still read only). The first

KICK0 data is 0x83e70b13. The second KICK1 data is 0x95a4f1e0. Writing any other data value to either of these kick MMRs will lock the kicker mechanism and block any writes to Bootcfg MMRs. To ensure protection of all Bootcfg MMRs, software must always re-lock the kicker mechanism after completing the

MMR writes.

4.3.5

LRESETNMI PIN Status (LRSTNMIPINSTAT) Register

The LRSTNMIPINSTAT Register is created in Boot Configuration to latch the status of LRESET and NMI based on CORESEL. The LRESETNMI PIN Status Register is shown and described in the following tables.

Figure 4-4. LRESETNMI PIN Status Register (LRSTNMIPINSTAT)

15 2 31

Reserved

R, +0000 0000

Legend: R = Read only; -n = value after reset;

18 17

Reserved

R-0

16

NMI0

WC,+0

Reserved

R, +0000 0000

1

Reserved

WC,+0

0

LR0

WC,+0

1

0

Bit Field

31-18 Reserved

17 Reserved

16 NMI0

15-2 Reserved

Reserved

LR0

Table 4-6. LRESETNMI PIN Status Register (LRSTNMIPINSTAT) Field Descriptions

Description

Reserved

Reserved

CorePac0 in NMI

Reserved

Reserved

CorePac0 in Local Reset

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4.3.6

LRESETNMI PIN Status Clear (LRSTNMIPINSTAT_CLR) Register

The LRSTNMIPINSTAT_CLR Register is used to clear the status of LRESET and NMI based on

CORESEL. The LRESETNMI PIN Status Clear Register is shown and described in the following tables.

Figure 4-5. LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR)

15 2 31 18 17

Reserved

R, +0000 0000

Reserved

WC,+0

Legend: R = Read only; -n = value after reset; WC = Write 1 to Clear

16

NMI0

WC,+0

Reserved

R, +0000 0000

1

Reserved

WC,+0

0

LR0

WC,+0

Table 4-7. LRESETNMI PIN Status Clear Register (LRSTNMIPINSTAT_CLR) Field Descriptions

Bit Field

31-18 Reserved

17

16

Reserved

NMI0

15-2 Reserved

1 Reserved

0 LR0

Description

Reserved

Reserved

CorePac0 in NMI Clear

Reserved

Reserved

CorePac0 in Local Reset Clear

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4.3.7

Reset Status (RESET_STAT) Register

The reset status register (RESET_STAT) captures the status of Local reset (LRx) for each of the cores and also the global device reset (GR). Software can use this information to take different device initialization steps, if desired.

• In case of Local reset: The LRx bits are written as 1 and GR bit is written as 0 only when the CorePac receives a local reset without receiving a global reset.

• In case of Global reset: The LRx bits are written as 0 and GR bit is written as 1 only when a global reset is asserted.

The Reset Status Register is shown and described in the following tables.

Figure 4-6. Reset Status Register (RESET_STAT)

2 31

GR

30

R, +1

Legend: R = Read only; -n = value after reset

Reserved

R, + 000 0000 0000 0000 0000 0000

1

Reserved

R,+0

0

LR0

R,+0

Bit

31

Field

GR

30-2 Reserved

1 Reserved

0 LR0

Table 4-8. Reset Status Register (RESET_STAT) Field Descriptions

Description

Global reset status

• 0 = Device has not received a global reset.

• 1 = Device received a global reset.

Reserved.

Reserved.

CorePac0 reset status

• 0 = CorePac0 has not received a local reset.

• 1 = CorePac0 received a local reset.

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4.3.8

Reset Status Clear (RESET_STAT_CLR) Register

The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR register. The Reset Status Clear Register is shown and described in the following tables.

Figure 4-7. Reset Status Clear Register (RESET_STAT_CLR)

2 31

GR

RW, +0

30

Reserved

R, + 000 0000 0000 0000 0000 0000

Legend: R = Read only; RW = Read/Write; -n = value after reset

1

Reserved

RW,+0

0

LR0

RW,+0

Bit

31

Field

GR

30-2 Reserved

1

0

Reserved

LR0

Table 4-9. Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions

Description

Global reset clear bit

• 0 = Writing a 0 has no effect.

• 1 = Writing a 1 to the GR bit clears the corresponding bit in the RESET_STAT register.

Reserved.

Reserved.

CorePac0 reset clear bit

• 0 = Writing a 0 has no effect.

• 1 = Writing a 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.

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4.3.9

Boot Complete (BOOTCOMPLETE) Register

The BOOTCOMPLETE register controls the BOOTCOMPLETE pin status. The purpose is to indicate the completion of the ROM booting process. The Boot Complete Register is shown and described in the following tables.

Figure 4-8. Boot Complete Register (BOOTCOMPLETE)

2 31

Reserved

R, + 0000 0000 0000 0000 0000 0000

Legend: R = Read only; RW = Read/Write; -n = value after reset

1

Reserved

RW,+0

0

BC0

RW,+0

1

0

Bit Field

31-2 Reserved

Reserved

BC0

Table 4-10. Boot Complete Register (BOOTCOMPLETE) Field Descriptions

Description

Reserved.

Reserved

CorePac0 boot status

• 0 = CorePac0 boot NOT complete

• 1 = CorePac0 boot complete

The BCx bit indicates the boot complete status of the corresponding core. All BCx bits will be sticky bits — that is they can be set only once by the software after device reset and they will be cleared to 0 on all device resets.

Boot ROM code will be implemented such that each core will set its corresponding BCx bit immediately before branching to the predefined location in memory.

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4.3.10 Power State Control (PWRSTATECTL) Register

The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code reads this register to differentiate between the various power saving modes. This register is cleared only by POR and will survive all other device resets. See the Hardware Design Guide for KeyStone Devices

( SPRABI2 ) for more information. The Power State Control Register is shown in

Figure 4-9

and described in

Table 4-11

.

31

Figure 4-9. Power State Control Register (PWRSTATECTL)

GENERAL_PURPOSE

RW, +0000 0000 0000 0000 0000 0000 0000 0

Legend: RW = Read/Write; -n = value after reset

3 2

HIBERNATION

_MODE

RW,+0

1

HIBERNATION

RW,+0

0

STANDBY

RW,+0

0 STANDBY

Table 4-11. Power State Control Register (PWRSTATECTL) Field Descriptions

Bit Field

31-3 GENERAL_PURPOSE

2

1

HIBERNATION_MODE

HIBERNATION

Description

Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the

C66x DSP User's Guide ( SPRUGY8 ).

Indicates whether the device is in hibernation mode 1 or mode 2.

• 0 = Hibernation mode 1

• 1 = Hibernation mode 2

Indicates whether the device is in hibernation mode or not.

• 0 = Not in hibernation mode

• 1 = Hibernation mode

Indicates whether the device is in standby mode or not.

• 0 = Not in standby mode

• 1 = Standby mode

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4.3.11 NMI Event Generation to CorePac (NMIGRx) Register

NMIGRx registers are used for generating NMI events to the CorePac. The C6654 has only NMIGR0, which generates an NMI event to the CorePac. Writing a 1 to the NMIG field generates an NMI pulse.

Writing a 0 has no effect and reads return 0 and have no other effect. The NMI Event Generation to

CorePac Register is shown in

Figure 4-10

and described in

Table 4-12

.

Figure 4-10. NMI Generation Register (NMIGRx)

31

Reserved

R, +0000 0000 0000 0000 0000 0000 0000 000

Legend: RW = Read/Write; -n = value after reset

1 0

NMIG

RW,+0

Bit Field

31-1 Reserved

0 NMIG

Table 4-12. NMI Generation Register (NMIGRx) Field Descriptions

Description

Reserved

NMI pulse generation.

Reads return 0

Writes:

• 0 = No effect

• 1 = Sends an NMI pulse to the CorePac

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4.3.12 IPC Generation (IPCGRx) Registers

IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.

The C6654 has only IPCGR0. This register can be used by external hosts to generate interrupts to the

CorePac. A write of 1 to the IPCG field of the IPCGRx register will generate an interrupt pulse to the

CorePac.

This register also provides a Source ID facility by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are given in the following tables. Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to

BOOTCFG module space can write to these registers. The IPC Generation Register is shown in

Figure 4-

11

and described in

Table 4-13

.

Figure 4-11. IPC Generation Registers (IPCGRx)

31 30 29 28

SRCS SRCS SRCS SRCS

27 26 25 24

27

SRCS23 – SRCS4

RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field)

Legend: R = Read only; RW = Read/Write; -n = value after reset

8 7 6 5 4

SRCS3 SRCS2 SRCS1 SRCS0

RW +0 RW +0 RW +0 RW +0

3

Reserved

1

R, +000

0

IPCG

RW +0

Bit Field

31-4 SRCSx

3-1

0

Reserved

IPCG

Table 4-13. IPC Generation Registers (IPCGRx) Field Descriptions

Description

Interrupt source indication.

Reads return current value of internal register bit.

Writes:

• 0 = No effect

• 1 = Sets both SRCSx and the corresponding SRCCx.

Reserved

Inter-DSP interrupt generation.

Reads return 0.

Writes:

• 0 = No effect

• 1 = Creates an Inter-DSP interrupt.

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4.3.13 IPC Acknowledgement (IPCARx) Registers

IPCARx are the IPC interrupt-acknowledgement registers to facilitate inter-CorePac core interrupts.

The C6654 has only IPCAR0. This register also provides a Source ID facility by which up to 28 different sources of interrupts can be identified. Allocation of source bits to source processor and meaning is entirely based on software convention. The register field descriptions are shown in the following tables.

Virtually anything can be a source for these registers as this is completely controlled by software. Any master that has access to BOOTCFG module space can write to these registers. The IPC

Acknowledgement Register is shown in

Figure 4-12

and described in

Table 4-14

.

Figure 4-12. IPC Acknowledgement Registers (IPCARx)

31 30 29 28

SRCC SRCC SRCC SRCC

27 26 25 24

27

SRCC23 – SRCC4

RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field)

Legend: R = Read only; RW = Read/Write; -n = value after reset

8 7 6 5 4

SRCC3 SRCC2 SRCC1 SRCC0

RW +0 RW +0 RW +0 RW +0

3

Reserved

R, +0000

0

Bit Field

31-4 SRCCx

3-0 Reserved

Table 4-14. IPC Acknowledgement Registers (IPCARx) Field Descriptions

Description

Interrupt source acknowledgement.

Reads return current value of internal register bit.

Writes:

• 0 = No effect

• 1 = Clears both SRCCx and the corresponding SRCSx

Reserved

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4.3.14 IPC Generation Host (IPCGRH) Register

The IPCGRH register facilitates interrupts to external hosts. Operation and use of the IPCGRH register is the same as for other IPCGR registers. The interrupt output pulse created by the IPCGRH register appears on device pin HOUT.

The host interrupt output pulse should be stretched. It should be asserted for 4 bootcfg clock cycles

(CPU/6) followed by a deassertion of 4 bootcfg clock cycles. Generating the pulse will result in 8 CPU/6 cycle pulse blocking window. Write to IPCGRH with IPCG bit (bit 0) set will only generate a pulse if they are beyond 8 CPU/6 cycle period. The IPC Generation Host Register is shown in

Figure 4-13

and described in

Table 4-15 .

Figure 4-13. IPC Generation Registers (IPCGRH)

31 30 29 28

SRCS SRCS SRCS SRCS

27 26 25 24

27

SRCS23 – SRCS4

RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field)

Legend: R = Read only; RW = Read/Write; -n = value after reset

8 7 6 5 4

SRCS3 SRCS2 SRCS1 SRCS0

RW +0 RW +0 RW +0 RW +0

3

Reserved

1

R, +000

0

IPCG

RW +0

Bit Field

31-4 SRCSx

3-1

0

Reserved

IPCG

Table 4-15. IPC Generation Registers (IPCGRH) Field Descriptions

Description

Interrupt source indication.

Reads return current value of internal register bit.

Writes:

• 0 = No effect

• 1 = Sets both SRCSx and the corresponding SRCCx.

Reserved

Host interrupt generation.

Reads return 0.

Writes:

• 0 = No effect

• 1 = Creates an interrupt pulse on device pin (host interrupt/event output in HOUT pin)

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4.3.15 IPC Acknowledgement Host (IPCARH) Register

IPCARH registers are provided to facilitate host DSP interrupt. Operation and use of IPCARH is the same as other IPCAR registers. The IPC Acknowledgement Host Register is shown in

Figure 4-14

and described in

Table 4-16 .

Figure 4-14. IPC Acknowledgement Register (IPCARH)

31 30 29 28

SRCC SRCC SRCC SRCC

27 26 25 24

27

SRCC23 – SRCC4

RW +0 RW +0 RW +0 RW +0 RW +0 (per bit field)

Legend: R = Read only; RW = Read/Write; -n = value after reset

8 7 6 5 4

SRCC3 SRCC2 SRCC1 SRCC0

RW +0 RW +0 RW +0 RW +0

3

Reserved

R, +0000

0

Bit Field

31-4 SRCCx

3-0 Reserved

Table 4-16. IPC Acknowledgement Register (IPCARH) Field Descriptions

Description

Interrupt source acknowledgement.

Reads return current value of internal register bit.

Writes:

• 0 = No effect

• 1 = Clears both SRCCx and the corresponding SRCSx

Reserved

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4.3.16 Timer Input Selection Register (TINPSEL)

Timer input selection is handled within the control register TINPSEL. The Timer Input Selection Register is shown in

Figure 4-15

and described in

Table 4-17 .

Figure 4-15. Timer Input Selection Register (TINPSEL)

31 16

Reserved

R, +1010 1010 1010 1010

15

RW,

+1

14

RW,

+0

13

RW,

+1

12

RW,

+0

11

RW,

+1

10

RW,

+0

9

RW,

+1

8

RW,

Legend: R = Read only; RW = Read/Write; -n = value after reset

+0

7 6 5 4 3 2 1 0

TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL TINPH TINPL

SEL7 SEL7 SEL6 SEL6 SEL5 SEL5 SEL4 SEL4 SEL3 SEL3 SEL2 SEL2 SEL1 SEL1 SEL0 SEL0

RW,

+1

RW,

+0

RW,

+1

RW,

+0

RW,

+1

RW,

+0

RW,

+1

RW,

+0

Bit Field

31-16 Reserved

15 TINPHSEL7

14

13

12

11

10

9

8

7

6

5

TINPLSEL7

TINPHSEL6

TINPLSEL6

TINPHSEL5

TINPLSEL5

TINPHSEL4

TINPLSEL4

TINPHSEL3

TINPLSEL3

TINPHSEL2

Table 4-17. Timer Input Selection Field Description (TINPSEL)

Description

• Reserved

Input select for TIMER7 high.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER7 low.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER6 high.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER6 low.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER5 high.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER5 low.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER4 high.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER4 low.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER3 high.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER3 low.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER2 high.

• 0 = TIMI0

• 1 = TIMI1

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Bit

4

3

2

1

0

Field

TINPLSEL2

TINPHSEL1

TINPLSEL1

TINPHSEL0

TINPLSEL0

Table 4-17. Timer Input Selection Field Description (TINPSEL) (continued)

Description

Input select for TIMER2 low.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER1 high.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER1 low.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER0 high.

• 0 = TIMI0

• 1 = TIMI1

Input select for TIMER0 low.

• 0 = TIMI0

• 1 = TIMI1

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4.3.17 Timer Output Selection Register (TOUTPSEL)

The timer output selection is handled within the control register TOUTSEL. The Timer Output Selection

Register is shown in

Figure 4-16

and described in

Table 4-18

.

Figure 4-16. Timer Output Selection Register (TOUTPSEL)

10 9 5 31

Reserved

R,+000000000000000000000000

Legend: R = Read only; RW = Read/Write; -n = value after reset

TOUTPSEL1

RW,+00001

4

TOUTPSEL0

RW,+00000

0

Bit Field

31-10 Reserved

9-5 TOUTPSEL1

4-0 TOUTPSEL0

Table 4-18. Timer Output Selection Field Description (TOUTPSEL)

Description

Reserved

Output select for TIMO1

• 0x0: TOUTL0

• 0x1: TOUTH0

• 0x2: TOUTL1

• 0x3: TOUTH1

• 0x4: TOUTL2

• 0x5: TOUTH2

• 0x6: TOUTL3

• 0x7: TOUTH3

• 0x8: TOUTL4

Output select for TIMO0

• 0x0: TOUTL0

• 0x1: TOUTH0

• 0x2: TOUTL1

• 0x3: TOUTH1

• 0x4: TOUTL2

• 0x5: TOUTH2

• 0x6: TOUTL3

• 0x7: TOUTH3

• 0x8: TOUTL4

• 0x9: TOUTH4

• 0xA: TOUTL5

• 0xB: TOUTH5

• 0xC: TOUTL6

• 0xD: TOUTH6

• 0xE: TOUTL7

• 0xF: TOUTH7

• 0x10 to 0x1F: Reserved

• 0x9: TOUTH4

• 0xA: TOUTL5

• 0xB: TOUTH5

• 0xC: TOUTL6

• 0xD: TOUTH6

• 0xE: TOUTL7

• 0xF: TOUTH7

• 0x10 to 0x1F: Reserved

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4.3.18 Reset Mux (RSTMUXx) Register

The software controls the Reset Mux block through the reset multiplex registers using RSTMUX0. This register islocated in Bootcfg memory space. The Reset Mux Register is shown in

Figure 4-17

and described in

Table 4-19 .

Figure 4-17. Reset Mux Register RSTMUXx

31 10

Reserved

R, +0000 0000 0000 0000 0000

00

9

EVTSTATCLR

RC, +0

8

Reserved

R, +0

7

DELAY

5

RW, +100

4

EVTSTAT

R, +0

Legend: R = Read only; RW = Read/Write; -n = value after reset; RC = Read only and write 1 to clear

3 1

OMODE

RW, +000

0

LOCK

RW, +0

Table 4-19. Reset Mux Register Field Descriptions

Bit Field

31-10 Reserved

9

8

7-5

Description

Reserved

EVTSTATCLR Clear event status

• 0 = Writing 0 has no effect

• 1 = Writing 1 clears the EVTSTAT bit

Reserved

DELAY

Reserved

Delay cycles between NMI & local reset

• 000b = 256 CPU/6 cycles delay between NMI & local reset, when OMODE = 100b

• 001b = 512 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

• 010b = 1024 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

• 011b = 2048 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

• 100b = 4096 CPU/6 cycles delay between NMI & local reset, when OMODE=100b (Default)

• 101b = 8192 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

• 110b = 16384 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

• 111b = 32768 CPU/6 cycles delay between NMI & local reset, when OMODE=100b

4

3-1

0

EVTSTAT

OMODE

LOCK

Event status.

• 0 = No event received (Default)

• 1 = WD timer event received by Reset Mux block

Timer event operation mode

• 000b = WD timer event input to the reset mux block does not cause any output event (default)

• 001b = Reserved

• 010b = WD timer event input to the reset mux block causes local reset input to CorePac

• 011b = WD timer event input to the reset mux block causes NMI input to CorePac

• 100b = WD timer event input to the reset mux block causes NMI input followed by local reset input to

CorePac. Delay between NMI and local reset is set in DELAY bit field.

• 101b = WD timer event input to the reset mux block causes device reset to C6654

• 110b = Reserved

• 111b = Reserved

Lock register fields

• 0 = Register fields are not locked (default)

• 1 = Register fields are locked until the next timer reset

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4.3.19 Device Speed (DEVSPEED) Register

The Device Speed Register indicates the device speed grade. The Device Speed Register is shown in

Figure 4-18

and described in

Table 4-20 .

Figure 4-18. Device Speed Register (DEVSPEED)

31

Reserved

R-n

30

DEVSPEED

R-n

23 22

Legend: R = Read only; RW = Read/Write; -n = value after reset

Reserved

R-n

0

Bit

31

Field

Reserved

30-23 DEVSPEED

22-0 Reserved

Table 4-20. Device Speed Register Field Descriptions

Description

Reserved. Read only

Indicates the speed of the device (Read Only)

• 1xxx xxxxb = 850 MHz

• 01xx xxxxb = Reserved

• 001x xxxxb = Reserved

• 0001 xxxxb = Reserved

• 0000 1xxxb = Reserved

• 0000 01xxb = Reserved

• 0000 001xb = Reserved

• 0000 0001b = 850 MHz

• 0000 0000b = 850 MHz

Reserved. Read only

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4.3.20 Pin Control 0 (PIN_CONTROL_0) Register

The Pin Control 0 Register controls the pin muxing between GPIO[16:31] and TIMER / UART / SPI pins.

The Pin Control 0 Register is shown in

Figure 4-19

and described in

Table 4-21 .

Figure 4-19. Pin Control 0 Register (PIN_CONTROL_0)

31 30 29 28 27 26 25 24

GPIO31_SPID GPIO30_SPIDI GPIO29_SPIC GPIO28_SPIC GPIO27_UART GPIO26_UART GPIO25_UART GPIO24_UART

OUT_MUX N_MUX S1_MUX S0_MUX RTS1_MUX CTS1_MUX TX1_MUX RX1_MUX

RW-0

23

RW-0

22

RW-0

21

RW-0

20

RW-0

19

RW-0

18

RW-0

17

RW-0

16

GPIO23_UART GPIO22_UART GPIO21_UART GPIO20_UART GPIO19_TIMO GPIO18_TIMO GPIO17_TIMI1 GPIO16_TIMI0

RTS0_MUX CTS0_MUX TX0_MUX RX0_MUX 1_MUX 0_MUX _MUX _MUX

RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

15 0

Reserved

R-0

Legend: R = Read only; RW = Read/Write; -n = value after reset

Bit Field

31 GPIO31_SPIDOUT_MUX

30

29

28

27

26

25

24

23

22

21

GPIO30_SPIDIN_MUX

GPIO29_SPICS1_MUX

GPIO28_SPICS0_MUX

GPIO27_UARTRTS1_MUX

GPIO26_UARTCTS1_MUX

GPIO25_UARTTX1_MUX

GPIO24_UARTRX1_MUX

GPIO23_UARTRTS0_MUX

GPIO22_UARTCTS0_MUX

GPIO21_UARTTX0_MUX

Table 4-21. Pin Control 0 Register Field Descriptions

Description

SPI or GPIO mux control

• 0 = SPIDOUT pin enabled

• 1 = GPIO31 pin enabled

SPI or GPIO mux control

• 0 = SPIDIN pin enabled

• 1 = GPIO30 pin enabled

SPI or GPIO mux control

• 0 = SPICS1 pin enabled

• 1 = GPIO29 pin enabled

SPI or GPIO mux control

• 0 = SPICS0 pin enabled

• 1 = GPIO28 pin enabled

UART or GPIO mux control

• 0 = UARTRTS1 pin enabled

• 1 = GPIO27 pin enabled

UART or GPIO mux control

• 0 = UARTCTS1 pin enabled

• 1 = GPIO26 pin enabled

UART or GPIO mux control

• 0 = UARTTX1 pin enabled

• 1 = GPIO25 pin enabled

UART or GPIO mux control

• 0 = UARTRX1 pin enabled

• 1 = GPIO24 pin enabled

UART or GPIO mux control

• 0 = UARTRTS0 pin enabled

• 1 = GPIO23 pin enabled

UART or GPIO mux control

• 0 = UARTCTS0 pin enabled

• 1 = GPIO22 pin enabled

UART or GPIO mux control

• 0 = UARTTX0 pin enabled

• 1 = GPIO21 pin enabled

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15-0 Reserved

Table 4-21. Pin Control 0 Register Field Descriptions (continued)

Bit Field

20 GPIO20_UARTRX0_MUX

19

18

17

16

GPIO19_TIMO1_MUX

GPIO18_TIMO0_MUX

GPIO17_TIMI1_MUX

GPIO16_TIMI0_MUX

Description

UART or GPIO mux control

• 0 = UARTRX0 pin enabled

• 1 = GPIO20 pin enabled

TIMER or GPIO mux control

• 0 = TIMO1 pin enabled

• 1 = GPIO19 pin enabled

TIMER or GPIO mux control

• 0 = TIMO0 pin enabled

• 1 = GPIO18 pin enabled

TIMER or GPIO mux control

• 0 = TIMI1 pin enabled

• 1 = GPIO17 pin enabled

TIMER or GPIO mux control

• 0 = TIMI0 pin enabled

• 1 = GPIO16 pin enabled

Reserved

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4.3.21 Pin Control 1 (PIN_CONTROL_1) Register

The Pin Control 1 Register controls the pin muxing between uPP and EMIF16 pins. The Pin Control 1

Register is shown in

Figure 4-20

and described in

Table 4-22

.

Figure 4-20. Pin Control 1Register (PIN_CONTROL_1)

31

Reserved

R-0

Legend: R = Read only; RW = Read/Write; -n = value after reset

1 0

UPP_EMIF16_MUX

RW-0

Bit Field

31-1 Reserved

0 UPP_EMIF_MUX

Table 4-22. Pin Control 1 Register Field Descriptions

Description

Reserved uPP or EMIF16 mux control

• 0 = EMIF16 pins enabled

• 1 = uPP pins enabled

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4.3.22 uPP Clock Source (UPP_CLOCK) Register

The uPP Clock Source Register controls whether the uPP transmit clock is internally or externally sourced. The uPP Clock Source Register is shown in

Figure 4-21

and described in

Table 4-23

.

Figure 4-21. uPP Clock Source Register (UPP_CLOCK)

31

Reserved

R-0

Legend: R = Read only; RW = Read/Write; -n = value after reset

1 0

UPP_TX_CLKSRC

RW-0

Bit Field

31-1 Reserved

0 UPP_TX_CLKSRC

Table 4-23. uPP Clock Source Register Field Descriptions

Description

Reserved uPP clock source selection

• 0 = from internal SYSCLK4 (CPU/3)

• 1 = from external UPP_2XTXCLK pin

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4.4

Pullup/Pulldown Resistors

Proper board design should ensure that input pins to the device always be at a valid logic level and not floating. This may be achieved via pullup/pulldown resistors. The device features internal pullup (IPU) and internal pulldown (IPD) resistors on most pins to eliminate the need, unless otherwise noted, for external pullup/pulldown resistors.

An external pullup/pulldown resistor needs to be used in the following situations:

Device Configuration Pins: If the pin is both routed out and is not driven (in Hi-Z state), an external pullup/pulldown resistor must be used, even if the IPU/IPD matches the desired value/state.

Other Input Pins: If the IPU/IPD does not match the desired value/state, use an external pullup/pulldown resistor to pull the signal to the opposite rail.

For the device configuration pins (listed in

Table 4-1

), if they are both routed out and are not driven (in Hi-

Z state), it is strongly recommended that an external pullup/pulldown resistor be implemented. Although, internal pullup/pulldown resistors exist on these pins and they may match the desired configuration value, providing external connectivity can help ensure that valid logic levels are latched on these device configuration pins. In addition, applying external pullup/pulldown resistors on the device configuration pins adds convenience to the user in debugging and flexibility in switching operating modes.

Tips for choosing an external pullup/pulldown resistor:

• Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure to include the leakage currents of all the devices connected to the net, as well as any internal pullup or pulldown resistors.

• Decide a target value for the net. For a pulldown resistor, this should be below the lowest V

IL all inputs connected to the net. For a pullup resistor, this should be above the highest V

IH level of level of all inputs on the net. A reasonable choice would be to target the V the limiting device; which, by definition, have margin to the V

IL

OL or V

OH and V

IH levels for the logic family of levels.

• Select a pullup/pulldown resistor with the largest possible value that can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor. The current to be considered includes leakage current plus, any other internal and external pullup/pulldown resistors on the net.

• For bidirectional nets, there is an additional consideration that sets a lower limit on the resistance value of the external resistor. Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level (including margin).

• Remember to include tolerances when selecting the resistor value.

• For pullup resistors, also remember to include tolerances on the DV

DD rail.

For most systems:

• A 1-k Ω resistor can be used to oppose the IPU/IPD while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

• A 20-k Ω resistor can be used to compliment the IPU/IPD on the device configuration pins while meeting the above criteria. Users should confirm this resistor value is correct for their specific application.

For more detailed information on input current (I

I

), and the low-level/high-level input voltages (V

IL for the C6654 device, see

Section 7.3

.

and V

IH

)

To determine which pins on the device include internal pullup/pulldown resistors, see

Table 3-39

.

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5 System Interconnect

On the C6654 device, the C66x CorePac, the EDMA3 transfer controller, and the system peripherals are interconnected through the TeraNet, which is a non-blocking switch fabric enabling fast and contentionfree internal data movement. The TeraNet allows for low-latency, concurrent data transfers between master peripherals and slave peripherals. The TeraNet also allows for seamless arbitration between the system masters when accessing system slaves.

5.1

Internal Buses and Switch Fabrics

Two types of buses exist in the device: data buses and configuration buses. Some peripherals have both a data bus and a configuration bus interface, while others have only one type of interface. Further, the bus interface width and speed varies from peripheral to peripheral. Configuration buses are mainly used to access the register space of a peripheral and the data buses are used mainly for data transfers.

The C66x CorePac, the EDMA3 traffic controller, and the various system peripherals can be classified into two categories: masters and slaves. Masters are capable of initiating read and write transfers in the system and do not rely on the EDMA3 for their data transfers. Slaves, on the other hand, rely on the masters to perform transfers to and from them. Examples of masters include the EDMA3 traffic controller and PCI Express. Examples of slaves include the SPI, UART, and I

2

C.

The masters and slaves in the device are communicating through the TeraNet (switch fabric). The device contains two switch fabrics. The data switch fabric (data TeraNet) and the configuration switch fabric

(configuration TeraNet). The data TeraNet, is a high-throughput interconnect mainly used to move data across the system. The data TeraNet connects masters to slaves via data buses. The configuration

TeraNet, is mainly used to access peripheral registers. The configuration TeraNet connects masters to slaves via configuration buses. Note that the data TeraNet also connects to the configuration TeraNet. For more details see

Section 5.2

.

5.2

Switch Fabric Connections Matrix

The tables below list the master and slave end point connections.

Intersecting cells may contain one of the following:

• Y — There is a connection between this master and that slave.

• - — There is NO connection between this master and that slave.

• n — A numeric value indicates that the path between this master and that slave goes through bridge n.

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Table 5-1. Switch Fabric Connection Matrix Section 1

SLAVES www.ti.com

SPI STM

MASTERS

EDMA3CC_TC0_RD Y

EDMA3CC_TC0_WR Y

EDMA3CC_TC1_RD Y

EDMA3CC_TC1_WR Y

EDMA3CC_TC2_RD Y

EDMA3CC_TC2_WR Y

EDMA3CC_TC3_RD Y

EDMA3CC_TC3_WR Y

PCIe_Master Y

EMAC 3

MSMC_Data_Master Y

QM Packet DMA Y

QM Second

DAP_Master

Y

Y

CorePac0_CFG

Tracer_Master uPP

-

-

3

-

Y

-

-

Y

-

-

-

Y

Y

Y

Y

-

Y

Y

Y

Y

-

Y

-

Y

Y

-

-

-

Y

Y

Y

Y

Y

Y

Y

Y

Y

-

Y

-

Y

Y

-

-

-

Y

-

Y

-

-

Y

-

Y

-

Y

Y -

-

-

-

Y 2, 4 2, 4

Y 2, 4 2, 4

Y 1, 4 1, 4

Y 1, 4 1, 4

Y -

Y 2

Y 1, 4 1, 4 1

-

-

2

-

-

-

-

-

-

-

-

Y 1, 4 1, 4 1

1

Y 1

Y 1, 4 1, 4 1

-

-

-

-

-

-

-

-

-

3

-

Y

Y

Y

-

-

3

Y

Y

Y

Y

Y

Y

Y

Y

Y

-

-

-

-

1

-

Y

-

1

-

-

-

1

-

-

1

-

-

1

-

-

1

-

1

-

-

-

-

2

1

-

-

-

1

-

-

-

-

1

-

Y

-

1

1

2

2

1

2

2

1

1

-

-

-

-

1

-

Y

-

-

-

-

-

1

2

-

-

-

1

1

-

-

1

-

-

1

1

-

Y

-

1

-

-

-

1

1

-

-

1

-

-

1

1

-

Y

-

1

-

-

-

-

-

-

-

1

Y

Y

-

1

1

2

2

1

2

2

1

1

-

-

1 1, 4

1 1, 4

-

-

1 1, 4

1 1, 4

-

-

1 1, 4

-

Y

-

-

-

-

-

1 1, 4

-

-

-

-

4

-

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Table 5-2. Switch Fabric Connection Matrix Section 2

SLAVES

I2C PLL CIC

MASTERS

EDMA3CC_TC0_RD

EDMA3CC_TC0_WR

EDMA3CC_TC1_RD

EDMA3CC_TC1_WR

EDMA3CC_TC2_RD

EDMA3CC_TC2_WR

EDMA3CC_TC3_RD

EDMA3CC_TC3_WR

PCIe_Master

EMAC

MSMC_Data_Master

QM Packet DMA

QM Second

DAP_Master

EDMA3CC

CorePac0_CFG

Tracer_Master uPP

1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1 1, 4 -

1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1 1, 4 -

-

-

1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1 1, 4 -

-

1, 4 1, 4 1, 4 1, 4 1

-

1, 4 1, 4 1, 4 1, 4 1

-

-

1, 4 1, 4 1, 4 1, 4 1

1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1 1, 4 -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

1, 4

-

-

1, 4

-

-

1, 4

-

-

1, 4

-

-

1

1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1

-

-

-

4

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1, 4 1

-

-

-

-

4

-

-

4

-

-

4

-

-

4

-

-

4

-

-

4

-

-

4

-

-

4

-

-

Y

-

-

4

-

-

4

-

-

4

-

-

4

-

-

4

-

-

4

-

-

4

-

-

Y

-

-

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5.3

TeraNet Switch Fabric Connections

The figures below show the connections between masters and slaves through various sections of the

TeraNet.

XMC

EMAC

UPP

M

M

PCIe

M

QM_SS

Packet DMA

M

QM_SS

Second

M

EDMA

CC

Debug_SS

TC_0

TC_1

TC_2

TC_3

M

M

M

M

M

TNet_3_D

CPU/3

Bridge 3

S

SES

Tracer_L2_0

Tracer_QM_M

TNet_6P_A

CPU/3

Tracer_TN_6P_A

Figure 5-1. TeraNet 3A

M S

MSMC

M

DDR3

Tracer_MSMC0

Tracer_MSMC1

Tracer_MSMC2

Tracer_MSMC3

MPU_1

MPU_4

Tracer_DDR

S

S

S

S

S

S

S

S

CorePac_0

QM_SS

PCIe

McBSP0

McBSP1

SPI

Boot_ROM

EMIF

To TeraNet_3P_A

Bridge_1

Bridge_2

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Bridge_1

Bridge_2

From TeraNet_3_A

CorePac_0

M

From TeraNet_3P_A

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

TNet_3P_C

CPU/3

Tracer_QM_CFG

Tracer_SM

MPU_2

MPU_3

MPU_0

S

S

S

S

S

S

MPU0

MPU1

MPU2

MPU3

CC

S

QM_SS

S

Semaphore

TETB (Debug_SS)

TETB (core)

To TeraNet_3P_Tracer

To TeraNet_3P_B

Tracer_CFG

Figure 5-2. TeraNet 3P_A

S

S

Tracer (´11)

UPP

Figure 5-3. TeraNet 3P_B

To TeraNet_6P_B

Bridge_4

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From TeraNet_3P_A

Tracer_

MSMC_0

Tracer_

MSMC_1

Tracer_

MSMC_2

M

M

M

Tracer_

MSMC_3

M

Tracer_CFG

M

Tracer_DDR

M

Tracer_SM

M

Tracer_

QM_M

M

Tracer_

QM_P

M

Tracer_L2_0

M

Tracer_TN_

6P_A

M

Figure 5-4. TeraNet 3P_Tracer www.ti.com

S

Debug_SS

STM

S

Debug_SS

TETB

100

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Bridge_4

From TeraNet_3P_B

Figure 5-5. TeraNet 6P_B

5.4

Bus Priorities

The priority level of all master peripheral traffic is defined at the TeraNet boundary. User programmable priority registers allow software configuration of the data traffic through the TeraNet. Note that a lower number means higher priority - PRI = 000b = urgent, PRI = 111b = low.

Most master ports provide their priority directly and do not need a default priority setting. Examples include the CorePacs, whose priorities are set through software in the UMC control registers. All the packet-DMAbased peripherals also have internal registers to define the priority level of their initiated transactions.

Some masters do not have apriority allocation register of their own. For these masters, a priority allocation register is provided for them and described in the sections below. For all other modules, see the respective User Guides in

Section 3.11

for programmable priority registers.

5.4.1

Packet DMA Priority Allocation (PKTDMA_PRI_ALLOC) Register

The packet DMA secondary port is one master port that does not have priority allocation register inside the IP. The priority level for transaction from this master port is described by PKTDMA_PRI_ALLOC register in

Figure 5-6

and

Table 5-3 .

Figure 5-6. Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC)

3 31

Reserved

R/W-00000000000000000000001000011

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

2

PKTDMA_PRI

RW-000

0

S

S

S

S

S

SmartReflex

GPIO

BOOTCFG

S

S

S

S

S

S

S

S

S

PSC

PLL_CTL

Debug_SS

MPU4

EMAC

McBSP

´

2

SEC_CTL

S

SEC_KEY_MGR

S

Efuse

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Bit

31-3

2-0

Table 5-3. Packet DMA Priority Allocation Register (PKTDMA_PRI_ALLOC) Field Descriptions

Name

Reserved

PKTDMA_PRI

Description

Reserved

Control the priority level for the transactions from packet DMA master port, which access the external linking RAM.

5.4.2

EMAC / uPP Priority Allocation (EMAC_UPP_PRI_ALLOC) Register

The EMAC and uPP are master ports that do not have priority allocation registers inside the IP. The priority level for transaction from these master ports is described by EMAC_UPP_PRI_ALLOC register in

Figure 5-7

and

Table 5-4

.

Figure 5-7. EMAC / uPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC)

31

Reserved

27 26 24

EMAC_EPRI

23

Reserved

19 18 16

EMAC_PRI

15

Reserved

11 10

UPP_EPRI

8

R-00000 RW-110 R-00000 RW-111

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

R-00000 RW-110

7

Reserved

R-00000

3 2

UPP_PRI

RW-111

0

Bit

31-27

26-24

23-19

18-16

15-11

10-8

7-3

2-0

Table 5-4. EMAC / uPP Priority Allocation Register (EMAC_UPP_PRI_ALLOC) Field Descriptions

Name

Reserved

EMAC_EPRI

Reserved

EMAC_PRI

Reserved

UPP_EPRI

Reserved

UPP_PRI

Description

Reserved

Control the maximum priority level for the transactions from EMAC master port.

Reserved

Control the priority level for the transactions from EMAC master port.

Reserved

Control the maximum priority level for the transactions from uPP master port.

Reserved

Control the priority level for the transactions from uPP master port.

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6 C66x CorePac

The C66x CorePac consists of several components:

• The C66x DSP and associated C66x CorePac core

• Level-one and level-two memories (L1P, L1D, L2)

• Data Trace Formatter (DTF)

• Embedded Trace Buffer (ETB)

• Interrupt Controller

• Power-down controller

• External Memory Controller

• Extended Memory Controller

• A dedicated power/sleep controller (LPSC)

The C66x CorePac also provides support for memory protection, bandwidth management (for resources local to the C66x CorePac) and address extension.

Figure 6-1

shows a block diagram of the C66x

CorePac.

32KB L1P

PLLC

Boot

Controller

LPSC

GPSC

Program Memory Controller (PMC) With

Memory Protect/Bandwidth Mgmt

C66x DSP Core

Instruction Fetch

16-/32-bit Instruction Dispatch

Control Registers

In-Circuit Emulation

Instruction Decode

Data Path A Data Path B

A Register File

A31-A16

A15-A0

B Register File

B31-B16

B15-B0

.L1

.S1

.M1

xx xx

.D1

.D2

.M2

xx xx

.S2

.L2

L2 Cache/

SRAM

1024KB

DDR3

SRAM

DMA Switch

Fabric

Data Memory Controller (DMC) With

Memory Protect/Bandwidth Mgmt

CFG Switch

Fabric

32KB L1D

Figure 6-1. C66x CorePac Block Diagram

For more detailed information on the TMS320C66x CorePac on the C6654 device, see the C66x CorePac

User's Guide ( SPRUGW0 ).

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6.1

Memory Architecture

The C66x CorePac in the device contains a 1024KB level-2 memory (L2), a 32KB level-1 program memory (L1P), and a 32KB level-1 data memory (L1D). The C6654 devices also contain a 1024KB multicore shared memory (MSM). All memory on the C6654 has a unique location in the memory map

(see

Table 3-2

).

After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PCFG) and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a twoway set-associative cache, while L1P is a direct-mapped cache.

The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the

Bootloader for the C66x DSP User's Guide ( SPRUGY5 ).

For more information on the operation L1 and L2 caches, see the C66x DSP Cache User's Guide

( SPRUGY8 ).

6.1.1

L1P Memory

The L1P memory configuration for the C6654 device is as follows:

• 32K bytes with no wait states

Figure 6-2

shows the available SRAM/cache configurations for L1P.

000 001

L1P mode bits

010 011 100 L1P memory

Block base address

00E0 0000h

All

SRAM

1/2

SRAM

16K bytes

7/8

SRAM

3/4

SRAM direct mapped cache

8K bytes dm cache direct mapped cache direct mapped cache

4K bytes

4K bytes

Figure 6-2. L1P Memory Configurations

00E0 4000h

00E0 6000h

00E0 7000h

00E0 8000h

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6.1.2

L1D Memory

The L1D memory configuration for the C6654 device is as follows:

• 32K bytes with no wait states

Figure 6-3

shows the available SRAM/cache configurations for L1D.

000 001

L1D mode bits

010 011 100 L1D memory

Block base address

00F0 0000h

1/2

SRAM

16K bytes

All

SRAM

7/8

SRAM

3/4

SRAM

2-way cache

8K bytes

2-way cache

2-way cache

2-way cache

4K bytes

4K bytes

Figure 6-3. L1D Memory Configurations

00F0 4000h

00F0 6000h

00F0 7000h

00F0 8000h

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6.1.3

L2 Memory

The L2 memory configuration for the C6654 device is as follows:

• Total memory is 1024KB

• Each core contains 1024KB of memory

• Local starting address for each core is 0080 0000h

L2 memory can be configured as all SRAM, all 4-way set-associative cache, or a mix of the two. The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2

Configuration Register (L2CFG) of the C66x CorePac.

Figure 6-4

shows the available SRAM/cache configurations for L2. By default, L2 is configured as all SRAM after device reset.

000 001 010

L2 Mode Bits

011 100 101 110 L2 Memory

Block Base

Address

0080 0000h

1/2

SRAM

512K bytes

ALL

SRAM

31/32

SRAM

15/16

SRAM

7/8

SRAM

3/4

SRAM

4-Way

Cache

0088 0000h

256K bytes

4-Way

Cache

128K bytes

4-Way

Cache

4-Way

Cache

4-Way

Cache

4-Way

Cache

Figure 6-4. L2 Memory Configurations

64K bytes

32K bytes

32K bytes

008C 0000h

008E 0000h

008F 0000h

008F 8000h

008F FFFFh

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Global addresses are accessible to all masters in the system. In addition, local memory can be accessed directly by the associated processor through aliased addresses, where the eight MSBs are masked to zero. The aliasing is handled within the C66x CorePac and allows for common code to be run unmodified on multiple cores. For example, address location 0x10800000 is the global base address for C66x

CorePac Core 0's L2 memory. C66x CorePac Core 0 can access this location by either using 0x10800000 or 0x00800000. Any other master on the device must use 0x10800000 only. Conversely, 0x00800000 can by used by any of the cores as their own L2 base addresses.

For C66x CorePac Core 0, address 0x00800000 is equivalent to 0x10800000. Local addresses should be used only for shared code or data, allowing a single image to be included in memory. Any code/data targeted to a specific core, or a memory region allocated during run-time by a particular core should always use the global address only.

6.1.4

MSM Controller

The MSM configuration for the device is as follows:

• Allows extension of external addresses from 2GB to up to 8GB

• Has built in memory protection features

For more details on external memory address extension and memory protection features, see the

Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide ( SPRUGW7 ).

6.1.5

L3 Memory

The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no requirement to block accesses from this portion to the ROM.

6.2

Memory Protection

Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16 pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (16KB each). The L1D, L1P, and L2 memory controllers in the C66x CorePac are equipped with a set of registers that specify the permissions for each memory page.

Each page may be assigned with fully orthogonal user and supervisor read, write, and execute permissions. In addition, a page may be marked as either (or both) locally accessible or globally accessible. A local access is a direct DSP access to L1D, L1P, and L2, while a global access is initiated by a DMA (either IDMA or the EDMA3) or by other system masters. Note that EDMA or IDMA transfers programmed by the DSP count as global accesses.

The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to specify whether memory pages are locally or globally accessible.

The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page protection scheme, see

Table 6-1 .

Table 6-1. Available Memory Page Protection Schemes

AIDx BIT LOCAL BIT DESCRIPTION

0 0 No access to memory page is permitted.

0 1

1

1

0

1

Only direct access by DSP is permitted.

Only accesses by system masters and IDMA are permitted (includes EDMA and IDMA accesses initiated by the DSP).

All accesses permitted.

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Faults are handled by software in an interrupt (or an exception, programmable within the C66x CorePac interrupt controller) service routine. A DSP or DMA access to a page without the proper permissions will:

• Block the access — reads return 0, writes are ignored

• Capture the initiator in a status register — ID, address, and access type are stored

• Signal event to DSP interrupt controller

The software is responsible for taking corrective action to respond to the event and resetting the error status in the memory controller. For more information on memory protection for L1D, L1P, and L2, see the

C66x CorePac User's Guide ( SPRUGW0 ).

6.3

Bandwidth Management

When multiple requestors contend for a single C66x CorePac resource, the conflict is resolved by granting access to the highest priority requestor. The following four resources are managed by the Bandwidth

Management control hardware:

• Level 1 Program (L1P) SRAM/Cache

• Level 1 Data (L1D) SRAM/Cache

• Level 2 (L2) SRAM/Cache

• Memory-mapped registers configuration bus

The priority level for operations initiated within the C66x CorePac are declared through registers in the

C66x CorePac. These operations are:

• DSP-initiated transfers

• User-programmed cache coherency operations

• IDMA-initiated transfers

The priority level for operations initiated outside the C66x CorePac by system peripherals is declared through the Priority Allocation Register (PRI_ALLOC), see

Section 5.4

for more details. System peripherals with no fields in the PRI_ALLOC have their own registers to program their priorities.

More information on the bandwidth management features of the C66x CorePac can be found in the C66x

CorePac User's Guide ( SPRUGW0 ).

6.4

Power-Down Control

The C66x CorePac supports the ability to power down various parts of the C66x CorePac. The power down controller (PDC) of the C66x CorePac can be used to power down L1P, the cache control hardware, the DSP, and the entire C66x CorePac. These power-down features can be used to design systems for lower overall system power requirements.

NOTE

The C6654 does not support power-down modes for the L2 memory at this time.

More information on the power-down features of the C66x CorePac can be found in the C66x CorePac

User's Guide ( SPRUGW0 ).

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6.5

C66x CorePac Revision

The version and revision of the C66x CorePac can be read from the CorePac Revision ID Register

(MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in

Figure 6-5

and described in

Table 6-2

. The C66x CorePac revision is dependent on the silicon revision being used.

Figure 6-5. CorePac Revision ID Register (MM_REVID) Address - 0181 2000h

16 15 31

VERSION

R-n

Legend: R = Read; -n = value after reset

REVISION

R-n

0

Bit Field

31-16 VERSION

15-0 REVISION

Table 6-2. CorePac Revision ID Register (MM_REVID) Field Descriptions

Description

Version of the C66x CorePac implemented on the device.

Revision of the C66x CorePac version implemented on the device.

6.6

C66x CorePac Register Descriptions

See the C66x CorePac Reference Guide ( SPRUGW0 ) for register offsets and definitions.

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7 Device Operating Conditions

7.1

Absolute Maximum Ratings

(1)

Over Operating Case Temperature Range (Unless Otherwise Noted)

Supply voltage range

(2)

:

Input voltage (V

I

) range:

Output voltage (V

O

) range:

Operating case temperature range, T

C

:

ESD stress voltage, V

ESD

(3)

:

Overshoot/undershoot

(6)

CVDD

CVDD1

DVDD15

DVDD18

VREFSSTL

VDDT1, VDDT2

VDDR1, VDDR2, VDDR3, VDDR4

AVDDA1, AVDDA2

VSS Ground

LVCMOS (1.8V)

DDR3

I

2

C

LVDS

LJCB

SerDes

LVCMOS (1.8V)

DDR3

I

2

C

SerDes

Commercial

Extended

HBM (human body model)

(4)

CDM (charged device model)

(5)

LVCMOS (1.8V)

DDR3

I

2

C

Storage temperature range, T stg

:

-0.3 V to 1.3 V

-0.3 V to 1.3 V

-0.3 V to 2.45 V

-0.3 V to 2.45 V

0.49 × DVDD15 to 0.51 × DVDD15

-0.3 V to 1.3 V

-0.3 V to 2.45 V

-0.3 V to 2.45 V

0 V

-0.3 V to DVDD18+0.3 V

-0.3 V to 2.45 V

-0.3 V to 2.45 V

-0.3 V to DVDD18+0.3 V

-0.3 V to 1.3 V

-0.3 V to CVDD1+0.3 V

-0.3 V to DVDD18+0.3 V

-0.3 V to 2.45 V

-0.3 V to 2.45 V

-0.3 V to CVDD1+0.3 V

0°C to 85°C

-40°C to 100°C

±1000 V

±250 V

20% Overshoot/Undershoot for 20% of

Signal Duty Cycle

-65°C to 150°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V

SS

.

(3) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.

(4) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process, and manufacturing with less than 500 V HBM is possible if necessary precautions are taken. Pins listed as 1000 V may actually have higher performance.

(5) Level listed above is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.

(6) Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1.8-V LVCMOS signals is DVDD18 + 0.20 × DVDD18 and maximum undershoot value would be V

SS

- 0.20 × DVDD18

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7.2

Recommended Operating Conditions

(1) (2)

CVDD

CVDD1

SR Core Supply 850MHz - Device

Core supply voltage for memory array

DVDD18

DVDD15

1.8-V supply I/O voltage

1.5-V supply I/O voltage

VREFSSTL DDR3 reference voltage

V

DDRx

(5)

SerDes regulator supply

V

DDAx

PLL analog supply

V

DDTx

V

SS

SerDes termination supply

Ground

V

IH

High-level input voltage

LVCMOS (1.8 V)

I

2

C

DDR3 EMIF

V

T

IL

C

Low-level input voltage

Operating case temperature

LVCMOS (1.8 V)

DDR3 EMIF

I

2

C

Commercial

Extended

MIN

SRVnom

(3)

× 0.95

0.95

1.71

1.425

0.49 × DVDD15

1.425

1.71

0.95

0

0.65 × DVDD18

0.7 × DVDD18

VREFSSTL + 0.1

-0.3

NOM

0.85-1.1

(4)

1

1.8

1.5

0.5 × DVDD15

1.5

1.8

1

0

MAX UNIT

SRVnom × 1.05

V

1.05

1.89

1.575

0.51 × DVDD15

1.575

V

V

V

V

V

1.89

1.05

0

V

V

V

V

V

0.35 × DVDD18

VREFSSTL - 0.1

0.3 × DVDD18 V

85 °C

100 °C

V

V

V

0

-40

(1) All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596.3-1996 and all SERDES I/Os comply with the XAUI

Electrical Specification, IEEE 802.3ae-2002.

(2) All SERDES I/Os comply with the XAUI Electrical Specification, IEEE 802.3ae-2002.

(3) SRVnom refers to the unique SmartReflex core supply voltage set from the factory for each individual device.

(4) The initial CVDD voltage at power on will be 1.1V nominal and it must transition to VID set value immediately after being presented on

VCNTL pins. This is required to maintain full power functionality and reliability targets guaranteed by TI.

(5) Where x = 1, 2, 3, 4... to indicate all supplies of the same kind.

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7.3

Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

PARAMETER TEST CONDITIONS

(1)

MIN NOM

LVCMOS (1.8 V) I

O

= I

OH

DVDD18 -

0.45

V

OH

High-level output voltage

DDR3

I

2

C

(2)

DVDD15 - 0.4

LVCMOS (1.8 V)

DDR3

I

O

= I

OL

V

OL

Low-level output voltage

I

I

(3)

Input current [DC]

I

2

C

LVCMOS (1.8 V)

I

2

C

I

O

= 3 mA, pulled up to

1.8 V

No IPD/IPU

Internal pullup

Internal pulldown

0.1 × DVDD18 V < V

I

0.9 × DVDD18 V

<

-5

50

-170

-10

MAX UNIT

0.45

0.4

0.4

5

100 170

(4)

-100 -50

10

V

V

µA

I

OH

I

OL

I

OZ

(6)

High-level output current

[DC]

Low-level output current

[DC]

Off-state output current

[DC]

LVCMOS (1.8 V)

DDR3

I

2

C

(5)

LVCMOS (1.8 V)

DDR3

I

2

C

LVCMOS (1.8 V)

DDR3

I

2

C

-2

-2

-2

-6

-8 mA

6

8 mA

3

2

2 µA

2

(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.

(2) I

2

C uses open collector IOs and does not have a V

OH

Minimum.

(3) I

I applies to input-only pins and bi-directional pins. For input-only pins, I

I indicates the input leakage current. For bi-directional pins, I includes input leakage current and off-state (Hi-Z) output leakage current.

I

(4) For RESETSTAT, max DC input current is 300 µA.

(5) I

2

C uses open collector IOs and does not have a I

OH

(6) I

OZ

Maximum.

applies to output-only pins, indicating off-state (Hi-Z) output leakage current.

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7.4

Power Supply to Peripheral I/O Mapping

(1) (2)

Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

CVDD

DVDD15

DVDD18

POWER SUPPLY

Supply Core Voltage

1.5-V supply I/O voltage DDR3 (1.5 V)

1.8-V supply I/O voltage

I/O BUFFER TYPE

LJCB

LVCMOS (1.8 V)

Open-drain (1.8V)

ASSOCIATED PERIPHERAL

CORECLK(P|N) PLL input buffers

SGMIICLK(P|N) SerDes PLL input buffers

DDRCLK(P|N) PLL input buffers

PCIECLK(P|N) SERDES PLL input buffers

All DDR3 memory controller peripheral I/O buffers

All GPIO peripheral I/O buffers

All JTAG and EMU peripheral I/O buffers

All Timer peripheral I/O buffers

All SPI peripheral I/O buffers

All RESETs, NMI, Control peripheral I/O buffers

All MDIO peripheral I/O buffers

All UART peripheral I/O buffers

All McBSP peripheral I/O buffers

All EMIF16 peripheral I/O buffers

All uPP peripheral I/O buffers

All I

2

C peripheral I/O buffers

All SmartReflex peripheral I/O buffers

VDDT2 SGMII/PCIE SerDes termination and analogue SerDes/CML front-end supply

SGMII/PCIE SerDes CML IO buffers

(1) Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to power peripheral I/O buffers and clock input buffers.

(2) Please see the Hardware Design Guide for KeyStone Devices ( SPRABI2 ) for more information about individual peripheral I/O.

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8 Peripheral Information and Electrical Specifications

This chapter covers the various peripherals on the C6654 DSP. Peripheral-specific information, timing diagrams, electrical specifications, and register memory maps are described in this chapter.

8.1

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between V

IH manner.

and V

IL

(or between V

IL and V

IH

) in a monotonic

8.2

Power Supplies

The following sections describe the proper power-supply sequencing and timing needed to properly power on the C6654. The various power supply rails and their primary function is listed in

Table 8-1 .

NAME

CVDD

CVDD1

VDDT1

VDDT2

DVDD15

VDDR1

VDDR2

VDDR3

VDDR4

DVDD18

AVDDA1

AVDDA2

VREFSSTL

VSS

Table 8-1. Power Supply Rails on C6654

PRIMARY FUNCTION

SmartReflex core supply voltage

VOLTAGE

0.85 V - 1.1 V

Core supply voltage for memory 1.0 V array

Reserved 1.0 V

SGMII/PCIE SerDes termination 1.0 V supply

1.5-V DDR3 IO supply

Reserved

1.5 V

1.5 V

PCIE SerDes regulator supply 1.5 V

SGMII SerDes regulator supply 1.5 V

NOTES

Includes core voltage for DDR3 module

Fixed supply at 1.0 V

Connect to CVDD1

Filtered version of CVDD1. Special considerations for noise. Filter is not needed if SGMII/PCIE is not in use.

Connect to DVDD15

Filtered version of DVDD15. Special considerations for noise. Filter is not needed if PCIE is not in use.

Filtered version of DVDD15. Special considerations for noise. Filter is not needed if SGMII is not in use.

Connect to DVDD15 Reserved

1.8-V IO supply

1.5 V

1.8V

Main PLL supply 1.8 V

DDR3 PLL supply 1.8 V

0.75-V DDR3 reference voltage 0.75 V

Ground GND

Filtered version of DVDD18. Special considerations for noise.

Filtered version of DVDD18. Special considerations for noise.

Should track the 1.5-V supply. Use 1.5 V as source.

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8.2.1

Power-Supply Sequencing

This section defines the requirements for a power up sequencing from a power-on reset condition. There are two acceptable power sequences for the device. The first sequence stipulates the core voltages starting before the IO voltages as shown below.

1. CVDD

2. CVDD1, VDDT1-2

3. DVDD18, AVDDA1, AVDDA2

4. DVDD15, VDDR1-4

The second sequence provides compatibility with other TI processors with the IO voltage starting before the core voltages as shown below.

1. DVDD18, AVDDA1, AVDDA2

2. CVDD

3. CVDD1, VDDT1-2

4. DVDD15, VDDR1-4

The clock input buffers for CORECLK, DDRCLK, SGMIICLK, and PCIECLK use only CVDD as a supply voltage. These clock inputs are not failsafe and must be held in a high-impedance state until CVDD is at a valid voltage level. Driving these clock inputs high before CVDD is valid could cause damage to the device. Once CVDD is valid it is acceptable that the P and N legs of these CLKs may be held in a static state (either high and low or low and high) until a valid clock frequency is needed at that input. To avoid internal oscillation the clock inputs should be removed from the high impedance state shortly after CVDD is present.

If a clock input is not used it must be held in a static state. To accomplish this the N leg should be pulled to ground through a 1K ohm resistor. The P leg should be tied to CVDD to ensure it won't have any voltage present until CVDD is active. Connections to the IO cells powered by DVDD18 and DVDD15 are not failsafe and should not be driven high before these voltages are active. Driving these IO cells high before DVDD18 or DVDD15 are valid could cause damage to the device.

The device initialization is broken into two phases. The first phase consists of the time period from the activation of the first power supply until the point in which all supplies are active and at a valid voltage level. Either of the sequencing scenarios described above can be implemented during this phase. The figures below show both the core-before-IO voltage sequence and the IO-before-core voltage sequence.

POR must be held low for the entire power stabilization phase.

This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of

RESETFULL will trigger the end of the initialization phase but both must be inactive for the initialization to complete. POR must always go inactive before RESETFULL goes inactive as described below. SYSCLK1 in the following section refers to the clock input that has been selected as the source for the main PLL and

SYSCLK1 refers to the main PLL output that is used by the CorePac, see

Figure 8-7

for more details.

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8.2.1.1

Core-Before-IO Power Sequencing

Figure 8-1

shows the power sequencing and reset control of C6654 for device initialization. POR may be removed after the power has been stable for the required 100 µsec. RESETFULL must be held low for a period after the rising edge of POR but may be held low for longer periods if necessary. The configuration bits shared with the GPIO pins will be latched on the rising edge of RESETFULL and must meet the setup and hold times specified. SYSCLK1 must always be active before POR can be removed. Core-before-IO power sequencing is defined in

Table 8-2

.

NOTE

TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp.

Power Stabilization Phase Device Initialization Phase

POR

7

RESETFULL

8

GPIO Config

Bits

4b 9 10

RESET

1

CVDD

CVDD1

2a

2c

6

3

DVDD18

4a

DVDD15

5

SYSCLK1P&N

2b

DDRCLKP&N

RESETSTAT

Figure 8-1. Core Before IO Power Sequencing

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2b

2c

3

5

6

4a

4b

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2a

7

8

TIME

1

9

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Table 8-2. Core Before IO Power Sequencing

SYSTEM STATE

Begin Power Stabilization Phase

• CVDD (core AVS) ramps up.

• POR must be held low through the power stabilization phase. Because POR is low, all the core logic that has async reset

(created from POR) is put into the reset state.

• CVDD1 (core constant) ramps at the same time or shortly following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted, the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.

• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst-case current could be on the order of twice the specified draw of CVDD1.

• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or be held in a static state with one leg high and one leg low.

• The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before

POR goes high specified by t6.

• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.

• RESETSTAT is driven low once the DVDD18 supply is available.

• All LVCMOS input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 is valid could cause damage to the device.

• DVDD15 (1.5 V) supply is ramped up following DVDD18. Although ramping DVDD18 and DVDD15 simultaneously is permitted, the voltage for DVDD15 must never exceed DVDD18.

• RESET may be driven high any time after DVDD18 is at a valid level. In a POR-controlled boot, RESET must be high before

POR is driven high.

• POR must continue to remain low for at least 100 µs after power has stabilized.

End Power Stabilization Phase

• Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33

nsec, so a delay of an additional 16 µs is required before a rising edge of POR. The clock must be active during the entire

16 µs.

• RESETFULL must be held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.

• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.

• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be

10000 to 50000 clock cycles.

End Device Initialization Phase

• GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL

• GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL

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8.2.1.2

IO-Before-Core Power Sequencing

The timing diagram for IO-before-core power sequencing is shown in

Figure 8-2

and defined in

Table 8-3

.

NOTE

TI recommends a maximum of 100 ms between one power rail being valid, and the next power rail in the sequence starting to ramp.

Power Stabilization Phase Device Initialization Phase

POR

5

7

RESETFULL

8

GPIO Config

Bits

2a

RESET

2b

CVDD

3c

9 10

6

3a

CVDD1

DVDD18

1

4

DVDD15

3b

SYSCLK1P&N

DDRCLKP&N

RESETSTAT

Figure 8-2. IO Before Core Power Sequencing

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3c

4

5

TIME

1

2a

2b

3a

3b

6

7

8

9

10

Table 8-3. IO Before Core Power Sequencing

SYSTEM STATE

Begin Power Stabilization Phase

• Because POR is low, all the core logic having async reset (created from POR) are put into reset state once the core supply ramps. POR must remain low through Power Stabilization Phase.

• Filtered versions of 1.8 V can ramp simultaneously with DVDD18.

• RESETSTAT is driven low once the DVDD18 supply is available.

• All input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 could cause damage to the device.

• RESET may be driven high anytime after DVDD18 is at a valid level.

• CVDD (core AVS) ramps up.

• CVDD1 (core constant) ramps at the same time or following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage.

• The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 should trail CVDD as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS), then the worst case current could be on the order of twice the specified draw of CVDD1.

• Once CVDD is valid, the clock drivers should be enabled. Although the clock inputs are not necessary at this time, they should either be driven with a valid clock or held in a static state with one leg high and one leg low.

• The DDRCLK and SYSCLK1 may begin to toggle anytime between when CVDD is at a valid level and the setup time before

POR goes high specified by t6.

• DVDD15 (1.5 V) supply is ramped up following CVDD1.

• POR must continue to remain low for at least 100 µs after power has stabilized.

End Power Stabilization Phase

Begin Device Initialization

• Device initialization requires 500 SYSCLK1 periods after the Power Stabilization Phase. The maximum clock period is 33.33

nsec so a delay of an additional 16 µs is required before a rising edge of POR. The clock must be active during the entire

16 µs.

• POR must remain low.

• RESETFULL is held low for at least 24 transitions of the SYSCLK1 after POR has stabilized at a high level.

• The rising edge of the RESETFULL will remove the reset to the efuse farm allowing the scan to begin.

• Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be

10000 to 50000 clock cycles.

End Device Initialization Phase

• GPIO configuration bits must be valid for at least 12 transitions of the SYSCLK1 before the rising edge of RESETFULL

• GPIO configuration bits must be held valid for at least 12 transitions of the SYSCLK1 after the rising edge of RESETFULL

8.2.1.3

Prolonged Resets

Holding the device in POR, RESETFULL, or RESET for long periods of time will affect the long term reliability of the part. The device should not be held in a reset for times exceeding one hour and should not be held in reset for more the 5% of the time during which power is applied. Exceeding these limits will cause a gradual reduction in the reliability of the part. This can be avoided by allowing the DSP to boot and then configuring it to enter a hibernation state soon after power is applied. This will satisfy the reset requirement while limiting the power consumption of the device.

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8.2.1.4

Clocking During Power Sequencing

Some of the clock inputs are required to be present for the device to initialize correctly, but behavior of many of the clocks is contingent on the state of the boot configuration pins.

Table 8-4

describes the clock sequencing and the conditions that affect the clock operation. Note that all clock drivers should be in a high-impedance state until CVDD is at a valid level and that all clock inputs either be active or in a static state with one leg pulled low and the other connected to CVDD.

CLOCK

DDRCLK

CORECLK

SRIOSGMII

CLK

PCIECLK

Table 8-4. Clock Sequencing

CONDITION

None

SEQUENCING

Must be present 16 µsec before POR transitions high.

None CORECLK used to clock the core PLL. It must be present 16 µsec before POR transitions high.

SRIOSGMIICLK must be present 16 µsec before POR transitions high.

The SGMII port will be used.

SGMII will not be used.

SRIOSGMIICLK is not used and should be tied to a static state.

PCIE will be used as a boot PCIECLK must be present 16 µsec before POR transitions high.

device.

PCIE will be used after boot.

PCIE will not be used.

PCIECLK is used as a source to the PCIE SERDES PLL. It must be present before the PCIE is removed from reset and programmed.

PCIECLK is not used and should be tied to a static state.

8.2.2

Power-Down Sequence

The power down sequence is the exact reverse of the power-up sequence described above. The goal is to prevent a large amount of static current and to prevent overstress of the device. A power-good circuit that monitors all the supplies for the device should be used in all designs. If a catastrophic power supply failure occurs on any voltage rail, POR should transition to low to prevent over-current conditions that could possibly impact device reliability.

A system power monitoring solution is needed to shut down power to the board if a power supply fails.

Long-term exposure to an environment in which one of the power supply voltages is no longer present will affect the reliability of the device. Holding the device in reset is not an acceptable solution because prolonged periods of time with an active reset can also affect long term reliability.

8.2.3

Power Supply Decoupling and Bulk Capacitors

In order to properly decouple the supply planes on the PCB from system noise, decoupling and bulk capacitors are required. Bulk capacitors are used to minimize the effects of low frequency current transients and decoupling or bypass capacitors are used to minimize higher frequency noise. For recommendations on selection of Power Supply Decoupling and Bulk capacitors see the Hardware Design

Guide for KeyStone Devices ( SPRABI2 ).

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8.2.4

SmartReflex

Increasing the device complexity increases its power consumption and with the smaller transistor structures responsible for higher achievable clock rates and increased performance, comes an inevitable penalty, increasing the leakage currents. Leakage currents are present in any active circuit, independently of clock rates and usage scenarios. This static power consumption is mainly determined by transistor type and process technology. Higher clock rates also increase dynamic power, the power used when transistors switch. The dynamic power depends mainly on a specific usage scenario, clock rates, and I/O activity.

Texas Instruments' SmartReflex technology is used to decrease both static and dynamic power consumption while maintaining the device performance. SmartReflex in the C6654 device is a feature that allows the core voltage to be optimized based on the process corner of the device. This requires a voltage regulator for each C6654 device.

To guarantee maximizing performance and minimizing power consumption of the device, SmartReflex is required to be implemented whenever the C6654 device is used. The voltage selection is done using 4

VCNTL pins which are used to select the output voltage of the core voltage regulator.

For information on implementation of SmartReflex see the Power Management for KeyStone Devices application report and the Hardware Design Guide for KeyStone Devices ( SPRABI2 ).

Table 8-5. SmartReflex 4-Pin VID Interface Switching Characteristics

4

5

2

3

NO.

1

(see

Figure 8-3

) td(VCNTL[2:0]-VCNTL[3]) toh(VCNTL[3] -VCNTL[2:0]) td(VCNTL[2:0]-VCNTL[3])

PARAMETER

Delay Time - VCNTL[2:0] valid after VCNTL[3] low

Output Hold Time - VCNTL[2:0] valid after VCNTL[3] low

Delay Time - VCNTL[2:0] valid after VCNTL[3] high toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] high

VCNTL being valid to CVDD being switched to SmartReflex Voltage

(2)

MIN MAX

300.00

0.07

172020C

(1)

0.07

300.00

172020C

10

(1) C = 1/SYSCLK1 frequency (See

Figure 8-9 ) in ms

(2) SmartReflex voltage must be set before execution of application code

UNIT

ns ms ns ms ms

1.1 V

SRV*

* SRV = Smart Reflex Voltage

CVDD

4

5

VCNTL[3]

VCNTL[2:0]

1 3

LSB VID[2:0] MSB VID[5:3]

2

Figure 8-3. SmartReflex 4-Pin VID Interface Timing

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8.3

Power Sleep Controller (PSC)

The Power Sleep Controller (PSC) controls overall device power by turning off unused power domains and gating off clocks to individual peripherals and modules. The PSC provides the user with an interface to control several important power and clock operations.

For information on the Power Sleep Controller, see the Power Sleep Controller (PSC) for KeyStone

Devices User's Guide ( SPRUGV4 ).

8.3.1

Power Domains

The device has several power domains that can be turned on for operation or off to minimize power dissipation. The global power/sleep controller (GPSC) is used to control the power gating of various power domains.

Table 8-6

shows the C6654 power domains.

5

6

7

3

4

8

9

10

11

12

13

1

2

DOMAIN BLOCK(S)

0 Most peripheral logic

Per-core TETB and System TETB

Reserved

PCIe

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

C66x Core 0, L1/L2 RAMs

14

15

Reserved

Reserved

Table 8-6. Power Domains

NOTE

Cannot be disabled

RAMs can be powered down

Reserved

Logic can be powered down

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

L2 RAMs can sleep

Reserved

Reserved

POWER CONNECTION

Always on

Software control

Reserved

Software control

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Software control via C66x CorePac. For details, see the C66x CorePac Reference

Guide.

Reserved

Reserved

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14

15

16

17

18

9

10

11

12

13

4

5

6

7

8

2

3

LPSC NUMBER

0

1

19

20

21

22

23

24

No LPSC

8.3.2

Clock Domains

Clock gating to each logic block is managed by the local power/sleep controllers (LPSCs) of each module.

For modules with a dedicated clock or multiple clocks, the LPSC communicates with the PLL controller to enable and disable that module's clock(s) at the source. For modules that share a clock with other modules, the LPSC controls the clock gating.

Table 8-7

shows the C6654 clock domains.

Table 8-7. Clock Domains

Reserved

PCIe

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

MODULE(S) NOTES

Shared LPSC for all peripherals other than those listed in this table Always on

SmartReflex Always on

DDR3 EMIF

EMAC

Always on

Software control

Reserved

Debug Subsystem and Tracers

Per-core TETB and System TETB

Reserved

Reserved

Reserved

Software control

Software control

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

C66x CorePac 0 and Timer 0

Timer1

Bootcfg, PSC, and PLL controller

Reserved

Software control

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Software control

Software control

These modules do not use LPSC

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0x22C

0x230

0x234

0x238

0x23C

0x240 - 0x2FC

0x300

0x304

0x308

0x30C

0x310

0x314

0x318

0x31C

0x320

0x324

0x328

0x32C

0x330

0x334

0x338

0x33C

0x340 - 0x7FC

0x800

0x204

0x208

0x20C

0x210

0x214

0x218

0x21C

0x220

0x224

0x228

OFFSET

0x000

0x004 - 0x010

0x014

0x018 - 0x11C

0x120

0x124

0x128

0x12C - 0x1FC

0x200

PDCTL4

PDCTL5

PDCTL6

PDCTL7

PDCTL8

PDCTL9

PDCTL10

PDCTL11

PDCTL12

PDCTL13

PDCTL14

Reserved

Reserved

MDSTAT0

PDSTAT11

PDSTAT12

PDSTAT13

PDSTAT14

Reserved

Reserved

PDCTL0

PDCTL1

PDCTL2

PDCTL3

REGISTER

PID

Reserved

VCNTLID

Reserved

PTCMD

Reserved

PTSTAT

Reserved

PDSTAT0

PDSTAT1

PDSTAT2

PDSTAT3

PDSTAT4

PDSTAT5

PDSTAT6

PDSTAT7

PDSTAT8

PDSTAT9

PDSTAT10

8.3.3

PSC Register Memory Map

Table 8-8

shows the PSC Register memory map.

Table 8-8. PSC Register Memory Map

DESCRIPTION

Peripheral Identification Register

Reserved

Voltage Control Identification Register

(1)

Reserved

Power Domain Transition Command Register

Reserved

Power Domain Transition Status Register

Reserved

Power Domain Status Register 0 (AlwaysOn)

Power Domain Status Register 1 (Per-core TETB and System TETB)

Power Domain Status Register 2 (Reserved)

Power Domain Status Register 3 (PCIe)

Power Domain Status Register 4 (Reserved)

Power Domain Status Register 5 (Reserved)

Power Domain Status Register 6 (Reserved)

Power Domain Status Register 7(Reserved)

Power Domain Status Register 8 (Reserved)

Power Domain Status Register 9 (Reserved)

Power Domain Status Register 10 (Reserved)

Power Domain Status Register 11(Reserved)

Power Domain Status Register 12 (Reserved)

Power Domain Status Register 13 (C66x CorePac 0)

Power Domain Status Register 14 (Reserved)

Reserved

Reserved

Power Domain Control Register 0 (AlwaysOn)

Power Domain Control Register 1 (Per-core TETB and System TETB)

Power Domain Control Register 2 (Reserved)

Power Domain Control Register 3 (PCIe)

Power Domain Control Register 4 (Reserved)

Power Domain Control Register 4 (Reserved)

Power Domain Control Register 6 (Reserved)

Power Domain Control Register 7 (Reserved)

Power Domain Control Register 8 (Reserved)

Power Domain Control Register 9 (Reserved)

Power Domain Control Register 10 (Reserved)

Power Domain Control Register 11(Reserved)

Power Domain Control Register 12(Reserved)

Power Domain Control Register 13 (C66x CorePac 0)

Power Domain Control Register 14 (Reserved)

Reserved

Reserved

Module Status Register 0 (Never Gated)

(1) VCNTLID register is available for debug purpose only.

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MDCTL6

MDCTL7

MDCTL8

MDCTL9

MDCTL10

MDCTL11

MDCTL12

MDCTL13

MDCTL14

MDCTL15

MDSTAT22

MDSTAT23

MDSTAT24

Reserved

MDCTL0

MDCTL1

MDCTL2

MDCTL3

MDCTL4

MDCTL5

MDCTL16

MDCTL17

MDCTL18

MDCTL19

MDCTL20

MDCTL21

REGISTER

MDSTAT1

MDSTAT2

MDSTAT3

MDSTAT4

MDSTAT5

MDSTAT6

MDSTAT7

MDSTAT8

MDSTAT9

MDSTAT10

MDSTAT11

MDSTAT12

MDSTAT13

MDSTAT14

MDSTAT15

MDSTAT16

MDSTAT17

MDSTAT18

MDSTAT19

MDSTAT20

MDSTAT21

0xA18

0xA1C

0xA20

0xA24

0xA28

0xA2C

0xA30

0xA34

0xA38

0xA3C

0x858

0x85C

0x860

0x864 - 0x9FC

0xA00

0xA04

0xA08

0xA0C

0xA10

0xA14

0xA40

0xA44

0xA48

0xA4C

0xA50

0xA54

0x830

0x834

0x838

0x83C

0x840

0x844

0x848

0x84C

0x850

0x854

OFFSET

0x804

0x808

0x80C

0x810

0x814

0x818

0x81C

0x820

0x824

0x828

0x82C

Table 8-8. PSC Register Memory Map (continued)

DESCRIPTION

Module Status Register 1 (SmartReflex)

Module Status Register 2 (DDR3 EMIF)

Module Status Register 3 (EMAC)

Module Status Register 4 (Reserved)

Module Status Register 5 (Debug Subsystem and Tracers)

Module Status Register 6 (Per-core TETB and System TETB)

Module Status Register 7 (Reserved)

Module Status Register 8 (Reserved)

Module Status Register 9 (Reserved)

Module Status Register 10 (PCIe)

Module Status Register 11(Reserved)

Module Status Register 12(Reserved)

Module Status Register 13 (Reserved)

Module Status Register 14 (Reserved)

Module Status Register 15 (Reserved)

Module Status Register 16 (Reserved)

Module Status Register 17 (Reserved)

Module Status Register 18 (Reserved)

Module Status Register 19 (Reserved)

Module Status Register 20 (Reserved)

Module Status Register 11 (Reserved)

Module Status Register 22(Reserved)

Module Status Register 23(C66x CorePac 0 and Timer 0)

Timer1

Reserved

Module Control Register 0 (Never Gated)

Module Control Register 1 (SmartReflex)

Module Control Register 2 (DDR3 EMIF)

Module Control Register 3 (EMAC)

Module Control Register 4 (Reserved)

Module Control Register 5 (Debug Subsystem and Tracers)

Module Control Register 6 (Per-core TETB and System TETB)

Module Control Register 7 (Reserved)

Module Control Register 8 (Reserved)

Module Control Register 9 (Reserved)

Module Control Register 10 (PCIe)

Module Control Register 11(Reserved)

Module Control Register 12(Reserved)

Module Control Register 13 (Reserved)

Module Control Register 14 (Reserved)

Module Control Register 15 (Reserved)

Module Control Register 16 (Reserved)

Module Control Register 17 (Reserved)

Module Control Register 18 (Reserved)

Module Control Register 19 (Reserved)

Module Control Register 20 (Reserved)

Module Control Register 21(Reserved)

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OFFSET

0xA58

REGISTER

MDCTL22

0xA5C MDCTL23

0xA60 MDCTL24

0xA5C - 0xFFC Reserved

Table 8-8. PSC Register Memory Map (continued)

DESCRIPTION

Module Control Register 22(Reserved)

Module Control Register 23(C66x CorePac 0 and Timer 0)

Timer1

Reserved

8.4

Reset Controller

The reset controller detects the different type of resets supported on the C6654 device and manages the distribution of those resets throughout the device.

The device has several types of resets:

• Power-on reset

• Hard reset

• Soft reset

• CPU local reset

Table 8-9

explains further the types of reset, the reset initiator, and the effects of each reset on the device.

For more information on the effects of each reset on the PLL controllers and their clocks, see

Section 8.4.7

.

RESET TYPE

POR

(Power On Reset)

Hard reset

Soft reset

C66x CorePac local reset

Table 8-9. Reset Types

INITIATOR

POR pin active low

RESETFULL pin active low

RESET pin active low

Emulation

PLLCTL register (RSCTRL)

EFFECT ON DEVICE WHEN RESET OCCURS

Total reset of the chip. Everything on the device is reset to its default state in response to this. Activates the POR signal on chip, which is used to reset test/emu logic. Boot configurations are latched. ROM boot process is initiated.

RESETSTAT

PIN STATUS

Toggles

RESETSTAT pin

Resets everything except for test/emu logic and reset isolation Toggles modules. Emulator and reset Isolation modules stay alive during RESETSTAT pin this reset. This reset is also different from POR in that the

PLLCTL assumes power and clocks are stable when device reset is asserted. Boot configurations are not latched. ROM boot process is initiated.

Watchdog timers

RESET pin active low

PLLCTL register (RSCTRL)

Watchdog timers

Software (through LPSC

MMR) Watchdog timers

LRESET pin

Software can program these initiators to be hard or soft. Hard reset is the default, but can be programmed to be soft reset.

Soft reset will behave like hard reset except that EMIF16

MMRs, DDR3 EMIF MMRs, sticky bits in PCIe MMRs, and external memory contents are retained. Boot configurations are not latched. ROM boot process is initiated.

Toggles

RESETSTAT pin

MMR bit in LPSC controls C66x CorePac local reset. Used by Does not toggle watchdog timers (in the event of a timeout) to reset C66x RESETSTAT pin

CorePac. Can also be initiated by LRESET device pin. C66x

CorePac memory system and slave DMA port are still alive when C66x CorePac is in local reset. Provides a local reset of the C66x CorePac, without destroying clock alignment or memory contents. Does not initiate ROM boot process.

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8.4.1

Power-on Reset

Power-on reset is used to reset the entire device, including the test and emulation logic.

Power-on reset is initiated by the following:

1. POR pin

2. RESETFULL pin

During power-up, the POR pin must be asserted (driven low) until the power supplies have reached their normal operating conditions. A RESETFULL pin is also provided to allow the on-board host to reset the entire device including the reset isolated logic. The assumption is that the device is already powered up and hence, unlike the POR pin, the RESETFULL pin will be driven by the on-board host control instead of the power-good circuitry. For power-on reset, the Main PLL Controller comes up in bypass mode and the

PLL is not enabled. Other resets do not affect the state of the PLL or the dividers in the PLL controller.

The following sequence must be followed during a power-on reset:

1. Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted

(driven low). While POR is asserted, all pins except RESETSTAT will be set to high-impedance. After the POR pin is de-asserted (driven high), all Z group pins, low group pins, and high group pins are set to their reset state and will remain at their reset state until otherwise configured by their respective peripheral. All peripherals that are power managed, are disabled after a power-on reset and must be enabled through the Device State Control Registers (for more details, see

Table 4-2 ).

2. Clocks are reset, and they are propagated throughout the device to reset any logic that was using reset synchronously. All logic is now reset and RESETSTAT will be driven low indicating that the device is in reset.

3. POR must be held active until all supplies on the board are stable then for at least an additional time for the chip-level PLLs to lock.

4. The POR pin can now be de-asserted. Reset-sampled pin values are latched at this point. The chip level PLLs are taken out of reset and begin their locking sequence, and all power-on device initialization also begins.

5. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high). By this time, the DDR3 PLL has already completed its locking sequence and is outputting a valid clock. The system clocks of both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks. After the pause, the system clocks are restarted at their default divide by settings.

6. The device is now out of reset and device execution begins as dictated by the selected boot mode.

NOTE

To most of the device, reset is de-asserted only when the POR and RESET pins are both de-asserted (driven high). Therefore, in the sequence described above, if the RESET pin is held low past the low period of the POR pin, most of the device will remain in reset. The

RESET pin should not be tied together with the POR pin.

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8.4.2

Hard Reset

A hard reset will reset everything on the device except the PLLs, test, emulation logic, and reset isolation modules. POR should also remain de-asserted during this time.

Hard reset is initiated by the following:

• RESET pin

• RSCTRL register in PLLCTL

• Watchdog timer

• Emulation

All the above initiators, by default, are configured to act as a hard reset. Except emulation, all the other three initiators can be configured as soft resets in the RSCFG register in PLLCTL.

The following sequence must be followed during a hard reset:

1. The RESET pin is pulled active low for a minimum of 24 input clock cycles. During this time, the

RESET signal is able to propagate to all modules (except those specifically mentioned above). All I/O are Hi-Z for modules affected by RESET, to prevent off-chip contention during the warm reset.

2. Once all logic is reset, RESETSTAT is driven active to denote that the device is in reset.

3. The RESET pin can now be released. A minimal device initialization begins to occur. Note that configuration pins are not re-latched and clocking is unaffected within the device.

4. After device initialization is complete, the RESETSTAT pin is de-asserted (driven high).

NOTE

The POR pin should be held inactive (high) throughout the warm reset sequence. Otherwise, if POR is activated (brought low), the minimum POR pulse width must be met. The RESET pin should not be tied together with the POR pin.

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8.4.3

Soft Reset

A soft reset will behave like a hard reset except that the PCIe MMR sticky bits and DDR3 EMIF MMRs contents are retained. POR should also remain de-asserted during this time.

Soft reset is initiated by the following:

• RESET pin

• RSCTRL register in PLLCTL

• Watchdog timer

All the above initiators by default are configured to act as hard reset. Except emulation, all the other three initiators can be configured as soft resets in the RSCFG register in PLLCTL.

In the case of a soft reset, the clock logic or the power control logic of the peripherals are not affected, and, therefore, the enabled/disabled state of the peripherals is not affected. On a soft reset, the DDR3 memory controller registers are not reset. In addition, the DDR3 SDRAM memory content is retained if the user places the DDR3 SDRAM in self-refresh mode before invoking the soft reset.

During a soft reset, the following happens:

1. The RESETSTAT pin goes low to indicate an internal reset is being generated. The reset is allowed to propagate through the system. Internal system clocks are not affected. PLLs also remain locked.

2. After device initialization is complete, the RESETSTAT pin is deasserted (driven high). In addition, the

PLL controllers pause their system clocks for about 8 cycles.

– At this point:

– The state of the peripherals before the soft reset is not changed.

– The I/O pins are controlled as dictated by the DEVSTAT register.

– The DDR3 MMRs and PCIe MMR sticky bits retain their previous values. Only the DDR3

Memory Controller and PCIe state machines are reset by the soft reset.

– The PLL controllers are operating in the mode prior to soft reset. System clocks are unaffected.

The boot sequence is started after the system clocks are restarted. Since the configuration pins are not latched with a system reset, the previous values, as shown in the DEVSTAT register, are used to select the boot mode.

8.4.4

Local Reset

The local reset can be used to reset a particular CorePac without resetting any other chip components.

Local reset is initiated by the following (for more details see the Phase Locked Loop (PLL) for KeyStone

Devices User's Guide ( SPRUGV2 ):

• LRESET pin

• Watchdog timer should cause one of the below based on the setting of the CORESEL[2:0] and

RSTCFG register in the PLL controller. See

Section 8.5.2.8

and

Section 8.8.2

:

– Local Reset

– NMI

– NMI followed by a time delay and then a local reset for the CorePac selected

– Hard Reset by requesting reset via PLLCTL

• LPSC MMRs (memory-mapped registers)

8.4.5

Reset Priority

If any of the above reset sources occur simultaneously, the PLLCTL processes only the highest priority reset request. The reset request priorities are as follows (high to low):

• Power-on reset

• Hard/soft reset

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8.4.6

Reset Controller Register

The reset controller register is part of the PLLCTL MMRs. All C6654 device-specific MMRs are covered in

Section 8.5.3

. For more details on these registers and how to program them, see the Phase Locked Loop

(PLL) for KeyStone Devices User's Guide ( SPRUGV2 ).

8.4.7

Reset Electrical Data / Timing

Table 8-10. Reset Timing Requirements

(1)

(see

Figure 8-4

and

Figure 8-5 )

NO.

1

2 tw(RESETFULL) tw(RESET)

RESETFULL Pin Reset

Pulse width - Pulse width RESETFULL low

Soft/Hard-Reset

Pulse width - Pulse width RESET low

(1) C = 1 / CORECLK(N|P) frequency in ns.

MIN

500C

500C

MAX UNIT

ns ns

Table 8-11. Reset Switching Characteristics Over Recommended Operating Conditions

(1)

(see

Figure 8-4

and

Figure 8-5 )

NO.

MIN MAX

3 td(RESETFULLH-

RESETSTATH)

PARAMETER

RESETFULL Pin Reset

Delay time - RESETSTAT high after RESETFULL high

Unit

50000C ns

4 td(RESETH-RESETSTATH)

Soft/Hard Reset

Delay time - RESETSTAT high after RESET high 50000C ns

(1) C = 1 / CORECLK(N|P) frequency in ns.

POR

1

RESETFULL

RESET

RESETSTAT

3

Figure 8-4. RESETFULL Reset Timing

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POR

RESETFULL

2

RESET

4

RESETSTAT

Figure 8-5. Soft/Hard-Reset Timing

Table 8-12. Boot Configuration Timing Requirements

(1)

(See

Figure 8-6

)

1

NO.

2 tsu(GPIOn-RESETFULL) Setup time - GPIO valid before RESETFULL asserted th(RESETFULL-GPIOn) Hold time - GPIO valid after RESETFULL asserted

(1) C = 1/SYSCLK1 frequency in ns.

MIN

12C

12C

MAX UNIT

ns ns

POR

1

RESETFULL

GPIO[15:0]

2

Figure 8-6. Boot Configuration Timing

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8.5

Main PLL and PLL Controller

This section provides a description of the Main PLL and the PLL controller. For details on the operation of the PLL controller module, see the Phase Locked Loop (PLL) for KeyStone Devices User's Guide

( SPRUGV2 ).

The Main PLL is controlled by the standard PLL controller. The PLL controller manages the clock ratios, alignment, and gating for the system clocks to the device.

Figure 8-7

shows a block diagram of the main

PLL and the PLL controller.

PLLD

PLL xPLLM

CORECLK(N|P)

0

PLLOUT

1

BYPASS

PLL Controller

1

0 1

PLLEN

PLLENSRC

0

0

/1

PLLDIV1

/x

PLLDIV2

PLLDIV3

/3

PLLDIV4

/y

PLLDIV5

PLLDIV6

/64

/6

PLLDIV7

/z

PLLDIV8

/2

/12

PLLDIV9

/3

PLLDIV10

/6

PLLDIV11

Figure 8-7. Main PLL and PLL Controller

SYSCLK1

C66x

CorePac

SYSCLK2

SYSCLK3

SYSCLK4

SYSCLK5

SYSCLK6

SYSCLK7

SYSCLK8

SYSCLK9

SYSCLK10

SYSCLK11

To Switch Fabric,

Peripherals,

Accelerators

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NOTE

PLLM[5:0] bits of the multiplier are controlled by the PLLM register inside the PLL controller and PLLM[12:6] bits are controlled by the chip level MAINPLLCTL0 register. The complete

13-bit value is latched when the GO operation is initiated in the PLL controller. Only

PLLDIV2, PLLDIV5, and PLLDIV8 are programmable on the C6654 device. See the Phase

Locked Loop (PLL) for KeyStone Devices User's Guide ( SPRUGV2 ) for more details on how to program the PLL controller.

The multiplication and division ratios within the PLL and the post-division for each of the chip-level clocks are determined by a combination of this PLL and the PLL Controller. The PLL controller also controls reset propagation through the chip, clock alignment, and test points. The PLL controller monitors the PLL status and provides an output signal indicating when the PLL is locked.

Main PLL power is supplied externally via the Main PLL power-supply pin (AVDDA1). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices

( SPRABI2 ) for detailed recommendations. For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter, maximize the spacing between switching signal traces and the

PLL external components (C1, C2, and the EMI Filter).

The minimum SYSCLK rise and fall times should also be observed. For the input clock timing requirements, see

Section 8.5.5

.

CAUTION

The PLL controller module as described in the Phase Locked Loop (PLL) for

KeyStone Devices User's Guide

SPRUGV2 includes a superset of features, some of which are not supported on the C6654 device. The following sections describe the registers that are supported; it should be assumed that any registers not included in these sections is not supported by the device.

Furthermore, only the bits within the registers described here are supported.

Avoid writing to any reserved memory location or changing the value of reserved bits.

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8.5.1

Main PLL Controller Device-Specific Information

8.5.1.1

Internal Clocks and Maximum Operating Frequencies

The Main PLL, used to drive the CorePacs, the switch fabric, and a majority of the peripheral clocks (all but the DDR3) requires a PLL controller to manage the various clock divisions, gating, and synchronization. The Main PLL’s PLL controller has several SYSCLK outputs that are listed below, along with the clock description. Each SYSCLK has a corresponding divider that divides down the output clock of the PLL. Note that dividers are not programmable unless explicitly mentioned in the description below.

SYSCLK1: Full-rate clock for the CorePac.

SYSCLK2: 1/x-rate clock for CorePac emulation. The default rate for this is 1/3. It is programmable from /1 to /32, where this clock does not violate the max of 350 MHz. The SYSCLK2 can be turned off by software.

SYSCLK3: 1/2-rate clock used to clock the MSMC and DDR EMIF.

SYSCLK4: 1/3-rate clock for the switch fabrics and fast peripherals. The Debug_SS and ETBs use this as well.

SYSCLK5: 1/y-rate clock for the system trace module only. The default rate for this is 1/5. It is configurable and the max configurable clock is 210 MHz and min configurable clock is 32 MHz. The

SYSCLK5 can be turned off by software.

SYSCLK6: 1/64-rate clock. 1/64 rate clock (emif_ptv) used to clock the PVT-compensated buffers for

DDR3 EMIF.

SYSCLK7: 1/6-rate clock for slow peripherals (GPIO, UART, Timer, I

2

C, SPI, EMIF16, McBSP, etc.) and sources the SYSCLKOUT output pin.

SYSCLK8: 1/z-rate clock. This clock is used as slow_sysclk in the system. Default is 1/64. It is programmable from /24 to /80.

SYSCLK9: 1/12-rate clock for SmartReflex.

• • SYSCLK11: 1/6-rate clock for PSC only.

Only SYSCLK2, SYSCLK5, and SYSCLK8 are programmable on theC6654 device.

NOTE

In case any of the other programmable SYSCLKs are set slower than 1/64 rate, then

SYSCLK8 (SLOW_SYSCLK) needs to be programmed to either match, or be slower than, the slowest SYSCLK in the system.

8.5.1.2

Main PLL Controller Operating Modes

The Main PLL controller has two modes of operation: bypass mode and PLL mode. The mode of operation is determined by BYPASS bit of the PLL Secondary Control Register (SECCTL). In PLL mode,

SYSCLK1 is generated from the PLL output using the values set in PLLM and PLLD bit fields in the

MAINPLLCTL0 Register. In bypass mode, PLL input is fed directly out as SYSCLK1.

All hosts must hold off accesses to the DSP while the frequency of its internal clocks is changing. A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed.

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8.5.1.3

Main PLL Stabilization, Lock, and Reset Times

The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device powerup. The PLL should not be operated until this stabilization time has elapsed.

The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the

Main PLL reset time value, see

Table 8-13 .

The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). The Main

PLL lock time is given in

Table 8-13 .

Table 8-13. Main PLL Stabilization, Lock, and Reset Times

PLL stabilization time

PLL lock time

PLL reset time

(1) PLLD is the value in PLLD bit fields of MAINPLLCTL0 register

(2) C = SYSCLK1(N|P) cycle time in ns.

MIN

100

1000

TYP MAX UNIT

µs

500 ×(PLLD

(1)

+1) × C

(2) ns

8.5.2

PLL Controller Memory Map

The memory map of the PLL controller is shown in

Table 8-14

. C6654-specific PLL Controller register definitions can be found in the sections following

Table 8-14

. For other registers in the table, see the

Phase Locked Loop (PLL) for KeyStone Devices User's Guide ( SPRUGV2 ).

CAUTION

Note that only registers documented here are accessible on the C6654. Other addresses in the PLL controller memory map including the reserved registers should not be modified. Furthermore, only the bits within the registers described here are supported. Avoid writing to any reserved memory location or changing the value of reserved bits. It is recommended to use read-modify-write sequence to make any changes to the valid bits in the register.

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HEX ADDRESS RANGE

0231 0000 - 0231 00E3

0231 00E4

0231 00E8

0231 00EC

0231 00F0

0231 00F0 - 0231 00FF

0231 0100

0231 0104

0231 0108

0231 010C

0231 0110

0231 0114

0231 0118

0231 011C

0231 0120

0231 0124

0231 0128

0231 012C - 0231 0134

0231 0138

0231 013C

0231 0140

0231 0144

0231 0148

0231 014C

0231 0150

0231 0154 - 0231 015C

0231 0160

0231 0164

0231 0168

0231 016C

0231 0170

0231 0174 - 0231 0193

0231 0194 - 0231 01FF

Table 8-14. PLL Controller Registers (Including Reset Controller)

-

FIELD

RSTYPE

RSTCTRL

RSTCFG

RSISO

-

PLLCTL

-

-

SECCTL

-

PLLM

-

-

PLLDIV1

PLLDIV2

PLLDIV3

-

PLLCMD

PLLSTAT

ALNCTL

DCHANGE

CKEN

CKSTAT

SYSTAT

-

PLLDIV4

PLLDIV5

PLLDIV6

PLLDIV7

-

PLLDIV8

PLLDIV9 - PLLDIV16

REGISTER NAME

Reserved

Reset Type Status Register (Reset Controller)

Software Reset Control Register (Reset Controller)

Reset Configuration Register (Reset Controller)

Reset Isolation Register (Reset Controller)

Reserved

PLL Control Register

Reserved

PLL Secondary Control Register

Reserved

PLL Multiplier Control Register

Reserved

Reserved

PLL Controller Divider 2 Register

Reserved

Reserved

Reserved

Reserved

PLL Controller Command Register

PLL Controller Status Register

PLL Controller Clock Align Control Register

PLLDIV Ratio Change Status Register

Reserved

Reserved

SYSCLK Status Register

Reserved

Reserved

PLL Controller Divider 5 Register

Reserved

Reserved

PLL Controller Divider 8 Register

Reserved

Reserved

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8.5.2.1

PLL Secondary Control Register (SECCTL)

The PLL Secondary Control Register contains extra fields to control the Main PLL and is shown in

Figure 8-8

and described in

Table 8-15

.

Figure 8-8. PLL Secondary Control Register (SECCTL)

31 24

Reserved

R-0000 0000

Legend: R/W = Read/Write; R = Read only; -n = value after reset

23

BYPASS

RW-0

22 19

OUTPUT_DIVIDE

RW-0001

18 0

Reserved

RW-001 0000 0000 0000 0000

Table 8-15. PLL Secondary Control Register (SECCTL) Field Descriptions

Bit Field

31-24 Reserved

Description

Reserved

23 BYPASS Main PLL Bypass Enable

• 0 = Main PLL Bypass disabled.

• 1 = Main PLL Bypass enabled.

22-19 OUTPUT_DIVIDE Output Divider ratio bits.

• 0h = ÷1. Divide frequency by 1.

• 1h = ÷2. Divide frequency by 2.

• 2h - Fh = Reserved.

18-0 Reserved Reserved

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8.5.2.2

PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)

The PLL Controller Divider Registers (PLLDIV2, PLLDIV5, and PLLDIV8) are shown in

Figure 8-9

and described in

Table 8-16 . The default values of the RATIO field on a reset for PLLDIV2, PLLDIV5, and

PLLDIV8 are different and mentioned in the footnote of

Figure 8-9

.

Figure 8-9. PLL Controller Divider Register (PLLDIVn)

14 31 16

Reserved

R-0

Legend: R/W = Read/Write; R = Read only; -n = value after reset

15

Dn

(1)

EN

R/W-1

(1) D2EN for PLLDIV2; D5EN for PLLDIV5; D8EN for PLLDIV8

(2) n=02h for PLLDIV2; n=04h for PLLDIV5; n=3Fh for PLLDIV8

Reserved

R-0

8 7

R/W-n

(2)

RATIO

0

Bit Field

31-16 Reserved

15 DnEN

14-8

7-0

Reserved

RATIO

Table 8-16. PLL Controller Divider Register (PLLDIVn) Field Descriptions

Description

Reserved.

Divider Dn enable bit. (see footnote of

Figure 8-9 )

• 0 = Divider n is disabled.

• 1 = No clock output. Divider n is enabled.

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

Divider ratio bits. (see footnote of

Figure 8-9

)

• 0h = ÷1. Divide frequency by 1.

• 1h = ÷2. Divide frequency by 2.

• 2h = ÷3. Divide frequency by 3.

• 3h = ÷4. Divide frequency by 4.

• 4h - 4Fh = ÷5 to ÷80. Divide frequency by 5 to divide frequency by 80.

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8.5.2.3

PLL Controller Clock Align Control Register (ALNCTL)

The PLL controller clock align control register (ALNCTL) is shown in

Figure 8-10

and described in

Table 8-

17 .

Figure 8-10. PLL Controller Clock Align Control Register (ALNCTL)

31

Reserved

R-0

8 7

ALN8

R/W-1

6

Reserved

R-0

Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value

5 4

ALN5

R/W-1

3 2

Reserved

R-0

1

ALN2

R/W-1

0

Reserved

R-0

Bit

31-8

7

6-5

4

3-2

1

0

Field

Reserved

ALN8

Reserved

ALN5

Reserved

ALN2

Table 8-17. PLL Controller Clock Align Control Register (ALNCTL) Field Descriptions

Reserved

Description

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

SYSCLKn alignment. Do not change the default values of these fields.

• 0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set.

• 1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1. The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

SYSCLKn alignment. Do not change the default values of these fields.

• 0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set.

• 1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1. The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

SYSCLKn alignment. Do not change the default values of these fields.

• 0 = Do not align SYSCLKn to other SYSCLKs during GO operation. If SYSn in DCHANGE is set, SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set.

• 1 = Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set and SYSn in DCHANGE is 1. The SYSCLKn rate is set to the ratio programmed in the RATIO bit in PLLDIVn.

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

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8.5.2.4

PLLDIV Divider Ratio Change Status Register (DCHANGE)

When a different ratio is written to the PLLDIVn registers, the PLLCTL flags the change in the DCHANGE

Status Register. During the GO operation, the PLL controller will change only the divide ratio of the

SYSCLKs with the bit set in DCHANGE. Note that the ALNCTL Register determines if that clock also needs to be aligned to other clocks. The PLLDIV divider ratio change status register is shown in

Figure 8-

11

and described in

Table 8-18

.

Figure 8-11. PLLDIV Divider Ratio Change Status Register (DCHANGE)

31

Reserved

R-0

8 7

SYS8

R/W-0

6

Reserved

R-0

Legend: R/W = Read/Write; R = Read only; -n = value after reset, for reset value

5 4

SYS5

R/W-0

3 2

Reserved

R-0

1

SYS2

R/W-0

0

Reserved

R-0

Bit

31-8

7

6-5

4

3-2

1

0

Field

Reserved

SYS8

Reserved

SYS5

Reserved

SYS2

Table 8-18. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions

Reserved

Description

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

Identifies when the SYSCLKn divide ratio has been modified.

• 0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.

• 1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

Identifies when the SYSCLKn divide ratio has been modified.

• 0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.

• 1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

Identifies when the SYSCLKn divide ratio has been modified.

• 0 = SYSCLKn ratio has not been modified. When GOSET is set, SYSCLKn will not be affected.

• 1 = SYSCLKn ratio has been modified. When GOSET is set, SYSCLKn will change to the new ratio.

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

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8.5.2.5

SYSCLK Status Register (SYSTAT)

The SYSCLK Status Register (SYSTAT) shows the status of SYSCLK[11:1]. SYSTAT is shown in

Figure 8-12

and described in

Table 8-19 .

Figure 8-12. SYSCLK Status Register (SYSTAT)

31

Reserved

11 10 9 8 7 6 5 4 3 2 1 0

R-n

SYS11 SYS10 SYS9ON SYS8ON SYS7ON SYS6ON SYS5ON SYS4ON SYS3ON SYS2ON SYS1ON

ON ON

R-1 R-1 R-1 R-1

Legend: R/W = Read/Write; R = Read only; -n = value after reset

R-1 R-1 R-1 R-1 R-1 R-1 R-1

Table 8-19. SYSCLK Status Register (SYSTAT) Field Descriptions

Bit Field Description

31-11 Reserved

10-0

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

SYS[N

(1)

]ON SYSCLK[N] on status.

• 0 = SYSCLK[N] is gated.

• 1 = SYSCLK[N] is on.

(1) Where N = 1, 2, 3,....N (Not all these output clocks may be used on a specific device. For more information, see the device-specific data manual)

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8.5.2.6

Reset Type Status Register (RSTYPE)

The Reset Type Status (RSTYPE) Register latches the cause of the last reset. If multiple reset sources occur simultaneously, this register latches the highest priority reset source. The Reset Type Status

Register is shown in

Figure 8-13

and described in

Table 8-20

.

Figure 8-13. Reset Type Status Register (RSTYPE)

31

Reserved

R-0

29 28

EMU-

RST

R-0

27

Reserved

R-0

Legend: R = Read only; -n = value after reset

12 11

WDRST[N]

R-0

8 7

Reserved

3

R-0

2 1

PLLCTRL RESET

RST

R-0 R-0

0

POR

R-0

Bit Field

31-29 Reserved

28 EMU-RST

27-12 Reserved

11 WDRST3

10

9

8

7-3

2

1

0

WDRST2

WDRST1

WDRST0

Reserved

PLLCTLRST

RESET

POR

Table 8-20. Reset Type Status Register (RSTYPE) Field Descriptions

Description

Reserved. Read only. Always reads as 0. Writes have no effect.

Reset initiated by emulation.

• 0 = Not the last reset to occur.

• 1 = The last reset to occur.

Reserved. Read only. Always reads as 0. Writes have no effect.

Reset initiated by watchdog timer[N].

• 0 = Not the last reset to occur.

• 1 = The last reset to occur.

Reset initiated by watchdog timer[N].

• 0 = Not the last reset to occur.

• 1 = The last reset to occur.

Reset initiated by watchdog timer[N].

• 0 = Not the last reset to occur.

• 1 = The last reset to occur.

Reset initiated by watchdog timer[N].

• 0 = Not the last reset to occur.

• 1 = The last reset to occur.

Reserved. Read only. Always reads as 0. Writes have no effect.

Reset initiated by PLLCTL.

• 0 = Not the last reset to occur.

• 1 = The last reset to occur.

RESET reset.

• 0 = RESET was not the last reset to occur.

• 1 = RESET was the last reset to occur.

Power-on reset.

• 0 = Power-on reset was not the last reset to occur.

• 1 = Power-on reset was the last reset to occur.

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8.5.2.7

Reset Control Register (RSTCTRL)

This register contains a key that enables writes to the MSB of this register and the RSTCFG Register. The key value is 0x5A69. A valid key will be stored as 0x000C, any other key value is invalid. When the

RSTCTRL or the RSTCFG is written, the key is invalidated. Every write must be set up with a valid key.

The Software Reset Control Register (RSTCTRL) is shown in

Figure 8-14

and described in

Table 8-21 .

Figure 8-14. Reset Control Register (RSTCTRL)

17 15 31

Reserved

R-0x0000

Legend: R = Read only; -n = value after reset;

(1) Writes are conditional based on valid key.

16

SWRST

R/W-0x

(1)

KEY

R/W-0x0003

0

Bit Field

31-17 Reserved

16 SWRST

15-0 KEY

Table 8-21. Reset Control Register (RSTCTRL) Field Descriptions

Description

Reserved.

Software reset

• 0 = Reset

• 1 = Not reset

Key used to enable writes to RSTCTRL and RSTCFG.

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8.5.2.8

Reset Configuration Register (RSTCFG)

This register is used to configure the type of reset initiated by RESET, watchdog timer and the PLL controller’s RSTCTRL Register; i.e., a hard reset or a soft reset. By default, these resets will be hard resets. The Reset Configuration Register (RSTCFG) is shown in

Figure 8-15

and described in

Table 8-22 .

Figure 8-15. Reset Configuration Register (RSTCFG)

31 14 13

Reserved

R-0

PLLCTLRST

TYPE

R/W-0

(2)

Legend: R = Read only; R/W = Read/Write; -n = value after reset

12

RESETTYPE

R/W-0

2

11

Reserved

R-0

4 3

WDTYPE[N

R/W-0

2

(1)

]

(1) Where N = 1, 2, 3,....N (Not all these output may be used on a specific device. For more information, see the device-specific data manual)

(2) Writes are conditional based on valid key. For details, see

Section 8.5.2.7

.

0

Bit Field

31-14 Reserved

13 PLLCTLRSTTYPE

12

11-4 Reserved

3 WDTYPE3

2

1

0

RESETTYPE

WDTYPE2

WDTYPE1

WDTYPE0

Table 8-22. Reset Configuration Register (RSTCFG) Field Descriptions

Description

Reserved.

PLL controller initiates a software-driven reset of type:

• 0 = Hard reset (default)

• 1 = Soft reset

RESET initiates a reset of type:

• 0 = Hard Reset (default)

• 1 = Soft Reset

Reserved.

Watchdog timer [N] initiates a reset of type:

• 0 = Hard Reset (default)

• 1 = Soft Reset

Watchdog timer [N] initiates a reset of type:

• 0 = Hard Reset (default)

• 1 = Soft Reset

Watchdog timer [N] initiates a reset of type:

• 0 = Hard Reset (default)

• 1 = Soft Reset

Watchdog timer [N] initiates a reset of type:

• 0 = Hard Reset (default)

• 1 = Soft Reset

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8.5.2.9

Reset Isolation Register (RSISO)

This register is used to select the module clocks that must maintain their clocking without pausing through non power-on reset. Setting any of these bits effectively blocks reset to all PLLCTL registers in order to maintain current values of PLL multiplier, divide ratios, and other settings. Along with setting module specific bit in RSISO, the corresponding MDCTLx[12] bit also needs to be set in PSC to reset-isolate a particular module. For more information on MDCTLx Register see the Power Sleep Controller (PSC) for

KeyStone Devices User's Guide ( SPRUGV4 ). The Reset Isolation Register (RSTCTRL) is shown below.

Figure 8-16. Reset Isolation Register (RSISO)

7 31 10

Reserved

R-0

Legend: R = Read only; R/W = Read/Write; -n = value after reset

9

Reserved

R/W-0

8

SRISO

R/W-0

Reserved

R-0

0

9

8

Bit Field

31-10 Reserved

Reserved

SRISO

7-0 Reserved

Table 8-23. Reset Isolation Register (RSISO) Field Descriptions

Description

Reserved.

Reserved.

Isolate SmartReflex

• 0 = Not reset isolated

• 1 = Reset Isolated

Reserved.

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8.5.3

Main PLL Control Register

The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) along with the PLL controller for its configuration. These MMRs exist inside the Bootcfg space. To write to these registers, software should go through an unlocking sequence using KICK0/KICK1 registers. For valid configurable values into the MAINPLLCTL0 and MAINPLLCTL1 Registers, see

Section 3.6

. See

Section 4.3.4

for the address location of the registers and locking and unlocking sequences for accessing the registers. The registers are reset on POR only.

Figure 8-17. Main PLL Control Register 0 (MAINPLLCTL0)

19 18 12 31 24 23

BWADJ[7:0]

RW-0000 0101

Reserved

RW-0000 0

Legend: RW = Read/Write; -n = value after reset

PLLM[12:6]

RW-0000000

11 6

Reserved

RW-000000

5 0

PLLD

RW-000000

Bit Field

31-24 BWADJ[7:0]

23-19 Reserved

18-12 PLLM[12:6]

11-6 Reserved

5-0 PLLD

Table 8-24. Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions

Description

BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) -1

Reserved

A 13-bit bus that selects the values for the multiplication factor (see Note below)

Reserved

A 6-bit bus that selects the values for the reference divider

Figure 8-18. Main PLL Control Register 1 (MAINPLLCTL1)

7 31

Reserved

RW-0000000000000000000000000

Legend: RW = Read/Write; -n = value after reset

6

ENSAT

RW-0

5 4

Reserved

RW-00

3

BWADJ[11:8]

RW-0000

0

Bit Field

31-7 Reserved

6

5-4

3-0

ENSAT

Reserved

BWADJ[11:8]

Table 8-25. Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions

Description

Reserved

Needs to be set to 1 for proper operation of PLL

Reserved

BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) -1

NOTE

PLLM[5:0] bits of the multiplier are controlled by the PLLM Register inside the PLL controller and PLLM[12:6] bits are controlled by the MAINPLLCTL0 chip-level register. The

MAINPLLCTL0 Register PLLM[12:6] bits should be written just before writing to the PLLM

Register PLLM[5:0] bits in the controller to have the complete 13-bit value latched when the

GO operation is initiated in the PLL controller. See the Phase Locked Loop (PLL) for

KeyStone Devices User's Guide ( SPRUGV2 ) for the recommended programming sequence.

Output divide ratio and bypass enable/disable of the Main PLL is controlled by the SECCTL

Register in the PLL Controller. See the

Section 8.5.2.1

for more details.

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8.5.4

Main PLL and PLL Controller Initialization Sequence

See the Phase Locked Loop (PLL) for KeyStone Devices User's Guide ( SPRUGV2 ) for details on the initialization sequence for Main PLL and PLL Controller.

8.5.5

Main PLL Controller/PCIe Clock Input Electrical Data/Timing

Table 8-26. Main PLL Controller/PCIe Clock Input Timing Requirements

1

1

3

3

4

2

2

1

1

3

(see

Figure 8-19

and

Figure 8-20 )

4

5

5

2

2

3

4

4

5

5

5

5

NO.

MIN MAX UNIT

tc(CORCLKN) tc(CORECLKP) tw(CORECLKN)

CORECLK[P:N]

Cycle time _ CORECLKN cycle time

Cycle time _ CORECLKP cycle time

Pulse width _ CORECLKN high tw(CORECLKN) tw(CORECLKP)

Pulse width _ CORECLKN low

Pulse width _ CORECLKP high tw(CORECLKP) Pulse width _ CORECLKP low tr(CORECLK_250mv) Transition time _ CORECLK differential rise time (250mV)

3.2

3.2

0.45*tc(CORECLKP)

50

25

25

0.45*tc(CORECLKN) 0.55*tc(CORECLKN)

0.45*tc(CORECLKN) 0.55*tc(CORECLKN)

0.45*tc(CORECLKP) 0.55*tc(CORECLKP)

0.55*tc(CORECLKP)

350 ps tf(CORECLK_250mv) Transition time _ CORECLK differential fall time (250 mV) tj(CORECLKN) tj(CORECLKP)

Jitter, peak_to_peak _ periodic CORECLKN

Jitter, peak_to_peak _ periodic CORECLKP

50 350

SRIOSGMIICLK[P:N]

tc(SRIOSGMIICLKN) Cycle time _ SRIOSGMIICLKN cycle time tc(SRIOSGMIICLKP) Cycle time _ SRIOSGMIICLKP cycle time tw(SRIOSGMIICLKN) Pulse with _ SRIOSGMIICLKN high tw(SRIOSGMIICLKN) Pulse width _ SRIOSGMIICLKN low

3.2 or 4 or 6.4

3.2 or 4 or 6.4

0.45*tc(SRIOSGMIICL 0.55*tc(SRIOSGMIICL

KN) KN)

0.45*tc(SRIOSGMIICL 0.55*tc(SRIOSGMIICL

KN) KN) tw(SRIOSGMIICLKP) Pulse width _ SRIOSGMIICLKP high tw(SRIOSGMIICLKP) Pulse width _ SRIOSGMIICLKP low

100

100

0.45*tc(SRIOSGMIICL 0.55*tc(SRIOSGMIICL

KP) KP)

0.45*tc(SRIOSGMIICL 0.55*tc(SRIOSGMIICL

KP) KP) tr(SRIOSGMIICLK_25 Transition time _ SRIOSGMIICLK differential

0mv) rise time (250 mV) tf(SRIOSGMIICLK_250 Transition time _ SRIOSGMIICLK differential mv) fall time (250 mV) tj(SRIOSGMIICLKN) Jitter, peak_to_peak _ periodic

SRIOSGMIICLKN tj(SRIOSGMIICLKP) Jitter, peak_to_peak _ periodic

SRIOSGMIICLKP

50

50

4

350

350

4 ps ps ps ns ns ns ns ns ns ps ps ps,RMS ps,RMS tj(SRIOSGMIICLKN) tj(SRIOSGMIICLKP)

Jitter, peak_to_peak _ periodic

SRIOSGMIICLKN (SRIO not used)

Jitter, peak_to_peak _ periodic

SRIOSGMIICLKP (SRIO not used)

8

8 ps,RMS ps,RMS ns ns ns ns ns ns

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Table 8-26. Main PLL Controller/PCIe Clock Input Timing Requirements (continued)

(see

Figure 8-19

and

Figure 8-20 )

NO.

3

2

1

1

2

3

4

4

5

5 tc(PCIECLKN) tc(PCIECLKP) tw(PCIECLKN) tw(PCIECLKN) tw(PCIECLKP) tw(PCIECLKP) tr(PCIECLK_250mv) tf(PCIECLK_250mv) tj(PCIECLKN) tj(PCIECLKP)

PCIECLK[P:N]

Cycle time _ PCIECLKN cycle time

Cycle time _ PCIECLKP cycle time

Pulse width _ PCIECLKN high

Pulse width _ PCIECLKN low

Pulse width _ PCIECLKP high

Pulse width _ PCIECLKP low

Transition time _ PCIECLK differential rise time (250 mV)

Transition time _ PCIECLK differential fall time (250 mV)

Jitter, peak_to_peak _ periodic PCIECLKN

Jitter, peak_to_peak _ periodic PCIECLKP

MIN

3.2

3.2

0.45*tc(PCIECLKN)

0.45*tc(PCIECLKN)

0.45*tc(PCIECLKP)

0.45*tc(PCIECLKP)

50

50

MAX UNIT

10

10

0.55*tc(PCIECLKN)

0.55*tc(PCIECLKN)

0.55*tc(PCIECLKP)

0.55*tc(PCIECLKP)

350

350 ps ps

4 ps,RMS

4 ps,RMS ns ns ns ns ns ns

1

2 3

<CLK_NAME>CLKN

<CLK_NAME>CLKP

4

5

Figure 8-19. Main PLL Controller/PCIe Clock Input Timing

peak-to-peak differential input voltage (250mV to 2 V)

0 250mV peak-to-peak for the 250mV peak-to-peak centered at zero crossing

Figure 8-20. Main PLL Clock Input Transition Time

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8.6

DDR3 PLL

The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on reset, the DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and used.

DDR3 PLL power is supplied externally via the Main PLL power-supply pin (AVDDA2). An external EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone Devices

( SPRABI2 ). For the best performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or components other than those shown. For reduced

PLL jitter, maximize the spacing between switching signal traces and the PLL external components (C1,

C2, and the EMI Filter).

Figure 8-21

shows the DDR3 PLL.

PLLD

DDR3 PLL xPLLM

DDRCLK(N|P)

0

PLLOUT

DDR3

PHY

1

BYPASS

Figure 8-21. DDR3 PLL Block Diagram

8.6.1

DDR3 PLL Control Register

The DDR3 PLL, which is used to drive the DDR PHY for the EMIF, does not use a PLL controller. The

DDR3 PLL can be controlled using the DDR3PLLCTL0 and DDR3PLLCTL1 Registers located in the

Bootcfg module. These MMRs exist inside the Bootcfg space. To write to these registers, software should go through an un-locking sequence using the KICK0/KICK1 registers. For suggested configurable values, see

Section 4.3.4

for the address location of the registers and locking and unlocking sequences for accessing the registers. This register is reset on POR only.

Figure 8-22. DDR3 PLL Control Register 0 (DDR3PLLCTL0)

(1)

31

BWADJ[7:0]

RW,+0000 1001

24 23

BYPASS

RW,+0

Legend: RW = Read/Write; -n = value after reset

22 19

Reserved

RW,+0001

18

PLLM

RW,+0000000010011

6 5 0

PLLD

RW,+000000

(1) This register is Reset on POR only. The regreset, reset and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn, regpwrdn, bgpwrdn are all tied to common pll0_ctrl_to_pll_pwrdn.

Bit Field

31-24 BWADJ[7:0]

23 BYPASS

22-19 Reserved

18-6 PLLM

5-0 PLLD

Table 8-27. DDR3 PLL Control Register 0 Field Descriptions

Description

BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. The combination

(BWADJ[11:0]) should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ

= ((PLLM+1)>>1) -1

Enable bypass mode

• 0 = Bypass disabled

• 1 = Bypass enabled

Reserved

A 13-bit bus that selects the values for the multiplication factor

A 6-bit bus that selects the values for the reference divider

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Figure 8-23. DDR3 PLL Control Register 1 (DDR3PLLCTL1)

12 7 31

Reserved

RW-000000000000000000

14 13

PLLRST

RW-0

Legend: RW = Read/Write; -n = value after reset

Reserved

RW-000000

6

ENSAT

RW-0

5 4

Reserved

R-0

3

BWADJ[11:8]

RW-0000

0

Bit Field

31-14 Reserved

13 PLLRST

12-7 Reserved

6 ENSAT

5-4

3-0

Reserved

BWADJ[11:8]

Table 8-28. DDR3 PLL Control Register 1 Field Descriptions

Description

Reserved

PLL reset bit.

• 0 = PLL reset is released.

• 1 = PLL reset is asserted.

Reserved

Needs to be set to 1 for proper operation of the PLL

Reserved

BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) -1

8.6.2

DDR3 PLL Device-Specific Information

As shown in

Figure 8-21 , the output of DDR3 PLL (PLLOUT) is divided by 2 and directly fed to the DDR3

memory controller. The DDR3 PLL is affected by power-on reset. During power-on resets, the internal clocks of the DDR3 PLL are affected as described in

Section 8.4

. The DDR3 PLL is unlocked only during

the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.

8.6.3

DDR3 PLL Initialization Sequence

See the Phase Locked Loop (PLL) for KeyStone Devices User's Guide ( SPRUGV2 ) for details on the initialization sequence for DDR3 PLL.

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8.6.4

DDR3 PLL Input Clock Electrical Data/Timing

Table 8-29. DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements

3

2

1

1

2

3

4

4

5

5

(see

Figure 8-24

and

Figure 8-20 )

NO

Cycle time _ DDRCLKN cycle time

Cycle time _ DDRCLKP cycle time

Pulse width _ DDRCLKN high

Pulse width _ DDRCLKN low

DDRCLK[P:N]

tc(DDRCLKN) tc(DDRCLKP) tw(DDRCLKN) tw(DDRCLKN) tw(DDRCLKP) Pulse width _ DDRCLKP high tw(DDRCLKP) Pulse width _ DDRCLKP low tr(DDRCLK_250mv) Transition time _ DDRCLK differential rise time (250 mV) tf(DDRCLK_250mv) Transition time _ DDRCLK differential fall time (250 mV) tj(DDRCLKN) Jitter, peak_to_peak _ periodic DDRCLKN tj(DDRCLKP) Jitter, peak_to_peak _ periodic DDRCLKP

MIN MAX UNIT

3.2

3.2

25

25

0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN)

0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN)

0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP)

0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP)

50 350

50 350

0.025*tc(DDRCLKN)

0.025*tc(DDRCLKP) ns ns ns ns ns ns ps ps ps ps

1

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SPRS841B – MARCH 2012 – REVISED APRIL 2015

2 3

DDRCLKN

DDRCLKP

4

Figure 8-24. DDR3 PLL DDRCLK Timing

5

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8.7

Enhanced Direct Memory Access (EDMA3) Controller

The primary purpose of the EDMA3 is to service user-programmed data transfers between two memorymapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (e.g., data movement between external memory and internal memory), performs sorting or subframe extraction of various data structures, services event driven peripherals, and offloads data transfers from the device

CPU.

There is one EDMA Channel Controller on the C6654 device: EDMA3_CC. It has four transfer controllers:

TC0, TC1, TC2, and TC3. In the context of this document, TCx associated with CC is referred to as

EDMA3_CC_TCx. Each of the transfer controllers has a direct connection to the switch fabric.

Section 5.2

lists the peripherals that can be accessed by the transfer controllers.

The EDMA3 Channel Controller includes the following features:

• Fully orthogonal transfer description

– Three transfer dimensions:

• Array (multiple bytes)

• Frame (multiple arrays)

• Block (multiple frames)

– Single event can trigger transfer of array, frame, or entire block

– Independent indexes on source and destination

• Flexible transfer definition:

– Increment or FIFO transfer addressing modes

– Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous transfers, all with no CPU intervention

– Chaining allows multiple transfers to execute with one event

• 512 PaRAM entries

– Used to define transfer context for channels

– Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry

• 64 DMA channels

– Manually triggered (CPU writes to channel controller register), external event triggered, and chain triggered (completion of one transfer triggers another)

• Eight Quick DMA (QDMA) channels

– Used for software-driven transfers

– Triggered upon writing to a single PaRAM set entry

• Four transfer controllers and four event queues with programmable system-level priority

• Interrupt generation for transfer completion and error conditions

• Debug visibility

– Queue watermarking/threshold allows detection of maximum usage of event queues

– Error and status recording to facilitate debug

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8.7.1

EDMA3 Device-Specific Information

The EDMA supports two addressing modes: constant addressing and increment addressing mode.

Constant addressing mode is applicable to a very limited set of use cases. For most applications, increment mode must be used. On the C6654, the EDMA can use constant addressing mode only with the

Enhanced Viterbi-Decoder Coprocessor (VCP) and the Enhanced Turbo Decoder Coprocessor (TCP).

Constant addressing mode is not supported by any other peripheral or internal memory in the device. Note that increment mode is supported by all peripherals, including VCP and TCP. For more information on these two addressing modes, see the Enhanced Direct Memory Access 3 (EDMA3) for KeyStone Devices

User's Guide ( SPRUGS5 ).

For the range of memory addresses that include EDMA3 channel controller (EDMA3_CC) control registers and EDMA3 transfer controller (TC) control register, see

Table 3-2

. For memory offsets and other details on EDMA3_CC and TC control registers entries, see the Enhanced Direct Memory Access 3 (EDMA3) for

KeyStone Devices User's Guide ( SPRUGS5 ).

8.7.2

EDMA3 Channel Controller Configuration

Table 8-30

provides the configuration of the EDMA3 channel controller present on the device.

Table 8-30. EDMA3 Channel Controller Configuration

DESCRIPTION

Number of DMA channels in Channel Controller

Number of QDMA channels

Number of interrupt channels

Number of PaRAM set entries

Number of event queues

Number of Transfer Controllers

Memory Protection Existence

Number of Memory Protection and Shadow Regions

512

4

4

Yes

8

EDMA3 CC

64

8

64

8.7.3

EDMA3 Transfer Controller Configuration

Each transfer controller on a device is designed differently based on considerations like performance requirements, system topology (like main TeraNet bus width, external memory bus width), and so on. The parameters that determine the transfer controller configurations are:

FIFOSIZE: Determines the size in bytes for the data FIFO that is the temporary buffer for the in-flight data. The data FIFO is where the read return data read by the TC read controller from the source endpoint is stored and subsequently written out to the destination endpoint by the TC write controller.

BUSWIDTH: The width of the read and write data buses, in bytes, for the TC read and write controller, respectively. This is typically equal to the bus width of the main TeraNet interface.

Default Burst Size (DBS): The DBS is the maximum number of bytes per read/write command issued by a transfer controller.

DSTREGDEPTH: This determines the number of destination FIFO register set. The number of destination FIFO register set for a transfer controller determines the maximum number of outstanding transfer requests.

All four parameters listed above are specified by the design of the device.

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Table 8-31

provides the configuration of the EDMA3 transfer controller present on the device.

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PARAMETER

FIFOSIZE

BUSWIDTH

DSTREGDEPTH

DBS

Table 8-31. EDMA3 Transfer Controller Configuration

TC0

1024 bytes

16 bytes

4 entries

64 bytes

TC1

512 bytes

16 bytes

4 entries

64 bytes

EDMA3 CC

TC2

512 bytes

16 bytes

4 entries

64 bytes

TC3

1024 bytes

16 bytes

4 entries

64 bytes

8.7.4

EDMA3 Channel Synchronization Events

The EDMA3 supports up to 64 DMA channels for EDMA3_CC that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization events generated by system peripherals. The following tables lists the source of the synchronization event associated with each of the EDMA3_CC DMA channels. On the C6654, the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.

For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured, processed, prioritized, linked, chained, and cleared, etc., see the Enhanced Direct Memory Access 3

(EDMA3) for KeyStone Devices User's Guide ( SPRUGS5 ).

154

Table 8-32. EDMA3_CC Events for C6654

17

18

19

20

21

22

23

24

12

13

14

15

16

7

8

9

10

11

2

3

4

5

6

0

1

EVENT

NUMBER EVENT

Reserved

Reserved

TINT2L

TINT2H

URXEVT

UTXEVT

GPINT0

GPINT1

GPINT2

GPINT3

Reserved

Reserved

Reserved

Reserved

URXEVT_B

UTXEVT_B

SPIINT0

SPIINT1

SEMINT0

SEMINT1

SEMINT2

SEMINT3

TINT4L

TINT4H

TINT5L

EVENT DESCRIPTION

Timer2 interrupt low

Timer2 interrupt high

UART0 receive event

UART0 transmit event

GPIO interrupt

GPIO interrupt

GPIO Interrupt

GPIO interrupt

UART1 receive event

UART1 transmit event

SPI interrupt

SPI interrupt

Semaphore interrupt

Semaphore interrupt

Semaphore interrupt

Semaphore interrupt

Timer4 interrupt low

Timer4 interrupt high

Timer5 interrupt low

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61

62

63

58

59

60

53

54

55

56

57

48

49

50

51

52

43

44

45

46

47

38

39

40

41

42

33

34

35

36

37

28

29

30

31

32

EVENT

NUMBER

25

26

27

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

Table 8-32. EDMA3_CC Events for C6654 (continued)

CIC1_OUT0

CIC1_OUT1

CIC1_OUT2

CIC1_OUT3

CIC1_OUT4

CIC1_OUT5

CIC1_OUT6

CIC1_OUT7

CIC1_OUT8

CIC1_OUT9

CIC1_OUT10

CIC1_OUT11

CIC1_OUT12

CIC1_OUT13

CIC1_OUT14

CIC1_OUT15

CIC1_OUT16

CIC1_OUT17

TETBFULLINT

TETBFULLINT0

TETBFULLINT1

EVENT

TINT5H

TINT6L

TINT6H

TINT7L

TINT7H

SPIXEVT

SPIREVT

I2CREVET

I2CXEVT

TINT3L

TINT3H

MCBSP0_REVT

MCBSP0_XEVT

MCBSP1_REVT

MCBSP1_XEVT

TETBHFULLINT

TETBHFULLINT0

TETBHFULLINT1

EVENT DESCRIPTION

Timer5 interrupt high

Timer6 interrupt low

Timer6 interrupt high

Timer7 interrupt low

Timer7 interrupt high

SPI transmit event

SPI receive event

I2C receive event

I2C transmit event

Timer3 interrupt low

Timer3 interrupt high

McBSP_0 receive event

McBSP_0 transmit event

McBSP_1 receive event

McBSP_1 transmit event

TETB half full interrupt

TETB half full interrupt

TETB half full interrupt

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

Interrupt Controller output

TETB full interrupt

TETB full interrupt

TETB full interrupt

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8.8

Interrupts

8.8.1

Interrupt Sources and Interrupt Controller

The CPU interrupts on the C6654 device are configured through the C66x CorePac Interrupt Controller.

The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs (CPUINT4 - CPUINT15), the CPU exception input (EXCEP), or the advanced emulation logic. The 128 system events consist of both internally-generated events (within the CorePac) and chiplevel events.

Additional system events are routed to each of the C66x CorePacs to provide chip-level events that are not required as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events. In addition, error-class events or infrequently used events are also routed through the system event router to offload the C66x CorePac interrupt selector. This is accomplished through CIC blocks, CIC[1:0]. This is clocked using CPU/6.

The event controllers consist of simple combination logic to provide additional events to the C66x

CorePacs, plus the EDMA3_CC and CIC0 provide 12 additional events as well as 8 broadcast events to the C66x CorePacs. CIC1 provides 18 additional events to EDMA3_CC.

There are a large number of events on the chip level. The chip level CIC provides a flexible way to combine and remap those events. Multiple events can be combined to a single event through chip level

CIC. However, an event can be mapped only to a single event output from the chip level CIC. The chip level CIC also allows the software to trigger system events through memory writes. The broadcast events to C66x CorePacs can be used for synchronization among multiple cores, inter-processor communication purposes, etc. For more details on the CIC features, please refer to the Chip Interrupt Controller (CIC) for

KeyStone Devices User's Guide ( SPRUGW4 ).

NOTE

Modules such as MPU, Tracer, and BOOT_CFG have level interrupts and an EOI handshaking interface. The EOI value is 0 for MPU, Tracer, and BOOT_CFG.

Figure 8-25

shows the C6654 interrupt topology.

58 Reserved Secondary Events

92 Core-only Secondary Events

58 Common Events

CIC0

16 Reserved Secondary Events

102 Primary Events

12 Secondary Events

6 Reserved Primary Events

Core0

8 Broadcast Events from CIC0

58 Common Events

11 Reserved Secondary Events

56 Reserved Secondary Events

46 EDMA3_CC-only

Secondary Events

CIC1

40 Primary Events

18 Secondary Events

6 Reserved Primary Events

Figure 8-25. C6654 Interrupt Topology

EDMA3

CC

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Table 8-33

shows the mapping of system events. For more information on the Interrupt Controller, see the

C66x CorePac User's Guide ( SPRUGW0 ).

Table 8-33. C6654 System Event Inputs — C66x CorePac Primary Interrupts

0

1

INPUT EVENT

NUMBER

2

3

7

8

9

4

5

6

26

27

28

29

30

21

22

23

24

25

34

35

36

31

32

33

14

15

16

17

18

19

20

10

11

12

13

INTERRUPT EVENT

EVT0

EVT1

EVT2

EVT3

TETBHFULLINTn

(1)

TETBFULLINTn

(1)

TETBACQINTn

(1)

TETBOVFLINTn

(1)

TETBUNFLINTn

(1)

EMU_DTDMA

MSMC_mpf_errorn

(2)

EMU_RTDXRX

EMU_RTDXTX

IDMA0

IDMA1

SEMERRn

(3)

SEMINTn

(3)

PCIExpress_MSI_INTn

(4)

PCIExpress_MSI_INTn+4

(4)

MACINTn

(5)

Reserved

Reserved

CIC0_OUT(0+20*n)

(6)

CIC0_OUT(1+20*n)

(6)

CIC0_OUT(2+20*n)

(6)

CIC0_OUT(3+20*n)

(6)

CIC0_OUT(4+20*n)

(6)

CIC0_OUT(5+20*n)

(6)

CIC0_OUT(6+20*n)

(6)

CIC0_OUT(7+20*n)

(6)

CIC0_OUT(8+20*n)

(6)

CIC0_OUT(9+20*n)

(6)

QM_INT_LOW_0

QM_INT_LOW_1

QM_INT_LOW_2

QM_INT_LOW_3

QM_INT_LOW_4

DESCRIPTION

Event combiner 0 output

Event combiner 1 output

Event combiner 2 output

Event combiner 3 output

TETB is half full

TETB is full

Acquisition has been completed

Overflow condition interrupt

Underflow condition interrupt

ECM interrupt for:

• 1. Host scan access

• 2. DTDMA transfer complete

• 3. AET interrupt

Memory protection fault indicators for local core

RTDX receive complete

RTDX transmit complete

IDMA channel 0 interrupt

IDMA channel 1 interrupt

Semaphore error interrupt

Semaphore interrupt

Message signaled interrupt mode

Message signaled interrupt mode

EMAC interrupt

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

QM Interrupt for 0~31 Queues

QM Interrupt for 32~63 Queues

QM Interrupt for 64~95 Queues

QM Interrupt for 96~127 Queues

QM Interrupt for 128~159 Queues

(1) CorePac[n] will receive TETBHFULLINTn, TETBFULLINTn, TETBACQINTn, TETBOVFLINTn, and TETBUNFLINTn.

(2) CorePac[n] will receive MSMC_mpf_errorn.

(3) CorePac[n] will receive SEMINTn and SEMERRn.

(4) CorePac[n] will receive PCIEXpress_MSI_INTn.

(5) CorePac[n] will receive MACINTn/MACRXINTn/MACTXINTn/MACTRESHn.

(6) n is core number.

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INTERRUPT EVENT

QM_INT_LOW_5

QM_INT_LOW_6

QM_INT_LOW_7

QM_INT_LOW_8

QM_INT_LOW_9

QM_INT_LOW_10

QM_INT_LOW_11

QM_INT_LOW_12

QM_INT_LOW_13

QM_INT_LOW_14

QM_INT_LOW_15

QM_INT_HIGH_n

(6)

QM_INT_HIGH_(n+4)

(6)

QM_INT_HIGH_(n+8)

(6)

QM_INT_HIGH_(n+12)

(6)

QM_INT_HIGH_(n+16)

(6)

QM_INT_HIGH_(n+20)

(6)

QM_INT_HIGH_(n+24)

(6)

QM_INT_HIGH_(n+28)

(6)

CIC0_OUT40

CIC0_OUT41

CIC0_OUT42

CIC0_OUT43

CIC0_OUT44

CIC0_OUT45

CIC0_OUT46

CIC0_OUT47

TINTLn

(7)

TINTHn

(7)

TINT2L

TINT2H

TINT3L

TINT3H

PCIExpress_MSI_INTn+2

(4)

PCIExpress_MSI_INTn+6

(4)

GPINT2

GPINT3

MACINTn+2

(5)

MACTXINTn+2

(5)

MACTRESHn+2

(5)

MACRXINTn+2

(5)

GPINT4

GPINT5

GPINT6

GPINT7

GPINT8

Table 8-33. C6654 System Event Inputs — C66x CorePac Primary Interrupts (continued)

70

71

72

73

74

65

66

67

68

69

60

61

62

63

64

55

56

57

58

59

75

76

77

78

79

80

81

82

50

51

52

53

54

45

46

47

48

49

40

41

42

43

44

INPUT EVENT

NUMBER

37

38

39

DESCRIPTION

QM Interrupt for 160~191 Queues

QM Interrupt for 192~223 Queues

QM Interrupt for 224~255 Queues

QM Interrupt for 256~287 Queues

QM Interrupt for 288~319 Queues

QM Interrupt for 320~351 Queues

QM Interrupt for 352~383 Queues

QM Interrupt for 384~415 Queues

QM Interrupt for 416~447 Queues

QM Interrupt for 448~479 Queues

QM Interrupt for 480~511 Queues

QM Interrupt for Queue 704+n

(6)

QM Interrupt for Queue 708+n

(6)

QM Interrupt for Queue 712+n

(6)

QM Interrupt for Queue 716+n

(6)

QM Interrupt for Queue 720+n

(6)

QM Interrupt for Queue 724+n

(6)

QM Interrupt for Queue 728+n

(6)

QM Interrupt for Queue 732+n

(6)

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Interrupt Controller Output

Local timer interrupt low

Local timer interrupt high

Timer2 interrupt low

Timer2 interrupt high

Timer3 interrupt low

Timer3 interrupt high

Message signaled interrupt mode

Message signaled interrupt mode

GPIO interrupt

GPIO interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

(7) CorePac[n] will receive TINTLn and TINTHn.

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Table 8-33. C6654 System Event Inputs — C66x CorePac Primary Interrupts (continued)

111

112

113

114

115

116

117

118

119

106

107

108

109

110

101

102

103

104

105

96

97

98

99

100

91

92

93

94

95

86

87

88

89

90

INPUT EVENT

NUMBER

83

84

85

INTERRUPT EVENT

GPINT9

GPINT10

GPINT11

GPINT12

GPINT13

GPINT14

GPINT15

IPC_LOCAL

GPINTn

(8)

CIC0_OUT(10+20*n)

(6)

CIC0_OUT(11+20*n)

(6)

MACTXINTn

(5)

MACTRESHn

(5)

INTERR

EMC_IDMAERR

Reserved

MACRXINTn

(5)

EFIINTA

EFIINTB

QM_INT_HIGH_(n+2)

(6)

QM_INT_HIGH_(n+6)

(6)

QM_INT_HIGH_(n+10)

(6)

QM_INT_HIGH_(n+14)

(6)

QM_INT_HIGH_(n+18)

(6)

QM_INT_HIGH_(n+22)

(6)

QM_INT_HIGH_(n+26)

(6)

QM_INT_HIGH_(n+30)

(6)

MDMAERREVT

Reserved

Reserved

PMC_ED

Reserved

EDMA3_CC_AETEVT

UMC_ED1

UMC_ED2

PDC_INT

SYS_CMPA

(8) CorePac[n] will receive GPINTn.

DESCRIPTION

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

Inter DSP interrupt from IPCGRn

Local GPIO interrupt

Interrupt Controller Output

Interrupt Controller Output

EMAC interrupt

EMAC interrupt

Dropped CPU interrupt event

Invalid IDMA parameters

EMAC interrupt

EFI Interrupt from side A

EFI Interrupt from side B

QM Interrupt for Queue 706+n

(6)

QM Interrupt for Queue 710+n

(6)

QM Interrupt for Queue 714+n

(6)

QM Interrupt for Queue 718+n

(6)

QM Interrupt for Queue 722+n

(6)

QM Interrupt for Queue 726+n

(6)

QM Interrupt for Queue 730+n

(6)

QM Interrupt for Queue 734+n

(6)

VbusM error event

Single bit error detected during DMA read

EDMA3 CC AET Event

Corrected bit error detected

Uncorrected bit error detected

Power down sleep interrupt

SYS CPU memory protection fault event

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Table 8-33. C6654 System Event Inputs — C66x CorePac Primary Interrupts (continued)

123

124

125

126

127

INPUT EVENT

NUMBER

120

121

122

INTERRUPT EVENT

PMC_CMPA

PMC_DMPA

DMC_CMPA

DMC_DMPA

UMC_CMPA

UMC_DMPA

EMC_CMPA

EMC_BUSERR

DESCRIPTION

PMC CPU memory protection fault event

PMC DMA memory protection fault event

DMC CPU memory protection fault event

DMC DMA memory protection fault event

UMC CPU memory protection fault event

UMC DMA memory protection fault event

EMC CPU memory protection fault event

EMC bus error interrupt

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Table 8-34. CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs)

37

38

39

40

41

32

33

34

35

36

42

43

44

45

46

27

28

29

30

31

22

23

24

25

26

17

18

19

20

21

12

13

14

15

16

7

8

9

5

6

10

11

1

2

3

4

INPUT EVENT# ON CIC SYSTEM INTERRUPT

0 GPINT16

GPINT17

GPINT18

GPINT19

GPINT20

GPINT21

GPINT22

GPINT23

GPINT24

GPINT25

GPINT26

GPINT27

GPINT28

GPINT29

GPINT30

GPINT31

EDMA3_CC_ERRINT

EDMA3_CC_MPINT

EDMA3_TC_ERRINT0

EDMA3_TC_ERRINT1

EDMA3_TC_ERRINT2

EDMA3_TC_ERRINT3

EDMA3_CC_GINT

Reserved

EDMA3_CC_INT0

EDMA3_CC_INT1

EDMA3_CC_INT2

EDMA3_CC_INT3

EDMA3_CC_INT4

EDMA3_CC_INT5

EDMA3_CC_INT6

EDMA3_CC_INT7

MCBSP0_RINT

MCBSP0_XINT

MCBSP0_REVT

MCBSP0_XEVT

MCBSP1_RINT

MCBSP1_XINT

MCBSP1_REVT

MCBSP1_XEVT

UARTINT_B

URXEVT_B

UTXEVT_B

Reserved

Reserved

Reserved

Reserved

DESCRIPTION

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

EDMA3_CC error interrupt

EDMA3_CC memory protection interrupt

EDMA3_CC TC0 error interrupt

EDMA3_CC TC1 error interrupt

EDMA3_CC TC2 error interrupt

EDMA3_CC TC3 error interrupt

EDMA3_CC GINT

EDMA3_CC individual completion interrupt

EDMA3_CC individual completion interrupt

EDMA3_CC individual completion interrupt

EDMA3_CC individual completion interrupt

EDMA3_CC individual completion interrupt

EDMA3_CC individual completion interrupt

EDMA3_CC individual completion interrupt

EDMA3_CC individual completion interrupt

McBSP0 interrupt

McBSP0 interrupt

McBSP0 interrupt

McBSP0 interrupt

McBSP1 interrupt

McBSP1 interrupt

McBSP1 interrupt

McBSP1 interrupt

UART_1 interrupt

UART_1 interrupt

UART_1 interrupt

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Table 8-34. CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (continued)

82

84

85

86

87

88

89

90

78

79

80

81

81

73

74

75

76

77

68

69

70

71

72

63

64

65

66

67

58

59

60

61

62

53

54

55

56

57

INPUT EVENT# ON CIC SYSTEM INTERRUPT

47 Reserved

48

49

50

51

52

PCIEXpress_ERR_INT

PCIEXpress_PM_INT

PCIEXpress_Legacy_INTA

PCIEXpress_Legacy_INTB

PCIEXpress_Legacy_CIC

PCIEXpress_Legacy_INTD

SPIINT0

SPIINT1

SPIXEVT

SPIREVT

I2CINT

I2CREVT

I2CXEVT

Reserved

Reserved

TETBHFULLINT

TETBFULLINT

TETBACQINT

TETBOVFLINT

TETBUNFLINT

91

SEMINT2

SEMINT3

SEMERR2

SEMERR3

Reserved

Tracer_core_0_INTD

Reserved

Reserved

Reserved

Tracer_DDR_INTD

Tracer_MSMC_0_INTD

Tracer_MSMC_1_INTD

Tracer_MSMC_2_INTD

Tracer_MSMC_3_INTD

Tracer_CFG_INTD

Tracer_QM_CFG_INTD

Tracer_QM_DMA_INTD

Tracer_SM_INTD

PSC_ALLINT

Reserved

BOOTCFG_INTD po_vcon_smpserr_intr

MPU0_INTD

(MPU0_ADDR_ERR_INT and

MPU0_PROT_ERR_INT combined)

Reserved

DESCRIPTION

Protocol error interrupt

Power management interrupt

Legacy interrupt mode

Legacy interrupt mode

Legacy interrupt mode

Legacy interrupt mode

SPI interrupt0

SPI interrupt1

Transmit event

Receive event

I

2

C interrupt

I

2

C receive event

I

2

C transmit event

TETB is half full

TETB is full

Acquisition has been completed

Overflow condition occur

Underflow condition occur

Semaphore interrupt

Semaphore interrupt

Semaphore interrupt

Semaphore interrupt

Tracer sliding time window interrupt for individual core

Tracer sliding time window interrupt for DDR3 EMIF1

Tracer sliding time window interrupt for MSMC SRAM bank0

Tracer sliding time window interrupt for MSMC SRAM bank1

Tracer sliding time window interrupt for MSMC SRAM bank2

Tracer sliding time window interrupt for MSMC SRAM bank3

Tracer sliding time window interrupt for CFG0 TeraNet

Tracer sliding time window interrupt for QM_SS CFG

Tracer sliding time window interrupt for QM_SS slave

Tracer sliding time window interrupt for semaphore

Power/sleep controller interrupt

Chip-level MMR error register

SmartReflex VolCon error status

MPU0 addressing violation interrupt and protection violation interrupt.

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Table 8-34. CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (continued)

128

129

130

131

132

133

134

123

124

125

126

127

118

119

120

121

122

113

114

115

116

117

108

109

110

111

112

101

102

103

104

105

105

107

97

98

99

100

INPUT EVENT# ON CIC SYSTEM INTERRUPT

92 MPU1_INTD

(MPU1_ADDR_ERR_INT and

MPU1_PROT_ERR_INT combined)

93

94

95

96

Reserved

MPU2_INTD

(MPU2_ADDR_ERR_INT and

MPU2_PROT_ERR_INT combined)

Reserved

MPU3_INTD

(MPU3_ADDR_ERR_INT and

MPU3_PROT_ERR_INT combined)

Reserved

Reserved

Reserved

Reserved

Reserved

MSMC_mpf_error8

MSMC_mpf_error9

MSMC_mpf_error10

MSMC_mpf_error11

MSMC_mpf_error12

MSMC_mpf_error13

MSMC_mpf_error14

MSMC_mpf_error15

DDR3_ERR

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved po_vp_smpsack_intr

Reserved

Reserved

Reserved

QM_INT_PASS_TXQ_PEND_662

DESCRIPTION

MPU1 addressing violation interrupt and protection violation interrupt.

MPU2 addressing violation interrupt and protection violation interrupt.

MPU3 addressing violation interrupt and protection violation interrupt.

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

DDR3 EMIF error interrupt

Indicating that Volt_Proc receives the r-edge at its smpsack input

Queue manager pend event

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Table 8-34. CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (continued)

175

176

177

178

179

180

166

167

168

169

170

171

172

173

174

161

162

163

164

165

156

157

158

159

160

151

152

153

154

155

146

147

148

149

150

141

142

143

144

145

INPUT EVENT# ON CIC SYSTEM INTERRUPT

135 QM_INT_PASS_TXQ_PEND_663

136

137

138

139

140

QM_INT_PASS_TXQ_PEND_664

QM_INT_PASS_TXQ_PEND_665

QM_INT_PASS_TXQ_PEND_666

QM_INT_PASS_TXQ_PEND_667

QM_INT_PASS_TXQ_PEND_668

QM_INT_PASS_TXQ_PEND_669

QM_INT_PASS_TXQ_PEND_670

Reserved

Reserved

TINT4L

TINT4H

Reserved

Reserved

Reserved

Reserved

TINT5L

TINT5H

TINT6L

TINT6H

Reserved

UPPINT

Reserved

Reserved

Reserved

MSMC_mpf_error2

MSMC_mpf_error3

TINT7L

TINT7H

UARTINT_A

URXEVT_A

UTXEVT_A

EASYNCERR

Tracer_EMIF16

Reserved

MSMC_mpf_error4

MSMC_mpf_error5

MSMC_mpf_error6

MSMC_mpf_error7

MPU4_INTD

(MPU4_ADDR_ERR_INT and

MPU4_PROT_ERR_INT combined)

QM_INT_PASS_TXQ_PEND_671

QM_INT_PKTDMA_0

QM_INT_PKTDMA_1

Reserved

Reserved

Reserved

DESCRIPTION

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Queue manager pend event

Timer4 interrupt low

Timer4 interrupt high

Timer5 interrupt low

Timer5 interrupt high

Timer6 interrupt low

Timer6 interrupt high uPP interrupt

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Timer7 interrupt low

Timer7interrupt high

UART_0 interrupt

UART_0 interrupt

UART_0 interrupt

EMIF16 error interrupt

Tracer sliding time window interrupt for EMIF16

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

MPU4 addressing violation interrupt and protection violation interrupt.

Queue manager pend event

QM interrupt for CDMA starvation

QM interrupt for CDMA starvation

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202

203

204

205

206

207

197

198

199

200

201

192

193

194

195

196

187

188

189

190

191

INPUT EVENT# ON CIC SYSTEM INTERRUPT

181 SmartReflex_intrreq0

182

183

184

185

SmartReflex_intrreq1

SmartReflex_intrreq2

SmartReflex_intrreq3

VPNoSMPSAck

186

Table 8-34. CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (continued)

VPEqValue

DESCRIPTION

SmartReflex sensor interrupt

SmartReflex sensor interrupt

SmartReflex sensor interrupt

SmartReflex sensor interrupt

VPVOLTUPDATE has been asserted but SMPS has not been responded to in a defined time interval

SRSINTERUPT is asserted, but the new voltage is not different from the current SMPS voltage

The new voltage required is equal to or greater than MaxVdd.

The new voltage required is equal to or less than MinVdd.

Indicating that the FSM of voltage processor is in idle.

Indicating that the average frequency error is within the desired limit.

VPMaxVdd

VPMinVdd

VPINIDLE

VPOPPChangeDone

Reserved

MACINT4

MACRXINT4

MACTXINT4

MACTRESH4

MACINT5

MACRXINT5

MACTXINT5

MACTRESH5

MACINT6

MACRXINT6

MACTXINT6

MACTRESH6

MACINT7

MACRXINT7

MACTXINT7

MACTRESH7

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

EMAC interrupt

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Table 8-35. CIC1 Event Inputs (Secondary Events for EDMA3_CC)

GPINT18

GPINT19

GPINT20

GPINT21

Reserved

QM_INT_HIGH_16

QM_INT_HIGH_17

QM_INT_HIGH_18

QM_INT_HIGH_19

QM_INT_HIGH_20

QM_INT_HIGH_21

QM_INT_HIGH_22

QM_INT_HIGH_23

QM_INT_HIGH_24

QM_INT_HIGH_25

QM_INT_HIGH_26

QM_INT_HIGH_27

QM_INT_HIGH_28

QM_INT_HIGH_29

QM_INT_HIGH_30

QM_INT_HIGH_31

Reserved

Reserved

Reserved

Reserved

Reserved

Tracer_core_0_INTD

SYSTEM INTERRUPT

GPINT8

GPINT9

GPINT10

GPINT11

GPINT12

GPINT13

GPINT14

GPINT15

Reserved

Reserved

TETBACQINT

Reserved

Reserved

TETBACQINT0

Reserved

Reserved

Reserved

GPINT16

GPINT17

34

35

36

37

38

29

30

31

32

33

42

43

44

45

39

40

41

24

25

26

27

28

19

20

21

22

23

14

15

16

17

18

9

10

11

12

13

4

5

6

7

8

2

3

0

1

INPUT EVENT # ON

CIC DESCRIPTION

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

System TETB acquisition has been completed

TETB0 acquisition has been completed

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

Tracer sliding time window interrupt for individual core

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Table 8-35. CIC1 Event Inputs (Secondary Events for EDMA3_CC) (continued)

77

78

79

80

81

82

83

71

72

73

74

75

76

87

88

89

84

85

86

62

63

64

59

60

61

54

55

56

57

58

49

50

51

52

53

INPUT EVENT # ON

CIC

46

47

48

65

66

67

68

69

70

SYSTEM INTERRUPT

Reserved

GPINT22

GPINT23

Tracer_DDR_INTD

Tracer_MSMC_0_INTD

Tracer_MSMC_1_INTD

Tracer_MSMC_2_INTD

Tracer_MSMC_3_INTD

Tracer_CFG_INTD

Tracer_QM_CFG_INTD

Tracer_QM_DMA_INTD

Tracer_SEM_INTD

SEMERR0

SEMERR1

SEMERR2

SEMERR3

BOOTCFG_INTD

UPPINT

MPU0_INTD (MPU0_ADDR_ERR_INT and

MPU0_PROT_ERR_INT combined)

Reserved

MPU1_INTD (MPU1_ADDR_ERR_INT and

MPU1_PROT_ERR_INT combined)

Reserved

MPU2_INTD (MPU2_ADDR_ERR_INT and

MPU2_PROT_ERR_INT combined)

QM_INT_PKTDMA_0

MPU3_INTD (MPU3_ADDR_ERR_INT and

MPU3_PROT_ERR_INT combined)

QM_INT_PKTDMA_1

Reserved

Reserved

Reserved

Reserved

MSMC_mpf_error0

MSMC_mpf_error1

MSMC_mpf_error2

MSMC_mpf_error3

MSMC_mpf_error4

MSMC_mpf_error5

MSMC_mpf_error6

MSMC_mpf_error7

MSMC_mpf_error8

MSMC_mpf_error9

MSMC_mpf_error10

MSMC_mpf_error11

MSMC_mpf_error12

MSMC_mpf_error13

DESCRIPTION

GPIO interrupt

GPIO interrupt

Tracer sliding time window interrupt for DDR3 EMIF

Tracer sliding time window interrupt for MSMC SRAM bank0

Tracer sliding time window interrupt for MSMC SRAM bank1

Tracer sliding time window interrupt for MSMC SRAM bank2

Tracer sliding time window interrupt for MSMC SRAM bank3

Tracer sliding time window interrupt for CFG0 TeraNet

Tracer sliding time window interrupt for QM_SS CFG

Tracer sliding time window interrupt for QM_SS slave port

Tracer sliding time window interrupt for semaphore

Semaphore interrupt

Semaphore interrupt

Semaphore interrupt

Semaphore interrupt

BOOTCFG interrupt BOOTCFG_ERR and BOOTCFG_PROT uPP interrupt

MPU0 addressing violation interrupt and protection violation interrupt.

MPU1 addressing violation interrupt and protection violation interrupt.

MPU2 addressing violation interrupt and protection violation interrupt.

QM interrupt for packet DMA starvation

MPU3 addressing violation interrupt and protection violation interrupt.

QM interrupt for packet DMA starvation

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

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Table 8-35. CIC1 Event Inputs (Secondary Events for EDMA3_CC) (continued)

123

124

125

126

127

118

119

120

121

122

113

114

115

116

117

108

109

110

111

112

128

129

130

131

132

133

134

135

103

104

105

106

107

98

99

100

101

102

93

94

95

96

97

INPUT EVENT # ON

CIC

90

91

92

GPINT25

Reserved

Reserved

GPINT26

GPINT27

Reserved

GPINT28

GPINT29

GPINT30

GPINT31

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

GPINT24

SYSTEM INTERRUPT

MSMC_mpf_error14

MSMC_mpf_error15

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

GPINT4

GPINT5

GPINT6

GPINT7

Reserved

Tracer_EMIF16

EASYNCERR

MPU4_INTD (MPU4_ADDR_ERR_INT and

MPU4_PROT_ERR_INT combined)

DESCRIPTION

Memory protection fault indicators for each system master PrivID

Memory protection fault indicators for each system master PrivID

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

GPIO interrupt

Tracer sliding time window interrupt for EMIF16

EMIF16 error interrupt

MPU4 addressing violation interrupt and protection violation interrupt.

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Table 8-35. CIC1 Event Inputs (Secondary Events for EDMA3_CC) (continued)

149

150

151

152

153

144

145

146

147

148

154

155

156

157

158

159

139

140

141

142

143

INPUT EVENT # ON

CIC

136

137

138

SYSTEM INTERRUPT

Reserved

QM_INT_HIGH_0

QM_INT_HIGH_1

QM_INT_HIGH_2

QM_INT_HIGH_3

QM_INT_HIGH_4

QM_INT_HIGH_5

QM_INT_HIGH_6

QM_INT_HIGH_7

QM_INT_HIGH_8

QM_INT_HIGH_9

QM_INT_HIGH_10

QM_INT_HIGH_11

QM_INT_HIGH_12

QM_INT_HIGH_13

QM_INT_HIGH_14

QM_INT_HIGH_15

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

DDR3_ERR

DESCRIPTION

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

QM interrupt

DDR3 error interrupt

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8.8.2

CIC Registers

This section includes the offsets for CIC registers. The base addresses for interrupt control registers are

CIC0 - 0x0260 0000 and CIC1 - 0x0260 4000.

8.8.2.1

CIC0 Register Map

Table 8-36. CIC0 Register

0x30c

0x310

0x314

0x318

0x380

0x384

0x388

0x38c

0x390

0x394

0x398

0x400

0x404

0x408

0x280

0x284

0x288

0x28c

0x290

0x294

0x298

0x300

0x304

0x308

0x2c

0x34

0x38

0x200

0x204

0x208

0x20c

0x210

0x214

0x218

ADDRESS

OFFSET

0x0

0x4

0xc

0x10

0x20

0x24

0x28

REGISTER MNEMONIC

REVISION_REG

CONTROL_REG

HOST_CONTROL_REG

GLOBAL_ENABLE_HINT_REG

STATUS_SET_INDEX_REG

STATUS_CLR_INDEX_REG

ENABLE_SET_INDEX_REG

ENABLE_CLR_INDEX_REG

HINT_ENABLE_SET_INDEX_REG

HINT_ENABLE_CLR_INDEX_REG

RAW_STATUS_REG0

RAW_STATUS_REG1

RAW_STATUS_REG2

RAW_STATUS_REG3

RAW_STATUS_REG4

RAW_STATUS_REG5

RAW_STATUS_REG6

ENA_STATUS_REG0

ENA_STATUS_REG1

ENA_STATUS_REG2

ENA_STATUS_REG3

ENA_STATUS_REG4

ENA_STATUS_REG5

ENA_STATUS_REG6

ENABLE_REG0

ENABLE_REG1

ENABLE_REG2

ENABLE_REG3

ENABLE_REG4

ENABLE_REG5

ENABLE_REG6

ENABLE_CLR_REG0

ENABLE_CLR_REG1

ENABLE_CLR_REG2

ENABLE_CLR_REG3

ENABLE_CLR_REG4

ENABLE_CLR_REG5

ENABLE_CLR_REG6

CH_MAP_REG0

CH_MAP_REG1

CH_MAP_REG2

REGISTER NAME

Revision Register

Control Register

Host Control Register

Global Host Int Enable Register

Status Set Index Register

Status Clear Index Register

Enable Set Index Register

Enable Clear Index Register

Host Int Enable Set Index Register

Host Int Enable Clear Index Register

Raw Status Register 0

Raw Status Register 1

Raw Status Register 2

Raw Status Register 3

Raw Status Register 4

Raw Status Register 5

Raw Status Register 6

Enabled Status Register 0

Enabled Status Register 1

Enabled Status Register 2

Enabled Status Register 3

Enabled Status Register 4

Enabled Status Register 5

Enabled Status Register 6

Enable Register 0

Enable Register 1

Enable Register 2

Enable Register 3

Enable Register 4

Enable Register 5

Enable Register 6

Enable Clear Register 0

Enable Clear Register 1

Enable Clear Register 2

Enable Clear Register 3

Enable Clear Register 4

Enable Clear Register 5

Enable Clear Register 6

Interrupt Channel Map Register for 0 to 0+3

Interrupt Channel Map Register for 4 to 4+3

Interrupt Channel Map Register for 8 to 8+3

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Table 8-36. CIC0 Register (continued)

0x47c

0x480

0x484

0x488

0x48c

0x490

0x494

0x498

0x49c

0x4a0

0x454

0x458

0x45c

0x460

0x464

0x468

0x46c

0x470

0x474

0x478

0x4a4

0x4a8

0x4ac

0x4b0

0x4b4

0x4b8

0x4bc

0x4c0

0x4c4

0x42c

0x430

0x434

0x438

0x43c

0x440

0x444

0x448

0x44c

0x450

ADDRESS

OFFSET

0x40c

0x410

0x414

0x418

0x41c

0x420

0x424

0x428

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CH_MAP_REG21

CH_MAP_REG22

CH_MAP_REG23

CH_MAP_REG24

CH_MAP_REG25

CH_MAP_REG26

CH_MAP_REG27

CH_MAP_REG28

CH_MAP_REG29

CH_MAP_REG30

CH_MAP_REG31

CH_MAP_REG32

CH_MAP_REG33

CH_MAP_REG34

CH_MAP_REG35

CH_MAP_REG36

CH_MAP_REG37

CH_MAP_REG38

CH_MAP_REG39

CH_MAP_REG40

REGISTER MNEMONIC

CH_MAP_REG3

CH_MAP_REG4

CH_MAP_REG5

CH_MAP_REG6

CH_MAP_REG7

CH_MAP_REG8

CH_MAP_REG9

CH_MAP_REG10

CH_MAP_REG11

CH_MAP_REG12

CH_MAP_REG13

CH_MAP_REG14

CH_MAP_REG15

CH_MAP_REG16

CH_MAP_REG17

CH_MAP_REG18

CH_MAP_REG19

CH_MAP_REG20

CH_MAP_REG41

CH_MAP_REG42

CH_MAP_REG43

CH_MAP_REG44

CH_MAP_REG45

CH_MAP_REG46

CH_MAP_REG47

CH_MAP_REG48

CH_MAP_REG49

REGISTER NAME

Interrupt Channel Map Register for 12 to 12+3

Interrupt Channel Map Register for 16 to 16+3

Interrupt Channel Map Register for 20 to 20+3

Interrupt Channel Map Register for 24 to 24+3

Interrupt Channel Map Register for 28 to 28+3

Interrupt Channel Map Register for 32 to 32+3

Interrupt Channel Map Register for 36 to 36+3

Interrupt Channel Map Register for 40 to 40+3

Interrupt Channel Map Register for 44 to 44+3

Interrupt Channel Map Register for 48 to 48+3

Interrupt Channel Map Register for 52 to 52+3

Interrupt Channel Map Register for 56 to 56+3

Interrupt Channel Map Register for 60 to 60+3

Interrupt Channel Map Register for 64 to 64+3

Interrupt Channel Map Register for 68 to 68+3

Interrupt Channel Map Register for 72 to 72+3

Interrupt Channel Map Register for 76 to 76+3

Interrupt Channel Map Register for 80 to 80+3

Interrupt Channel Map Register for 84 to 84+3

Interrupt Channel Map Register for 88 to 88+3

Interrupt Channel Map Register for 92 to 92+3

Interrupt Channel Map Register for 96 to 96+3

Interrupt Channel Map Register for 100 to 100+3

Interrupt Channel Map Register for 104 to 104+3

Interrupt Channel Map Register for 108 to 108+3

Interrupt Channel Map Register for 112 to 112+3

Interrupt Channel Map Register for 116 to 116+3

Interrupt Channel Map Register for 120 to 120+3

Interrupt Channel Map Register for 124 to 124+3

Interrupt Channel Map Register for 128 to 128+3

Interrupt Channel Map Register for 132 to 132+3

Interrupt Channel Map Register for 136 to 136+3

Interrupt Channel Map Register for 140 to 140+3

Interrupt Channel Map Register for 144 to 144+3

Interrupt Channel Map Register for 148 to 148+3

Interrupt Channel Map Register for 152 to 152+3

Interrupt Channel Map Register for 156 to 156+3

Interrupt Channel Map Register for 160 to 160+3

Interrupt Channel Map Register for 164 to 164+3

Interrupt Channel Map Register for 168 to 168+3

Interrupt Channel Map Register for 172 to 172+3

Interrupt Channel Map Register for 176 to 176+3

Interrupt Channel Map Register for 180 to 180+3

Interrupt Channel Map Register for 184 to 184+3

Interrupt Channel Map Register for 188 to 188+3

Interrupt Channel Map Register for 192 to 192+3

Interrupt Channel Map Register for 196 to 196+3

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0x818

0x81c

0x820

0x824

0x828

0x82c

0x830

0x834

0x838

0x83c

ADDRESS

OFFSET

0x4c8

0x4cc

0x800

0x804

0x808

0x80c

0x810

0x814

0x840

0x844

0x848

0x84c

0x850

0x854

0x858

0x860

0x1500

0x1504

0x1508

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

Table 8-36. CIC0 Register (continued)

REGISTER MNEMONIC

CH_MAP_REG50

CH_MAP_REG51

HINT_MAP_REG0

HINT_MAP_REG1

HINT_MAP_REG2

HINT_MAP_REG3

HINT_MAP_REG4

HINT_MAP_REG5

HINT_MAP_REG6

HINT_MAP_REG7

HINT_MAP_REG8

HINT_MAP_REG9

HINT_MAP_REG10

HINT_MAP_REG11

HINT_MAP_REG12

HINT_MAP_REG13

HINT_MAP_REG14

HINT_MAP_REG15

HINT_MAP_REG16

HINT_MAP_REG17

HINT_MAP_REG18

HINT_MAP_REG19

HINT_MAP_REG20

HINT_MAP_REG21

HINT_MAP_REG22

HINT_MAP_REG23

ENABLE_HINT_REG0

ENABLE_HINT_REG1

ENABLE_HINT_REG2

REGISTER NAME

Interrupt Channel Map Register for 200 to 200+3

Interrupt Channel Map Register for 204 to 204+3

Host Interrupt Map Register for 0 to 0+3

Host Interrupt Map Register for 4 to 4+3

Host Interrupt Map Register for 8 to 8+3

Host Interrupt Map Register for 12 to 12+3

Host Interrupt Map Register for 16 to 16+3

Host Interrupt Map Register for 20 to 20+3

Host Interrupt Map Register for 24 to 24+3

Host Interrupt Map Register for 28 to 28+3

Host Interrupt Map Register for 32 to 32+3

Host Interrupt Map Register for 36 to 36+3

Host Interrupt Map Register for 40 to 40+3

Host Interrupt Map Register for 44 to 44+3

Host Interrupt Map Register for 48 to 48+3

Host Interrupt Map Register for 52 to 52+3

Host Interrupt Map Register for 56 to 56+3

Host Interrupt Map Register for 60 to 60+3

Host Interrupt Map Register for 64 to 64+3

Host Interrupt Map Register for 68 to 68+3

Host Interrupt Map Register for 72 to 72+3

Host Interrupt Map Register for 76 to 76+3

Host Interrupt Map Register for 80 to 80+3

Host Interrupt Map Register for 84 to 84+3

Host Interrupt Map Register for 88 to 88+3

Host Interrupt Map Register for 92 to 92+3

Host Int Enable Register 0

Host Int Enable Register 1

Host Int Enable Register 2

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8.8.2.2

CIC1 Register Map

Table 8-37. CIC1 Register

0x404

0x408

0x40c

0x410

0x414

0x418

0x41c

0x420

0x424

0x428

0x42c

0x430

0x434

0x438

0x43c

0x440

0x304

0x308

0x30c

0x310

0x380

0x384

0x388

0x38c

0x390

0x400

0x204

0x208

0x20c

0x210

0x280

0x284

0x288

0x28c

0x290

0x300

ADDRESS

OFFSET

0x0

0x10

0x20

0x24

0x28

0x2c

0x34

0x38

0x200

REGISTER MNEMONIC

REVISION_REG

GLOBAL_ENABLE_HINT_REG

STATUS_SET_INDEX_REG

STATUS_CLR_INDEX_REG

ENABLE_SET_INDEX_REG

ENABLE_CLR_INDEX_REG

HINT_ENABLE_SET_INDEX_REG

HINT_ENABLE_CLR_INDEX_REG

RAW_STATUS_REG0

RAW_STATUS_REG1

RAW_STATUS_REG2

RAW_STATUS_REG3

RAW_STATUS_REG4

ENA_STATUS_REG0

ENA_STATUS_REG1

ENA_STATUS_REG2

ENA_STATUS_REG3

ENA_STATUS_REG4

ENABLE_REG0

ENABLE_REG1

ENABLE_REG2

ENABLE_REG3

ENABLE_REG4

ENABLE_CLR_REG0

ENABLE_CLR_REG1

ENABLE_CLR_REG2

ENABLE_CLR_REG3

ENABLE_CLR_REG4

CH_MAP_REG0

CH_MAP_REG1

CH_MAP_REG2

CH_MAP_REG3

CH_MAP_REG4

CH_MAP_REG5

CH_MAP_REG6

CH_MAP_REG7

CH_MAP_REG8

CH_MAP_REG9

CH_MAP_REG10

CH_MAP_REG11

CH_MAP_REG12

CH_MAP_REG13

CH_MAP_REG14

CH_MAP_REG15

CH_MAP_REG16

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REGISTER NAME

Revision Register

Global Host Int Enable Register

Status Set Index Register

Status Clear Index Register

Enable Set Index Register

Enable Clear Index Register

Host Int Enable Set Index Register

Host Int Enable Clear Index Register

Raw Status Register 0

Raw Status Register 1

Raw Status Register 2

Raw Status Register 3

Raw Status Register 4

Enabled Status Register 0

Enabled Status Register 1

Enabled Status Register 2

Enabled Status Register 3

Enabled Status Register 4

Enable Register 0

Enable Register 1

Enable Register 2

Enable Register 3

Enable Register 4

Enable Clear Register 0

Enable Clear Register 1

Enable Clear Register 2

Enable Clear Register 3

Enable Clear Register 4

Interrupt Channel Map Register for 0 to 0+3

Interrupt Channel Map Register for 4 to 4+3

Interrupt Channel Map Register for 8 to 8+3

Interrupt Channel Map Register for 12 to 12+3

Interrupt Channel Map Register for 16 to 16+3

Interrupt Channel Map Register for 20 to 20+3

Interrupt Channel Map Register for 24 to 24+3

Interrupt Channel Map Register for 28 to 28+3

Interrupt Channel Map Register for 32 to 32+3

Interrupt Channel Map Register for 36 to 36+3

Interrupt Channel Map Register for 40 to 40+3

Interrupt Channel Map Register for 44 to 44+3

Interrupt Channel Map Register for 48 to 48+3

Interrupt Channel Map Register for 52 to 52+3

Interrupt Channel Map Register for 56 to 56+3

Interrupt Channel Map Register for 60 to 60+3

Interrupt Channel Map Register for 64 to 64+3

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0x814

0x818

0x81c

0x820

0x824

0x828

0x82c

0x830

0x834

0x838

0x83c

0x1500

0x1504

0x48c

0x490

0x494

0x498

0x49c

0x800

0x804

0x808

0x80c

0x810

0x464

0x468

0x46c

0x470

0x474

0x478

0x47c

0x480

0x484

0x488

ADDRESS

OFFSET

0x444

0x448

0x44c

0x450

0x454

0x458

0x45c

0x460

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

Table 8-37. CIC1 Register (continued)

REGISTER MNEMONIC

CH_MAP_REG17

CH_MAP_REG18

CH_MAP_REG19

CH_MAP_REG20

CH_MAP_REG21

CH_MAP_REG22

CH_MAP_REG23

CH_MAP_REG24

CH_MAP_REG25

CH_MAP_REG26

CH_MAP_REG27

CH_MAP_REG28

CH_MAP_REG29

CH_MAP_REG30

CH_MAP_REG31

CH_MAP_REG32

CH_MAP_REG33

CH_MAP_REG34

CH_MAP_REG35

CH_MAP_REG36

CH_MAP_REG37

CH_MAP_REG38

CH_MAP_REG39

HINT_MAP_REG0

HINT_MAP_REG1

HINT_MAP_REG2

HINT_MAP_REG3

HINT_MAP_REG4

HINT_MAP_REG5

HINT_MAP_REG6

HINT_MAP_REG7

HINT_MAP_REG8

HINT_MAP_REG9

HINT_MAP_REG10

HINT_MAP_REG11

HINT_MAP_REG12

HINT_MAP_REG13

HINT_MAP_REG14

HINT_MAP_REG15

ENABLE_HINT_REG0

ENABLE_HINT_REG1

REGISTER NAME

Interrupt Channel Map Register for 68 to 68+3

Interrupt Channel Map Register for 72 to 72+3

Interrupt Channel Map Register for 76 to 76+3

Interrupt Channel Map Register for 80 to 80+3

Interrupt Channel Map Register for 84 to 84+3

Interrupt Channel Map Register for 88 to 88+3

Interrupt Channel Map Register for 92 to 92+3

Interrupt Channel Map Register for 96 to 96+3

Interrupt Channel Map Register for 100 to 100+3

Interrupt Channel Map Register for 104 to 104+3

Interrupt Channel Map Register for 108 to 108+3

Interrupt Channel Map Register for 112 to 112+3

Interrupt Channel Map Register for 116 to 116+3

Interrupt Channel Map Register for 120 to 120+3

Interrupt Channel Map Register for 124 to 124+3

Interrupt Channel Map Register for 128 to 128+3

Interrupt Channel Map Register for 132 to 132+3

Interrupt Channel Map Register for 136 to 136+3

Interrupt Channel Map Register for 140 to 140+3

Interrupt Channel Map Register for 144 to 144+3

Interrupt Channel Map Register for 148 to 148+3

Interrupt Channel Map Register for 152 to 152+3

Interrupt Channel Map Register for 156 to 156+3

Host Interrupt Map Register for 0 to 0+3

Host Interrupt Map Register for 4 to 4+3

Host Interrupt Map Register for 8 to 8+3

Host Interrupt Map Register for 12 to 12+3

Host Interrupt Map Register for 16 to 16+3

Host Interrupt Map Register for 20 to 20+3

Host Interrupt Map Register for 24 to 24+3

Host Interrupt Map Register for 28 to 28+3

Host Interrupt Map Register for 32 to 32+3

Host Interrupt Map Register for 36 to 36+3

Host Interrupt Map Register for 40 to 40+3

Host Interrupt Map Register for 44 to 44+3

Host Interrupt Map Register for 48 to 48+3

Host Interrupt Map Register for 52 to 52+3

Host Interrupt Map Register for 56 to 56+3

Host Interrupt Map Register for 60 to 60+3

Host Int Enable Register 0

Host Int Enable Register 1

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8.8.3

Inter-Processor Register Map

ADDRESS START ADDRESS END

0x02620200

0x02620204

0x02620203

0x02620207

0x02620208

0x0262020C

0x0262020B

0x0262020F

0x02620210

0x02620214

0x02620218

0x0262021C

0x02620220

0x02620213

0x02620217

0x0262021B

0x0262021F

0x0262023F

0x02620240

0x02620244

0x02620248

0x0262024C

0x02620250

0x02620254

0x02620258

0x0262025C

0x02620260

0x0262027C

0x02620243

0x02620247

0x0262024B

0x0262024F

0x02620253

0x02620257

0x0262025B

0x0262025F

0x0262027B

0x0262027F

0x02620280

0x02620284

0x02620288

0x0262028C

0x02620290

0x02620294

0x02620298

0x0262029C

0x026202A0

0x026202BC

0x02620283

0x02620287

0x0262028B

0x0262028F

0x02620293

0x02620297

0x0262029B

0x0262029F

0x026202BB

0x026202BF

Table 8-38. IPC Generation Registers (IPCGRx)

IPCAR0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IPCARH

IPCGR0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IPCGRH

REGISTER NAME

NMIGR0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

4B

4B

4B

28B

4B

4B

4B

4B

4B

4B

4B

4B

4B

4B

32B

SIZE

4B

4B

4B

4B

4B

4B

4B

28B

4B

4B

4B

4B

4B

4B

DESCRIPTION

NMI Event Generation Register for CorePac0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IPC Generation Register for CorePac 0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IPC Generation Register for Host

IPC Acknowledgement Register for CorePac 0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

IPC Acknowledgement Register for Host

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8.8.4

NMI and LRESET

Non-maskable interrupts (NMI) can be generated by chip-level registers and the LRESET can be generated by software writing into LPSC registers. LRESET and NMI can also be asserted by device pins or watchdog timers. One NMI pin and one LRESET pin are shared by all CorePacs on the device. The

CORESEL[3:0] pins can be configured to select between the CorePacs available as shown in

Table 8-39

.

CORESEL[1:0]

PIN INPUT

XX

00

01

1x

00

01

1x

00

01

1x

LRESET

PIN INPUT

X

0

0

0

1

1

1

1

1

1

Table 8-39. LRESET and NMI Decoding

NMI

PIN INPUT

X

X

X

X

1

1

1

0

0

0

LRESETNMIEN

PIN INPUT

1

0

0

0

0

0

0

0

0

0

RESET MUX BLOCK OUTPUT

No local reset or NMI assertion.

Assert local reset to CorePac 0

Reserved

Assert local reset to all CorePacs

De-assert local reset & NMI to CorePac 0

Reserved

De-assert local reset & NMI to all CorePacs

Assert NMI to CorePac 0

Reserved

Assert NMI to all CorePacs

8.8.5

External Interrupts Electrical Data/Timing

Table 8-40. NMI and Local Reset Timing Requirements

(1)

(see

Figure 8-26 )

2

3

2

2

1

1

NO.

1 tsu(LRESET-LRESETNMIENL) Setup Time - LRESET valid before LRESETNMIEN low tsu(NMI-LRESETNMIENL) Setup Time - NMI valid before LRESETNMIEN low tsu(CORESELn-LRESETNMIENL) Setup Time - CORESEL[2:0] valid before LRESETNMIEN low th(LRESETNMIENL-LRESET) th(LRESETNMIENL-NMI)

Hold Time - LRESET valid after LRESETNMIEN high

Hold Time - NMI valid after LRESETNMIEN high th(LRESETNMIENL-CORESELn) Hold Time - CORESEL[2:0] valid after LRESETNMIEN high tw(LRESETNMIEN) Pulse Width - LRESETNMIEN low width

(1) P = 1/SYSCLK1 clock frequency in ns.

MIN

12*P

12*P

12*P

12*P

12*P

12*P

12*P

MAX

ns ns ns ns

UNIT

ns ns ns

1 2

CORESEL[3:0]/

LRESET /

NMI

3

LRESETNMIEN

Figure 8-26. NMI and Local Reset Timing

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TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

8.9

Memory Protection Unit (MPU)

The C6654 supports five MPUs:

• One MPU is used to protect main CORE/3 CFG TeraNet (CFG space of all slave devices on the

TeraNet is protected by the MPU).

• Two MPUs are used for QM_SS (one for the DATA PORT port and the other is for the CFG PORT port).

• One MPU is used for Semaphore.

• One MPU is used for EMIF16

This section contains MPU register map and details of device-specific MPU registers only. For MPU features and details of generic MPU registers, see the Memory Protection Unit (MPU) for KeyStone

Devices User's Guide ( SPRUGW5 ).

The following tables show the configuration of each MPU and the memory regions protected by each

MPU.

Table 8-41. MPU Default Configuration

SETTING

MPU0 (MAIN CFG MPU1 (QM_SS

TERANET) DATA PORT)

Default permission Assume allowed

Number of allowed IDs supported 16

Assume allowed

16

Number of programmable ranges 16 supported

Compare width 1KB granularity

5

1KB granularity

MPU2 (QM_SS CFG MPU3

PORT) (SEMAPHORE)

MPU4

(EMIF16)

Assume allowed

16

16

Assume allowed Assume allowed

16

1

16

16

1KB granularity 1KB granularity 1KB granularity

MPU0

MPU1

MPU2

MPU3

MPU4

Table 8-42. MPU Memory Regions

MEMORY PROTECTION

Main CFG TeraNet

QM_SS DATA PORT

QM_SS CFG PORT

Semaphore

EMIF16

START ADDRESS

0x01D00000

0x34000000

0x02A00000

0x02640000

0x70000000

END ADDRESS

0x026207FF

0x340BFFFF

0x02ABFFFF

0x026407FF

0x7FFFFFFF

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Table 8-43

shows the privilege ID of each CORE and every mastering peripheral.

Table 8-43

also shows the privilege level (supervisor vs. user), and access type (instruction read vs. data/DMA read or write) of each master on the device. In some cases, a particular setting depends on software being executed at the time of the access or the configuration of the master peripheral.

Table 8-43. Privilege ID Settings

PRIVILEGE LEVEL

SW dependant, driven by MSMC

ACCESS

TYPE

DMA

12

13

14

15

9

10

11

4

5

6

7

8

2

3

PRIVILEGE ID MASTER

0

1

CorePac0

Reserved

Reserved

Reserved

Reserved

Reserved uPP

EMAC

QM_PKTDMA

Reserved

QM_second

PCIe

DAP

Reserved

Reserved

Reserved

User

User

User

User

Supervisor

Driven by Debug_SS

DMA

DMA

DMA

DMA

DMA

DMA

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Table 8-44

shows the master ID of each CorePac and every mastering peripheral. Master IDs are used to determine allowed connections between masters and slaves. Unlike privilege IDs, which can be shared across different masters, master IDs are unique to each master.

Table 8-44. Master ID Settings

(1)

27

28

29

30

31

22

23

24

25

26

32

33

34

35

36 - 37

38 - 39

17

18

19

20

21

12

13

14

15

16

7

8

9

5

6

10

11

1

2

3

4

MASTER ID

0

MASTER

CorePac0

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

CorePac0_CFG

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

EDMA_TC0 read

EDMA_TC0 write

EDMA_TC1 read

EDMA_TC1 write

EDMA_TC2 read

EDMA_TC2 write

EDMA_TC3 read

EDMA_TC3 write

Reserved

Reserved

MASTER ID

40 - 47

48

49

50

51

52

53

54

55

56

57 - 87

88 - 91

92 - 93

94

95

96 - 127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

(1) Some of the PKTDMA-based peripherals require multiple master IDs. QMS_PKTDMA is assigned with 88,89,90,91, but only 88-89 are actually used. There are two master ID values are assigned for the QM_second master port, one master ID for external linking RAM and the other one for the PDSP/MCDM accesses.

(2) The master ID for MSMC is for the transactions initiated by MSMC internally and sent to the DDR.

(3) All Tracers are set to the same master ID and bit 7 of the master ID needs to be 1.

MASTER

Reserved

DAP

Reserved

EDMA3_CC

Reserved

MSMC

(2)

PCIe

Reserved

Reserved

EMAC

Reserved

QM_PKTDMA

QM_Second

Reserved uPP

Reserved

Tracer_core_0

(3)

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Tracer_DDR

Tracer_SEM

Tracer_QM_CFG

Tracer_QM_DMA

Tracer_CFG

Reserved

Reserved

Reserved

Tracer_EMIF16

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274h

278h

280h

284h

288h

290h

294h

298h

2A0h

2A4h

2A8h

2B0h

2B4h

258h

260h

264h

268h

270h

240h

244h

248h

250h

254h

224h

228h

230h

234h

238h

208h

210h

214h

218h

220h

18h

1Ch

20h

200h

204h

OFFSET

0h

4h

10h

14h

PROG4_MPSAR

PROG4_MPEAR

PROG4_MPPA

PROG5_MPSAR

PROG5_MPEAR

PROG5_MPPA

PROG6_MPSAR

PROG6_MPEAR

PROG6_MPPA

PROG7_MPSAR

PROG7_MPEAR

PROG7_MPPA

PROG8_MPSAR

PROG8_MPEAR

PROG8_MPPA

PROG9_MPSAR

PROG9_MPEAR

PROG9_MPPA

PROG10_MPSAR

PROG10_MPEAR

PROG10_MPPA

PROG11_MPSAR

PROG11_MPEAR

NAME

REVID

CONFIG

IRAWSTAT

IENSTAT

IENSET

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

PROG0_MPPA

PROG1_MPSAR

PROG1_MPEAR

PROG1_MPPA

PROG2_MPSAR

PROG2_MPEAR

PROG2_MPPA

PROG3_MPSAR

PROG3_MPEAR

PROG3_MPPA

8.9.1

MPU Registers

This section includes the offsets for MPU registers and definitions for device specific MPU registers.

8.9.1.1

MPU Register Map

Table 8-45. MPU0 Registers

DESCRIPTION

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Interrupt enable

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Programmable range 0, memory page protection attributes

Programmable range 1, start address

Programmable range 1, end address

Programmable range 1, memory page protection attributes

Programmable range 2, start address

Programmable range 2, end address

Programmable range 2, memory page protection attributes

Programmable range 3, start address

Programmable range 3, end address

Programmable range 3, memory page protection attributes

Programmable range 4, start address

Programmable range 4, end address

Programmable range 4, memory page protection attributes

Programmable range 5, start address

Programmable range 5, end address

Programmable range 5, memory page protection attributes

Programmable range 6, start address

Programmable range 6, end address

Programmable range 6, memory page protection attributes

Programmable range 7, start address

Programmable range 7, end address

Programmable range 7, memory page protection attributes

Programmable range 8, start address

Programmable range 8, end address

Programmable range 8, memory page protection attributes

Programmable range 9, start address

Programmable range 9, end address

Programmable range 9, memory page protection attributes

Programmable range 10, start address

Programmable range 10, end address

Programmable range 10, memory page protection attributes

Programmable range 11, start address

Programmable range 11, end address

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2F4h

2F8h

300h

304h

308h

OFFSET

2B8h

2C0h

2C4h

2C8h

2D0h

2D4h

2Dh

2E0h

2E4h

2E8h

2F0h

NAME

PROG11_MPPA

PROG12_MPSAR

PROG12_MPEAR

PROG12_MPPA

PROG13_MPSAR

PROG13_MPEAR

PROG13_MPPA

PROG14_MPSAR

PROG14_MPEAR

PROG14_MPPA

PROG15_MPSAR

PROG15_MPEAR

PROG15_MPPA

FLTADDRR

FLTSTAT

FLTCLR

234h

238h

240h

244h

248h

218h

220h

224h

228h

230h

300h

304h

308h

1Ch

20h

200h

204h

208h

210h

214h

OFFSET

0h

4h

10h

14h

18h

NAME

REVID

CONFIG

IRAWSTAT

IENSTAT

IENSET

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

PROG0_MPPA

PROG1_MPSAR

PROG1_MPEAR

PROG1_MPPA

PROG2_MPSAR

PROG2_MPEAR

PROG2_MPPA

PROG3_MPSAR

PROG3_MPEAR

PROG3_MPPA

PROG4_MPSAR

PROG4_MPEAR

PROG4_MPPA

FLTADDRR

FLTSTAT

FLTCLR

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

Table 8-45. MPU0 Registers (continued)

DESCRIPTION

Programmable range 11, memory page protection attributes

Programmable range 12, start address

Programmable range 12, end address

Programmable range 12, memory page protection attributes

Programmable range 13, start address

Programmable range 13, end address

Programmable range 13, memory page protection attributes

Programmable range 14, start address

Programmable range 14, end address

Programmable range 14, memory page protection attributes

Programmable range 15, start address

Programmable range 15, end address

Programmable range 15, memory page protection attributes

Fault address

Fault status

Fault clear

Table 8-46. MPU1 Registers

DESCRIPTION

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Interrupt enable

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Programmable range 0, memory page protection attributes

Programmable range 1, start address

Programmable range 1, end address

Programmable range 1, memory page protection attributes

Programmable range 2, start address

Programmable range 2, end address

Programmable range 2, memory page protection attributes

Programmable range 3, start address

Programmable range 3, end address

Programmable range 3, memory page protection attributes

Programmable range 4, start address

Programmable range 4, end address

Programmable range 4, memory page protection attributes

Fault address

Fault status

Fault clear

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284h

288h

290h

294h

298h

2A0h

2A4h

2A8h

2B0h

2B4h

268h

270h

274h

278h

280h

250h

254h

258h

260h

264h

2B8h

2C0h

2C4h

2C8h

2D0h

234h

238h

240h

244h

248h

218h

220h

224h

228h

230h

1Ch

20h

200h

204h

208h

210h

214h

OFFSET

0h

4h

10h

14h

18h

PROG5_MPSAR

PROG5_MPEAR

PROG5_MPPA

PROG6_MPSAR

PROG6_MPEAR

PROG6_MPPA

PROG7_MPSAR

PROG7_MPEAR

PROG7_MPPA

PROG8_MPSAR

PROG8_MPEAR

PROG8_MPPA

PROG9_MPSAR

PROG9_MPEAR

PROG9_MPPA

PROG10_MPSAR

PROG10_MPEAR

PROG10_MPPA

PROG11_MPSAR

PROG11_MPEAR

PROG11_MPPA

PROG12_MPSAR

PROG12_MPEAR

PROG12_MPPA

PROG13_MPSAR

NAME

REVID

CONFIG

IRAWSTAT

IENSTAT

IENSET

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

PROG0_MPPA

PROG1_MPSAR

PROG1_MPEAR

PROG1_MPPA

PROG2_MPSAR

PROG2_MPEAR

PROG2_MPPA

PROG3_MPSAR

PROG3_MPEAR

PROG3_MPPA

PROG4_MPSAR

PROG4_MPEAR

PROG4_MPPA

Table 8-47. MPU2 Registers

DESCRIPTION

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Interrupt enable

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Programmable range 0, memory page protection attributes

Programmable range 1, start address

Programmable range 1, end address

Programmable range 1, memory page protection attributes

Programmable range 2, start address

Programmable range 2, end address

Programmable range 2, memory page protection attributes

Programmable range 3, start address

Programmable range 3, end address

Programmable range 3, memory page protection attributes

Programmable range 4, start address

Programmable range 4, end address

Programmable range 4, memory page protection attributes

Programmable range 5, start address

Programmable range 5, end address

Programmable range 5, memory page protection attributes

Programmable range 6, start address

Programmable range 6, end address

Programmable range 6, memory page protection attributes

Programmable range 7, start address

Programmable range 7, end address

Programmable range 7, memory page protection attributes

Programmable range 8, start address

Programmable range 8, end address

Programmable range 8, memory page protection attributes

Programmable range 9, start address

Programmable range 9, end address

Programmable range 9, memory page protection attributes

Programmable range 10, start address

Programmable range 10, end address

Programmable range 10, memory page protection attributes

Programmable range 11, start address

Programmable range 11, end address

Programmable range 11, memory page protection attributes

Programmable range 12, start address

Programmable range 12, end address

Programmable range 12, memory page protection attributes

Programmable range 13, start address

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2F4h

2F8h

300h

304h

308h

OFFSET

2D4h

2Dh

2E0h

2E4h

2E8h

2F0h

NAME

PROG13_MPEAR

PROG13_MPPA

PROG14_MPSAR

PROG14_MPEAR

PROG14_MPPA

PROG15_MPSAR

PROG15_MPEAR

PROG15_MPPA

FLTADDRR

FLTSTAT

FLTCLR

1Ch

20h

200h

204h

208h

OFFSET

0h

4h

10h

14h

18h

300h

304h

308h

NAME

REVID

CONFIG

IRAWSTAT

IENSTAT

IENSET

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

PROG0_MPPA

FLTADDRR

FLTSTAT

FLTCLR

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

Table 8-47. MPU2 Registers (continued)

DESCRIPTION

Programmable range 13, end address

Programmable range 13, memory page protection attributes

Programmable range 14, start address

Programmable range 14, end address

Programmable range 14, memory page protection attributes

Programmable range 15, start address

Programmable range 15, end address

Programmable range 15, memory page protection attributes

Fault address

Fault status

Fault clear

Table 8-48. MPU3 Registers

DESCRIPTION

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Interrupt enable

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Programmable range 0, memory page protection attributes

Fault address

Fault status

Fault clear

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284h

288h

290h

294h

298h

2A0h

2A4h

2A8h

2B0h

2B4h

268h

270h

274h

278h

280h

250h

254h

258h

260h

264h

2B8h

2C0h

2C4h

2C8h

2D0h

234h

238h

240h

244h

248h

218h

220h

224h

228h

230h

1Ch

20h

200h

204h

208h

210h

214h

OFFSET

0h

4h

10h

14h

18h

PROG5_MPSAR

PROG5_MPEAR

PROG5_MPPA

PROG6_MPSAR

PROG6_MPEAR

PROG6_MPPA

PROG7_MPSAR

PROG7_MPEAR

PROG7_MPPA

PROG8_MPSAR

PROG8_MPEAR

PROG8_MPPA

PROG9_MPSAR

PROG9_MPEAR

PROG9_MPPA

PROG10_MPSAR

PROG10_MPEAR

PROG10_MPPA

PROG11_MPSAR

PROG11_MPEAR

PROG11_MPPA

PROG12_MPSAR

PROG12_MPEAR

PROG12_MPPA

PROG13_MPSAR

NAME

REVID

CONFIG

IRAWSTAT

IENSTAT

IENSET

IENCLR

EOI

PROG0_MPSAR

PROG0_MPEAR

PROG0_MPPA

PROG1_MPSAR

PROG1_MPEAR

PROG1_MPPA

PROG2_MPSAR

PROG2_MPEAR

PROG2_MPPA

PROG3_MPSAR

PROG3_MPEAR

PROG3_MPPA

PROG4_MPSAR

PROG4_MPEAR

PROG4_MPPA

Table 8-49. MPU4 Registers

DESCRIPTION

Revision ID

Configuration

Interrupt raw status/set

Interrupt enable status/clear

Interrupt enable

Interrupt enable clear

End of interrupt

Programmable range 0, start address

Programmable range 0, end address

Programmable range 0, memory page protection attributes

Programmable range 1, start address

Programmable range 1, end address

Programmable range 1, memory page protection attributes

Programmable range 2, start address

Programmable range 2, end address

Programmable range 2, memory page protection attributes

Programmable range 3, start address

Programmable range 3, end address

Programmable range 3, memory page protection attributes

Programmable range 4, start address

Programmable range 4, end address

Programmable range 4, memory page protection attributes

Programmable range 5, start address

Programmable range 5, end address

Programmable range 5, memory page protection attributes

Programmable range 6, start address

Programmable range 6, end address

Programmable range 6, memory page protection attributes

Programmable range 7, start address

Programmable range 7, end address

Programmable range 7, memory page protection attributes

Programmable range 8, start address

Programmable range 8, end address

Programmable range 8, memory page protection attributes

Programmable range 9, start address

Programmable range 9, end address

Programmable range 9, memory page protection attributes

Programmable range 10, start address

Programmable range 10, end address

Programmable range 10, memory page protection attributes

Programmable range 11, start address

Programmable range 11, end address

Programmable range 11, memory page protection attributes

Programmable range 12, start address

Programmable range 12, end address

Programmable range 12, memory page protection attributes

Programmable range 13, start address

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2F4h

2F8h

300h

304h

308h

OFFSET

2D4h

2Dh

2E0h

2E4h

2E8h

2F0h

NAME

PROG13_MPEAR

PROG13_MPPA

PROG14_MPSAR

PROG14_MPEAR

PROG14_MPPA

PROG15_MPSAR

PROG15_MPEAR

PROG15_MPPA

FLTADDRR

FLTSTAT

FLTCLR

Table 8-49. MPU4 Registers (continued)

DESCRIPTION

Programmable range 13, end address

Programmable range 13, memory page protection attributes

Programmable range 14, start address

Programmable range 14, end address

Programmable range 14, memory page protection attributes

Programmable range 15, start address

Programmable range 15, end address

Programmable range 15, memory page protection attributes

Fault address

Fault status

Fault clear

8.9.1.2

Device-Specific MPU Registers

8.9.1.2.1 Configuration Register (CONFIG)

The Configuration Register (CONFIG) contains the configuration value of the MPU.

31

MPU0

MPU1

Reset Values

MPU2

MPU3

MPU4

ADDR_WIDTH

R-0

R-0

R-0

R-0

R-0

Legend: R = Read only; -n = value after reset

24

Figure 8-27. Configuration Register (CONFIG)

23 20

NUM_FIXED

R-0

R-0

R-0

R-0

R-0

19 16

NUM_PROG

R-16

R-5

R-16

R-1

R-16

15 12

NUM_AIDS

R-16

R-16

R-16

R-16

R-16

11 1 0

Reserved ASSUME_ALLOWED

R-0 R-1

R-0

R-0

R-1

R-1

R-0

R-0

R-1

R-1

Bit Field

31 – 24 ADDR_WIDTH

23 – 20 NUM_FIXED

19 – 16 NUM_PROG

15 – 12 NUM_AIDS

11 – 1 Reserved

0 ASSUME_ALLOWED

Table 8-50. Configuration Register (CONFIG) Field Descriptions

Description

Address alignment for range checking

• 0 = 1KB alignment

• 6 = 64KB alignment

Number of fixed address ranges

Number of programmable address ranges

Number of supported AIDs

Reserved. These bits will always reads as 0.

Assume allowed bit. When an address is not covered by any MPU protection range, this bit determines whether the transfer is assumed to be allowed or not.

• 0 = Assume disallowed

• 1 = Assume allowed

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8.9.2

MPU Programmable Range Registers

8.9.2.1

Programmable Range n Start Address Register (PROGn_MPSAR)

The Programmable Address Start Register holds the start address for the range. This register is writeable by a supervisor entity only.

The start address must be aligned on a page boundary. The size of the page is 1K byte. The size of the page determines the width of the address field in MPSAR and MPEAR.

Figure 8-28. Programmable Range n Start Address Register (PROGn_MPSAR)

10 9 31

START_ADDR

R/W

Legend: R = Read only; R/W = Read/Write

Reserved

R

0

Bit

31 – 10

9 – 0

Table 8-51. Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions

Field

START_ADDR

Reserved

Description

Start address for range n.

Reserved and these bits always read as 0.

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8.9.2.2

Programmable Range n End Address Register (PROGn_MPEAR)

The Programmable Address End Register holds the end address for the range. This register is writeable by a supervisor entity only.

The end address must be aligned on a page boundary. The size of the page depends on the MPU number. The page size for MPU1 is 1K byte and for MPU2 it is 64K bytes. The size of the page determines the width of the address field in MPSAR and MPEAR

Figure 8-29. Programmable Range n End Address Register (PROGn_MPEAR)

10 9 31

END_ADDR

R/W

Legend: R = Read only; R/W = Read/Write

Reserved

R

0

Bit

31 – 10

9 – 0

Table 8-52. Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions

Field

END_ADDR

Reserved

Description

End address for range n.

Reserved and these bits always read as 3FFh.

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8.9.2.3

Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)

The Programmable Address Memory Protection Page Attribute Register holds the permissions for the region. This register is writeable only by a non-debug supervisor entity.

Figure 8-30. Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)

31

14 13

Reserved

R

12 11

26

10

25

AID15

R/W

9

AID4 AID3 AID2 AID1 AID0 AIDX

24

AID14

R/W

8

Reserved

23

AID13

R/W

22

AID12

R/W

7

Reserved

21

AID11

R/W

6

EMU

20

AID10

R/W

5

SR

19

AID9

R/W

4

SW

18

AID8

R/W

3

SX

17

AID7

R/W

2

UR

16

AID6

R/W

1

UW

15

AID5

R/W

0

UX

R/W R/W R/W R/W R/W

Legend: R = Read only; R/W = Read/Write

R/W R R R/W R/W R/W R/W R/W R/W R/W

Bit Field

31 – 26 Reserved

25 AID15

24

23

22

21

20

19

18

17

16

15

14

Table 8-53. Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA)

Field Descriptions

AID14

AID13

AID12

AID11

AID10

AID9

AID8

AID7

AID6

AID5

AID4

Description

Reserved. These bits will always reads as 0.

Controls permission check of ID = 15

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 14

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 13

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 12

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 11

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 10

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 9

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 8

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 7

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 6

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 5

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 4

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

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12

11

10

9

8

7

6

Bit

13

5

4

3

2

1

0

Table 8-53. Programmable Range n Memory Protection Page Attribute Register (PROGn_MPPA) Field

Descriptions (continued)

Field

AID3

AID2

AID1

AID0

AIDX

Reserved

Reserved

EMU

SR

SW

SX

UR

UW

UX

Description

Controls permission check of ID = 3

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 2

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 1

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID = 0

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Controls permission check of ID > 15

• 0 = AID is not checked for permissions

• 1 = AID is checked for permissions

Always reads as 0.

Always reads as 1.

Emulation (debug) access permission.

• 0 = Debug access not allowed.

• 1 = Debug access allowed.

Supervisor Read permission

• 0 = Access not allowed.

• 1 = Access allowed.

Supervisor Write permission

• 0 = Access not allowed.

• 1 = Access allowed.

Supervisor Execute permission

• 0 = Access not allowed.

• 1 = Access allowed.

User Read permission

• 0 = Access not allowed.

• 1 = Access allowed

User Write permission

• 0 = Access not allowed.

• 1 = Access allowed.

User Execute permission

• 0 = Access not allowed.

• 1 = Access allowed.

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8.9.2.4

MPU Registers Reset Values

PROGRAMMA START ADDRESS

BLE RANGE (PROGn_MPSAR)

PROG0

PROG1

PROG2

PROG3

0x01D0_0000

0x01F0_0000

0x0200_0000

0x01E0_0000

PROG4

PROG5

PROG6

PROG7

PROG8

PROG9

PROG10

PROG11

0x021C_0000

0x021F_0000

0x0220_0000

0x0231_0000

0x0232_0000

0x0233_0000

0x0235_0000

0x0240_0000

PROG12

PROG13

PROG14

PROG15

Table 8-54. Programmable Range n Registers Reset Values for MPU0

MPU0 (MAIN CFG TERANET)

END ADDRESS

(PROGn_MPEAR)

MEMORY PAGE

PROTECTION ATTRIBUTE

(PROGn_MPPA)

0x01D8_007F

0x01F7_FFFF

0x0209_FFFF

0x01EB_FFFF

0x03FF_FCB6

0x03FF_FC80

0x03FF_FCB6

0x03FF_FCB6

0x021E_0C3F

0x021F_7FFF

0x0227_007F

0x0231_03FF

0x0232_03FF

0x0233_03FF

0x0235_0FFF

0x0245_3FFF

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB6

0x0250_0000

0x0253_0000

0x0260_0000

0x0262_0000

0x0252_03FF

0x0255_03FF

0x0260_BFFF

0x0262_07FF

0x03FF_FCB4

0x03FF_FCB6

0x03FF_FCB4

0x03FF_FCB4

MEMORY PROTECTION

Tracers

Reserved

Reserved

Reserved

Reserved

Reserved

Timers

PLL

GPIO

SmartReflex

PSC

DEBUG_SS, Tracer

Formatters

EFUSE

I

2

C, UART

CICs

Chip-level Registers

Table 8-55. Programmable Range n Registers Reset Values for MPU1

PROGRAMMA START ADDRESS

BLE RANGE (PROGn_MPSAR)

PROG0 0x3400_0000

PROG1

PROG2

0x3402_0000

0x3406_0000

PROG3

PROG4

0x3406_8000

0x340B_8000

END ADDRESS

(PROGn_MPEAR)

0x3401_FFFF

MPU1 (QM_SS DATA PORT)

MEMORY PAGE

PROTECTION ATTRIBUTE

(PROGn_MPPA)

0x03FF_FC80

0x3405_FFFF

0x3406_7FFF

0x340B_7FFF

0x340B_FFFF

0x000F_FCB6

0x03FF_FCB4

0x03FF_FC80

0x03FF_FCB6

MEMORY PROTECTION

Queue Manager subsystem data

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PROGRAMMA START ADDRESS

BLE RANGE (PROGn_MPSAR)

PROG0

PROG1

PROG2

PROG3

0x02A0_0000

0x02A2_0000

0x02A4_0000

0x02A6_0000

PROG4

PROG5

PROG6

PROG7

PROG8

PROG9

PROG10

0x02A6_8000

0x02A6_9000

0x02A6_A000

0x02A6_B000

0x02A6_C000

0x02A6_E000

0x02A8_0000

PROG11

PROG12

PROG13

PROG14

PROG15

0x02A9_0000

0x02AA_0000

0x02AA_8000

0x02AB_0000

0x02AB_8000

Table 8-56. Programmable Range n Registers Reset Values for MPU2

END ADDRESS

MPU2 (QM_SS CFG PORT)

(PROGn_MPEAR)

MEMORY PAGE

PROTECTION ATTRIBUTE

(PROGn_MPPA)

0x02A1_FFFF

0x02A3_FFFF

0x02A5_FFFF

0x02A6_7FFF

0x03FF_FCA4

0x000F_FCB6

0x000F_FCB6

0x03FF_FCB4

0x02A6_8FFF

0x02A6_9FFF

0x02A6_AFFF

0x02A6_BFFF

0x02A6_DFFF

0x02A6_FFFF

0x02A8_FFFF

0x02A9_FFFF

0x02AA_7FFF

0x02AA_FFFF

0x02AB_7FFF

0x02AB_FFFF

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCA4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB4

0x03FF_FCB6

MEMORY PROTECTION

Queue Manager subsystem configuration

Table 8-57. Programmable Range n Registers Reset Values for MPU3

PROGRAMMA START ADDRESS

BLE RANGE (PROGn_MPSAR)

PROG0 0x0264_0000

END ADDRESS

(PROGn_MPEAR)

0x0264_07FF

MPU3 (SEMAPHORE)

MEMORY PAGE

PROTECTION

ATTRIBUTES

(PROGn_MPPA)

0x0003_FCB6

MEMORY PROTECTION

Semaphore

Table 8-58. Programmable Range n Registers Reset Values for MPU4

PROGRAMMA START ADDRESS

BLE RANGE (PROGn_MPSAR)

PROG0 0x7000_0000

PROG1

PROG2

0x7100_0000

0x7200_0000

PROG3

PROG4

PROG5

PROG6

PROG7

0x7300_0000

0x7400_0000

0x7500_0000

0x7600_0000

0x7700_0000

PROG8

PROG9

PROG10

PROG11

PROG12

PROG13

PROG14

PROG15

0x7800_0000

0x7900_0000

0x7A00_0000

0x7B00_0000

0x7C00_0000

0x7D00_0000

0x7E00_0000

0x7F00_0000

END ADDRESS

(PROGn_MPEAR)

0x70FF_FFFF

0x71FF_FFFF

0x72FF_FFFF

0x73FF_FFFF

0x74FF_FFFF

0x75FF_FFFF

0x76FF_FFFF

0x77FF_FFFF

0x78FF_FFFF

0x79FF_FFFF

0x7AFF_FFFF

0x7BFF_FFFF

0x7CFF_FFFF

0x7DFF_FFFF

0x7EFF_FFFF

0x7FFF_FFFF

MPU4 (EMIF16)

MEMORY PAGE

PROTECTION ATTRIBUTE

(PROGn_MPPA)

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

0x03FF_FCB6

MEMORY PROTECTION

EMIF16 data

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8.10 DDR3 Memory Controller

The 32-bit DDR3 Memory Controller bus of the C6654 is used to interface to JEDEC-standard-compliant

DDR3 SDRAM devices. The DDR3 external bus interfaces only to DDR3 SDRAM devices; it does not share the bus with any other types of peripherals.

8.10.1 DDR3 Memory Controller Device-Specific Information

The C6654 includes one 32-bit wide 1.5-V DDR3 SDRAM EMIF interface. The DDR3 interface can operate at 800 Mega transfers per second (MTS) and 1033 MTS.

Due to the complicated nature of the interface, a limited number of topologies will be supported to provide a 16-bit or 32-bit interface.

The DDR3 electrical requirements are fully specified in the DDR Jedec Specification JESD79-3C.

Standard DDR3 SDRAMs are available in 8- and 16-bit versions, allowing for the following bank topologies to be supported by the interface:

• 36-bit: Three 16-bit SDRAMs (including 4 bits of ECC)

• 36-bit: Five 8-bit SDRAMs (including 4 bits of ECC)

• 32-bit: Two 16-bit SDRAMs

• 32-bit: Four 8-bit SDRAMs

• 16-bit: One 16-bit SDRAM

• 16-bit: Two 8-bit SDRAM

The approach to specifying interface timing for the DDR3 memory bus is different than on other interfaces such as I

2

C or SPI. For these other interfaces, the device timing was specified in terms of data manual specifications and I/O buffer information specification (IBIS) models. For the DDR3 memory bus, the approach is to specify compatible DDR3 devices and provide the printed circuit board (PCB) solution and guidelines directly to the user.

A race condition may exist when certain masters write data to the DDR3 memory controller. For example, if master A passes a software message via a buffer in external memory and does not wait for an indication that the write completes, before signaling to master B that the message is ready, when master B attempts to read the software message, then the master B read may bypass the master A write and, thus, master B may read stale data and, therefore, receive an incorrect message.

Some master peripherals (e.g., EDMA3 transfer controllers with TCCMOD=0) will always wait for the write to complete before signaling an interrupt to the system, thus avoiding this race condition. For masters that do not have a hardware specification of write-read ordering, it may be necessary to specify data ordering via software.

If master A does not wait for indication that a write is complete, it must perform the following workaround:

1. Perform the required write to DDR3 memory space.

2. Perform a dummy write to the DDR3 memory controller module ID and revision register.

3. Perform a dummy read from the DDR3 memory controller module ID and revision register.

4. Indicate to master B that the data is ready to be read after completion of the read in step 3. The completion of the read in step 3 ensures that the previous write was done.

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8.10.2 DDR3 Memory Controller Electrical Data/Timing

The KeyStone DSP DDR3 Implementation Guidelines ( SPRABI1 ) specifies a complete DDR3 interface solution as well as a list of compatible DDR3 devices. The DDR3 electrical requirements are fully specified in the DDR3 Jedec Specification JESD79-3C. TI has performed the simulation and system characterization to ensure all DDR3 interface timings in this solution are met; therefore, no electrical data/timing information is supplied here for this interface.

NOTE

TI supports only designs that follow the board design guidelines outlined in the application report.

8.11 I

2

C Peripheral

The inter-integrated circuit (I

2

C) module provides an interface between DSP and other devices compliant with Philips Semiconductors Inter-IC bus (I

2

C bus) specification version 2.1 and connected by way of an

I

2

C bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the DSP through the I

2

C module.

8.11.1 I

2

C Device-Specific Information

The C6654 device includes an I

2

C peripheral module.

NOTE

When using the I

2

C module, ensure there are external pullup resistors on the SDA and SCL pins.

The I

2

C modules on the C6654 may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.) or may be used to communicate with other controllers in a system or to implement a user interface.

The I

2

C port is compatible with Philips I

2

C specification revision 2.1 (January 2000) and supports:

• Fast mode up to 400 Kbps (no fail-safe I/O buffers)

• Noise filter to remove noise 50 ns or less

• 7-bit and 10-bit device addressing modes

• Multi-master (transmit/receive) and slave (transmit/receive) functionality

• Events: DMA, interrupt, or polling

• Slew-rate limited open-drain output buffers

Figure 8-31

shows a block diagram of the I

2

C module.

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2

I C Clock

SCL

Noise

Filter

2

I C Data

SDA

Noise

Filter

Clock

Prescale

2

I CPSC

Bit Clock

Generator

2

I CCLKL

Transmit

2

I CXSR

2

I CDXR

Transmit

Shift

Transmit

Buffer

Peripheral Clock

(CPU/6)

Control

2

I COAR

2

I CSAR

Own

Address

Slave

Address

Mode

Data

Count

Extended

Mode

Receive

2

I CRSR

Receive

Buffer

Receive

Shift

Interrupt/DMA

2

I CSTR

2

I CIVR

Interrupt

Mask/Status

Interrupt

Status

Interrupt

Vector

Shading denotes control/status registers.

Figure 8-31. I

2

C Module Block Diagram www.ti.com

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8.11.2 I

2

C Peripheral Register Description(s)

HEX ADDRESS RANGE

0253 0000

0253 0004

0253 0008

0253 000C

0253 0010

0253 0014

0253 0018

0253 001C

0253 0020

0253 0024

0253 0028

0253 002C

0253 0030

0253 0034

0253 0038

0253 003C - 0253 007F

REGISTER

ICOAR

ICIMR

ICSTR

ICCLKL

ICCLKH

ICCNT

ICDRR

ICSAR

ICDXR

ICMDR

ICIVR

ICEMDR

ICPSC

ICPID1

-

ICPID2

Table 8-59. I

2

C Registers

REGISTER NAME

I

2

C Own Address Register

I

2

C Interrupt Mask/Status Register

I

2

C Interrupt Status Register

I

2

C Clock Low-Time Divider Register

I

2

C Clock High-Time Divider Register

I

2

C Data Count Register

I

2

C Data Receive Register

I

2

C Slave Address Register

I

2

C Data Transmit Register

I

2

C Mode Register

I

2

C Interrupt Vector Register

I

2

C Extended Mode Register

I

2

C Prescaler Register

I

2

C Peripheral Identification Register 1 [Value: 0x0000 0105]

I

2

C Peripheral Identification Register 2 [Value: 0x0000 0005]

Reserved

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8.11.3 I

2

C Electrical Data/Timing

8.11.3.1 Inter-Integrated Circuits (I

2

C) Timing

8.12 I

2

C Timing Requirements

(1)

(see

Figure 8-32 )

NO.

1

2

STANDARD MODE

MIN MAX

10

FAST MODE

MIN

UNIT

MAX S

2.5

µs t t c(SCL) su(SCLH-SDAL)

Cycle time, SCL

Setup time, SCL high before SDA low (for a repeated

START condition)

4.7

0.6

µs

3 t h(SDAL-SCLL)

Hold time, SCL low after SDA low (for a START and a repeated START condition)

Pulse duration, SCL low

4 0.6

µs

4

5

6

7 t w(SCLL) t w(SCLH) t su(SDAV-SCLH) t h(SCLL-SDAV)

Pulse duration, SCL high

Setup time, SDA valid before SCL high

Hold time, SDA valid after SCL low (For I

2

C bus devices)

4.7

0

4

250

(3)

3.45

1.3

0.6

100

0

(2)

(3)

0.9

(4)

µs

µs ns

µs

8 t w(SDAH)

Pulse duration, SDA high between STOP and START conditions

4.7

1.3

µs

9

10

11

12 t t r(SDA) r(SCL) t f(SDA) t f(SCL)

Rise time, SDA

Rise time, SCL

Fall time, SDA

Fall time, SCL

1000 20 + 0.1C

b

(5)

1000 20 + 0.1C

b

(5)

300 20 + 0.1C

b

(5)

300 20 + 0.1C

b

(5)

300

300

300

300 ns ns ns ns

13

14

15 t su(SCLH-SDAH) t w(SP)

C b

(5)

Setup time, SCL high before SDA high (for STOP condition)

Pulse duration, spike (must be suppressed)

Capacitive load for each bus line

4

400

0.6

0 50

400

µs ns pF

(1) The I

2

C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down

(2) A Fast-mode I

2

C-bus™ device can be used in a Standard-mode I

2

C-bus™ system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t

(according to the Standard-mode I

2

C-Bus Specification) before the SCL line is released.

r max + t su(SDA-SCLH)

= 1000 + 250 = 1250 ns

(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V

IHmin undefined region of the falling edge of SCL.

of the SCL signal) to bridge the

(4) The maximum t h(SDA-SCLL)

(5) C b has only to be met if the device does not stretch the low period [t w(SCLL)

] of the SCL signal.

= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

11 9

SDA

8

6

4

10

5

14

13

SCL

1

12

3

7

3

2

Stop Start Repeated

Start

Figure 8-32. I

2

C Receive Timings

Stop

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Table 8-60. I

2

C Switching Characteristics

(1)

(see

Figure 8-33 )

NO.

16 t c(SCL)

17

18 t t su(SCLH-SDAL) h(SDAL-SCLL)

PARAMETER

Cycle time, SCL

Setup time, SCL high to SDA low (for a repeated START condition)

Hold time, SDA low after SCL low (for a START and a repeated START condition)

STANDARD MODE

MIN

10

4.7

4

MAX

FAST MODE

MIN

2.5

0.6

0.6

19 t w(SCLL)

20 t w(SCLH)

21 t

22 t

23 t d(SDAV-SDLH) v(SDLL-SDAV) w(SDAH)

Pulse duration, SCL low

Pulse duration, SCL high

Delay time, SDA valid to SCL high

Valid time, SDA valid after SCL low (For I

2

C bus devices)

Pulse duration, SDA high between STOP and START conditions

4.7

4

250

0

4.7

1.3

0.6

100

0

1.3

24 t r(SDA)

25 t r(SCL)

26 t f(SDA)

27 t f(SCL)

28 t d(SCLH-SDAH)

29 C p

Rise time, SDA

Rise time, SCL

Fall time, SDA

Fall time, SCL

Delay time, SCL high to SDA high (for STOP condition)

Capacitance for each I

2

C pin

4

1000 20 + 0.1C

b

(1)

1000 20 + 0.1C

b

(1)

300 20 + 0.1C

b

(1)

300 20 + 0.1C

b

(1)

10

(1) C b

= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.

0.6

MAX UNIT

ms ms ms ms ms ns

0.9

ms ms

300 ns

300 ns

300 ns

300 ns ms

10 pF

26

24

SDA

23

21

19

25

20

28

SCL

16

27

17

18

18

22

Stop Start Repeated

Start

Figure 8-33. I

2

C Transmit Timings

Stop

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7

7

7

7

8

8

8

8

8.13 SPI Peripheral

The serial peripheral interconnect (SPI) module provides an interface between the DSP and other SPIcompliant devices. The primary intent of this interface is to allow for connection to an SPI ROM for boot.

The SPI module on the C6654 is supported only in master mode. Additional chip-level components can also be included, such as temperature sensors or an I/O expander.

8.13.1 SPI Electrical Data/Timing

8.13.1.1 SPI Timing

Table 8-61. SPI Timing Requirements

(See

Figure 8-34 )

NO.

MIN MAX UNIT

tsu(SDI-SPC) tsu(SDI-SPC) tsu(SDI-SPC) tsu(SDI-SPC) th(SPC-SDI) th(SPC-SDI) th(SPC-SDI) th(SPC-SDI)

Master Mode Timing Diagrams — Base Timings for 3 Pin Mode

Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 0

Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 0 Phase = 1

Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 0

Input Setup Time, SPIDIN valid before receive edge of SPICLK. Polarity = 1 Phase = 1

Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 0

Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 0 Phase = 1

Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 0

Input Hold Time, SPIDIN valid after receive edge of SPICLK. Polarity = 1 Phase = 1

2

2

2

2

5

5

5

5 ns ns ns ns ns ns ns ns

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Table 8-62. SPI Switching Characteristics

(See

Figure 8-34

and

Figure 8-35 )

NO.

4

4

4

5

5

5

5

6

6

6

6

19

19

19

19

20

1

2

3

4

20

20

20 tc(SPC) tw(SPCH) tw(SPCL) td(SDO-SPC) td(SDO-SPC) td(SDO-SPC) td(SDO-SPC) td(SPC-SDO) td(SPC-SDO) td(SPC-SDO) td(SPC-SDO) toh(SPC-SDO) toh(SPC-SDO) toh(SPC-SDO) toh(SPC-SDO) td(SCS-SPC) td(SCS-SPC) td(SCS-SPC) td(SCS-SPC) td(SPC-SCS) td(SPC-SCS) td(SPC-SCS) td(SPC-SCS) tw(SCSH)

PARAMETER

Master Mode Timing Diagrams — Base Timings for 3 Pin Mode

Cycle Time, SPICLK, All Master Modes

Pulse Width High, SPICLK, All Master Modes

Pulse Width Low, SPICLK, All Master Modes

Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.

Polarity = 0, Phase = 0.

Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.

Polarity = 0, Phase = 1.

Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK

Polarity = 1, Phase = 0

Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK

Polarity = 1, Phase = 1

Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on

SPICLK. Polarity = 0 Phase = 0

Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK

Polarity = 0 Phase = 1

Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK

Polarity = 1 Phase = 0

Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on SPICLK

Polarity = 1 Phase = 1

MIN

3*P2

(1)

0.5*tc - 1

0.5*tc - 1

MAX

5

5

5

5

2

2

2

2

Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 0 Phase = 0

Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 0 Phase = 1

Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 1 Phase = 0

Output hold time, SPIDOUT valid after receive edge of SPICLK except for final bit. Polarity = 1 Phase = 1

Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 0

Phase = 1

Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 1

Phase = 0

Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 1

Phase = 1

Minimum inactive time on SPISCS[n] pin between two transfers when SPISCS[n] is not held using the CSHOLD feature.

0.5*tc - 2

0.5*tc - 2

0.5*tc - 2

0.5*tc - 2

Additional SPI Master Timings — 4 Pin Mode with Chip Select Option

Delay from SPISCS[n] active to first SPICLK. Polarity = 0 Phase = 0

Delay from SPISCS[n] active to first SPICLK. Polarity = 0 Phase = 1

2*P2 - 5 2*P2 + 5

0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5

Delay from SPISCS[n] active to first SPICLK. Polarity = 1 Phase = 0

Delay from SPISCS[n] active to first SPICLK. Polarity = 1 Phase = 1

Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 0

Phase = 0

2*P2 - 5

0.5*tc + (2*P2) - 5

1*P2 - 5

2*P2 + 5

0.5*tc + (2*P2) + 5

1*P2 + 5

0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5

1*P2 - 5

0.5*tc + (1*P2) - 5

2*P2 - 5

1*P2 + 5

0.5*tc + (1*P2) + 5

(1) P2 = 1/SYSCLK7

UNIT

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

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SPICLK

SPIDOUT

SPIDIN

2

1

3

4

MO(0)

7

MI(0)

8

5

MO(1)

MI(1)

MASTER MODE

POLARITY = 0 PHASE = 0

6

MO(n−1)

MI(n−1)

MO(n)

MI(n)

SPICLK

SPIDOUT

SPIDIN

MASTER MODE

POLARITY = 0 PHASE = 1

4

MO(0)

7

MI(0)

8

5

MO(1)

6

MI(1)

MO(n−1)

MI(n−1)

MO(n)

MI(n)

4

MO(0)

7

MI(0)

8

5

MO(1)

MI(1)

MASTER MODE

POLARITY = 1 PHASE = 0

6

MO(n−1)

MI(n−1)

MO(n)

MI(n)

SPICLK

SPIDOUT

SPIDIN

MASTER MODE

POLARITY = 1 PHASE = 1

SPICLK

SPIDOUT

4

MO(0)

7

MI(0)

8

5

MO(1)

6

MO(n−1) MO(n)

SPIDIN

MI(1) MI(n−1) MI(n)

Figure 8-34. SPI Master Mode Timing Diagrams — Base Timings for 3 Pin Mode

MASTER MODE 4 PIN WITH CHIP SELECT

19 20

SPICLK

SPIDOUT

SPIDIN

SPISCSx

MO(0)

MI(0)

MO(1)

MI(1)

MO(n−1)

MI(n−1)

MO(n)

MI(n)

Figure 8-35. SPI Additional Timings for 4 Pin Master Mode with Chip Select Option

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8.14 UART Peripheral

The universal asynchronous receiver/transmitter (UART) module provides an interface between the DSP and a UART terminal interface or other UART-based peripheral. The UART is based on the industry standard TL16C550 asynchronous communications element, which, in turn, is a functional upgrade of the

TL16C450. Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the

UART can be placed in an alternate FIFO (TL16C550) mode. This relieves the DSP of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to

16 bytes including three additional bits of error status per byte for the receiver FIFO.

The UART performs serial-to-parallel conversions on data received from a peripheral device and parallelto-serial conversion on data received from the DSP. The DSP can read the UART status at any time. The

UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link. For more information on UART, see the Universal

Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User's Guide ( SPRUGP1 ).

Table 8-63. UART Timing Requirements

(see

Figure 8-36

and

Figure 8-37 )

NO.

5

6

6

6

4

5

8 tw(RXSTART) tw(RXH) tw(RXL) tw(RXSTOP1) tw(RXSTOP15) tw(RXSTOP2) td(CTSL-TX)

Receive Timing

Pulse width, receive start bit

Pulse width, receive data/parity bit high

Pulse width, receive data/parity bit low

Pulse width, receive stop bit 1

Pulse width, receive stop bit 1.5

Pulse width, receive stop bit 2

Autoflow Timing Requirements

Delay time, CTS asserted to START bit transmit

(1) U = UART baud time = 1/programmed baud rate

(2) P = 1/SYSCLK7

MIN

0.96U

(1)

0.96U

0.96U

1.05U

1.05U

1.05U

0.96U

1.05U

1.5*(0.96U) 1.5*(1.05U)

2*(0.96U) 2*(1.05U)

P

(2)

MAX

5P

UNIT

ns ns ns ns ns ns ns

RXD

Stop/Idle

4

Start Bit 0

5

Bit 1 Bit N-1 Bit N

5

Parity

6

Stop Idle Start

Figure 8-36. UART Receive Timing Waveform

8

TXD Bit N-1 Bit N Stop Start Bit 0

CTS

Figure 8-37. UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform

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Table 8-64. UART Switching Characteristics

(See

Figure 8-38

and

Figure 8-39 )

NO.

2

3

1

2

3

3

7 tw(TXSTART) tw(TXH) tw(TXL) tw(TXSTOP1) tw(TXSTOP15) tw(TXSTOP2) td(RX-RTSH)

PARAMETER

Transmit Timing

Pulse width, transmit start bit

Pulse width, transmit data/parity bit high

Pulse width, transmit data/parity bit low

Pulse width, transmit stop bit 1

Pulse width, transmit stop bit 1.5

Pulse width, transmit stop bit 2

Autoflow Timing Requirements

Delay time, STOP bit received to RTS deasserted

(1) U = UART baud time = 1/programmed baud rate

(2) P = 1/SYSCLK7

MIN

P

(2)

MAX

U

(1)

- 2

U - 2

U - 2

U - 2

U + 2

U + 2

U + 2

U + 2

1.5 * (U - 2) 1.5 * ('U + 2)

2 * (U - 2) 2 * ('U + 2)

5P

UNIT

ns ns ns ns ns ns ns

TXD Stop/Idle

1

Start Bit 0

2

Bit 1 Bit N-1 Bit N

2

Parity

3

Stop Idle Start

Figure 8-38. UART Transmit Timing Waveform

RXD Bit N-1 Bit N

7

Stop Start

CTS

Figure 8-39. UART RTS (Request-to-Send Output) — Autoflow Timing Waveform

8.15 PCIe Peripheral

The two-lane PCI express (PCIe) module on the device provides an interface between the DSP and other

PCIe-compliant devices. The PCI Express module provides low-pin-count, high-reliability, and high-speed data transfer at rates of 5.0 GBaud per lane on the serial links. For more information, see the Peripheral

Component Interconnect Express (PCIe) for KeyStone Devices User's Guide ( SPRUGS6 ). The PCIe electrical requirements are fully specified in the PCI Express Base Specification Revision 2.0 of PCI-SIG.

TI has performed the simulation and system characterization to ensure all PCIe interface timings in this solution are met; therefore, no electrical data/timing information is supplied here for this interface.

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8.16 EMIF16 Peripheral

The EMIF16 module provides an interface between DSP and external memories such as NAND and NOR flash. For more information, see the External Memory Interface (EMIF16) for KeyStone Devices User's

Guide ( SPRUGZ3 ).

8.16.1 EMIF16 Electrical Data/Timing

15

23

24

24

20

21

22

26

27

25

16

17

16

17

18

19

Table 8-65. EMIF16 Asynchronous Memory Timing Requirements

(1) (2)

(see

Figure 8-40

and

Figure 8-41 )

NO.

2

28

14

3 t w

(WAIT) t d

(WAIT-WEH) t d

(WAIT-OEH) t

C

(CEL)

General Timing

Pulse duration, WAIT assertion and deassertion minimum time

Setup time, WAIT asserted before WE high

Setup time, WAIT asserted before OE high

Read Timing

EMIF read cycle time when ew = 0, meaning not in extended wait mode

MIN

3

10

10

11

12

7

8

9

13

4

5

6

4

5

15 t

C

(CEL) t osu

(CEL-OEL) t oh

(OEH-CEH) t osu

(CEL-OEL) t oh

(OEH-CEH) t osu

(BAV-OEL) t oh

(OEH-BAIV) t osu

(AV-OEL) t oh

(OEH-AIV) t w

(OEL) t w

(OEL) t d

(WAITH-OEH) t su

(D-OEH) t h

(OEH-D)

EMIF read cycle time when ew =1, meaning extended wait mode enabled

Output setup time from CE low to OE low. SS = 0, not in select strobe mode

Output hold time from OE high to CE high. SS = 0, not in select strobe mode

Output setup time from CE low to OE low in select strobe mode, SS = 1

Output hold time from OE high to CE high in select strobe mode, SS = 1

Output setup time from BA valid to OE low

Output hold time from OE high to BA invalid

Output setup time from A valid to OE low

Output hold time from OE high to A invalid

OE active time low, when ew = 0. Extended wait mode is disabled.

OE active time low, when ew = 1. Extended wait mode is enabled.

Delay time from WAIT deasserted to OE# high

Input setup time from D valid to OE high

Input hold time from OE high to D invalid

Write Timing

EMIF write cycle time when ew = 0, meaning not in extended wait mode

MAX

2E

4E + 3

4E + 3

(RS+RST+RH+3 (RS+RST+RH+3

)*E-3 )*E+3

(RS+RST+WAIT (RS+RST+WAIT

+RH+3)*E-3 +RH+3)*E+3

(RS+1) * E - 3

(RH+1) * E - 3

(RS+1) * E + 3

(RH+1) * E + 3

(RS+1) * E - 3

(RH+1) * E - 3

(RS+1) * E - 3

(RH+1) * E - 3

(RS+1) * E - 3

(RH+1) * E - 3

(RS+1) * E + 3

(RH+1) * E + 3

(RS+1) * E + 3

(RH+1) * E + 3

(RS+1) * E + 3

(RH+1) * E + 3

(RST+1) * E - 3 (RST+1) * E + 3

(RST+1) * E - 3 (RST+1) * E + 3

4E + 3

3

0.5

t c

(CEL) t c

(CEL) t osu

CEL-WEL) t oh

(WEH-CEH) t osu

CEL-WEL) t oh

(WEH-CEH) t osu

(RNW-WEL) t oh

(WEH-RNW) t osu

(BAV-WEL) t oh

(WEH-BAIV) t osu

(AV-WEL) t oh

(WEH-AIV) t w

(WEL) t w

(WEL) t osu

(DV-WEL) t oh

(WEH-DIV) t d

(WAITH-WEH)

EMIF write cycle time when ew =1., meaning extended wait mode is enabled

Output setup time from CE low to WE low. SS = 0, not in select strobe mode

Output hold time from WE high to CE high. SS = 0, not in select strobe mode

Output setup time from CE low to WE low in select strobe mode, SS = 1

Output hold time from WE high to CE high in select strobe mode, SS = 1

Output setup time from RNW valid to WE low

Output hold time from WE high to RNW invalid

Output setup time from BA valid to WE low

Output hold time from WE high to BA invalid

Output setup time from A valid to WE low

Output hold time from WE high to A invalid

WE active time low, when ew = 0. Extended wait mode is disabled.

WE active time low, when ew = 1. Extended wait mode is enabled.

Output setup time from D valid to WE low

Output hold time from WE high to D invalid

Delay time from WAIT deasserted to WE# high

(WS+WST+WH+ (WS+WST+WH+

3)*E-3 3)*E+3

(WS+WST+WAI (WS+WST+WAI

T+WH+3)*E-3 T+WH+3)*E+3

(WS+1) * E - 3

(WH+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

(WST+1) * E - 3

(WST+1) * E - 3

(WS+1) * E - 3

(WH+1) * E - 3

4E + 3

UNIT

ns ns ns ns ns ns ns

(1) E = 1/SYSCLK7, RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold.

(2) WAIT = number of cycles wait is asserted between the programmed end of the strobe period and wait de-assertion.

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

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3

EM_CE[3:0]

EM_R/W

EM_BA[1:0]

EM_A[21:0]

6

8

4 9

7

5

10

EM_OE

12 13

EM_D[15:0]

EM_WE

Figure 8-40. EMIF16 Asynchronous Memory Read Timing Diagram

15

EM_CE[3:0]

EM_R/W

EM_BA[1:0]

EM_A[21:0]

16

18

20

22

19

21

23

17

24

EM_WE

26

27

EM_D[15:0]

EM_OE

Figure 8-41. EMIF16 Asynchronous Memory Write Timing Diagram

Setup Strobe Extended Due to EM_WAIT Strobe Hold

EM_CE[3:0]

EM_BA[1:0]

EM_A[21:0]

EM_D[15:0]

204

EM_OE

EM_WAIT

2

Asserted

14

2

Deasserted

11

Figure 8-42. EMIF16 EM_WAIT Read Timing Diagram

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EM_CE[3:0]

EM_BA[1:0]

EM_A[21:0]

EM_D[15:0]

EM_WE

EM_WAIT

Setup Strobe

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Extended Due to EM_WAIT Strobe Hold

2

Asserted

28

2

Deasserted

25

Figure 8-43. EMIF16 EM_WAIT Write Timing Diagram

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8.17 Ethernet Media Access Controller (EMAC)

The Ethernet media access controller (EMAC) module provides an efficient interface between the C6654

DSP core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/second

[Mbps]), and 100BaseTX (100 Mbps), in half- or full-duplex mode, and 1000BaseT (1000 Mbps) in fullduplex mode, with hardware flow control and quality-of-service (QOS) support.

The EMAC module conforms to the IEEE 802.3-2002 standard, describing the Carrier Sense Multiple

Access with Collision Detection (CSMA/CD) Access Method and Physical Layer specifications. The IEEE

802.3 standard has also been adopted by ISO/IEC and re-designated as ISO/IEC 8802-3:2000(E).

Deviating from this standard, the EMAC module does not use the transmit coding error signal MTXER.

Instead of driving the error pin when an underflow condition occurs on a transmitted frame, the EMAC will intentionally generate an incorrect checksum by inverting the frame CRC, so that the transmitted frame will be detected as an error by the network.

The EMAC control module is the main interface between the device core processor, the MDIO module, and the EMAC module. The relationship between these three components is shown in

Figure 8-44

. The

EMAC control module contains the necessary components to allow the EMAC to make efficient use of device memory, plus it controls device interrupts. The EMAC control module incorporates 8K bytes of internal RAM to hold EMAC buffer descriptors.

Interrupt

Controller

Configuration Bus

DMA Memory

Transfer Controller

Peripheral Bus

EMAC/MDIO

Interrupt

EMAC Control Module

EMAC Module MDIO Module

Ethernet Bus

MDIO Bus

Figure 8-44. EMAC, MDIO, and EMAC Control Modules

For more detailed information on the EMAC/MDIO, see Gigabit Ethernet (GbE) Subsystem for KeyStone

Devices User's Guide ( SPRUGV9 ).

8.17.1 EMAC Device-Specific Information

The EMAC module on the device supports Serial Gigabit Media Independent Interface (SGMII). The

SGMII interface conforms to version 1.8 of the industry standard specification.

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HEX ADDRESS

02C0 8000

02C0 8004

02C0 8008

02C0 800F

02C0 8010

02C0 8014

02C0 8018

02C0 801C

02C0 8020 - 02C0 807C

02C0 8080

02C0 8084

02C0 8088

02C0 808C

02C0 8090

02C0 8094

02C0 8098 - 02C0 819C

02C0 80A0

02C0 80A4

02C0 80A8

02C0 80AC

02C0 80B0

02C0 80B4

02C0 80B8

02C0 80BC

02C0 80C0 - 02C0 80FC

02C0 8100

02C0 8104

02C0 8108

02C0 810C

02C0 8110

02C0 8114

02C0 8118 - 02C0 811C

02C0 8120

02C0 8124

02C0 8128

02C0 812C

02C0 8130

02C0 8134

02C0 8138

02C0 813C

02C0 8140

02C0 8144

02C0 8148

02C0 814C

8.17.2 EMAC Peripheral Register Description(s)

The memory maps of the EMAC are shown in

Table 8-66

through

Table 8-71

.

Table 8-66. Ethernet MAC (EMAC) Control Registers

ACRONYM

TXIDVER

TXCONTROL

TXTEARDOWN

-

RXIDVER

RXCONTROL

RXTEARDOWN

-

-

TXINTSTATRAW

TXINTSTATMASKED

TXINTMASKSET

TXINTMASKCLEAR

MACINVECTOR

MACEOIVECTOR

-

RXINTSTATRAW

RXINTSTATMASKED

RXINTMASKSET

REGISTER NAME

Transmit Identification and Version Register

Transmit Control Register

Transmit Teardown register

Reserved

Receive Identification and Version Register

Receive Control Register

Receive Teardown Register

Reserved

Reserved

Transmit Interrupt Status (Unmasked) Register

Transmit Interrupt Status (Masked) Register

Transmit Interrupt Mask Set Register

Transmit Interrupt Mask Clear Register

MAC Input Vector Register

MAC End of Interrupt Vector Register

Reserved

Receive Interrupt Status (Unmasked) Register

Receive Interrupt Status (Masked) Register

Receive Interrupt Mask Set Register

RXINTMASKCLEAR Receive Interrupt Mask Clear Register

MACINTSTATRAW MAC Interrupt Status (Unmasked) Register

MACINTSTATMASKED MAC Interrupt Status (Masked) Register

MACINTMASKSET

MACINTMASKCLEAR

MAC Interrupt Mask Set Register

MAC Interrupt Mask Clear Register

-

RXMBPENABLE

RXUNICASTSET

RXUNICASTCLEAR

RXMAXLEN

Reserved

Receive Multicast/Broadcast/Promiscuous Channel Enable Register

Receive Unicast Enable Set Register

Receive Unicast Clear Register

Receive Maximum Length Register

RXBUFFEROFFSET Receive Buffer Offset Register

RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register

Reserved

RX0FLOWTHRESH

RX1FLOWTHRESH

Receive Channel 0 Flow Control Threshold Register

Receive Channel 1 Flow Control Threshold Register

RX2FLOWTHRESH

RX3FLOWTHRESH

RX4FLOWTHRESH

RX5FLOWTHRESH

RX6FLOWTHRESH

Receive Channel 2 Flow Control Threshold Register

Receive Channel 3 Flow Control Threshold Register

Receive Channel 4 Flow Control Threshold Register

Receive Channel 5 Flow Control Threshold Register

Receive Channel 6 Flow Control Threshold Register

RX7FLOWTHRESH

RX0FREEBUFFER

RX1FREEBUFFER

RX2FREEBUFFER

RX3FREEBUFFER

Receive Channel 7 Flow Control Threshold Register

Receive Channel 0 Free Buffer Count Register

Receive Channel 1 Free Buffer Count Register

Receive Channel 2 Free Buffer Count Register

Receive Channel 3 Free Buffer Count Register

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Table 8-66. Ethernet MAC (EMAC) Control Registers (continued)

MACADDRHI

MACINDEX

-

TX0HDP

TX1HDP

TX2HDP

TX3HDP

TX4HDP

TX5HDP

TX6HDP

TX7HDP

RX0HDP

RX1HDP

RX2HDP

RX3HDP

RX4HDP

RX5HDP

RX6HDP

RX7HDP

TX0CP

TX1CP

TX2CP

TX3CP

TX4CP

TX5CP

TX6CP

ACRONYM

RX4FREEBUFFER

RX5FREEBUFFER

RX6FREEBUFFER

RX7FREEBUFFER

MACCONTROL

MACSTATUS

EMCONTROL

FIFOCONTROL

MACCONFIG

SOFTRESET

MACSRCADDRLO

MACSRCADDRHI

MACHASH1

MACHASH2

BOFFTEST

TPACETEST

RXPAUSE

TXPAUSE

-

-

MACADDRLO

HEX ADDRESS

02C0 8150

02C0 8154

02C0 8158

02C0 815C

02C0 8160

02C0 8164

02C0 8168

02C0 816C

02C0 8170

02C0 8174

02C0 81D0

02C0 81D4

02C0 81D8

02C0 81DC

02C0 81E0

02C0 81E4

02C0 81E8

02C0 81EC

02C0 8200 - 02C0 82FC

02C0 8300 - 02C0 84FC

02C0 8500

02C0 8504

02C0 8508

02C0 850C - 02C0 85FC

02C0 8600

02C0 8604

02C0 8608

02C0 860C

02C0 8610

02C0 8614

02C0 8618

02C0 861C

02C0 8620

02C0 8624

02C0 8628

02C0 862C

02C0 8630

02C0 8634

02C0 8638

02C0 863C

02C0 8640

02C0 8644

02C0 8648

02C0 864C

02C0 8650

02C0 8654

02C0 8658

REGISTER NAME

Receive Channel 4 Free Buffer Count Register

Receive Channel 5 Free Buffer Count Register

Receive Channel 6 Free Buffer Count Register

Receive Channel 7 Free Buffer Count Register

MAC Control Register

MAC Status Register

Emulation Control Register

FIFO Control Register

MAC Configuration Register

Soft Reset Register

MAC Source Address Low Bytes Register

MAC Source Address High Bytes Register

MAC Hash Address Register 1

MAC Hash Address Register 2

Back Off Test Register

Transmit Pacing Algorithm Test Register

Receive Pause Timer Register

Transmit Pause Timer Register

See

Table 8-67

Reserved

MAC Address Low Bytes Register (used in Receive Address Matching)

MAC Address High Bytes Register (used in Receive Address Matching)

MAC Index Register

Reserved

Transmit Channel 0 DMA Head Descriptor Pointer Register

Transmit Channel 1 DMA Head Descriptor Pointer Register

Transmit Channel 2 DMA Head Descriptor Pointer Register

Transmit Channel 3 DMA Head Descriptor Pointer Register

Transmit Channel 4 DMA Head Descriptor Pointer Register

Transmit Channel 5 DMA Head Descriptor Pointer Register

Transmit Channel 6 DMA Head Descriptor Pointer Register

Transmit Channel 7 DMA Head Descriptor Pointer Register

Receive Channel 0 DMA Head Descriptor Pointer Register

Receive t Channel 1 DMA Head Descriptor Pointer Register

Receive Channel 2 DMA Head Descriptor Pointer Register

Receive t Channel 3 DMA Head Descriptor Pointer Register

Receive Channel 4 DMA Head Descriptor Pointer Register

Receive t Channel 5 DMA Head Descriptor Pointer Register

Receive Channel 6 DMA Head Descriptor Pointer Register

Receive t Channel 7 DMA Head Descriptor Pointer Register

Transmit Channel 0 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 1 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 2 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 3 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 4 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 5 Completion Pointer (Interrupt Acknowledge) Register

Transmit Channel 6 Completion Pointer (Interrupt Acknowledge) Register

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HEX ADDRESS

02C0 8200

02C0 8204

02C0 8208

02C0 820C

02C0 8210

02C0 8214

02C0 8218

02C0 821C

02C0 8220

02C0 8224

02C0 8228

02C0 822C

02C0 8230

02C0 8234

02C0 8238

02C0 823C

02C0 8240

02C0 8244

02C0 8248

02C0 824C

02C0 8250

02C0 8254

02C0 8258

02C0 825C

02C0 8260

02C0 8264

02C0 8268

HEX ADDRESS

02C0 865C

02C0 8660

02C0 8664

02C0 8668

02C0 866C

02C0 8670

02C0 8674

02C0 8678

02C0 867C

02C0 8680 - 02C0 86FC

02C0 8700 - 02C0 877C

02C0 8780 - 02C0 8FFF

Table 8-66. Ethernet MAC (EMAC) Control Registers (continued)

ACRONYM

TX7CP

RX0CP

RX1CP

RX2CP

RX3CP

RX4CP

RX5CP

RX6CP

RX7CP

-

-

-

REGISTER NAME

Transmit Channel 7 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 0 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 1 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 2 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 3 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 4 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 5 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 6 Completion Pointer (Interrupt Acknowledge) Register

Receive Channel 7 Completion Pointer (Interrupt Acknowledge) Register

Reserved

Reserved

Reserved

Table 8-67. EMAC Statistics Registers

ACRONYM

RXGOODFRAMES

RXBCASTFRAMES

RXMCASTFRAMES

RXPAUSEFRAMES

RXCRCERRORS

RXALIGNCODEERRORS

RXOVERSIZED

RXJABBER

RXUNDERSIZED

RXFRAGMENTS

RXFILTERED

RXQOSFILTERERED

RXOCTETS

TXGOODFRAMES

TXBCASTFRAMES

TXMCASTFRAMES

TXPAUSEFRAMES

TXDEFERED

TXCOLLISION

TXSINGLECOLL

TXMULTICOLL

TXEXCESSIVECOLL

TXLATECOLL

TXUNDERRUN

TXCARRIERSENSE

TXOCTETS

FRAME64

REGISTER NAME

Good Receive Frames Register

Broadcast Receive Frames Register (Total number of Good Broadcast Frames

Receive)

Multicast Receive Frames Register (Total number of Good Multicast Frames

Received)

Pause Receive Frames Register

Receive CRC Errors Register (Total number of Frames Received with CRC

Errors)

Receive Alignment/Code Errors register (Total number of frames received with alignment/code errors)

Receive Oversized Frames Register (Total number of Oversized Frames

Received)

Receive Jabber Frames Register (Total number of Jabber Frames Received)

Receive Undersized Frames Register (Total number of Undersized Frames

Received)

Receive Frame Fragments Register

Filtered Receive Frames Register

Received QOS Filtered Frames Register

Receive Octet Frames Register (Total number of Received Bytes in Good

Frames)

Good Transmit Frames Register (Total number of Good Frames Transmitted)

Broadcast Transmit Frames Register

Multicast Transmit Frames Register

Pause Transmit Frames Register

Deferred Transmit Frames Register

Transmit Collision Frames Register

Transmit Single Collision Frames Register

Transmit Multiple Collision Frames Register

Transmit Excessive Collision Frames Register

Transmit Late Collision Frames Register

Transmit Under Run Error Register

Transmit Carrier Sense Errors Register

Transmit Octet Frames Register

Transmit and Receive 64 Octet Frames Register

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HEX ADDRESS

02C0 826C

02C0 8270

02C0 8274

02C0 8278

02C0 827C

02C0 8280

02C0 8284

02C0 8288

02C0 828C

02C0 8290 - 02C0 82FC

HEX ADDRESS

02C0 A000 - 02C0 BFFF

HEX ADDRESS

02C0 8900

02C0 8904

02C0 8910

02C0 8914

02C0 8918

02C0 891C

02C0 8920

02C0 8924 - 02C0 8948

Table 8-67. EMAC Statistics Registers (continued)

ACRONYM

FRAME65T127

FRAME128T255

FRAME256T511

FRAME512T1023

FRAME1024TUP

NETOCTETS

RXSOFOVERRUNS

RXMOFOVERRUNS

RXDMAOVERRUNS

-

REGISTER NAME

Transmit and Receive 65 to 127 Octet Frames Register

Transmit and Receive 128 to 255 Octet Frames Register

Transmit and Receive 256 to 511 Octet Frames Register

Transmit and Receive 512 to 1023 Octet Frames Register

Transmit and Receive 1024 to 1518 Octet Frames Register

Network Octet Frames Register

Receive FIFO or DMA Start of Frame Overruns Register

Receive FIFO or DMA Middle of Frame Overruns Register

Receive DMA Start of Frame and Middle of Frame Overruns Register

Reserved

Table 8-68. EMAC Descriptor Memory

ACRONYM

-

REGISTER NAME

EMAC Descriptor Memory

Table 8-69. SGMII Control Registers

ACRONYM

IDVER

SOFT_RESET

CONTROL

STATUS

MR_ADV_ABILITY

-

MR_LP_ADV_ABILITY

-

REGISTER NAME

Identification and Version register

Software Reset Register

Control Register

Status Register

Advertised Ability Register

Reserved

Link Partner Advertised Ability Register

Reserved

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HEX ADDRESS

02C0 8A00

02C0 8A04

02C0 8A08

02C0 8A0C

02C0 8A10

02C0 8A14

02C0 8A18

02C0 8A1C

02C0 8A10

02C0 8A14

02C0 8A18

02C0 8A1C

02C0 8A90

02C0 8A94

02C0 8A98

02C0 8A9C

02C0 8AA0

02C0 8AA4

02C0 8AA8

02C0 8AAC

02C0 8B10

02C0 8B14

02C0 8B18

02C0 8B1C

Table 8-70. EMIC Control Registers

ACRONYM

IDVER

SOFT_RESET

EM_CONTROL

INT_CONTROL

C0_RX_THRESH_EN

C0_RX_EN

C0_TX_EN

C0_MISC_EN

Reserved

Reserved

Reserved

Reserved

REGISTER NAME

Identification and Version register

Software Reset Register

Emulation Control Register

Interrupt Control Register

Receive Threshold Interrupt Enable Register for CorePac0

Receive Interrupt Enable Register for CorePac0

Transmit Interrupt Enable Register for CorePac0

Misc Interrupt Enable Register for CorePac0

C0_RX_THRESH_STAT Receive Threshold Masked Interrupt Status Register for CorePac0

C0_RX_STAT

C0_TX_STAT

Receive Interrupt Masked Interrupt Status Register for CorePac0

Transmit Interrupt Masked Interrupt Status Register for CorePac0

C0_MISC_STAT

Reserved

Misc Interrupt Masked Interrupt Status Register for CorePac0

Reserved

Reserved

Reserved

C0_RX_IMAX

C0_TX_IMAX

Reserved

Reserved

Receive Interrupts Per Millisecond for CorePac0

Transmit Interrupts Per Millisecond for CorePac0

8.17.3 EMAC Electrical Data/Timing (SGMII)

The Hardware Design Guide for KeyStone Devices ( SPRABI2 ) specifies a complete EMAC and SGMII interface solution for the C6654 as well as a list of compatible EMAC and SGMII devices. TI has performed the simulation and system characterization to ensure all EMAC and SGMII interface timings in this solution are met; therefore, no electrical data/timing information is supplied here for this interface.

NOTE

TI supports only designs that follow the board design guidelines outlined in the application report.

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8.18 Management Data Input/Output (MDIO)

The management data input/output (MDIO) module implements the 802.3 serial management interface to interrogate and control up to 32 Ethernet PHY(s) connected to the device, using a shared two-wire bus.

Application software uses the MDIO module to configure the auto-negotiation parameters of each PHY attached to the GbE switch subsystem, retrieve the negotiation results, and configure required parameters in the GbE switch subsystem module for correct operation. The module is designed to allow almost transparent operation of the MDIO interface, with very little maintenance from the core processor. For more information, see the Gigabit Ethernet (GbE) Subsystem for KeyStone Devices User's Guide

( SPRUGV9 ).

The EMAC control module is the main interface between the device core processor, the MDIO module, and the EMAC module. The relationship between these three components is shown in

Figure 8-44 .

For more detailed information on the EMAC/MDIO, see Gigabit Ethernet (GbE) Subsystem for KeyStone

Devices User's Guide ( SPRUGV9 ).

8.18.1 MDIO Peripheral Registers

The memory map of the MDIO is shown in

Table 8-71 .

HEX ADDRESS

02C0 8800

02C0 8804

02C0 8808

02C0 880C

02C0 8810

02C0 8814

02C0 8818 - 02C0 881C

02C0 8820

02C0 8824

02C0 8828

02C0 882C

02C0 8830 - 02C0 887C

02C0 8880

02C0 8884

02C0 8888

02C0 888C

02C0 8890 - 02C0 8FFF

Table 8-71. MDIO Registers

ACRONYM

VERSION

CONTROL

ALIVE

LINK

LINKINTRAW

LINKINTMASKED

-

USERINTRAW

USERINTMASKED

USERINTMASKSET

REGISTER NAME

MDIO Version Register

MDIO Control Register

MDIO PHY Alive Status Register

MDIO PHY Link Status Register

MDIO link Status Change Interrupt (unmasked) Register

MDIO link Status Change Interrupt (masked) Register

Reserved

MDIO User Command Complete Interrupt (Unmasked) Register

MDIO User Command Complete Interrupt (Masked) Register

MDIO User Command Complete Interrupt Mask Set Register

USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register

-

USERACCESS0

Reserved

MDIO User Access Register 0

USERPHYSEL0

USERACCESS1

USERPHYSEL1

-

MDIO User PHY Select Register 0

MDIO User Access Register 1

MDIO User PHY Select Register 1

Reserved

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8.18.2 MDIO Timing

Table 8-72. MDIO Timing Requirements

See

Figure 8-45

2

3

4

NO.

1

5 tc(MDCLK) tw(MDCLKH) tw(MDCLKL)

Cycle time, MDCLK

Pulse duration, MDCLK high

Pulse duration, MDCLK low tsu(MDIO-

MDCLKH)

Setup time, MDIO data input valid before MDCLK high th(MDCLKH-MDIO) Hold time, MDIO data input valid after MDCLK high tt(MDCLK) Transition time, MDCLK

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MIN

400

180

180

10

0

MAX

5

UNIT

ns ns ns ns ns ns

1

MDCLK

2 3

4 5

MDIO

(Input)

Figure 8-45. MDIO Input Timing

Table 8-73. MDIO Switching Characteristics

See

Figure 8-46

NO.

6

PARAMETER

td(MDCLKL-MDIO) Delay time, MDCLK low to MDIO data output valid

MIN

1

MDCLK

6

MDIO

(Ouput)

Figure 8-46. MDIO Output Timing

MAX

100

UNIT

ns

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8.19 Timers

The timers can be used to: time events, count events, generate pulses, interrupt the CPU and send synchronization events to the EDMA3 channel controller.

8.19.1 Timers Device-Specific Information

The C6654 device has seven 64-bit timers in total. Timer0 is dedicated to the CorePac as a watchdog timer and can also be used as a general-purpose timer. Each of the other six timers can also be configured as a general-purpose timer only, programmed as a 64-bit timer or as two separate 32-bit timers.

When operating in 64-bit mode, the timer counts either VBUS clock cycles or input (TINPLx) pulses (rising edge) and generates an output pulse/waveform (TOUTLx) plus an internal event (TINTLx) on a softwareprogrammable period.

When operating in 32-bit mode, the timer is split into two independent 32-bit timers. Each timer is made up of two 32-bit counters: a high counter and a low counter. The timer pins, TINPLx and TOUTLx are connected to the low counter. The timer pins, TINPHx and TOUTHx are connected to the high counter.

When operating in watchdog mode, the timer counts down to 0 and generates an event. It is a requirement that software writes to the timer before the count expires, after which the count begins again.

If the count ever reaches 0, the timer event output is asserted. Reset initiated by a watchdog timer can be set by programming

Section 8.5.2.6

and the type of reset initiated can set by programming

Section 8.5.2.8

. For more information, see the 64-bit Timer (Timer 64) for KeyStone Devices User's Guide

( SPRUGV5 ).

8.19.2 Timers Electrical Data/Timing

The tables and figure below describe the timing requirements and switching characteristics of Timer0 through Timer7 peripherals.

Table 8-74. Timer Input Timing Requirements

(1)

(see

Figure 8-47 )

NO.

1

2 t w(TINPH) t w(TINPL)

Pulse duration, high

Pulse duration, low

(1) C = 1 / CORECLK(N|P) frequency in ns.

PARAMETER MIN

12C

12C

MAX UNIT

ns ns

Table 8-75. Timer Output Switching Characteristics

(1)

(see

Figure 8-47 )

NO.

3

4 t w(TOUTH) t w(TOUTL)

Pulse duration, high

Pulse duration, low

(1) C = 1 / CORECLK(N|P) frequency in ns.

PARAMETER MIN

12C - 3

12C - 3

MAX UNIT

ns ns

1 2

TIMIx

3 4

TIMOx

Figure 8-47. Timer Timing

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8.20 General-Purpose Input/Output (GPIO)

8.20.1 GPIO Device-Specific Information

On the C6654, the GPIO peripheral pins GP[15:0] are also used to latch configuration settings. For more detailed information on device/peripheral configuration and the C6654 device pin muxing, see

Section 4 .

For more information on GPIO, see the General Purpose Input/Output (GPIO) for KeyStone Devices

User's Guide ( SPRUGV1 ).

8.20.2 GPIO Electrical Data/Timing

Table 8-76. GPIO Input Timing Requirements

NO.

1

2 t w(GPOH) t w(GPOL)

Pulse duration, GPOx high

Pulse duration, GPOx low

(1) C = 1/SYSCLK1 frequency in ns.

MIN

12C

(1)

12C

MAX UNIT

ns ns

Table 8-77. GPIO Output Switching Characteristics

NO.

3

4 t w(GPOH) t w(GPOL)

PARAMETER

Pulse duration, GPOx high

Pulse duration, GPOx low

(1) C = 1/SYSCLK1 frequency in ns.

MIN

36C

(1)

- 8

36C - 8

1 2

GPIx

3

4

GPOx

Figure 8-48. GPIO Timing

MAX UNIT

ns ns

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8.21 Semaphore2

The device contains an enhanced semaphore module for the management of shared resources of the

DSP C66x CorePac. The semaphore enforces atomic accesses to shared chip-level resources so that the read-modify-write sequence is not broken. The semaphore module has a unique interrupt to the CorePac to identify when the core has acquired the resource.

Semaphore resources within the module are not tied to specific hardware resources. It is a software requirement to allocate semaphore resources to the hardware resource(s) to be arbitrated.

The semaphore module supports 8 master and contains 32 semaphores to be used within the system.

The Semaphore module is accessible only by masters with privilege ID (privID) 0, which means only

CorePac 0 or the EDMA transactions initiated by CorePac 0 can access the Semaphore module.

There are two methods of accessing a semaphore resource:

Direct Access: A core directly accesses a semaphore resource. If free, the semaphore will be granted. If not, the semaphore is not granted.

Indirect Access: A core indirectly accesses a semaphore resource by writing it. Once it is free, an interrupt notifies the CPU that it is available.

8.22 Multichannel Buffered Serial Port (McBSP)

The McBSP provides these functions:

• Full-duplex communication

• Double-buffered data registers, which allow a continuous data stream

• Independent framing and clocking for receive and transmit

• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected analog-to-digital (A/D) and digital-to-analog (D/A) devices

• External shift clock or an internal, programmable frequency shift clock for data transfer

• Transmit & receive FIFO buffers allow the McBSP to operate at a higher sample rate by making it more tolerant to DMA latency

If an internal clock source is used, the CLKGDV field of the Sample Rate Generator Register (SRGR) must always be set to a value of 1 or greater.

For more information, see the Multichannel Buffered Serial Port (McBSP) for KeyStone Devices User's

Guide.

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8.22.1 McBSP Peripheral Register

Table 8-78. McBSP/FIFO Registers

MCBSP0

BYTE ADDRESS

0x021B 4000

0x021B 4004

0x021B 4008

0x021B 400C

0x021B 4010

0x021B 4014

0x021B 4018

0x021B 401C

0x021B 4020

0x021B 4024

0x021B 4028

0x021B 402C

0x021B 4030

0x021B 4034

0x021B 4038

0x021B 403C

0x021B 6000

0x021B 6010

0x021B 6014

0x021B 6018

0x021B 601C

0x2200 0000

0x2200 0000

McBSP1

BYTE ADDRESS

0x021B 8000

0x021B 8004

0x021B 8008

0x021B 800C

0x021B 8010

0x021B 8014

0x021B 8018

0x021B 801C

0x021B 8020

0x021B 8024

0x021B 8028

0x021B 802C

0x021B 8030

0x021B 8034

0x021B 8038

0x021B 803C

0x021B A000

0x021B A010

0x021B A014

0x021B A018

0x021B A01C

0x2240 0000

0x2240 0000

ACRONYM

DRR

DXR

SPCR

RCR

XCR

SRGR

MCR

RCERE0

XCERE0

PCR

RCERE1

REGISTER DESCRIPTION

McBSP Registers

McBSP Data Receive Register (read-only)

McBSP Data Transmit Register

McBSP Serial Port Control Register

McBSP Receive Control Register

McBSP Transmit Control Register

McBSP Sample Rate Generator register

McBSP Multichannel Control Register

McBSP Enhanced Receive Channel Enable Register 0 Partition A/B

McBSP Enhanced Transmit Channel Enable Register 0 Partition A/B

McBSP Pin Control Register

McBSP Enhanced Receive Channel Enable Register 1 Partition C/D

XCERE1

RCERE2

XCERE2

RCERE3

XCERE3

McBSP Enhanced Transmit Channel Enable Register 1 Partition C/D

McBSP Enhanced Receive Channel Enable Register 2 Partition E/F

McBSP Enhanced Transmit Channel Enable Register 2 Partition E/F

McBSP Enhanced Receive Channel Enable Register 3 Partition G/H

McBSP Enhanced Transmit Channel Enable Register 3 Partition G/H

McBSP FIFO Control and Status Registers

BFIFOREV

WFIFOCTL

BFIFO Revision Identification Register

Write FIFO Control Register

WFIFOSTS

RFIFOCTL

RFIFOSTS

Write FIFO Status Register

Read FIFO Control Register

RBUF

XBUF

Read FIFO Status Register

McBSP FIFO Data Registers

McBSP FIFO Receive Buffer

McBSP FIFO Transmit Buffer

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8.22.2 McBSP Electrical Data/Timing

The following tables assume testing over recommended operating conditions.

8.22.2.1 McBSP Timing

Table 8-79. McBSP Timing Requirements

(1)

(see

Figure 8-49 )

NO.

2 t c(CKRX)

3 t w(CKRX)

5

6

7

8

10

11 t t t t t t su(FRH-CKRL) h(CKRL-FRH) su(DRV-CKRL) h(CKRL-DRV) su(FXH-CKXL) h(CKXL-FXH)

Cycle time, CLKR/X

Pulse duration, CLKR/X high or CLKR/X low

Setup time, external FSR high before CLKR low

Hold time, external FSR high after CLKR low

Setup time, DR valid before CLKR low

Hold time, DR valid after CLKR low

Setup time, external FSX high before CLKX low

Hold time, external FSX high after CLKX low

CLKR/X ext

CLKR/X ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

CLKR int

CLKR ext

MIN

2P or 20

(2) (3)

P-1

(4)

14

4

6

3

14

4

3

3

14

4

6

3

MAX UNIT

ns ns ns ns ns ns ns ns

(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.

(2) P = SYSCLK7 period in ns. For example, when the SYSCLK7 clock domain is running at 166MHz, use 6ns.

(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements

(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.

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Table 8-80. McBSP Switching Characteristics

(1) (2)

(see

Figure 8-49 )

NO.

1 t d(CKSH-

CKRXH)

2 t c(CKRX)

3 t w(CKRX)

4 t d(CKRH-FRV)

4

9

12

13

14 t t t t d(CKXH-FXV) dis(CKXH-

DXHZ) d(CKXH-DXV) d(FXH-DXV)

PARAMETER

Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from

CLKS input.

Cycle time, CLKR/X

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X int

CLKR/X int

Delay time, CLKR high to internal FSR valid

Delay time, CLKX high to internal FSX valid

Disable time, DX Hi-Z following last data bit from CLKX high

CLKR int

CLKR int

CLKX int

CLKX ext

CLKX int

Delay time, CLKX high to DX valid

Delay time, FSX high to DX valid applies ONLY when in data delay 0 (XDATDLY = 00b) mode

CLKX ext

CLKX int

CLKX ext

FSX int

FSX ext

MIN

1

2P or 20

(3) (4)

C - 2

(5)

-4

1

-4

1

-4

1

-4 + D1

(6)

1 + D1

(6)

-4 + D1

(7)

-2 + D1

(7)

MAX UNIT

14.5

ns

C + 2

(5) ns ns

5.5

ns

(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(2) Minimum delay times also represent minimum output hold times.

(3) P = SYSCLK7 period in ns. For example, when the SYSCLK7 clock domain is running at 166 MHz, use 6 ns.

(4) Use whichever value is greater.

(5) C = H or L

S = sample rate generator input clock = P if CLKSM = 1 (P = SYSCLK7 period)

S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

If CLKGDV is even:

(1) H = CLKX high pulse width = (CLKGDV/2 + 1) * S

(2) L = CLKX low pulse width = (CLKGDV/2) * S

If CLKGDV is odd:

(1) H = (CLKGDV + 1)/2 * S

(2) L = (CLKGDV + 1)/2 * S

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit.

(6) Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P

(7) Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0 if DXENA = 1, then D1 = 4P, D2 = 8P

14.5

ns

5.5

ns

14.5

7.5

14.5

5.5 + D2

(6)

14.5 + D2

(6)

5 + D2

(7)

14.5 + D2

(7) ns ns ns

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CLKS

1

3

2

3

CLKR

4

4

FSR (int)

5

6

FSR (ext)

7

DR

Bit(n-1)

8

(n-2) (n-3)

3

2

3

CLKX

9

FSX (int)

11

10

FSX (ext)

FSX (XDATDLY=00b)

DX Bit 0

12

14

13

(B)

Bit(n-1)

Figure 8-49. McBSP Timing

13

(n-2) (n-3)

Table 8-81. McBSP Timing Requirements for FSR When GSYNC = 1

(see

Figure 8-50 )

NO.

1 t su(FRH-CKSH)

2 t h(CKSH-FRH)

Setup time, FSR high before CLKS high

Hold time, FSR high after CLKS high

MIN

4

4

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MAX UNIT

ns ns

CLKS

1

2

FSR external

CLKR/X

(no need to resync)

CLKR/X

(needs resync)

Figure 8-50. FSR Timing When GSYNC = 1

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8.23 Universal Parallel Port (uPP)

The universal parallel port (uPP) peripheral is a multichannel, high-speed parallel interface with dedicated data lines and minimal control signals. It is designed to interface cleanly with high-speed analog-to-digital converters (ADCs) or digital-to-analog converters (DACs) with up to 16-bits of data width (per channel). It may also be interconnected with field-programmable gate arrays (FPGAs) or other uPP devices to achieve high-speed digital data transfer. It can operate in receive mode, transmit mode, or duplex mode, in which its individual channels operate in opposite directions.

The uPP peripheral includes an internal DMA controller to maximize throughput and minimize CPU overhead during high-speed data transmission. All uPP transactions use the internal DMA to provide data to or retrieve data from the I/O channels. The DMA controller includes two DMA channels, which typically service separate I/O channels. The uPP peripheral also supports data interleave mode, in which all DMA resources service a single I/O channel. In this mode, only one I/O channel may be used.

The features of the uPP include:

• Programmable data width per channel (from 8 bits to 16 bits inclusive)

• Programmable data justification

– Right-justify with 0 extend

– Right-justify with sign extend

– Left-justify with 0 fill

• Supports multiplexing of interleaved data during SDR transmit

• Optional frame START signal with programmable polarity

• Optional data ENABLE signal with programmable polarity

• Optional synchronization WAIT signal with programmable polarity

• Single Data Rate (SDR) or Double Data Rate (DDR, interleaved) interface

– Supports multiplexing of interleaved data during SDR transmit

– Supports demultiplexing and multiplexing of interleaved data during DDR transfers

For more information, see the Universal Parallel Port (uPP) for KeyStone Devices User's Guide.

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8.23.1 uPP Register Descriptions

BYTE ADDRESS ACRONYM

0x0258 0000

0x0258 0004

UPPID

UPPCR

0x0258 0008

0x0258 0010

UPDLB

UPCTL

0x0258 0014

0x0258 0018

0x0258 001C

0x0258 0020

0x0258 0024

UPICR

UPIVR

UPTCR

UPISR

UPIER

0x0258 0028

0x0258 002C

0x0258 0030

0x0258 0040

0x0258 0044

0x0258 0048

0x0258 0050

0x0258 0054

0x0258 0058

0x0258 0060

0x0258 0064

0x0258 0068

0x0258 0070

0x0258 0074

0x0258 0078

UPIES

UPIEC

UPEOI

UPID0

UPID1

UPID2

UPIS0

UPIS1

UPIS2

UPQD0

UPQD1

UPQD2

UPQS0

UPQS1

UPQS2

Table 8-82. Universal Parallel Port (uPP) Registers

REGISTER DESCRIPTION

uPP Peripheral Identification Register uPP Peripheral Control Register uPP Digital Loopback Register uPP Channel Control Register uPP Interface Configuration Register uPP Interface Idle Value Register uPP Threshold Configuration Register uPP Interrupt Raw Status Register uPP Interrupt Enabled Status Register uPP Interrupt Enable Set Register uPP Interrupt Enable Clear Register uPP End-of-Interrupt Register uPP DMA Channel I Descriptor 0 Register uPP DMA Channel I Descriptor 1 Register uPP DMA Channel I Descriptor 2 Register uPP DMA Channel I Status 0 Register uPP DMA Channel I Status 1 Register uPP DMA Channel I Status 2 Register uPP DMA Channel Q Descriptor 0 Register uPP DMA Channel Q Descriptor 1 Register uPP DMA Channel Q Descriptor 2 Register uPP DMA Channel Q Status 0 Register uPP DMA Channel Q Status 1 Register uPP DMA Channel Q Status 2 Register

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Table 8-83. uPP Timing Requirements

(see

Figure 8-51 , Figure 8-52 ,

Figure 8-53 , Figure 8-54 )

NO.

1

2

3 t t t c(INCLK) w(INCLKH) w(INCLKL)

4 t su(STV-INCLKH)

5 t h(INCLKH-STV)

6 t su(ENV-INCLKH)

7 t h(INCLKH-ENV)

8 t su(DV-INCLKH)

9 t h(INCLKH-DV)

10 t su(DV-INCLKL)

11 t h(INCLKL-DV)

19 t su(WTV-OUTCLKL)

20 t h(INCLKL-WTV)

21 t c(2xTXCLK)

Cycle time, CHn_CLK

Pulse width, CHn_CLK high

Pulse width, CHn_CLK low

Setup time, CHn_START valid before CHn_CLK high

Hold time, CHn_START valid after CHn_CLK high

Setup time, CHn_ENABLE valid before CHn_CLK high

Hold time, CHn_ENABLE valid after CHn_CLK high

Setup time, CHn_DATA/XDATA valid before CHn_CLK high

Hold time, CHn_DATA/XDATA valid after CHn_CLK high

Setup time, CHn_DATA/XDATA valid before CHn_CLK low

Hold time, CHn_DATA/XDATA valid after CHn_CLK low

Setup time, CHn_WAIT valid before CHn_CLK high

Hold time, CHn_WAIT valid after CHn_CLK high

Cycle time, 2xTXCLK input clock

(1)

SDR mode

DDR mode

SDR mode

DDR mode

SDR mode

DDR mode

MIN

13.33

26.66

5

10

5

10

4

0.8

4

0.8

4

0.8

4

0.8

4

0.8

6.66

MAX UNIT

ns ns ns ns ns ns ns ns ns ns ns ns ns ns

(1) 2xTXCLK is an alternate transmit clock source that must be at least 2 times the required uPP transmit clock rate (as it is divided down by 2 inside the uPP). 2xTXCLK has no specified skew relationship to the CHn_CLOCK and therefore is not shown in the timing diagram.

Table 8-84. uPP Switching Characteristics

(see

Figure 8-53 , Figure 8-54 )

NO.

PARAMETER MAX UNIT

12 t c(OUTCLK)

13 t w(OUTCLKH)

14 t w(OUTCLKL)

Cycle time, CHn_CLK

Pulse width, CHn_CLK high

Pulse width, CHn_CLK low

15 t d(OUTCLKH-STV)

16 t d(OUTCLKH-ENV)

17 t d(OUTCLKH-DV)

18 t d(OUTCLKL-DV)

Delay time, CHn_START valid after CHn_CLK high

Delay time, CHn_ENABLE valid after CHn_CLK high

Delay time, CHn_DATA/XDATA valid after CHn_CLK high

Delay time, CHn_DATA/XDATA valid after CHn_CLK low

SDR mode

DDR mode

SDR mode

DDR mode

SDR mode

DDR mode

MIN

13.33

26.66

5

10

5

10

1

1

1

1 ns ns ns

11 ns

11 ns

11 ns

11 ns

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1

CHx_CLK

CHx_START

4 5

2 3

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6 7

CHx_ENABLE

CHx_WAIT

CHx_DATA[n:0]

CHx_XDATA[n:0]

8

Data1 Data2 Data3 Data4 Data5 Data6

9

Figure 8-51. uPP Single Data Rate (SDR) Receive Timing

Data7 Data8 Data9

1

2

3

CHx_CLK

CHx_START

4 5

6 7

CHx_ENABLE

CHx_WAIT

CHx_DATA[n:0]

CHx_XDATA[n:0]

I1 Q1 I2 Q2 I3 Q3

8

I4 Q4 I5 Q5 I6 Q6

10

I7 Q7 I8 Q8

11

I9 Q9

9

Figure 8-52. uPP Double Data Rate (DDR) Receive Timing

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12 13

TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

14

CHx_CLK

CHx_START

CHx_ENABLE

CHx_WAIT

CHx_DATA[n:0]

CHx_XDATA[n:0]

15

16

19 20

17

Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9

Figure 8-53. uPP Single Data Rate (SDR) Transmit Timing

12 13 14

CHx_CLK

CHx_START

CHx_ENABLE

CHx_WAIT

CHx_DATA[n:0]

CHx_XDATA[n:0]

15

16

19 20

17

I1 Q1 I2 Q2 I3 Q3

18

I4 Q4 I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9

Figure 8-54. uPP Double Data Rate (DDR) Transmit Timing

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8.24 Emulation Features and Capability

8.24.1 Advanced Event Triggering (AET)

The C6654 device supports advanced event triggering (AET). This capability can be used to debug complex problems as well as understand performance characteristics of user applications. AET provides the following capabilities:

Hardware Program Breakpoints: specify addresses or address ranges that can generate events such as halting the processor or triggering the trace capture.

Data Watchpoints: specify data variable addresses, address ranges, or data values that can generate events such as halting the processor or triggering the trace capture.

Counters: count the occurrence of an event or cycles for performance monitoring.

State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences.

For more information on AET, see the following documents in

Section 3.11

:

Using Advanced Event Triggering to Find and Fix Intermittent Real-Time Bugs ( SPRA753 )

Using Advanced Event Triggering to Debug Real-Time Problems in High Speed Embedded

Microprocessor Systems ( SPRA387 )

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TMS320C6654

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8.24.2 Trace

The C6654 device supports trace. Trace is a debug technology that provides a detailed, historical account of application code execution, timing, and data accesses. Trace collects, compresses, and exports debug information for analysis. Trace works in real-time and does not impact the execution of the system.

For more information on board design guidelines for trace advanced emulation, see the 60-Pin Emulation

Header Technical Reference.

8.24.2.1 Trace Electrical Data/Timing

Table 8-85. DSP Trace Switching Characteristics

(1)

(see

Figure 8-55 )

2

3

1

2

NO.

1 t tw(DPnH) t w

(DPnH)90% t w

(DPnL) t w

(DPnL)10% sko

(DPn)

PARAMETER

Pulse duration, DPn/EMUn high detected at 50% Voh

Pulse duration, DPn/EMUn high detected at 90% Voh

Pulse duration, DPn/EMUnlow detected at 50% Voh

Pulse duration, DPn/EMUnlow detected at 10% Voh

Output skew time, time delay difference between DPn/EMUnpins configured as trace t skp

(DPn)

Pulse skew, magnitude of difference between high-to-low (tphl) and low-to-high

(tplh) propagation delays.

t

σλδπ_o

(DPn) Output slew rate DPn/EMUn

(1) Over recommended operating conditions.

Table 8-86. STM Trace Switching Characteristics

(1)

(see

Figure 8-55 )

2

2

3

NO.

1

1 t t t t t w w w w

(DPnH)

(DPnH)90%

(DPnL)

(DPnL)10% sko

(DPn)

PARAMETER

Pulse duration, DPn/EMUn high detected at 50% Voh with 60/40 duty cycle

Pulse duration, DPn/EMUn high detected at 90% Voh

Pulse duration, DPn/EMUn low detected at 50% Voh with 60/40 duty cycle

Pulse duration, DPn/EMUn low detected at 10% Voh

Output skew time, time delay difference between DPn/EMUn pins configured as trace t skp

(DPn) t

σλδπ_o

(DPn)

Pulse skew, magnitude of difference between high-to-low (tphl) and low-to-high

(tplh) propagation delays.

Output slew rate DPn/EMUn

(1) Over recommended operating conditions.

3.3

MIN

4

3.5

4

3.5

-1

MIN

2.4

1.5

2.4

1.5

-1

3.3

MAX UNIT

ns ns ns ns

1 ns

600 ps

V/ns

MAX UNIT

ns ns ns ns

1 ns

1 ns

V/ns

A

T

PLH

T

PHL

1 2

B

3

C

A.

EMUx represents the EMU output pin configured as the trace clock output.

EMUy and EMUz represent all of the trace output data pins.

Figure 8-55. Trace Timing

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8.24.3 IEEE 1149.1 JTAG

The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan supported allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g., no EMU[1:0]) required for boundary scan. Most interfaces on the device follow the Boundary Scan Test Specification

(IEEE1149.1), while all of the SerDes (SGMII) support the AC-coupled net test defined in AC-Coupled Net

Test Specification (IEEE1149.6).

It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain fashion, in accordance with the specification. The JTAG interface uses 1.8-V LVCMOS buffers, compliant with the Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuit

Specification (EAI/JESD8-5).

8.24.3.1 IEEE 1149.1 JTAG Compatibility Statement

For maximum reliability, the C6654 DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive

TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the

DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan operations.

8.24.3.2 JTAG Electrical Data/Timing

Table 8-87. JTAG Test Port Timing Requirements

(see

Figure 8-56 )

4

4

3

3

NO.

1 t c(TCK)

1a tw(TCKH)

1b tw(TCKL) tsu(TDI-TCK) tsu(TMS-TCK) th(TCK-TDI) th(TCK-TMS)

Cycle time, TCK

Pulse duration, TCK high (40% of tc)

Pulse duration, TCK low(40% of tc) input setup time, TDI valid to TCK high input setup time, TMS valid to TCK high input hold time, TDI valid from TCK high input hold time, TMS valid from TCK high

Table 8-88. JTAG Test Port Switching Characteristics

(1)

(see

Figure 8-56 )

NO.

2 t d(TCKL-TDOV)

(1) Over recommended operating conditions.

PARAMETER

Delay time, TCK low to TDO valid

MIN

34

13.6

13.6

3.4

3.4

17

17

MIN

MAX UNIT

ns ns ns ns ns ns ns

MAX UNIT

13.6

ns

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TMS320C6654

SPRS841B – MARCH 2012 – REVISED APRIL 2015

1

1a 1b

TCK

2

TDO

4

3

TDI / TMS

Figure 8-56. JTAG Test-Port Timing

8.25 Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

PARTS

TMS320C6654

PRODUCT FOLDER

Click here

Table 8-89. Related Links

SAMPLE & BUY

Click here

TECHNICAL

DOCUMENTS

Click here

TOOLS &

SOFTWARE

Click here

SUPPORT &

COMMUNITY

Click here

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9 Mechanical Data

9.1

Thermal Data

Table 9-1

shows the thermal resistance characteristics for the PBGA - CZH/GZH mechanical package.

Table 9-1. Thermal Resistance Characteristics (PBGA Package) [CZH/GZH]

NO.

1 R

θ

JC

2 R θ

JB

Junction-to-case

Junction-to-board

°C/W

0.284

4.200

9.2

Packaging Information

The following packaging information reflects the most current released data available for the designated device(s). This data is subject to change without notice and without revision of this document.

230

Mechanical Data

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PACKAGE OPTION ADDENDUM

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11-Feb-2015

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

TMS320C6654CZH8 ACTIVE FCBGA CZH 625 60 Green (RoHS

& no Sb/Br)

SNAGCU Level-3-245C-168 HR 0 to 85 TMS320C6654CZH

@2012 TI

850MHZ

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

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