Microdrive 3K4 Specification v.4

Hitachi Global Storage Technologies storage products

Hard disk drive specifications

Hitachi Microdrive™

with CF+ Type II interface

Models

4GB 3K4-4 HMS360404D5CF00

2GB 3K4-2 HMS360402D5CF00

Revision 0.4

17 Oct. 2003

Hard disk drive specfication for Hitachi Microdrive TM

Subject to change

3K4

1

Hitachi Global Storage Technologies storage products

S14R-8897-04 Publication #E001

Hard disk drive specfication for Hitachi Microdrive TM

Subject to change

3K4

2

Hitachi Global Storage Technologies storage products

Hard disk drive specfication for Hitachi Microdrive TM

Subject to change

3K4

3

Hitachi Global Storage Technologies storage products

Hard disk drive specifications

Hitachi Microdrive™

with CF+ Type II interface

Models

4GB 3K4-4 HMS360404D5CF00

2GB 3K4-2 HMS360402D5CF00

Revision 0.4

17 Oct, 2003

S14R-8897-04 Publication #E001

Hard disk drive specfication for Hitachi Microdrive TM

Subject to change

3K4

4

Hitachi Global Storage Technologies storage products

1st Revision (Rev 0.1) Sxxx-xxxx-xx (Jul. 14, 2003) Preliminary

2nd Revision (Rev 0.2) Sxxx-xxxx-xx (Aug. 20, 2003) Preliminary

- Power / zone format

3rd Revision (Rev 0.3) Sxxx-xxxx-xx (Oct. 10, 2003) Preliminary

- Peak power / power rising time

4th Revision (Rev 0.4) S14R-8897-04 (Oct. 17, 2003)

The following paragraph does not apply to the United Kingdom or any country where such provisions

are inconsistent with local law: HITACHI GLOBAL STORAGE TECHINOLOGIES PROVIDES THIS

PUBLICATION "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, IN-

CLUDING,BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FIT-

NESS FOR A PARTICULAR PURPOSE. Some states do not allow disclaimer or express or implied warranties in certain transactions, therefore, this statement may not apply to you.

This publication could include technical inaccuracies or typographical errors. Changes are periodically made to theinformation herein; these changes will be incorporated in new editions of the publication. HGST may make improvements and/or changes in the product(s) and/or the program(s) described in this publication at any time.

It is possible that this publication may contain reference to, or information about, HGST products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that HGST intends to announce such HGST products, programming, or services in your country.

Technical information about this product is available by contacting a local HGST representative or

http://www.hgst.com

HGST may have patents or pending patent applications covering subject matter in this document. The furnishing of this document does not give you any license to these patents.

(C) Copyright Hitachi Global Storage Technologies

Note to U.S. Government Users — Documentation related to restricted rights — Use, duplication or disclosure is subject to restrictions set forth in GSA ADP Schedule Contract with HGST.

Hard disk drive specfication for Hitachi Microdrive TM

Subject to change

3K4

5

Hitachi Global Storage Technologies storage products

Table of contents

List of figures

1.0 General

.............................................

10

.......

...............................................

12

.......

1.1 References

1.2 Abbreviations

.............................................

12

.......

...........................................

12

.......

1.3 Drive handling precautions

2.0 General features

..................................

13

.......

........................................

14

.......

Part 1. Functional specification

................................

16

.......

3.0 Fixed disk subsystem description

..........................

18

.......

3.1 Control electronics

3.2 Head disk assembly

........................................

18

.......

.......................................

18

.......

4.0 Fixed disk characteristics

4.1 Formatted capacity

.................................

20

.......

.......................................

20

.......

4.2 Data sheet .............................................

20

.......

4.3 Performance characteristics .................................

21

.......

4.3.1 Command overhead

4.3.2 Mechanical positioning

..................................

21

.......

................................

21 .......

4.3.3 Operating modes

5.0 Data integrity

....................................

23 .......

...........................................

24 .......

5.1 Data loss at power off

5.2 Write cache

......................................

24 .......

.............................................

24 .......

5.3 Equipment status

5.4 WRITE safety

.........................................

24 .......

...........................................

24 .......

5.5 Data buffer test

5.6 Error recovery

..........................................

24 .......

...........................................

25 .......

5.7 Automatic reallocation

.....................................

25 .......

5.7.1 Nonrecovered write errors

..............................

25 .......

5.7.2 Nonrecovered read errors

5.7.3 Recovered read errors

.............................

25 .......

................................

25 .......

6.0 File organization

7.0 Specification

........................................

26 .......

...........................................

28

.......

7.1 Environment

............................................

28

.......

7.1.1 Temperature and humidity

7.1.1 Radiation noise

.............................

28

.......

.....................................

29

.......

7.1.2 Conductive noise

7.1.3 Magnetic fields

....................................

29

.......

......................................

29

.......

7.2 DC power requirements

7.3 Reliability

....................................

30

.......

...............................................

30

.......

7.3.1 Load/unload cycles

7.3.2 Warranty

...................................

30

.......

..........................................

30

.......

7.3.3 Life

..............................................

30

.......

7.3.4 Preventive maintenance

...............................

30

.......

7.4 Error rates ..............................................

31

.......

7.4.1 Recoverable errors ...................................

31

.......

7.4.2 Nonrecoverable errors

7.5 Mechanical specifications

................................

31

.......

...................................

32

.......

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7.5.1 Physical dimensions and weight

.........................

32 .......

7.5.2 Mechanical dimensions

7.5.3 Connector

...............................

32 .......

.........................................

33 .......

7.5.4 Mounting orientation

..................................

33 .......

7.5.5 Load/Unload mechanism

..............................

33 .......

7.6 Vibration and shock

.......................................

33 .......

7.6.1 Operating vibration

...................................

33 .......

7.6.2 Nonoperating vibration

7.6.3 Operating shock

................................

34 .......

.....................................

34 .......

7.6.4 Nonoperating shock

7.7 Acoustics

..................................

34 .......

...............................................

34

.......

7.7.1 Sound power level

7.7.2 Discrete tone penalty

...................................

34

.......

.................................

35

.......

7.8 Identification labels

........................................

36

.......

7.9 Electromagnetic compatibility

................................

36

.......

7.9.1 CE Mark

...........................................

36

.......

7.9.2 C-Tick Mark

........................................

36

.......

7.10 Safety

................................................

36

.......

7.10.1 Underwriters Lab (UL) approval

.........................

36

.......

7.10.2 Canadian Standards Authority (CSA) approval

7.10.3 IEC compliance

..............

36

.......

....................................

37

.......

7.10.4 German Safety Mark

7.10.5 Flammability

.................................

37

.......

.......................................

37

.......

7.10.6 Safe handling

7.10.7 Environment

......................................

37

.......

.......................................

37

.......

7.10.8 Secondary circuit protection

7.11 Packaging

...........................

37

.......

.............................................

37

.......

8.0 Electrical interface specifications

8.1 Cabling

...........................

40

.......

................................................

40

.......

8.2 Interface connector

8.3 Signal definition

.......................................

40 .......

.........................................

40 .......

8.4 Signal description

........................................

40 .......

8.5 Interface logic signal levels

.................................

41 .......

8.6 Attribute Memory Read timing

8.7 Common Memory Read timing

...............................

42 .......

...............................

43 .......

8.8 Attribute and Common Memory Read timing

8.9 I/O Input (Read) timing

.....................

44 .......

....................................

45 .......

8.10 I/O Input (Write) timing

....................................

46 .......

8.11 True IDE Mode I/O Input (Read) Timing

.......................

47 .......

8.12 True IDE Mode Multiword DMA Data Transfer Timing

8.13 True IDE Mode Ultra DMA Data Transfer Timing

.............

48 .......

.................

49 .......

8.14 Power on/off timing

......................................

50 .......

Part 2. Interface specification

.................................

52 .......

9 General

.................................................

53 .......

9.1 Introduction

.............................................

53

.......

10 Deviations from Standard

11 System interface

.................................

54

.......

.........................................

55

.......

11.1 PCMCIA memory spaces and configuration registers

11.2 Card configuration registers

.............

55

.......

................................

57

.......

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11.2.1 Configuration Option Register (Offset 00h)

.................

57 .......

11.2.2 Card Configuration Status Register (Offset 02h)

11.2.3 Pin Replacement Register (Offset 04h)

.............

58 .......

....................

59 .......

11.2.4 Socket and Copy Register (Offset 06h)

....................

59 .......

11.3 CF-ATA Drive Register Set Definition and Protocol

...............

60 .......

11.3.1 Primary or Secondary I/O mapped addressing

11.3.2 Contiguous I/O mapped addressing

..............

60 .......

......................

61 .......

11.3.3 Memory mapped addressing

11.3.4 True IDE Mode addressing

...........................

62 .......

............................

63 .......

11.4 CF-ATA Registers

.......................................

64 .......

11.4.1 Alternate Status Register

..............................

64

.......

11.4.2 Command Register

..................................

64

.......

11.4.3 Cylinder High Register

11.4.4 Cylinder Low Register

...............................

64

.......

................................

64

.......

11.4.5 Data Register

......................................

64

.......

11.4.6 Device Control Register

..............................

65

.......

11.4.7 Drive Address Register

11.4.8 Device/Head Register

...............................

65

.......

................................

66

.......

11.4.9 Error Register

......................................

66

.......

11.4.10 Feature Register

...................................

67

.......

11.4.11 Sector Count Register

11.4.12 Sector Number Register

...............................

67

.......

.............................

67

.......

11.4.13 Status Register

12.1 Reset Response

....................................

68

.......

........................................

69

.......

12.1.1 Register Initialization .................................

70

.......

12.2 Diagnostic and Reset considerations ..........................

71

.......

12.3 Power-off considerations

12.3.1 Load/Unload

..................................

72

.......

.......................................

72

.......

12.3.2 Emergency unload ..................................

72

.......

12.3.3 Required power-off sequence

..........................

72 .......

12.4 Sector Addressing Mode

..................................

74 .......

12.4.1 Logical CHS Addressing Mode

..........................

74 .......

12.4.2 LBA Addressing Mode

12.5 Power Management Feature

................................

74 .......

................................

75 .......

12.5.1 Power Mode

.......................................

75 .......

12.5.2 Power Management Commands

........................

75 .......

12.5.3 STANDBY command completion timing

12.5.4 Standby timer

...................

75 .......

......................................

76 .......

12.5.5 Status

............................................

76 .......

12.5.6 Interface Capability for Power Modes

.....................

76 .......

12.5.7 Initial Power Mode at Power On

.........................

76 .......

12.6 Advanced Power Management (Adaptive Battery Life Extender 3)

Feature

...................................................

77

.......

12.6.1 Performance Idle mode ...............................

77

.......

12.6.2Active Idle mode .....................................

77

.......

12.6.3 Low Power Idle mode ................................

78

.......

12.6.4 Transition Time

12.7 Seek Overlap

.....................................

78

.......

..........................................

79

.......

12.8 Write Cache Function

12.9 Reassign Function

.....................................

80

.......

.......................................

81

.......

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12.9.1 Auto Reassign Function

13.1 Data In Commands

13.2 Data Out Commands

...............................

81 .......

12.10 Metadata Storage Function

................................

82 .......

12.10.1 Meatadata Storage Command Set

......................

82 .......

......................................

83 .......

.....................................

85 .......

13.3 Non-Data Commands

.....................................

86 .......

13.4 DMA Data Transfer Commands

.............................

87 .......

13.4.1 Access Metadata Storage - B8h

13.4.2 Check Power Mode (E5h/98h)

.........................

88 .......

..........................

91 .......

13.4.3 Execute Device Diagnostics (90h)

13.4.4 Erase Sectors (C0h)

.......................

92 .......

.................................

93

.......

13.4.5 Flush Cache (E7h)

..................................

94

.......

13.4.6 Format Track (50h: Vendor Specific)

.....................

95

.......

13.4.7Format Unit (F7h: Vendor Specific)

13.4.8Identify Device (ECh)

.......................

98

.......

.................................

99

.......

13.4.9 Idle (E3h/97h)

......................................

105

13.4.10 Idle Immediate (E1h/95h)

.............................

106

13.4.11 Initialize Device Parameters (91h)

13.4.12 Read Buffer (E4h)

......................

107

..................................

108

13.4.13 Read DMA(C8h/C9h)

13.4.14 Read Long (22h/23h)

................................

109

................................

111

13.4.15 Read Multiple (C4h)

.................................

113

13.4.16 Read Sector(s) (20h/21h) .............................

115

13.4.17 Read Verify (40h/41h)

13.4.18 Recalibrate (1Xh)

...............................

117

..................................

119

13.4.19 Request Sense (03h) ...............................

120

13.4.20 Security Erase Prepare (F3h) ..........................

122

13.4.21 Seek (7Xh) .......................................

123

13.4.22 Sense Condition (F0h : vendor specific) ..................

124

13.4.23 Set Features (EFh)

13.4.24 Set Multiple (C6h)

.................................

125

..................................

127

13.4.25 Sleep (E6h/99h)

13.4.26Standby (E2h/96h)

...................................

128

..................................

129

13.4.27 Standby Immediate (E0h/94h)

13.4.28 Translate Sector (87h)

.........................

130

..............................

131

13.4.29 Wear Level (F5h)

13.4.30 Write Buffer (E8h)

13.4.31 Write DMA (CAh/CBh)

13.4.32 Write Long (32h/33h)

..................................

132

..................................

133

...............................

134

................................

136

13.4.33 Write Multiple (C5h)

.................................

138

13.4.34 Write Multiple without Erase (CDh)

......................

140

13.4.35 Write Sector(s) (30h/31h)

.............................

141

13.4.36 Write Sector(s) without Erase (38h)

.....................

143

13.4.37 Write Verify (3Ch: Vendor Specific)

13.5 Error Posting

.....................

144

...........................................

145

13.6 Card information structure

.................................

146

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

......

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Hitachi Global Storage Technologies storage products

List of figures

Figure 1. Formatted capacity

..................................

20

.......

Figure 2. Data sheet

........................................

20

.......

Figure 3. Performance parameters

..............................

21

.......

Figure 4. Mechanical positioning performance

Figure 5. Full stroke seek time

......................

21

.......

.................................

22

.......

Figure 6. Single track seek time

Figure 7. Latency Time

................................

22

.......

.......................................

22

.......

Figure 8. Drive Ready Time

Figure 9. Operating modes

...................................

23

.......

....................................

23

.......

Figure 10. Cylinder allocation

...................................

26

.......

Figure 11. Temperature and humidity specifications

...................

28

.......

Figure 12. Radiation noise .....................................

29

.......

Figure 13. DC power requirements.

..............................

30

.......

Figure 14. Physical dimensions and weight

Figure 15. Mechanical outline of the drive

.........................

32

.......

..........................

32

.......

Figure 16. Random vibration ...................................

33

.......

Figure 17. Random vibration PSD profile breakpoints (nonoperating) ......

34

.......

Figure 18. Sound power levels

Figure 19. DC characteristics

..................................

35

.......

...................................

40 .......

Figure 20. Interface logic signal levels.

............................

41 .......

Figure 21. Attribute Memory Read timing data

.......................

42 .......

Figure 22. Attribute Memory Read timing diagram

Figure 23. Common Memory Read timing

....................

42 .......

..........................

43 .......

Figure 24. Attribute and Common Memory Read timing data

Figure 25. Attribute and Common Memory Read timing

............

44 .......

................

44 .......

Figure 26. Common Memory Read Timing data

......................

45 .......

Figure 27. Common Memory Read Timing diagram

...................

45 .......

Figure 28. I/O Write timing data

.................................

46 .......

Figure 29. I/O Write timing diagram

...............................

46 .......

Figure 30. True IDE Mode IO Input (Read) timing data

.................

47 .......

Figure 31. True IDE Mode IO Input (Read) timing diagram

..............

47 .......

Figure 32. Multiword DMA data transfer timing data

Figure 33. Ultra DMA data transfer timing data

...................

48 .......

......................

49

.......

Figure 34. Power On/Off timing data

..............................

50

.......

Figure 35. Power On/Off timing diagram

...........................

51

.......

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1.0 General

This document describes the characteristics of 1.0-type 3600-RPM hard disk drive with a CF+ Type II interface and with capacities of 4 GB and 2 GB. This drive is the HGST Microdrive™ and is hereafter referred to as "the drive". This document defines the hardware functional and interface specifications.

The drive is available in the following models:

4GB 3K4-4 HMS360404D5CF00

2GB 3K4-2 HMS360402D5CF00

The major difference among 3K4-4 and 3K4-2 is the number of heads.

The specifications are subject to change without notice.

1.1 References

y Compact Flash Specification Version 1.4

1.2 Abbreviations

Kbit/mm

Mbps

KB

MB

GB

128 KB

Mb/sq-mm drive

Hitachi Microdrive™

MLC

TBD

1,000 bits per millimeter

1,000,000 bits per second

1,024 bytes

1,000,000 bytes

1,000,000,000 bytes

128 x 1 024 bytes

1,000,000 bits per square millimeter

3K4-4/3K4-2

3K4-4/3K4-2

Machine Level Control to be defined

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1.3

Drive handling precautions

y The drive can be easily damaged by shocks or Electric Static Discharge (ESD). Any damage incurred by the drive after removal of it from the shipping package and opening of the ESD protective bag is the user’s responsibility.

y Do not apply pressing force onto the top or bottom surface of the drive.

DO NOT PRESS!

DO NOT PRESS WHEN REMOVING THE

DRIVE

DO NOT PRESS WHEN CARRYING THE

DRIVE

DO NOT APPLY PRESSURE WHEN

ATTACHING THE DRIVE

y Do not seal the breather hole on the top cover.

DO NOT SEAL THIS HOLE!

SEALING THIS HOLE WILL RESULT IN LOSS OF DATA

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Hitachi Global Storage Technologies storage products

2.0 General features

w

Compact Flash Type-2 Card Compliance. w

4.0GB and 2.0GB formatted capacity w

512 bytes/sector w

CF + Interface w

Integrated controller w

No-ID recording format w

ME2PR 120/126 coding w

Multi zone recording w

Enhanced ECC On-The-Fly

Š 42.5 bytes Reed Solomon Code

Š 20 byte On-The-Fly correction w

128kB cache (total buffer 320kB , upper 192KB is used for firmware) w

Fast data transfer rate

- Up to 16.7MB/sec at PIO mode 4

- Up to 16.7MB/sec at Multiword DMA mode 2 (True IDE Mode only)

- Up to 33 MB/sec at Ultra DMA mode 2 (True IDE Mode only) w

Media data transfer rate 98 (outer zone / typical) - 57 (inner zone) Mbits/sec w

Average seek time 12 msec for read w

Closed -loop actuator servo (Embedded Sector Servo) w

True Track servo w

Rotary voice coil motor actuator w

Load/Unload mechanism w

Mechanical latch w

Adaptive power save control w

1.0 sec Power on to ready w

Shock

– Non-operation

– Operation

: 19600 m/s2 / 1 ms (2000 G/1 ms)

: 1960 m/s2 / 2 ms (200 G/2 ms)

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Part 1. Functional specification

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3.0 Fixed disk subsystem description

3.1 Control electronics

The control electronics works with the following function: y

Compact Flash Card Interface Protocol y Embedded Sector Servo y No-ID(TM) format y Multi zone recording y ME2PR 120/126 Code y ECC On-The-Fly y Enhanced Adaptive Battery Life Extender

3.2 Head disk assembly

The following technologies are used in the drive: y Femto slider y Smooth glass disk y GMR head y Integrated Lead Suspension (ILS) y Load/Unload mechanism y Mechanical latch y Frame bumper

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4.0 Fixed disk characteristics

4.1 Formatted capacity

The defaults of the logical drive parameters in Identify Device Data are as follows:

Description

Physical Layout

Bytes per Sector

Sectors per Track

Number of Heads

Number of Disks

RPM

Logical Layout

Number of Heads

Number of Sectors/Track

Number of Cylinders

Number of Sectors

Total Logical Data Bytes

Figure 1. Formatted capacity

3K4-4

512

160–266

2

1

3600

16

63

7936

7,999,488

4,095,737,856

4.2 Data sheet

Rotational Speed (RPM)

Data transfer rates (buffer to/from media)

Data transfer rates (host to/from buffer)

Recording Density (kbit/mm)

Track Density (ktrack/mm)

Areal Density (Mbit/sq-mm)

Data Bands

Figure 2. Data sheet

3K4-2

512

160–266

1

1

3600

16

63

3968

3,999,744

2,047,868,928

3600

57.1–97.9 Mb/s

16.7 MB/sec (PIO mode4)

16.7 MB/sec

(Multiword DMA mode2 at TRUE IDE)

33MB/sec

(Ultra DMA at TRUE IDE )

24.7 (Max)

3.54

87.6 (Max)

16

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4.3 Performance characteristics

Drive performance is determined by the following parameters: y Command overhead y Mechanical positioning

- Seek time

- Latency y Data transfer speed y Buffering operation (Look ahead/Write cache)

Note: All the above parameters contribute to drive performance. Other parameters also contribute to the performance of the actual system. This specification describes only the characteristics of the drive, not the system throughput which depends on the system and the application.

The following table gives a typical value of each parameter. Detailed descriptions follow in the next sections.

Function

Average Random Seek Time for Read

Average Random Seek Time for Write

Rotational speed

Power On To Ready

Command Overhead

Disk-buffer data transfer

Disk-host data transfer

Typical

12 ms

13 ms

3600 RPM

1.0 sec

1 ms

57.1–97.9 Mbit/s

Refer to CFA Spec.

Figure 3. Performance parameters

4.3.1 Command overhead

Command overhead time is defined as the total time from the receipt of the command by the drive to the start of motion of the actuator.

4.3.2

Mechanical positioning

4.3.2.1 Average Seek Time (Including Settling)

Command Type

Read

Write

Typical (ms)

12

13

Max (ms)

14

15

Figure 4. Mechanical positioning performance

Headings " Typical" and "Max" are given throughout the performance specification. Typical means the average of the drive population tested at nominal environmental and voltage conditions.

Max

means the maximum value measured on any one drive over the full range of the environmental and voltage conditions. (See section “Environment” Also see Section, “DC Power Requirements” .)

The seek time is period of time from the start of the motion of the actuator to the start of a reliable read or write operation. A reliable read or write implies that error correction/recovery is not employed to correct arrival problems. The Average Seek Time is a measure of the weighted average of all possible seek combinations.

max

SUM (max + 1 – n) (Tn in

+ Tn out

)

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n=1

Weighted Average = --------------------------------------------------

(max + 1) (max)

Where: max = Maximum Seek Length n = Seek Length ( 1 to max )

Tn in

= Inward measured seek time for an n track seek

Tn out

= Outward measured seek time for an n track seek

4.3.2.2 Full Stroke Seek Time

Function

Read

Write

Typical (ms)

20.0

21.0

Maximum (ms)

24.0

25.0

Figure 5. Full stroke seek time

Full stroke seek is measured as the average of 1000 full stroke seeks.

4.3.2.3 Single Track Seek Time (without Command Overhead, including settling)

Function

Read

Write

Typical (ms)

1.0

1.0

Maximum (ms)

2.0

3.0

Figure 6. Single track seek time

Single track seek time is an average. The single track seek time is calculated by adding the time of inward and outward seek time of each single track and dividing that sum by the total number of tracks.

4.3.2.4 Average latency

Rotation speed

(RPM)

3600

Figure 7. Latency Time

Time for a revolution

(ms)

16.7

Average latency

(ms)

8.3

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4.3.2.5 Drive Ready Time/Mode Transition Time

Condition

Power on to Stand by

Stand by to Idle

Typical (sec)

0.5

0.5

Maximum (sec)

0.7

0.7

Figure 8. Drive Ready Time

4.3.3 Operating modes

Operating mode

Spin-up

Seek

Write

Read

Performance Idle

Active idle

Low power idle

Standby

Description

Start up time period from spindle stop or power down

Seek operation mode

Write operation mode

Read operation mode

The drive is capable of responding immediately to media access requests. All electronic components remain powered and full frequency servo remains operational.

The device is capable of responding immediately to media access requests.Some circuitry including servo system and R/W electronics is in power saving mode. The head is parked near the mid-diameter the disk without servoing.

Spindle motor is rotating normally with actuator unloaded to the parking positions.

The drive interface is capable of accepting commands. Spindle motor is stopped. All circuitry except the host interface is in power saving mode.

The execution of commands is delayed until spindle becomes ready.

Same as Standby Sleep

Figure 9. Operating modes

4.3.3.1

Operating mode at power on

The drive powers up in Standby mode.

4.3.3.2 Adaptive Power Save Control

The transition timing from Performance Idle to Standby depends on both the access pattern of the host system and the setting of the advanced power management level. With the power-on default, the transition timing for each power mode is under control of Adaptive Battery Life Extender algorithm.

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5.0 Data integrity

5.1

Data loss at power off

y Power off during any operations except for write operation will not cause any data loss.

y Power off during a write operation causes the loss of data received by the drive but not yet written onto the disk media.

y There is a possibility that power off during a write operation might make a maximum of 1 sector of data unreadable. This state can be recovered by a rewrite operation.

5.2 Write cache

y When write cache is enabled, there is a possibility that the write command completes before the actual disk write operation finishes. This means that there is a possibility that a power off event may occur even after a full write command finishes. This means that it is possible that even after a write command completion a power off might cause the loss of the data which the drive has received but not yet written onto the disk.

y

In order to prevent data loss, confirm the completion of the actual write operation prior to the power off by issuing the Standby Immediate or Sleep command and confirming its completion.

y The default state of the write cache at power-on is "OFF."

5.3 Equipment status

Equipment status is available to the host system any time the drive is not ready to read, write, or seek. This status normally exists at power-on time and will be maintained until the following conditions are satisfied: y Access recalibration/tuning is complete.

y Spindle speed meets requirements for reliable operation.

y Self-check of drive is complete.

Appropriate error status is made available to the host system if either of the following conditions occur after the drive has once become ready: y Spindle speed outside requirements for reliable operation.

y Occurrence of a Write Fault condition.

5.4 WRITE safety

The drive ensures that the data is written onto the disk media properly. The following conditions are monitored during a write operation. When one of those conditions exceeds the criteria, the write operation is terminated and automatic retry sequence will be invoked.

y Head off track y External shock y Low supply voltage y Spindle speed tolerance y Head open/short

5.5

Data buffer test

The data buffer is tested at Power-on-reset. The test consists of a write/read "00"x and "ff"x pattern on each buffer position.

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5.6

Error recovery

Errors occurring on the drive are handled by the error recovery procedure.

Errors that are uncorrectable after application of the error recovery procedures are reported to the host system as nonrecoverable errors.

5.7

Automatic reallocation

The sectors those show some errors may be reallocated automatically when specific conditions are met. The drive does not report automatic reallocation to the host system. The conditions for automatic reallocation are described below.

5.7.1

Nonrecovered write errors

When a write operation cannot be completed after the Error Recovery Procedure (ERP) is fully carried out, the sector(s) are reallocated to the spare location. An error is reported to the host system only when the write cache is disabled and the auto reallocation has failed.

5.7.2

Nonrecovered read errors

When a read operation has failed after defined ERP is fully carried out, a hard error is reported to the host system. This location is registered internally as a candidate for the reallocation. When a registered location is specified as a target of a write operation, a sequence of media verification is performed automatically. When the result of this verification meets the criteria, this sector is reallocated.

5.7.3

Recovered read errors

When a read operation for a sector fails once and is then recovered at the specific ERP step, this sector is reallocated automatically. A media verification sequence may be run prior to the reallocation according to the predefined conditions.

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6.0 File organization

The following figure shows the cylinder allocation for the drive.

4

5

6

7

Zone

0

1

2

3

8

9

10

11

12

13

14

15

Cylinder

0–1023

1024–1919

1920–3327

3328–4479

4480–5503

5504–6527

6528–7551

7552–8447

8448–9727

9728–11391

11392–12799

12800–13695

13696 - 14847

14848 - 16383

16384 - 17919

17920 -

Figure 10

. Cylinder allocation

Sectors per Track

266

266

256

240

240

240

224

224

213

200

192

180

160

160

160

160

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7.0 Specification

7.1 Environment

7.1.1 Temperature and humidity

Temperature

Relative humidity

Maximum wet bulb temperature

Maximum temperature gradient

Altitude

Temperature

Relative humidity

Maximum wet bulb temperature

Maximum temperature gradient

Altitude

Operating conditions

0–70°C (See Note)

8–90%, non condensing

29.4°C non condensing

5°C/Minutes

–300 to 3048 m

Nonoperating conditions

–40 to 70°C (See note)

5–95%, non condensing

40°C, non condensing

5°C/Minutes

–300 to 12,192 m

Note: Regardless of the ambient temperature, the drive can be operated at a maximum temperature of 70°C at the center of the base spindle of the drive.

Figure 11. Temperature and humidity specifications

Maximum storage period with shipping package is one year.

7.1.1.1 Corrosion test

The hard disk drive must be functional and show no signs of corrosion after being subjected to temperatures of 50°C with 90% relative humidity for one week of storage followed by a return to 25°C with 40% relative humidity in two hours.

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7.1.1 Radiation noise

The disk drive must work without degradation of the soft error rate under the following magnetic flux density limit at the enclosure surface.

Frequency

0–60

61–100

101–200

201–400

Limits (µT RMS)

500

250

100

50

Figure 12.

Radiation noise

7.1.2

Conductive noise

The disk drive shall work without degradation of the soft error rate with an AC current of up to 45 mA(p-p) in the frequency range from DC to 20 MHz, injected through any two of the mounting screw holes of the drive via a 50-Ohm resistor.

7.1.3 Magnetic fields

The disk drive must withstand the radiation and conductive noise limits shown above. The test method is devined in the document "Noise Susceptibility Method" specification (P/N 95F3944).

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7.2 DC power requirements

Connection to the drive should be made in a safety extra low voltage (SELV) circuit.

Power supply

Nominal supply

Power supply ripple

(0-20Mhz)

Tolerance

Supply current (nominal condition)

Performance idle average

Active idle average

Low power idle average

Read

Write

Seek average

Standby

Peak (maximum RMS in

0.5 ms windows)

+3.3V power supply case

+3.3 Volts

70 mV p-p max.

±5%

Population mean

225 mA

70 mA

67 mA

303 mA

305 mA

265 mA

16 mA

363 mA

+5V power supply case

+5 Volt

100 mV p-p max.

±5%

Population mean

230 mA

75 mA

72 mA

315 mA

314 mA

230 mA

18 mA

385 mA

Notes

1

2

3

3

4

4

5

6

Notes

1.

The maximum fixed disk ripple is measured at 3.3 / 5 V input of the drive.

2.

3.

4.

5.

6.

The disk drive shall not incur damage for an over voltage condition of +25% (maximum duration of

20 ms) on the 3.3 / 5 Volt nominal supply.

The idle current is specified at an inner track.

The read/write current is specified at 100%duty.

The seek average current is specified based on three operations per 100 ms.

The worst case operating current at unloading.

Figure 13. DC power requirements.

7.3

Reliability

7.3.1

Load/unload cycles

The drive will meet the specified error rates after the following Load/Unload cycles: y 300,000 cycles (Load/Unload to be controlled by the drive microcode) y 20,000 cycles (Emergency unloads)

7.3.2

Warranty

The warranty will be covered by contracts.

7.3.3 Life

To be discussed separately.

7.3.4

Preventive maintenance

None required.

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7.4

Error rates

Error rates fall into two categories: y Recoverable errors y Nonrecoverable errors

The following error rates assume that no attempts are made to read or write in areas already identified as being defective. The error rates are defined for the drive operating at the full range of environmental conditions and are shown in section “Environment”. The voltage limits are shown in section “DC Power Requirements”.

7.4.1 Recoverable errors

A recoverable error is defined as an operation that failed the first time but succeeded in recovering the error when the drive error recovery procedure was invoked. ECC On-The-Fly, which is always active, is transparent to the system and is not counted as a recoverable error.

A typical drive shall have no more than one recoverable error per 100 million bits transferred (1 in 10 when operated at nominal voltage and environmental condition. The typical disk drive error rate

8 ) represents the geometric mean of the error rates of the total disk drive population. The size of the drive population is 50 drives or more.

Each drive in the population shall have no more than one recoverable error per 10 million bits transferred (1 in 10 7 ) when operated at full range of voltage and environmental conditions and the operating vibration levels stated in, “Vibration and Shock” on page 0.

7.4.2 Nonrecoverable errors

A nonrecoverable error is defined as an operation that failed and was not recovered by the fixed disk error recovery procedure. No drive has more than one nonrecoverable error per 10 trillion bits transferred (1 in 10 13 ) when operated at the full range of voltage and environmental conditions.

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7.5 Mechanical specifications

7.5.1 Physical dimensions and weight

The following table lists the dimensions and weight of the HGST Microdrive.

Height (mm)

Width (mm)

Length (mm)

Weight (grams)

5.0 + 0.0/–0.1

42.80±0.101

36.40±0.15

16 (typical)

Figure 14. Physical dimensions and weight

7.5.2 Mechanical dimensions

Figure 15. Mechanical outline of the drive

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7.5.3 Connector

See Section, “Interface Connector”.

7.5.4

Mounting orientation

The drive will operate in all axes (360°).

Performance and error rate will stay within specification limits if the drive is operated in the other permissible orientations from which it was formatted. Thus a drive formatted in a horizontal orientation is able to run vertically and vice versa.

Vibration test and shock test are to be conducted by mounting the drive to the test table using a special fixture.

7.5.5

Load/Unload mechanism

The head load/unload mechanism is provided to protect the disk during shipping, movement, or storage.

Upon power down, a head unload mechanism secures the heads at the unload position. See Section,

“Nonoperating shock” for additional details.

7.6

Vibration and shock

All vibration and shock measurements in this section are for the drive without the mounting attachments for the systems. The input level is applied to the normal drive mounting points.

7.6.1

Operating vibration

The drive will operate without a hard error while being subjected to the following vibration levels.

7.6.1.1 Operating random vibration

The test consits of 30 minutes of random vibration using the power spectral density (PSD) levels specified in C-S 1-9711-002 (1990-03) as V5L. The vibration test level for V5L is 6.57 m/sec 2 RMS.

Frequency (Hz)

5

17

45

48

62

65

150

200

500

(m/sec 2 ) 2

1.92 x E-3

1.05 x E-1

1.05 x E-1

7.68 x E-1

7.68 x E-1

0.96 x E-1

0.96 x E-1

4.80 x E-2

4.80 x E-2

Note: Random vibration PSD profile breakpoints (Operating).

Figure 16. Random vibration

7.6.1.2 Operating swept sine vibration

y

9.8 m/sec 2 (Zero-to-peak), 5 to 500 to 5 Hz sine wave y 2.0 oct/min sweep rate

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7.6.2 Nonoperating vibration

7.6.2.1 Nonoperating random vibration

The test consists of a random vibration applied in each of three mutually perpendicular axes with a

15-minute duration per axis. The Power Spectral Density (PSD) levels for the test simulates the shipping and relocation environment which is shown below.

Frequency (Hz)

2.5

5

40

500

Power Spectral Density

(m/sec 2)2 /Hz)

0.096

2.88

1.728

1.728

Note: Overall RMS level of vibration is 29.49 m/sec

2

RMS.

Figure 17. Random vibration PSD profile breakpoints (nonoperating)

7.6.2.2 Nonoperating swept sine vibration

y

49 m/sec 2 (zero-to-peak), 10 to 500 to 10 Hz sine wave y 0.5 oct/min sweep rate

7.6.3 Operating shock

The drive meets the following criteria while operating under the conditions described as follows: y The shock test consists of ten shock inputs in each axis and direction for a total of 60 shocks.

y There must be a minimum delay of 3 seconds between shock pulses. Soft errors and automatic retries are allowed during the test.

y No data loss or permanent damage occurs during a half-sine shock pulse of 1960 m/sec 2

2-ms duration and a half-sine shock pulse of 98 m/sec 2 of 11-ms duration.

of y The input level shall be applied to the normal disk drive subsystem mounting points of the device into which it is installed, as mounted in normal system use.

7.6.4

Nonoperating shock

The disk drive must withstand with no damage a half-sine wave shock pulse of 1176 m/sec 2 duration and a half-sine wave shock pulse of 19600 m/sec 2

of 11-ms

of 1-ms duration on six sides when heads are unloaded. (When the power is not applied to the unit, the heads are automatically located on the unloaded position.)

All shocks shall be applied in each direction of the drive’s three mutually perpendicular axes, one axis at a time. Input levels shall be measured at the frame of the disk drive. The input level shall be applied to the device into which the HGST Microdrive is mounted. Through this device the operating shock is imparted to the HGST Microdrive through the normal disk drive guide rails and connector retention mountings of the device under test.

7.7 Acoustics

7.7.1

Sound power level

The criteria of A-weighted sound power level is described as follows.

Measurements are to be taken in accordance with ISO 7779. The mean of 40 drives is to be less than the typical value. Each drive is to be less than the maximum value. Drives are to meet this requirement in both board down orientations.

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A-weighted sound power

(Bels)

Idle

Operating

Typical

1.8

2.1

Maximum

2.0

2.4

Figure

18

. Sound power levels

Background power levels of the acoustic test chamber for each octave band are to be recorded.

Sound power tests are to be conducted with the drive supported by spacers so that the lower surface of the drive is located at 25±3 mm height from the chamber floor. No sound absorbing material is used.

The acoustical characteristics of the disk drive are measured under the following conditions:

Mode definition

y

Idle mode

Power on, disks spinning, track following, unit ready to receive and respond to control line command y

Operating mode

Continuous random cylinder selection and seek operation of actuator with a dwell time at each cylinder. Seek rate for the drive can be calculated as follows:

Ns = 0.4 / (Tt + T1) where

Ns = average seek rate in seeks/second

Tt = published seek time from one random track to another without including rotational latency

T1 = equivalent time, in seconds, for the drive to rotate by half a revolution

7.7.2 Discrete tone penalty

Discrete tone penalties are added to the A-weighted sound power (LW) with the following formula only when determining compliance:

LWt(spec) = LW + 0.1Pt + 0.3 < 4.0 (Bels) where

LW = A-weighted sound power level

Pt = Value of discrete tone penalty [= dLt–6.0 (dBA)] dLt = Tone-to-noise ratio taken in accordance with ISO 7779 at each octave band

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7.8 Identification labels

The labels are affixed to every drive.

The top side of the label contains y Model name y Part number y The statement "Made by HGST" y Country of origin y Notifications to the customer y The marks of agencies approval y Bar code of the serial numbers

The bottom side of the label contains y The HGST logo y The capacity y The product name (Microdrive)

Due to space limitations, no additional requirements by customer are allowed.

7.9

Electromagnetic compatibility

The drive—when installed in a suitable enclosure and exercised with a random accessing routine at maximum data rate—meets the following worldwide EMC requirements.

y United States Federal Communications Commission (FCC) Rules and Regulations (Class B),

Part 15 y UE EMC Directive Technical Requirements and Conformity Assessment Procedures:

NB 20-0001-038

HGST small LES development will provide technical support to assist users in complying with the

EMC requirements.

7.9.1 CE Mark

The product is certified for compliance with EC directive 89/336/EEC. The EC marking for the certification appears on the drive.

7.9.2

C-Tick Mark

The product complies with the following Australian EMC standard—limits and methods of measurement of radio disturbance characteristics of information technology equipment per document

AS/NZS 3548:1995 Class B,

7.10 Safety

7.10.1

Underwriters Lab (UL) approval

All models of the drive comply with UL 1950.

7.10.2

Canadian Standards Authority (CSA) approval

All models of the drive comply with CSA C22.2 950-M1995.

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7.10.3

IEC compliance

All models of the drive comply with IEC 950.

7.10.4 German Safety Mark

All models of the drive are approved by TUV on Test Requirement EN 60 950:1988/A1:1990, but the

GS mark has not been obtained.

7.10.5

Flammability

Printed circuit boards used in this product are made of material with a UL recognized flammability rating of V-1 or better. The flammability rating is marked or etched on the board. All other parts not considered electrical components except for minor mechanical parts are made of material with a UL recognized flammability rating of V-1 or better.

7.10.6

Safe handling

The products are designed for safe handling with regards to sharp edges and corners.

7.10.7 Environment

The product does not contain any known or suspected carcinogens.

Environmental controls meet or exceed all applicable government regulations in the country of origin.

Safe chemical usage and manufacturing control are used to protect the environment. An environmental impact assessment has been done on the manufacturing process used to build the drive, the drive itself, and the disposal of the drive at the end of its life.

Production also meets the requirements of the international treaty on chloroflurocarbon (CFC) control known as the United Nations Environment Program Montreal Protocol, and as ratified by the member nations. Material to be controlled include CFC-11, CFC-12, CFC-113, CFC-114, CFC-115, Halon

1211, Halon 1301, and Halon 2402. Although not specified by the Protocol, CFC-112 is also controlled. In addition to the Protocol HGST requires the following: y No packaging used for the shipment of the product uses controlled CFCs in the manufacturing process.

y No manufacturing processes for parts or assemblies—including printed circuit boards—use controlled CFC materials.

7.10.8 Secondary circuit protection

This product utilizes printed circuit wiring that must be protected against the possibility of sustained combustion due to circuit or component failures as defined in C-B 2-4700-034 (Protection Against

Combustion). Adequate secondary over-current protection is the responsibility of the using system.

The user protects the HDD from its electrical short circuit problem. A 0.5-Amp limit is required for safety purposes.

7.11 Packaging

Drives are shipped in appropriate containers and placed on pallets in accordance with HGST Supplier

Packaging Instruction (HGST specification GA-21-9261-8).

Drives procured under this specification are assembled and tested using "Electrostatic Discharge

Protection" process and precedure—HGST document number EN/14/0116. A protection system suitable for the fixed disk drive must be installed and monitored by the appropriate ME/QA function.

The goal is to prevent electrostatic potential from accumulating on any object which may deliberately or inadvertently be brought into contact with the drive.

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Drives are shipped in ESD protective bags as defined in the HGST specification control drawing

(P/N 6937283).

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8.0 Electrical interface specifications

The following figure defines all the DC characteristics of the drive. Unless otherwise stated, the following are the electrical interface requirements: y Vcc = 5 ± 5% V y Vcc = 3.3 ± 5% V y Ta = 0–70°C (70°CMax at Top cover of the drive)

(See Section,“Environment”)

Symbol

V cc

V i

V o

Pd

T opr

T stg

Item

Input power

Input Voltage

Output Voltage

Power consumption

Operating Temperature

Storage temperature

Figure

19

. DC characteristics

Measurement method

with respect to ground

Ta = 25°C

Conditions

–0.3 to 7.0

–0.3 to V

CC

+ 0.3

–0.3 to V

CC

+ 0.3

1.2

0–70

–40 to 70

Unit s

Volt s

Volt s

Volt s

Wat t

°C

°C

8.1 Cabling

Refer to CompactFlash specification.

8.2 Interface connector

The CompactFlash (CF) interface connector is designed to meet the connector interface specification specified in CF specification revision 1.4.

8.3 Signal definition

For the pin assignments of the interface signals, refer to the CompactFlash specification revision 1.4.

8.4 Signal description

Refer to Table 4-2 of CompactFlash specification revision 1.4 with the following exceptions:

In True IDE Mode -INPACK (pin 43) is used as DMARQ (DMA request) for DMA data transfers.

This signal is asserted by the device when it is ready to transfer data to or from the host.

In True IDE Mode -REG (pin 44) is used as -DMACK (DMA acknowledge) for DMA data transfers. This signal is used by the host in response to DMARQ to initiate DMA transfers.

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8.5 Interface logic signal levels

The interface logic signal has the following electrical specifications:

Symbol

Paramete r

V

V

I

I

OH

OL

IH

IL

Condition

"H"

Output

Voltag e

"L"

Output

Voltag e

"H"

Input

Current

"L"

Input

Current

I

OH

=

2.0 mA (3.135V)

4.0mA (4.75V)

I

OH

=

3.5 mA (3.135 V)

7.0 mA (4.75 V)

I

OH

=

–2.5 mA

(3.465V)

–4.0 mA (5.25 V)

I

OH

=

–4.0 mA (3.465

V)

–7.0 mA (5.25 V)

READY,

INPACK#,

BVDI,

BVD2 the other computer

READY,

INPACK#,

BVDI,

BVD2 the other outputs

V

V

IN

IN

=V

CC

= GND

PC Card Mode

V

IN

= GND

IDE Mode

CE1#, CE2#,

OE#, WE#,

IORD#,

IOWR#,

REG#,

CSEL,

A10–A0

RESET

BVD1,

BVD2,

D15–D0

CE1#, CE2#,

OE#, WE#,

REG#,

IORD#,

IOWR#,

CSEL

RESET

A10–A0

D15–D0

CE1#, CE2#,

IORD#,

IOWR#,

A10–A0,

RESET

D15–D0

OE#, WE#,

REG#,

BVD1, BVD2,

CSEL

Minimum

3.135

V

4.75 V

63

–14

–7

–14

3.00

–1

–5

–1

–5

–1

–5

90

–20

–10

–20

Typica

l

Maximum

3.465

V

5.25 V

70

–90

–45

–90

3.45

0.4

1

5

1

5

1

5

110

–140

–70

–140

Figure 20. Interface logic signal levels.

Unit

Volts

Volts mA mA

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8.6 Attribute Memory Read timing

The Attribute Memory access time is defined as 300 ns. Detailed timing specifications are shown in the following two figures.

Symbol

tcR taA taCE taOE tdisCE tdisOE tenCE tenOE tvA

Item

Read Cycle Time

Address Access Time

Card Enable Access Time

Output Enable Access Time

Output Disable Time from CE

Output Disable time from OE

Output Enable Time from CE

Output Enable Time from OE

Data Valid from Address Change

Figure 21. Attribute Memory Read timing data

Minimum

(ns)

300

5

5

0

Typical

(ns)

Maximum

(ns)

300

300

150

100

100

Memory Timing Chart

Read Cycle

VIH

An

-REG

VIL

VIH

CE#

VIL

VIH

OE#

VIL

VIH

WAIT#

VIL

??(A)

??(CE) ten(CE) ta(OE)

?c(?) ta(OE) tv(A) tdis(CE) tdis(CE) tdis(OE) ten(OE)

VOH

Dm

VOL

(Dout)

WE#= ‘‘? ”

Note?

Hi-Z

Data invalid

Figure 22. Attribute Memory Read timing diagram

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8.7

Common Memory Read timing

Detailed timing specifications are shown in the following figure.

Symbol

tcR taA taCE taOE tdisCE tdisOE tenCE tenOE tvA

Item

Read Cycle Time

Address Access Time

Card Enable Access Time

Output Enable Access Time

Output Disable Time from CE

Output Disable time from OE

Output Enable Time from CE

Output Enable Time from OE

Data Valid from Address Change

Figure 23. Common Memory Read timing

Minimum

(ns)

250

5

5

0

Typical

(ns)

Maximum

(ns)

250

250

125

100

100

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Hitachi Global Storage Technologies storage products

8.8

Attribute and Common Memory Read timing

The Card Configuration write access time is defined as 250 ns. Detailed timing specifications are shown in the following figure.

Symbol

tcW twWE taA tsuA-WEH tsuCE-WEH tsuD-WEH thD trecWE tdisWE tdisOE tenWE tenOE tsuOE-WE thOE-WE

Item

Write Cycle Time

Write Pulse Width

Address Setup Time

Address Setup Time for WE="H"

Card Enable Setup time for

Data Setup Time for WE="H"

Data Hold Time

Write Recovery Time

Output Disable Time from WE

Output Disable Time from OE

Output Enable Time from WE

Output Enable Time from OE

Output Enable Setup for WE="H"

Output Enable Hold for WE="H"

Figure 24. Attribute and Common

Memory Read timing data

tcw

V

IH

An,REG#

V

IL

CE#

VIH

VIL

VIH

OE3

VIL

VIH

WE#

VIL

Dm

VIH

VOH

VOL tSU(CE-WEH) tSU(A-WEH)

Minimum

(ns)

250

150

30

180

180

80

30

30

Typical

(ns)

Maximum

(ns)

5

5

10

10

tSU(A) tW(WE) trec(WE)

Hi-Z tSU(OE-WE) tdis(OE) th(OE-WE) tSU(D-WEH) tH(D) tdis(WE)

Hi-Z

Data In

Valid ten(OE) ten(WE)

100

100

Figure 25. Attribute and Common

Memory Read timing

Hard disk drive specfication for Hitachi Microdrive TM

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Hitachi Global Storage Technologies storage products

8.9 I/O Input (Read) timing

Detailed timing specifications are shown in the following two figures.

Symbol

td (IORD) tw th (IORD) tw (IORD) tsu A (IORD) th A (IORD) tsu CE (IORD) th CE (IORD) tsu REG (IORD) th REG (IORD) tdf INPACK (IORD) tdr INPACK (IORD) tdf IOIS16 (ADR) tdr iois16 (ADR) tdf WT (IIORD) tdr (WT) tw (WT)

Figure 26. Common Memory Read Timing data

Item

Data Delay after IORD

Data Hold following IORD

IORD width Time

Address Setup before IORD

Address Hold following IORD

CE Setup before IORD

CE Hold following IORD

REG Setup before IORD

REG Hold following IORD

INPACK Delay Falling from IORD

INPACK Delay Rising from IORD

IOIS16 Delay Falling from Address

IOIS16 Delay Rising from Address

Wait Deay Falling from IORD

Data Delay from Wait Rising

Wait Width Time

Minimum

(ns)

Maximum

(ns)

0

165

70

20

5

20

5

0

45

45

35

35

35

0

350

A[10::0]

REG#

CE#

IORD# tsuREG(IORD) tsuCE(IORD) th th

A(IORD)

REG(IORD) th

CE(IORD) tw(IORD) tsuCE(IORD) tdrINPACK(ADR)

INPACK# tdfINPACK(IORD)

IOIS16# tdfIOIS16(ADR)

WAIT# tdfWT(IORD) td(IORD) tdr(WT) tw(WT) tdrIOIS16(ADR) th(IORD)

D[15::0]

Figure 27. Common Memory Read Timing diagram

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Hitachi Global Storage Technologies storage products

8.10 I/O Input (Write) timing

Detailed timing specifications are shown in the following two figures.

Symbol Item

td(IOWR) th(IOWR) tw(IOWR) tsuA(IOWR) thA(IOWR) tsuCE(IOWR) thCE(IOWR) tsuREG(IOWR) thREG (IOWR) tdf IOIS16 (ADR) tdr IOIS16 (ADR) tdfWT(IOWR) tdr IOWR(WT) tw(WT)

Data Setup before IOWR

Data Hold following IOWR

IOWR width Time

Address Setup before IOWR

Address Hold following IOWR

CE Setup before IOWR

CE Hold following IOWR

REG Setup before IOWR

REG Hold following IOWR

IOIS16 Delay Falling from Address

IOIS16 Delay rising from Address

Wait Deay Falling from IOWR

IOWR high from Wait high

Wait Width Time

Minimum

(ns)

60

30

165

70

20

5

20

5

0

Maximum

(ns)

0

35

35

35

350

Note: The maximum load on -WAIT, -INPACK, and -IOIS16 is 1LST TL with a 50 pF total load.

Figure 28. I/O Write timing data

A[10::0]

REG#

CE#

IORD# tsuREG(IORD) tsuCE(IORD) th th

A(IORD)

REG(IORD) th

CE(IORD) tw(IORD) tsuCE(IORD) tdrINPACK(ADR)

INPACK# tdfINPACK(IORD)

IOIS16# tdfIOIS16(ADR)

WAIT# tdfWT(IORD) td(IORD) tdr(WT) tw(WT) tdrIOIS16(ADR) th(IORD)

D[15::0]

Figure 29. I/O Write timing diagram

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Hitachi Global Storage Technologies storage products

8.11 True IDE Mode I/O Input (Read) Timing

Detailed timing specifications are shown in the following two figures.

Symbol

td (IORD) th (IORD) tw (IORD) tsu A (IORD) th A (IORD) tsu CE (IORD) th CE (IORD) tdf IOIS16 (ADR) tdf IOIS16 (ADR)

Item

Data Delay after IORD

Data Hold following IORD

IORD Width Time

Address Setup before IORD

Address Hold following IORD

CE Setup before IORD

CE Hold following IORD

IOIS16 Delay Falling from

Address

IOIS16 Delay Rising from

Address

Figure 30. True IDE Mode IO Input (Read) timing data

Minimum

(ns)

0

165

70

20

5

20

Maximum

(ns)

100

35

35

An

CE#

IORD# tsuA(IORD) tsuCE(IORD) tw(IORD) td(IORD)

IOIS16# tdfIOIS16(ADR)

Dout th

A(IORD) th

CE(IORD) th

(IORD)

Note: The maximum load on -IOIS16 is a 1 LSTTL with a 50 pF total load.

Figure 31. True IDE Mode IO Input (Read) timing diagram

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8.12 True IDE Mode Multiword DMA Data Transfer Timing

The device supports multiword DMA data transfer for Read DMA and Write DMA commands, which are available in true IDE mode only. In multiword DMA data transfer, INPACK# is used as DMARQ and REG# is used as DMACK#. Detailed timing specifications are shown in the following figure. Note that the fastest transfer timing is equivalent to “DMA Mode 2” as defined in ATA/ATAPI-4 standard.

Symbol

t0 (*1) tC tD (*1) tE tF tG tH tI tJ tKr (*1) tKw (*1) tLr tLw tZ

Item

Cycle time

DMACK# to DMARQ delay

IOR#/IOW#

IOR# data access

IOR# data hold

IOR#/IOW# data setup

IOW# data hold

DMACK# to IOR#/IOW# setup

IOR#/DIOW# to DMACK# hold

IOR# negated pulse width

IOW# negated pulse width

IOR# to DMARQ delay

IOW# to DMARQ delay

DMACK# to tristate

Minimum

(ns)

120

70

5

20

10

0

5

25

25

Maximum

(ns)

60

35

35

25

Notes:

(*1) t0 is the minimum total cycle time, tD is the minimum command active time, and tK (tKr or tKw, as appropriate) is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, tD, tK shall be met. The minimum tootle cycle time requirement, t0, is greater than the sum of tD and tK. This means the host can lengthen either tD or tK or both to ensure that t0 is equal to the value reported in the devices identify drive data.

Figure 32. Multiword DMA data transfer timing data

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8.13 True IDE Mode Ultra DMA Data Transfer Timing

The device supports Ultra DMA data transfer for Read DMA and Write DMA commands, which are available in true IDE mode only. In Ultra DMA data transfer, INPACK# is used as DMARQ and REG# is used as DMACK#. Detailed timing specifications are shown in the following figure. Note that the fastest transfer timing is equivalent to “Ultra DMA Mode 2” as defined in ATA/ATAPI-4 standard.

Symbol

t

2cyctyp t cyc t

2cyc t

DS t

DH t

DVS t

DVH t

CS t

CH t

CVS t

CVH t

ZFS t

DZFS t

FS t

LI t

MLI t

UI t

AZ t

ZAH t

ENV t

RFS t

RP t

IORDYZ t

IORDYY t

ACK t

SS

Item

Typical sustained average two Cycle time

Cycle Time allowing for asymmetry and clock variations

Two cycle time allowing for clock variations

Data setup time at recipient

Data hold time at recipient

Data Valid setup time at sender

Data Valid hold time at sender

CRC word setup time at device

CRC word hold time at device

CRC word valid setup time at host

CRC word valid hold time at sender

Time from STROBE output released-to-driving until the first transition of critial timing

Time from data output released-to-driving until the first transition of critical timing

First STROBE time

Limited interlock time

Interlock time with minimum

Unlimited interlock time

Maximum Time allowed for output drivers to release

Minimum delay time required for output

Envelope time

Ready-to-final-STROBE time

Ready-to-pause time

Maximum time before releasing IORDY

Minimum time before driving IORDY

Setup and hold times for DMACK-

Time from STROBE edge to negation of

DMARQ or assertion of STOP

Minimum

(ns)

120

54

115

7.0

5.0

31.0

6.2

7.0

5.0

31.0

6.2

0

31.0

0

20

50

0

20

0

20

20

0

100

Maximum

10

(ns)

170

150

70

60

20

Figure 33. Ultra DMA data transfer timing data

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Hitachi Global Storage Technologies storage products

8.14 Power on/off timing

Detailed timing specifications are shown in the following two figures.

Symbol

Vi(CE)

Item

Card Enable signal level

V

IH

Condition

0 V =< V

2 V =< V

=< V

CC

CC

CC

< 2 V

< V

IH tsu(V

CC

) tsu (RESET) trec (Vcc) tpr tpf tw (RESET) th (Hi-zRESET) ts (Hi-zRESET)

Card Enable Setup time

RESET Setup time

Card Enable Recovery time

Power rising time

Power falling time

RESET pulse width

10% J 90% of V

CC

90% of V

CC

J 10%

20

20

1

0.1

3

10

1

0

Minimum Typ.

V

CC

0

V

- 0.1

IH

V

CC

Max.

V

CC

V

CC

+ 0.1

V

CC

+ 0.1

40

300 u s m s u s m s m s m s lt s

V o lt s

V o it s

U n lt s

V o m s m s

Figure 34. Power On/Off timing data

Hard disk drive specfication for Hitachi Microdrive TM

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Hitachi Global Storage Technologies storage products

[email protected]%

VIH tpr

[email protected]%

2V tsu(Vcc) tsu(RESET) th(Hi-z

RESET)

Hi-z tw(RESET)

Vcc

CE1#,

CE2#

RESET tsu(RESET) tw(RESET)

CE1#,

CE2#

Vcc tpf

[email protected]% trec(Vcc)

VIH

2V ts(Hi-z

RESET)

[email protected]%

Hi-z

Figure 35. Power On/Off timing diagram

Hard disk drive specfication for Hitachi Microdrive TM

Subject to change

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Hitachi Global Storage Technologies storage products

Part 2. Interface specification

Hard disk drive specfication for Hitachi Microdrive TM 3K4

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9 General

9.1 Introduction

This part of specification describes the host interface of Hitachi Microdrive 3K4.

The interface conforms to the CF+ and CompactFlash Specification with certain limitations described in " 2 Deviations from Standard " on page 0.

Hitachi Microdrive<ProductName> 3K4 following new functions included by

CompactFlash Specification 1.4 or newer standard.

Hitachi Microdrive 3K4 support following functions as Vendor Specific Function.

y

SENSE CONDITION command y y

Format Unit command

Metadata Storage Function

The following terminology is used in this part of specification.

Device

Host

First Command

INTRQ

Device indicates Hitachi Microdrive 3K4

Host indicates the system that the device is attached to.

The command which is executed first right after power on reset or hard reset when the initial power mode at power on is Standby mode.

Interrupt request (Device or Host)

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10 Deviations from Standard

ICRCE (CRC)

Standby Timer

Write Verify

The device supports Ultra DMA transfer mode. BBK bit in Error register is replaced by ICRCE ( Interface CRC Error ) bit.

If STANDBY command or IDLE command is used with the Sector Count

Register being zero, the standby timer is programmed to 109 minutes, instead of disabling automatic standby function. Note that if the advanced power management level is less than 80h, which is power-on default, the transition timing to enter Standby mode is determined by either the standby timer or Adaptive Battery File Extender algorithm, whichever meets the condition first.

WRITE VERIFY command does not include read verification after write operation. The function is exactly same as WRITE SECTORS command.

Hard disk drive specfication for Hitachi Microdrive TM 3K4

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11 System interface

11.1 PCMCIA memory spaces and configuration registers

There are two types of memory address space in the drive: common memory and attribute memory. Common memory is the working address space used to map the memory arrays for storing data. It may be accessed by the host for memory read and write operations. The card permits both 8 and 16 bit accesses to all of its common memory addresses. Attribute memory is used for configuration information and is limited to 8-bit wide accesses only at even addresses. The attribute memory space contains the CIS (Card Information Structure) and configuration registers. The drive is identified by appropriate information in the CIS. The following configuration registers are used to coordinate the I/O spaces and the Interrupt level of cards that are located in the system.

0

X

1

1

-CE2 -CE1 -REG -OE

1

X

1

0

X

0

X

0

1 0 1 0

-WE

X

1

A10

X

0

1 X

A9

X

1

X

A8-A4 A3

XX

XX

X

X

XX X

A2

X

X

X

A1

X

X

X

A0

X

0

X

0

0

X

1

0

1

0

0

1

0

0

0

1

0

0

0

0

0

1

1

1

1

0

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

0

1

0

1

0

1

1

1

0

0

0

0

1

0

1

0

1

0

X

X

0

X

X

X

0

0

X

X

X

X

X

X

1

X

X

X

0

0

X

X

X

X

XX

XX

XX

XX

XX

XX

XX

XX

XX

XX

XX

XX

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

0

0

0

1

0

0

X

X

X

X

X

1

Selected space

Standby

Configuration Registers Read

Common Memory Read (8-bit

  D7-D0)

Common Memory Read (8-bit

D15-D8)

Common Memory Read (16-bit

D15-D0)

Configuration Registers Write

Common Memory Write (8-bit

D7-D0)

Common Memory Write (8-bit

D15-D8)

Common Memory Write (16-bit

D15-D0)

Card Information Structure read

Invalid Access (CIS Write)

Invalid Access (Odd Attribute

Read)

Invalid Access (Odd Attribute

Write)

Invalid Access (Odd Attribute

Read)

Invalid Access (Odd Attribute

Write)

Figure 1. Registers and memory space decoding

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Hitachi Global Storage Technologies storage products

X

X

X

X

X

X

X

-CE2 -CE1

X 0

-REG

0

-OE

0

-WE

1

A10

0

A9

1

A8-A4

00

A3

0

0

0

0

0

0

0

0

0

1

0

1

0

0

1

0

1

0

0

0

0

1

1

1

1

00

00

00

00

0

0

0

0

0

0

0

0

0

0

1

0

1

0

1

0

0

0

0

1

1

1

00

00

00

0

0

0

A2

0

0

0

0

1

1

1

1

A1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

A0

0

0

Selected space

Configuration Option

Register Read

Configuration Option

Register Write

Card Status Register Read

Card Status Register Write

Pin Replacement Register

Read

Pin Replacement Register

Write

Socket and Copy Register

Read

Socket and Copy Register

Write

Figure 2. Configuration registers decoding

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11.2 Card configuration registers

The drive has a set of configuration registers in attribute memory space. These registers are used to control the configurable characteristics of the card. The configurable characteristics include the electrical interface, I/O address space, interrupt request, and power requirements of the card. These registers also provide a method for accessing status information about the card. The information can be used to arbitrate between multiple-interrupt sources on the same interrupt request level. Addresses of the configuration registers are specified by the Configuration registers Base Address in the

TPCC_RADR field of the Configuration Tuple and offset relative to the base address.

For example, the Configuration and Status register can be located at offset 02h from the base address. The addresses of the card configuration registers should always be read from the CIS since these addresses may vary in future products.

11.2.1 Configuration Option Register (Offset 00h)

The Configuration Option Register is used to configure the cards interface, address decoding, and interrupt and to issue a soft reset to the drive.

Operation

R/W

D7

SRESET

D6

LevlREQ

D5

Conf5

D4

Conf4

Figure 3. Configuration Option Register (Offset 00h)

D3

Conf3

D2

Conf2

D1

Conf1

D0

Conf0

SRESET: Soft Reset -Setting this bit to one (1), waiting the minimum reset width time and returning to zero (0) places the card in the Reset state. Setting this bit to one (1) is equivalent to assertion of +RESET signal except that the SRESET bit is not cleared. Returning this bit to zero (0) leaves the card in the same unconfigured, Reset state as following power-up and hardware reset. This bit is set to zero (0) by power-up and hardware reset. Using PCMCIA Soft Reset is considered a hard reset from the ATA point of view. An "ATA" soft reset is issued through the Device Control Register.

LevlREQ: This bit is set to (1) when level mode Interrupt is selected, and zero (0) when pulse mode is selected. This bit is set to zero (0) by power-up and hardware reset. When the card is in Level Mode, the

-IREQ pin is pulled up to Vcc on the card and asserted low to signal an interrupt. The interrupt is kept asserted until the host reads the card status register, thereby resetting the interrupt indication and causing

-IREQ to be deasserted. When the card is in pulse mode, the card signals an interrupt by the trailing edge of the negative pulse which width is at least 0.5ms.

Conf5 - Conf0: Configuration Index. This is set to zero (0) by power-up and hardware reset. It is used to select operation mode of the card as shown below. Conf5 and Conf4 are reserved and must be written as zero (0) .

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Conf5

0

0

0

0

Conf4

0

0

0

0

Conf3

0

0

0

0

Conf2

0

0

0

0

Conf1

0

0

1

1

Conf0

0

1

0

1

Card Configuration Mode

Memory mapped

I/O mapped 16 contiguous registers at any

16-byte system decoded boundary

Primary I/O mapped, 1F0h n 1F7h/3F6h n

3F7h

Secondary I/O mapped, 170h n 177h/376h n

377h

Figure 4. Configuration Option Register (Offset 00h)

11.2.2 Card Configuration Status Register (Offset 02h)

The Card Configuration and Status Register contains information about the card condition.

Operation

Read

Write

D7

Changed

0

D6

SigChg

SigChg

D5

IOis8

IOis8

D4

-XE

-XE

D3

0

0

D2

PwrDwn

PwrDwn

D1

Int

0

D0

0

0

Figure 5. Configuration Status Register (Offset 02h)

Changed: This bit indicates that one or both of the Pin Replacement register CRdy, or CWProt bits are set to one (1). When the Changed bit is set, pin 46 (-STSCHG) is held low if the SigChg bit is a one (1) and the card is configured for the I/O interface.

SigChg: This bit serves as a gate for pin 46 (-STSCHG). If the card is configured for the I/O interface and this bit is zero (0), pin 46 (-STSCHG) is held high. If the card is configured for the I/O interface and both the Changed and SigChg bits are set to one (1), the card asserts pin 46 (-STSCHG) upon changes in the Changed bit.

IOis8: This bit is set to one (1) when the card is configured in 8-bit I/O mode as the host provides I/O cycles only with an 8-bit (D7-D0) data path.

-XE: Extended power enabled. When the host sets this bit to zero (0), the card enables extended power operations. When the host sets this field to one (1), the card disables extended power operations. When this filed is read, the bit indicates the card's acceptance of extended power operations. If it is read as one

(1), extended power operations are being disabled. If it is read as zero (0), the card can perform extended power operations. This bit is read as zero (0) after power-up and hardware reset. Identify Device information word 170 also has -XE bit for the same purpose. These -XE bits are always consistent.

Extended power operations are defined as a command that requires the hostís extended power capability.

For the drive, extended power operations includes any read, write and seek commands. Identify Device,

Set Features (Enable Extended Power and Disable Extended Power), Request Sense and Execute Device

Diagnostics are not extended power operations, i.e., these commands can be performed regardless of the setting in -XE bit.

PwrDwn: The device does not change PwrDwn bit even if the power mode is changed as a result of either an internal event or command completion. Also, the state of Rdy/-Bsy signal is not changed when the host changes PwrDwn bit is intended for the host system to direct the device's immediate entrance of

Standby mode upon command completion. If PwrDwn bit is set to one(1), the device immediately enters

Standby mode after command completion, regardless of the standby timer and setting of the advanced power management level. If PwrDwn is set to zero(0), the device entrance of Standby mode is controlled by both standby timer and Adaptive Battery Life Extender algorithm

Int: This bit represents the internal state of the interrupt request. This value is available whether or note

I/O interface has been configured. This signal remains true until the condition which caused the interrupt

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request has been serviced. If interrupts are disabled byte -IEN bit in the Device Control Register, this bit is zero (0).

11.2.3

Pin Replacement Register (Offset 04h)

The Pin Replacement Register is used to provide the card status information about

READY.

Operation

Read

Write

D7

0

0

D6

0

0

D5

CRdy/-Bsy

CRdy/-Bsy

D4

0

0

Figure 6. Pin Replacement Register (Offset 04h)

D3

1

0

D2

1

0

D1

Rdy/-Bsy

MRdy/-Bsy

D0

0

0

Crdy/-Bsy: This bit is set to one (1) when the bit Rdy/-Bsy changes state. This bit can also be written by the host.

Rdy/-Bsy: This bit is used to determine the internal state of the Rdy/-Bsy signal. This bit can be used to determine the state of the RDY/-BSY as this pin has been reallocated for use as -IREQ on the I/O interface.

MRdy/-Bsy: This bit acts as a mask for writing the corresponding bit CRdy/-Bsy.

11.2.4

Socket and Copy Register (Offset 06h)

This register contains additional configuration information. The host must always set this register before writing configuration index to the Configuration Option Register.

Operation

Read

Write

D7

Reserved

0

D6

0

0

D5

0

0

D4

Device #

Device #

Figure 7. Socket and Copy Register (Offset 06h)

D3

0

X

D2

0

X

D1

0

X

D0

0

X

Reserved: This bit is reserved for future standards. This bit must be set to zero (0) by the host whenever the register is written.

Device #: This is always read as zero (0) and must be set to zero (0) as the drive does not support twin card configuration.

X: the socket number field is ignored by the drive.

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11.3 CF-ATA Drive Register Set Definition and Protocol

The drive can be configured as an I/O device through y

Primary I/O mapped address spaces (1F0h - 1F7h, 3F6h - 3F7h) or secondary I/O y mapped address spaces (170h - 177h, 376h - 377h)

Contiguous I/O mapped address spaces; any system decoded 16-byte I/O block y y

Memory mapped space

True IDE mode; only I/O operations to the Task File and Data registers allowed, no

PCMCIA functionality.

The communication to or from the card is done using the Task File registers which provide all the necessary registers for control and status information.

-REG

0

0

0

0

0

0

0

0

0

0

11.3.1 Primary or Secondary I/O mapped addressing

A9-A4

1Fh(17h)

1Fh(17h)

1Fh(17h)

1Fh(17h)

1Fh(17h)

1Fh(17h)

1Fh(17h)

1Fh(17h)

1Fh(17h)

1Fh(17h)

0

0

0

0

0

0

0

0

A3

0

0

0

0

1

1

1

1

1

1

A2

0

0

1

1

0

0

1

1

1

1

A1

0

0

0

1

0

1

0

1

0

1

A0

0

1

-IORD=0

Even RD Data

Error Register

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Status

Alternate Status

Device Address

-IOWR=0

Even WR data

Features

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Command

Device Control

Reserved

Notes

1,2

1,2

Notes:

1.Register 0 is accessed with -CE1 low and -CE2 low (and A0 = dont care) as a word register on the combined

Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with

-CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access.

2. A byte access to Register 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register.

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11.3.2 Contiguous I/O mapped addressing

-REG

0

0

0

0

0

0

0

0

0

0

0

0

0

A3

0

0

0

0

0

0

0

0

1

1

1

1

1

A2

0

0

0

0

1

1

1

1

0

0

1

1

1

A1

0

0

1

1

0

0

1

1

0

0

0

1

1

A0

0

1

0

1

0

1

0

1

0

1

1

0

1

Offset

0

1

2

3

4

5

6

7

8

9

D

E

F

-IORD=0

Even RD Data

Error

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Status

Dup. Even RD Data

Dup. Odd RD Data

Dup. Error

Alternate Status

Device Address

-IOWR=0

Even WR Data

Features

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Command

Dup. Even WR Data

Dup. Odd WR Data

Dup. Features

Device Control

Reserved

Notes

1

2

2

2

2,3

Notes:

1. Register 0 is accessed with -CE1 low and -CE2 low (and A0 = don’t care) as a word register on the combined

Odd Data Bus and Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with

-CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. A byte access to register 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register.

2. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even than odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data buffer. Repeated byte accesses to register 9 are not supported. However, repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data buffer. Byte accesses to register 9 access only the odd byte of the data.

3. The drive does not support accessing the Dup. Features and the Dup. Error as word register at offset 0Ch with

CE1 low and CE2 low.

4. Address lines that are not indicated are ignored by the drive for accessing all the registers in this table.

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11.3.3 Memory mapped addressing

-REG A10 A9-A4 A

3

A

2

A

1

A

0

Offset

9

D

E

F

8

9

0

1

2

3

4

5

6

7

8

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

1

1 x x

0

0

1

1

0

0

1

1

0

0

1

1

1 x x

0

0

0

0

1

1

1

1

0

1

1

1

1 x x

0

0

0

0

0

0

0

0

1 x x x x x x x x x x x x x x x

0

0

0

0

1

1

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

-OE=0 -WE=0

Even RD Data

Error

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Status

Dup. Even RD

Data

Dup. Odd RD

Data

Dup. Error

Alternate Status

Device Address

Even RD Data

Odd RD Data

Even WR Data

Features

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Command

Dup. Even WR

Data

Dup. Odd WR

Data

Dup. Features

Device Control

Reserved

Even WR Data

Odd WR Data

3

3

Notes:

1. Register 0 is accessed with -CE1 low and -CE2 low as a word register on the combined Odd Data Bus and

Even Data Bus (D15-D0). This register may also be accessed by a pair of byte accesses to the offset 0 with -CE1 low and -CE2 high. Note that the address space of this word register overlaps the address space of the Error and

Feature byte-wide registers that lie at offset 1. When accessed twice as byte register with -CE1 low, the first byte to be accessed is the even byte of the word and the second byte accessed is the odd byte of the equivalent word access. A byte access to address 0 with -CE1 high and -CE2 low accesses the error (read) or feature (write) register.

2. Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is equivalent to register 0, while register 9 accesses the odd byte. Therefore, if the registers are byte accessed in the order 9 then 8 the data will be transferred odd byte then even byte. Repeated byte accesses to register 8 or 0 will access consecutive (even then odd) bytes from the data buffer. Repeated word accesses to register 8, 9 or 0 will access consecutive words from the data buffer. Repeated byte accesses to register 9 are not supported. However, repeated alternating byte accesses to registers 8 then 9 will access consecutive (even then odd) bytes from the data buffer. Byte accesses to register 9 access only the odd byte of the data.

3. Accesses to even addresses between 400h and 7FFh access register 8. Accesses to odd addresses between

400h and 7FFh access register 9. This 1 Kbyte memory window to the data register is provided so that hosts can perform memory to memory block moves to the data register when the register lies in memory space. Some hosts, such as the X86 processors, must increment both the source and destination addresses when executing the memory to memory block move instruction. Some PCMCIA socket adapters also have auto incrementing address logic embedded within them. This address window allows these hosts and adapters to function efficiently. Note that this entire window accesses the Data Register FIFO and does not allow random access to the data buffer within the drive. A word access to address at offset 8 will provide even data on the low-order byte of the data bus, along with odd data at offset 9 on the high-order byte of the data bus.

4. The drive does not support accessing the Dup. Features and the Dup. Error as word register at offset 0Ch with

CE1 low and CE2 low.

1,

2

1,

2

N ot es

2

2

2,

4

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11.3.4 True IDE Mode addressing

-CE2

1

1

1

1

1

1

1

1

0

0

-CE1

0

0

0

0

0

0

0

0

1

1

A2

0

0

0

0

1

1

1

1

1

1

A1

0

0

1

1

0

0

1

1

1

1

A0

0

1

0

1

0

1

0

1

0

1

-IORD=0

RD Data

Error

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Status

Alternate Status

Device Address

-IOWR=0

WR Data

Features

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Command

Device Control

Reserved

The Command Block Registers are used for sending commands to the device or posting status from the device.

The Control Block Registers are used for device control and to post alternate status.

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11.4 CF-ATA Registers

11.4.1 Alternate Status Register

7

BSY

6

RDY

5

DF

Alternate Status Register

4

DSC

3

DRQ

2

COR

1

IDX

0

ERR

This register contains the same information as the Status Register. The only difference is that reading this register does not imply interrupt acknowledge or clear a pending interrupt. See "Status register" for the definition of the bits in this register.

11.4.2 Command Register

This register contains the command code being sent to the device. Command execution begins immediately after this register is written.

All other registers required for the command must be set up before writing the

Command Register.

11.4.3 Cylinder High Register

This register contains the high order bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number.

In LBA Mode this register contains Bits 16-23. At the end of the command, this register is updated to reflect the current LBA Bits 16-23.

The cylinder number may be from zero to the number of cylinders minus one.

11.4.4 Cylinder Low Register

This register contains the low order 8 bits of the starting cylinder address for any disk access. At the end of the command, this register is updated to reflect the current cylinder number.

In LBA Mode this register contains Bits 8-15. At the end of the command, this register is updated to reflect the current LBA Bits 8-15.

The cylinder number may be from zero to the number of cylinders minus one.

11.4.5 Data Register

This register is used to transfer data blocks between the device data buffer and the host for data-in,data-out and DMA commands. Because this register overlaps the Error

Register, results of accessing to the registers at address 1F1h ( in I/O primary address configuration ) or 171 ( in I/O secondary address conifguration ) with 16-bit width. ( i.e.

-CE2=0 and -CE1=0 ) are undefined.

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11.4.6 Device Control Register

7

-

6

-

5

-

Device Control Register

4

-

3

1

2

SRST

1

-IEN

0

0

This register is used to control thr Compact Flash Storage Card interrupt request and to issue an ATA soft reset to the card. This register can be wrriten even if the device is

BUSY.

Bit Definitions

SRST (RST)

-IEN

Software Reset. The device is held reset when RST=1. Setting RST=0 reenables the device.

The host must set RST=1 and wait for at least 5 microseconds before setting

RST=0, to ensure that the device recognizes the reset.

Interrupt Enable. When -IEN=0, and the device is selected, device interrupts to the host will be enabled. When -IEN=1, or the device is not selected, device interrupts to the host will be disabled.

11.4.7 Drive Address Register

7

HIZ

6

-WTG

5

-H3

Drive Address Register

4

-H2

3

-H1

2

-H0

1

-DS1

0

-DS0

This register contains the inverted drive select and head select addresses of the currently selected drive.

Bit Definitions

HIZ

-WTG

-H3,-H2,-H1,-H0

-DS1

-DS0

High Impedance. This bit is not device and will always be in a high impedance state.

-Write Gate. This bit is 0 when writing to the disk device is in progress.

-Head Select. These four bits are the one's complement of the binary coded address of the currently selected head. -H0 is the least significant.

-Drive Select 1. Drive select bit for device 1, active low. DS1=0 when device 1 (slave) is selected and active.

-Drive Select 0. Drive Select bit for device 0, active low. DS0=0 when device

0 (master) is selected and active.

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11.4.8 Device/Head Register

7

1

6

L

5

1

Device/Head Register

4

DRV

3

HS3

2

HS2

This register contains the device and head numbers.

1

HS1

0

HS0

Bit Definitions

L

DRV

HS3,HS2,HS1,HS0

Binary encoded address mode select. When L=0, addressing is by CHS mode. When L=1, addressing is by LBA mode.

Device. When DRV=0, device 0 (master) is selected. When DRV=1, device

1 (slave) is selected.

Head Select. These four bits indicate binary encoded address of the head.

HS0 is the least significant bit. At command completion, these bits are updated to reflect the currently selected head.

The head number may be from zero to the number of heads minus one.

In LBA mode, HS3 through HS0 contain bits 24-27 of the LBA. At command completion, these bits are updated to reflect the current LBA bits

24-27.

11.4.9 Error Register

7

CRC

6

UNC

5

0

Error Register

4

IDNF

3

0

2

ABRT

1

TK0N

0

AMNF

This register contains status from the last command executed by the device, or a diagnostic code.

At the completion of any command except Execute Device Diagnostic, the contents of this register are valid always even if ERR=0 in the Status Register.

Following a power on, a reset, or completion of an E

EXECUTE DEVICE DIAGNOSTICS command, this register contains a diagnostic code. See "Diagnostic Codes" on page 29 for the definition.

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Bit Definitions

ICRCE (CRC)

UNC

IDNF (IDN)

ABRT (ABT)

TK0NF (T0N)

AMNF (AMN)

Interface CRC Error. CRC=1 indicates a CRC error has occured on the data bus during a Ultra-DMA transfer.

Uncorrectable Data Error. UNC=1 indicates an uncorrectable data error has been encountered.

ID Not Found. IDNF=1 indicates the requested sector's ID field could not be found.

Aborted Command. ABT=1 indicates the requested command has been aborted due to a device status error or an invalid parameter in an output register.

Track 0 Not Found. T0N=1 indicates track 0 was not found during a

Recalibrate command.

Address Mark Not Found. AMN=1 indicates the data address mark has not been found after finding the correct ID field for the requested sector.

11.4.10 Feature Register

This register is command specific. This is used with ACCESS METADATA

STORGAE command and SET FEATURES command.

11.4.11 Sector Count Register

This register contains the number of sectors of data requested to be transferred on a read or write operation between the host and the device. If the value in the register is set to 0, a count of 256 sectors is specified.

If the register is zero at command completion, the command was successful. If not successfully completed, the register contains the number of sectors which need to be transferred in order to complete the request.

The contents of the register are defined otherwise on some commands. These definitions are given in the command descriptions.

11.4.12 Sector Number Register

This register contains the starting sector number for any disk data access for the subsequent command. The sector number is from one to the maximum number of sectors per track.

In LBA mode, this register contains Bits 0-7. At the end of the command, this register is updated to reflect the current LBA Bits 0-7.

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11.4.13 Status Register

7

BSY

6

DRDY

5

DF

Status Register

4

DSC

3

DRQ

2

CORR

1

IDX

0

ERR

This register contains the device status. The contents of this register are updated whenever an error occurs and at the completion of each command.

If the host reads this register when an interrupt is pending, it is considered to be the interrupt acknowledge. Any pending interrupt is cleared whenever this register is read.

If BSY=1, no other bits in the register are valid.

Bit Definitions

BSY

DRDY (RDY)

DF

DSC

DRQ

CORR (COR)

IDX

ERR

Busy. BSY=1 whenever the device is accessing the registers. The host should not read or write any registers when BSY=1. If the host reads any register when BSY=1, the contents of the Status Register will be returned.

Device Ready. RDY=1 indicates that the device is capable of responding to a command. RDY will be set to 0 during power on until the device is ready to accept a command.

Device Fault. DF=1 indicates that the device has detected a write fault condition. DF is set to 0 after the Status Register is read by the host.

Device Seek Complete. DSC=1 indicates that a seek has completed and the device head is settled over a track. DSC is set to 0 by the device just before a seek begins. When an error occurs, this bit is not changed until the Status

Register is read by the host, at which time the bit again indicates the current seek complete status.

When the device enters into or is in Standby mode, this bit is set by device in spite of not spinning up.

Data Request. DRQ=1 indicates that the device is ready to transfer a word or byte of data between the host and the device. The host should not write the

Command register when DRQ=1.

Corrected Data. Always 0.

Index. Always 0.

ERR=1 indicates that an error occurred during execution of the previous command. The Error Register should be read to determine the error type.

The device sets ERR=0 when the next command is received from the host.

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12

General Operation Descriptions

12.1 Reset Response

There are three types of resets in a CompactFlash device: a power-on reset, a hardware reset, and a software reset. There is also a reset called PCMCIA soft reset, which uses bit 7 of Configuration Option

Register. It is treated as a hard reset.

Type

Power On Reset (POR)

Hard Reset (Hardware Reset)

Description

A reset carried out upon device's every power up sequence

A reset initiated by a raising edge of RESET signal (in True IDE mode)

A reset initiated by a falling edge of RESET signal (In PC Card mode)

Soft Reset (Software Reset)

PCMCIA soft reset

A reset initiated by changing bit 2 (SRST) of Device Control

Register as 0, 1 then 0

A reset initiated by changing bit 7 (SRESET) of Configuration

Option Register as 0, 1 then 0. It is equivalent to a hardware reset

Figure 8. 36Reset type

Description

Aborting Host interface

Aborting Device operation

Initialization of hardware

Internal diagnostics

Initialization of task file registers (2)

Initialization of registers at attribute memory

DASP– handshake (3)

PDIAG– handshake (3)

Reverting programmed parameters to power-on default y Logical geometry (number of cylinders/heads/sectors) y Multiple mode y Write cache y Read look-ahead y ECC bytes for Read Long and Write Long y Delayed Write y On-demand prefetch

Byte transfer mode (3)

PIO transfer mode

DMA transfer mode (3)

ABLE mode

Reset Standby timer

POR

O

O

O

O

O

O

O

0

Hard Reset

O

'(1)

O

O

O

O

O

O

O

0

Soft Reset

O

'(1)

X

X

O

X

O

O

'(4)

X

Figure 9. 37Reset Response

Notes:

– - not applicable

O - executed

X - not executed

(1) If the device receives a reset during cached writing, the reset completes after cached writing completes.

(2) Initialized value of task file registers are shown in figure 58 below.

(3) True IDE mode only.

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(4) If the device has received Set Features with feature code CCh prior to a reset, setting is reverted to the power-on default.

12.1.1 Register Initialization

After power on, hard reset, or software reset, the register values are initialized as shown in the following table.

Register

Error

Sector Count

Sector Number

Cylinder Low

Cylinder High

Device/Head

Status

Default Value

Diagnostic Code

01h

01h

00h

00h

00h

50h

Alternate Status

Figure 10. Default Register Values

50h

The meaning of the Error Register diagnostic codes resulting from power on, hard reset or the EXECUTE DEVICE DIAGNOSTICS command are shown in the following table.

Code Description

01h

02h

03h

No error Detected

Formatter device error

Sector buffer error

04h

05h

8xh

Figure 11. Diagnostic Codes

Ecc circuitry error

Controller microprocessor error

Device 1 failed

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12.2 Diagnostic and Reset considerations

For each Reset and Execute Device Diagnostic, the Diagnostic is done as follows:

Power On Reset, Hard Reset

DASP- is read by Device 0 to determine if Device 1 is present. If Device 1 is present Device 0 will read PDIAG- to determine when it is valid to clear the BSY bit and whether Device 1 has powered on or reset without error, otherwise Device

0 clears the BSY bit whenever it is ready to accept commands. Device 0 asserts

DASP- to indicate device activity. If Device 1 is not present, Device 0 does not

Assert DASP- at POR.

Soft Reset

If Device 1 is present Device 0 will read PDIAG- to determine when it is valid to clear the BSY bit and whether Device 1 has reset without any errors, otherwise

Device 0 will reset and clear the BSY bit. DASP- is asserted by Device 0 (and

Device 1 if it is present) in order to indicate device active.

Execute Device Diagnostic

If Device 1 is present, Device 0 will read PDIAG- to determine when it is valid to clear the BSY bit and if Device 1 passed or failed the EXECUTE DEVICE

DIAGNOSTICS command, otherwise Device 0 will execute its diagnostics and then clear the BSY bit. DASP- is asserted by Device 0 (and Device 1 if it is present) in order to indicate the device is active.

In all the above cases: Power on, RESET-, Soft reset, and the EXECUTE DEVICE

DIAGNOSTICS command the Device 0 Error register is shown in the following table.

Device 1 Present?

Yes

Yes

PDIAG- Asserted?

Yes

Yes

Device 0 Passed

Yes

No

Error Register

01h

0xh

Yes

Yes

No

No

Yes

No

81h

8xh

No

No

(not read)

(not read)

Yes

No

01h

0xh

Where x indicates the appropriate Diagnostic Code for the Power on, RESET-, Soft reset, or Device

Diagnostic error.

Figure 12. Reset error register values

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12.3 Power-off considerations

12.3.1 Load/Unload

The product will support a minimum of 300,000 normal load/unloads.

The Load/Unload is a functional mechanism of the HDD. It is controlled by the drive microcode. Specifically, unloading of the heads is invoked by the commands:

Microcode revision: DNxOCxxx (Where x indicates "don't care".)

Command

Standby

Standby Immediate

Sleep

*UL -> Complete

*UL -> Complete

*UL -> Complete

Reset

Soft Reset

Hard Reset

**Rdy

*UL -> **Rdy

*

**

UL means unload

Rdy means interface ready

Figure 13. A Device's behavior by ATA commands

Load/Unload is also invoked as one of the idle modes of the drive.

The specified start/stop life of the product assumes that Load/Unload is operated normally, NOT in emergency mode.

12.3.2 Emergency unload

When HDD power is interrupted while the heads are still loaded, the microcode cannot operate and the normal 3.3/5V power is unavailable to unload the heads. In this case, normal unload is not possible, so the heads are unloaded by routing the back-EMF of the spinning motor to the voice coil. The actuator velocity is greater than the normal case, and the unload process is inherently less controllable without a normal seek current profile.

Emergency unload is intended to be invoked in rare situations. Because this operation is inherently uncontrolled, it is more mechanically stressful than a normal unload.

A single emergency unload operation is more stressful than 100 normal unloads. Use of emergency unload reduces the start/stop life of the HDD at a rate at least 100X faster than that of normal unload, and may damage the HDD.

Warranty is void on a drive that has experienced 3,000 or more emergency unloads.

12.3.3 Required power-off sequence

Problems can occur on most HDDs when power is removed at an arbitrary time.

Examples:

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y y y

Data loss from the write buffer.

If the drive is writing a sector, a partially-written sector with an incorrect ECC block results. The sector contents are destroyed, and reading that sector results in a hard error.

Heads possibly land in the data zone instead of landing zone, depending on the design of the HDD.

You may then turn off the HDD in the following order:

I.

Issue STANDBY IMMEDIATE command. ( STANDBY IMMEDIATE command

II.

can be replaced by STANDBY or SLEEP command )

Wait until Command Complete Status is returned. (It may take up to 350 ms in

III.

typical case)

Terminate power to HDD.

This power-down sequence should be followed for entry into any system power-down state, or system suspend state, or system hibernation state. In a robustly designed system, emergency unload is limited to rare scenarios such as battery removal during operation.

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12.4 Sector Addressing Mode

12.4.1

Logical CHS Addressing Mode

The logical CHS addressing is made up of three fields: the cylinder number, the head number and the sector number. Sectors are numbered from 1 to the maximum value allowed by the current CHS translation mode but can not exceed 255(0FFh). Heads are numbered from 0 to the maximum value allowed by the current CHS translation mode but can not exceed 15(0Fh). Cylinders are numbered from 0 to the maximum value allowed by the current CHS translation mode but cannot exceed 65535(0FFFFh).

When the host selects a CHS translation mode using the INITIALIZE DRIVE

PARAMETERS command, the host requests the number of sectors per logical track and the number of heads per logical cylinder. The device then computes the number of logical cylinders available in requested mode.

The current CHS translation mode, as well as the default CHS translation mode, is returned by the Identify Device Information.

12.4.2

LBA Addressing Mode

Logical sectors on the device shall be linearly mapped with the first LBA addressed sector (sector 0) being the same sector as the first logical CHS addressed sector ( cylinder 0, head 0, sector 1). Irrespective of the logical CHS translation mode currently in effect, the LBA address of a given logical sector does not change. The following is always true:

LBA = ( (cylinder * heads_per_cylinder + heads)

* sectors_per_track ) + sector - 1 where heads_per_cylinder and sectors_per_track are the current translation mode values.

On LBA addressing mode, the LBA value is set to the following register.

Device/Head

Cylinder High

Cylinder Low

Sector Number

<---

<---

<---

<---

LBA bits

LBA bits

LBA bits

LBA bits

27-24

23-16

15- 8

7- 0

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12.5 Power Management Feature

The power management feature set permits a host to modify the behavior in a manner which reduces the power required to operate. The power management feature set provides a set of commands and a timer that enables a device to implement low power consumption modes.

implement the following set of functions.

I.

A Standby timer

II.

IDLE command

III.

IDLE IMMEDIATE command

IV.

STANDBY command

V.

STANDBY IMMEDIATE command

12.5.1 Power Mode

Standby

Mode

Idle Mode

Active Mode

The device interface is capable of accepting commands, but as the media may not immediately accessible, there is a delay while waiting for the spindle to reach operating speed.

Refer to the section of Adoptive Battery Life Extender Feature.

The device is in execution of a command or accessing the disk media with read look-ahead function or write cache function.

12.5.2 Power Management Commands

The CHECK POWER MODE command allows a host to determine if a device is currently in, going to or leaving standby mode.

The IDLE and IDLE IMMEDIATE commands move a device to idle mode immediately from the active or standby modes. The IDLE command also sets the standby timer count and starts the standby timer.

The STANDBY and STANDBY IMMEDIATE commands move a device to standby mode immediately from the active or idle modes. The STANDBY command also sets the standby timer count.

12.5.3 STANDBY command completion timing

I.

Confirm the completion of writing cached data in the buffer to media

II.

Unload heads on the ramp

III.

Set DRDY bit and DSC bit in Status Register

IV.

Set INTRQ (completion of the command)

V.

Activate the spindle break to stop the spindle motor

VI.

Wait until spindle motor is stopped

VII.

Perform post process

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12.5.4 Standby timer

The standby timer provides a method for the device to automatically enter standby mode from either active or idle mode following a host programmed period of inactivity.

If the device is in the active or idle mode, the device waits for the specified time period and if no command is received, the device automatically enters the standby mode.

If the value of SECTOR COUNT register on IDLE command or STANDBY command is set to 00h, the device will automatically set the standby timer to 109 minutes. If the advanced power management level is less than 80h, which is power-on default, the transition timing to enter Standby mode is determined by either standby timer or

Adaptive Battery Life Extender algorithm, whichever meets the condition first.

12.5.5 Status

In the active, idle and standby modes, the device shall have RDY bit of the status register set. If BSY bit is not set, device shall be ready to accept any command.

12.5.6 Interface Capability for Power Modes

Each power mode affects the physical interface as defined in the following table:

Mode

Active

Idle

Standby

Sleep

Figure 14. Power conditions

BSY

x

0

0

0

RDY

x

1

1

1

Interface active

Yes

Yes

Yes

Yes

Media

Active

Active

Inactive

Inactive

Ready(RDY) is not a power condition. A device may post ready at the interface even though the media may not be accessible.

12.5.7 Initial Power Mode at Power On

The device power up in Standby mode.

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12.6 Advanced Power Management (Adaptive Battery Life

Extender 3) Feature

This feature provides power saving without performance degradation. The Adaptive

Battery Life Extender 3 (ABLE-3) technology intelligently manages transition among power modes within the device by monitoring access patterns of the host.

This technology has three idle modes; Performance Idle mode, Active Idle mode, and

Low Power Idle mode.

This feature allows the host to select an advanced power management level. The advanced power management level is a scale from the lowest power consumption setting of 01h to the maximum performance level of FEh. Device performance may increase with increasing advanced power management levels. Device power consumption may increase with increasing advanced power management levels. The advanced power management levels contain discrete bands, described in the section of

SET FEATURE command in detail.

This feature set uses the following functions: y

A SET FEATURES subcommand to enable Advanced Power Management y

A SET FEATURES subcommand to disable Advanced Power Management

The Advanced Power Management feature is independent of the Standby timer setting.

If both Advanced Power Management level and the Standby timer are set, the device will goto the Standby state when the timer times out or the device's Advanced Power

Management algorithm indicates that it is time to enter the Standby state.

The IDENTIFY DEVICE response word 83, bit 3 indicates that Advanced Power

Management feature is supported if set. Word 86, bit 3 indicates that Advanced Power

Management is enabled if set.

Word 96, bits 7-0 contain the current Advanced Power Management level if Advanced

Power Management is enabled.

12.6.1 Performance Idle mode

This mode is usually entered immediately after Active mode command processing is complete, instead of conventional idle mode. In Performance Idle mode, all electronic components remain powered and full frequency servo remains operational. This provides instantaneous response to the next command. The duration of this mode is intelligently managed as described below.

12.6.2Active Idle mode

In this mode, power consumption is 45-55% less than that of Performance Idle mode.

Additional electronics are powered off, and the head is prked near the mid-diameter without servoing. Recovery time to Active mode is about 10ms.

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12.6.3 Low Power Idle mode

Power consumption is 55%-65% less than that of Performance Idle mode. The heads are unloaded on the ramp, however the spindle is still rotated at the full speed. Recovery time to Active mode is about 300ms.

12.6.4 Transition Time

The transition time is dynamically managed by users recent access pattern, instead of fixed times. The ABLE-3 algorithm monitors the interval between commands instead of the command frequency of ABLE-2. The algorithm supposes that next command will come with the same command interval distribution as the previous access pattern. The algorithm calculates the expected average saving energy and response delay for next command in several transition time case based on this assumption. And it selects the most effective transition time with the condition that the calculated response delay is shorter than the value calculated from the specifid level by SET FEATURE ENABLE

ADAPTIVE POWER MANAGEMENT command.

The optimal time to enter Active Idle mode is variable depending on the users recent behavior. It is not possible to achieve the same level of Power savings with a fixed entry time into Performance Idle because every users data and access pattern is different. The optimum entry time changes over time.

The same algorithm works for entering into Low Power Idle mode and Standby mode, which consumes less power but need more recovery time switching from this mode to

Active mode.

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12.7 Seek Overlap

The drive provide accurate seek time measurement method. The SEEK command is usualy used to measure the device seek time by accumulating execution time for a number of SEEK commands. With typical implementation of the SEEK command, this measurement must including the device and host command overhead. To eliminate this overhead, overlap the SEEK command as described below.

The first SEEK command completes before the actual seek operation is over. Then device can receive the next SEEK command from the host but actual seek operation for the next SEEK command starts right after the actual seek operation for the first SEEK command is completed. In other words, the execution of two SEEK commands overlaps excluding the actual seek operation.

With this overlap, total elapsed time for a number of SEEK commands is the total accumulated time for the actual seek operation plus one pre and post overhead. When the number of seeks is large, just this one overhead can be ignored.

(1) With overlap

Host process

Device process

Seek operation

Overhead

A

Total time = (n-1) * (Seek operation) + A + B

(2) Without overlap

Host process

Device process

Seek operation

Overhead A B+A

Total time = n * (Seek operation + A + B)

Figure 15. Seek overlap

B+A

B

B

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12.8 Write Cache Function

Write cache is a performance enhancement whereby the device reports completion of the write command (WRITE SECTORS, WRITE MULTIPLE, WRITE SECTORS

WITHOUT ERASE, WRITE MULTIPLE WITHOUT ERASE, WRITE DMA, WRITE

VERIFY ) to the host as soon as the device has received all of the data into its buffer.

The device assumes responsibility to write the data subsequently onto the disk.

y

While writing data after completed acknowledgment of a write command, soft reset or hard reset does not affect its operation. But power off terminates writing operation immediately and unwritten data are to be lost.

y

FLUSH CACHE, SOFT RESET, STANDBY, STANDBY IMMEDIATE and

SLEEP are executed after the completion of writing to disk media on enabling write cache function. So the host system can confirm the completion of write cache operation by issuing FLUSH CACHE command, SOFT RESET, STANDBY command, STANDBY IMMEDIATE command and SLEEP command, and then, by confirming its completion.

y

The retry bit of WRITE SECTORS is ignored when write cache is enabled.

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12.9 Reassign Function

The Reassign Function is used with read commands and write commands. The sectors of data for reassignment are prepared as the spare data sector. The number of the spare sector's entry is 2026 entries. The one entry can register 256 consecutive sectors maximally.

This reassignment information is registered internally, and the information is available right after completing the reassign function. Also the information is used on the next power on reset or hard reset.

If the number of the spare sector reaches 0 sector, the reassign function will be disabled automatically.

The spare tracks for reassignment are located at regular interval. As a result of reassignment, the physical location of logically sequenced sectors will be dispersed.

12.9.1 Auto Reassign Function

The sectors that show some errors may be reallocated automatically when specific conditions are met. The spare sectors for reallocation are located at reserved area. The conditions for auto-reallocation are described below.

Non recovered write errors

When a write operation can not be completed after the Error Recovery Procedure(ERP) is fully carried out, the sector(s) are reallocated to the spare location. An error is reported to the host system only when the write cache is disabled and the auto reallocation fails.

If the number of available spare sectors reaches 16 sectors, the write cache function will be disabled automatically.

If the command is without retry and the write cache function is disabled, the auto reassign function is not invoked.

Non recovered read errors

When a read operation fails after defined ERP is fully carried out, a hard error is reported to the host system. This location is registerred internally as a candidate for the reallocation. When a registerred location is specified as a target of a write operation, a sequence of media verification is performed automatically. When the result of this verification meets the criteria, this sector is reallocated.

Recovered read errors

When a read operation for a sector failed once then recovered at the specific ERP step, this sector of data is reallocated automatically. A media verification sequence may be run prior to the relocation according to the pre-defined conditions.

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12.10

Metadata Storage Function

Metadata storage is a small, non-volatile user area which address space is logically separated from the main storage. The host can use metadata storage to store information on the data contents itself, e.g, available free blocks, device properties, or any summary information. The first implementation of metadata storage in the drive provides just

32-bytes, but the command set design does not preclude any future enhancement.

The metadata concept itself is not bound to any specific physical medium, although the drive's metadata storage has one important property for rotating devices: the host can access metadata without rotating the disk. This medium property is expected to supplement the applicability of the drive for the digital appliance.

12.10.1

Meatadata Storage Command Set

All metadata commands use command code B8h. Each command is specified as a subcommand of command B8h with Features Register containing the subcommand code. Cylinder Low and High registers are used to specify metadata block address in

512-byte unit, which ranges from 0 to [metadata capacity in bytes + 2] / 512. The

H itachi

driv e

provides 32 bytes of metadata capacity; thus the valid address for the

H itachi

driv e

is 0000h only. Sector Count Register is used to specify the number of blocks transferred between the host and the device. Sector Number Register is reserved and must be 00h for future use.

Inquiry Metadata Media, which uses subcommand code 02h, returns 1 sector of data containing information on the device's metadata storage. Read Metadata, which uses subcommand code 03h, can read metadata contents. Inquiry Metadata Media and Read

Metadata return a status word that indicates whether the main storage contents have been modified since the last Write Metadata. The host can use the status word to check if metadata is not consistent with the main storage contents. Write Metadata, which uses subcommand code 04h. can write metadata. The device does not interpret metadata itself, though it is recommended the first 10 bytes of metadata be a unique number that signifies the identity of remaining.

In addition to define new command set, Identify Device is enhanced to use word 161 as a capability bitstrip for CF command set extensions, which indicates support for the metadata command set.

Details of command description are refered to "6.5 CF-ATA Command Description".

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13 Command Protocol

The commands are grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined below.

For all commands, the host must first check if BSY=1, and should proceed no further unless and until BSY=0. For all commands, the host must also wait for RDY=1 before proceeding.

A device must maintain either BSY=1 or DRQ=1 at all times until the command is completed. The INTRQ signal is used by the device to signal most, but not all, times when the BSY bit is changed from 1 to 0 during command execution.

A command shall only be interrupted with a hardware or software reset. The result of writing to the Command register while BSY=1 or DRQ=1 is unpredictable and may result in data corruption. A command should only be interrupted by a reset at times when the host thinks there may be a problem, such as a device that is no longer responding.

Interrupts are cleared when the host reads the Status Register, issues a reset, or writes to the Command Register.

13.1 Data In Commands

These commands are: y y y y

Identify Device

Read Buffer

Read Long

Read Multiple y

Read Sectors

Execution includes the transfer of one or more 512 byte (>512 bytes on Read Long) sectors of data from the device to the host.

1.

2.

3.

4.

The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and

Device/Head Registers.

The host writes the command code to the Command Register.

For each sector (or block) of data to be transferred:

a.

The device sets BSY=1 and prepares for data transfer.

b.

When a sector (or block) of data is available for transfer to the host, the device sets BSY=0, sets

DRQ=1, and interrupts the host.

c.

In response to the interrupt, the host reads the Status Register.

d.

e.

The device clears the interrupt in response to the Status Register being read.

The host reads one sector (or block) of data via the Data Register.

f.

The device sets DRQ=0 after the sector (or block)has been transferred to the host.

For the Read Long command:

a.

The device sets BSY=1 and prepares for data transfer.

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e.

f.

b.

c.

d.

When the sector of data is available for transfer to the host, the device sets BSY=0, sets DRQ=1, and interrupts the host.

In response to the interrupt, the host reads the Status Register.

The device clears the interrupt in response to the Status Register being read.

The host reads the sector of data including ECC bytes via the Data Register.

The device sets DRQ=0 after the sector has been transferred to the host.

The Read Multiple command transfers one block of data for each interrupt. The other commands transfer one sector of data for each interrupt.

Note that the status data for a sector of data is available in the Status Register before the sector is transferred to the host.

If the device detects an invalid parameter, then it will abort the command by setting

BSY=0, ERR=1, ABT=1, and interrupting the host.

If an error occurs, the device will set BSY=0, ERR=1, and DRQ=1. The device will then store the error status in the Error Register, and interrupt the host. The registers will contain the location of the sector in error. The errored location will be reported with

CHS mode or LBA mode, the mode is decided by mode select bit (bit 6) of

Device/Head register on issuing the command.

If an Uncorrectable Data Error (UNC=1) occurs, the defective data will be transferred from the media to the sector buffer, and will be available to be transferred to the host, at the host's option. In case of Read Multiple command, the host should complete transfer the block which includes the error from the sector buffer and terminate whatever kind of type of error occurred.

All data transfers to the host through the Data Register are 16 bits, except for the ECC bytes, which are 8 bits.

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13.2 Data Out Commands

y y y y y y

These commands are:

Format Track

Write Buffer

Write Long

Write Multiple

Write Sectors

Write Verify

Execution includes the transfer of one or more 512 byte (>512 bytes on Write Long) sectors of data from the host to the device.

1.

2.

3.

4.

5.

The host writes any required parameters to the Features, Sector Count, Sector Number, Cylinder, and

Device/Head Registers.

The host writes the command code to the Command Register.

The device sets BSY=1.

For each sector (or block) of data to be transferred:

a.

The device sets BSY=0 and DRQ=1 when it is ready to receive a sector (or block).

b.

c.

The host writes one sector (or block) of data via the Data Register.

The device sets BSY=1 after it has received the sector (or block).

d.

When the device has finished processing the sector (or block), it sets BSY=0, and interrupts the host.

In response to the interrupt, the host reads the Status Register.

e.

f.

The device clears the interrupt in response to the Status Register being read.

For the Write Long command:

a.

The device sets BSY=0 and DRQ=1 when it is ready to receive a sector.

b.

c.

The host writes one sector of data including ECC bytes via the Data Register.

The device sets BSY=1 after it has received the sector.

d.

After processing the sector of data the device sets BSY=0 and interrupts the host.

e.

f.

In response to the interrupt, the host reads the Status Register.

The device clears the interrupt in response to the Status Register being read.

The Write Multiple command transfers one block of data for each interrupt. The other commands transfer one sector of data for each interrupt.

If the device detects an invalid parameter, then it will abort the command by setting

BSY=0, ERR=1, ABT=1, and interrupting the host.

If an uncorrectable error occurs, the device will set BSY=0 and ERR=1, store the error status in the Error Register, and interrupt the host. The registers will contain the location of the sector in error. The errored location will be reported with CHS mode or

LBA mode. The mode is decided by mode select bit (bit 6) of Device/Head register on issuing the command.

All data transfers to the device through the Data Register are 16 bits, except for the

ECC bytes, which are 8 bits.

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13.3

Non-Data Commands

y y y y y y y y y y y y y y y y y y y

These commands are:

Check Power Mode

Enable/Disable Delayed Write

Erase sectors

Execute Device Diagnostic

Flush Cache

Format Unit

Idle

Idle Immediate

Initialize Device Parameters

Read Verify Sectors

Recalibrate

Security Erase Prepare

Seek

Sense condition

Set Features

Set Multiple Mode

Sleep

Standby

Standby Immediate

Execution of these commands involves no data transfer.

I.

II.

III.

IV.

V.

VI.

The host writes any required parameters to the Features, Sector Count, Sector

Number, Cylinder, and Device/Head Registers.

The host writes the command code to the Command Register.

The device sets BSY=1.

When the device has finished processing the command, it sets BSY=0, and interrupts the host.

In response to the interrupt, the host reads the Status Register.

The device clears the interrupt in response to the Status Register being read.

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13.4 DMA Data Transfer Commands

The drive supports DMA Data Transfer Commands ONLY in True IDE mode.

These commands are: y y

Read DMA

Write DMA

Data transfer using DMA commands differ in two ways from PIO transfers: y y data transfers are performed using the slave-DMA channel no intermediate sector interrupts are issued on multi-sector commands

Initiation of the DMA transfer commands is identical to the Read Sector or Write Sector commands except that the host initializes the slave-DMA channel prior to issuing the command.

The interrupt handler for DMA transfers is different in that: y y no intermediate sector interrupts are issued on multi-sector commands the host resets the DMA channel prior to reading status from the device.

The DMA protocol allows high performance multi-tasking operating systems to eliminate processor overhead associated with PIO transfers.

I.

II.

III.

IV.

V.

Host initializes the slave-DMA channel

Host writes any required parameters to the Features, Sector Count, Sector Number,

Cylinder and Device/Head registers.

Host writes command code to the Command Register

The device sets DMARQ when it is ready to transfer any part of the data.

Host transfers the data using the DMA transfer protocol currently in effect.

When all of the data has been transferred, the device generates an interrupt to the

VI.

VII.

host.

Host resets the slave-DMA channel

VIII.

Host reads the Status Register and, optionally, the Error Register

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13.4.1 Access Metadata Storage - B8h

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

V V V V V V

1

-

V

Sector Count

0 0 0 0 0 0 0

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 0 1 1 1 0 0

0

-

V

1

-

-

-

-

0

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

V

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

0

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 0

1

IDX

0

0

ERR

V

Figure 16. Access Metadata Storage Command (B8h)

This command accesses metadata storage area.

Following subcommand are supported and specified with Feature Register value.

Feature

02h

03h

04h

Operation

Inquiry Metadata Storage

Read Metadata Storage

Write Metadata Storage

Figure 17. Supported subcommand

Inquiry Metadata Storage (subcommand code - 02h) enables host to read capacity of the device's Metadata Storage along with information associated with the charasteristics of the

Metadata Storage. The data returned from the device is in following format.

word

0

1

2

data

0001h

0000h

000xh

Description

data format revision media property

bit 0: 1 = rotating, 0 = silicon

bit 1-15: reserved media status word bit 0: 1 = content changed

0 = content not changed

bit 1-15: reserved

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3

4

5

6

7 - 255

1-32

33-255

0020h

0000h xxxxh xxxxh

0000h xxxxh

0000h metadata capacity in bytes (low) metadata capacity in bytes (high) number of sectors per device(low) number of sectors per device(high) reserved

Figure 18. Data format of Inquiry Metadata Storage

Reserved bits and words are 0. Bit 0 of media status word (word 2) indicates whether the main storage contents have been changed by any commands (e.g, Write Sectors, Format Track, Erase

Sectors etc.). Media status word is also returned by Read Metadata Storage as a header part of metadata.

Read Metadata Storage enables the host to read from device's metadata storage. Cylinder Low and Cylinder High Registers are used to specify the metadata block address, which can range from 0 to ([metadata capacity in bytes + 2] / 512). Sector Count Register is used to specify the number of sectors to transfer. For the microdrive, Cylinder Low and Cylinder High Registers must be 00h, Sector Count Register must be 01h because of the total capacity of metadata storage (32 bytes). The first block of metadata contains media status word that is also returned by Inquiry Metadata Media. Both words represent the identical information.

word

0

data

000xh

Description

media status word bit 0: 1 = content changed

0 = content not changed

bit 1-15: reserved metadata (32 bytes)

Reserved

Figure 19. Data format of Read Metadata Storage

Reserved words would be used if the device has more than 32 bytes of metadata capacity. The host should not assume capacity of metadata to be 32 bytes. The number is merely H itachi

Microdrive's implementation.

Write Metadata enables the host to write to device's metadata storage. Usage of Cylinder Low,

Cylinder High and Sector Count Registers are the same as Read Metadata. Upon successful completion of Write Metadata, media status is reset to "unchanged" condition and subsequent media status word (by either Inquiry Metadata Media or Read Metadata) will show bit 0 cleared until the device receives any commands that changes the main storage contents. The commands that affect media status are: Write Sectors, Write Sectors without Erase, Write Long, Write

Verify, Write Multiple, Write Multiple without Erase, Erase Sectors and Format Track. (** note: the list may grow if we get new commands that change the media contents)

word

0

1-32

33-255

data

xxxxh xxxxh

0000h

description

ignored metadata (32 bytes) reserved

Figure 20. Data format of Write Metadata Storage

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Word 0 is a pad and metadata starts with the word 1. Reserved words would be used if the device has more than 32 bytes of metadata capacity. The host should not assume capacity of metadata to be 32 bytes. The number is merely Hitachi Microdrive's implementation.

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13.4.2 Check Power Mode (E5h/98h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 0 0 1

1

-

-

-

-

-

-

-

0

-

-

-

-

-

-

-

0 1

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

V V V V V V V

0

-

V

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

0

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 0

1

IDX

0

0

ERR

V

Figure 21. Check Power Mode Command (E5h/98h)

The Check Power Mode command will report whether the device is spun up and the media is available for immediate access.

Sector Count

Input Parameters From The Device

The power mode code. The command returns FFh in the Sector Count Register if the spindle motor is at speed and the device is not in Standby or Sleep mode.

Otherwise, the Sector Count Register will be set to 0.

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13.4.3 Execute Device Diagnostics (90h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 -

Command

1 0 0 1 0 0

1

-

-

-

-

-

-

-

0

-

-

-

-

-

-

-

0 0

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

V

5

0

V

Error Register

4

IDN

3

0

2

ABT

V V V

1

T0N

V

0

AMN

V

7

BSY

0

6

RDY

0

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 0

1

IDX

0

0

ERR

0

Figure 22. Execute Device Diagnostic Command (90h)

The Execute Device Diagnostic command performs the internal diagnostic tests implemented by the device. The results of the test are stored in the Error Register.

The normal Error Register bit definitions do not apply to this command. Instead, the register contains a diagnostic code. See "Diagnostic Codes" on page ??71 for the definition.

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13.4.4 Erase Sectors (C0h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

V V V V V V V

0

-

-

V

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

1 L 1 D H H H H

Command

1 1 0 0 0 0 0 0

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

V V V V V V V

0

-

V

Sector Number

V V V V V V V V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

0

6

UNC

V

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

V

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 23. Erase Sectors Command (C0h)

The Erase sectors command fills specified sectors with 00h pattern.

Note: H itachi

Microdrive does not need pre-erase in advance of a write operation.

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13.4.5 Flush Cache (E7h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 0 0 1

1

-

-

-

-

-

-

-

0

-

-

-

-

-

-

-

1 1

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

Figure 24. Flush Cache Command (E7h)

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

This command causes the device to complete writing data from its cache.

The device returns a status, RDY=1 and DSC=1 (50h), after following sequence. y y

Data in the write cache buffer is written to disk media.

Return a successfully completion.

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13.4.6 Format Track (50h: Vendor Specific)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

V V V V V V

Cylinder Low

V V V V V V

Cylinder High

V V V V V V

Device/Head

1 L 1 D H H

Command

0 1 0 1 0 0

1

-

-

-

0

-

-

-

V V

V V

V V

H H

0 0

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

V V V V V V V

0

-

-

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

V V 0

1

IDX

0

0

ERR

V

Figure 25. Format Track (50h)

The Format Track command formats a single logical track on the device. Each good sector of data on the track will be initialized to zero with write operation. At this time, whether the sector of data is initialized correctly is not verified with read operation. Any data previously stored on the track will be lost.

The host transfers a sector of data containing a format table to the device. The format table should contain two bytes for each sector on the track to be formatted.The structure of format table is shown in "Format track data field format

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" on page 99. The first byte should contain a descriptor value and the second byte should contain the sector number. The descriptor value should be 0 for a good sector, and any other descriptor value will cause an aborted error. The remaining bytes of the sector following the format table are ignored.

Since device performance is optimal at 1:1 interleave, and the device uses relative block addressing internally, the device will always format a track in the same way no matter what sector numbering is specified in the format table.

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Sector Number

Cylinder High/Low

H

Output Parameters To The Device

In LBA mode, this register specifies LBA address bits 0 - 7 to be formatted.

(L=1)

The cylinder number of the track to be formatted. (L=0)

In LBA mode, this register specifies LBA address bits 8 - 15 (Low), 16 - 23

(High) to be formatted. (L=1)

The head number of the track to be formatted. (L=0)

In LBA mode, this register specifies LBA address bits 24 - 27 to be formatted.

(L=1)

Sector Number

Cylinder High/Low

H

Error

Input Parameters From The Device

In LBA mode, this register specifies current LBA address bits 0-7. (L=1)

In LBA mode, this register specifies current LBA address bits 8 - 15 (Low), 16 -

23 (High)

In LBA mode, this register specifies current LBA address bits 24 - 27. (L=1)

The Error Register. An Abort error (ABT=1) will be returned under the following conditions: y The descriptor value does not match the certain value. (except 00h)

In LBA mode, this command formats a single logical track including the specified LBA.

Descriptor : 00h

Explanation for descriptor

The sector of data will be initialized to 00h.

Byte Data Description

0

1

2

3

4

5 xxh

00h xxh

01h xxh

02h descriptor value for sector number 00h sector number descriptor value for sector number 01h sector number descriptor value for sector number 02h sector number

:

N*2

N*2+1

: xxh

N descriptor value for sector number N sector number (last sector for the track)

N*2+2

N*2+3

:

00h

00h

: remainder of buffer filled with 00h

510 00h

511 00h

Descriptor : 00h - Format sector as good sector

Figure 26. Format track data field format

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13.4.7Format Unit (F7h: Vendor Specific)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

V V V V V V

1

-

V

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 1 0 1 1

0

-

V

-

-

-

-

-

1

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

V

3

0

0

2

ABT

V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

0

Status Register

4

DSC

V

3

DRQ

-

2

COR

0

1

IDX

0

0

ERR

V

Figure 27. Format Unit (F7h)

The Format Unit command initializes all user data sectors after merging reassigned sector location into the defect information of the device and clearing the reassign information. Both new reassign information and new defect information are available right after this command completion, and are also used on next power on reset or hard reset. Both previous information are erased from the device by this command.

Note that the Format Unit command initializes from LBA 0 to MAX LBA.

The Security Erase Prepare command should be completed immediately prior to the Format

Unit command. If the device receives a Format Unit command without a prior Security Erase

Prepare command the device aborts the Format Unit command.

If Feature register is NOT 11h, the device returns Abort error to the host.

This command does not request to data transfer.

Feature

Output Parameters To The Device

11H Merge reassigned location into the defect information

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13.4.8Identify Device (ECh)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 0 1 1

1

-

-

-

-

-

-

-

0

-

-

-

-

-

-

-

0 0

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 0

1

IDX

0

0

ERR

V

Figure 28. Identify Device Command (ECh)

The Identify Device command requests the device to transfer configuration information to the host. The device will transfer a sector to the host containing the information in "" on page

1070TBD.

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68

82

83

84

85

86

87

88

91

129

130

131

160

161

59

60-61

63

64

65

66

Word

Address

0

1

2

3

6

7-8

10-19

22

23-26

27-46

47

49

51

52

53

54

55

56

57-58

Default

Value

848Ah

Note.1

0000h

0010h

003Fh

Note.1

Note.2

0004h

XXXX

Note.3

8020h

0F00h

0200h

0200h

0007h

XXXXh

XXXXh

XXXXh

XXXXh

01XXh

Note.1

0X07h

0003h

0078h

0078h

0078h

7068h

500Ch

4000h

7048h

100Ch

4000h

0007h

4060h

0002h

0000h

0001h

8100h

8001h

Total

Bytes

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

4

2

2

2

2

20

2

8

40

2

2

2

2

4

2

2

2

2

2

2

2

2

2

Data Field Type Information

General configuration - signature for the CompactFlash

Storage Card

Default number of cylinders

Reserved

Default number of heads

Default number of sectors per track

Number of sectors per card (Word 7 = MSW, Word 8 =

LSW)

Serial number in ASCII (Right justified)

# of ECC bytes passed on Read/Write Long Commands

Vendor specific Firmware revision in ASCII. Big Endian

Byte Order in Word

Model number in ASCII (Left Justified) Big Endian Byte

Order in Word

Maximum number of sectors on Read/Write Multiple command

Capabilities

PIO data transfer cycle timing mode

DMA data transfer cycle timing mode

Translation parameters are valid

Current numbers of cylinders

Current number of heads

Current sectors per track

Current capacity in sectors (LBAs)(Word 57 = LSW,

Word 58 = MSW)

Multiple sector setting

Total number of sectors addressable in LBA Mode

Multiword DMA Transfer Capability

Flow Control PIO Transfer modes supported

Minimum Multiword DMA Transfer Cycle Time

Manufacturer's Recommended Multiword DMA Transfer

Cycle Time

Minimum PIO Transfer Cycle Time with IORDY Flow

Command Set supported

Command Set supported

Commad Set/Feature supported Extention

Command Set/Feature Enabled

Command Set/Feature Enabled

Command Set/Feature Enabled

Ultra DMA Transfer Capability

Current Advanced Power Management Level

Current Set Features Option, Bit Assignment

Reassigned Sectors

Initial Power mode Selection, Bit Assignment

Power requirement description

CF command set Extentions

Figure 29. Word address and data field type information

Note.1 See Logical layout in the next page

Note.2. The device has 8 characters unique serial number..

Note.3.See Model number description in the next page

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word 0 : General Configuration

This field informs the device is a CompactFlash Storage Card.

word 1 : Default Number of Cylinders word 2 : Default Number of Heads word 6 : Default Number of Sectors per Track word 7-8 : Number of Sectors per Card

The default logical parameter of the device is,

Description

Logical Layout

Number of Heads

Number of Sectors/Track

Number of Cylinders

Number of Sectors

Total Logical Data Bytes

3K4-4

16

7936

7999488

4095737856

Figure 30. Logical parameter of the device

3K4-2

16

3968

3999744

2047868928

word 10 - 19 : Memory Card Serial Number

The contents of this field are right justified and padded with spaces (20h).

word 22 : ECC Count

This field defines the number of ECC bytes used on each sector in the Read and Write Long commands.

word 23 - 26 : Firmware Revision

This field contains the revision of the firmware for the Hitachi Microdrive.

word 27 - 46 : Model Number

This field contains the model number for this product and is left justified and padded with spaces (20h).

Model Number

Hitachi Microdrive 3K4-4

Hitachi Microdrive 3K4-2

Figure 31. Model Number

HMS360404D5CF00

HMS360402D5CF00

word 47 : Read/Write Multiple Sector Count

The even byte value of this field contains the maximum number of sectors that can be read or written per interrupt using the Read Multiple or Write Multiple commands.

word 49 : Capabilities

Bit 13 = 0 : Standby timer operation is Hitachi specific

Bit 11 = 1 : IORDY supported

Bit 10 = 1 : IORDY can be disabled

Bit 9 = 1: LBA mode supported

Bit 8 = 1: DMA transfer supported (True IDE mode ONLY)

word 51 : PIO Data Transfer Cycle Timing Mode

This field defines the mode for PIO data transfer.

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word 52 : DMA Data Transfer Cycle Timing Mode

This field defines the mode for DMA data transfer.

word 53 : Translation Parameters are Valid

Bit 0 of this field is set to 1 indicating that word 54 to 58 are valid and reflect the current number of cylinders, heads and sectors. Bit 1 of this field is set to 1 indicating the device supports PIO mode 4, thus word 64 to 70 are valid. Bit 2 of this field is set to 1 indicating word 88 is valid.

word 54 - 56 : Current Number of Cylinders, Heads, Sectors/Track

These fields contains the current number of user addressable Cylinders, Heads, and Sectors/Track in the current translation mode.

word 57 - 58 : Current Capacity

This field contains the product of the current cylinders times heads times sectors.

word 59 : Multiple Sector Setting

This field contains a validity flag in the odd byte and the current number of sectors that can be transferred per interrupt for R/W Multiple in the even byte. The odd byte is always 01h, which indicates that the even byte is always valid.

The even byte value depends on the value set by the Set Multiple command. The even byte of this word by default contains a 00h, which indicates that R/W Multiple commands are not valid.

word 60-61 : Total Sectors Addressable in LBA Mode

This field contains the number of sectors addressable for the card in LBA mode only.

word 63 : Multiword DMA Transfer Capability

This field contains the capability of Multiword DMA Transfer. The low order byte identifies by bit all of the Modes which are supported, e.g., if Mode 0 is supported, bit 0 is set to one. The high order byte contains a single bit set to indicate which mode is active supported, e.g., if Mode 0 is active, bit 0 is set to one.

word 64 : Flow Control PIO Transfer modes supported

Bits 7 through 0 of this field is defined as the Advanced PIO Data Transfer Supported Field. This field is bit significant. Any number of bits may be set in this field by the device to indicate which Advanced PIO

Modes it is capable of supporting.

Of these bits, bits 7 through 2 are Reserved for future Advanced PIO Modes. Bit 0, if set, indicates that the device supports PIO Mode 3. Bit 1, if set, indicates that the device supports PIO Mode 4.

Note : For backwards compatibility with BIOSs written before Word 64 was defined for advanced modes, a device reports in Word 51 the highest original PIO mode (i.e. PIO mode 0, 1, or 2) it can support.

word 65 : Minimum Multiword DMA Transfer Cycle Time

This field is defined as the Minimum Multiword DMA Transfer Cycle Time Per Word. This field defines, in nanoseconds, the minimum cycle time that the device can support when performing

Multiword DMA transfers on a per word basis.

word 66 : Manufacturer's Recommeded Multiword DMA Transfer Cycle Time

This field is defined as the Device Recommended Multiword DMA Transfer Cycle Time. This field defines, in nanoseconds, the minimum cycle time per word during a single sector host transfer while performing a multiple sector READ DMA or WRITE DMA command over all locations on the media under nominal conditions. If a host runs at a faster cycle rate by operating at a cycle time of less than this value, the device may negate DMARQ for flow control. The rate at which DMARQ is negated could

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result in reduced throughput despite the faster cycle rate. Transfer at this rate does not ensure that flow control will not be used, but implies that higher performance may result.

word 68 : Minimum PIO Transfer Cycle Time with IORDY Flow Control

This field is defined as the Minimum PIO Transfer With IORDY Flow Control Cycle Time. This field defines, in nanoseconds, the minimum cycle time that the device can support while performing data transfers while utilizing IORDY flow control.

word 82 - 84 : Command Set Supported

Words 82, 83, and 84 indicate features/command sets supported. Bits 1 through 13 of word 83 and bits 0 through 13 of word 84 are reserved.

Bit 3 of word 82 is set to one indicating the device supports the Power Management feature set .

Bit 5 of word 82 is set to one indicating the device supports write cache.

Bit 6 of word 82 is set to one indicating the device supports look-ahead.

Bit 12 of word 82 is set to one indicating the device supports the Write Buffer command.

Bit 13 of word 82 is set to one indicating the device supports the Read Buffer command.

Bit 14 of word 82 is set to one indicating the device supports the NOP command.

Bit 2 of word 83 is set to one indicating the device supports the CFA feature set.

Bit 3 of word 83 is set to one indicating the device supports the Advanced Power Management feature set.

Bit 12 of word 83 is set to one indicating the device supports Flush Cache command.

Bit 14 of word 83 is set to one.

Bit 14 of word 84 is set ot one.

word 85 - 87 : Command Set/Feature Enabled

Words 85, 86, and 87 indicate features/command sets enabled. Bits 1 through 15 of word 86 are reserved.

Bits 0-13 of word 87 are reserved.

Bit 3 of word 85 is set to one, if the Power Management feature set has been enabled.

Bit 5 of word 85 is set ot one, if the write cache has been enabled.

Bit 6 of word 85 is set to one, if the look-ahead has been enabled.

Bit 12 of word 85 is set to one, if the Write Buffer command has been enabled.

Bit 13 of word 85 is set to one, if the Read Buffer command has been enabled.

Bit 14 of word 85 is set to one, if the NOP command has been enabled.

Bit 2 of word 86 is set to one, if the CFA feature set has been enabled.

Bit 3 of word 86 is set to one, if the Advanced Power Management feature set has been enabled via the

Set Features command.

Bit 12 of word 86 is set to one indicating the device supports Flush Cache command.

Bit 14 of word 87 is set to one.

word 88 : Ultra DMA Transfer Capability

This field contains the capability of Ultra DMA Transfer. The low order byte identifies by bit all of the

Modes which are supported, e.g., if Mode 0 is supported, bit 0 is set to one. The high order byte contains a single bit set to indicate which mode is active supported, e.g., if Mode 0 is active, bit 0 is set to one.

word 91 : Current Advanced Power Management Level

This field contains Current Value of Advanced Power Management Level.

word 129 : Current Set Features Option, Bit Assignment

This field contains Current Option Value of Set Features.

word 130 : Reassigned Sectors

This field contains the number of reassigned sectors.

word 131 : Initial Power mode Selection, Bit Assignment

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This field contains the mode definition at power on reset.

word 160 : Power Requirement Description

This word is required for CompactFlash Storage Cards that support power mode 1.

Bit 15: VLD if set to 1, indicates that this word contains a valid power requirement description.

if set to 0, indicates that this word does not contain a power requirement description.

Bit 14: RSV

This bit is reserved and must be 0.

Bit 13: -XP if set to 1, indicates that the Card does not have Power Level 1 commands.

if set to 0, indicates that the Card has Power Level 1 commands

Bit 12: -XE if set to 1, indicates that Power Level 1 commands are disabled..

if set to 0, indicates that Power Level 1 commands are enabled.

Bit 0-11: Maximum current

This field contains the Card’s maximum current in mA.

word 161 : CF Command Set Extentions

This word is assigned to have capability of CF command set extentions.

Bit 0:

If set to 1, indicates that Metadata command set is supported.

If set to 0, indicates that Metadata command set is not supported.

Bit 15:

If set to 1, Word 161 is valid.

If set to 0, Word 161 is not valid.

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13.4.9 Idle (E3h/97h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 0 0 0 1

0

-

-

V

-

-

-

-

1

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 32. Idle Command (E3h/97h)

The Idle command causes the device to enter Idle mode immediatly, and set auto power down timeout parameter(standby timer). And then the timer starts counting down.

When the Idle mode is entered, the device is spun up to operating speed. If the device is already spinning, the spin up sequence is not executed.

During Idle mode the device is spinning and ready to respond to host commands immediately.

Sector Count

Output Parameters To The Device

Timeout Parameter. If zero, the timeout interval(Standby Timer) is NOT disabled, but the timeout interval is set for 109 minutes automatically. If other than zero, the timeout interval is set for (Timeout Parameter x5) seconds.

The device will enter Standby mode automatically if the timeout interval expires with no device access from the host. The timeout interval will be reinitialized if there is a device access before the timeout interval expires.

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13.4.10 Idle Immediate (E1h/95h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 0 0 0

1

-

-

-

-

-

-

-

0

-

-

-

-

-

-

-

0 1

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 33. Idle Immediate Command (E1h/95h)

The Idle Immediate command causes the device to enter Idle mode.

The device is spun up to operating speed. If the device is already spinning, the spin up sequence is not executed.

During Idle mode the device is spinning and ready to respond to host commands immediately.

The Idle Immediate command will not affect the auto power down timeout parameter.

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13.4.11 Initialize Device Parameters (91h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D H H H

0

-

-

V

-

-

-

H

Command

1 0 0 1 0 0 0 1

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

0

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 0

1

IDX

0

0

ERR

V

Figure 34. Initialize Device Parameters Command (91h) y y y y

The Initialize Device Parameters command enables the host to set the number of sectors per track and the number of heads minus 1, per cylinder. Words 54-58 in Identify Device

Information reflects these parameters.

The parameters remain in effect until the following events:

Another Initialize Device Parameters command is received.

The device is powered off.

Hard reset occurs.

Soft reset occurs and the Set Feature option of CCh is set

Sector Count

H

Output Parameters To The Device

The number of sectors per track. 0 does not mean there are 256 sectors per track, but there is no sector per track.

The number of heads minus 1 per cylinder. The minimum is 0 and the maximum is

15.

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13.4.12 Read Buffer (E4h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 0 0 1

1

-

-

-

-

-

-

-

0

-

-

-

-

-

-

-

0 0

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 0

1

IDX

0

0

ERR

V

Figure 35. Read Buffer Command (E4h)

The Read Buffer command transfers a sector of data from the sector buffer of device to the host.

The sector is transferred through the Data Register 16 bits at a time.

The sector transferred will be from the same part of the buffer written to by the last Write Buffer command. The contents of the sector may be different if any reads or writes have occurred since the Write Buffer command was issued.

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13.4.13 Read DMA(C8h/C9h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

V V V V V V V

0

-

-

V

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

1 L 1 D H H H H

Command

1 1 0 0 1 0 0 R

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

V V V V V V V

0

-

V

Sector Number

V V V V V V V V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

V

6

UNC

V

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

V

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 36. Read DMA Command (C8h/C9h)

The Read DMA command reads one or more sectors of data from disk media, then transfers the data from the device to the host.

The sectors are transferred through the Data Register 16 bits at a time.

The host initializes a slave-DMA channel prior to issuing the command. The data transfers are qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one interrupt per command to indicate that data transfer has terminated and status is available.

If an uncorrectable error occurs, the read will be terminated at the failing sector.

Sector Count

Sector Number

Cylinder High/Low

H

R

Sector Count

Output Parameters To The Device

The number of continuous sectors to be transferred. If zero is specified, then 256 sectors will be transferred.

The sector number of the first sector to be transferred. (L=0)

In LBA mode, this register specifies LBA address bits 0 - 7 to be transferred. (L=1)

The cylinder number of the first sector to be transferred. (L=0)

In LBA mode, this register specifies LBA address bits 8 - 15 (Low) 16 - 23

(High) to be transferred. (L=1)

The head number of the first sector to be transferred. (L=0)

In LBA mode, this register specifies LBA bits 24-27 to be transferred.

(L=1)

The retry bit. If set to one, then retries are disabled.

Input Parameters From The Device

The number of requested sectors not transferred. This will be zero, unless

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Sector Number

Cylinder High/Low

H

an unrecoverable error occurs.

The sector number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 0 - 7. (L=1)

The cylinder number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 8 - 15 (Low), 16 - 23

(High). (L=1)

The head number of the sector to be transferred. (L=0)

In LBA mode, this register contains current LBA bits 24 - 27. (L=1)

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13.4.14 Read Long (22h/23h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

0 0 0 0 0 0

Sector Number

V V V V V V

Cylinder Low

V V V V V V

Cylinder High

V V V V V V

Device/Head

1 L 1 D H H

Command

0 0 1 0 0 0

1

-

-

0

0

-

-

1

V V

V V

V V

H H

1 R

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

V V V V V V V

0

-

V

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

V

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 37. Read Long Command (22h/23h)

The Read Long command reads the designated one sector of data and the ECC bytes from the disk media, then transfers the data and ECC bytes from the device to the host.

After 512 bytes of data have been transferred, the device will keep setting DRQ=1 to indicate that the device is ready to transfer the ECC bytes to the host. The data is transferred 16 bits at a time, and the ECC bytes are transferred 8 bits at a time. The number of ECC bytes are 4 or according to the setting of Set Feature option. The default setting is 4 bytes of ECC data.

The command makes a single attempt to read the data and does not check the data using ECC.

Whatever is read is returned to the host.

Sector Count

Sector Number

Cylinder High/Low

H

R

Sector Count

Sector Number

Output Parameters To The Device

The number of continuous sectors to be transferred. The Sector Count must be set to one.

The sector number of the sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 0 - 7. (L=1)

The cylinder number of the sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High).

(L=1)

The head number of the sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 24-27. (L=1)

The retry bit. If set to one, then retries are disabled.

Input Parameters From The Device

The number of requested sectors not transferred.

The sector number of the transferred sector. (L=0)

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Cylinder High/Low

H

In LBA mode, this register contains current LBA bits 0 - 7. (L=1)

The cylinder number of the transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 8 - 15 (Low), 16 - 23

(High). (L=1)

The head number of the transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 24-27. (L=1)

It should be noted that the device internally uses bytes of ECC data on all data written or read from the disk. The 4 byte mode of operation is provided via an emulation. It is recommended that for testing the effectiveness and integrity of the devices ECC functions that the byte ECC mode should be used.

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13.4.15 Read Multiple (C4h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

V V V V V V V

0

-

-

V

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

1 L 1 D H H H H

Command

1 1 0 0 0 1 0 0

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

V V V V V V V

0

-

V

Sector Number

V V V V V V V V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

0

6

UNC

V

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

V

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 38. Read Multiple Command (C4h)

The Read Multiple command reads one or more sectors of data from disk media, then transfers the data from the device to the host.

The sectors are transferred through the Data Register 16 bits at a time. Command execution is identical to the Read Sectors command except that an interrupt is generated for each block (as defined by the Set Multiple command) instead of for each sector.

Sector Count

Sector Number

Cylinder High/Low

H

Sector Count

Sector Number

Cylinder High/Low

Output Parameters To The Device

The number of continuous sectors to be transferred. If zero is specified, then 256 sectors will be transferred.

The sector number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 0 - 7. (L=1)

The cylinder number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High).

(L=1)

The head number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 24 - 27. (L=1)

Input Parameters From The Device

The number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs.

The sector number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 0 - 7. (L=1)

The cylinder number of the last transferred sector. (L=0)

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H

In LBA mode, this register contains current LBA bits 8-15 (Low), 16-23

(High). (L=1)

The head number of the last transferred sector. (L=0)

LBA mode, this register contains current LBA bits 24 - 27. (L=1)

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13.4.16 Read Sector(s) (20h/21h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

V V V V V V V

0

-

-

V

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

1 L 1 D H H H H

Command

0 0 1 0 0 0 0 R

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

V V V V V V V

0

-

V

Sector Number

V V V V V V V V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

0

6

UNC

V

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

V

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 39. Read Sector(s) Command (20h/21h)

The Read Sectors command reads one or more sectors of data from disk media, then transfers the data from the device to the host.

The sectors are transferred through the Data Register 16 bits at a time.

If an uncorrectable error occurs, the read will be terminated at the failing sector.

Sector Count

Sector Number

Cylinder High/Low

H

R

Sector Count

Sector Number

Cylinder High/Low

Output Parameters To The Device

The number of continuous sectors to be transferred. If zero is specified, then 256 sectors will be transferred.

The sector number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 0 - 7. (L=1)

The cylinder number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High).

(L=1)

The head number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 24 - 27. (L=1)

The retry bit. If set to one, then retries are disabled.

Input Parameters From The Device

The number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs.

The sector number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 0 - 7. (L=1)

The cylinder number of the last transferred sector. (L=0)

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H

In LBA mode, this register contains current LBA bits 8 - 15 (Low), 16 - 23

(High). (L=1)

The head number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 24 - 27. (L=1)

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13.4.17 Read Verify (40h/41h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

V V V V V V V

0

-

-

V

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

1 L 1 D H H H H

Command

0 0 1 0 0 0 0 R

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

V V V V V V V

0

-

V

Sector Number

V V V V V V V V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

0

6

UNC

V

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

V

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 40. Read Verify Command (40h/41h)

The Read Verify Sectors verifies one or more sectors on the device. No data is transferred to the host.

The difference of Read Sectors command and Read Verify Sectors command is whether the data is transferred to the host or not.

If an uncorrectable error occurs, the read verify will be terminated at the failing sector.

Sector Count

Sector Number

Cylinder High/Low

H

R

Sector Count

Sector Number

Output Parameters To The Device

The number of continuous sectors to be verified. If zero is specified, then

256 sectors will be verified.

The sector number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 0 - 7. (L=1)

The cylinder number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High).

(L=1)

The head number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 24 - 27. (L=1)

The retry bit. If set to one, then retries are disabled.

Input Parameters From The Device

The number of requested sectors not verified. This will be zero, unless an unrecoverable error occurs.

The sector number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 0 - 7. (L=1)

The cylinder number of the last transferred sector. (L=0)

Cylinder High/Low

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H

In LBA mode, this register contains current LBA bits 8 - 15 (Low), 16 - 23

(High). (L=1)

The head number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 24 - 27. (L=1)

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13.4.18 Recalibrate (1Xh)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

0 0 0 1 -

1 0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

V

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 41. Recalibrate Command (1Xh)

The Recalibrate command moves the read/write heads from anywhere on the disk to cylinder 0.

If the device cannot reach cylinder 0, T0N (Track 0 Not Found) will be set in the Error Register.

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13.4.19 Request Sense (03h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

0 0 0 1 -

1 0

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

0

3

0

0

2

ABT

V

1

T0N

V

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

0

Status Register

4

DSC

V

3

DRQ

-

2

COR

0

1

IDX

0

0

ERR

V

Figure 42. Request Sense Command (03h)

This command requests extended error information for the previous command. The following table defines the valid extended error codes for the H itachi

Microdrive. The extended error code is returned to the host in the Error Register.

Code

00h

09h

20h

21h

3Ah

0Ch

03h

22h

2Fh

11h

05h

10h

Error Type

No Error Detected

Miscellaneous Error

Invalid Command

Invalid Address (Requested Head or Sector

Invalid)

Address Overflow (Address Too Large)

Uncorrectable ECC Error

Self Test or Diagnostic Failed

ID Not Found

Spare Sectors Exhausted

Corrupted Media Format

Write/Erase Failed

Extended Power Operations Disabled

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Figure 43. Extended Error Codes

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13.4.20 Security Erase Prepare (F3h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 1 0 0

1

-

-

-

-

-

-

-

0

-

-

-

-

-

-

-

1 1

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 44. Security Erase Prepare (F3h)

The Security Erase Prepare Command must be issued immeidately before the Format Unit to prevent accidental erasure of the device. This command does not request to transfer data

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13.4.21 Seek (7Xh)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

V V V V V V

Cylinder Low

V V V V V V

Cylinder High

V V V V V V

Device/Head

1 L 1 D H H

Command

0 1 1 1 -

1

-

-

-

0

-

-

-

V V

V V

V V

H H

-

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

V V V V V V V

0

-

-

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 45. Seek Command (7Xh)

The Seek command initiates a seek to the designated track and selects the designated head. The device need not be formatted for a seek to execute properly.

Sector Number

Cylinder High/Low

H

Sector Number

Cylinder High/Low

H

Output Parameters To The Device

In LBA mode, this register specifies LBA address bits 0 - 7 for seek. (L=1)

The cylinder number of the seek.

In LBA mode, this register specifies LBA address bits 8 - 15 (Low), 16 - 23

(High) for seek. (L=1)

The head number of the seek.

In LBA mode, this register specifies LBA address bits 24 - 27 for seek.

(L=1)

Input Parameters From The Device

In LBA mode, this register contains current LBA bits 0 - 7. (L=1)

In LBA mode, this register contains current LBA bits 8 - 15 (Low), 16 - 23

(High). (L=1)

In LBA mode, this register contains current LBA bits 24 - 27. (L=1)

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13.4.22 Sense Condition (F0h : vendor specific)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

0 0 0 0 0 0

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 1 0 0

1

-

0

-

-

-

-

-

0

-

1

-

-

-

-

-

0 0

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

V V V V V V V

0

-

V

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

D -

Status

...See Below...

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

Figure 46. Sense Condition Command (F0h)

7

BSY

V

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V -

1

IDX

0

0

ERR

V

The Sense Condition command is used to sense temparature in a device.

This command is executable winthout spinning up even if a device is started with No Spin Up option.

Feature

Sector Count

Output Parameters To The Device

The Feature register must be set to 01h. All other value are rejected with setting ABORT bit in status register.

Input Parameters From The Device

The Sector Count register contains result value.

Value

00h

01h-FEh

FFh

Description

Temperature is equal to or lower than -20 degC

Temperature is (Value / 2 - 20) deg C

Temperature is higher than 107 degC

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13.4.23 Set Features (EFh)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

V V V V V V

1

-

V

Sector Count

Note.1

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 0 1 1 1

0

-

V

-

-

-

-

1

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 0

1

IDX

0

0

ERR

V

Figure 47. Set Features Command (EFh)

The Set Feature command establishes the following parameters which affect the execution of certain features as shown in below table.

ABT will be set to 1 in the Error Register if the Feature register contains any undefined values.

Feature

01h

02h

03h

05h

44h

55h

66h

69h

81h

82h

85h

96h

Operation

Enable 8-bit data transfer

Enable Write Cache

Used for Set Transfer Mode command

Set Advanced Power Management Mode

Product specific ECC bytes (34 bytes) apply on Read/Write Long commands

Disable Read Look Ahead

Disable Power on Reset (POR) establishment of defaults at Soft

Reset

NOP n Accepted for backward compatibility

Disable 8-bit data transfer

Disable Write Cache

Disable Advanced Power Management

NOP n Accepted for backward compatibility

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97h

9Ah

AAh

BBh

CCh

Accepted for backward compatibility. Use of this feature is not recommended

NOP n Accepted for backward compatibility

Enable Read Look Ahead

4 bytes of ECC apply on Read/Write Long commands

Enable Power on Rest (POR) establishment of defaults at Soft Reset

Figure 48. Features Supported

Features 01h and 81h are used to enable and clear 8 bit data transfer modes in True IDE Mode.

If the 01h feature command is issued all data transfers will occur on the low order D7-D0 data bus and the IOIS16 signal will not be asserted for data register accesses.

Features 82h, AAh and BBh are the default features for the H itachi

Microdrive, thus, the host does not have to issue this command with these features unless it is necessary for compatibility reasons.

Features 66h and CCh can be used to enable and disable whether the Power On Reset (POR)

Defaults will be set when a soft reset occurs. The default setting is to revert to the POR defaults when a soft reset occurs.

Feature 05h is used for advanced power management. The Sector Count Register specifies the advanced power management level as below. The advanced power management level at power on reset is 60h.

y

80h - FEh Up to Low Power Idle mode y

01h - 7Fh Up to Standby mode y

00h, FFh Reserved

Feature 85h is used to disable advanced power management. This results in the same effect as the host uses features 05h with the Sector Count Register FEh.

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13.4.24 Set Multiple (C6h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 0 0 0 1 1

0

-

-

V

-

-

-

-

0

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

Figure 49. Set Multiple Command (C6h)

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 0

1

IDX

0

0

ERR

V

The Set Multiple command enables the device to perform Read and Write Multiple commands and establishes the block size for these commands. The block size is the number of sectors to be transferred for each interrupt.

The default block size after power up, or hard reset is 0, and Read Multiple and Write Multiple commands are disabled.

If an invalid block size is specified, an Abort error will be returned to the host, and Read

Multiple and Write Multiple commands will be disabled.

Sector Count

Output Parameters To The Device

The block size to be used for Read Multiple and Write Multiple commands.

Valid block sizes can be selected from 0, 1, 2, 4, 8 or 16. If 0 is specified, then Read Multiple and Write Multiple commands are disabled.

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13.4.25 Sleep (E6h/99h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 0 0 1

1

-

-

-

-

-

-

-

0

-

-

-

-

-

-

-

1 0

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 50. Sleep Command (E6h/99h)

The Sleep command causes the device to enter the Sleep Mode immediately.

When this command is issued, the device confirms the completion of the cached write commands before it asserts INTRQ. Then the device is spun down. If the device is already spun down, the spin down sequence is not executed. It is not required to use a software reset or a hardware reset to recover from Sleep Mode, but simply issue a command to the device.

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13.4.26Standby (E2h/96h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 0 0 0 1

0

-

-

V

-

-

-

-

0

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 51. Standby Command (E2h/96h)

The Standby command causes the device to enter the Standby Mode immediately, and set auto power down timeout parameter(standby timer).

When this command is issued, the device confirms the completion of the cached write commands before it asserts INTRQ. Then the device is spun down, but the interface remains active.

If the device is already spun down, the spin down sequence is not executed.

During the Standby mode the device will respond to commands, but there is a delay while waiting for the spindle to reach operating speed.

The timer starts counting down when the device returns to Idle mode.

Sector Count

Output Parameters To The Device

Timeout Parameter. If zero, the timeout interval(Standby Timer) is NOT disabled, but the timeout interval is set to 109 minutes automatically. If other than zero, the timeout interval is set for (Timeout Parameter x5) seconds.

When the automatic power down sequence is enabled,

The device will enter Standby mode automatically if the timeout interval expires with no device access from the host. The timeout interval will be reinitialized if there is a device access before the timeout interval expires.

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13.4.27 Standby Immediate (E0h/94h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 0 0 0

1

-

-

-

-

-

-

-

0

-

-

-

-

-

-

-

0 0

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 52. Standby Immediate Command (E0h/94h)

The Standby Immediate command causes the device to enter Standby mode immediately.

When this command is issued, the device confirms the completion of the cached write commands before asserts INTRQ. Then the device is spun down, but the interface remains active.

If the device is already spun down, the spin down sequence is not executed.

During the Standby mode, the device will respond to commands, but there is a delay while waiting for the spindle to reach operating speed.

The Standby Immediate command will not affect the auto power down timeout parameter.

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13.4.28 Translate Sector (87h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

V V V V V V

Cylinder Low

V V V V V V

Cylinder High

V V V V V V

Device/Head

1 L 1 D H H

Command

0 0 1 0 0 0

1

-

-

-

0

-

-

-

V V

V V

V V

H H

0 R

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

V V V V V V V

0

-

-

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

0

6

UNC

V

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

V

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 53. Translate Sector command (87h)

This command allows the host a method of determining the exact number of times a user sector has been erased and programmed. The controller responds with a 512 byte buffer of information containing the desired cylinder, head and sector, including its Logical Address, and the Hot

Count, if available, for that sector. The following table represents the information in the buffer.

Please note that this command is unique to the card.

Address

00h-01h

02h

03h

04h-06h

07h-12h

13h

14h-17h

18h-1Ah

1Bh-1FFh

Information

Cylinder MSB (00), Cylinder LSB (01)

Head

Sector

LBA MSB (04) - LSB (06)

Reserved

Erased Flag (FFh) = Erased; 00h = Not Erased

Reserved

Hot Count MSB (18) - LSB (1A)

Reserved

Figure 54. Translate Sector Information

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13.4.29 Wear Level (F5h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D V V

Command

1 1 1 1 0 1

1

-

-

-

-

-

-

0

-

-

-

-

-

-

V V

0 1

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

0 0 0 0 0 0 0

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

0

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 V 0

1

IDX

0

0

ERR

V

Figure 55. Wear Level Command (F5h)

This command is implemented as a nop command. However, the Sector Count Register is returned with 00h for backward compatibility.

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13.4.30 Write Buffer (E8h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

1 1 D -

Command

1 1 1 0 1 0

1

-

-

-

-

-

-

-

0

-

-

-

-

-

-

-

0 0

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

-

Cylinder Low

-

Cylinder High

-

Device/Head

-

Status

...See Below...

0

-

-

-

-

-

-

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

0 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

0 0

1

IDX

0

0

ERR

V

Figure 56. Write Buffer Command (E8h)

The Write Buffer command transfers a sector of data from the host to the sector buffer of the device. The sectors of data are transferred through the Data Register 16 bits at a time.

The Read Buffer and Write Buffer commands are synchronized such that sequential Write

Buffer and Read Buffer commands access the same 512 byte within the buffer.

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13.4.31 Write DMA (CAh/CBh)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

V V V V V V V

0

-

-

V

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

1 L 1 D H H H H

Command

1 1 0 0 1 0 1 R

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

V V V V V V V

0

-

V

Sector Number

V V V V V V V V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

V

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

V V 0

1

IDX

0

0

ERR

V

Figure 57. Write DMA Command (CAh/CBh)

The Write DMA command transfers one or more sectors of data from the host to the device, then the data is written to the disk media.

The sectors of data are transferred through the Data Register 16 bits at a time.

The host initializes a slave-DMA channel prior to issuing the command. Data transfers are qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one interrupt per command to indicate that data transfer has terminated and status is available.

If an uncorrectable error occurs, the write will be terminated at the failing sector.

Sector Count

Sector Number

Cylinder High/Low

H

R

Output Parameters To The Device

The number of continuous sectors to be transferred. If zero is specified, then 256 sectors will be transferred.

The sector number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 0 - 7. (L=1)

The cylinder number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High).

(L=1)

The head number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 24 - 27. (L=1)

The retry bit. If set to one, then retries are disabled. When write cache is enabled, They are ignored. (Ignoring the retry bit is in violation of ATA-3.)

Input Parameters From The Device

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Sector Count

Sector Number

Cylinder High/Low

H

The number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs.

The sector number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 0 - 7. (L=1)

The cylinder number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 8 - 15 (Low), 16 - 23

(High). (L=1)

The head number of the last transferred sector. (L=0) In LBA mode, this register contains current LBA bits 24 - 27. (L=1)

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13.4.32 Write Long (32h/33h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

0 0 0 0 0 0

Sector Number

V V V V V V

Cylinder Low

V V V V V V

Cylinder High

V V V V V V

Device/Head

1 L 1 D H H

Command

0 0 1 1 0 0

1

-

-

0

0

-

-

1

V V

V V

V V

H H

1 R

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

-

Sector Number

V V V V V V V

0

-

V

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

V V 0

1

IDX

0

0

ERR

V

Figure 58. Write Long Command (32h/33h)

The Write Long command transfers the data and the ECC bytes of the designated one sector from the host to the device, then the data and the ECC bytes are written to the disk media.

After 512 bytes of data have been transferred, the device will keep setting DRQ=1 to indicate that the device is ready to receive the ECC bytes from the host. The data is transferred 16 bits at a time, and the ECC bytes are transferred 8 bits at a time. The number of ECC bytes are 4 or according to setting of Set Feature option. The default number after power on is 4 bytes.

Sector Count

Sector Number

Cylinder High/Low

H

R

Sector Count

Sector Number

Output Parameters To The Device

The number of continuous sectors to be transferred. The Sector Count must be set to one.

The sector number of the sector to be transferred. (L=0) In LBA mode, this register contains LBA bits 0 - 7. (L=1)

The cylinder number of the sector to be transferred. (L=0) In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1)

The head number of the sector to be transferred. (L=0) In LBA mode, this register contains LBA bits 24 - 27. (L=1)

The retry bit. If set to one, then retries are disabled.

Input Parameters From The Device

The number of requested sectors not transferred.

The sector number of the sector to be transferred. (L=0) In LBA mode, this register contains current LBA bits 0 - 7. (L=1)

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Cylinder High/Low

H

The cylinder number of the sector to be transferred. (L=0) In LBA mode, this register contains current LBA bits 8 - 15 (Low), 16 - 23 (High). (L=1)

The head number of the sector to be transferred. (L=0) In LBA mode, this register contains current LBA bits 24 - 27. (L=1)

The file internally uses bytes of ECC on all data read or writes. The 4 byte mode of operation is provided via an emulation technique. As a consequence of this emulation it is recommended that byte ECC mode is used for all tests to confirm the operation of the files ECC hardware.

Unexpected results may occur if such testing is performed using 4 byte mode.

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13.4.33 Write Multiple (C5h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

V V V V V V V

0

-

-

V

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

1 L 1 D H H H H

Command

1 1 0 0 0 1 0 1

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

V V V V V V V

0

-

V

Sector Number

V V V V V V V V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

V V 0

1

IDX

0

0

ERR

V

Figure 59. Write Multiple Command (C5h)

The Write Multiple command transfers one or more sectors from the host to the device, then the data is written to the disk media.

Command execution is identical to the Write Sectors command except that an interrupt is generated for each block (as defined by the Set Multiple command) instead of for each sector.

The sectors are transferred through the Data Register 16 bits at a time.

Sector Count

Sector Number

Cylinder High/Low

H

Sector Count

Sector Number

Cylinder High/Low

Output Parameters To The Device

The number of continuous sectors to be transferred. If zero is specified, then 256 sectors will be transferred.

The sector number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 0 - 7. (L=1)

The cylinder number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High).

(L=1)

The head number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 24 - 27. (L=1)

Input Parameters From The Device

The number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs.

The sector number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 0 - 7. (L=1)

The cylinder number of the last transferred sector. (L=0)

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H

In LBA mode, this register contains current LBA bits 8 - 15 (Low), 16 - 23

(High). (L=1)

The head number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 24 - 27. (L=1)

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13.4.34 Write Multiple without Erase (CDh)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

V V V V V V V

0

-

-

V

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

1 L 1 D H H H H

Command

0 0 1 1 0 0 0 R

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

V V V V V V V

0

-

V

Sector Number

V V V V V V V V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

V V 0

1

IDX

0

0

ERR

V

Figure 60. Write Multiple without Erase Command (CDh)

This command is identical to the Write Multiple command as the H itachi

Microdrive does not need pre-erase before a write operation.

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13.4.35 Write Sector(s) (30h/31h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

V V V V V V V

0

-

-

V

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

1 L 1 D H H H H

Command

0 0 1 1 0 0 0 R

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

V V V V V V V

0

-

V

Sector Number

V V V V V V V V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

V V 0

1

IDX

0

0

ERR

V

Figure 61. Write Sector(s) Command (30h/31h)

The Write Sectors command transfers one or more sectors from the host to the device, then the data is written to the disk media.

The sectors are transferred through the Data Register 16 bits at a time.

If an uncorrectable error occurs, the write will be terminated at the failing sector, when the auto reassign function is disable.

Sector Count

Sector Number

Cylinder High/Low

H

R

Sector Count

Sector Number

Output Parameters To The Device

The number of continuous sectors to be transferred. If zero is specified, then 256 sectors will be transferred.

The sector number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 0 - 7. (L=1)

The cylinder number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 8 - 15 (Low), 16 - 23 (High).

(L=1)

The head number of the first sector to be transferred. (L=0)

In LBA mode, this register contains LBA bits 24 - 27. (L=1)

The retry bit. If set to one, then retries are disabled. But ignored, when write cache is enabled. (Ignoring the retry bit is in violation of ATA-3.)

Input Parameters From The Device

The number of requested sectors not transferred. This will be zero, unless an unrecoverable error occurs.

The sector number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 0 - 7. (L=1)

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Cylinder High/Low

H

The cylinder number of the last transferred sector. (L=0)

In LBA mode, this register contains current LBA bits 8 - 15 (Low), 16 - 23

(High). (L=1)

The head number of the last transferred sector. (L=0)In LBA mode, this register contains current LBA bits 24 - 27. (L=1)

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13.4.36 Write Sector(s) without Erase (38h)

Command Block Output Registers

Register

7 6 5 4 3 2

Data

-

Feature

-

Sector Count

V V V V V V

1

-

-

V

Sector Number

V V V V V V V

0

-

-

V

V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

1 L 1 D H H H H

Command

0 0 1 1 0 0 0 R

Command Block Input Registers

Register

7 6 5 4 3 2

Data

-

Error

...See Below...

1

-

Sector Count

V V V V V V V

0

-

V

Sector Number

V V V V V V V V

Cylinder Low

V V V V V V V V

Cylinder High

V V V V V V V V

Device/Head

H H H H

Status

...See Below...

7

CRC

0

6

UNC

0

5

0

0

Error Register

4

IDN

3

0

2

ABT

V 0 V

1

T0N

0

0

AMN

0

7

BSY

0

6

RDY

V

5

DF

Status Register

4

DSC

3

DRQ

2

COR

V V 0

1

IDX

0

0

ERR

V

Figure 62. Write Sector(s) without Erase Command (38h)

This command is identical to the Write Sector(s) command as the H itachi

Microdrive does not need pre- erase before a write operation.

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13.4.37 Write Verify (3Ch: Vendor Specific)

In implementation, Write Verify command is exactry same as Write Sector(s) command (30h).

No read verification is performed after write operation.

Refer to Write Sectors Command for parameters.

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COMMAND

Access Metadata

Storage

Check Power Mode

Execute Device

Diagnostic

Erase Sector(s)

Flush Cache

Format Track

Identify Device

Idle

Idle Immediate

Initialize Device

Parameters

Read Buffer

Read DMA

Read Multiple

Read Long Sector

Read Sector(s)

Read Verify

Recalibrate

Request Sense

Seek

Sense Condition

Set Features

Set Multiple Mode

Set Sleep Mode

Standby

Standby Immediate

Translate Sector

Wear Level

Write Buffer

Write DMA

Write Long Sector

Write Multiple

Write Multiple w/o erase

Write Sector(s)

Write Sector(s) w/o

Erase

Write Verify

Invalid Command

Code

13.5 Error Posting

The following table summarizes the valid status and error value for all the CF-ATA Command set.

V = valid on this command

CRC

Error Register

UNC IDNF ABRT

V

AMN

F

V

DRDY

V

Status Register

DWF DSC

COR

R

V

ERR

V

V V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

Figure 63. Error and Status Register

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13.6 Card information structure

01 ; CISTPL_DEVICE (5V Device Information Tuple)

04 ; Tuple length = 4 bytes

DF ; Device ID

; Device Type (bit4..7) = D (DTYPE_FUNCSPEC)

; WPS(write protect switch) (bit3) = 1 (non WP)

; Device Speed (bit0..2) = 3 (DSPEED_150NS)

12 ;

01 ; Device Size = 1 (2K bytes)

FF ; End Mark

1C ; CISTPL_DEVICE_0C (Additional Device Information Tuple)

05 ; Tuple length = 5 bytes

03 ; Other Condition Info

; Ext (bit7) = 0

; Reserved (bit3..6) = 0

; Vcc Used (bit 1,2) = 1 (3.3V)

; MWAIT (bit0) = 1

; Device Info fields

DF ; Device Information

; Device Type (bit4..7) = D (DTYPE_FUNCSPEC)

; WPS(write protect switch) (bit3) = 1 (non WP)

; Device Speed (bit0..2) = 3 (DSPEED_150NS)

12

01 ; Device Size Code = 1 (2K bytes)

FF ; End Mark

18 ; CISTPL_JEDEC_C (JEDEC ID Tuple)

02 ; Tuple length = 2 bytes

DF ; PC Card ATA with no Vpp required for any operation

01 ;

21 ; CISTPL_FUNCID (Function ID Tuple)

02 ; Tuple length = 2 bytes

04 ; TPLFID_FUNCTION (IC Card function code) = 04 (Fixed Disk)

01 ; TPLFID_SYSINIT (System Initialization bit mask)

; POST(bit0) = 1

; ROM (bit1) = 0

22 ; CISTPL_FUNCE (Function Extension Tuple)

02 ; Tuple length = 2 bytes

01 ; TPLFE_TYPE (Extension Type) = 01 (Disk Device Interface)

01 ; TPLFE_DATA (Interface Type) = 01 (PC Card ATA Interface)

22 ; CISTPL_FUNCE (Function Extension tuple)

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03 ; Tuple length = 3 bytes

02 ; TPLFE_TYPE (Extension Type) = 02 (Basic PC Card ATA Interface)

08 ; TPLFE_DATA

; V : Vpp[2::1] (bit0,1) = 00 (Vpp not required)

; S : Silicon (bit2) = 0 (Rotating device)

; U : Unique (bit3) = 1 (Model/Serial is unique)

; D : Dual drive (bit4) = 0 (single drive)

0F ; TPLFE_DATA

; P0 : Sleep (bit0) = 1 (support sleep mode)

; P1 : Standby (bit1) = 1 (support standby mode)

; P2 : Idle (bit2) = 1 (support idle mode)

; P3 : Auto (bit3) = 1(support automatic power control)

; N : 3F7/377 (bit4) = 0(include 3F7h 377h for I/O address)

; E : Index Emulate (bit5)= 0 (index emulation is not supported)

; I : IOIS16 (bit6) = 0

1A ; CISTPL_CONFIG (Configuration Tuple)

05 ; Tuple length = 5 bytes

01 ; TPCC_SZ (Size of Fields Byte)

; TPCC_RASZ (Size of TPCC_RADR) (bit0,1) = 1 (2bytes)

; TPCC_RMSZ (Size of TPCC_RMSK) (bit2..5) = 0 (1byte)

07 ; TPCC_LAST (Last Entry Index) = 07

00 ; TPCC_RADR (Base address of Configuration Register) = 0200h

02 ; v

0F ; TPCC_RMSK (Register Presence Mask) = 00001111b(200,202,204,206)

1B ; CISTPL_CFTABLE_ENTRY(16bit PCCardConfiguration Table Entry Tuple)

0B ; Tuple length = 0Bh bytes

C0 ; TPCE_INDX (Configuration Table Index Byte)

; Config Entry Number (bit0..5)= 00 (Memory Mode)

; Default (bit6) = 1

; Interface (bit7) = 1 (interface field exist)

C0 ; TPCE_IF (Interface Description Field)

; Interface Type (bit0..3) = 00 (Memory)

; BVDs active (bit4) = 0

; WP active (bit5) = 0

; READY active (bit6) = 1

; M Wait required (bit7) = 1

A1 ; TPCE_FS (Feature Selection byte)

; Power (bit0,1) = 01 (Vcc only)

; Timing (bit2) = 0

; I/O (bit3) = 0

; Interrupt (bit4) = 0

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; Memory (bit5,6) = 01

; Misc (bit7) = 1

; TPCE_PD (Power Description Structure)

27 ; Parameter Selection Byte

; NomV (bit0) = 1

; MinV (bit1) = 1

; MaxV (bit2) = 1

; PeakI (bit5) = 1

55 ; Power Parameter Definition (NomV)

; Exponent (bit0..2) = 5 (1V) --> 5.0 V

; Mantissa (bit3..6) = A (5.0)

4D ; Power Parameter Definition (MinV)

; Exponent (bit0..2) = 5 (1V) --> 4.5 V

; Mantissa (bit3..6) = 9 (4.5)

5D ; Power Parameter Definition (MaxV)

; Exponent (bit0..2) = 5 (1V) --> 5.5 V

; Mantissa (bit3..6) = C (5.5)

4E ; Power Parameter Definition (PeakI)

; Exponent (bit0..2) = 6 (100mA) --> 450 mA

; Mantissa (bit3..6) = 9 (4.5)

; TPCE_MS (Memory Space Description Structure)

08 ; Memory Space Descriptor Byte

; # of Windows (-1) (bit0..2) = 0 (# of window = 1)

; Length Size (bit3..4) = 1 (length field size = 1 byte)

; Card Address Size (bit5..6) = 0 (no card addr field)

; Host Addr (bit7) = 0 (arbitrary host addr)

00 ; Window Descriptor

; Length of the window = 0

20 ; TPCE_MI (Miscellaneous Features Field)

; Max Twin Card (bit0..2) = 0

; Audio (bit3) = 0

; Read Only (bit4) = 0

; Power Down (bit5) = 1 (support power down mode)

1B ;CISTPL_CFTABLE_ENTRY(16bit PCCard Configuration Table Entry Tuple)

06 ; Tuple length = 06h bytes

00 ; TPCE_INDX (Configuration Table Index Byte)

; Config Entry Number (bit0..5)= 00 (Memory Mode)

; Default (bit6) = 0

; Interface (bit7) = 0 (interface field exist)

01 ; TPCE_FS (Feature Selection byte)

; Power (bit0,1) = 01 (Vcc only)

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; Timing (bit2) = 0

; I/O (bit3) = 0

; Interrupt (bit4) = 0

; Memory (bit5,6) = 00

; Misc (bit7) = 0

21 ; Parameter Selection Byte

; NomV (bit0) = 1

; MinV (bit1) = 0

; MaxV (bit2) = 0

; PeakI (bit5) = 1

B5 ; Power Parameter Definition (NomV)

; Exponent (bit0..2) = 5 (1V) --+-> 3.3 V

; Mantissa (bit3..6) = 6 (3.0) +

; Extension (bit7) = 1 (extension exists) +

1E ; Extension = 1Eh = +0.30 --+

3E ; Power Parameter Definition (PeakI)

; Exponent (bit0..2) = 6 (100mA) --> 350 mA

; Mantissa (bit3..6) = 7 (3.5)

1B ;CISTPL_CFTABLE_ENTRY(16bit PCCard Configuration Table Entry Tuple)

0D ; Tuple length = 0Dh bytes

C1 ; TPCE_INDX (Configuration Table Index Byte)

; Config Entry Number (bit0..5)= 01 (I/O and Memory Mode)

; Default (bit6) = 1

; Interface (bit7) = 1 (interface field exist)

41 ; TPCE_IF (Interface Description Field)

; Interface Type (bit0..3) = 01 (I/O and Memory)

; BVDs active (bit4) = 0

; WP active (bit5) = 0

; READY active (bit6) = 1

; M Wait required (bit7) = 0

99 ; TPCE_FS (Feature Selection byte)

; Power (bit0,1) = 01 (Vcc only)

; Timing (bit2) = 0

; I/O (bit3) = 1

; Interrupt (bit4) = 1

; Memory (bit5,6) = 00

; Misc (bit7) = 1

; TPCE_PD (Power Description Structure)

27 ; Parameter Selection Byte

; NomV (bit0) = 1

; MinV (bit1) = 1

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; MaxV (bit2) = 1

; PeakI (bit5) = 1

55 ; Power Parameter Definition (NomV)

; Exponent (bit0..2) = 5 (1V) --> 5.0 V

; Mantissa (bit3..6) = A (5.0)

4D ; Power Parameter Definition (MinV)

; Mantissa (bit0..2) = 5 (1V) --> 4.5 V

; Exponent (bit3..6) = 9 (4.5)

5D ; Power Parameter Definition (MaxV)

; Exponent (bit0..2) = 5 (1V) --> 5.5 V

; Mantissa (bit3..6) = C (5.5)

4E ; Power Parameter Definition (PeakI)

; Exponent (bit0..2) = 6 (100mA) --> 450 mA

; Mantissa (bit3..6) = 9 (4.5)

64 ; TPCE_IO (I/O space address required for this configuration)

; IO Address Lines (bit0..4) = 4 (16byte boundary)

; Bus 16/8 (bit 5,6) = 3 (support 16/8 bit access)

; Range (bit 7) = 0

; TPCE_IR (Interrupt Request Description structure)

F0 ; IRQ line 0..15 (bit0..3) = 0

; MASK (bit4) = 1

; Level (bit5) = 1

; Pulse (bit6) = 1

; Share (bit7) = 1

FF ; IRQ0..IRQ7 = all supported

FF ; IRQ8..IRQ15 = all supported

20 ; TPCE_MI (Miscellaneous Features Field)

; Max Twin Card (bit0..2) = 0

; Audio (bit3) = 0

; Read Only (bit4) = 0

; Power Down (bit5) = 1 (support power down mode)

1B ;CISTPL_CFTABLE_ENTRY(16bit PCCard Configuration Table Entry Tuple)

06 ; Tuple length = 06h bytes

01 ; TPCE_INDX (Configuration Table Index Byte)

; Config Entry Number (bit0..5)= 01 (I/O and Memory Mode)

; Default (bit6) = 0

; Interface (bit7) = 0 (interface field exist)

01 ; TPCE_FS (Feature Selection byte)

; Power (bit0,1) = 01 (Vcc only)

; Timing (bit2) = 0

; I/O (bit3) = 0

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; Interrupt (bit4) = 0

; Memory (bit5,6) = 00

; Misc (bit7) = 0

; TPCE_PD (Power Description Structure)

21 ; Parameter Selection Byte

; NomV (bit0) = 1

; MinV (bit1) = 0

; MaxV (bit2) = 0

; PeakI (bit5) = 1

B5 ; Power Parameter Definition (NomV)

; Exponent (bit0..2) = 5 (1V) --+-> 3.3 V

; Mantissa (bit3..6) = 6 (3.0) +

; Extension (bit7) = 1 (extension exists) +

1E ; Extension = 1Eh = +0.30 --+

3E ; Power Parameter Definition (PeakI)

; Exponent (bit0..2) = 6 (100mA) --> 350 mA

; Mantissa (bit3..6) = 7 (3.5)

1B ;CISTPL_CFTABLE_ENTRY(16bit PCCard Configuration Table Entry Tuple)

12 ; Tuple length = 12h bytes

C2 ; TPCE_INDX (Configuration Table Index Byte)

; Config Entry Number (bit0..5)= 02 (I/O Primary Mode)

; Default (bit6) = 1

; Interface (bit7) = 1 (interface field exist)

41 ; TPCE_IF (Interface Description Field)

; Interface Type (bit0..3) = 01 (I/O and Memory)

; BVDs active (bit4) = 0

; WP active (bit5) = 0

; READY active (bit6) = 1

; M Wait required (bit7) = 0

99 ; TPCE_FS (Feature Selection byte)

; Power (bit0,1) = 01 (Vcc only)

; Timing (bit2) = 0

; I/O (bit3) = 1

; Interrupt (bit4) = 1

; Memory (bit5,6) = 00

; Misc (bit7) = 1

; TPCE_PD (Power Description Structure)

27 ; Parameter Selection Byte

; NomV (bit0) = 1

; MinV (bit1) = 1

; MaxV (bit2) = 1

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; PeakI (bit5) = 1

55 ; Power Parameter Definition (NomV)

; Exponent (bit0..2) = 5 (1V) --> 5.0 V

; Mantissa (bit3..6) = A (5.0)

4D ; Power Parameter Definition (MinV)

; Exponent (bit0..2) = 5 (1V) --> 4.5 V

; Mantissa (bit3..6) = 9 (4.5)

5D ; Power Parameter Definition (MaxV)

; Exponent (bit0..2) = 5 (1V) --> 5.5 V

; Mantissa (bit3..6) = C (5.5)

4E ; Power Parameter Definition (PeakI)

; Exponent (bit0..2) = 6 (100mA) --> 450 mA

; Mantissa (bit3..6) = 9 (4.5)

EA ; TPCE_IO (I/O space address required for this configuration)

; IO Address Lines (bit0..4) = A (1Kbyte boundary)

; Bus 16/8 (bit 5,6) = 3 (support 16/8 bit access)

; Range (bit 7) = 1 (see range description)

61 ; I/O range description byte

; # of address range -1 (bit0..3) = 1 (# of field = 2)

; size of address (bit 4,5) = 2 (2byte address)

; size of length (bit 6,7) = 1 (1byte length)

F0 ; I/O address range description field #1 address = 1F0

01 ; |

07 ; V address block length = 8

F6 ; I/O address range description field #2 address = 3F6

03 ; |

01 ; V address block length = 2

EE ; TPCE_IR (Interrupt Request Description structure)

; IRQ line 0..15 (bit0..3) = E ??

; MASK (bit4) = 0

; Level (bit5) = 1

; Pulse (bit6) = 1

; Share (bit7) = 1

20 ; TPCE_MI (Miscellaneous Features Field)

; Max Twin Card (bit0..2) = 0

; Audio (bit3) = 0

; Read Only (bit4) = 0

; Power Down (bit5) = 1 (support power down mode)

1B ;CISTPL_CFTABLE_ENTRY(16bit PCCard Configuration Table Entry Tuple)

06 ; Tuple length = 06h bytes

02 ; TPCE_INDX (Configuration Table Index Byte)

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; Config Entry Number (bit0..5)= 02 (I/O Primary Mode)

; Default (bit6) = 0

; Interface (bit7) = 0 (interface field exist)

01 ; TPCE_FS (Feature Selection byte)

; Power (bit0,1) = 01 (Vcc only)

; Timing (bit2) = 0

; I/O (bit3) = 0

; Interrupt (bit4) = 0

; Memory (bit5,6) = 00

; Misc (bit7) = 0

; TPCE_PD (Power Description Structure)

21 ; Parameter Selection Byte

; NomV (bit0) = 1

; MinV (bit1) = 0

; MaxV (bit2) = 0

; PeakI (bit5) = 1

B5 ; Power Parameter Definition (NomV)

; Exponent (bit0..2) = 5 (1V) --+-> 3.3 V

; Mantissa (bit3..6) = 6 (3.0) +

; Extension (bit7) = 1 (extension exists) +

1E ; Extension = 1Eh = +0.30 --+

3E ; Power Parameter Definition (PeakI)

; Exponent (bit0..2) = 6 (100mA) --> 350 mA

; Mantissa (bit3..6) = 7 (3.5)

1B ;CISTPL_CFTABLE_ENTRY(16bit PCCard Configuration Table Entry Tuple)

12 ; Tuple length = 12h bytes

C3 ; TPCE_INDX (Configuration Table Index Byte)

; Config Entry Number (bit0..5)= 03 (I/O Secondary Mode)

; Default (bit6) = 1

; Interface (bit7) = 1 (interface field exist)

41 ; TPCE_IF (Interface Description Field)

; Interface Type (bit0..3) = 01 (I/O and Memory)

; BVDs active (bit4) = 0

; WP active (bit5) = 0

; READY active (bit6) = 1

; M Wait required (bit7) = 0

99 ; TPCE_FS (Feature Selection byte)

; Power (bit0,1) = 01 (Vcc only)

; Timing (bit2) = 0

; I/O (bit3) = 1

; Interrupt (bit4) = 1

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; Memory (bit5,6) = 00

; Misc (bit7) = 1

; TPCE_PD (Power Description Structure)

27 ; Parameter Selection Byte

; NomV (bit0) = 1

; MinV (bit1) = 1

; MaxV (bit2) = 1

; PeakI (bit5) = 1

55 ; Power Parameter Definition (NomV)

; Exponent (bit0..2) = 5 (1V) --> 5.0 V

; Mantissa (bit3..6) = A (5.0)

4D ; Power Parameter Definition (MinV)

; Exponent (bit0..2) = 5 (1V) --> 4.5 V

; Mantissa (bit3..6) = 9 (4.5)

5D ; Power Parameter Definition (MaxV)

; Exponent (bit0..2) = 5 (1V) --> 5.5 V

; Mantissa (bit3..6) = C (5.5)

4E ; Power Parameter Definition (PeakI)

; Exponent (bit0..2) = 6 (100mA) --> 450 mA

; Mantissa (bit3..6) = 9 (4.5)

EA ; TPCE_IO (I/O space address required for this configuration)

; IO Address Lines (bit0..4) = A (1Kbyte boundary)

; Bus 16/8 (bit 5,6) = 3 (support 16/8 bit access)

; Range (bit 7) = 1 (see range description)

61 ; I/O range description byte

; # of address range -1 (bit0..3) = 1 (# of field = 2)

; size of address (bit 4,5) = 2 (2byte address)

; size of length (bit 6,7) = 1 (1byte length)

70 ; I/O address range description field #1 address = 170

01 ; |

07 ; V address block length = 8

76 ; I/O address range description field #2 address = 376

03 ; |

01 ; V address block length = 2

EE ; TPCE_IR (Interrupt Request Description structure)

; IRQ line 0..15 (bit0..3) = E

; MASK (bit4) = 0

; Level (bit5) = 1

; Pulse (bit6) = 1

; Share (bit7) = 1

20 ; TPCE_MI (Miscellaneous Features Field)

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; Max Twin Card (bit0..2) = 0

; Audio (bit3) = 0

; Read Only (bit4) = 0

; Power Down (bit5) = 1 (support power down mode)

1B ;CISTPL_CFTABLE_ENTRY(16bit PCCard Configuration Table Entry Tuple)

06 ; Tuple length = 06h bytes

03 ; TPCE_INDX (Configuration Table Index Byte)

; Config Entry Number (bit0..5)= 03 (I/O Secondary Mode)

; Default (bit6) = 0

; Interface (bit7) = 0 (interface field exist)

01 ; TPCE_FS (Feature Selection byte)

; Power (bit0,1) = 01 (Vcc only)

; Timing (bit2) = 0

; I/O (bit3) = 0

; Interrupt (bit4) = 0

; Memory (bit5,6) = 00

; Misc (bit7) = 0

; TPCE_PD (Power Description Structure)

21 ; Parameter Selection Byte

; NomV (bit0) = 1

; MinV (bit1) = 0

; MaxV (bit2) = 0

; PeakI (bit5) = 1

B5 ; Power Parameter Definition (NomV)

; Exponent (bit0..2) = 5 (1V) --+-> 3.3 V

; Mantissa (bit3..6) = 6 (3.0) +

; Extension (bit7) = 1 (extension exists) +

1E ; Extension = 1Eh = +0.30 --+

3E ; Power Parameter Definition (PeakI)

; Exponent (bit0..2) = 6 (100mA) --> 350 mA

; Mantissa (bit3..6) = 7 (3.5)

20 ; CISTPL_MANFID ( Manufacture ID Tuple )

04 ; Tuple length = 4 bytes

07 ; TPLMID_MANF ( Manufacture Code ) = 0319h for Hitachi

00 ; V

00 ; TPLMID_CARD ( Manufacture Info )

00 ; V

15 ; CISTPL_VERS_1 ( level1 Version Tuple )

12 ; tuple length = 12h ( 18 ) bytes

04 ; Major Version = 4 ( JEIDA 4.2/PCMCIA 2.1 )

01 ; Minor Version = 1 V

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48 ; "H"

49 ; "I"

54 ; "T"

41 ; "A"

43 ; "C"

48 ; "H"

49 ; "I"

00

6D ; "m"

69 ; "i"

63 ; "c"

72 ; "r"

6F ; "o"

64 ; "d"

72 ; "r"

69 ; "i"

76 ; "v"

65 ; "e"

00

FF ; End Mark

14 ; CISTPL_NO_LINK (No Link Tuple)

00 ; Tuple length = 0 bytes

FF ; CISTPL_END (Tuple End)

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© Copyright Hitachi Global Storage Technologies

Hitachi Global Storage Technologies

5600 Cottle Road

San Jose, CA 95193

Produced in the United States

10/03

All rights reserved Travelstar™ is a trademark of

Hitachi Global Storage Technologies.

Microsoft, Windows XP, and Windows are trademarks of Microsoft Corporation in the United States, other countries, or both.

Other product names are trademarks or registered trademarks of their respective companies.

References in this publication to Hitachi Global Storage

Technologies products, programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi

Global Storage Technologies operates.

Product information is provided for information purposes only and does not constitute a warranty.

Information is true as of the date of publication and is subject to change. Actual results may vary.

This publication is for general guidance only. Photographs may show design models.

17 October 2003

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