PIC16C6x
PIC16C6X
8-Bit CMOS Microcontrollers
Devices included in this data sheet:
• PIC16C61
• PIC16C64A
• PIC16C62
• PIC16CR64
• PIC16C62A
• PIC16C65
• PIC16CR62
• PIC16C65A
• PIC16C63
• PIC16CR65
• PIC16CR63
• PIC16C66
• PIC16C64
• PIC16C67
• Low-power, high-speed CMOS EPROM/ROM
technology
• Fully static design
• Wide operating voltage range: 2.5V to 6.0V
• Commercial, Industrial, and Extended
temperature ranges
• Low-power consumption:
• < 2 mA @ 5V, 4 MHz
• 15 µA typical @ 3V, 32 kHz
• < 1 µA typical standby current
PIC16C6X Microcontroller Core Features:
PIC16C6X Peripheral Features:
• High performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two-cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Interrupt capability
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via
external crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture/Compare/PWM (CCP) module(s)
• Capture is 16-bit, max resolution is 12.5 ns,
Compare is 16-bit, max resolution is 200 ns,
PWM max resolution is 10-bit.
• Synchronous Serial Port (SSP) with SPI and I2C
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP) 8-bits wide, with
external RD, WR and CS controls
• Brown-out detection circuitry for
Brown-out Reset (BOR)
PIC16C6X Features
61
62
62A
R62
63
R63
64
64A
R64
65
65A
R65
66
67
Program Memory
(EPROM) x 14
1K
2K
2K
—
4K
—
2K
2K
—
4K
4K
—
8K
8K
(ROM) x 14
—
—
—
2K
—
4K
—
—
2K
—
—
4K
—
—
Data Memory (Bytes) x 8
36
128
128
128
192
192
128
128
128
192
192
192
368
368
I/O Pins
13
22
22
22
22
22
33
33
33
33
33
33
22
33
Parallel Slave Port
—
—
—
—
—
—
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
Capture/Compare/PWM
Module(s)
—
1
1
1
2
2
1
1
1
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
Timer Modules
1
3
3
Serial Communication
—
SPI/
I2 C
SPI/
I2C
SPI/ SPI/I2C, SPI/I2C, SPI/
I2C USART USART I2C
SPI/
I2C
SPI/ SPI/I2C, SPI/I2C, SPI/I2C, SPI/I2C, SPI/I2C,
I2C USART USART USART USART USART
In-Circuit Serial
Programming
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Brown-out Reset
—
—
Yes
Yes
Yes
Yes
—
Yes
Interrupt Sources
3
7
7
7
10
10
8
8
Sink/Source Current (mA) 25/20 25/25 25/25 25/25 25/25
 1997 Microchip Technology Inc.
3
Yes
Yes
Yes
Yes
Yes
Yes
—
Yes
Yes
Yes
Yes
8
11
11
11
10
11
25/25
25/25
25/25
25/25
25/25 25/25 25/25 25/25 25/25
DS30234D-page 1
PIC16C6X
Pin Diagrams
SDIP, SOIC, SSOP, Windowed CERDIP (300 mil)
PDIP, SOIC, Windowed CERDIP
RA1
RA2
1
18
RA3
2
17
RA0
RA4/T0CKI
3
16
OSC1/CLKIN
MCLR/VPP
4
15
OSC2/CLKOUT
VSS
5
14
VDD
RB0/INT
6
13
RB7
RB1
7
12
RB6
RB2
8
11
RB5
RB3
9
10
RB4
MCLR/VPP
RA0
RA1
RA2
RA3
1
2
3
4
28
27
26
25
5
6
7
8
24
23
22
21
OSC1/CLKIN
OSC2/CLKOUT
9
10
20
19
RC0/T1OSI/T1CKI
RC1/T1OSO
RC2/CCP1
RC3/SCK/SCL
11
12
13
14
18
17
16
15
RA4/T0CKI
RA5/SS
VSS
PIC16C61
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
PIC16C62
SDIP, SOIC, SSOP, Windowed CERDIP (300 mil)
MCLR/VPP
RA0
RA1
RA2
1
2
3
4
28
27
26
25
RA3
RA4/T0CKI
RA5/SS
VSS
OSC1/CLKIN
5
6
7
8
24
23
22
21
9
10
20
19
11
12
13
14
18
17
16
15
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
SDIP, SOIC, Windowed CERDIP (300 mil)
MCLR/VPP
RA0
RA1
RA2
1
2
3
4
28
27
26
25
RA3
RA4/T0CKI
RA5/SS
VSS
OSC1/CLKIN
5
6
7
8
24
23
22
21
9
10
20
19
11
12
13
14
18
17
16
15
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC6
RC5/SDO
RC4/SDI/SDA
PIC16C62A
PIC16CR62
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
PIC16C63
PIC16CR63
PIC16C66
PDIP, Windowed CERDIP
MCLR/VPP
RA0
RA1
RA2
RA3
RA4/T0CKI
RA5/SS
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSI/T1CKI
RC1/T1OSO
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16C64
DS30234D-page 2
RB7
MCLR/VPP
RB6
RA0
RB5
RA1
RB4
RA2
RB3
RA3
RB2
RA4/T0CKI
RB1
RA5/SS
RB0/INT
RE0/RD
VDD
RE1/WR
VSS
RE2/CS
VDD
RD7/PSP7
VSS
RD6/PSP6
RD5/PSP5
OSC1/CLKIN
RD4/PSP4
OSC2/CLKOUT
RC7
RC0/T1OSO/T1CKI
RC6
RC1/T1OSI
RC5/SDO
RC2/CCP1
RC4/SDI/SDA
RC3/SCK/SCL
RD3/PSP3
RD0/PSP0
RD2/PSP2
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16C64A
PIC16CR64
RB7
MCLR/VPP
RB6
RA0
RB5
RA1
RB4
RA2
RB3
RA3
RB2
RA4/T0CKI
RB1
RA5/SS
RB0/INT
RE0/RD
VDD
RE1/WR
VSS
RE2/CS
VDD
RD7/PSP7
VSS
RD6/PSP6
RD5/PSP5
OSC1/CLKIN
RD4/PSP4
OSC2/CLKOUT
RC7
RC0/T1OSO/T1CKI
RC6
RC1/T1OSI/CCP2
RC5/SDO
RC2/CCP1
RC4/SDI/SDA
RC3/SCK/SCL
RD3/PSP3
RD0/PSP0
RD2/PSP2
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
PIC16C65
PIC16C65A
PIC16CR65
PIC16C67
 1997 Microchip Technology Inc.
PIC16C6X
PLCC
RC7
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
44
43
42
41
40
39
38
37
36
35
34
6
5
4
3
2
1
44
43
42
41
40
MQFP
RA3
RA2
RA1
RA0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
RC6
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSO
NC
Pin Diagrams (Cont.’d)
1
2
3
4
5
6
7
8
9
10
11
PIC16C64
33
32
31
30
29
28
27
26
25
24
23
NC
RC0/T1OSI/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS
RE1/WR
RE0/RD
RA5/SS
RA4/T0CKI
RA4/T0CKI
RA5/SS
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSI/T1CKI
NC
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
PIC16C64
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7
28
27
26
25
24
23
22
21
20
19
18
22
21
20
19
18
17
16
15
14
13
12
NC
RC6
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSO
RA3
RA2
RA1
RA0
MCLR/VPP
RB7
RB6
RB5
RB4
NC
NC
MQFP,
TQFP (PIC16C64A only)
1
2
3
4
5
6
7
8
9
10
11
PIC16C64A
PIC16CR64
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS
RE1/WR
RE0/RD
RA5/SS
RA4/T0CKI
RA4/T0CKI
RA5/SS
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
7
8
9
10
11
12
13
14
15
16
17
PIC16C64A
PIC16CR64
39
38
37
36
35
34
33
32
31
30
29
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7
39
38
37
36
35
34
33
32
31
30
29
RB3
RB2
RB1
RB0/INT
VDD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
28
27
26
25
24
23
22
21
20
19
18
RC7
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
44
43
42
41
40
39
38
37
36
35
34
6
5
4
3
2
1
44
43
42
41
40
RC6
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI
NC
RA3
RA2
RA1
RA0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
PLCC
NC
RC6
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI
RA3
RA2
RA1
RA0
MCLR/VPP
RB7
RB6
RB5
RB4
NC
NC
MQFP,
TQFP (Not on PIC16C65)
1
2
3
4
5
6
7
8
9
10
11
PIC16C65
PIC16C65A
PIC16CR65
PIC16C67
22
21
20
19
18
17
16
15
14
13
12
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
VSS
VDD
RE2/CS
RE1/WR
RE0/RD
RA5/SS
RA4/T0CKI
RA4/T0CKI
RA5/SS
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
RA3
RA2
RA1
RA0
MCLR/VPP
NC
RB7
RB6
RB5
RB4
NC
7
8
9
10
11
12
13
14
15
16
17
PIC16C65
PIC16C65A
PIC16CR65
PIC16C67
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI /CCP2
RA3
RA2
RA1
RA0
MCLR/VPP
RB7
RB6
RB5
RB4
NC
NC
 1997 Microchip Technology Inc.
33
32
31
30
29
28
27
26
25
24
23
28
27
26
25
24
23
22
21
20
19
18
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VSS
VDD
RB0/INT
RB1
RB2
RB3
44
43
42
41
40
39
38
37
36
35
34
6
5
4
3
2
1
44
43
42
41
40
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
PLCC
DS30234D-page 3
PIC16C6X
Table Of Contents
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
19.0
20.0
21.0
22.0
23.0
24.0
General Description ....................................................................................................................................................................... 5
PIC16C6X Device Varieties ........................................................................................................................................................... 7
Architectural Overview ................................................................................................................................................................... 9
Memory Organization................................................................................................................................................................... 19
I/O Ports....................................................................................................................................................................................... 51
Overview of Timer Modules ......................................................................................................................................................... 63
Timer0 Module ............................................................................................................................................................................. 65
Timer1 Module ............................................................................................................................................................................. 71
Timer2 Module ............................................................................................................................................................................. 75
Capture/Compare/PWM (CCP) Module(s)................................................................................................................................... 77
Synchronous Serial Port (SSP) Module....................................................................................................................................... 83
Universal Synchronous Asynchronous Receiver Transmitter (USART) Module ....................................................................... 105
Special Features of the CPU ..................................................................................................................................................... 123
Instruction Set Summary............................................................................................................................................................ 143
Development Support ................................................................................................................................................................ 159
Electrical Characteristics for PIC16C61 ..................................................................................................................................... 163
DC and AC Characteristics Graphs and Tables for PIC16C61.................................................................................................. 173
Electrical Characteristics for PIC16C62/64................................................................................................................................ 183
Electrical Characteristics for PIC16C62A/R62/64A/R64............................................................................................................ 199
Electrical Characteristics for PIC16C65 ..................................................................................................................................... 215
Electrical Characteristics for PIC16C63/65A ............................................................................................................................. 231
Electrical Characteristics for PIC16CR63/R65........................................................................................................................... 247
Electrical Characteristics for PIC16C66/67................................................................................................................................ 263
DC and AC Characteristics Graphs and Tables for:
PIC16C62, PIC16C62A, PIC16CR62, PIC16C63, PIC16C64, PIC16C64A, PIC16CR64,
PIC16C65A, PIC16C66, PIC16C67........................................................................................................................................... 281
25.0 Packaging Information ............................................................................................................................................................... 291
Appendix A: Modifications.............................................................................................................................................................. 307
Appendix B: Compatibility .............................................................................................................................................................. 307
Appendix C: What’s New................................................................................................................................................................ 308
Appendix D: What’s Changed ........................................................................................................................................................ 308
Appendix E:
PIC16/17 Microcontrollers ....................................................................................................................................... 309
Pin Compatibility ................................................................................................................................................................................ 315
Index .................................................................................................................................................................................................. 317
List of Equation and Examples........................................................................................................................................................... 326
List of Figures..................................................................................................................................................................................... 326
List of Tables...................................................................................................................................................................................... 330
Reader Response .............................................................................................................................................................................. 334
PIC16C6X Product Identification System........................................................................................................................................... 335
For register and module descriptions in this data sheet, device legends show which devices apply to those sections. For
example, the legend below shows that some features of only the PIC16C62A, PIC16CR62, PIC16C63, PIC16C64A,
PIC16CR64, and PIC16C65A are described in this section.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
things. If you find any information that is missing or appears in error, please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.
DS30234D-page 4
 1997 Microchip Technology Inc.
PIC16C6X
1.0
GENERAL DESCRIPTION
The PIC16CXX is a family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers.
All PIC16/17 microcontrollers employ an advanced
RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack,
and multiple internal and external interrupt sources.
The separate instruction and data buses of the Harvard
architecture allow a 14-bit wide instruction word with
separate 8-bit wide data. The two stage instruction
pipeline allows all instructions to execute in a single
cycle, except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available. Additionally, a large register set gives
some of the architectural innovations used to achieve a
very high performance.
PIC16CXX microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16C61 device has 36 bytes of RAM and 13 I/O
pins. In addition a timer/counter is available.
The PIC16C62/62A/R62 devices have 128 bytes of
RAM and 22 I/O pins. In addition, several peripheral
features are available, including: three timer/counters,
one Capture/Compare/PWM module and one serial
port. The Synchronous Serial Port can be configured
as either a 3-wire Serial Peripheral Interface (SPI) or
the two-wire Inter-Integrated Circuit (I2C) bus.
The PIC16C63/R63 devices have 192 bytes of RAM,
while the PIC16C66 has 368 bytes. All three devices
have 22 I/O pins. In addition, several peripheral features are available, including: three timer/counters, two
Capture/Compare/PWM modules and two serial ports.
The Synchronous Serial Port can be configured as
either a 3-wire Serial Peripheral Interface (SPI) or the
two-wire Inter-Integrated Circuit (I2C) bus. The Universal Synchronous Asynchronous Receiver Transmitter
(USART) is also know as a Serial Communications
Interface or SCI.
The PIC16C64/64A/R64 devices have 128 bytes of
RAM and 33 I/O pins. In addition, several peripheral
features are available, including: three timer/counters,
one Capture/Compare/PWM module and one serial
port. The Synchronous Serial Port can be configured
as either a 3-wire Serial Peripheral Interface (SPI) or
the two-wire Inter-Integrated Circuit (I2C) bus. An 8-bit
Parallel Slave Port is also provided.
The PIC16C65/65A/R65 devices have 192 bytes of
RAM, while the PIC16C67 has 368 bytes. All four
devices have 33 I/O pins. In addition, several peripheral
features are available, including: three timer/counters,
two Capture/Compare/PWM modules and two serial
ports. The Synchronous Serial Port can be configured
as either a 3-wire Serial Peripheral Interface (SPI) or
the two-wire Inter-Integrated Circuit (I2C) bus. The Universal Synchronous Asynchronous Receiver Transmit-
 1997 Microchip Technology Inc.
ter (USART) is also known as a Serial Communications
Interface or SCI. An 8-bit Parallel Slave Port is also provided.
The PIC16C6X device family has special features to
reduce external components, thus reducing cost,
enhancing system reliability and reducing power consumption. There are four oscillator options, of which the
single pin RC oscillator provides a low-cost solution,
the LP oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers a power saving
mode. The user can wake the chip from SLEEP
through several external and internal interrupts, and
resets.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software lockup.
A UV erasable CERDIP packaged version is ideal for
code
development,
while
the
cost-effective
One-Time-Programmable (OTP) version is suitable for
production in any volume.
The PIC16C6X family fits perfectly in applications ranging from high-speed automotive and appliance control
to low-power remote sensors, keyboards and telecom
processors. The EPROM technology makes customization of application programs (transmitter codes,
motor speeds, receiver frequencies, etc.) extremely
fast and convenient. The small footprint packages
make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power, high
performance, ease-of-use, and I/O flexibility make the
PIC16C6X very versatile even in areas where no microcontroller use has been considered before (e.g. timer
functions, serial communication, capture and compare,
PWM functions, and co-processor applications).
1.1
Family and Upward Compatibility
Those users familiar with the PIC16C5X family of
microcontrollers will realize that this is an enhanced
version of the PIC16C5X architecture. Please refer to
Appendix A for a detailed list of enhancements. Code
written for PIC16C5X can be easily ported to
PIC16CXX family of devices (Appendix B).
1.2
Development Support
PIC16C6X devices are supported by the complete line
of Microchip Development tools.
Please refer to Section 15.0 for more details about
Microchip’s development tools.
DS30234D-page 5
PIC16C6X
TABLE 1-1:
PIC16C6X FAMILY OF DEVICES
PIC16C62A
PIC16C61
PIC16CR62
PIC16C63
PIC16CR63
Maximum Frequency
of Operation (MHz)
20
20
20
20
20
EPROM Program Memory
(x14 words)
1K
2K
—
4K
—
ROM Program Memory
(x14 words)
—
—
2K
—
4K
Data Memory (bytes)
36
128
128
192
192
Timer Module(s)
TMR0
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Compare/
Peripherals PWM Module(s)
—
1
1
2
2
Serial Port(s)
(SPI/I2C, USART)
—
SPI/I2C
SPI/I2C
SPI/I2C,
USART
SPI/I2C
USART
Clock
Memory
Features
Parallel Slave Port
—
—
—
—
—
Interrupt Sources
3
7
7
10
10
I/O Pins
13
22
22
22
22
Voltage Range (Volts)
3.0-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
In-Circuit Serial Programming
Yes
Yes
Yes
Yes
Yes
Brown-out Reset
—
Yes
Yes
Yes
Yes
Packages
18-pin DIP, SO 28-pin SDIP,
SOIC, SSOP
28-pin SDIP,
SOIC, SSOP
28-pin SDIP, 28-pin SDIP,
SOIC
SOIC
PIC16C64A
Clock
Memory
PIC16C65A
PIC16CR65
PIC16C66
PIC16C67
20
20
20
20
20
20
EPROM Program Memory
(x14 words)
2K
—
4K
—
8K
8K
ROM Program Memory (x14
words)
—
2K
—
4K
—
—
Data Memory (bytes)
128
128
192
192
368
368
Timer Module(s)
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
1
1
2
2
2
2
Serial Port(s) (SPI/I2C, USART)
SPI/I2C
SPI/I2C
SPI/I2C,
USART
SPI/I2C,
USART
SPI/I2C,
USART
SPI/I2C,
USART
Parallel Slave Port
Yes
Yes
Yes
Yes
—
Yes
Interrupt Sources
8
8
11
11
10
11
I/O Pins
33
33
33
33
22
33
Voltage Range (Volts)
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
In-Circuit Serial Programming
Yes
Yes
Yes
Yes
Yes
Yes
Brown-out Reset
Yes
Yes
Yes
Yes
Yes
Yes
Packages
40-pin DIP; 40-pin DIP;
40-pin DIP;
40-pin DIP;
44-pin PLCC, 44-pin PLCC, 44-pin PLCC, 44-pin
MQFP, TQFP MQFP, TQFP MQFP, TQFP PLCC,
MQFP,
TQFP
Capture/Compare/PWM ModPeripherals ule(s)
Features
PIC16CR64
Maximum Frequency
of Operation (MHz)
28-pin SDIP, 40-pin DIP;
SOIC
44-pin
PLCC,
MQFP,
TQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability. All PIC16C6X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS30234D-page 6
 1997 Microchip Technology Inc.
PIC16C6X
2.0
PIC16C6X DEVICE VARIETIES
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C6X Product Identification System section at the end of this data sheet.
When placing orders, please use that page of the data
sheet to specify the correct part number.
For the PIC16C6X family of devices, there are four
device “types” as indicated in the device number:
1.
2.
3.
4.
2.1
C, as in PIC16C64. These devices have
EPROM type memory and operate over the
standard voltage range.
LC, as in PIC16LC64. These devices have
EPROM type memory and operate over an
extended voltage range.
CR, as in PIC16CR64. These devices have
ROM program memory and operate over the
standard voltage range.
LCR, as in PIC16LCR64. These devices have
ROM program memory and operate over an
extended voltage range.
UV Erasable Devices
The UV erasable version, offered in CERDIP package
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's PICSTART Plus and PRO MATE II
programmers both support programming of the
PIC16C6X.
2.2
One-Time-Programmable (OTP)
Devices
2.3
Quick-Turnaround-Production (QTP)
Devices
Microchip offers a QTP Programming Service for factory production orders. This service is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but
with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before production shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password, or ID number.
ROM devices do not allow serialization information in
the program memory space. The user may have this
information programmed in the data memory space.
For information on submitting ROM code, please contact your regional sales office.
2.5
Read Only Memory (ROM) Devices
Microchip offers masked ROM versions of several of
the highest volume parts, thus giving customers a low
cost option for high volume, mature products.
For information on submitting ROM code, please contact your regional sales office.
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications.
The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the
program memory, the configuration bits must also be
programmed.
 1997 Microchip Technology Inc.
DS30234D-page 7
PIC16C6X
NOTES:
DS30234D-page 8
 1997 Microchip Technology Inc.
PIC16C6X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16CXX family can be
attributed to a number of architectural features commonly found in RISC microprocessors. To begin with,
the PIC16CXX uses a Harvard architecture, in which,
program and data are accessed from separate memories using separate buses. This improves bandwidth
over traditional von Neumann architecture where program and data may be fetched from the same memory
using the same bus. Separating program and data busses further allows instructions to be sized differently
than 8-bit wide data words. Instruction opcodes are
14-bits wide making it possible to have all single word
instructions. A 14-bit wide program memory access
bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions execute in a single cycle (200 ns @ 20 MHz) except for
program branches.
The PIC16C61 addresses 1K x 14 of program memory.
The PIC16C62/62A/R62/64/64A/R64 address 2K x 14 of
program memory, and the PIC16C63/R63/65/65A/R65
devices address 4K x 14 of program memory. The
PIC16C66/67 address 8K x 14 program memory. All
program memory is internal.
The PIC16CXX device contains an 8-bit ALU and working register (W). The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions
between data in the working register and any register
file.
The ALU is 8-bits wide and capable of addition, subtraction, shift, and logical operations. Unless otherwise
mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically
one operand is the working register (W register), the
other operand is a file register or an immediate constant. In single operand instructions, the operand is
either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending upon the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. Bits C and DC
operate as a borrow and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
The PIC16CXX can directly or indirectly address its
register files or data memory. All special function registers including the program counter are mapped in
the data memory. The PIC16CXX has an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation on any register using any
addressing mode. This symmetrical nature and lack of
“special optimal situations” makes programming with
the PIC16CXX simple yet efficient, thus significantly
reducing the learning curve.
 1997 Microchip Technology Inc.
DS30234D-page 9
PIC16C6X
FIGURE 3-1:
PIC16C61 BLOCK DIAGRAM
13
EPROM
Program
Memory
Program
Bus
14
PORTA
RA0
RA1
RA2
RA3
RAM
File
Registers
36 x 8
8 Level Stack
(13-bit)
1K x 14
8
Data Bus
Program Counter
RAM Addr(1)
RA4/T0CKI
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
8
Indirect
Addr
FSR reg
RB0/INT
RB7:RB1
STATUS reg
8
Power-up
Timer
Instruction
Decode &
Control
Oscillator
Start-up Timer
Timing
Generation
Watchdog
Timer
Power-on
Reset
3
MUX
ALU
8
W reg
OSC1/CLKIN
OSC2/CLKOUT
Timer0
MCLR
VDD, VSS
Note 1: Higher order bits are from the STATUS register.
DS30234D-page 10
 1997 Microchip Technology Inc.
PIC16C6X
FIGURE 3-2:
PIC16C62/62A/R62/64/64A/R64 BLOCK DIAGRAM
13
Program
Bus
14
PORTA
RA0
RA1
RA2
RA3
RAM
File
Registers
128 x 8
8 Level Stack
(13-bit)
2K x 14
8
Data Bus
Program Counter
EPROM/
ROM
Program
Memory
RAM Addr(1)
RA4/T0CKI
RA5/SS
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
8
RB0/INT
Indirect
Addr
RB7:RB1
FSR reg
STATUS reg
8
PORTC
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
3
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset(3)
MCLR
RC0/T1OSO/T1CKI(4)
RC1/T1OSI(4)
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7
MUX
ALU
8
W reg
PORTD
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
VDD, VSS
Parallel Slave
Port
PORTE
RE0/RD
Timer1
Timer2
RE1/WR
CCP1
RE2/CS
(Note 2)
Timer0
Note 1:
2:
3:
4:
Synchronous
Serial Port
Higher order bits are from the STATUS register.
PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C62/62A/R62.
Brown-out Reset is not available on the PIC16C62/64.
Pin functions T1OSI and T1OSO are swapped on the PIC16C62/64.
 1997 Microchip Technology Inc.
DS30234D-page 11
PIC16C6X
FIGURE 3-3:
PIC16C63/R63/65/65A/R65 BLOCK DIAGRAM
13
Program
Memory
Program
Bus
14
PORTA
RA0
RA1
RA2
RA3
RA4/T0CKI
RAM
File
Registers
192 x 8
8 Level Stack
(13-bit)
4K x 14
8
Data Bus
Program Counter
EPROM
RAM Addr(1)
RA5/SS
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
8
RB0/INT
Indirect
Addr
RB7:RB1
FSR reg
STATUS reg
8
PORTC
Power-up
Timer
Instruction
Decode &
Control
Oscillator
Start-up Timer
Timing
Generation
Watchdog
Timer
OSC1/CLKIN
OSC2/CLKOUT
Power-on
Reset
3
MUX
ALU
8
W reg
PORTD
Brown-out
Reset(3)
MCLR
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
VDD, VSS
Parallel Slave
Port
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
PORTE
RE0/RD
RE1/WR
Timer0
Timer1
Timer2
RE2/CS
(Note 2)
USART
Synchronous
Serial Port
CCP1
CCP2
Note 1: Higher order bits are from the STATUS register.
2: PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C63/R63.
3: Brown-out Reset is not available on the PIC16C65.
DS30234D-page 12
 1997 Microchip Technology Inc.
PIC16C6X
FIGURE 3-4:
PIC16C66/67 BLOCK DIAGRAM
13
Program
Memory
Program
Bus
14
PORTA
RA0
RA1
RA2
RA3
RA4/T0CKI
RAM
File
Registers
368 x 8
8 Level Stack
(13-bit)
8K x 14
8
Data Bus
Program Counter
EPROM
RAM Addr(1)
RA5/SS
PORTB
9
Addr MUX
Instruction reg
Direct Addr
7
8
RB0/INT
Indirect
Addr
RB7:RB1
FSR reg
STATUS reg
8
PORTC
Power-up
Timer
Instruction
Decode &
Control
Oscillator
Start-up Timer
Timing
Generation
Watchdog
Timer
OSC1/CLKIN
OSC2/CLKOUT
Power-on
Reset
3
MUX
ALU
8
W reg
PORTD
Brown-out
Reset
MCLR
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
VDD, VSS
Parallel Slave
Port
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
PORTE
RE0/RD
RE1/WR
Timer0
Timer1
Timer2
RE2/CS
(Note 2)
USART
Synchronous
Serial Port
CCP1
CCP2
Note 1: Higher order bits are from the STATUS register.
2: PORTD, PORTE and the Parallel Slave Port are not available on the PIC16C66.
 1997 Microchip Technology Inc.
DS30234D-page 13
PIC16C6X
TABLE 3-1:
PIC16C61 PINOUT DESCRIPTION
DIP
Pin#
SOIC
Pin#
Pin Type
OSC1/CLKIN
16
16
I
OSC2/CLKOUT
15
15
O
—
Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, the pin outputs CLKOUT which has
1/4 the frequency of OSC1, and denotes the instruction cycle rate.
MCLR/VPP
4
4
I/P
ST
Master clear reset input or programming voltage input. This pin is an
active low reset to the device.
PORTA is a bi-directional I/O port.
RA0
RA1
RA2
RA3
RA4/T0CKI
17
18
1
2
3
17
18
1
2
3
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
Pin Name
Buffer
Type
Description
ST/CMOS(1) Oscillator crystal input/external clock source input.
RA4 can also be the clock input to the Timer0 timer/counter.
Output is open drain type.
PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0 can also be the external interrupt pin.
6
6
I/O
TTL/ST(2)
7
7
I/O
TTL
8
8
I/O
TTL
9
9
I/O
TTL
10
10
I/O
TTL
Interrupt on change pin.
11
11
I/O
TTL
Interrupt on change pin.
12
12
I/O
TTL/ST(3)
Interrupt on change pin. Serial programming clock.
13
13
I/O
TTL/ST(3)
Interrupt on change pin. Serial programming data.
5
5
P
—
Ground reference for logic and I/O pins.
14
14
P
—
Positive supply for logic and I/O pins.
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
2: This buffer is a Schmitt Trigger input when configured as the external interrupt.
3: This buffer is a Schmitt Trigger input when used in serial programming mode.
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
VSS
VDD
Legend: I = input
DS30234D-page 14
 1997 Microchip Technology Inc.
PIC16C6X
TABLE 3-2:
PIC16C62/62A/R62/63/R63/66 PINOUT DESCRIPTION
Pin#
Pin Type
Buffer
Type
OSC1/CLKIN
9
I
ST/CMOS(3)
OSC2/CLKOUT
10
O
—
Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the pin outputs CLKOUT which
has 1/4 the frequency of OSC1, and denotes the instruction cycle
rate.
MCLR/VPP
1
I/P
ST
Master clear reset input or programming voltage input. This pin is
an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0
RA1
RA2
RA3
RA4/T0CKI
2
3
4
5
6
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
RA5/SS
7
I/O
TTL
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL/ST(4)
TTL
TTL
TTL
TTL
TTL
TTL/ST(5)
TTL/ST(5)
Pin Name
Description
Oscillator crystal input/external clock source input.
RA4 can also be the clock input to the Timer0 timer/counter.
Output is open drain type.
RA5 can also be the slave select for the synchronous serial
port.
PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0 can also be the external interrupt pin.
Interrupt on change pin.
Interrupt on change pin.
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
11
I/O
ST
RC0 can also be the Timer1 oscillator output(1) or Timer1
RC0/T1OSO(1)/T1CKI
clock input.
12
I/O
ST
RC1 can also be the Timer1 oscillator input(1) or Capture2
RC1/T1OSI(1)/CCP2(2)
input/Compare2 output/PWM2 output(2).
RC2/CCP1
13
I/O
ST
RC2 can also be the Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
14
I/O
ST
RC3 can also be the synchronous serial clock input/output
for both SPI and I2C modes.
RC4/SDI/SDA
15
I/O
ST
RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO
16
I/O
ST
RC5 can also be the SPI Data Out (SPI mode).
17
I/O
ST
RC6 can also be the USART Asynchronous Transmit(2) or
RC6/TX/CK(2)
Synchronous Clock(2).
(2)
18
I/O
ST
RC7 can also be the USART Asynchronous Receive(2) or
RC7/RX/DT
Synchronous Data(2).
VSS
8,19
P
—
Ground reference for logic and I/O pins.
VDD
20
P
—
Positive supply for logic and I/O pins.
Legend: I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
Note 1: Pin functions T1OSO and T1OSI are reversed on the PIC16C62.
2: The USART and CCP2 are not available on the PIC16C62/62A/R62.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
4: This buffer is a Schmitt Trigger input when configured as the external interrupt.
5: This buffer is a Schmitt Trigger input when used in serial programming mode.
 1997 Microchip Technology Inc.
DS30234D-page 15
PIC16C6X
TABLE 3-3:
PIC16C64/64A/R64/65/65A/R65/67 PINOUT DESCRIPTION
DIP
Pin#
PLCC
Pin#
TQFP
MQFP
Pin#
Pin
Type
OSC1/CLKIN
13
14
30
I
OSC2/CLKOUT
14
15
31
O
—
Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the
instruction cycle rate.
MCLR/VPP
1
2
18
I/P
ST
Master clear reset input or programming voltage input. This
pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0
RA1
RA2
RA3
RA4/T0CKI
2
3
4
5
6
3
4
5
6
7
19
20
21
22
23
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
RA5/SS
7
8
24
I/O
TTL
RB0/INT
RB1
RB2
RB3
RB4
RB5
RB6
RB7
33
34
35
36
37
38
39
40
36
37
38
39
41
42
43
44
8
9
10
11
14
15
16
17
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL/ST(4)
TTL
TTL
TTL
TTL
TTL
TTL/ST(5)
TTL/ST(5)
Pin Name
Buffer
Type
Description
ST/CMOS(3) Oscillator crystal input/external clock source input.
RA4 can also be the clock input to the Timer0
timer/counter. Output is open drain type.
RA5 can also be the slave select for the synchronous
serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0 can also be the external interrupt pin.
Interrupt on change pin.
Interrupt on change pin.
Interrupt on change pin. Serial programming clock.
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO(1)/T1CKI
15
16
32
I/O
ST
RC0 can also be the Timer1 oscillator output(1) or
Timer1 clock input.
RC1/T1OSI(1)/CCP2(2)
16
18
35
I/O
ST
RC1 can also be the Timer1 oscillator input(1) or
Capture2 input/Compare2 output/PWM2 output(2).
RC2/CCP1
17
19
36
I/O
ST
RC2 can also be the Capture1 input/Compare1 output/PWM1 output.
RC3/SCK/SCL
18
20
37
I/O
ST
RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes.
RC4/SDI/SDA
23
25
42
I/O
ST
RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO
24
26
43
I/O
ST
RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK(2)
25
27
44
I/O
ST
RC6 can also be the USART Asynchronous Transmit(2)
or Synchronous Clock(2).
(2)
RC7/RX/DT
26
29
1
I/O
ST
RC7 can also be the USART Asynchronous Receive(2)
or Synchronous Data(2).
Legend: I = input
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
Note 1: Pin functions T1OSO and T1OSI are reversed on the PIC16C64.
2: CCP2 and the USART are not available on the PIC16C64/64A/R64.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
4: This buffer is a Schmitt Trigger input when configured as the external interrupt.
5: This buffer is a Schmitt Trigger input when used in serial programming mode.
6: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
DS30234D-page 16
 1997 Microchip Technology Inc.
PIC16C6X
TABLE 3-3:
Pin Name
PIC16C64/64A/R64/65/65A/R65/67 PINOUT DESCRIPTION (Cont.’d)
DIP
Pin#
PLCC
Pin#
TQFP
MQFP
Pin#
Pin
Type
Buffer
Type
Description
PORTD can be a bi-directional I/O port or parallel slave port
for interfacing to a microprocessor bus.
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE0/RD
RE1/WR
RE2/CS
VSS
VDD
NC
19
20
21
22
27
28
29
30
21
22
23
24
30
31
32
33
38
39
40
41
2
3
4
5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL(6)
ST/TTL(6)
ST/TTL(6)
ST/TTL(6)
ST/TTL(6)
ST/TTL(6)
ST/TTL(6)
ST/TTL(6)
8
9
10
12,31
11,32
—
9
10
11
13,34
12,35
1,17,
28,40
25
26
27
6,29
7,28
12,13,
33,34
I/O
I/O
I/O
P
P
—
ST/TTL(6)
ST/TTL(6)
ST/TTL(6)
—
—
—
PORTE is a bi-directional I/O port.
RE0 can also be read control for the parallel slave port.
RE1 can also be write control for the parallel slave port.
RE2 can also be select control for the parallel slave port.
Ground reference for logic and I/O pins.
Positive supply for logic and I/O pins.
These pins are not internally connected. These pins should
be left unconnected.
Legend: I = input
Note 1:
2:
3:
4:
5:
6:
O = output
I/O = input/output
P = power
— = Not used
TTL = TTL input
ST = Schmitt Trigger input
Pin functions T1OSO and T1OSI are reversed on the PIC16C64.
CCP2 and the USART are not available on the PIC16C64/64A/R64.
This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
This buffer is a Schmitt Trigger input when configured as the external interrupt.
This buffer is a Schmitt Trigger input when used in serial programming mode.
This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
 1997 Microchip Technology Inc.
DS30234D-page 17
PIC16C6X
3.1
Clocking Scheme/Instruction Cycle
3.2
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1
through Q4. The clock and instruction execution flow is
shown in Figure 3-5.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3, and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-5:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
Phase
Clock
Q3
Q4
PC
(Program counter)
OSC2/CLKOUT
(RC mode)
PC
PC+1
Fetch INST (PC)
Execute INST (PC-1)
EXAMPLE 3-1:
1. MOVLW 55h
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
Tcy0
Tcy1
Fetch 1
Execute 1
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
Fetch 2
Tcy2
Tcy3
Tcy4
Tcy5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS30234D-page 18
 1997 Microchip Technology Inc.
PIC16C6X
4.0
MEMORY ORGANIZATION
FIGURE 4-2:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Program Memory Organization
The PIC16C6X family has a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. The amount of program memory available to
each device is listed below:
Device
PIC16C61
PIC16C62
PIC16C62A
PIC16CR62
PIC16C63
PIC16CR63
PIC16C64
PIC16C64A
PIC16CR64
PIC16C65
PIC16C65A
PIC16CR65
PIC16C66
PIC16C67
Program
Memory
Address Range
1K x 14
2K x 14
2K x 14
2K x 14
4K x 14
4K x 14
2K x 14
2K x 14
2K x 14
4K x 14
4K x 14
4K x 14
8K x 14
8K x 14
0000h-03FFh
0000h-07FFh
0000h-07FFh
0000h-07FFh
0000h-0FFFh
0000h-0FFFh
0000h-07FFh
0000h-07FFh
0000h-07FFh
0000h-0FFFh
0000h-0FFFh
0000h-0FFFh
0000h-1FFFh
0000h-1FFFh
For those devices with less than 8K program memory,
accessing a location above the physically implemented
address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1:
0000h
Peripheral Interrupt Vector
0004h
0005h
On-chip Program
Memory
0000h
Peripheral Interrupt Vector
0004h
0005h
On-chip Program
Memory
1FFFh
FIGURE 4-3:
PIC16C63/R63/65/65A/R65
PROGRAM MEMORY MAP
AND STACK
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
•
•
•
Stack Level 8
User Memory
Space
Reset Vector
Reset Vector
07FFh
0800h
PIC16C61 PROGRAM
MEMORY MAP AND STACK
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
•
•
•
Stack Level 8
User Memory
Space
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
•
•
•
Stack Level 8
User Memory
Space
4.1
PIC16C62/62A/R62/64/64A/
R64 PROGRAM MEMORY
MAP AND STACK
Reset Vector
0000h
Peripheral Interrupt Vector
0004h
0005h
On-chip Program
Memory (Page 0)
07FFh
0800h
On-chip Program
Memory (Page 1)
0FFFh
1000h
03FFh
0400h
1FFFh
1FFFh
 1997 Microchip Technology Inc.
DS30234D-page 19
PIC16C6X
FIGURE 4-4:
PIC16C66/67 PROGRAM
MEMORY MAP AND STACK
User Memory
Space
PC<12:0>
13
CALL, RETURN
RETFIE, RETLW
Stack Level 1
•
•
•
Stack Level 8
For the PIC16C61, general purpose register locations
8Ch-AFh of Bank 1 are not physically implemented.
These locations are mapped into 0Ch-2Fh of Bank 0.
FIGURE 4-5:
PIC16C61 REGISTER FILE
MAP
File Address
Reset Vector
0000h
Peripheral Interrupt Vector
0004h
0005h
On-chip Program
Memory (Page 0)
07FFh
0800h
On-chip Program
Memory (Page 1)
0FFFh
1000h
On-chip Program
Memory (Page 2)
(1)
INDF
00h
INDF
01h
TMR0
OPTION
81h
02h
PCL
PCL
82h
03h
STATUS
STATUS
83h
04h
FSR
FSR
84h
05h
PORTA
TRISA
85h
06h
PORTB
TRISB
86h
80h
07h
87h
08h
88h
89h
09h
0Ah
0Bh
17FFh
1800h
File Address
(1)
PCLATH
PCLATH
8Ah
INTCON
INTCON
8Bh
8Ch
0Ch
On-chip Program
Memory (Page 3)
General
Purpose
Register
Mapped
in Bank 0(2)
1FFFh
4.2
Data Memory Organization
2Fh
AFh
30h
B0h
7Fh
FFh
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
RP1:RP0 (STATUS<6:5>)
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2
= 11 → Bank3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.
4.2.1
Bank 0
Bank 1
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.
2: These locations are unimplemented in
Bank 1. Any access to these locations will
access the corresponding Bank 0 register.
GENERAL PURPOSE REGISTERS
These registers are accessed either directly or indirectly through the File Select Register (FSR)
(Section 4.5).
DS30234D-page 20
 1997 Microchip Technology Inc.
PIC16C6X
FIGURE 4-6:
PIC16C62/62A/R62/64/64A/
R64 REGISTER FILE MAP
File Address
File Address
00h
INDF(1)
(1)
01h
TMR0
OPTION
02h
PCL
PCL
03h
STATUS
STATUS
INDF
FIGURE 4-7:
PIC16C63/R63/65/65A/R65
REGISTER FILE MAP
File Address
File Address
80h
00h
INDF(1)
(1)
81h
01h
TMR0
OPTION
81h
82h
02h
PCL
PCL
82h
83h
03h
STATUS
STATUS
83h
FSR
FSR
84h
INDF
80h
04h
FSR
FSR
84h
04h
05h
PORTA
TRISA
85h
05h
PORTA
TRISA
85h
06h
PORTB
TRISB
86h
06h
PORTB
TRISB
86h
07h
PORTC
TRISC
87h
07h
PORTC
TRISC
87h
08h
PORTD(2)
TRISD(2)
88h
08h
PORTD(2)
TRISD(2)
88h
PORTE(2)
TRISE(2)
89h
PORTE(2)
TRISE(2)
89h
0Ah
PCLATH
PCLATH
8Ah
0Ah
PCLATH
PCLATH
8Ah
0Bh
INTCON
INTCON
8Bh
0Bh
INTCON
INTCON
8Bh
0Ch
PIR1
PIE1
8Ch
09h
0Dh
PCON
09h
0Ch
PIR1
PIE1
8Ch
8Dh
0Dh
PIR2
PIE2
8Dh
8Eh
0Eh
TMR1L
PCON
8Eh
0Eh
TMR1L
0Fh
TMR1H
8Fh
0Fh
TMR1H
8Fh
10h
T1CON
90h
10h
T1CON
90h
11h
TMR2
91h
11h
TMR2
91h
12h
T2CON
PR2
92h
12h
T2CON
PR2
92h
13h
SSPBUF
SSPADD
93h
13h
SSPBUF
SSPADD
93h
SSPSTAT
94h
14h
SSPCON
SSPSTAT
94h
14h
SSPCON
15h
CCPR1L
95h
15h
CCPR1L
95h
16h
CCPR1H
96h
16h
CCPR1H
96h
17h
CCP1CON
97h
17h
CCP1CON
97h
98h
18h
RCSTA
TXSTA
98h
19h
TXREG
SPBRG
99h
1Ah
RCREG
9Ah
1Bh
CCPR2L
9Bh
9Fh
1Ch
CCPR2H
9Ch
A0h
1Dh
CCP2CON
9Dh
18h
1Fh
20h
General
Purpose
Register
7Fh
General
Purpose
Register
BFh
C0h
FFh
Bank 1
Bank 0
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.
2: PORTD and PORTE are not available on
the PIC16C62/62A/R62.
 1997 Microchip Technology Inc.
1Eh
9Eh
1Fh
9Fh
20h
7Fh
General
Purpose
Register
General
Purpose
Register
A0h
FFh
Bank 1
Bank 0
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register
2: PORTD and PORTE are not available on
the PIC16C63/R63.
DS30234D-page 21
PIC16C6X
FIGURE 4-8:
PIC16C66/67 DATA MEMORY MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD (1)
PORTE (1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
General
Purpose
Register
7Fh
*
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD (1)
TRISE (1)
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
General
Purpose
Register
16 Bytes
A0h
General
Purpose
Register
80 Bytes
96 Bytes
Bank 0
Indirect addr.(*)
accesses
70h-7Fh
in Bank 0
Bank 1
EFh
F0h
FFh
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
in Bank 0
Bank 2
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
16Fh
170h
17Fh
Indirect addr.(*)
OPTION
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
General
Purpose
Register
16 Bytes
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
General
Purpose
Register
80 Bytes
accesses
70h-7Fh
in Bank 0
Bank 3
1EFh
1F0h
1FFh
Unimplemented data memory locations, read as '0'.
Not a physical register.
These registers are not implemented on the PIC16C66.
Note:
DS30234D-page 22
The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require
relocation of data memory usage in the user application code if upgrading to the PIC16C66/67.
 1997 Microchip Technology Inc.
PIC16C6X
4.2.2
SPECIAL FUNCTION REGISTERS:
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
TABLE 4-1:
Address Name
The special function registers can be classified into two
sets (core and peripheral). The registers associated
with the “core” functions are described in this section
and those related to the operation of the peripheral features are described in the section of that peripheral feature.
SPECIAL FUNCTION REGISTERS FOR THE PIC16C61
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR
Value on
all other
resets(3)
Bank 0
00h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
02h(1)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h(1)
STATUS
04h(1)
FSR
05h
PORTA
06h
PORTB
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
—
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
PORTB Data Latch when written: PORTB pins when read
---x xxxx ---u uuuu
xxxx xxxx uuuu uuuu
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
0Ah(1,2)
PCLATH
—
—
—
0Bh(1)
INTCON
GIE
—
T0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
---0 0000 ---0 0000
RBIF
0-00 000x 0-00 000u
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
Bank 1
80h(1)
INDF
81h
OPTION
(1)
82h
PCL
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
STATUS
(1)
84h
FSR
85h
TRISA
86h
TRISB
87h
–
Unimplemented
—
—
88h
–
Unimplemented
—
—
–
Unimplemented
—
—
89h
(4)
0000 0000 0000 0000
(1)
83h
IRP(4)
1111 1111 1111 1111
RP1
RP0
Z
DC
C
—
—
—
PCLATH
—
—
—
INTCON
GIE
—
T0IE
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
---1 1111 ---1 1111
PORTB Data Direction Control Register
(1)
8Bh
PD
Indirect data memory address pointer
(1,2)
8Ah
TO
1111 1111 1111 1111
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF
---0 0000 ---0 0000
0-00 000x
0-00 000u
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented locations read as '0'.
Shaded locations are unimplemented and read as ‘0’
Note 1: These registers can be addressed from either bank.
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C61, always maintain these bits clear.
 1997 Microchip Technology Inc.
DS30234D-page 23
PIC16C6X
TABLE 4-2:
SPECIAL FUNCTION REGISTERS FOR THE PIC16C62/62A/R62
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Bank 0
00h(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
02h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h(1)
STATUS
04h(1)
FSR
05h
PORTA
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
01h
(1)
INDF
IRP(5)
RP1(5)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
--xx xxxx --uu uuuu
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
(1,2)
PCLATH
—
—
—
(1)
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
(6)
(6)
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
00-- 0000 00-- 0000
0Ah
Write Buffer for the upper 5 bits of the Program Counter
0Dh
—
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
10h
T1CON
11h
TMR2
12h
T2CON
13h
SSPBUF
14h
SSPCON
15h
CCPR1L
Capture/Compare/PWM1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
18h-1Fh
—
Unimplemented
---0 0000 ---0 0000
—
—
—
xxxx xxxx uuuu uuuu
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
TOUTPS3 TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0 -000 0000 -000 0000
SSPM2
SSPM1
Timer2 module’s register
—
SSPOV
—
Unimplemented
—
--00 0000 --uu uuuu
0000 0000 0000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
—
xxxx xxxx uuuu uuuu
SSPEN
CCP1X
CKP
CCP1Y
SSPM3
CCP1M3
xxxx xxxx uuuu uuuu
CCP1M2
CCP1M1
SSPM0
CCP1M0
0000 0000 0000 0000
--00 0000 --00 0000
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C62, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C62/62A/R62, always maintain these bits clear.
6: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C62/62A/R62, always maintain these bits clear.
DS30234D-page 24
 1997 Microchip Technology Inc.
PIC16C6X
TABLE 4-2:
Address Name
SPECIAL FUNCTION REGISTERS FOR THE PIC16C62/62A/R62 (Cont.’d)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Bank 1
80h(1)
INDF
81h
OPTION
82h(1)
PCL
83h(1)
STATUS
84h(1)
FSR
85h
TRISA
86h
TRISB
87h
TRISC
88h
—
Unimplemented
—
—
—
Unimplemented
—
—
89h
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP(5)
RP1(5)
RP0
TO
—
1111 1111 1111 1111
0000 0000 0000 0000
PD
Z
DC
C
0001 1xxx 000q quuu
Indirect data memory address pointer
—
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
--11 1111 --11 1111
PORTB Data Direction Register
1111 1111 1111 1111
PORTC Data Direction Register
1111 1111 1111 1111
(1,2)
PCLATH
—
—
—
(1)
8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
8Ch
PIE1
(6)
(6)
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
00-- 0000 00-- 0000
—
—
—
—
—
POR
8Ah
---0 0000 ---0 0000
Write Buffer for the upper 5 bits of the Program Counter
8Dh
—
8Eh
PCON
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
91h
—
Unimplemented
—
—
92h
PR2
93h
SSPADD
94h
SSPSTAT
95h-9Fh
Unimplemented
—
—
(4)
BOR
Timer2 Period Register
—
Synchronous Serial Port
—
Unimplemented
—
—
---- --qq ---- --uu
1111 1111 1111 1111
(I2
0000 0000 0000 0000
C mode) Address Register
D/A
P
S
R/W
UA
BF
--00 0000 --00 0000
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C62, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C62/62A/R62, always maintain these bits clear.
6: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C62/62A/R62, always maintain these bits clear.
 1997 Microchip Technology Inc.
DS30234D-page 25
PIC16C6X
TABLE 4-3:
Address Name
SPECIAL FUNCTION REGISTERS FOR THE PIC16C63/R63
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Bank 0
00h(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
02h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h(1)
STATUS
04h(1)
FSR
05h
PORTA
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
01h
(1)
INDF
IRP(4)
RP1(4)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
--xx xxxx --uu uuuu
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
(1,2)
PCLATH
—
—
—
(1)
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
(5)
(5)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
0Dh
PIR2
—
—
—
—–
—
—
—
CCP2IF
---- ---0 ---- ---0
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
10h
T1CON
11h
TMR2
12h
T2CON
13h
SSPBUF
14h
SSPCON
15h
CCPR1L
Capture/Compare/PWM1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
18h
RCSTA
19h
TXREG
USART Transmit Data Register
0000 0000 0000 0000
1Ah
RCREG
USART Receive Data Register
0000 0000 0000 0000
1Bh
CCPR2L
Capture/Compare/PWM2 (LSB)
xxxx xxxx uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM2 (MSB)
0Ah
1Dh
1Eh-1Fh
CCP2CON
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
TOUTPS3 TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0 -000 0000 -000 0000
SSPM2
SSPM1
Timer2 module’s register
—
SSPOV
--00 0000 --uu uuuu
0000 0000 0000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
---0 0000 ---0 0000
SSPEN
CKP
SSPM3
xxxx xxxx uuuu uuuu
SSPM0
0000 0000 0000 0000
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000 --00 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
—
Unimplemented
—
CCP2X
xxxx xxxx uuuu uuuu
CCP2Y
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000 --00 0000
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The IRP and RP1 bits are reserved on the PIC16C63/R63, always maintain these bits clear.
5: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C63/R63, always maintain these bits clear.
 1997 Microchip Technology Inc.
DS30234D-page 26
PIC16C6X
TABLE 4-3:
Address Name
SPECIAL FUNCTION REGISTERS FOR THE PIC16C63/R63 (Cont.’d)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Bank 1
80h(1)
INDF
81h
OPTION
82h(1)
PCL
83h(1)
STATUS
84h(1)
FSR
85h
TRISA
86h
TRISB
87h
TRISC
88h
—
Unimplemented
—
—
—
Unimplemented
—
—
89h
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP(4)
RP1(4)
RP0
TO
—
1111 1111 1111 1111
0000 0000 0000 0000
PD
Z
DC
C
Indirect data memory address pointer
—
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
--11 1111 --11 1111
PORTB Data Direction Register
1111 1111 1111 1111
PORTC Data Direction Register
1111 1111 1111 1111
(1,2)
PCLATH
—
—
—
(1)
8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
8Ch
PIE1
(5)
(5)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0 ---- ---0
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
—
Unimplemented
—
—
8Ah
91h
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
92h
PR2
Timer2 Period Register
1111 1111 1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000 0000 0000
94h
SSPSTAT
—
—
D/A
P
S
R/W
UA
BF
--00 0000 --00 0000
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
(2)
TXSTA
(2)
SPBRG
98h
99h
CSRC
TX9
TXEN
Baud Rate Generator Register
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
—
Unimplemented
—
—
9Fh
—
Unimplemented
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The IRP and RP1 bits are reserved on the PIC16C63/R63, always maintain these bits clear.
5: PIE1<7:6> and PIR1<7:6> are reserved on the PIC16C63/R63, always maintain these bits clear.
 1997 Microchip Technology Inc.
DS30234D-page 27
PIC16C6X
TABLE 4-4:
SPECIAL FUNCTION REGISTERS FOR THE PIC16C64/64A/R64
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Bank 0
00h(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
02h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h(1)
STATUS
04h(1)
FSR
05h
PORTA
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
08h
PORTD
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx uuuu uuuu
01h
(1)
09h
INDF
IRP(5)
RP1(5)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
PORTE
—
—
—
(1,2)
PCLATH
—
—
—
(1)
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
PSPIF
(6)
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
00-- 0000 00-- 0000
0Ah
—
—
RE2
RE1
--xx xxxx --uu uuuu
RE0
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
0Dh
—
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h
T1CON
11h
TMR2
Unimplemented
---- -xxx ---- -uuu
—
—
—
T1CKPS1
—
TOUTPS3 TOUTPS2
12h
T2CON
SSPBUF
14h
SSPCON
15h
CCPR1L
Capture/Compare/PWM1 (LSB)
16h
CCPR1H
Capture/Compare/PWM1 (MSB)
17h
CCP1CON
—
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0 -000 0000 -000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
—
Unimplemented
—
--00 0000 --uu uuuu
0000 0000 0000 0000
13h
18h-1Fh
T1CKPS0
Timer2 module’s register
—
SSPEN
CCP1X
CKP
SSPM3
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
SSPM0
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000 --00 0000
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C64, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C64/64A/R64, always maintain these bits clear.
6: PIE1<6> and PIR1<6> are reserved on the PIC16C64/64A/R64, always maintain these bits clear.
DS30234D-page 28
 1997 Microchip Technology Inc.
PIC16C6X
TABLE 4-4:
Address Name
SPECIAL FUNCTION REGISTERS FOR THE PIC16C64/64A/R64 (Cont.’d)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Bank 1
80h(1)
INDF
81h
OPTION
82h(1)
PCL
83h(1)
STATUS
84h(1)
FSR
85h
TRISA
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
88h
TRISD
PORTD Data Direction Register
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP(5)
RP1(5)
RP0
TO
—
1111 1111 1111 1111
0000 0000 0000 0000
PD
Z
DC
C
0001 1xxx 000q quuu
Indirect data memory address pointer
—
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
--11 1111 --11 1111
1111 1111 1111 1111
—
TRISE
OBF
IBOV
8Ah
PCLATH
—
—
—
8Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
8Ch
PIE1
PSPIE
(6)
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
00-- 0000 00-- 0000
89h
(1,2)
8Dh
—
PSPMODE
PORTE Data Direction Bits
IBF
0000 -111 0000 -111
---0 0000 ---0 0000
Write Buffer for the upper 5 bits of the Program Counter
Unimplemented
—
(4)
—
8Eh
PCON
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
—
Unimplemented
—
—
91h
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
92h
PR2
Timer2 Period Register
1111 1111 1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000 0000 0000
94h
SSPSTAT
95h-9Fh
—
—
Unimplemented
—
D/A
P
S
R/W
UA
BF
--00 0000 --00 0000
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C64, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C64/64A/R64, always maintain these bits clear.
6: PIE1<6> and PIR1<6> are reserved on the PIC16C64/64A/R64, always maintain these bits clear.
 1997 Microchip Technology Inc.
DS30234D-page 29
PIC16C6X
TABLE 4-5:
SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Bank 0
00h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
(1)
02h
(1)
STATUS
(1)
04h
FSR
05h
PORTA
06h
PORTB
03h
IRP(5)
(5)
RP0
RP1
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
--xx xxxx --uu uuuu
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
08h
PORTD
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx uuuu uuuu
09h
PORTE
—
—
—
0Ah(1,2)
PCLATH
—
—
—
0Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
PSPIF
(6)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
0Dh
PIR2
—
—
—
—–
—
—
—
CCP2IF
---- ---0 ---- ---0
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h
T1CON
11h
TMR2
—
—
T1CKPS1
—
—
RE2
RE1
RE0
Write Buffer for the upper 5 bits of the Program Counter
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
Timer2 module’s register
---0 0000 ---0 0000
--00 0000 --uu uuuu
0000 0000 0000 0000
12h
T2CON
13h
SSPBUF
14h
SSPCON
15h
CCPR1L
Capture/Compare/PWM1 (LSB)
16h
CCPR1H
Capture/Compare/PWM1 (MSB)
17h
CCP1CON
18h
RCSTA
19h
TXREG
USART Transmit Data Register
0000 0000 0000 0000
1Ah
RCREG
USART Receive Data Register
0000 0000 0000 0000
1Bh
CCPR2L
Capture/Compare/PWM2 (LSB)
xxxx xxxx uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM2 (MSB)
xxxx xxxx uuuu uuuu
1Dh
CCP2CON
1Eh-1Fh
—
—
---- -xxx ---- -uuu
TOUTPS3 TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0 -000 0000 -000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
SSPEN
CKP
SSPM3
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
SSPM0
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000 --00 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
—
Unimplemented
—
CCP2X
CCP2Y
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000 --00 0000
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C65, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C65/65A/R65, always maintain these bits clear.
6: PIE1<6> and PIR1<6> are reserved on the PIC16C65/65A/R65, always maintain these bits clear.
DS30234D-page 30
 1997 Microchip Technology Inc.
PIC16C6X
TABLE 4-5:
Address Name
SPECIAL FUNCTION REGISTERS FOR THE PIC16C65/65A/R65 (Cont.’d)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Bank 1
80h(1)
INDF
81h
OPTION
82h(1)
PCL
83h(1)
STATUS
84h(1)
FSR
85h
TRISA
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
88h
TRISD
PORTD Data Direction Register
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP(5)
RP1(5)
RP0
TO
—
1111 1111 1111 1111
0000 0000 0000 0000
PD
Z
DC
C
Indirect data memory address pointer
—
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
--11 1111 --11 1111
1111 1111 1111 1111
—
TRISE
OBF
IBOV
8Ah
PCLATH
—
—
—
8Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
8Ch
PIE1
PSPIE
(6)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0 ---- ---0
8Eh
PCON
—
—
—
—
—
—
POR
BOR(4)
---- --qq ---- --uu
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
—
Unimplemented
—
—
89h
(1,2)
91h
PSPMODE
PORTE Data Direction Bits
IBF
0000 -111 0000 -111
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
92h
PR2
Timer2 Period Register
1111 1111 1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000 0000 0000
94h
SSPSTAT
—
—
D/A
P
S
R/W
UA
BF
--00 0000 --00 0000
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
TXSTA
99h
SPBRG
CSRC
TX9
TXEN
Baud Rate Generator Register
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
—
Unimplemented
—
—
9Fh
—
Unimplemented
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: The BOR bit is reserved on the PIC16C65, always maintain this bit set.
5: The IRP and RP1 bits are reserved on the PIC16C65/65A/R65, always maintain these bits clear.
6: PIE1<6> and PIR1<6> are reserved on the PIC16C65/65A/R65, always maintain these bits clear.
 1997 Microchip Technology Inc.
DS30234D-page 31
PIC16C6X
TABLE 4-6:
SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Bank 0
00h(1)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
02h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h(1)
STATUS
04h(1)
FSR
05h
PORTA
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
07h
PORTC
PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
(5)
PORTD
PORTD Data Latch when written: PORTD pins when read
xxxx xxxx uuuu uuuu
(5)
PORTE
—
—
—
(1,2)
PCLATH
—
—
—
(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
(4)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000 0000 0000
—
—
—–
—
—
—
CCP2IF
---- ---0 ---- ---0
01h
(1)
08h
09h
0Ah
0Bh
INDF
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
(6)
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Latch when written: PORTA pins when read
—
—
RE2
RE1
--xx xxxx --uu uuuu
RE0
Write Buffer for the upper 5 bits of the Program Counter
---- -xxx ---- -uuu
---0 0000 ---0 0000
0Ch
PIR1
0Dh
PIR2
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
10h
T1CON
11h
TMR2
12h
T2CON
13h
SSPBUF
14h
SSPCON
15h
CCPR1L
Capture/Compare/PWM1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
18h
RCSTA
19h
TXREG
USART Transmit Data Register
0000 0000 0000 0000
1Ah
RCREG
USART Receive Data Register
0000 0000 0000 0000
1Bh
CCPR2L
Capture/Compare/PWM2 (LSB)
xxxx xxxx uuuu uuuu
1Ch
CCPR2H
Capture/Compare/PWM2 (MSB)
xxxx xxxx uuuu uuuu
1Dh
CCP2CON
1Eh-1Fh
—
PSPIF
—
—
—
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
TOUTPS3 TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0 -000 0000 -000 0000
SSPM2
SSPM1
Timer2 module’s register
—
0000 0000 0000 0000
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL
SSPOV
--00 0000 --uu uuuu
SSPEN
CKP
SSPM3
xxxx xxxx uuuu uuuu
SSPM0
0000 0000 0000 0000
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
--00 0000 --00 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
—
Unimplemented
—
CCP2X
CCP2Y
CCP2M3
CCP2M2
CCP2M1
CCP2M0
--00 0000 --00 0000
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.
5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.
6: PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.
DS30234D-page 32
 1997 Microchip Technology Inc.
PIC16C6X
TABLE 4-6:
Address Name
SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.’d)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Bank 1
80h(1)
INDF
81h
OPTION
82h(1)
PCL
83h(1)
STATUS
84h(1)
FSR
85h
TRISA
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
87h
TRISC
PORTC Data Direction Register
1111 1111 1111 1111
TRISD
PORTD Data Direction Register
(5)
88h
(5)
(1,2)
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
—
1111 1111 1111 1111
0000 0000 0000 0000
PD
Z
DC
C
Indirect data memory address pointer
—
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
PORTA Data Direction Register
--11 1111 --11 1111
1111 1111 1111 1111
—
TRISE
OBF
IBOV
8Ah
PCLATH
—
—
—
8Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
8Ch
PIE1
PSPIE(6)
(4)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000 0000 0000
8Dh
PIE2
—
—
—
—
—
—
—
CCP2IE
---- ---0 ---- ---0
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --qq ---- --uu
8Fh
—
Unimplemented
—
—
90h
—
Unimplemented
—
—
—
Unimplemented
—
—
89h
91h
PSPMODE
PORTE Data Direction Bits
IBF
0000 -111 0000 -111
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
92h
PR2
Timer2 Period Register
1111 1111 1111 1111
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000 0000 0000
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
TXSTA
99h
SPBRG
CSRC
TX9
TXEN
Baud Rate Generator Register
SYNC
—
BRGH
TRMT
TX9D
0000 -010 0000 -010
0000 0000 0000 0000
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
Unimplemented
—
—
9Eh
—
Unimplemented
—
—
9Fh
—
Unimplemented
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.
5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.
6: PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.
 1997 Microchip Technology Inc.
DS30234D-page 33
PIC16C6X
TABLE 4-6:
SPECIAL FUNCTION REGISTERS FOR THE PIC16C66/67 (Cont.’d)
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
resets(3)
Bank 2
100h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000 0000 0000
101h
TMR0
Timer0 module’s register
xxxx xxxx uuuu uuuu
102h(1)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
103h(1)
STATUS
104h(1)
FSR
105h
RP1
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
106h
IRP
PORTB
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
Unimplemented
—
PORTB Data Latch when written: PORTB pins when read
—
xxxx xxxx uuuu uuuu
107h
—
Unimplemented
—
—
108h
—
Unimplemented
—
—
—
Unimplemented
—
—
109h
(1,2)
PCLATH
—
—
—
(1)
INTCON
GIE
PEIE
T0IE
10Ah
10Bh
10Ch10Fh
—
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF
Unimplemented
---0 0000 ---0 0000
0000 000x 0000 000u
—
—
Bank 3
180h(1)
INDF
181h
OPTION
182h(1)
PCL
183h(1)
STATUS
184h(1)
FSR
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
PD
Z
DC
C
Indirect data memory address pointer
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
185h
—
186h
TRISB
187h
—
Unimplemented
—
—
188h
—
Unimplemented
—
—
—
Unimplemented
—
—
189h
Unimplemented
—
PORTB Data Direction Register
(1,2)
PCLATH
—
—
—
(1)
INTCON
GIE
PEIE
T0IE
18Ah
18Bh
18Ch19Fh
—
Unimplemented
—
1111 1111 1111 1111
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF
---0 0000 ---0 0000
0000 000x 0000 000u
—
—
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented location read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from any bank.
2: The upper byte of the Program Counter (PC) is not directly accessible. PCLATH is a holding register for the PC whose
contents are transferred to the upper byte of the program counter. (PC<12:8>)
3: Other (non power-up) resets include external reset through MCLR and the Watchdog Timer reset.
4: PIE1<6> and PIR1<6> are reserved on the PIC16C66/67, always maintain these bits clear.
5: PORTD, PORTE, TRISD, and TRISE are not implemented on the PIC16C66, read as '0'.
6: PSPIF (PIR1<7>) and PSPIE (PIE1<7>) are reserved on the PIC16C66, maintain these bits clear.
DS30234D-page 34
 1997 Microchip Technology Inc.
PIC16C6X
4.2.2.1
STATUS REGISTER
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The STATUS register, shown in Figure 4-9, contains the
arithmetic status of the ALU, the RESET status and the
bank select bits for data memory.
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions, not affecting any status bits, see the
“Instruction Set Summary.”
Note 1: For those devices that do not use bits IRP
and RP1 (STATUS<7:6>), maintain these
bits clear to ensure upward compatibility
with future products.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 2: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
FIGURE 4-9:
R/W-0
IRP
bit7
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
RP1
R/W-0
RP0
R-1
TO
R-1
PD
R/W-x
Z
R/W-x
DC
R/W-x
C
bit0
R = Readable bit
W = Writable bit
- n = Value at POR reset
x = unknown
bit 7:
IRP: RegIster Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5:
RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (for ADDWF, ADDLW,SUBLW, and SUBWF instructions) (For borrow the polarity is reversed).
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (for ADDWF, ADDLW,SUBLW, and SUBWF instructions)( For borrow the polarity is reversed).
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result
Note: a subtraction is executed by adding the two’s complement of the second operand.
For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
 1997 Microchip Technology Inc.
DS30234D-page 35
PIC16C6X
4.2.2.2
OPTION REGISTER
Note:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The OPTION register is a readable and writable register which contains various control bits to configure the
TMR0/WDT prescaler, the external INT interrupt,
TMR0, and the weak pull-ups on PORTB.
To achieve a 1:1 prescaler assignment for
TMR0 register, assign the prescaler to the
Watchdog Timer.
FIGURE 4-10: OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1
RBPU
bit7
R/W-1
INTEDG
R/W-1
T0CS
R/W-1
T0SE
R/W-1
PSA
R/W-1
PS2
R/W-1
PS1
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0:
PS2:PS0: Prescaler Rate Select bits
Bit Value
TMR0 Rate
WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
DS30234D-page 36
R/W-1
PS0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
 1997 Microchip Technology Inc.
PIC16C6X
4.2.2.3
INTCON REGISTER
Note:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The INTCON Register is a readable and writable register which contains the various enable and flag bits for
the TMR0 register overflow, RB port change and external RB0/INT pin interrupts.
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
FIGURE 4-11: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh 18Bh)
R/W-0
GIE
bit7
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RBIE
R/W-0
T0IF
R/W-0
INTF
R/W-x
RBIF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
x = unknown
bit 7:
GIE:(1) Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE:(2) Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (see Section 5.2 to clear the interrupt)
0 = None of the RB7:RB4 pins have changed state
Note 1: For the PIC16C61/62/64/65, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may unintentionally
be re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine. Refer to Section 13.5 for a detailed
description.
2: The PEIE bit (bit6) is unimplemented on the PIC16C61, read as '0'.
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
 1997 Microchip Technology Inc.
DS30234D-page 37
PIC16C6X
4.2.2.4
PIE1 REGISTER
Note:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
This register contains the individual enable bits for the
peripheral interrupts.
FIGURE 4-12: PIE1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 8Ch)
RW-0
—
bit7
R/W-0
—
U-0
—
U-0
—
R/W-0
SSPIE
R/W-0
CCP1IE
bit 7-6:
Reserved: Always maintain these bits clear.
bit 5-4:
Unimplemented: Read as '0'
bit 3:
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2:
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1:
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0:
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
DS30234D-page 38
R/W-0
TMR2IE
R/W-0
TMR1IE
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
 1997 Microchip Technology Inc.
PIC16C6X
FIGURE 4-13: PIE1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 8Ch)
R/W-0
—
bit7
R/W-0
—
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
CCP1IE
bit 7-6:
Reserved: Always maintain these bits clear.
bit 5:
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4:
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3:
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2:
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1:
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0:
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
R/W-0
TMR2IE
R/W-0
TMR1IE
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
FIGURE 4-14: PIE1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 8Ch)
R/W-0
PSPIE
bit7
R/W-0
—
U-0
—
U-0
—
R/W-0
SSPIE
R/W-0
CCP1IE
bit 7:
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6:
Reserved: Always maintain this bit clear.
bit 5-4:
Unimplemented: Read as '0'
bit 3:
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2:
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1:
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0:
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
 1997 Microchip Technology Inc.
R/W-0
TMR2IE
R/W-0
TMR1IE
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
DS30234D-page 39
PIC16C6X
FIGURE 4-15: PIE1 REGISTER FOR PIC16C65/65A/R65/67 (ADDRESS 8Ch)
R/W-0
PSPIE
bit7
R/W-0
—
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
CCP1IE
bit 7:
PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6:
Reserved: Always maintain this bit clear.
bit 5:
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4:
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3:
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2:
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1:
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0:
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
DS30234D-page 40
R/W-0
TMR2IE
R/W-0
TMR1IE
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
 1997 Microchip Technology Inc.
PIC16C6X
4.2.2.5
PIR1 REGISTER
Note:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
This register contains the individual flag bits for the
peripheral interrupts.
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
FIGURE 4-16: PIR1 REGISTER FOR PIC16C62/62A/R62 (ADDRESS 0Ch)
R/W-0
—
bit7
R/W-0
—
U-0
—
U-0
—
R/W-0
SSPIF
R/W-0
CCP1IF
R/W-0
TMR2IF
R/W-0
TMR1IF
bit0
bit 7-6:
Reserved: Always maintain these bits clear.
bit 5-4:
Unimplemented: Read as '0'
bit 3:
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0:
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflow occurred (must be cleared in software)
0 = No TMR1 register overflow occurred
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
 1997 Microchip Technology Inc.
DS30234D-page 41
PIC16C6X
FIGURE 4-17: PIR1 REGISTER FOR PIC16C63/R63/66 (ADDRESS 0Ch)
R/W-0
—
bit7
R/W-0
—
R-0
RCIF
R-0
TXIF
R/W-0
SSPIF
R/W-0
CCP1IF
R/W-0
TMR2IF
R/W-0
TMR1IF
bit0
bit 7-6:
Reserved: Always maintain these bits clear.
bit 5:
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is empty
bit 4:
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
bit 3:
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0:
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflow occurred (must be cleared in software)
0 = No TMR1 register overflow occurred
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
DS30234D-page 42
 1997 Microchip Technology Inc.
PIC16C6X
FIGURE 4-18: PIR1 REGISTER FOR PIC16C64/64A/R64 (ADDRESS 0Ch)
R/W-0
PSPIF
bit7
R/W-0
—
U-0
—
U-0
—
R/W-0
SSPIF
R/W-0
CCP1IF
R/W-0
TMR2IF
R/W-0
TMR1IF
bit0
bit 7:
PSPIF: Parallel Slave Port Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write operation has taken place
bit 6:
Reserved: Always maintain this bit clear.
bit 5-4:
Unimplemented: Read as '0'
bit 3:
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0:
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflow occurred (must be cleared in software)
0 = No TMR1 register occurred
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
 1997 Microchip Technology Inc.
DS30234D-page 43
PIC16C6X
FIGURE 4-19: PIR1 REGISTER FOR PIC16C65/65A/R65/67 (ADDRESS 0Ch)
R/W-0
PSPIF
bit7
R/W-0
—
R-0
RCIF
R-0
TXIF
R/W-0
SSPIF
R/W-0
CCP1IF
R/W-0
TMR2IF
R/W-0
TMR1IF
bit0
bit 7:
PSPIF: Parallel Slave Port Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write operation has taken place
bit 6:
Reserved: Always maintain this bit clear.
bit 5:
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is empty
bit 4:
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
bit 3:
SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2:
CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1:
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0:
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflow occurred (must be cleared in software)
0 = No TMR1 register overflow occurred
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
DS30234D-page 44
 1997 Microchip Technology Inc.
PIC16C6X
4.2.2.6
PIE2 REGISTER
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
This register contains the CCP2 interrupt enable bit.
FIGURE 4-20: PIE2 REGISTER (ADDRESS 8Dh)
U-0
—
bit7
U-0
—
U-0
—
U-0
—
bit 7-1:
Unimplemented: Read as '0'
bit 0:
CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
 1997 Microchip Technology Inc.
U-0
—
U-0
—
U-0
—
R/W-0
CCP2IE
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
DS30234D-page 45
PIC16C6X
4.2.2.7
PIR2 REGISTER
.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Note:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
U-0
—
R/W-0
CCP2IF
bit0
This register contains the CCP2 interrupt flag bit.
FIGURE 4-21: PIR2 REGISTER (ADDRESS 0Dh)
U-0
—
bit7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7-1:
Unimplemented: Read as '0'
bit 0:
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to
enabling an interrupt.
DS30234D-page 46
 1997 Microchip Technology Inc.
PIC16C6X
4.2.2.8
PCON REGISTER
Note:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The Power Control register (PCON) contains a flag bit
to allow differentiation between a Power-on Reset to an
external MCLR reset or WDT reset. Those devices with
brown-out detection circuitry contain an additional bit to
differentiate a Brown-out Reset condition from a
Power-on Reset condition.
FIGURE 4-22:
U-0
—
bit7
U-0
—
BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOR is
clear, indicating a brown-out has occurred.
The BOR status bit is a “don't care” and is
not necessarily predictable if the brown-out
circuit is disabled (by clearing the BODEN
bit in the Configuration word).
PCON REGISTER FOR PIC16C62/64/65 (ADDRESS 8Eh)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
R/W-q
—
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
q = value depends on conditions
bit 7-2:
Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
Reserved
This bit should be set upon a Power-on Reset by user software and maintained as set. Use of this bit as a general
purpose read/write bit is not recommended, since this may affect upward compatibility with future products.
FIGURE 4-23: PCON REGISTER FOR PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67
(ADDRESS 8Eh)
U-0
—
bit7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
POR
R/W-q
BOR
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
q = value depends on conditions
bit 7-2:
Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
 1997 Microchip Technology Inc.
DS30234D-page 47
PIC16C6X
4.3
PCL and PCLATH
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any reset, the upper bits of the PC
will be cleared. Figure 4-24 shows the two situations for
the loading of the PC. The upper example in the figure
shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
FIGURE 4-24: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
8
PCLATH<4:0>
5
Instruction with
PCL as
destination
ALU
PCLATH
PCH
12
11 10
PCL
8
0
7
PC
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
4.3.1
Note 2: There are no instructions mnemonics
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt
address
4.4
Program Memory Paging
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PIC16C6X devices are capable of addressing a continuous 8K word block of program memory. The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction the upper two
bits of the address are provided by PCLATH<4:3>.
When doing a CALL or GOTO instruction, the user must
ensure that the page select bits are programmed so
that the desired program memory page is addressed. If
a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the return instructions (which POPs the
address from the stack).
Note:
GOTO, CALL
2
Note 1: There are no status bits to indicate stack
overflows or stack underflow conditions.
PIC16C6X devices with 4K or less of program memory ignore paging bit
PCLATH<4>. The use of PCLATH<4> as a
general purpose read/write bit is not recommended since this may affect upward
compatibility with future products.
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 word block). Refer to the
application note “Implementing a Table Read” (AN556).
4.3.2
STACK
The PIC16CXX family has an 8 deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or a POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS30234D-page 48
 1997 Microchip Technology Inc.
PIC16C6X
Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that the PCLATH is saved and restored by the interrupt
service routine (if interrupts are used).
4.5
EXAMPLE 4-1:
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
ORG 0x500
BSF
PCLATH,3
BCF
PCLATH,4
CALL
SUB1_P1
:
:
:
ORG 0x900
SUB1_P1:
:
:
RETURN
Indirect Addressing, INDF and FSR
Registers
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly
(FSR = '0') will produce 00h. Writing to the INDF register indirectly results in a no-operation (although status
bits may be affected). An effective 9-bit address is
obtained by concatenating the 8-bit FSR register and
the IRP bit (STATUS<7>), as shown in Figure 4-25.
;Select page 1 (800h-FFFh)
;Only on >4K devices
;Call subroutine in
;page 1 (800h-FFFh)
;called subroutine
;page 1 (800h-FFFh)
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-2.
;return to Call subroutine
;in page 0 (000h-7FFh)
EXAMPLE 4-2:
movlw
movwf
clrf
incf
btfss
goto
NEXT
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
;initialize pointer
; to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
CONTINUE
:
;YES, continue
FIGURE 4-25: DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1: RP0
bank select
6
Indirect Addressing
0
from opcode
IRP
7
bank select
location select
00
01
10
FSR
0
location select
11
00h
80h
100h
180h
7Fh
FFh
17Fh
1FFh
Data
Memory
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 4-5, Figure 4-6, Figure 4-7, and Figure 4-8.
 1997 Microchip Technology Inc.
DS30234D-page 49
PIC16C6X
NOTES:
DS30234D-page 50
 1997 Microchip Technology Inc.
PIC16C6X
5.0
I/O PORTS
FIGURE 5-1:
BLOCK DIAGRAM OF THE
RA3:RA0 PINS AND THE RA5
PIN
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Some pins for these I/O ports are multiplexed with an
alternate function(s) for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
5.1
PORTA and TRISA Register
Data
bus
D
VDD
WR
Port
Pin RA4/T0CKI is a Schmitt Trigger input and an open
drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data
direction bits (TRIS registers) which can configure
these pins as output or input.
Q
CK
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
All devices have a 6-bit wide PORTA, except for the
PIC16C61 which has a 5-bit wide PORTA.
Q
Data Latch
Q
N
Q
VSS
TRIS Latch
TTL
input
buffer
D
WR
TRIS
CK
Setting a bit in the TRISA register puts the corresponding output driver in a hi-impedance mode. Clearing a bit
in the TRISA register puts the contents of the output
latch on the selected pin.
Reading PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read,
this value is modified, and then written to the port data
latch.
Pin RA4 is multiplexed with Timer0 module clock input
to become the RA4/T0CKI pin.
EXAMPLE 5-1:
BCF
BCF
CLRF
BSF
MOVLW
MOVWF
INITIALIZING PORTA
STATUS, RP0
STATUS, RP1
PORTA
STATUS, RP0
0xCF
TRISA
;
;
;
;
;
;
;
;
;
;
;
;
;
PIC16C66/67 only
Initialize PORTA by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RA<3:0> as inputs
RA<5:4> as outputs
TRISA<7:6> are always
read as '0'.
P
I/O pin(1)
RD TRIS
Q
D
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and
VSS.
2: The PIC16C61 does not have an RA5 pin.
FIGURE 5-2:
Data
bus
WR
PORT
BLOCK DIAGRAM OF THE
RA4/T0CKI PIN
D
Q
CK
Q
N
I/O pin(1)
Data Latch
WR
TRIS
D
Q
CK
Q
VSS
Schmitt
Trigger
input
buffer
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
 1997 Microchip Technology Inc.
DS30234D-page 51
PIC16C6X
TABLE 5-1:
PORTA FUNCTIONS
Name
Bit#
Buffer Type
RA0
RA1
RA2
RA3
RA4/T0CKI
bit0
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
ST
RA5/SS (1)
bit5
TTL
Function
Input/output
Input/output
Input/output
Input/output
Input/output or external clock input for Timer0.
Output is open drain type.
Input/output or slave select input for synchronous serial port.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: The PIC16C61 does not have PORTA<5> or TRISA<5>, read as ‘0’.
TABLE 5-2:
REGISTERS/BITS ASSOCIATED WITH PORTA
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
05h
PORTA
—
—
RA5(1)
RA4
RA3
RA2
RA1
RA0
--xx xxxx
--uu uuuu
85h
TRISA
—
—
--11 1111
--11 1111
PORTA Data Direction Register(1)
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note 1: PORTA<5> and TRISA<5> are not implemented on the PIC16C61, read as '0'.
DS30234D-page 52
 1997 Microchip Technology Inc.
PIC16C6X
5.2
PORTB and TRISB Register
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit
in the TRISB register puts the corresponding output
driver in a hi-impedance mode. Clearing a bit in the
TRISB register puts the contents of the output latch on
the selected pin(s).
EXAMPLE 5-2:
INITIALIZING PORTB
BCF
CLRF
STATUS, RP0
PORTB
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISB
;
;
;
;
;
;
;
;
;
;
;
Initialize PORTB by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RB<3:0> as inputs
RB<5:4> as outputs
RB<7:6> as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU (OPTION<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are also
disabled on a Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB port change
interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the interrupt in the following manner:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with software configurable pull-ups on these four pins allow
easy interface to a keypad and make it possible for
wake-up on key-depression. Refer to the Embedded
Control Handbook, Application Note, “Implementing
Wake-up on Key Stroke” (AN552).
Note:
For PIC16C61/62/64/65, if a change on the
I/O pin should occur when a read operation
is being executed (start of the Q2 cycle),
then interrupt flag bit RBIF may not get set.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-3:
BLOCK DIAGRAM OF THE
RB7:RB4 PINS FOR
PIC16C61/62/64/65
VDD
RBPU(2)
Data bus
weak
P pull-up
Data Latch
D
Q
WR Port
I/O
pin(1)
CK
TRIS Latch
D
Q
WR TRIS
TTL
Input
Buffer
CK
RD TRIS
Q
ST
Buffer
Latch
D
EN
RD Port
Set RBIF
From other
RB7:RB4 pins
Q
D
EN
RD Port
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RPBU bit (OPTION<7>).
 1997 Microchip Technology Inc.
DS30234D-page 53
PIC16C6X
FIGURE 5-4:
BLOCK DIAGRAM OF THE
RB7:RB4 PINS FOR
PIC16C62A/63/R63/64A/65A/
R65/66/67
FIGURE 5-5:
VDD
RBPU(2)
weak
P pull-up
VDD
RBPU(2)
Data Latch
D
Q
WR Port
WR Port
TRIS Latch
D
Q
WR TRIS
TRIS Latch
D
Q
TTL
Input
Buffer
CK
I/O
pin(1)
CK
I/O
pin(1)
CK
WR TRIS
Data Latch
D
Q
Data bus
weak
P pull-up
Data bus
BLOCK DIAGRAM OF THE
RB3:RB0 PINS
TTL
Input
Buffer
CK
ST
Buffer
RD TRIS
Q
RD TRIS
Latch
Q
D
EN
RD Port
EN
RD Port
Q1
D
RB0/INT
Set RBIF
Schmitt Trigger
Buffer
Q
From other
RB7:RB4 pins
RD Port
D
RD Port
EN
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RPBU bit (OPTION<7>).
Q3
RB7:RB6 in serial programming mode
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RPBU bit (OPTION<7>).
TABLE 5-3:
PORTB FUNCTIONS
Name
Bit#
Buffer Type
RB0/INT
bit0
TTL/ST
RB1
RB2
RB3
RB4
bit1
bit2
bit3
bit4
TTL
TTL
TTL
TTL
RB5
bit5
TTL
RB6
bit6
TTL/ST(2)
RB7
bit7
TTL/ST(2)
(1)
Function
Input/output pin or external interrupt input. Internal software programmable
weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin. Internal software programmable weak pull-up.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
TABLE 5-4:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
06h, 106h PORTB
86h, 186h TRISB
81h, 181h OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
PORTB Data Direction Register
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Value on:
POR,
BOR
Value on all
other resets
xxxx xxxx uuuu uuuuu
1111 1111
1111 1111
1111 1111
1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS30234D-page 54
 1997 Microchip Technology Inc.
PIC16C6X
5.3
PORTC and TRISC Register
FIGURE 5-6:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PORTC is an 8-bit wide bi-directional port. Each pin is
individually configurable as an input or output through
the TRISC register. PORTC is multiplexed with several
peripheral functions (Table 5-5). PORTC pins have
Schmitt Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
EXAMPLE 5-3:
INITIALIZING PORTC
BCF
BCF
CLRF
STATUS, RP0
STATUS, RP1
PORTC
BSF
MOVLW
STATUS, RP0
0xCF
MOVWF
TRISC
TABLE 5-5:
;
;
;
;
;
;
;
;
;
;
;
;
PIC16C66/67 only
Initialize PORTC by
clearing output
data latches
Select Bank 1
Value used to
initialize data
direction
Set RC<3:0> as inputs
RC<5:4> as outputs
RC<7:6> as inputs
PORTC BLOCK DIAGRAM
PORT/PERIPHERAL Select(2)
Peripheral Data Out
Data bus
WR
PORT
D
VDD
0
Q
P
1
CK
Q
Data Latch
WR
TRIS
D
CK
I/O
pin(1)
Q
Q
N
TRIS Latch
VSS
Schmitt
Trigger
RD TRIS
Peripheral
OE(3)
RD
PORT
Peripheral input
Q
D
EN
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
PORTC FUNCTIONS FOR PIC16C62/64
Name
Bit# Buffer Type Function
RC0/T1OSI/T1CKI
bit0
ST
Input/output port pin or Timer1 oscillator input or Timer1 clock input
RC1/T1OSO
bit1
ST
Input/output port pin or Timer1 oscillator output
RC2/CCP1
bit2
ST
Input/output port pin or Capture1 input/Compare1 output/PWM1 output
RC3 can also be the synchronous serial clock for both SPI and I2C modes.
RC3/SCK/SCL
bit3
ST
RC4/SDI/SDA
RC5/SDO
bit4
ST
bit5
ST
RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
Input/output port pin or synchronous serial port data output
RC6
bit6
ST
Input/output port pin
RC7
bit7
ST
Input/output port pin
Legend: ST = Schmitt Trigger input
 1997 Microchip Technology Inc.
DS30234D-page 55
PIC16C6X
TABLE 5-6:
PORTC FUNCTIONS FOR PIC16C62A/R62/64A/R64
Name
Bit# Buffer Type Function
RC0/T1OSO/T1CKI
bit0
ST
Input/output port pin or Timer1 oscillator output or Timer1 clock input
RC1/T1OSI
bit1
ST
Input/output port pin or Timer1 oscillator input
RC2/CCP1
bit2
ST
RC3/SCK/SCL
bit3
ST
Input/output port pin or Capture input/Compare output/PWM1 output
RC3 can also be the synchronous serial clock for both SPI and I2C modes.
RC4/SDI/SDA
RC5/SDO
bit4
ST
bit5
ST
RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
Input/output port pin or synchronous serial port data output
RC6
bit6
ST
Input/output port pin
RC7
bit7
ST
Input/output port pin
Legend: ST = Schmitt Trigger input
TABLE 5-7:
PORTC FUNCTIONS FOR PIC16C63/R63/65/65A/R65/66/67
Name
Bit# Buffer Type Function
RC0/T1OSO/T1CKI
bit0
ST
Input/output port pin or Timer1 oscillator output or Timer1 clock input
RC1/T1OSI/CCP2
bit1
ST
Input/output port pin or Timer1 oscillator input or Capture2 input/Compare2
output/PWM2 output
RC2/CCP1
bit2
ST
RC3/SCK/SCL
bit3
ST
Input/output port pin or Capture1 input/Compare1 output/PWM1 output
RC3 can also be the synchronous serial clock for both SPI and I2C modes.
RC4/SDI/SDA
RC5/SDO
bit4
ST
bit5
ST
RC6/TX/CK
bit6
ST
Input/output port pin or USART Asynchronous Transmit, or USART Synchronous Clock
RC7/RX/DT
bit7
ST
Input/output port pin or USART Asynchronous Receive, or USART Synchronous Data
RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode).
Input/output port pin or synchronous serial port data output
Legend: ST = Schmitt Trigger input
TABLE 5-8:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Address Name
07h
PORTC
87h
TRISC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
PORTC Data Direction Register
Legend: x = unknown, u = unchanged.
DS30234D-page 56
 1997 Microchip Technology Inc.
PIC16C6X
5.4
PORTD and TRISD Register
FIGURE 5-7:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Data
bus
PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as input or output.
D
WR
PORT
PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit
PSPMODE (TRISE<4>). In this mode, the input buffers
are TTL.
PORTD BLOCK DIAGRAM
(IN I/O PORT MODE)
Q
I/O pin(1)
CK
Data Latch
D
WR
TRIS
Q
Schmitt
Trigger
input
buffer
CK
TRIS Latch
RD TRIS
Q
D
EN
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 5-9:
Name
RD0/PSP0
RD1/PSP1
RD2/PSP2
PORTD FUNCTIONS
Bit#
Buffer Type
bit0
ST/TTL(1)
Function
Input/output port pin or parallel slave port bit0
bit1
(1)
Input/output port pin or parallel slave port bit1
(1)
Input/output port pin or parallel slave port bit2
(1)
ST/TTL
bit2
ST/TTL
RD3/PSP3
bit3
ST/TTL
Input/output port pin or parallel slave port bit3
RD4/PSP4
bit4
ST/TTL(1)
Input/output port pin or parallel slave port bit4
bit5
(1)
Input/output port pin or parallel slave port bit5
(1)
Input/output port pin or parallel slave port bit6
(1)
Input/output port pin or parallel slave port bit7
RD5/PSP5
RD6/PSP6
RD7/PSP7
ST/TTL
bit6
ST/TTL
bit7
ST/TTL
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Buffer is a Schmitt Trigger when in I/O mode, and a TTL buffer when in Parallel Slave Port mode.
TABLE 5-10:
Address Name
08h
PORTD
88h
TRISD
89h
TRISE
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
0000 -111
0000 -111
PORTD Data Direction Register
IBF
OBF
IBOV
PSPMODE
—
PORTE Data Direction Bits
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTD.
 1997 Microchip Technology Inc.
DS30234D-page 57
PIC16C6X
5.5
PORTE and TRISE Register
FIGURE 5-8:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Data
bus
PORTE has three pins, RE2/CS, RE1/WR, and
RE0/RD which are individually configurable as inputs
or outputs. These pins have Schmitt Trigger input buffers.
PORTE BLOCK DIAGRAM
(IN I/O PORT MODE)
D
WR
PORT
Q
I/O pin(1)
CK
Data Latch
I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In
this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs). In this mode the input buffers are TTL.
D
WR
TRIS
Q
Schmitt
Trigger
input
buffer
CK
TRIS Latch
Figure 5-9 shows the TRISE register, which controls
the parallel slave port operation and also controls the
direction of the PORTE pins.
RD TRIS
Q
D
EN
EN
RD PORT
Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 5-9:
R-0
IBF
bit7
TRISE REGISTER (ADDRESS 89h)
R-0
OBF
R/W-0
IBOV
R/W-0
PSPMODE
U-0
—
R/W-1
bit2
R/W-1
bit1
R/W-1
bit0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7 :
IBF: Input Buffer Full Status bit
1 = A word has been received and is waiting to be read by the CPU
0 = No word has been received
bit 6:
OBF: Output Buffer Full Status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5:
IBOV: Input Buffer Overflow Detect bit (in microprocessor mode)
1 = A write occurred when a previously input word has not been read (must be cleared in software)
0 = No overflow occurred
bit 4:
PSPMODE: Parallel Slave Port Mode Select bit
1 = Parallel slave port mode
0 = General purpose I/O mode
bit 3:
Unimplemented: Read as '0'
PORTE Data Direction Bits
bit 2:
Bit2: Direction Control bit for pin RE2/CS
1 = Input
0 = Output
bit 1:
Bit1: Direction Control bit for pin RE1/WR
1 = Input
0 = Output
bit 0:
Bit0: Direction Control bit for pin RE0/RD
1 = Input
0 = Output
DS30234D-page 58
 1997 Microchip Technology Inc.
PIC16C6X
TABLE 5-11:
PORTE FUNCTIONS
Name
Bit#
Buffer Type
RE0/RD
bit0
ST/TTL(1)
Function
Input/output port pin or Read control input in parallel slave port mode.
RD
1 = Not a read operation
0 = Read operation. The system reads the PORTD register (if
chip selected)
RE1/WR
bit1
ST/TTL(1)
Input/output port pin or Write control input in parallel slave port mode.
WR
1 = Not a write operation
0 = Write operation. The system writes to the PORTD register (if
chip selected)
RE2/CS
bit2
ST/TTL(1)
Input/output port pin or Chip select control input in parallel slave port
mode.
CS
1 = Device is not selected
0 = Device is selected
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note 1: Buffer is a Schmitt Trigger when in I/O mode, and a TTL buffer when in Parallel Slave Port (PSP) mode.
TABLE 5-12:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
PORTE
—
—
—
—
—
RE2
RE1
RE0
---- -xxx
---- -uuu
TRISE
IBF
OBF
IBOV
PSPMODE
—
0000 -111
0000 -111
Address
Name
09h
89h
PORTE Data Direction Bits
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells not used by PORTE.
 1997 Microchip Technology Inc.
DS30234D-page 59
PIC16C6X
5.6
I/O Programming Considerations
EXAMPLE 5-4:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
5.6.1
BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and rewritten to the data latch of this particular
pin, overwriting the previous content. As long as the pin
stays in the input mode, no problem occurs. However, if
bit0 is switched into output mode later on, the content
of the data latch may now be unknown.
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
Example 5-4 shows the effect of two sequential
read-modify-write instructions on an I/O port.
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
;Initial PORT settings: PORTB<7:4> Inputs
;
PORTB<3:0> Outputs
;PORTB<7:6> have external pull-ups and are
;not connected to other circuitry
;
;
PORT latch PORT pins
;
---------- --------BCF PORTB, 7
; 01pp pppp
11pp pppp
BCF PORTB, 6
; 10pp pppp
11pp pppp
BSF STATUS, RP0 ;
BCF TRISB, 7
; 10pp pppp
11pp pppp
BCF TRISB, 6
; 10pp pppp
10pp pppp
;
;Note that the user may have expected the
;pin values to be 00pp pppp. The 2nd BCF
;caused RB7 to be latched as the pin value
;(high).
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage the
chip.
5.6.2
SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 5-10). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that file
to be read into the CPU is executed. Otherwise, the
previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with a NOP or another
instruction not accessing this I/O port.
FIGURE 5-10: SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Instruction
fetched
PC
PC + 1
MOVWF PORTB MOVF PORTB,W
write to
PORTB
PC + 2
PC + 3
NOP
NOP
This example shows a write to PORTB
followed by a read from PORTB.
Note that:
data setup time = (0.25TCY - TPD)
RB7:RB0
where TCY = instruction cycle
TPD = propagation delay
Port pin
sampled here
TPD
Instruction
executed
NOP
MOVWF PORTB
write to
PORTB
DS30234D-page 60
Note:
MOVF PORTB,W
Therefore, at higher clock frequencies,
a write followed by a read may be problematic.
 1997 Microchip Technology Inc.
PIC16C6X
5.7
Parallel Slave Port
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PORTD operates as an 8-bit wide parallel slave port
(microprocessor port) when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through
RD control input (RE0/RD) and WR control input pin
(RE1/WR).
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set).
There are actually two 8-bit latches, one for data-out
(from the PIC16/17) and one for data input. The user
writes 8-bit data to PORTD data latch and reads data
from the port pin latch (note that they have the same
address). In this mode, the TRISD register is ignored
since the microprocessor is controlling the direction of
data flow.
A write to the PSP occurs when both the CS and WR
lines are first detected low. When either the CS or WR
lines become high (level triggered), then the Input
Buffer Full status flag bit IBF (TRISE<7>) is set on the
Q4 clock cycle, following the next Q2 cycle, to signal
the write is complete (Figure 5-12). The interrupt flag bit
PSPIF (PIR1<7>) is also set on the same Q4 clock
cycle. IBF can only be cleared by reading the PORTD
input latch. The input Buffer Overflow status flag bit
IBOV (TRISE<5>) is set if a second write to the Parallel
Slave Port is attempted when the previous byte has not
been read out of the buffer.
FIGURE 5-11: PORTD AND PORTE AS A
PARALLEL SLAVE PORT
Data bus
D
WR
PORT
Q
RDx
pin
CK
TTL
Q
RD
PORT
D
EN
EN
One bit of PORTD
Set interrupt flag
PSPIF (PIR1<7>)
Read
TTL
RD
Chip Select
TTL
CS
TTL
WR
Write
Note: I/O pin has protection diodes to VDD and VSS.
A read from the PSP occurs when both the CS and RD
lines are first detected low. The Output Buffer Full status flag bit OBF (TRISE<6>) is cleared immediately
(Figure 5-13) indicating that the PORTD latch is waiting
to be read by the external bus. When either the CS or
RD pin becomes high (level triggered), the interrupt flag
bit PSPIF is set on the Q4 clock cycle, following the
next Q2 cycle, indicating that the read is complete.
OBF remains low until data is written to PORTD by the
user firmware.
When not in Parallel Slave Port mode, the IBF and OBF
bits are held clear. However, if flag bit IBOV was previously set, it must be cleared in firmware.
An interrupt is generated and latched into flag bit
PSPIF when a read or write operation is completed.
PSPIF must be cleared by the user in firmware and the
interrupt can be disabled by clearing the interrupt
enable bit PSPIE (PIE1<7>).
 1997 Microchip Technology Inc.
DS30234D-page 61
PIC16C6X
FIGURE 5-12: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q4
Q1
Q2
Q3
Q4
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
FIGURE 5-13: PARALLEL SLAVE PORT READ WAVEFORMS
Q1
Q2
Q3
Q4
Q1
Q2
Q3
CS
WR
RD
PORTD<7:0>
IBF
OBF
PSPIF
TABLE 5-13:
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
08h
PORTD
PSP7
PSP6
PSP5
PSP4
PSP3
PSP2
PSP1
PSP0
xxxx xxxx
uuuu uuuu
09h
PORTE
—
—
—
—
—
RE2
RE1
RE0
---- -xxx
---- -uuu
89h
TRISE
IBF
OBF
IBOV
PSPMODE
—
0000 -111
0000 -111
RCIF(2)
TXIF(2)
SSPIF
CCP1IF TMR2IF TRM1IF
0000 0000
0000 0000
RCIE(2)
TXIE(2)
SSPIE CCP1IE TMR2IE TMR1IE
0000 0000
0000 0000
0Ch
PIR1
PSPIF
(1)
8Ch
PIE1
PSPIE
(1)
PORTE Data Direction Bits
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by the PSP.
Note 1: These bits are reserved, always maintain these bits clear.
2: These bits are implemented on the PIC16C65/65A/R65/67 only.
DS30234D-page 62
 1997 Microchip Technology Inc.
PIC16C6X
6.0
OVERVIEW OF TIMER
MODULES
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
All PIC16C6X devices have three timer modules except
for the PIC16C61, which has one timer module. Each
module can generate an interrupt to indicate that an
event has occurred (i.e., timer overflow). Each of these
modules are detailed in the following sections. The
timer modules are:
6.3
Timer2 Overview
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Timer2 is an 8-bit timer with a programmable prescaler
and a programmable postscaler, as well as an 8-bit
Period Register (PR2). Timer2 can be used with the
CCP module (in PWM mode) as well as the Baud Rate
Generator for the Synchronous Serial Port (SSP). The
prescaler option allows Timer2 to increment at the following rates: 1:1, 1:4, and 1:16.
• Timer0 module (Section 7.0)
• Timer1 module (Section 8.0)
• Timer2 module (Section 9.0)
The postscaler allows TMR2 register to match the
period register (PR2) a programmable number of times
before generating an interrupt. The postscaler can be
programmed from 1:1 to 1:16 (inclusive).
6.1
6.4
Timer0 Overview
CCP Overview
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The Timer0 module is a simple 8-bit overflow counter.
The clock source can be either the internal system
clock (Fosc/4) or an external clock. When the clock
source is an external clock, the Timer0 module can be
selected to increment on either the rising or falling
edge.
The CCP module(s) can operate in one of three modes:
16-bit capture, 16-bit compare, or up to 10-bit Pulse
Width Modulation (PWM).
The Timer0 module also has a programmable prescaler option. This prescaler can be assigned to either
the Timer0 module or the Watchdog Timer. Bit PSA
(OPTION<3>) assigns the prescaler, and bits PS2:PS0
(OPTION<2:0>) determine the prescaler value. TMR0
can increment at the following rates: 1:1 when the prescaler is assigned to Watchdog Timer, 1:2, 1:4, 1:8,
1:16, 1:32, 1:64, 1:128, and 1:256.
Synchronization of the external clock occurs after the
prescaler. When the prescaler is used, the external
clock frequency may be higher then the device’s frequency. The maximum frequency is 50 MHz, given the
high and low time requirements of the clock.
6.2
Timer1 Overview
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Capture mode captures the 16-bit value of TMR1 into
the CCPRxH:CCPRxL register pair. The capture event
can be programmed for either the falling edge, rising
edge, fourth rising edge, or sixteenth rising edge of the
CCPx pin.
Compare mode compares the TMR1H:TMR1L register
pair to the CCPRxH:CCPRxL register pair. When a
match occurs, an interrupt can be generated and the
output pin CCPx can be forced to a given state (High or
Low) and Timer1 can be reset. This depends on control
bits CCPxM3:CCPxM0.
PWM mode compares the TMR2 register to a 10-bit
duty cycle register (CCPRxH:CCPRxL<5:4>) as well as
to an 8-bit period register (PR2). When the TMR2 register = Duty Cycle register, the CCPx pin will be forced
low. When TMR2 = PR2, TMR2 is cleared to 00h, an
interrupt can be generated, and the CCPx pin (if an output) will be forced high.
Timer1 is a 16-bit timer/counter. The clock source can
be either the internal system clock (Fosc/4), an external
clock, or an external crystal. Timer1 can operate as
either a timer or a counter. When operating as a
counter (external clock source), the counter can either
operate synchronized to the device or asynchronously
to the device. Asynchronous operation allows Timer1 to
operate during sleep, which is useful for applications
that require a real-time clock as well as the power savings of SLEEP mode.
TImer1 also has a prescaler option which allows TMR1
to increment at the following rates: 1:1, 1:2, 1:4, and
1:8. TMR1 can be used in conjunction with the Capture/
Compare/PWM module. When used with a CCP module, Timer1 is the time-base for 16-bit capture or 16-bit
compare and must be synchronized to the device.
 1997 Microchip Technology Inc.
DS30234D-page 63
PIC16C6X
NOTES:
DS30234D-page 64
 1997 Microchip Technology Inc.
PIC16C6X
7.0
TIMER0 MODULE
(OPTION<4>). Clearing bit T0SE selects the rising
edge. Restrictions on the external clock input are discussed in detail in Section 7.2.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit
PSA (OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 module. The prescaler is not
readable or writable. When the prescaler is assigned to
the Timer0 module, prescale values of 1:2, 1:4, ...,
1:256 are selectable. Section 7.3 details the operation
of the prescaler.
The Timer0 module has the following features:
• 8-bit timer/counter register, TMR0
- Read and write capability
- Interrupt on overflow from FFh to 00h
• 8-bit software programmable prescaler
• Internal or external clock select
- Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
7.1
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Timer mode is selected by clearing bit T0CS
(OPTION<5>). In timer mode, the Timer0 module will
increment every instruction cycle (without prescaler). If
TMR0 register is written, the increment is inhibited for
the following two instruction cycles (Figure 7-2 and
Figure 7-3). The user can work around this by writing
an adjusted value to the TMR0 register.
The TMR0 interrupt is generated when the register
(TMR0) overflows from FFh to 00h. This overflow sets
interrupt flag bit T0IF (INTCON<2>). The interrupt can
be masked by clearing enable bit T0IE (INTCON<5>).
Flag bit T0IF must be cleared in software by the TImer0
interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot wake the processor
from SLEEP since the timer is shut off during SLEEP.
Figure 7-4 displays the Timer0 interrupt timing.
Counter mode is selected by setting bit T0CS. In this
mode, Timer0 will increment either on every rising or
falling edge of pin RA4/T0CKI. The incrementing edge
is determined by the source edge select bit T0SE
FIGURE 7-1:
TMR0 Interrupt
TIMER0 BLOCK DIAGRAM
Data bus
RA4/T0CKI
pin
FOSC/4
0
PSout
1
Sync with
Internal
clocks
1
Programmable
Prescaler
8
0
TMR0 reg
PSout
(2 cycle delay)
T0SE
3
Set bit T0IF
on overflow
PSA
PS2, PS1, PS0
T0CS
Note 1: Bits, T0CS, T0SE, PSA, and PS2, PS1, PS0 are (OPTION<5:0).
2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed diagram).
FIGURE 7-2:
PC
(Program
Counter)
TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
Instruction
Fetch
TMR0
T0
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
T0+1
Instruction
Executed
 1997 Microchip Technology Inc.
PC+2
PC+3
MOVF TMR0,W MOVF TMR0,W
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
PC+4
MOVF TMR0,W
NT0
Read TMR0
reads NT0
PC+5
PC+6
MOVF TMR0,W
NT0+1
NT0+2
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0 + 2
DS30234D-page 65
PIC16C6X
FIGURE 7-3:
PC
(Program
Counter)
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
Instruction
Fetch
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
Instruction
Execute
PC+4
PC+5
MOVF TMR0,W
PC+6
MOVF TMR0,W
NT0+1
NT0
Read TMR0
reads NT0
Write TMR0
executed
FIGURE 7-4:
PC+3
MOVF TMR0,W
T0+1
T0
TMR0
PC+2
MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
T0
Read TMR0
reads NT0 + 1
TMR0 INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
Timer0
FEh
T0IF bit
(INTCON<2>)
FFh
00h
01h
02h
1
1
GIE bit
(INTCON<7>)
INSTRUCTION
FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC +1
PC +1
Inst (PC+1)
Inst (PC)
Dummy cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy cycle
Inst (0004h)
Note 1: Interrupt flag bit T0IF is sampled here (every Q1).
2: Interrupt latency = 4Tcy where Tcy = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
DS30234D-page 66
 1997 Microchip Technology Inc.
PIC16C6X
7.2
Using Timer0 with External Clock
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For
the external clock to meet the sampling requirement,
the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at
least 4Tosc (and a small RC delay of 40 ns) divided by
the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical specification of the
desired device.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (TOSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 7-5).
Therefore, it is necessary for T0CKI to be high for at
least 2Tosc (and a small RC delay of 20 ns) and low for
at least 2Tosc (and a small RC delay of 20 ns). Refer to
the electrical specification of the desired device.
FIGURE 7-5:
7.2.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the Timer0 module is actually incremented. Figure 7-5 shows the delay
from the external clock edge to the timer incrementing.
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max.
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
 1997 Microchip Technology Inc.
DS30234D-page 67
PIC16C6X
7.3
Prescaler
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF TMR0,
MOVWF TMR0, BSF TMR0,bitx) will clear the prescaler count. When assigned to the Watchdog Timer, a
CLRWDT instruction will clear the Watchdog Timer and
the prescaler count. The prescaler is not readable or
writable.
An 8-bit counter is available as a prescaler for the
Timer0 module or as a postscaler for the Watchdog
Timer (WDT), respectively (Figure 7-6). For simplicity,
this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be
used by either the Timer0 module or the Watchdog
Timer, but not both. Thus, a prescaler assignment for
the Timer0 module means that there is no prescaler for
the Watchdog Timer, and vice-versa.
FIGURE 7-6:
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (=Fosc/4)
0
RA4/T0CKI
pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Set flag bit T0IF
on Overflow
PSA
8-bit Prescaler
8
8 - to - 1MUX
PS2:PS0
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
DS30234D-page 68
 1997 Microchip Technology Inc.
PIC16C6X
7.3.1
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control, i.e., it can be changed “on the fly” during program
execution.
Note:
To avoid an unintended device RESET, the
following instruction sequence (shown in
Example 7-1) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This precaution must
be followed even if the WDT is disabled.
EXAMPLE 7-1:
CHANGING PRESCALER (TIMER0→WDT)
Lines 2 and 3 do NOT have to
be included if the final desired
prescale value is other than 1:1.
If 1:1 is final desired value, then
a temporary prescale value is
set in lines 2 and 3 and the final
prescale value will be set in lines
10 and 11.
1)
BSF
STATUS, RP0
;Bank 1
2)
MOVLW
b'xx0x0xxx'
;Select clock source and prescale value of
3)
MOVWF
OPTION_REG
;other than 1:1
4)
BCF
STATUS, RP0
;Bank 0
5)
CLRF
TMR0
;Clear TMR0 and prescaler
6)
BSF
STATUS, RP1
;Bank 1
7)
MOVLW
b'xxxx1xxx'
;Select WDT, do not change prescale value
8)
MOVWF
OPTION_REG
;
9)
CLRWDT
;Clears WDT and prescaler
10) MOVLW
b'xxxx1xxx'
;Select new prescale value and WDT
11) MOVWF
OPTION_REG
;
12) BCF
STATUS, RP0
;Bank 0
To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 7-2.
EXAMPLE 7-2:
CLRWDT
BSF
MOVLW
MOVWF
BCF
CHANGING PRESCALER (WDT→TIMER0)
STATUS, RP0
b'xxxx0xxx'
OPTION_REG
STATUS, RP0
TABLE 7-1:
Address
Name
01h, 101h
TMR0
;Clear WDT and prescaler
;Bank 1
;Select TMR0, new prescale value and clock source
;
;Bank 0
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module’s register
PEIE(1)
T0IE
INTE
RBIE
T0IF
INTF
RBIF
81h, 181h
OPTION RBPU INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
85h
TRISA
0Bh,8Bh,
INTCON
10Bh,18Bh
GIE
—
—
PORTA Data Direction Register(1)
Value on:
POR,
BOR
Value on all
other resets
xxxx xxxx
uuuu uuuu
0000 000x
0000 000u
1111 1111
1111 1111
--11 1111
--11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
Note 1: TRISA<5> and bit PEIE are not implemented on the PIC16C61, read as '0'.
 1997 Microchip Technology Inc.
DS30234D-page 69
PIC16C6X
NOTES:
DS30234D-page 70
 1997 Microchip Technology Inc.
PIC16C6X
8.0
TIMER1 MODULE
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Timer1 is a 16-bit timer/counter consisting of two 8-bit
registers (TMR1H and TMR1L) which are readable and
writable. Register TMR1 (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clearing the TMR1 interrupt enable bit TMR1IE (PIE1<0>).
Timer1 can operate in one of two modes:
Timer1 also has an internal “reset input”. This reset can
be generated by CCP1 or CCP2 (Capture/Compare/
PWM) module. See Section 10.0 for details. Figure 8-1
shows the Timer1 control register.
For the PIC16C62A/R62/63/R63/64A/R64/65A/R65/
R66/67, when the Timer1 oscillator is enabled
(T1OSCEN is set), the RC1 and RC0 pins become
inputs. That is, the TRISC<1:0> value is ignored.
For the PIC16C62/64/65, when the Timer1 oscillator is
enabled (T1OSCEN is set), RC1 pin becomes an input,
however the RC0 pin will have to be configured as an
input by setting the TRISC<0> bit.
The Timer1 module also has a software programmable
prescaler.
• As a timer
• As a counter
The operating mode is determined by clock select bit,
TMR1CS (T1CON<1>) (Figure 8-2).
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
FIGURE 8-1:
U-0
—
bit7
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
R/W-0
R/W-0
TMR1CS TMR1ON
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-6:
Unimplemented: Read as '0'
bit 5-4:
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3:
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain.
bit 2:
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1:
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from T1OSI (on the rising edge) (See pinouts for pin with T1OSI function)
0 = Internal clock (Fosc/4)
bit 0:
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
 1997 Microchip Technology Inc.
DS30234D-page 71
PIC16C6X
8.1
Timer1 Operation in Timer Mode
8.2.1
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
When an external clock input is used for Timer1 in synchronized counter mode, it must meet certain requirements. The external clock requirement is due to
internal phase clock (Tosc) synchronization. Also, there
is a delay in the actual incrementing of TMR1 after synchronization.
Timer mode is selected by clearing bit TMR1CS
(T1CON<1>). In this mode, the input clock to the timer
is Fosc/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect since the internal clock is
always in sync.
8.2
When the prescaler is 1:1, the external clock input is
the same as the prescaler output. The synchronization
of T1CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T1CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to appropriate
electrical specification section, parameters 45, 46, and
47.
Timer1 Operation in Synchronized
Counter Mode
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Counter mode is selected by setting bit TMR1CS. In
this mode the timer increments on every rising edge of
clock input on T1OSI when enable bit T1OSCEN is set
or pin with T1CKI when bit T1OSCEN is cleared.
Note:
The T1OSI function is multiplexed to different pins, depending on the device. See the
pinout descriptions to see which pin has
the T1OSI function.
When a prescaler other than 1:1 is used, the external
clock input is divided by the asynchronous ripplecounter type prescaler so that the prescaler output is
symmetrical. In order for the external clock to meet the
sampling requirement, the ripple counter must be taken
into account. Therefore, it is necessary for T1CKI to
have a period of at least 4Tosc (and a small RC delay
of 40 ns) divided by the prescaler value. The only
requirement on T1CKI high and low time is that they do
not violate the minimum pulse width requirements of
10 ns). Refer to applicable electrical specification section, parameters 40, 42, 45, 46, and 47.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if an external clock is present, since
the synchronization circuit is shut off. The prescaler,
however, will continue to increment.
FIGURE 8-2:
EXTERNAL CLOCK INPUT TIMING FOR
SYNCHRONIZED COUNTER MODE
TIMER1 BLOCK DIAGRAM
TMR1IF
Overflow
Interrupt
flag bit
TMR1H
Synchronized
clock input
0
TMR1
TMR1L
1
TMR1ON
on/off
T1OSC
T1OSO(2)
T1OSI(2)
T1SYNC
(3)
1
T1OSCEN Fosc/4
Enable
Internal
Oscillator(1) Clock
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
SLEEP input
TMR1CS
T1CKPS1:T1CKPS0
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
2: See pinouts for pins with T1OSO and T1OSI functions.
3: For the PIC16C62/64/65, the Schmitt Trigger is not implemented in external clock mode.
DS30234D-page 72
 1997 Microchip Technology Inc.
PIC16C6X
8.3
Timer1 Operation in Asynchronous
Counter Mode
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and generate an interrupt on overflow which will wake the processor. However, special precautions in software are
needed to read-from or write-to the Timer1 register
pair, TMR1L and TMR1H (Section 8.3.2).
In asynchronous counter mode, Timer1 cannot be used
as a time-base for capture or compare operations.
8.3.1
EXTERNAL CLOCK INPUT TIMING WITH
UNSYNCHRONIZED CLOCK
If control bit T1SYNC is set, the timer will increment
completely asynchronously. The input clock must meet
certain minimum high time and low time requirements,
as specified in timing parameters (45 - 47).
8.3.2
READING AND WRITING TMR1 IN
ASYNCHRONOUS COUNTER MODE
Reading TMR1H or TMR1L, while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write contention may occur by writing to the timer registers while the
register is incrementing. This may produce an unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Example 8-1 is an example routine to read the 16-bit
timer value. This is useful if the timer cannot be
stopped.
EXAMPLE 8-1:
;
READING A 16-BIT
FREE-RUNNING TIMER
All Interrupts
MOVF
TMR1H,
MOVWF TMPH
MOVF
TMR1L,
MOVWF TMPL
MOVF
TMR1H,
SUBWF TMPH,
are disabled
W
;Read high byte
;
W
;Read low byte
;
W
;Read high byte
W
;Sub 1st read
;with 2nd read
BTFSC STATUS,Z
;is result = 0
GOTO
CONTINUE
;Good 16-bit read
; TMR1L may have rolled over between the read
; of the high and low bytes. Reading the high
; and low bytes now will read a good value.
MOVF
TMR1H, W
;Read high byte
MOVWF TMPH
;
MOVF
TMR1L, W
;Read low byte
MOVWF TMPL
;
;
Re-enable Interrupt (if required)
CONTINUE
;Continue with
:
;your code
8.4
Timer1 Oscillator
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
A crystal oscillator circuit is built in-between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 8-1 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must allow a software time delay to ensure
proper oscillator start-up.
TABLE 8-1:
CAPACITOR SELECTION
FOR THE TIMER1
OSCILLATOR
Osc Type
Freq
C1
C2
LP
32 kHz
100 kHz
200 kHz
33 pF
15 pF
15 pF
33 pF
15 pF
15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz
Epson C-2 100.00 KC-P
± 20 PPM
200 kHz
STD XTL 200.000 kHz
± 20 PPM
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.
 1997 Microchip Technology Inc.
DS30234D-page 73
PIC16C6X
8.5
Resetting Timer1 using a CCP Trigger
Output
8.6
Resetting of TMR1 Register Pair
(TMR1H:TMR1L)
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
CCP2 is implemented on the PIC16C63/R63/65/65A/
R65/66/67 only.
The TMR1H and TMR1L registers are not reset to 00h
on a POR or any other reset except by the CCP1 or
CCP2 special event trigger.
If CCP1 or CCP2 module is configured in Compare
mode to generate a “special event trigger”
(CCPxM3:CCPxM0 = 1011), this signal will reset
Timer1.
Note:
The T1CON register is reset to 00h on a Power-on
Reset or a Brown-out Reset, which shuts off the timer
and leaves a 1:1 prescaler. In all other resets, the register is unaffected.
The “special event trigger” from the
CCP1and CCP2 modules will not set interrupt flag bit TMR1IF(PIR1<0>).
8.7
Timer1 Prescaler
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this feature.
If the Timer1 is running in asynchronous counter mode,
this reset operation may not work.
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will
take precedence.
In this mode of operation, the CCPRxH:CCPRxL registers pair effectively becomes the period register for the
Timer1 module.
TABLE 8-2:
Address
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name
Value on:
POR,
BOR
Value on
all other
resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
PIR1
PSPIF(2)
(3)
RCIF(1)
TXIF(1)
SSPIF
CCP1IF TMR2IF
8Ch
PIE1
PSPIE(2)
(3)
RCIE(1)
TXIE(1)
SSPIE
CCP1IE TMR2IE
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h
T1CON
0Bh,8Bh
INTCON
10Bh,18Bh
0Ch
—
—
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000
TMR1IE 0000 0000 0000 0000
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: The USART is implemented on the PIC16C63/R63/65/65A/R65/66/67 only.
2: Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear.
3: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.
DS30234D-page 74
 1997 Microchip Technology Inc.
PIC16C6X
9.0
TIMER2 MODULE
9.1
Timer2 Prescaler and Postscaler
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It is especially suitable as PWM time-base
for PWM mode of CCP module(s). TMR2 is a readable
and writable register, and is cleared on any device
reset.
The prescaler and postscaler counters are cleared
when any of the following occurs:
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is initialized to FFh upon reset.
The match output of the TMR2 register goes through a
4-bit postscaler (which gives a 1:1 to 1:16 scaling,
inclusive) to generate a TMR2 interrupt (latched in flag
bit TMR2IF (PIR1<1>)).
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (POR, BOR, MCLR Reset, or
WDT Reset).
TMR2 is not cleared when T2CON is written.
9.2
Output of TMR2
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module which optionally uses
it to generate shift clock.
FIGURE 9-1:
The Timer2 module can be shut off by clearing control
bit TMR2ON (T2CON<2>) to minimize power consumption.
Figure 9-2 shows the Timer2 control register. T2CON is
cleared upon reset which initializes Timer2 as shut off
with the prescaler and postscaler at a 1:1 value.
Sets
TMR2
interrupt
flag bit,
TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2
output(1)
Reset
Postscaler
1:1 to 1:16
EQ
4
Note 1:
FIGURE 9-2:
TMR2 reg
Comparator
Prescaler
1:1, 1:4, 1:16
Fosc/4
2
PR2 reg
TMR2 register output can be software selected by
the SSP Module as a baud clock.
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
—
bit7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit0
bit 7:
Unimplemented: Read as '0'
bit 6-3:
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 postscale
0001 = 1:2 postscale
•
•
1111 = 1:16 postscale
bit 2:
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0:
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = 1:1 prescale
01 = 1:4 prescale
1x = 1:16 prescale
 1997 Microchip Technology Inc.
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
DS30234D-page 75
PIC16C6X
TABLE 9-1:
Address
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name
Value on:
POR,
BOR
Value on
all other
resets
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
PIR1
PSPIF(2)
(3)
RCIF(1)
TXIF(1)
SSPIF
CCP1IF
TMR2IF
TMR1IF 0000 0000 0000 0000
8Ch
PIE1
PSPIE(2)
(3)
RCIE(1)
TXIE(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
11h
TMR2
Timer2 module’s register
0Bh,8Bh
INTCON
10Bh,18Bh
0Ch
12h
T2CON
92h
PR2
Legend:
Note 1:
2:
3:
—
0000 000x 0000 000u
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period register
1111 1111 1111 1111
x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer2.
The USART is implemented on the PIC16C63/R63/65/65A/R65/66/67 only.
Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear.
PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.
DS30234D-page 76
 1997 Microchip Technology Inc.
PIC16C6X
10.0
CAPTURE/COMPARE/PWM
(CCP) MODULE(s)
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 CCP1
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67 CCP2
Each CCP (Capture/Compare/PWM) module contains
a 16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register, or as a PWM
master/slave duty cycle register. Both the CCP1 and
CCP2 modules are identical in operation, with the
exception of the operation of the special event trigger.
Table 10-1 and Table 10-2 show the resources and
interactions of the CCP modules(s). In the following
sections, the operation of a CCP module is described
with respect to CCP1. CCP2 operates the same as
CCP1, except where noted.
CCP2 module:
Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
For use of the CCP modules, refer to the Embedded
Control Handbook, “Using the CCP Modules” (AN594).
TABLE 10-1:
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
CCP1 module:
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 10-2:
INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Same TMR1 time-base.
Capture
Compare
The compare should be configured for the special event trigger, which clears TMR1.
Compare
Compare
The compare(s) should be configured for the special event trigger, which clears TMR1.
PWM
PWM
The PWMs will have the same frequency, and update rate (TMR2 interrupt).
PWM
Capture
None
PWM
Compare
None
 1997 Microchip Technology Inc.
DS30234D-page 77
PIC16C6X
FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh)
U-0
—
bit7
U-0
—
R/W-0
CCPxX
R/W-0
R/W-0
CCPxY CCPxM3
R/W-0
CCPxM2
R/W-0
R/W-0
CCPxM1 CCPxM0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5-4: CCPxX:CCPxY: PWM Least Significant bits
Capture Mode
Unused
Compare Mode
Unused
PWM Mode
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCPx module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (bit CCPxIF is set)
1001 = Compare mode, clear output on match (bit CCPxIF is set)
1010 = Compare mode, generate software interrupt on match (bit CCPxIF is set, CCPx pin is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1)
11xx = PWM mode
10.1
Capture Mode
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 10-2: CAPTURE MODE
OPERATION BLOCK
DIAGRAM
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on pin RC2/CCP1 (Figure 10-2). An event is defined as:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value will be lost.
10.1.1
CCP PIN CONFIGURATION
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit.
Note:
If the RC2/CCP1 pin is configured as an
output, a write to PORTC can cause a capture condition.
DS30234D-page 78
Prescaler
÷ 1, 4, 16
Set CCP1IF
PIR1<2>
RC2/CCP1
pin
CCPR1H
CCPR1L
Capture
Enable
and
edge detect
TMR1H
TMR1L
CCP1CON<3:0>
Q’s
10.1.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work consistently.
10.1.3
SOFTWARE INTERRUPT
When the Capture event is changed, a false capture
interrupt may be generated. The user should clear
enable bit CCP1IE (PIE1<2>) to avoid false interrupts
and should clear flag bit CCP1IF following any such
change in operating mode.
 1997 Microchip Technology Inc.
PIC16C6X
10.1.4
CCP PRESCALER
10.2.1
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore the first capture may be from
a non-zero prescaler. Example 10-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
EXAMPLE 10-1: CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
MOVLW
MOVWF
10.2
CCP1CON
; Turn CCP module off
NEW_CAPT_PS ; Load the W reg with
; the new prescaler
; mode value and CCP ON
CCP1CON
; Load CCP1CON with
; this value
Compare Mode
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven High
• Driven Low
• Remains Unchanged
The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit.
Note:
10.2.1
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
10.2.2
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled).
10.2.3
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
which may be used to initiate an action.
The special event trigger output of CCP1 and CCP2
resets the TMR1 register pair. This allows the
CCPR1H:CCPR1L and CCPR2H:CCPR2L registers to
effectively be 16-bit programmable period register(s)
for Timer1.
For compatibility issues, the special event trigger output of CCP1 (PIC16C72) and CCP2 (all other
PIC16C7X devices) also starts an A/D conversion.
Note:
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time interrupt flag bit CCP1IF is set.
CCP PIN CONFIGURATION
The “special event trigger” from the
CCP1and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>).
FIGURE 10-3: COMPARE MODE
OPERATION BLOCK
DIAGRAM
Special event trigger will reset Timer1, but not
set interrupt flag bit TMR1IF (PIR1<0>).
Special Event Trigger
Set CCP1IF
PIR1<2>
CCPR1H CCPR1L
Q
RC2/CCP1
S
R
Output
Logic
TRISC<2>
Output Enable
CCP1CON<3:0>
Mode Select
 1997 Microchip Technology Inc.
match
Comparator
TMR1H
TMR1L
DS30234D-page 79
PIC16C6X
10.3
PWM Mode
10.3.1
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Figure 10-4 shows a simplified block diagram of the
CCP module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 10.3.3.
FIGURE 10-4: SIMPLIFIED PWM BLOCK
DIAGRAM
The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
Note:
CCP1CON<5:4>
Duty cycle registers
CCPR1L
10.3.2
CCPR1H (Slave)
R
Comparator
Q
RC2/CCP1
TMR2
PWM PERIOD
The Timer2 postscaler (see Section 9.1) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different frequency than the PWM output.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available: the CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
(Note 1)
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
S
TRISC2
Comparator
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
A PWM output (Figure 10-5) has a time base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 10-5: PWM OUTPUT
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM
frequency:
Period
(
log
=
TMR2 = PR2
TMR2 = Duty Cycle
DS30234D-page 80
)
bits
log(2)
Duty Cycle
TMR2 = PR2
FOSC
FPWM
Note:
If the PWM duty cycle value is longer than
the PWM period the CCP1 pin will not be
forced to the low level.
 1997 Microchip Technology Inc.
PIC16C6X
EXAMPLE 10-2: PWM PERIOD AND DUTY
CYCLE CALCULATION
In order to achieve higher resolution, the PWM frequency must be decreased. In order to achieve higher
PWM frequency, the resolution must be decreased.
Desired PWM frequency is 78.125 kHz,
Fosc = 20 MHz
TMR2 prescale = 1
Table 10-3 lists example PWM frequencies and resolutions for Fosc = 20 MHz. The TMR2 prescaler and PR2
values are also shown.
1/78.125 kHz = [(PR2) + 1] • 4 • 1/20 MHz • 1
12.8 µs
= [(PR2) + 1] • 4 • 50 ns • 1
10.3.3
PR2
= 63
The following steps should be taken when configuring
the CCP module for PWM operation:
Find the maximum resolution of the duty cycle that can
be used with a 78.125 kHz frequency and 20 MHz
oscillator:
1/78.125 kHz = 2PWM RESOLUTION • 1/20 MHz • 1
12.8 µs
=2
256
= 2PWM RESOLUTION
log(256)
= (PWM Resolution) • log(2)
8.0
= PWM Resolution
PWM RESOLUTION
2.
• 50 ns • 1
3.
4.
At most, an 8-bit resolution duty cycle can be obtained
from a 78.125 kHz frequency and a 20 MHz oscillator,
i.e., 0 ≤ CCPR1L:CCP1CON<5:4> ≤ 255. Any value
greater than 255 will result in a 100% duty cycle.
TABLE 10-3:
1.22 kHz 4.88 kHz 19.53 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
Add
5.
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Make the CCP1 pin an output by clearing the
TRISC<2> bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
TABLE 10-4:
1.
SET-UP FOR PWM OPERATION
16
0xFF
10
4
0xFF
10
78.12 kHz
156.3 kHz
208.3 kHz
1
0x3F
8
1
0x1F
7
1
0x17
5.5
1
0xFF
10
REGISTERS ASSOCIATED WITH TIMER1, CAPTURE AND COMPARE
Name
0Bh,8Bh
INTCON
10Bh,18Bh
0Ch
PIR1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
PSPIF(2)
(3)
RCIF(1)
TXIF(1)
SSPIF
Value on:
Value on
POR,
all other
BOR
Resets
0000 000x 0000 000u
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh(4)
PIR2
—
—
—
—
—
8Ch
PIE1
PSPIE(2)
(3)
RCIE(1)
TXIE(1)
SSPIE
8Dh(4)
PIE2
—
—
—
—
—
87h
TRISC
PORTC Data Direction register
1111 1111 1111 1111
0Eh
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h
T1CON
15h
CCPR1L
Capture/Compare/PWM1 (LSB)
16h
CCPR1H
Capture/Compare/PWM1 (MSB)
17h
CCP1CON
1Bh(4)
CCPR2L
Capture/Compare/PWM2 (LSB)
1Ch(4)
CCPR2H
Capture/Compare/PWM2 (MSB)
1Dh(4)
CCP2CON
Legend:
Note 1:
2:
3:
4:
—
—
—
—
—
—
—
—
CCP2IF ---- ---0 ---- ---0
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
—
—
CCP2IE ---- ---0 ---- ---0
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCP1X
CCP2X
CCP1Y
CCP2Y
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented locations read as '0’. Shaded cells are not used in these modes.
These bits are associated with the USART module, which is implemented on the PIC16C63/R63/65/65A/R65/66/67 only.
Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear.
The PIR1<6> and PIE1<6> bits are reserved, always maintain these bits clear.
These registers are associated with the CCP2 module, which is only implemented on the PIC16C63/R63/65/65A/R65/66/67.
 1997 Microchip Technology Inc.
DS30234D-page 81
PIC16C6X
TABLE 10-5:
Addr
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Name
0Bh,8Bh
INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
PSPIF(2)
(3)
RCIF(1)
TXIF(1)
SSPIF
CCP1IF
TMR2IF
Value on:
POR,
BOR
Value on
all other
Resets
0000 000x 0000 000u
0Ch
PIR1
0Dh(4)
PIR2
—
—
—
—
—
—
—
CCP2IF ---- ---0 ---- ---0
8Ch
PIE1
PSPIE(2)
(3)
RCIE(1)
TXIE(1)
SSPIE
CCP1IE
TMR2IE
TMR1IE 0000 0000 0000 0000
8Dh(4)
87h
PIE2
TRISC
—
—
—
PORTC Data Direction register
—
—
—
—
CCP2IE ---- ---0 ---- ---0
1111 1111 1111 1111
11h
TMR2
Timer2 module’s register
0000 0000 0000 0000
92h
PR2
Timer2 module’s Period register
1111 1111 1111 1111
12h
T2CON
15h
CCPR1L
16h
CCPR1H
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Capture/Compare/PWM1 (LSB)
xxxx xxxx uuuu uuuu
Capture/Compare/PWM1 (MSB)
xxxx xxxx uuuu uuuu
17h
CCP1CON
1Bh(4)
CCPR2L
—
—
CCP1X
CCP1Y
Capture/Compare/PWM2 (LSB)
CCPR2H
Capture/Compare/PWM2 (MSB)
1Ch(4)
1Dh(4)
Legend:
Note 1:
2:
3:
4:
TMR1IF 0000 0000 0000 0000
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP2CON
—
—
CCP2X
CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented locations read as '0’. Shaded cells are not used in this mode.
These bits are associated with the USART module, which is implemented on the PIC16C63/R63/65/65A/R65/66/67 only.
Bits PSPIE and PSPIF are reserved on the PIC16C62/62A/R62/63/R63/66, always maintain these bits clear.
The PIR1<6> and PIE1<6> bits are reserved, always maintain these bits clear.
These registers are associated with the CCP2 module, which is only implemented on the PIC16C63/R63/65/65A/R65/66/67.
DS30234D-page 82
 1997 Microchip Technology Inc.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
11.0
SYNCHRONOUS SERIAL
PORT (SSP) MODULE
11.1
SSP Module Overview
PIC16C6X
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other peripheral
or microcontroller devices. These peripheral devices
may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate
in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
The SSP module in I2C mode works the same in all
PIC16C6X devices that have an SSP module. However
the SSP Module in SPI mode has differences between
the PIC16C66/67 and the other PIC16C6X devices.
The register definitions and operational description of
SPI mode has been split into two sections because of
the differences between the PIC16C66/67 and the
other PIC16C6X devices. The default reset values of
both the SPI modules is the same regardless of the
device:
11.2 SPI Mode for PIC16C62/62A/R62/63/R63/64/
64A/R64/65/65A/R65 .......................................84
11.3 SPI Mode for PIC16C66/67..............................89
11.4 I2C™ Overview ................................................95
11.5 SSP I2C Operation...........................................99
Refer to Application Note AN578, “Use of the SSP Module in the I 2C Multi-Master Environment.”
 1997 Microchip Technology Inc.
DS30234D-page 83
PIC16C6X
11.2
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
SPI Mode for PIC16C62/62A/R62/63/
R63/64/64A/R64/65/65A/R65
This section contains register definitions and operational characteristics of the SPI module for the
PIC16C62, PIC16C62A, PIC16CR62, PIC16C63,
PIC16CR63, PIC16C64, PIC16C64A, PIC16CR64,
PIC16C65, PIC16C65A, PIC16CR65.
FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)
U-0
—
bit7
U-0
—
R-0
D/A
R-0
P
R-0
S
R-0
R/W
R-0
UA
R-0
BF
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7-6: Unimplemented: Read as '0'
bit 5:
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4:
P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3:
S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
bit 2:
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is valid from the address
match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
bit 1:
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0:
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
DS30234D-page 84
 1997 Microchip Technology Inc.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PIC16C6X
FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
WCOL
bit7
R/W-0
SSPOV
R/W-0
SSPEN
R/W-0
CKP
R/W-0
SSPM3
R/W-0
SSPM2
R/W-0
SSPM1
R/W-0
SSPM0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7:
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overflow Detect bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow,
the data in SSPSR register is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set
since each new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
In I2C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care"
in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level. Transmit happens on falling edge, receive on rising edge.
0 = Idle state for clock is a low level. Transmit happens on rising edge, receive on falling edge.
In I2C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = Fosc/4
0001 = SPI master mode, clock = Fosc/16
0010 = SPI master mode, clock = Fosc/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1011 = I2C firmware controlled Master Mode (slave idle)
1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled
1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled
 1997 Microchip Technology Inc.
DS30234D-page 85
PIC16C6X
11.2.1
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
OPERATION OF SSP MODULE IN SPI
MODE
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
Additionally a fourth pin may be used when in a slave
mode of operation:
• Slave Select (SS)
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>).
These control bits allow the following to be specified:
• Master Mode (SCK is the clock output)
• Slave Mode (SCK is the clock input)
• Clock Polarity (Output/Input data on the Rising/
Falling edge of SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
The SSP consists of a transmit/receive Shift Register
(SSPSR) and a Buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR,
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then the Buffer Full bit, BF (SSPSTAT<0>)
and flag bit SSPIF are set. This double buffering of the
received data (SSPBUF) allows the next byte to start
reception before reading the data that was just
received. Any write to the SSPBUF register during
transmission/reception of data will be ignored, and the
write collision detect bit, WCOL (SSPCON<7>) will be
set. User software must clear bit WCOL so that it can
be determined if the following write(s) to the SSPBUF
completed successfully. When the application software
is expecting to receive valid data, the SSPBUF register
should be read before the next byte of data to transfer
is written to the SSPBUF register. The Buffer Full bit BF
(SSPSTAT<0>) indicates when the SSPBUF register
has been loaded with the received data (transmission
is complete). When the SSPBUF is read, bit BF is
cleared. This data may be irrelevant if the SPI is only a
transmitter. Generally the SSP Interrupt is used to
determine when the transmission/reception has completed. The SSPBUF register must be read and/or written. If the interrupt method is not going to be used, then
software polling can be done to ensure that a write collision does not occur. Example 11-1 shows the loading
of the SSPBUF (SSPSR) register for data transmission. The shaded instruction is only required if the
received data is meaningful.
DS30234D-page 86
EXAMPLE 11-1: LOADING THE SSPBUF
(SSPSR) REGISTER
BSF
STATUS, RP0
LOOP BTFSS SSPSTAT, BF
GOTO
BCF
MOVF
;Specify Bank 1
;Has data been
;received
;(transmit
;complete)?
;No
;Specify Bank 0
;W reg = contents
;of SSPBUF
;Save in user RAM
;W reg = contents
; of TXDATA
;New data to xmit
LOOP
STATUS, RP0
SSPBUF, W
MOVWF RXDATA
MOVF TXDATA, W
MOVWF SSPBUF
The block diagram of the SSP module, when in SPI
mode (Figure 11-3), shows that the SSPSR register is
not directly readable or writable, and can only be
accessed from addressing the SSPBUF register. Additionally, the SSP status register (SSPSTAT) indicates
the various status conditions.
FIGURE 11-3: SSP BLOCK DIAGRAM
(SPI MODE)
Internal
data bus
Read
Write
SSPBUF reg
SSPSR reg
RC4/SDI/SDA
shift
clock
bit0
RC5/SDO
SS Control
Enable
RA5/SS
Edge
Select
2
Clock Select
SSPM3:SSPM0
4
Edge
Select
RC3/SCK/
SCL
TMR2 output
2
Prescaler TCY
4, 16, 64
TRISC<3>
 1997 Microchip Technology Inc.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
To enable the serial port, SSP enable bit SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear enable bit SSPEN, re-initialize SSPCON
register, and then set enable bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port
pins. For the pins to behave as the serial port function,
they must have their data direction bits (in the TRIS register) appropriately programmed. That is:
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set (if implemented)
Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. An example
would be in master mode where you are only sending
data (to a display driver), then both SDI and SS could
be used as general purpose outputs by clearing their
corresponding TRIS register bits.
Figure 11-4 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge
of the clock. Both processors should be programmed to
the same Clock Polarity (CKP), then both controllers
would send and receive data at the same time.
Whether the data is meaningful (or dummy data)
depends on the application software. This leads to
three scenarios for data transmission:
PIC16C6X
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2) is to broadcast data by
the software protocol.
In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SCK output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate. As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched interrupt flag bit SSPIF (PIR1<3>) is
set.
The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
Figure 11-5 and Figure 11-6 where the MSB is transmitted first. In master mode, the SPI clock rate (bit rate)
is user programmable to be one of the following:
•
•
•
•
Fosc/4 (or TCY)
Fosc/16 (or 4 • TCY)
Fosc/64 (or 16 • TCY)
Timer2 output/2
This allows a maximum bit clock frequency (at 20 MHz)
of 5 MHz. When in slave mode the external clock must
meet the minimum high and low times.
In sleep mode, the slave can transmit and receive data
and wake the device from sleep.
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
FIGURE 11-4: SPI MASTER/SLAVE CONNECTION
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF register)
Serial Input Buffer
(SSPBUF register)
SDI
Shift Register
(SSPSR)
MSb
SDO
LSb
Shift Register
(SSPSR)
MSb
LSb
Serial Clock
SCK
PROCESSOR 1
 1997 Microchip Technology Inc.
SCK
PROCESSOR 2
DS30234D-page 87
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PIC16C6X
point at which it was taken high. External pull-up/
pull-down resistors may be desirable, depending on the
application.
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode (SSPCON<3:0> = 04h)
and the TRISA<5> bit must be set the for synchronous slave mode to be enabled. When the SS pin is
low, transmission and reception are enabled and
the SDO pin is driven. When the SS pin goes high,
the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating
output. If the SS pin is taken low without resetting
SPI mode, the transmission will continue from the
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 11-5: SPI MODE TIMING, MASTER MODE OR SLAVE MODE W/O SS CONTROL
SCK
(CKP = 0)
SCK
(CKP = 1)
bit6
bit7
SDO
bit5
bit4
bit3
bit2
bit1
bit0
SDI
bit7
bit0
SSPIF
FIGURE 11-6: SPI MODE TIMING, SLAVE MODE WITH SS CONTROL
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
bit7
SDO
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI
bit7
bit0
SSPIF
TABLE 11-1:
REGISTERS ASSOCIATED WITH SPI OPERATION
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
T0IF
INTF
RBIF
Value on
all other
Resets
0Bh,8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
0000 000x
0000 000u
0Ch
PIR1
PSPIF(2)
(3)
RCIF(1)
TXIF(1)
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000
0000 0000
8Ch
PIE1
PSPIE(2)
(3)
RCIE(1)
TXIE(1)
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000
0000 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
14h
SSPCON
85h
TRISA
87h
TRISC
94h
SSPSTAT
WCOL
—
SSPOV SSPEN
—
CKP
SSPM3
SSPM2
xxxx xxxx
SSPM1
0000 0000
--11 1111
--11 1111
PORTA Data Direction Register
1111 1111
PORTC Data Direction Register
—
—
D/A
P
S
R/W
UA
uuuu uuuu
SSPM0 0000 0000
BF
--00 0000
1111 1111
--00 0000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in SPI
mode.
Note 1: These bits are associated with the USART which is implemented on the PIC16C63/R63/65/65A/R65 only.
2: PSPIF and PSPIE are reserved on the PIC16C62/62A/R62/63/R63, always maintain these bits clear.
3: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.
DS30234D-page 88
 1997 Microchip Technology Inc.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
11.3
PIC16C6X
SPI Mode for PIC16C66/67
This section contains register definitions and operational characterisitics of the SPI module on the
PIC16C66 and PIC16C67 only.
FIGURE 11-7: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)(PIC16C66/67)
R/W-0 R/W-0
SMP
CKE
R-0
R-0
R-0
R-0
R-0
R-0
D/A
P
S
R/W
UA
BF
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7:
SMP: SPI data input sample phase
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
bit 6:
CKE: SPI Clock Edge Select (Figure 11-11, Figure 11-12, and Figure 11-13)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5:
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4:
P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is
detected last, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3:
S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is
detected last, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
bit 2:
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or ACK bit.
1 = Read
0 = Write
bit 1:
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0:
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Transmit in progress, SSPBUF is full
0 = Transmit complete, SSPBUF is empty
 1997 Microchip Technology Inc.
DS30234D-page 89
PIC16C6X
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 11-8: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)(PIC16C66/67)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
bit 7:
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word
(must be cleared in software)
0 = No collision
bit 6:
SSPOV: Receive Overflow Indicator bit
In SPI mode
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF,
even if only transmitting data, to avoid setting overflow. In master mode the overflow bit is not set since
each new reception (and transmission) is initiated by writing to the SSPBUF register.
0 = No overflow
In I2C mode
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t
care" in transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5:
SSPEN: Synchronous Serial Port Enable bit
In SPI mode
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2C mode
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
bit 4:
CKP: Clock Polarity Select bit
In SPI mode
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I2C mode
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch) (Used to ensure data setup time)
bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits
0000 = SPI master mode, clock = FOSC/4
0001 = SPI master mode, clock = FOSC/16
0010 = SPI master mode, clock = FOSC/64
0011 = SPI master mode, clock = TMR2 output/2
0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin
0110 = I2C slave mode, 7-bit address
0111 = I2C slave mode, 10-bit address
1011 = I2C firmware controlled master mode (slave idle)
1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled
1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled
DS30234D-page 90
 1997 Microchip Technology Inc.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
11.3.1
SSP MODULE IN SPI MODE FOR
PIC16C66/67
The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO) RC5/SDO
• Serial Data In (SDI) RC4/SDI/SDA
• Serial Clock (SCK) RC3/SCK/SCL
Additionally a fourth pin may be used when in a slave
mode of operation:
PIC16C6X
EXAMPLE 11-2: LOADING THE SSPBUF
(SSPSR) REGISTER
(PIC16C66/67)
BCF
STATUS, RP1
BSF
STATUS, RP0
LOOP BTFSS SSPSTAT, BF
GOTO
BCF
MOVF
LOOP
STATUS, RP0
SSPBUF, W
• Slave Select (SS) RA5/SS
MOVWF RXDATA
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the following to be specified:
MOVF
•
•
•
•
Master Mode (SCK is the clock output)
Slave Mode (SCK is the clock input)
Clock Polarity (Idle state of SCK)
Clock edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select Mode (Slave mode only)
The SSP consists of a transmit/receive Shift Register
(SSPSR) and a buffer register (SSPBUF). The SSPSR
shifts the data in and out of the device, MSb first. The
SSPBUF holds the data that was written to the SSPSR
until the received data is ready. Once the 8-bits of data
have been received, that byte is moved to the SSPBUF
register. Then the buffer full detect bit BF
(SSPSTAT<0>) and interrupt flag bit SSPIF (PIR1<3>)
are set. This double buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored, and the write collision detect bit WCOL
(SSPCON<7>) will be set. User software must clear the
WCOL bit so that it can be determined if the following
write(s) to the SSPBUF register completed successfully. When the application software is expecting to
receive valid data, the SSPBUF should be read before
the next byte of data to transfer is written to the
SSPBUF. Buffer full bit BF (SSPSTAT<0>) indicates
when SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
bit BF is cleared. This data may be irrelevant if the SPI
is only a transmitter. Generally the SSP Interrupt is
used to determine when the transmission/reception
has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then
software polling can be done to ensure that a write collision does not occur. Example 11-2 shows the loading
of the SSPBUF (SSPSR) for data transmission. The
shaded instruction is only required if the received data
is meaningful.
 1997 Microchip Technology Inc.
;Specify Bank 1
;
;Has data been
;received
;(transmit
;complete)?
;No
;Specify Bank 0
;W reg = contents
; of SSPBUF
;Save in user RAM
TXDATA, W
;W reg = contents
; of TXDATA
;New data to xmit
MOVWF SSPBUF
The block diagram of the SSP module, when in SPI
mode (Figure 11-9), shows that the SSPSR is not
directly readable or writable, and can only be accessed
from addressing the SSPBUF register. Additionally, the
SSP status register (SSPSTAT) indicates the various
status conditions.
FIGURE 11-9: SSP BLOCK DIAGRAM
(SPI MODE)(PIC16C66/67)
Internal
data bus
Read
Write
SSPBUF reg
SSPSR reg
RC4/SDI/SDA
shift
clock
bit0
RC5/SDO
SS Control
Enable
RA5/SS
Edge
Select
2
Clock Select
SSPM3:SSPM0
4
Edge
Select
RC3/SCK/
SCL
TMR2 output
2
Prescaler TCY
4, 16, 64
TRISC<3>
DS30234D-page 91
PIC16C6X
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
To enable the serial port, SSP Enable bit, SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISC register) appropriately programmed. That is:
• SDI must have TRISC<4> set
• SDO must have TRISC<5> cleared
• SCK (Master mode) must have TRISC<3>
cleared
• SCK (Slave mode) must have TRISC<3> set
• SS must have TRISA<5> set
Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. An example
would be in master mode where you are only sending
data (to a display driver), then both SDI and SS could
be used as general purpose outputs by clearing their
corresponding TRIS register bits.
The master can initiate the data transfer at any time
because it controls the SCK. The master determines
when the slave (Processor 2) is to broadcast data by
the firmware protocol.
In master mode the data is transmitted/received as
soon as the SSPBUF register is written to. If the SPI is
only going to receive, the SCK output could be disabled
(programmed as an input). The SSPSR register will
continue to shift in the signal present on the SDI pin at
the programmed clock rate. As each byte is received, it
will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately
set). This could be useful in receiver applications as a
“line activity monitor” mode.
In slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched the interrupt flag bit SSPIF (PIR1<3>)
is set.
The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then would give
waveforms for SPI communication as shown in
Figure 11-11, Figure 11-12, and Figure 11-13 where
the MSB is transmitted first. In master mode, the SPI
clock rate (bit rate) is user programmable to be one of
the following:
Figure 11-10 shows a typical connection between two
microcontrollers. The master controller (Processor 1)
initiates the data transfer by sending the SCK signal.
Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge
of the clock. Both processors should be programmed to
same Clock Polarity (CKP), then both controllers would
send and receive data at the same time. Whether the
data is meaningful (or dummy data) depends on the
application firmware. This leads to three scenarios for
data transmission:
•
•
•
•
• Master sends data — Slave sends dummy data
• Master sends data — Slave sends data
• Master sends dummy data — Slave sends data
In sleep mode, the slave can transmit and receive data
and wake the device from sleep.
FOSC/4 (or TCY)
FOSC/16 (or 4 • TCY)
FOSC/64 (or 16 • TCY)
Timer2 output/2
This allows a maximum bit clock frequency (at 20 MHz)
of 5 MHz. When in slave mode the external clock must
meet the minimum high and low times.
FIGURE 11-10: SPI MASTER/SLAVE CONNECTION (PIC16C66/67)
SPI Master SSPM3:SSPM0 = 00xxb
SPI Slave SSPM3:SSPM0 = 010xb
SDO
SDI
Serial Input Buffer
(SSPBUF)
Serial Input Buffer
(SSPBUF)
SDI
Shift Register
(SSPSR)
MSb
SDO
LSb
Shift Register
(SSPSR)
MSb
LSb
Serial Clock
SCK
PROCESSOR 1
DS30234D-page 92
SCK
PROCESSOR 2
 1997 Microchip Technology Inc.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The SS pin allows a synchronous slave mode. The
SPI must be in slave mode (SSPCON<3:0> = 04h)
and the TRISA<5> bit must be set for the synchronous slave mode to be enabled. When the SS pin is
low, transmission and reception are enabled and the
SDO pin is driven. When the SS pin goes high, the
SDO pin is no longer driven, even if in the middle of
a transmitted byte, and becomes a floating output. If
the SS pin is taken low without resetting SPI mode,
the transmission will continue from the point at
which it was taken high. External pull-up/ pull-down
resistors may be desirable, depending on the application.
PIC16C6X
Note:
When the SPI is in Slave Mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is set
to VDD.
Note:
If the SPI is used in Slave Mode with
CKE = '1', then the SS pin control must be
enabled.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver the SDO pin can be configured as
an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
FIGURE 11-11: SPI MODE TIMING, MASTER MODE (PIC16C66/67)
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit7
SDO
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SDI (SMP = 1)
bit7
bit0
SSPIF
FIGURE 11-12: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) (PIC16C66/67)
SS (optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit7
SDO
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SSPIF
 1997 Microchip Technology Inc.
DS30234D-page 93
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PIC16C6X
FIGURE 11-13: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) (PIC16C66/67)
SS
(not optional)
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit6
bit7
bit5
bit3
bit4
bit2
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SSPIF
TABLE 11-2:
Address
REGISTERS ASSOCIATED WITH SPI OPERATION (PIC16C66/67)
Name
0Bh,8Bh,
INTCON
10Bh,18Bh
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
PSPIF(1)
(2)
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
8Ch
PIE1
PSPIE(1)
(2)
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
14h
SSPCON
85h
TRISA
87h
TRISC
94h
SSPSTAT
WCOL
—
SSPOV SSPEN
—
CKP
SSPM3 SSPM2 SSPM1
xxxx xxxx
uuuu uuuu
SSPM0 0000 0000
0000 0000
--11 1111
--11 1111
1111 1111
1111 1111
0000 0000
0000 0000
PORTA Data Direction register
PORTC Data Direction register
SMP
CKE
D/A
P
S
R/W
UA
BF
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by SSP module in SPI mode.
Note 1: PSPIF and PSPIE are reserved on the PIC16C66, always maintain these bits clear.
2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.
DS30234D-page 94
 1997 Microchip Technology Inc.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
I2C™ Overview
11.4
This section provides an overview of the Inter-Integrated Circuit (I 2C) bus, with Section 11.5 discussing
the operation of the SSP module in I2C mode.
The I 2C bus is a two-wire serial interface developed by
the Philips® Corporation. The original specification, or
standard mode, was for data transfers of up to 100
Kbps. The enhanced specification (fast mode) is also
supported. This device will communicate with both
standard and fast mode devices if attached to the same
bus. The clock will determine the data rate.
The I 2C interface employs a comprehensive protocol to
ensure reliable transmission and reception of data.
When transmitting data, one device is the “master”
which initiates transfer on the bus and generates the
clock signals to permit that transfer, while the other
device(s) acts as the “slave.” All portions of the slave
protocol are implemented in the SSP module’s hardware, except general call support, while portions of the
master protocol need to be addressed in the
PIC16CXX software. Table 11-3 defines some of the
I 2C bus terminology. For additional information on the
I 2C interface specification, refer to the Philips document “The I 2C bus and how to use it.” #939839340011,
which can be obtained from the Philips Corporation.
In the I 2C interface protocol each device has an
address. When a master wishes to initiate a data transfer, it first transmits the address of the device that it
wishes to “talk” to. All devices “listen” to see if this is
their address. Within this address, a bit specifies if the
master wishes to read-from/write-to the slave device.
The master and slave are always in opposite modes
(transmitter/receiver) of operation during a data transfer. That is they can be thought of as operating in either
of these two relations:
In both cases the master generates the clock signal.
The output stages of the clock (SCL) and data (SDA)
lines must have an open-drain or open-collector in
order to perform the wired-AND function of the bus.
External pull-up resistors are used to ensure a high
level when no device is pulling the line down. The number of devices that may be attached to the I2C bus is
limited only by the maximum bus loading specification
of 400 pF.
11.4.1
INITIATING AND TERMINATING DATA
TRANSFER
During times of no data transfer (idle time), both the
clock line (SCL) and the data line (SDA) are pulled high
through the external pull-up resistors. The START and
STOP conditions determine the start and stop of data
transmission. The START condition is defined as a high
to low transition of the SDA when the SCL is high. The
STOP condition is defined as a low to high transition of
the SDA when the SCL is high. Figure 11-14 shows the
START and STOP conditions. The master generates
these conditions for starting and terminating data transfer. Due to the definition of the START and STOP conditions, when data is being transmitted, the SDA line
can only change state when the SCL line is low.
FIGURE 11-14: START AND STOP
CONDITIONS
SDA
SCL
S
Start
Condition
• Master-transmitter and Slave-receiver
• Slave-transmitter and Master-receiver
TABLE 11-3:
PIC16C6X
P
Change
of Data
Allowed
Change
of Data
Allowed
Stop
Condition
I2C BUS TERMINOLOGY
Term
Description
Transmitter
The device that sends the data to the bus.
Receiver
The device that receives the data from the bus.
Master
The device which initiates the transfer, generates the clock and terminates the transfer.
Slave
The device addressed by a master.
Multi-master
More than one master device in a system. These masters can attempt to control the bus at the
same time without corrupting the message.
Arbitration
Procedure that ensures that only one of the master devices will control the bus. This ensure that
the transfer data does not get corrupted.
Synchronization
Procedure where the clock signals of two or more devices are synchronized.
 1997 Microchip Technology Inc.
DS30234D-page 95
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PIC16C6X
ADDRESSING I 2C DEVICES
11.4.2
FIGURE 11-17: SLAVE-RECEIVER
ACKNOWLEDGE
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure 11-15). The
more complex is the 10-bit address with a R/W bit
(Figure 11-16). For 10-bit address format, two bytes
must be transmitted with the first five bits specifying this
to be a 10-bit address.
Data
Output by
Transmitter
Data
Output by
Receiver
R/W ACK
slave address
S
R/W
ACK
Sent by
Slave
Start Condition
Read/Write pulse
Acknowledge
S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the slave to move the
received data or fetch the data it needs to transfer
before allowing the clock to start. This wait state technique can also be implemented at the bit level,
Figure 11-18. The slave will inherently stretch the clock,
when it is a transmitter, but will not when it is a receiver.
The slave will have to clear the SSPCON<4> bit to
enable clock stretching when it is a receiver.
sent by slave
= 0 for write
11.4.3
Clock Pulse for
Acknowledgment
If the master is receiving the data (master-receiver), it
generates an acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an acknowledge (not acknowledge). The
slave then releases the SDA line so the master can
generate the STOP condition. The master can also
generate the STOP condition during the acknowledge
pulse for valid termination of data transfer.
FIGURE 11-16: I2C 10-BIT ADDRESS FORMAT
S
R/W
ACK
9
8
2
1
S
Start
Condition
LSb
S
acknowledge
SCL from
Master
FIGURE 11-15: 7-BIT ADDRESS FORMAT
MSb
not acknowledge
- Start Condition
- Read/Write Pulse
- Acknowledge
TRANSFER ACKNOWLEDGE
All data must be transmitted per byte, with no limit to the
number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an acknowledge bit (ACK) (Figure 11-17). When a slave-receiver
doesn’t acknowledge the slave address or received
data, the master must abort the transfer. The slave
must leave SDA high so that the master can generate
the STOP condition (Figure 11-14).
FIGURE 11-18: DATA TRANSFER WAIT STATE
SDA
MSB
acknowledgment
signal from receiver
byte complete
interrupt with receiver
acknowledgment
signal from receiver
clock line held low while
interrupts are serviced
SCL
S
Start
Condition
DS30234D-page 96
1
2
Address
7
8
9
R/W
ACK
1
Wait
State
2
Data
3•8
9
ACK
P
Stop
Condition
 1997 Microchip Technology Inc.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PIC16C6X
SCL is high), but occurs after a data transfer acknowledge pulse (not the bus-free state). This allows a master to send “commands” to the slave and then receive
the requested information or to address a different
slave device. This sequence is shown in Figure 11-21.
Figure 11-19 and Figure 11-20 show Master-transmitter and Master-receiver data transfer sequences.
When a master does not wish to relinquish the bus (by
generating a STOP condition), a repeated START condition (Sr) must be generated. This condition is identical to the start condition (SDA goes high-to-low while
FIGURE 11-19: MASTER-TRANSMITTER SEQUENCE
For 10-bit address:
S Slave Address R/W A1 Slave Address A2
Second byte
First 7 bits
For 7-bit address:
S Slave Address R/W A Data A Data A/A P
'0' (write)
data transferred
(n bytes - acknowledge)
A master transmitter addresses a slave receiver with a
7-bit address. The transfer direction is not changed.
From master to slave
From slave to master
(write)
Data A
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Data A/A P
A master transmitter addresses a slave receiver
with a 10-bit address.
FIGURE 11-20: MASTER-RECEIVER SEQUENCE
For 10-bit address:
For 7-bit address:
S Slave Address R/W A1 Slave Address A2
Second byte
First 7 bits
S Slave Address R/W A Data A Data A P
'1' (read)
data transferred
(n bytes - acknowledge)
A master reads a slave immediately after the first byte.
From master to slave
From slave to master
(write)
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
Sr Slave Address R/W A3 Data A
First 7 bits
Data A P
(read)
A master transmitter addresses a slave receiver
with a 10-bit address.
FIGURE 11-21: COMBINED FORMAT
(read or write)
(n bytes + acknowledge)
S Slave Address R/W A Data A/A Sr Slave Address R/W A Data A/A P
(read)
Sr = repeated
Start Condition
(write)
Direction of transfer
may change at this point
Transfer direction of data and acknowledgment bits depends on R/W bits.
Combined format:
Sr Slave Address R/W A Slave Address A Data A
First 7 bits
Second byte
Data A/A Sr Slave Address R/W A Data A
First 7 bits
Data A P
(read)
(write)
Combined format - A master addresses a slave with a 10-bit address, then transmits
data to this slave and reads data from this slave.
From master to slave
From slave to master
 1997 Microchip Technology Inc.
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
S = Start Condition
P = Stop Condition
DS30234D-page 97
PIC16C6X
11.4.4
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
MULTI-MASTER
11.2.4.2 Clock Synchronization
The I2C protocol allows a system to have more than
one master. This is called multi-master. When two or
more masters try to transfer data at the same time, arbitration and synchronization occur.
11.4.4.1
ARBITRATION
Arbitration takes place on the SDA line, while the SCL
line is high. The master which transmits a high when
the other master transmits a low loses arbitration
(Figure 11-22), and turns off its data output stage. A
master which lost arbitration can generate clock pulses
until the end of the data byte where it lost arbitration.
When the master devices are addressing the same
device, arbitration continues into the data.
FIGURE 11-22: MULTI-MASTER
ARBITRATION
(TWO MASTERS)
Clock synchronization occurs after the devices have
started arbitration. This is performed using a wiredAND connection to the SCL line. A high to low transition
on the SCL line causes the concerned devices to start
counting off their low period. Once a device clock has
gone low, it will hold the SCL line low until its SCL high
state is reached. The low to high transition of this clock
may not change the state of the SCL line, if another
device clock is still within its low period. The SCL line is
held low by the device with the longest low period.
Devices with shorter low periods enter a high waitstate, until the SCL line comes high. When the SCL line
comes high, all devices start counting off their high
periods. The first device to complete its high period will
pull the SCL line low. The SCL line high time is determined by the device with the shortest high period,
Figure 11-23.
FIGURE 11-23: CLOCK SYNCHRONIZATION
transmitter 1 loses arbitration
DATA 1 SDA
wait
state
DATA 1
DATA 2
start counting
HIGH period
CLK
1
SDA
CLK
2
counter
reset
SCL
SCL
Masters that also incorporate the slave function, and
have lost arbitration must immediately switch over to
slave-receiver mode. This is because the winning master-transmitter may be addressing it.
Arbitration is not allowed between:
• A repeated START condition
• A STOP condition and a data bit
• A repeated START condition and a STOP condition
Care needs to be taken to ensure that these conditions
do not occur.
DS30234D-page 98
 1997 Microchip Technology Inc.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
11.5
SSP I2C Operation
The SSP module in I 2C mode fully implements all slave
functions, except general call support, and provides
interrupts on start and stop bits in hardware to facilitate
firmware implementations of the master functions. The
SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins
are used for data transfer. These are the RC3/SCK/
SCL pin, which is the clock (SCL), and the RC4/SDI/
SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the
TRISC<4:3> bits. The SSP module functions are
enabled by setting SSP Enable bit SSPEN (SSPCON<5>).
FIGURE 11-24: SSP BLOCK DIAGRAM
(I2C MODE)
Internal
data bus
Read
Write
SSPBUF reg
RC3/SCK/SCL
shift
clock
SSPSR reg
RC4/
SDI/
SDA
MSb
LSb
Match detect
Addr Match
SSPADD reg
Start and
Stop bit detect
Set, Reset
S, P bits
(SSPSTAT reg)
The SSP module has five registers for I2C operation.
These are the:
PIC16C6X
The SSPCON register allows control of the I2C operation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I 2C modes to be selected:
• I 2C Slave mode (7-bit address)
• I 2C Slave mode (10-bit address)
• I 2C Slave mode (7-bit address), with start and
stop bit interrupts enabled
• I 2C Slave mode (10-bit address), with start and
stop bit interrupts enabled
• I 2C Firmware controlled Master Mode, slave is
idle
Selection of any I 2C mode, with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting
the appropriate TRISC bits.
The SSPSTAT register gives the status of the data
transfer. This information includes detection of a
START or STOP bit, specifies if the received byte was
data or address if the next byte is the completion of 10bit address, and if this will be a read or write data transfer. The SSPSTAT register is read only.
The SSPBUF is the register to which transfer data is
written to or read from. The SSPSR register shifts the
data in or out of the device. In receive operations, the
SSPBUF and SSPSR create a doubled buffered
receiver. This allows reception of the next byte to begin
before reading the last byte of received data. When the
complete byte is received, it is transferred to the
SSPBUF register and flag bit SSPIF is set. If another
complete byte is received before the SSPBUF register
is read, a receiver overflow has occurred and bit
SSPOV (SSPCON<6>) is set and the byte in the
SSPSR is lost.
The SSPADD register holds the slave address. In 10-bit
mode, the user first needs to write the high byte of the
address (1111 0 A9 A8 0). Following the high byte
address match, the low byte of the address needs to be
loaded (A7:A0).
•
•
•
•
SSP Control Register (SSPCON)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not directly accessible
• SSP Address Register (SSPADD)
 1997 Microchip Technology Inc.
DS30234D-page 99
PIC16C6X
11.5.1
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
SLAVE MODE
In slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will
override the input state with the output data when
required (slave-transmitter).
When an address is matched or the data transfer after
an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
There are certain conditions that will cause the SSP
module not to give this ACK pulse. These are if either
(or both):
a)
b)
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 11-4 shows what happens when a data transfer
byte is received, given the status of bits BF and SSPOV.
The shaded cells show the condition where user software did not properly clear the overflow condition. Flag
bit BF is cleared by reading the SSPBUF register while
bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification as well as the requirement of the SSP
module is shown in timing parameter #100 and parameter #101.
11.5.1.1
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
In 10-bit address mode, two address bytes need to be
received by the slave (Figure 11-16). The five Most Significant bits (MSbs) of the first address byte specify if
this is a 10-bit address. Bit R/W (SSPSTAT<2>) must
specify a write so the slave device will receive the second address byte. For a 10-bit address the first byte
would equal ‘1111 0 A9 A8 0’, where A9 and A8 are
the two MSbs of the address. The sequence of events
for 10-bit address is as follows, with steps 7- 9 for slavetransmitter:
1.
2.
3.
4.
5.
ADDRESSING
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
TABLE 11-4:
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit, BF is set.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
6.
7.
8.
9.
Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of Address, if match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive repeated START condition.
Receive first (high) byte of Address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
Set bit SSPIF
(SSP Interrupt occurs
if enabled)
BF
SSPOV
SSPSR → SSPBUF
Generate ACK
Pulse
0
0
Yes
Yes
Yes
1
0
No
No
Yes
1
1
No
No
Yes
0
1
No
No
Yes
DS30234D-page 100
 1997 Microchip Technology Inc.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
11.5.1.2
PIC16C6X
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the
status of the byte.
RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the
SSPBUF register.
When the address byte overflow condition exists, then
no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set
or bit SSPOV (SSPCON<6>) is set.
FIGURE 11-25: I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address
Receiving Data
R/W=0
Receiving Data
ACK
ACK
ACK
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
S
1
2
3
4
5
6
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
8
7
Cleared in software
9
P
Bus Master
terminates
transfer
SSPBUF register is read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
 1997 Microchip Technology Inc.
DS30234D-page 101
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PIC16C6X
11.5.1.3
TRANSMISSION
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RC3/SCK/SCL is held
low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register.
Then pin RC3/SCK/SCL should be enabled by setting
bit CKP (SSPCON<4>). The master must monitor the
SCL pin prior to asserting another clock pulse. The
slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the
falling edge of the SCL input. This ensures that the SDA
signal is valid during the SCL high time (Figure 11-26).
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then the
data transfer is complete. When the ACK is latched by
the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the START bit. If the SDA line was low (ACK),
the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin
RC3/SCK/SCL should be enabled by setting bit CKP.
FIGURE 11-26: I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address
SDA
SCL
A7
S
A6
1
2
Data in
sampled
R/W = 1
A5
A4
A3
A2
A1
3
4
5
6
7
8
9
ACK
Transmitting Data
ACK
D7
1
SCL held low
while CPU
responds to SSPIF
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
cleared in software
SSPBUF is written in software
From SSP interrupt
service routine
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written-to
before the CKP bit can be set)
DS30234D-page 102
 1997 Microchip Technology Inc.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
11.5.2
11.5.3
MASTER MODE
MULTI-MASTER MODE
In multi-master mode, the interrupt generation on the
detection of the START and STOP conditions allows
the determination of when the bus is free. The STOP
(P) and START (S) bits are cleared from a reset or
when the SSP module is disabled. The STOP (P) and
START (S) bits will toggle based on the START and
STOP conditions. Control of the I2C bus may be taken
when bit P (SSPSTAT<4>) is set, or the bus is idle and
both the S and P bits clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the STOP condition occurs.
Master mode of operation is supported in firmware
using interrupt generation on the detection of the
START and STOP conditions. The STOP (P) and
START (S) bits are cleared from a reset or when the
SSP module is disabled. The STOP (P) and START (S)
bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when the P
bit is set, or the bus is idle and both the S and P bits are
clear.
In master mode the SCL and SDA lines are manipulated by clearing the corresponding TRISC<4:3> bit(s).
The output level is always low, irrespective of the
value(s) in PORTC<4:3>. So when transmitting data, a
'1' data bit must have the TRISC<4> bit set (input) and
a '0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the
TRISC<3> bit.
In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output
level. This check only needs to be done when a high
level is output. If a high level is expected and a low level
is present, the device needs to release the SDA and
SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost, these are:
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• Address Transfer
• Data Transfer
• START condition
• STOP condition
• Data transfer byte transmitted/received
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address transfer stage, communication to the device may be in
progress. If addressed an ACK pulse will be generated.
If arbitration was lost during the data transfer stage, the
device will need to re-transfer the data at a later time.
Master mode of operation can be done with either the
slave mode idle (SSPM3:SSPM0 = 1011) or with the
slave active. When both master and slave modes are
enabled, the software needs to differentiate the
source(s) of the interrupt.
TABLE 11-5:
PIC16C6X
REGISTERS ASSOCIATED WITH I2C OPERATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on all
other resets
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
PIR1
PSPIF(1)
(2)
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
(2)
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
0000 0000
0000 0000
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
93h
SSPADD Synchronous Serial Port (I2C mode) Address Register
0000 0000
0000 0000
14h
SSPCON
WCOL
SSPOV SSPEN
0000 0000
0000 0000
94h
SSPSTAT
SMP(3)
CKE(3)
0000 0000
0000 0000
87h
TRISC
1111 1111
1111 1111
Address
Name
0Bh, 8Bh, INTCON
10Bh, 18Bh
0Ch
D/A
PORTC Data Direction register
CKP
P
SSPM3 SSPM2 SSPM1 SSPM0
S
R/W
UA
BF
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.
Shaded cells are not used by SSP module in SPI mode.
Note 1: PSPIF and PSPIE are reserved on the PIC16C66, always maintain these bits clear.
2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.
3: The SMP and CKE bits are implemented on the PIC16C66/67 only. All other PIC16C6X devices have these two bits unimplemented, read as '0'.
 1997 Microchip Technology Inc.
DS30234D-page 103
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PIC16C6X
FIGURE 11-27: OPERATION OF THE I 2C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE
IDLE_MODE (7-bit):
if (Addr_match)
{
Set interrupt;
if (R/W = 1)
{
Send ACK = 0;
set XMIT_MODE;
}
else if (R/W = 0) set RCV_MODE;
}
RCV_MODE:
if ((SSPBUF=Full) OR (SSPOV = 1))
{
Set SSPOV;
Do not acknowledge;
}
else
{
transfer SSPSR → SSPBUF;
send ACK = 0;
}
Receive 8-bits in SSPSR;
Set interrupt;
XMIT_MODE:
While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low;
Send byte;
Set interrupt;
if ( ACK Received = 1)
{
End of transmission;
Go back to IDLE_MODE;
}
else if ( ACK Received = 0) Go back to XMIT_MODE;
IDLE_MODE (10-Bit):
If (High_byte_addr_match AND (R/W = 0))
{
PRIOR_ADDR_MATCH = FALSE;
Set interrupt;
if ((SSPBUF = Full) OR ((SSPOV = 1))
{
Set SSPOV;
Do not acknowledge;
}
else
{
Set UA = 1;
Send ACK = 0;
While (SSPADD not updated) Hold SCL low;
Clear UA = 0;
Receive Low_addr_byte;
Set interrupt;
Set UA = 1;
If (Low_byte_addr_match)
{
PRIOR_ADDR_MATCH = TRUE;
Send ACK = 0;
while (SSPADD not updated) Hold SCL low;
Clear UA = 0;
Set RCV_MODE;
}
}
}
else if (High_byte_addr_match AND (R/W = 1)
{
if (PRIOR_ADDR_MATCH)
{
send ACK = 0;
set XMIT_MODE;
}
else PRIOR_ADDR_MATCH = FALSE;
}
DS30234D-page 104
 1997 Microchip Technology Inc.
PIC16C6X
12.0
UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
MODULE
minals and personal computers, or it can be configured
as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, Serial EEPROMs etc.
The USART can be configured in the following modes:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
• Asynchronous (full duplex)
• Synchronous - Master (half duplex)
• Synchronous - Slave (half duplex)
The Universal Synchronous Asynchronous Receiver
Transmitter (USART) module is one of the two serial
I/O modules. (USART is also known as a Serial Communications Interface or SCI) The USART can be configured as a full duplex asynchronous system that can
communicate with peripheral devices such as CRT ter-
Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to
be set in order to configure pins RC6/TX/CK and
RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter.
FIGURE 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0
CSRC
bit7
bit 7:
R/W-0
TX9
R/W-0
TXEN
R/W-0
SYNC
U-0
—
R/W-0
BRGH
R-1
TRMT
R/W-0
TX9D
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n =Value at POR reset
CSRC: Clock Source Select bit
Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6:
TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5:
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
Note: SREN/CREN overrides TXEN in SYNC mode.
bit 4:
SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 3:
Unimplemented: Read as '0'
bit 2:
BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
Note: For the PIC16C63/R63/65/65A/R65 the asynchronous high speed mode (BRGH = 1) may
experience a high rate of receive errors. It is recommended that BRGH = 0. If you desire a
higher baud rate than BRGH = 0 can support, refer to the device errata for additional information or use the PIC16C66/67.
0 = Low speed
Synchronous mode
Unused in this mode
bit 1:
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
bit 0:
TX9D: 9th bit of transmit data. Can be parity bit.
 1997 Microchip Technology Inc.
DS30234D-page 105
PIC16C6X
FIGURE 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0
SPEN
bit7
R/W-0
RX9
R/W-0
SREN
R/W-0
CREN
U-0
—
R-0
FERR
R-0
OERR
R-x
RX9D
bit0
R
W
U
= Readable bit
= Writable bit
= Unimplemented
bit, read as ‘0’
- n = Value at POR reset
x
= unknown
bit 7:
SPEN: Serial Port Enable bit
(Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins when bits TRISC<7:6> are set)
1 = Serial port enabled
0 = Serial port disabled
bit 6:
RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5:
SREN: Single Receive Enable bit
Asynchronous mode
Don’t care
Synchronous mode - master
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave
Unused in this mode
bit 4:
CREN: Continuous Receive Enable bit
Asynchronous mode
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3:
Unimplemented: Read as '0'
bit 2:
FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1:
OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0:
RX9D: 9th bit of received data (Can be parity bit)
DS30234D-page 106
 1997 Microchip Technology Inc.
PIC16C6X
12.1
USART Baud Rate Generator (BRG)
EXAMPLE 12-1: CALCULATING BAUD
RATE ERROR
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Desired Baud rate = Fosc / (64 (X + 1))
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit
baud rate generator. The SPBRG register controls the
period of a free running 8-bit timer. In asynchronous
mode bit BRGH (TXSTA<2>) also controls the baud
rate. In synchronous mode bit BRGH is ignored.
Table 12-1 shows the formula for computation of the
baud rate for different USART modes which only apply
in master mode (internal clock).
Given the desired baud rate and Fosc, the nearest integer value for the SPBRG register can be calculated
using the formula in Table 12-1. From this, the error in
baud rate can be determined.
Example 12-1 shows the calculation of the baud rate
error for the following conditions:
9600 =
16000000 /(64 (X + 1))
X
25.042 = 25
=
Calculated Baud Rate=16000000 / (64 (25 + 1))
=
Error
=
9615
(Calculated Baud Rate - Desired Baud Rate)
Desired Baud Rate
=
(9615 - 9600) / 9600
=
0.16%
It may be advantageous to use the high baud rate
(BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
baud rate error in some cases.
Note:
FOSC = 16 MHz
Desired Baud Rate = 9600
BRGH = 0
SYNC = 0
For the PIC16C63/R63/65/65A/R65 the
asynchronous
high
speed
mode
(BRGH = 1) may experience a high rate of
receive errors. It is recommended that
BRGH = 0. If you desire a higher baud rate
than BRGH = 0 can support, refer to the
device errata for additional information or
use the PIC16C66/67.
Writing a new value to the SPBRG register, causes the
BRG timer to be reset (or cleared), this ensures that the
BRG does not wait for a timer overflow before outputting the new baud rate.
TABLE 12-1:
BAUD RATE FORMULA
SYNC
BRGH = 0 (Low Speed)
BRGH = 1 (High Speed)
0
(Asynchronous) Baud Rate = FOSC/(64(X+1))
(Synchronous) Baud Rate = FOSC/(4(X+1))
1
X = value in SPBRG (0 to 255)
TABLE 12-2:
Address
Baud Rate = FOSC/(16(X+1))
N/A
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
18h
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
99h
SPBRG
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.
 1997 Microchip Technology Inc.
Value on
POR,
BOR
Value on
all other
Resets
0000 -010 0000 -010
0000 -00x 0000 -00x
0000 0000 0000 0000
DS30234D-page 107
PIC16C6X
TABLE 12-3:
BAUD
RATE
(K)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 20 MHz
KBAUD
NA
NA
NA
NA
19.53
76.92
96.15
294.1
500
5000
19.53
16 MHz
SPBRG
value
%
KBAUD
ERROR (decimal)
+1.73
+0.16
+0.16
-1.96
0
-
255
64
51
16
9
0
255
FOSC = 5.0688 MHz
BAUD
RATE
(K)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
+0.16
+0.16
-0.79
+2.56
0
-
207
51
41
12
7
0
255
4 MHz
NA
NA
NA
9.766
19.23
75.76
96.15
312.5
500
2500
9.766
7.15909 MHz
SPBRG
SPBRG
value
value
%
%
KBAUD
ERROR (decimal)
ERROR (decimal)
+1.73
+0.16
-1.36
+0.16
+4.17
0
-
255
129
32
25
7
4
0
255
3.579545 MHz
NA
NA
NA
9.622
19.24
77.82
94.20
298.3
NA
1789.8
6.991
+0.23
+0.23
+1.32
-1.88
-0.57
-
1 MHz
185
92
22
18
5
0
255
32.768 kHz
SPBRG
SPBRG
SPBRG
SPBRG
SPBRG
KBAUD
%
value KBAUD
%
value
KBAUD
%
value KBAUD
%
value KBAUD
%
value
ERROR (decimal)
ERROR (decimal)
ERROR (decimal)
ERROR (decimal)
ERROR (decimal)
NA
NA
NA
9.6
19.2
79.2
97.48
316.8
NA
1267
4.950
TABLE 12-4:
BAUD
RATE
(K)
NA
NA
NA
NA
19.23
76.92
95.24
307.69
500
4000
15.625
10 MHz
SPBRG
value
%
KBAUD
ERROR (decimal)
0
0
+3.13
+1.54
+5.60
-
131
65
15
12
3
0
255
NA
NA
NA
9.615
19.231
76.923
1000
NA
NA
100
3.906
NA
1.221
2.404
9.469
19.53
78.13
104.2
312.5
NA
312.5
1.221
103
51
12
9
0
255
NA
NA
NA
9.622
19.04
74.57
99.43
298.3
NA
894.9
3.496
+0.23
-0.83
-2.90
+3.57
-0.57
-
92
46
11
8
2
0
255
NA
1.202
2.404
9.615
19.24
83.34
NA
NA
NA
250
0.9766
+0.16
+0.16
+0.16
+0.16
+8.51
-
207
103
25
12
2
0
255
0.303
1.170
NA
NA
NA
NA
NA
NA
NA
8.192
0.032
+1.14
-2.48
-
26
6
0
255
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz
KBAUD
+0.16
+0.16
+0.16
+4.17
-
16 MHz
SPBRG
%
value
ERROR (decimal) KBAUD
+1.73
+0.16
-1.36
+1.73
+1.73
+8.51
+4.17
-
255
129
32
15
3
2
0
0
255
FOSC = 5.0688 MHz
NA
1.202
2.404
9.615
19.23
83.33
NA
NA
NA
250
0.977
10 MHz
SPBRG
%
value
ERROR (decimal) KBAUD
+0.16
+0.16
+0.16
+0.16
+8.51
-
207
103
25
12
2
0
255
4 MHz
NA
1.202
2.404
9.766
19.53
78.13
NA
NA
NA
156.3
0.6104
7.15909 MHz
SPBRG
SPBRG
%
value
%
value
ERROR (decimal) KBAUD ERROR (decimal)
+0.16
+0.16
+1.73
+1.73
+1.73
-
3.579545 MHz
129
64
15
7
1
0
255
NA
1.203
2.380
9.322
18.64
NA
NA
NA
NA
111.9
0.437
+0.23
-0.83
-2.90
-2.90
-
1 MHz
92
46
11
5
0
255
32.768 kHz
BAUD
RATE
(K)
SPBRG
SPBRG
SPBRG
SPBRG
SPBRG
%
value
%
value
%
value
%
value
%
value
KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal)
0.3
1.2
2.4
9.6
19.2
76.8
96
300
500
HIGH
LOW
0.31
1.2
2.4
9.9
19.8
79.2
NA
NA
NA
79.2
0.3094
+3.13
0
0
+3.13
+3.13
+3.13
-
DS30234D-page 108
255
65
32
7
3
0
0
255
0.3005
1.202
2.404
NA
NA
NA
NA
NA
NA
62.500
3.906
-0.17
+1.67
+1.67
-
207
51
25
0
255
0.301
1.190
2.432
9.322
18.64
NA
NA
NA
NA
55.93
0.2185
+0.23
-0.83
+1.32
-2.90
-2.90
-
185
46
22
5
2
0
255
0.300
1.202
2.232
NA
NA
NA
NA
NA
NA
15.63
0.0610
+0.16
+0.16
-6.99
-
51
12
6
0
255
0.256
NA
NA
NA
NA
NA
NA
NA
NA
0.512
0.0020
-14.67
-
1
0
255
 1997 Microchip Technology Inc.
PIC16C6X
TABLE 12-5:
BAUD
RATE
(K)
9.6
19.2
38.4
57.6
115.2
250
625
1250
BAUD
RATE
(K)
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz
KBAUD
9.615
19.230
37.878
56.818
113.636
250
625
1250
16 MHz
SPBRG
%
value
ERROR (decimal) KBAUD
+0.16
+0.16
-1.36
-1.36
-1.36
0
0
0
129
64
32
21
10
4
1
0
9.615
19.230
38.461
58.823
111.111
250
NA
NA
10 MHz
SPBRG
%
value
ERROR (decimal) KBAUD
+0.16
+0.16
+0.16
+2.12
-3.55
0
-
103
51
25
16
8
3
-
9.615
18.939
39.062
56.818
125
NA
625
NA
7.16 MHz
SPBRG
SPBRG
%
value
%
value
ERROR (decimal) KBAUD ERROR (decimal)
+0.16
-1.36
+1.7
-1.36
+8.51
0
-
64
32
15
10
4
0
-
9.520
19.454
37.286
55.930
111.860
NA
NA
NA
-0.83
+1.32
-2.90
-2.90
-2.90
-
46
22
11
7
3
-
FOSC = 5.068 MHz
4 MHz
3.579 MHz
1 MHz
32.768 kHz
SPBRG
SPBRG
SPBRG
SPBRG
SPBRG
%
value
%
value
%
value
%
value
%
value
KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal)
9.6
19.2
9.6
18.645
0
-2.94
32
16
NA
1.202
38.4
57.6
115.2
250
625
1250
39.6
52.8
105.6
NA
NA
NA
+3.12
-8.33
-8.33
-
7
5
2
-
2.403
9.615
19.231
NA
NA
NA
Note:
+0.17
+0.13
+0.16
+0.16
-
207
9.727
18.643
+1.32
-2.90
22
11
8.928
20.833
-6.99
+8.51
6
2
NA
NA
-
-
103
25
12
-
37.286 -2.90
55.930 -2.90
111.860 -2.90
223.721 -10.51
NA
NA
-
5
3
1
0
-
31.25
62.5
NA
NA
NA
NA
-18.61
+8.51
-
1
0
-
NA
NA
NA
NA
NA
NA
-
-
For the PIC16C63/R63/65/65A/R65 the asynchronous high speed mode (BRGH = 1) may experience a
high rate of receive errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH
= 0 can support, refer to the device errata for additional information or use the PIC16C66/67.
 1997 Microchip Technology Inc.
DS30234D-page 109
PIC16C6X
12.1.1
set (i.e., at the high baud rates), the sampling is done
on the 3 clock edges preceding the second rising edge
after the first falling edge of a x4 clock (Figure 12-4 and
Figure 12-5).
SAMPLING
The data on the RC7/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin. If bit BRGH
(TXSTA<2>) is clear (i.e., at the low baud rates), the
sampling is done on the seventh, eighth and ninth falling edges of a x16 clock (Figure 12-3). If bit BRGH is
FIGURE 12-3: RX PIN SAMPLING SCHEME (BRGH = 0) PIC16C63/R63/65/65A/R65)
Start bit
RX
(RC7/RX/DT pin)
Bit0
Baud CLK for all but start bit
baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
Samples
FIGURE 12-4: RX PIN SAMPLING SCHEME (BRGH = 1) (PIC16C63/R63/65/65A/R65)
RC7/RX/DT pin
bit0
Start Bit
bit1
baud clk
First falling edge after RX pin goes low
Second rising edge
x4 clk
1
2
3
4
1
2
3
4
1
2
Q2, Q4 clk
Samples
Samples
Samples
FIGURE 12-5: RX PIN SAMPLING SCHEME (BRGH = 1) (PIC16C63/R63/65/65A/R65)
RC7/RX/DT pin
Start Bit
bit0
Baud clk for all but start bit
baud clk
First falling edge after RX pin goes low
Second rising edge
x4 clk
1
2
3
4
Q2, Q4 clk
Samples
DS30234D-page 110
 1997 Microchip Technology Inc.
PIC16C6X
FIGURE 12-6: RX PIN SAMPLING SCHEME (BRGH = 0 OR = 1) (PIC16C66/67)
Start bit
RX
(RC7/RX/DT pin)
Bit0
Baud CLK for all but start bit
baud CLK
x16 CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
Samples
 1997 Microchip Technology Inc.
DS30234D-page 111
PIC16C6X
12.2
USART Asynchronous Mode
abled by setting/clearing enable bit TXIE (PIE1<4>).
Flag bit TXIF will be set regardless of the state of
enable bit TXIE and cannot be cleared in software. It
will reset only when new data is loaded into the TXREG
register. While flag bit TXIF indicates the status of the
TXREG register, another bit, TRMT (TXSTA<1>)
shows the status of the TSR register. Status bit TRMT
is a read only bit which is set when the TSR register is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR register is empty.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
In this mode, the USART uses standard nonreturn-tozero (NRZ) format (one start bit, eight or nine data bits
and one stop bit). The most common data format is
8-bits. An on-chip dedicated 8-bit baud rate generator
can be used to derive standard baud rate frequencies
from the oscillator. The USART transmits and receives
the LSb first. The USART’s transmitter and receiver are
functionally independent but use the same data format
and baud rate. The baud rate generator produces a
clock either x16 or x64 of the bit shift rate, depending
on bit BRGH (TXSTA<2>). Parity is not supported by
the hardware, but can be implemented in software (and
stored as the ninth data bit). Asynchronous mode is
stopped during SLEEP.
Note 1: The TSR register is not mapped in data
memory so it is not available to the user.
Note 2: Flag bit TXIF is set when enable bit TXEN
is set.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data
and the baud rate generator (BRG) has produced a
shift clock (Figure 12-7). The transmission can also be
started by first loading the TXREG register and then
setting enable bit TXEN. Normally when transmission
is first started, the TSR register is empty, so a transfer
to the TXREG register will result in an immediate transfer to TSR register resulting in an empty TXREG register. A back-to-back transfer is thus possible (Figure 129). Clearing enable bit TXEN during a transmission will
cause the transmission to be aborted and will reset the
transmitter. As a result the RC6/TX/CK pin will revert to
hi-impedance.
Asynchronous mode is selected by clearing bit SYNC
(TXSTA<4>).
The USART Asynchronous module consists of the following important elements:
•
•
•
•
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
12.2.1
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 12-7. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer, TXREG. The
TXREG register is loaded with data in software. The
TSR register is not loaded until the STOP bit has been
transmitted from the previous load. As soon as the
STOP bit is transmitted, the TSR is loaded with new
data from the TXREG (if available). Once the TXREG
register transfers the data to the TSR register (occurs
in one TCY) the TXREG register is empty and flag bit
TXIF (PIR1<4>) is set. This interrupt is enabled/dis-
In order to select 9-bit transmission, transmit bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to bit TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). In such a case, an
incorrect ninth data bit maybe loaded in the TSR register.
FIGURE 12-7: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF
TXREG register
TXIE
8
MSb
LSb
• • •
(8)
Pin Buffer
and Control
0
TSR register
RC6/TX/CK pin
Interrupt
TXEN
Baud Rate CLK
TRMT
SPEN
SPBRG
Baud Rate Generator
TX9
TX9D
DS30234D-page 112
 1997 Microchip Technology Inc.
PIC16C6X
Steps to follow when setting up an Asynchronous
Transmission:
5.
1.
6.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
then set bit BRGH. (Section 12.1).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set transmit
bit TX9.
2.
3.
4.
7.
Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Load data to the TXREG register (starts transmission).
FIGURE 12-8: ASYNCHRONOUS MASTER TRANSMISSION
Write to TXREG reg
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
Start Bit
Bit 0
Bit 1
Bit 7/8
Stop Bit
WORD 1
TXIF bit
(Transmit buffer
reg. empty flag)
WORD 1
Transmit Shift Reg
TRMT bit
(Transmit shift
reg. empty flag)
FIGURE 12-9: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Write to TXREG reg
Word 1
BRG output
(shift clock)
RC6/TX/CK (pin)
TXIF bit
(interrupt reg. flag)
TRMT bit
(Transmit shift
reg. empty flag)
Word 2
Start Bit
Bit 0
Bit 1
WORD 1
Bit 7/8
Stop Bit
Start Bit
Bit 0
WORD 2
WORD 1
Transmit Shift Reg.
WORD 2
Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 12-6:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Value on
POR,
BOR
Value on
all other
Resets
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Ch
PIR1
PSPIF(1)
(2)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
0000 0000
0000 0000
18h
RCSTA
19h
TXREG
8Ch
PIE1
SPEN
RX9
SREN
CREN
—
FERR
OERR
USART Transmit Register
PSPIE(1)
(2)
RCIE
TXIE
SSPIE CCP1IE
TMR2IE
TMR1IE
0000 -010 0000 -010
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
98h
TXSTA
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission.
Note 1: PSPIF and PSPIE are reserved on the PIC16C63/R63/66, always maintain these bits clear.
2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.
 1997 Microchip Technology Inc.
DS30234D-page 113
PIC16C6X
12.2.2
possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte begin shifting to the RSR register. On the detection of the STOP
bit of the third byte, if the RCREG is still full, then the
overrun error bit, OERR (RCSTA<1>) will be set. The
word in the RSR register will be lost. The RCREG register can be read twice to retrieve the two bytes in the
FIFO. Overrun bit OERR has to be cleared in software.
This is done by resetting the receive logic (CREN is
cleared and then set). If bit OERR is set, transfers from
the RSR register to the RCREG register are inhibited,
so it is essential to clear overrun bit OERR if it is set.
Framing error bit FERR (RCSTA<2>) is set if a stop bit
is detected as clear. Error bit FERR and the 9th receive
bit are buffered the same way as the receive data.
Reading the RCREG register will load bits RX9D and
FERR with new values. Therefore it is essential for the
user to read the RCSTA register before reading
RCREG in order not to lose the old FERR and RX9D
information.
USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 12-10.
The data comes in the RC7/RX/DT pin and drives the
data recovery block. The data recovery block is actually
a high speed shifter operating at x16 times the baud
rate, whereas the main receive serial shifter operates
at the bit rate or at FOSC.
Once Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift register (RSR). After sampling the STOP bit, the received
data in the RSR is transferred to the RCREG register (if
it is empty). If the transfer is complete, flag bit RCIF
(PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is
double buffered register, i.e., it is a two deep FIFO. It is
FIGURE 12-10: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
FERR
OERR
CREN
SPBRG
÷ 64
or
÷ 16
Baud Rate Generator
RSR register
MSb
Stop (8)
• • •
7
1
LSb
0 Start
RC7/RX/DT
Pin Buffer
and Control
Data
Recovery
RX9
RX9D
SPEN
RCREG register
FIFO
8
RCIF
Interrupt
Data Bus
RCIE
FIGURE 12-11: ASYNCHRONOUS RECEPTION
RC7/RX/DT (pin)
Rcv shift
reg
Rcv buffer reg
Read Rcv
buffer reg
RCREG
Start
bit
bit0
bit1
bit7/8 Stop
bit
Start
bit
WORD 1
RCREG
bit0
bit7/8
Stop
bit
Start
bit
bit7/8
Stop
bit
WORD 2
RCREG
RCIF
(interrupt flag)
OERR bit
CREN bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing overrun error bit OERR to be set.
DS30234D-page 114
 1997 Microchip Technology Inc.
PIC16C6X
6.
Steps to follow when setting up an Asynchronous
Reception:
1.
2.
3.
4.
5.
Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 12.1).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting enable bit
CREN.
TABLE 12-7:
7.
8.
9.
Flag bit RCIF will be set when reception is complete, and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address
Name
Bit 7
Bit 6
0Ch
PIR1
PSPIF(1)
(2)
18h
RCSTA
SPEN
RX9
1Ah
RCREG
8Ch
PIE1
98h
TXSTA
99h
SPBRG
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
TMR2IE
TMR1IE
0000 0000
0000 0000
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Bit 5
USART Receive Register
PSPIE(1)
(2)
RCIE
TXIE
CSRC
TX9
TXEN
SYNC
Baud Rate Generator Register
SSPIE CCP1IE
—
BRGH
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.
Note 1: PSPIE and PSPIF are reserved on the PIC16C63/R63/66, always maintain these bits clear.
2: PIE1<6> and PIR1<6> are reserved, always maintain these bits clear.
 1997 Microchip Technology Inc.
DS30234D-page 115
PIC16C6X
12.3
USART Synchronous Master Mode
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
In Synchronous Master mode the data is transmitted in
a half-duplex manner i.e., transmission and reception
do not occur at the same time. When transmitting data
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition enable bit SPEN (RCSTA<7>) is set in order to
configure the RC6 and RC7 I/O pins to CK (clock) and
DT (data) lines respectively. The Master mode indicates that the processor transmits the master clock on
the CK line. The Master mode is entered by setting bit
CSRC (TXSTA<7>).
12.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
Clearing enable bit TXEN, during a transmission, will
cause the transmission to be aborted and will reset the
transmitter. The DT and CK pins will revert to hi-impedance. If, during a transmission, either bit CREN or bit
SREN is set the transmission is aborted and the DT pin
reverts to a hi-impedance state (for a reception). The
CK pin will remain an output if bit CSRC is set (internal
clock). The transmitter logic however, is not reset
although it is disconnected from the pins. In order to
reset the transmitter, the user has to clear enable bit
TXEN. If enable bit SREN is set (to interrupt an on
going transmission and receive a single word), then
after the single word is received, enable bit SREN will
be cleared, and the serial port will revert back to transmitting since enable bit TXEN is still set. The DT line
will immediately switch from hi-impedance receive
mode to transmit and start driving. To avoid this, enable
bit TXEN should be cleared.
The USART transmitter block diagram is shown in
Figure 12-7. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register,
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR register is
loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to
the TSR register (occurs in one Tcycle), the TXREG
register is empty and interrupt flag bit TXIF (PIR1<4>)
is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF
will be set regardless of the status of enable bit TXIE
and cannot be cleared in software. It will clear only
when new data is loaded into the TXREG register.
While flag bit TXIF indicates the status of the TXREG
register, another bit, TRMT (TXSTA<1>), shows the
status of the TSR register. Status bit TRMT is a read
only bit which is set when the TSR register is empty. No
interrupt logic is tied to this bit, so the user has to poll
this bit in order to determine if the TSR register is
empty. The TSR register is not mapped in data memory
so it is not available to the user.
In order to select 9-bit transmission, bit TX9
(TXSTA<6>) should be set and the ninth bit should be
written to bit TX9D (TXSTA<0>). The ninth bit must be
written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the
TSR register (if the TSR is empty). If the TSR register
was empty and the TXREG register was written before
writing the “new” TX9D, the “present” value of bit TX9D
is loaded.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock
(Figure 12-12). The transmission can also be started by
first loading the TXREG register and then setting
enable bit TXEN (Figure 12-13). This is advantageous
when slow baud rates are selected, since the BRG is
kept in reset when bits TXEN, CREN, and SREN are
clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally when transmission is first started, the TSR register is empty, so a
transfer to the TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG register. Back-to-back transfers are possible.
7.
DS30234D-page 116
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
Initialize the SPBRG register for the appropriate
baud rate (Section 12.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
 1997 Microchip Technology Inc.
PIC16C6X
TABLE 12-8:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
0Ch
PIR1
PSPIF(1)
(2)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
18h
RCSTA
19h
TXREG
8Ch
PIE1
98h
TXSTA
99h
SPBRG
USART Transmit Register
PSPIE(1)
(2)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Synchronous Master Transmission.
Note 1: PSPIE and PSPIF are reserved on the PIC16C63/R63/66, always maintain these bits clear.
2: PIE1<6> and PIR1<6> are reserved, always maintain these bits clear.
FIGURE 12-12: SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
RC7/RX/DT pin
Bit 0
Bit 1
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
Bit 2
Bit 7
Bit 0
WORD 1
Bit 1
WORD 2
Bit 7
RC6/TX/CK pin
Write to
TXREG reg
Write word1
Write word2
TXIF bit
(Interrupt flag)
TRMT
TRMT bit
TXEN bit
'1'
'1'
Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words
FIGURE 12-13: SYNCHRONOUS TRANSMISSION THROUGH TXEN
RC7/RX/DT pin
bit0
bit1
bit2
bit6
bit7
RC6/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit
 1997 Microchip Technology Inc.
DS30234D-page 117
PIC16C6X
12.3.2
Steps to follow when setting up Synchronous Master
Reception:
USART SYNCHRONOUS MASTER
RECEPTION
1.
Initialize the SPBRG register for the appropriate
baud rate (Section 12.1).
2. Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
3. Ensure bits CREN and SREN are clear.
4. If interrupts are desired, then set enable bit
RCIE.
5. If 9-bit reception is desired, then set bit RX9.
6. If a single reception is required, set enable bit
SREN. For continuous reception set enable bit
CREN.
7. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable
bit RCIE was set.
8. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
9. Read the 8-bit received data by reading the
RCREG register.
10. If any error occurred, clear the error by clearing
enable bit CREN.
Once Synchronous Mode is selected, reception is
enabled by setting either enable bit SREN
(RCSTA<5>) bit or enable bit CREN (RCSTA<4>).
Data is sampled on the DT pin on the falling edge of the
clock. If enable bit SREN is set, then only a single word
is received. If enable bit CREN is set, the reception is
continuous until bit CREN is cleared. If both the bits are
set then bit CREN takes precedence. After clocking the
last bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the transfer is complete, interrupt bit
RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
reset by the hardware. In this case, it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register, i.e., it is a two
deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full, then overrun error bit, OERR
(RCSTA<1>) is set. The word in the RSR register will
be lost. The RCREG register can be read twice to
retrieve the two bytes in the FIFO. Overrun error bit
OERR has to be cleared in software (by clearing bit
CREN). If bit OERR is set, transfers from the RSR to
the RCREG are inhibited, so it is essential to clear bit
OERR if it is set. The 9th receive bit is buffered the
same way as the receive data. Reading the RCREG
register will load bit RX9D with a new value. Therefore
it is essential for the user to read the RCSTA register
before reading the RCREG register in order not to lose
the old RX9D bit information.
TABLE 12-9:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
0Ch
PIR1
PSPIF(1)
(2)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
0000 0000
0000 0000
18h
RCSTA
1Ah
RCREG
8Ch
PIE1
98h
TXSTA
99h
SPBRG
USART Receive Register
PSPIE(1)
(2)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
0000 0000
0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: PSPIF and PSPIE are reserved on the PIC16C63/R63/66, always maintain these bits clear.
2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.
DS30234D-page 118
 1997 Microchip Technology Inc.
PIC16C6X
FIGURE 12-14: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin
bit0
bit1
bit2
bit3
bit4
bit5
bit6
bit7
RC6/TX/CK pin
Write to
bit SREN
SREN bit
CREN bit '0'
'0'
RCIF bit
(interrupt)
Read
RXREG
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'.
 1997 Microchip Technology Inc.
DS30234D-page 119
PIC16C6X
12.4
USART Synchronous Slave Mode
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Synchronous Slave Mode differs from Master Mode in
the fact that the shift clock is supplied externally at the
CK pin (instead of being supplied internally in master
mode). This allows the device to transfer or receive
data while in SLEEP mode. Slave mode is entered by
clearing bit CSRC (TXSTA<7>).
12.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the synchronous master and slave
modes are identical except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in TXREG register.
Flag bit TXIF will not be set.
When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the interrupt vector (0004h).
12.4.2
The operation of the synchronous master and slave
modes is identical except in the case of the SLEEP
mode. Also, enable bit SREN is a don't care in slave
mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, then a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register
and if enable bit RCIE is set, the interrupt generated will
wake the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt vector
(0004h).
Steps to follow when setting up a Synchronous Slave
Reception:
1.
2.
3.
4.
5.
6.
Steps to follow when setting up Synchronous Slave
Transmission:
7.
1.
8.
2.
3.
4.
5.
6.
7.
Enable the synchronous slave serial port by setting bits SYNC and SPEN, and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
DS30234D-page 120
USART SYNCHRONOUS SLAVE
RECEPTION
Enable the synchronous master serial port by
setting bits SYNC and SPEN, and clearing bit
CSRC.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
To enable reception, set enable bit CREN.
Flag bit RCIF will be set when reception is complete, and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
 1997 Microchip Technology Inc.
PIC16C6X
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
0Ch
PIR1
PSPIF(1)
(2)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
18h
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
19h
TXREG
USART Transmit Register
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
(2)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
99h
SPBRG
0000 0000
0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
Note 1: PSPIF and PSPIE are reserved on the PIC16C63/R63/66, always maintain these bits clear.
2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.
TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR,
BOR
Value on
all other
Resets
0Ch
PIR1
PSPIF(1)
(2)
RCIF
TXIF
SSPIF
CCP1IF
TMR2IF
TMR1IF
0000 0000
0000 0000
18h
RCSTA
SPEN
RX9
SREN
CREN
—
FERR
OERR
RX9D
0000 -00x
0000 -00x
1Ah
RCREG
USART Receive Register
0000 0000
0000 0000
8Ch
PIE1
PSPIE(1)
(2)
RCIE
TXIE
SSPIE
CCP1IE
TMR2IE
TMR1IE
0000 0000
0000 0000
98h
TXSTA
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
0000 -010
0000 -010
99h
SPBRG
0000 0000
0000 0000
Baud Rate Generator Register
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Synchronous Slave Reception.
Note 1: PSPIF and PSPIE are reserved on the PIC16C63/R63/66, always maintain these bits clear.
2: PIR1<6> and PIE1<6> are reserved, always maintain these bits clear.
 1997 Microchip Technology Inc.
DS30234D-page 121
PIC16C6X
NOTES:
DS30234D-page 122
 1997 Microchip Technology Inc.
PIC16C6X
13.0
SPECIAL FEATURES OF THE
CPU
timers that offer necessary delays on power-up. One is
the Oscillator Start-up Timer (OST), intended to keep
the chip in RESET until the crystal oscillator is stable.
The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up
only, designed to keep the part in reset while the power
supply stabilizes. With these two timers on-chip, most
applications need no external reset circuitry.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC16CXX family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external components, provide power saving operating modes and offer
code protection. These are:
SLEEP mode is designed to offer a very low current
power-down mode. The user can wake from SLEEP
through external reset, Watchdog Timer Wake-up or
through an interrupt. Several oscillator options are also
made available to allow the part to fit the application.
The RC oscillator option saves system cost while the
LP crystal option saves power. A set of configuration
bits are used to select various options.
• Oscillator selection
• Reset
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP mode
• Code protection
• ID locations
• In-circuit serial programming
13.1
Configuration Bits
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in program memory location 2007h.
The user will note that address 2007h is beyond the
user program memory space. In fact, it belongs to the
special test/configuration memory space (2000h 3FFFh), which can be accessed only during programming.
The PIC16CXX has a Watchdog Timer which can be
shut off only through configuration bits. It runs off its
own RC oscillator for added reliability. There are two
FIGURE 13-1: CONFIGURATION WORD FOR PIC16C61
—
—
—
—
—
—
—
—
—
CP0 PWRTE WDTE FOSC1 FOSC0
bit13
bit0
Register:
Address
CONFIG
2007h
bit 13-5: Unimplemented: Read as '1'
bit 4:
CP0: Code protection bit
1 = Code protection off
0 = All memory is code protected, but 00h - 3Fh is writable
bit 3:
PWRTE: Power-up Timer Enable bit
1 = Power-up Timer enabled
0 = Power-up Timer disabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
 1997 Microchip Technology Inc.
DS30234D-page 123
PIC16C6X
FIGURE 13-2: CONFIGURATION WORD FOR PIC16C62/64/65
—
—
—
—
—
—
—
—
CP1
CP0
bit13
PWRTE WDTE FOSC1 FOSC0
bit0
Register:
Address
CONFIG
2007h
bit 13-6: Unimplemented: Read as '1'
bit 5-4:
CP1:CP0: Code Protection bits
11 = Code protection off
10 = Upper half of program memory code protected
01 = Upper 3/4th of program memory code protected
00 = All memory is code protected
bit 3:
PWRTE: Power-up Timer Enable bit
1 = Power-up Timer enabled
0 = Power-up Timer disabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
FIGURE 13-3: CONFIGURATION WORD FOR PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67
CP1
CP0
CP1
CP0
CP1
CP0
—
BODEN
CP1
bit13
CP0
PWRTE WDTE FOSC1 FOSC0
bit0
Register:
Address
CONFIG
2007h
bit 13-8: CP1:CP0: Code Protection bits(2)
bit 5:4
11 = Code protection off
10 = Upper half of program memory code protected
01 = Upper 3/4th of program memory code protected
00 = All memory is code protected
bit 7:
Unimplemented: Read as '1'
bit 6:
BODEN: Brown-out Reset Enable bit (1)
1 = Brown-out Reset enabled
0 = Brown-out Reset disabled
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = Power-up Timer disabled
0 = Power-up Timer enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to implement the code protection scheme listed.
DS30234D-page 124
 1997 Microchip Technology Inc.
PIC16C6X
13.2
Oscillator Configurations
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
13.2.1
OSCILLATOR TYPES
The PIC16CXX can be operated in four different oscillator modes. The user can program two configuration
bits (FOSC1 and FOSC0) to select one of these four
modes:
•
•
•
•
LP
XT
HS
RC
13.2.2
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
CRYSTAL OSCILLATOR/CERAMIC
RESONATORS
In LP, XT, or HS modes a crystal or ceramic resonator
is connected to the OSC1/CLKIN and OSC2/CLKOUT
pins to establish oscillation (Figure 13-4). The
PIC16CXX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a
frequency out of the crystal manufacturers specifications. When in LP, XT, or HS modes, the device can
have an external clock source to drive the OSC1/CLKIN
pin (Figure 13-5).
FIGURE 13-4: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP OSC
CONFIGURATION)
OSC1
(2)
C1
XTAL
OSC2
C2
(2)
To internal
logic
See Table 13-1, Table 13-3, Table 13-2 and Table 13-4 for
recommended values of C1 and C2.
Note 1: A series resistor may be required for AT strip
cut crystals.
2: For the PIC16C61 the buffer is on the OSC2
pin, all other devices have the buffer on the
OSC1 pin.
FIGURE 13-5: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
OSC1
Clock from
ext. system
PIC16CXX
Open
 1997 Microchip Technology Inc.
SLEEP
PIC16CXX
RF
RS
Note1
To internal
logic
OSC2
DS30234D-page 125
PIC16C6X
TABLE 13-1:
CERAMIC RESONATORS
PIC16C61
TABLE 13-3:
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
FOR PIC16C61
Ranges Tested:
Mode
XT
Freq
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
HS
OSC1
OSC2
Mode
Freq
OSC1
OSC2
47 - 100 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
10 - 47 pF
47 - 100 pF
15 - 68 pF
15 - 68 pF
15 - 68 pF
10 - 47 pF
LP
32 kHz
200 kHz
100 kHz
500 kHz
1 MHz
2 MHz
4 MHz
8 MHz
20 MHz
33 - 68 pF
15 - 47 pF
33 - 68 pF
15 - 47 pF
47 - 100 pF
20 - 68 pF
15 - 68 pF
15 - 47 pF
15 - 33 pF
15 - 47 pF
15 - 47 pF
47 - 100 pF
20 - 68 pF
15 - 68 pF
15 - 47 pF
15 - 33 pF
15 - 47 pF
15 - 47 pF
XT
These values are for design guidance only. See
notes at bottom of page.
HS
Resonators Used:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA16.00MX
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
These values are for design guidance only. See
notes at bottom of page.
TABLE 13-4:
All resonators used did not have built-in capacitors.
TABLE 13-2:
CERAMIC RESONATORS
PIC16C62/62A/R62/63/R63/64/
64A/R64/65/65A/R65/66/67
Osc Type
Crystal
Freq
Cap. Range
C1
Cap.
Range
C2
LP
32 kHz
33 pF
33 pF
Ranges Tested:
Mode
XT
Freq
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
HS
OSC1
68 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
OSC2
68 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
These values are for design guidance only. See
notes at bottom of page.
XT
HS
Resonators Used:
455 kHz
2.0 MHz
4.0 MHz
8.0 MHz
16.0 MHz
Panasonic EFO-A455K04B
Murata Erie CSA2.00MG
Murata Erie CSA4.00MG
Murata Erie CSA8.00MT
Murata Erie CSA16.00MX
± 0.3%
± 0.5%
± 0.5%
± 0.5%
± 0.5%
All resonators used did not have built-in capacitors.
CAPACITOR SELECTION
FOR CRYSTAL OSCILLATOR
FOR PIC16C62/62A/R62/63/
R63/64/64A/R64/65/65A/R65/
66/67
200 kHz
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
20 MHz
15-33 pF
15-33 pF
These values are for design guidance only. See
notes at bottom of page.
Crystals Used
32 kHz
Epson C-001R32.768K-A
± 20 PPM
STD XTL 200.000KHz
± 20 PPM
1 MHz
ECS ECS-10-13-1
± 50 PPM
4 MHz
ECS ECS-40-20-1
± 50 PPM
8 MHz
EPSON CA-301 8.000M-C
± 30 PPM
20 MHz
EPSON CA-301 20.000M-C ± 30 PPM
200 kHz
Note 1: Recommended values of C1 and C2 are identical to the ranges tested Table 13-1 and Table 13-2.
2: Higher capacitance increases the stability of oscillator but also increases the start-up time.
3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level specification.
DS30234D-page 126
 1997 Microchip Technology Inc.
PIC16C6X
13.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and
better stability. A well-designed crystal oscillator will
provide good performance with TTL gates. Two types
of crystal oscillator circuits can be used; one with series
resonance, or one with parallel resonance.
Figure 13-6 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides
the negative feedback for stability. The 10 kΩ potentiometer biases the 74AS04 in the linear region. This
could be used for external oscillator designs.
FIGURE 13-6: EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
PIC16CXX
CLKIN
74AS04
RC OSCILLATOR
For timing insensitive applications the RC device option
offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor
(Rext) and capacitor (Cext) values, and the operating
temperature. In addition to this, the oscillator frequency
will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame
capacitance between package types will also affect the
oscillation frequency, especially for low Cext values.
The user also needs to take into account variation due
to tolerance of external R and C components used.
Figure 13-8 shows how the RC combination is connected to the PIC16CXX. For Rext values below
2.2 kΩ, the oscillator operation may become unstable
or stop completely. For very high Rext values (e.g.
1 MΩ), the oscillator becomes sensitive to noise,
humidity and leakage. Thus, we recommend keeping
Rext between 3 kΩ and 100 kΩ.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or package lead frame capacitance.
See characterization data for desired device for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since
leakage current variation will affect RC frequency more
for large R) and for smaller C (since variation of input
capacitance will affect RC frequency more).
10k
XTAL
10k
20 pF
13.2.4
20 pF
Figure 13-7 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 kΩ resistors provide the negative feedback to bias the inverters in their linear region.
See characterization data for desired device for variation of oscillator frequency due to VDD for given Rext/
Cext values as well as frequency variation due to operating temperature for given R, C, and VDD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-5 for
waveform).
FIGURE 13-8: RC OSCILLATOR MODE
FIGURE 13-7: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
V DD
Rext
330 kΩ
330 kΩ
74AS04
74AS04
74AS04
PIC16CXX
CLKIN
0.1 µF
Internal
clock
OSC1
To Other
Devices
Cext
PIC16CXX
VSS
Fosc/4
OSC2/CLKOUT
XTAL
 1997 Microchip Technology Inc.
DS30234D-page 127
PIC16C6X
13.3
Reset
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The PIC16CXX differentiates between various kinds of
reset:
•
•
•
•
•
Power-on Reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT Reset (normal operation)
Brown-out Reset (BOR) - Not on PIC16C61/62/
64/65
The TO and PD bits are set or cleared differently in different reset situations as indicated in Table 13-7,
Table 13-8, and Table 13-9. These bits are used in software to determine the nature of the reset. See
Table 13-12 for a full description of reset states of all
registers.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 13-9.
On the PIC16C62A/R62/63/R63/64A/R64/65A/R65/
66/67, the MCLR reset path has a noise filter to detect
and ignore small pulses. See parameter #34 for pulse
width specifications.
Some registers are not affected in any reset condition,
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on MCLR or WDT
Reset, on MCLR reset during SLEEP, and on Brownout Reset (BOR). They are not affected by a WDT
Wake-up, which is viewed as the resumption of normal
operation.
It should be noted that a WDT Reset does not drive the
MCLR pin low.
FIGURE 13-9: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR/VPP pin
SLEEP
WDT
Module
WDT
Time-out
VDD rise
detect
Power-on Reset
VDD pin
(2)
Brown-out
Reset
S
BODEN
OST/PWRT
OST
Chip Reset
10-bit Ripple counter
OSC1/
CLKIN
pin
R
Q
(1) PWRT
On-chip
RC OSC
10-bit Ripple counter
Enable PWRT
(3)
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: Brown-out Reset is NOT implemented on the PIC16C61/62/64/65.
3: See Table 13-5 and Table 13-6 for time-out situations.
DS30234D-page 128
 1997 Microchip Technology Inc.
PIC16C6X
13.4
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOR)
The power-up time delay will vary from chip to chip due
to VDD, temperature, and process variation. See DC
parameters for details.
13.4.3
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
13.4.1
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures the crystal oscillator
or resonator has started and stabilized.
POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.5V - 2.1V). To
take advantage of the POR, just tie the MCLR/VPP pin
directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create
a Power-on Reset. A maximum rise time for VDD is
required. See Electrical Specifications for details.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
13.4.4
BROWN-OUT RESET (BOR)
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met. Brown-out Reset may be used to meet the startup
conditions.
A configuration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below 4.0V (parameter D005 in
Electrical Specification section) for greater than parameter #34 (see Electrical Specification section), the
brown-out situation will reset the chip. A reset may not
occur if VDD falls below 4.0V for less than parameter
#34. The chip will remain in Brown-out Reset until VDD
rises above BVDD. The Power-up Timer will now be
invoked and will keep the chip in RESET an additional
72 ms. If VDD drops below BVDD while the Power-up
Timer is running, the chip will go back into a Brown-out
Reset and the Power-up Timer will be initialized. Once
VDD rises above BVDD, the Power-up Timer will execute a 72 ms time delay. The Power-up Timer should
always be enabled when Brown-out Reset is enabled.
Figure 13-10 shows typical brown-out situations.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting.”
13.4.2
OSCILLATOR START-UP TIMER (OST)
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms nominal
time-out on power-up only, from POR. The Power-up
Timer operates on an internal RC oscillator. The chip is
kept in reset as long as PWRT is active. The PWRT’s
time delay allows VDD to rise to an acceptable level. A
configuration bit is provided to enable/disable the
PWRT.
FIGURE 13-10: BROWN-OUT SITUATIONS
VDD
Internal
Reset
BVDD Max.
BVDD Min.
72 ms
VDD
Internal
Reset
BVDD Max.
BVDD Min.
<72 ms
72 ms
VDD
Internal
Reset
 1997 Microchip Technology Inc.
BVDD Max.
BVDD Min.
72 ms
DS30234D-page 129
PIC16C6X
13.4.5
13.4.6
TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
a PWRT time-out is invoked after the POR time delay
has expired. Then OST is activated. The total time-out
will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode, with the
PWRT disabled, there will be no time-out at all.
Figure 13-11, Figure 13-12, and Figure 13-13 depict
time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if the
MCLR/VPP pin is kept low long enough, the time-outs
will expire. Then bringing the MCLR/VPP pin high will
begin execution immediately (Figure 13-14). This is
useful for testing purposes or to synchronize more than
one PIC16CXX device operating in parallel.
Table 13-10 and Table 13-11 show the reset conditions
for some special function registers, while Table 13-12
shows the reset conditions for all the registers.
TABLE 13-5:
XT, HS, LP
RC
Bit1 is POR (Power-on Reset Status bit). It is cleared
on a Power-on Reset and unaffected otherwise. The
user must set this bit following a Power-on Reset.
Wake-up from SLEEP
1024 TOSC
—
Power-up
PWRTE = 0
PWRTE = 1
72 ms + 1024TOSC
1024TOSC
72 ms
—
Brown-out
Wake up from
SLEEP
72 ms + 1024TOSC
72 ms
1024 TOSC
—
STATUS BITS AND THEIR SIGNIFICANCE, PIC16C61
TO
PD
1
0
0
1
1
1
0
0
POR
Bit0 is BOR (Brown-out Reset Status bit). BOR is
unknown on Power-on Reset. It must then be set by the
user and checked on subsequent resets to see if BOR
cleared, indicating that a brown-out has occurred. The
BOR status bit is a “Don’t Care” and is not necessarily
predictable if the Brown-out Reset circuitry is disabled
(by clearing bit BODEN in the Configuration Word).
TIME-OUT IN VARIOUS SITUATIONS,
PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67
Oscillator Configuration
TABLE 13-8:
The Power Control/Status Register, PCON has up to
two bits, depending upon the device. Bit0 is not implemented on the PIC16C62/64/65.
Power-up
PWRTE = 1
PWRTE = 0
72 ms + 1024TOSC
1024TOSC
72 ms
—
XT, HS, LP
RC
TABLE 13-7:
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
TIME-OUT IN VARIOUS SITUATIONS, PIC16C61/62/64/65
Oscillator Configuration
TABLE 13-6:
POWER CONTROL/STATUS REGISTER
(PCON)
Power-on Reset or MCLR reset during normal operation
WDT Reset
WDT Wake-up
MCLR reset during SLEEP or interrupt wake-up from SLEEP
STATUS BITS AND THEIR SIGNIFICANCE, PIC16C62/64/65
TO
PD
0
1
1
0
0
x
0
x
0
1
0
1
1
0
0
1
u
u
1
1
0
Legend: x = unknown, u = unchanged
DS30234D-page 130
Power-on Reset
Illegal, TO is set on a Power-on Reset
Illegal, PD is set on a Power-on Reset
WDT Reset
WDT Wake-up
MCLR reset during normal operation
MCLR reset during SLEEP or interrupt wake-up from SLEEP
 1997 Microchip Technology Inc.
PIC16C6X
TABLE 13-9:
POR
STATUS BITS AND THEIR SIGNIFICANCE FOR
PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67
BOR
TO
0
x
1
0
x
0
0
x
x
1
0
x
1
1
0
1
1
0
1
1
u
1
1
1
Legend: x = unknown, u = unchanged
PD
1
x
0
x
1
0
u
0
Power-on Reset
Illegal, TO is set on a Power-on Reset
Illegal, PD is set on a Power-on Reset
Brown-out Reset
WDT Reset
WDT Wake-up
MCLR reset during normal operation
MCLR reset during SLEEP or interrupt wake-up from SLEEP
TABLE 13-10: RESET CONDITION FOR SPECIAL REGISTERS ON PIC16C61/62/64/65
Program Counter
STATUS
PCON(2)
Power-on Reset
000h
0001 1xxx
---- --0-
MCLR reset during normal operation
000h
000u uuuu
---- --u-
MCLR reset during SLEEP
000h
0001 0uuu
---- --u-
WDT Reset
000h
0000 1uuu
---- --u-
WDT Wake-up
Interrupt wake-up from SLEEP
PC + 1
uuu0 0uuu
---- --u-
PC + 1(1)
uuu1 0uuu
---- --u-
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and the global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1.
2: The PCON register is not implemented on the PIC16C61.
TABLE 13-11: RESET CONDITION FOR SPECIAL REGISTERS ON
PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/67
Program Counter
STATUS
PCON
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR reset during normal operation
000h
000u uuuu
---- --uu
MCLR reset during SLEEP
000h
0001 0uuu
---- --uu
WDT Reset
000h
0000 1uuu
---- --uu
Brown-out Reset
000h
0001 1uuu
---- --u0
PC + 1
uuu0 0uuu
---- --uu
uuu1 0uuu
---- --uu
WDT Wake-up
Interrupt wake-up from SLEEP
(1)
PC + 1
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.
Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt
vector (0004h) after execution of PC+1.
 1997 Microchip Technology Inc.
DS30234D-page 131
PIC16C6X
TABLE 13-12: INITIALIZATION CONDITIONS FOR ALL REGISTERS
Register
Applicable Devices
Power-on Reset MCLR Reset during:
Brown-out
– normal operation
Reset
– SLEEP
Wake-up via
interrupt or
WDT Wake-up
WDT Reset
W
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
INDF
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
N/A
N/A
N/A
TMR0
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000h
0000h
STATUS
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0001 1xxx
000q quuu(3)
uuuq quuu(3)
FSR
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
PC + 1(2)
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
---x xxxx
---u uuuu
---u uuuu
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
--xx xxxx
--uu uuuu
--uu uuuu
PORTB
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTD
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTE
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
---- -xxx
---- -uuu
---- -uuu
PCLATH
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
---0 0000
---0 0000
---u uuuu
INTCON
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 000x
0000 000u
uuuu uuuu(1)
PIR1
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
00-- 0000
00-- 0000
uu-- uuuu(1)
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu(1)
PIR2
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
---- ---0
---- ---0
---- ---u(2)
PORTA
TMR1L
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
--00 0000
--uu uuuu
--uu uuuu
TMR2
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
T2CON
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
-000 0000
-000 0000
-uuu uuuu
SSPBUF
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPCON
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
CCPR1L
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
--00 0000
--00 0000
--uu uuuu
RCSTA
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 -00x
0000 -00x
uuuu -uuu
TXREG
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
RCREG
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
CCPR2L
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2H
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
OPTION
TRISA
TRISB
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
1111 1111
1111 1111
uuuu uuuu
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
---1 1111
---1 1111
---u uuuu
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
--11 1111
--11 1111
--uu uuuu
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
1111 1111
1111 1111
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0', q = value depends on condition.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h)
after execution of PC + 1.
3: See Table 13-10 and Table 13-11 for reset value for specific conditions.
DS30234D-page 132
 1997 Microchip Technology Inc.
PIC16C6X
TABLE 13-12: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
Register
Applicable Devices
Power-on Reset MCLR Reset during:
Brown-out
– normal operation
Reset
– SLEEP
Wake-up via
interrupt or
WDT Wake-up
WDT Reset
TRISC
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
1111 1111
1111 1111
uuuu uuuu
TRISD
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
1111 1111
1111 1111
uuuu uuuu
TRISE
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 -111
0000 -111
uuuu -uuu
PIE1
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
00-- 0000
00-- 0000
uu-- uuuu
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
PIE2
PCON
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
---- ---0
---- ---0
---- ---u
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
---- --0u
---- --uu
---- --uu
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
---- --0-
---- --u-
---- --u-
PR2
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
1111 1111
1111 1111
1111 1111
SSPADD
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
--00 0000
--00 0000
--uu uuuu
TXSTA
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 -010
0000 -010
uuuu -uuu
SPBRG
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
0000 0000
0000 0000
uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0', q = value depends on condition.
Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h)
after execution of PC + 1.
3: See Table 13-10 and Table 13-11 for reset value for specific conditions.
 1997 Microchip Technology Inc.
DS30234D-page 133
PIC16C6X
FIGURE 13-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 13-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 13-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
DS30234D-page 134
 1997 Microchip Technology Inc.
PIC16C6X
FIGURE 13-14: EXTERNAL POWER-ON
RESET CIRCUIT (FOR SLOW
VDD POWER-UP)
FIGURE 13-15: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 1
VDD
VDD
D
VDD
33k
R
10k
MCLR
R1
MCLR
C
40k
PIC16CXX
PIC16CXX
Note 1: External Power-on Reset circuit is required
only if VDD power-up slope is too slow. The
diode D helps discharge the capacitor
quickly when VDD powers down.
2: R < 40 kΩ is recommended to make sure
that voltage drop across R does not violate
the devices electrical specifications.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge
(ESD) or Electrostatic Overstress (EOS).
Note 1: This circuit will activate reset when VDD
goes below (Vz + 0.7V) where Vz = Zener
voltage.
2: Internal brown-out detection on the
PIC16C62A/R62/63/R63/64A/R64/65A/
R65/66/67 should be disabled when using
this circuit.
3: Resistors should be adjusted for the
characteristics of the transistors.
FIGURE 13-16: EXTERNAL BROWN-OUT
PROTECTION CIRCUIT 2
VDD
VDD
R1
Q1
MCLR
R2
40k
PIC16CXX
Note 1: This brown-out circuit is less expensive,
albeit less accurate. Transistor Q1 turns
off when VDD is below a certain level such
that:
R1
= 0.7V
VDD •
R1 + R2
2: Internal brown-out detection on the
PIC16C62A/R62/63/R63/64A/R64/65A/
R65/66/67 should be disabled when using
this circuit.
3: Resistors should be adjusted for the
characteristics of the transistors.
 1997 Microchip Technology Inc.
DS30234D-page 135
PIC16C6X
13.5
Interrupts
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The PIC16C6X family has up to 11 sources of interrupt.
The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
Note:
Individual interrupt flag bits are set regardless of the status of their corresponding
mask bit or global enable bit, GIE.
Global interrupt enable bit, GIE (INTCON<7>) enables
(if set) all un-masked interrupts or disables (if cleared)
all interrupts. When bit GIE is enabled, and an interrupt
flag bit and mask bit are set, the interrupt will vector
immediately. Individual interrupts can be disabled
through their corresponding enable bits in the INTCON
register. GIE is cleared on reset.
avoid infinite interrupt requests. Individual interrupt flag
bits are set regardless of the status of their corresponding mask bit or the GIE bit.
Note:
For the PIC16C61/62/64/65, if an interrupt
occurs while the Global Interrupt Enable
bit, GIE is being cleared, bit GIE may unintentionally be re-enabled by the user’s
Interrupt Service Routine (the RETFIE
instruction). The events that would cause
this to occur are:
1.
An instruction clears the GIE bit while
an interrupt is acknowledged
2.
The program branches to the Interrupt
vector and executes the Interrupt Service Routine.
3.
The Interrupt Service Routine completes with the execution of the RETFIE instruction. This causes the GIE
bit to be set (enables interrupts), and
the program returns to the instruction
after the one which was meant to disable interrupts.
4.
Perform the following to ensure that
interrupts are globally disabled.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enable interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flag bits are contained
in the INTCON register.
The peripheral interrupt flag bits are contained in special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special
function registers PIE1 and PIE2 and the peripheral
interrupt enable bit is contained in special function register INTCON.
When an interrupt is responded to, bit GIE is cleared to
disable any further interrupts, the return address is
pushed onto the stack and the PC is loaded with
0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
LOOP BCF INTCON,GIE
BTFSC INTCON,GIE
GOTO
:
LOOP
;Disable Global
;Interrupt bit
;Global Interrupt
;Disabled?
;NO, try again
;Yes, continue
;with program flow
For external interrupt events, such as the RB0/INT pin
or RB port change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs
(Figure 1319). The latency is the same for one or two cycle
instructions. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
DS30234D-page 136
 1997 Microchip Technology Inc.
PIC16C6X
FIGURE 13-17: INTERRUPT LOGIC FOR PIC16C61
Wake-up
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt to CPU
RBIF
RBIE
GIE
FIGURE 13-18: INTERRUPT LOGIC FOR PIC16C6X
PSPIF
PSPIE
RCIF
RCIE
Wake-up (If in SLEEP mode)
T0IF
T0IE
INTF
INTE
TXIF
TXIE
Interrupt to CPU
RBIF
RBIE
SSPIF
SSPIE
PEIE
CCP1IF
CCP1IE
GIE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
CCP2IF
CCP2IE
The following table shows which devices have which interrupts.
Device
T0IF INTF RBIF PSPIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF
PIC16C62
Yes
Yes
Yes
-
-
-
Yes
Yes
Yes
Yes
-
PIC16C62A
Yes
Yes
Yes
-
-
-
Yes
Yes
Yes
Yes
-
PIC16CR62
Yes
Yes
Yes
-
-
-
Yes
Yes
Yes
Yes
-
PIC16C63
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC16CR63
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC16C64
Yes
Yes
Yes
Yes
-
-
Yes
Yes
Yes
Yes
-
PIC16C64A
Yes
Yes
Yes
Yes
-
-
Yes
Yes
Yes
Yes
-
PIC16C64
Yes
Yes
Yes
Yes
-
-
Yes
Yes
Yes
Yes
-
PIC16C65
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC16C65A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC16CR65
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC16C66
Yes
Yes
Yes
-
Yes
Yes
Yes
Yes
Yes
Yes
Yes
PIC16C67
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
 1997 Microchip Technology Inc.
DS30234D-page 137
PIC16C6X
13.5.1
INT INTERRUPT
13.5.2
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit T0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit T0IE
(INTCON<5>) (Section 7.0).
External interrupt on RB0/INT pin is edge triggered:
either rising if edge select bit INTEDG (OPTION<6>) is
set, or falling, if bit INTEDG is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). The INTF bit
must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt
can wake the processor from SLEEP, if enable bit INTE
was set prior to going into SLEEP. The status of global
enable bit GIE decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 13.8 for details on SLEEP mode.
13.5.3
PORTB INTERRUPT ON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>)
(Section 5.2).
Note:
For the PIC16C61/62/64/65, if a change on
the I/O pin should occur when the read
operation is being executed (start of the Q2
cycle), then flag bit RBIF may not get set.
FIGURE 13-19: INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
4
INT pin
1
1
INTF flag
(INTCON<1>)
Interrupt Latency (2)
5
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC+1
Inst (PC+1)
Inst (PC)
PC+1
—
Dummy Cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3TCY for synchronous interrupt and 3-4TCY for asynchronous interrupt.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC oscillator mode.
4: For minimum width spec of INT pulse, refer to AC specs.
5: INTF can to be set anytime during the Q4-Q1 cycles.
DS30234D-page 138
 1997 Microchip Technology Inc.
PIC16C6X
13.6
Context Saving During Interrupts
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt i.e., W register and STATUS
register. This will have to be implemented in software.
Example 13-1 stores and restores the STATUS and W
registers. Example 13-2 stores and restores the
STATUS, W, and PCLATH registers (Devices with
paged program memory). For all PIC16C6X devices
with greater than 1K of program memory (all devices
except PIC16C61), the register, W_TEMP, must be
defined in all banks and must be defined at the same
offset from the bank base address (i.e., if W_TEMP is
defined at 0x20 in bank 0, it must also be defined at
0xA0 in bank 1, 0x120 in bank 2, and 0x1A0 in bank 3).
The examples:
a)
b)
c)
d)
e)
f)
g)
Stores the W register
Stores the STATUS register in bank 0
Stores PCLATH
Executes ISR code
Restores PCLATH
Restores STATUS register (and bank select bit)
Restores W register
EXAMPLE 13-1: SAVING STATUS AND W REGISTERS IN RAM (PIC16C61)
MOVWF
SWAPF
MOVWF
:
:(ISR)
:
SWAPF
W_TEMP
STATUS,W
STATUS_TEMP
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;Save status to bank zero STATUS_TEMP register
STATUS_TEMP,W
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
EXAMPLE 13-2: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
(ALL OTHER PIC16C6X DEVICES)
MOVWF
SWAPF
CLRF
MOVWF
MOVF
MOVWF
CLRF
BCF
MOVF
MOVWF
:(ISR)
:
MOVF
MOVWF
SWAPF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
PCLATH, W
PCLATH_TEMP
PCLATH
STATUS, IRP
FSR, W
FSR_TEMP
;Copy W to TEMP register, could be bank one or zero
;Swap status to be saved into W
;bank 0, regardless of current bank, Clears IRP,RP1,RP0
;Save status to bank zero STATUS_TEMP register
;Only required if using pages 1, 2 and/or 3
;Save PCLATH into W
;Page zero, regardless of current page
;Return to Bank 0
;Copy FSR to W
;Copy FSR from W to FSR_TEMP
PCLATH_TEMP, W
PCLATH
STATUS_TEMP,W
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Restore PCLATH
;Move W into PCLATH
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
 1997 Microchip Technology Inc.
DS30234D-page 139
PIC16C6X
13.7
Watchdog Timer (WDT)
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET condition.
The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKIN pin. That means that the WDT will
run, even if the clock on the OSC1/CLKIN and OSC2/
CLKOUT pins of the device has been stopped, for
example, by execution of a SLEEP instruction. During
normal operation, a WDT time-out generates a device
reset. If the device is in SLEEP mode, a WDT time-out
causes the device to wake-up and continue with normal
operation (WDT Wake-up). The WDT can be permanently disabled by clearing configuration bit WDTE
(Section 13.1).
13.7.1
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
13.7.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
Note:
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
FIGURE 13-20: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(see Figure 7-6)
0
Watchdog
Timer
Postscaler
M
U
X
1
8
PS2:PS0
8- to -1 MUX
PSA
WDT
Enable bit
To TMR0 (Figure 7-6)
0
1
MUX
PSA
WDT
Time-out
Note: Bits T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
FIGURE 13-21: SUMMARY OF WATCHDOG TIMER REGISTERS
Address
Name
2007h
Config. bits
81h,181h
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(1)
BODEN(1)
CP1
CP0
PWRTE(1)
WDTE
FOSC1
FOSC0
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Figure 13-1, Figure 13-2, and Figure 13-3 for details of these bits for the specific device.
DS30234D-page 140
 1997 Microchip Technology Inc.
PIC16C6X
13.8
Power-down Mode (SLEEP)
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, status bit PD (STATUS<3>) is cleared,
status bit TO (STATUS<4>) is set, and the oscillator
driver is turned off. The I/O ports maintain the status
they had before the SLEEP instruction was executed
(driving high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD, or VSS, ensure no external circuitry is drawing current from the I/O pin, and disable
external clocks. Pull all I/O pins, that are hi-impedance
inputs, high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should
also be at VDD or VSS for lowest current consumption.
The contribution from on-chip pull-ups on PORTB
should be considered.
The MCLR/VPP pin must be at a logic high level
(VIHMC).
13.8.1
WAKE-UP FROM SLEEP
The device can wake from SLEEP through one of the
following events:
1.
2.
3.
External reset input on MCLR/VPP pin.
Watchdog Timer Wake-up (if WDT was
enabled).
Interrupt from RB0/INT pin, RB port change, or
some peripheral interrupts.
External MCLR Reset will cause a device reset. All
other events are considered a continuation of program
execution and cause a “wake-up”. The TO and PD bits
in the STATUS register can be used to determine the
cause of device reset. The PD bit, which is set on
power-up is cleared when SLEEP is invoked. The TO bit
is cleared if WDT time-out occurred (and caused wakeup).
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have a NOP after the SLEEP instruction.
13.8.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bits will not be cleared.
• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction
will be completely executed before the wake-up.
Therefore, the WDT and WDT postscaler will be
cleared, the TO bit will be set and the PD bit will
be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
The following peripheral interrupts can wake the device
from SLEEP:
1.
2.
3.
4.
5.
6.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
SSP (Start/Stop) bit detect interrupt.
SSP transmit or receive in slave mode (SPI/I2C).
CCP capture mode interrupt.
Parallel Slave Port read or write.
USART TX or RX (synchronous slave mode).
 1997 Microchip Technology Inc.
DS30234D-page 141
PIC16C6X
FIGURE 13-22: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3
Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst(PC) = SLEEP
Instruction
executed
Inst(PC - 1)
PC+1
PC+2
PC+2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
Note 1: XT, HS or LP oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.
3: GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine.
If GIE = '0', execution will continue in-line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
13.9
Program Verification/Code Protection
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
Note:
13.10
Microchip does not recommend code protecting windowed devices.
ID Locations
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Four memory locations (2000h - 2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least significant bits of the ID
location are used.
For ROM devices, these values are submitted along
with the ROM code.
13.11
In-Circuit Serial Programming
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
The PIC16CXX microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom firmware to be programmed.
DS30234D-page 142
The device is placed into a program/verify mode by
holding pins RB6 and RB7 low while raising the MCLR
(VPP) pin from VIL to VIHH (see programming specification). RB6 becomes the programming clock and RB7
becomes the programming data. Both RB6 and RB7
are Schmitt Trigger inputs in this mode.
After reset, to place the device in program/verify mode,
the program counter (PC) is at location 00h. A 6-bit
command is then supplied to the device. Depending on
the command, 14-bits of program data are then supplied to or from the device, depending if the command
was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X Programming Specifications (Literature #DS30228).
FIGURE 13-23: TYPICAL IN-CIRCUIT SERIAL
PROGRAMMING
CONNECTION
External
Connector
Signals
To Normal
Connections
PIC16CXX
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB6
Data I/O
RB7
VDD
To Normal
Connections
 1997 Microchip Technology Inc.
PIC16C6X
14.0
INSTRUCTION SET SUMMARY
Each PIC16CXX instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16CXX instruction
set summary in Table 14-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 14-1
shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 14-1:
OPCODE FIELD
DESCRIPTIONS
Field
Description
Register file address (0x00 to 0x7F)
Working register (accumulator)
Bit address within an 8-bit file register
Literal field, constant data or label
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all
Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
label Label name
TOS Top of Stack
PC Program Counter
f
W
b
k
x
The instruction set is highly orthogonal and is grouped
into three basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction.
In this case, the execution takes two instruction cycles
with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for
an oscillator frequency of 4 MHz, the normal instruction
execution time is 1 µs. If a conditional test is true or the
program counter is changed as a result of an instruction, the instruction execution time is 2 µs.
Table 14-2 lists the instructions recognized by the
MPASM assembler.
Figure 14-1 shows the general formats that the instructions can have.
Note:
All examples use the following format to represent a
hexadecimal number:
0xhh
where h signifies a hexadecimal digit.
FIGURE 14-1: GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
[ ]
( )
→
<>
∈
Global Interrupt Enable bit
Watchdog Timer/Counter
Time-out bit
Power-down bit
Destination either the W register or the specified
register file location
Options
Contents
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
PCLATH Program Counter High Latch
GIE
WDT
TO
PD
dest
To maintain upward compatibility with
future PIC16CXX products, do not use the
OPTION and TRIS instructions.
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
Assigned to
Register bit field
In the set of
italics User defined term (font is courier)
CALL and GOTO instructions only
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
 1997 Microchip Technology Inc.
DS30234D-page 143
PIC16C6X
TABLE 14-2:
PIC16CXX INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
1
1
1 (2)
1 (2)
01
01
01
01
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into standby mode
Subtract W from literal
Exclusive OR literal with W
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS30234D-page 144
 1997 Microchip Technology Inc.
PIC16C6X
14.1
Instruction Descriptions
ADDLW
Add Literal and W
ANDLW
AND Literal with W
Syntax:
[label] ADDLW
Syntax:
[label] ANDLW
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
Operation:
(W) + k → (W)
Operation:
(W) .AND. (k) → (W)
C, DC, Z
Status Affected:
Z
Status Affected:
Encoding:
11
k
111x
kkkk
kkkk
Encoding:
11
k
1001
kkkk
kkkk
Description:
The contents of the W register are
added to the eight bit literal 'k' and the
result is placed in the W register.
Description:
The contents of W register are
AND’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
1
Words:
1
1
Cycles:
1
Cycles:
Q Cycle Activity:
Example:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
W
ADDLW
0x15
Q Cycle Activity:
Example
=
=
ADDWF
Add W and f
Syntax:
[label] ADDWF
Operands:
Q3
Q4
Decode
Read
literal "k"
Process
data
Write to
W
ANDLW
0x5F
W
0x10
=
0xA3
After Instruction
After Instruction
W
Q2
Before Instruction
Before Instruction
W
Q1
W
0x25
=
0x03
ANDWF
AND W with f
Syntax:
[label] ANDWF
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) + (f) → (destination)
Operation:
(W) .AND. (f) → (destination)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
00
f,d
0111
dfff
ffff
Encoding:
00
f,d
0101
dfff
ffff
Description:
Add the contents of the W register with
register 'f'. If 'd' is 0 the result is stored
in the W register. If 'd' is 1 the result is
stored back in register 'f'.
Description:
AND the W register with register 'f'. If 'd'
is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in
register 'f'.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
ADDWF
FSR, 0
Before Instruction
W =
FSR =
 1997 Microchip Technology Inc.
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
ANDWF
FSR, 1
Before Instruction
0x17
0xC2
After Instruction
W =
FSR =
Q Cycle Activity:
W =
FSR =
0x17
0xC2
After Instruction
0xD9
0xC2
W =
FSR =
0x17
0x02
DS30234D-page 145
PIC16C6X
BCF
Bit Clear f
BTFSC
Bit Test, Skip if Clear
Syntax:
[label] BCF
Syntax:
[label] BTFSC f,b
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
0 → (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Encoding:
01
f,b
00bb
bfff
ffff
Description:
Bit 'b' in register 'f' is cleared.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
BCF
Encoding:
10bb
bfff
ffff
Description:
Words:
1
Cycles:
1(2)
Q Cycle Activity:
FLAG_REG, 7
01
If bit 'b' in register 'f' is '1' then the next
instruction is executed.
If bit 'b', in register 'f', is '0' then the next
instruction is discarded, and a NOP is
executed instead, making this a 2TCY
instruction.
Before Instruction
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
NoOperation
Q3
Q4
FLAG_REG = 0xC7
If Skip:
After Instruction
FLAG_REG = 0x47
Example
(2nd Cycle)
Q1
Q2
NoOperation
NoOperation
HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
NoNoOperation Operation
FLAG,1
PROCESS_CODE
Before Instruction
PC =
address HERE
After Instruction
BSF
Bit Set f
Syntax:
[label] BSF
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
1 → (f<b>)
Status Affected:
None
Encoding:
01
if FLAG<1> = 0,
PC =
address TRUE
if FLAG<1>=1,
PC =
address FALSE
f,b
01bb
bfff
Description:
Bit 'b' in register 'f' is set.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
ffff
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
BSF
FLAG_REG,
7
Before Instruction
FLAG_REG = 0x0A
After Instruction
FLAG_REG = 0x8A
DS30234D-page 146
 1997 Microchip Technology Inc.
PIC16C6X
BTFSS
Bit Test f, Skip if Set
CALL
Call Subroutine
Syntax:
[label] BTFSS f,b
Syntax:
[ label ] CALL k
Operands:
0 ≤ f ≤ 127
0≤b<7
Operands:
0 ≤ k ≤ 2047
Operation:
Operation:
skip if (f<b>) = 1
Status Affected:
None
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Status Affected:
None
Encoding:
Description:
01
1
Cycles:
1(2)
If Skip:
Example
bfff
ffff
If bit 'b' in register 'f' is '0' then the next
instruction is executed.
If bit 'b' is '1', then the next instruction is
discarded and a NOP is executed
instead, making this a 2TCY instruction.
Words:
Q Cycle Activity:
11bb
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
NoOperation
(2nd Cycle)
Q1
Q2
NoOperation
NoOperation
HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
Q3
10
FLAG,1
PROCESS_CODE
kkkk
kkkk
Call Subroutine. First, return address
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH. CALL
is a two cycle instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k',
Push PC
to Stack
Process
data
Write to
PC
Q4
NoNoOperation Operation
0kkk
Description:
1st Cycle
2nd Cycle
Example
NoNoNoNoOperation Operation Operation Operation
HERE
CALL
THERE
Before Instruction
PC = Address HERE
After Instruction
Before Instruction
PC =
Encoding:
address HERE
PC = Address THERE
TOS = Address HERE+1
After Instruction
if FLAG<1> = 0,
PC =
address FALSE
if FLAG<1> = 1,
PC =
address TRUE
 1997 Microchip Technology Inc.
DS30234D-page 147
PIC16C6X
CLRF
Clear f
Syntax:
[label] CLRF
Operands:
0 ≤ f ≤ 127
Operation:
00h → (f)
1→Z
Status Affected:
Z
Encoding:
00
f
0001
1fff
ffff
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h → (W)
1→Z
Status Affected:
Z
Encoding:
00
0001
0xxx
xxxx
Description:
The contents of register 'f' are cleared
and the Z bit is set.
Description:
W register is cleared. Zero bit (Z) is
set.
Words:
1
Words:
1
Cycles:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
CLRF
Q Cycle Activity:
Example
FLAG_REG
=
0x5A
Q3
Q4
NoOperation
Process
data
Write to
W
CLRW
=
=
0x00
1
W
=
0x5A
After Instruction
After Instruction
FLAG_REG
Z
Q2
Before Instruction
Before Instruction
FLAG_REG
Q1
Decode
W
Z
=
=
0x00
1
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected:
TO, PD
Encoding:
00
0000
0110
0100
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD are
set.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
NoOperation
Process
data
Clear
WDT
Counter
CLRWDT
Before Instruction
WDT counter =
?
After Instruction
WDT counter =
WDT prescaler=
TO
=
PD
=
DS30234D-page 148
0x00
0
1
1
 1997 Microchip Technology Inc.
PIC16C6X
COMF
Complement f
DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] COMF
Syntax:
[ label ] DECFSZ f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (destination)
Operation:
Status Affected:
Z
(f) - 1 → (destination);
skip if result = 0
Status Affected:
None
Encoding:
Description:
00
f,d
1001
dfff
ffff
The contents of register 'f' are complemented. If 'd' is 0 the result is stored in
W. If 'd' is 1 the result is stored back in
register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
Encoding:
COMF
0x13
1
Cycles:
1(2)
=
=
0x13
0xEC
If Skip:
After Instruction
REG1
W
DECF
Decrement f
Syntax:
[label] DECF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination)
Status Affected:
Z
Encoding:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
Write to
destination
Q3
Q4
NoNoNoOperation Operation Operation
Example
0011
dfff
ffff
Decrement register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Words:
1
Cycles:
1
Example
HERE
DECFSZ
GOTO
CONTINUE •
•
•
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
DECF
NoOperation
CNT, 1
LOOP
Before Instruction
Description:
Q Cycle Activity:
(2nd Cycle)
Q1
Q2
PC
00
ffff
Words:
Before Instruction
=
dfff
The contents of register 'f' are decremented. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
If the result is 1, the next instruction, is
executed. If the result is 0, then a NOP is
executed instead making it a 2TCY instruction.
REG1,0
REG1
1011
Description:
Q Cycle Activity:
Example
00
=
address HERE
After Instruction
CNT
if CNT
PC
if CNT
PC
=
=
=
≠
=
CNT - 1
0,
address CONTINUE
0,
address HERE+1
CNT, 1
Before Instruction
CNT
Z
=
=
0x01
0
=
=
0x00
1
After Instruction
CNT
Z
 1997 Microchip Technology Inc.
DS30234D-page 149
PIC16C6X
GOTO
Unconditional Branch
INCF
Increment f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 2047
Operands:
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) + 1 → (destination)
None
Status Affected:
Z
Status Affected:
Encoding:
10
GOTO k
1kkk
kkkk
kkkk
Encoding:
00
INCF f,d
1010
dfff
ffff
Description:
GOTO is an unconditional branch. The
eleven bit immediate value is loaded
into PC bits <10:0>. The upper bits of
PC are loaded from PCLATH<4:3>.
GOTO is a two cycle instruction.
Description:
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
Words:
1
Words:
1
Cycles:
2
Cycles:
1
Q Cycle Activity:
1st Cycle
2nd Cycle
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
PC
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
INCF
CNT, 1
NoNoNoNoOperation Operation Operation Operation
Example
Example
Before Instruction
GOTO THERE
After Instruction
PC =
Address THERE
CNT
Z
0xFF
0
=
=
0x00
1
After Instruction
CNT
Z
DS30234D-page 150
=
=
 1997 Microchip Technology Inc.
PIC16C6X
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected:
None
Encoding:
Description:
00
1
Cycles:
1(2)
If Skip:
1111
dfff
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
Write to
destination
Q3
Q4
NoNoNoOperation Operation Operation
Example
ffff
Q1
(2nd Cycle)
Q1
Q2
HERE
INCFSZ
GOTO
CONTINUE •
•
•
Inclusive OR Literal with W
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operation:
(W) .OR. k → (W)
Status Affected:
Z
Encoding:
The contents of register 'f' are incremented. If 'd' is 0 the result is placed in
the W register. If 'd' is 1 the result is
placed back in register 'f'.
If the result is 1, the next instruction is
executed. If the result is 0, a NOP is
executed instead making it a 2TCY
instruction.
Words:
Q Cycle Activity:
INCFSZ f,d
IORLW
11
IORLW k
1000
kkkk
kkkk
Description:
The contents of the W register is
OR’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
W
IORLW
0x35
Before Instruction
W
=
0x9A
After Instruction
W
Z
=
=
0xBF
1
NoOperation
CNT, 1
LOOP
Before Instruction
PC
=
address HERE
After Instruction
CNT =
if CNT=
PC
=
if CNT≠
PC
=
 1997 Microchip Technology Inc.
CNT + 1
0,
address CONTINUE
0,
address HERE +1
DS30234D-page 151
PIC16C6X
IORWF
Inclusive OR W with f
MOVLW
Move Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ k ≤ 255
Operation:
(W) .OR. (f) → (destination)
Operation:
k → (W)
Status Affected:
Z
Status Affected:
None
Encoding:
IORWF
00
f,d
0100
dfff
ffff
Description:
Inclusive OR the W register with register 'f'. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
Encoding:
11
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
IORWF
00xx
kkkk
kkkk
Description:
The eight bit literal 'k' is loaded into W
register. The don’t cares will assemble
as 0’s.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
MOVLW k
Example
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
W
MOVLW
0x5A
After Instruction
RESULT, 0
W
=
0x5A
Before Instruction
RESULT =
W
=
0x13
0x91
After Instruction
RESULT =
W
=
Z
=
0x13
0x93
1
MOVF
Move f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (destination)
Status Affected:
Z
Encoding:
Encoding:
Description:
00
MOVF f,d
1000
dfff
ffff
The contents of register f is moved to a
destination dependant upon the status
of d. If d = 0, destination is W register. If
d = 1, the destination is file register f
itself. d = 1 is useful to test a file register since status flag Z is affected.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
MOVF
FSR, 0
After Instruction
MOVWF
Move W to f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
Operation:
(W) → (f)
Status Affected:
None
00
MOVWF
0000
f
1fff
ffff
Description:
Move data from W register to register
'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write
register 'f'
MOVWF
OPTION_REG
Before Instruction
OPTION =
W
=
0xFF
0x4F
After Instruction
OPTION =
W
=
0x4F
0x4F
W = value in FSR register
Z =1
DS30234D-page 152
 1997 Microchip Technology Inc.
PIC16C6X
NOP
No Operation
RETFIE
Return from Interrupt
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
No operation
Operation:
Status Affected:
None
TOS → PC,
1 → GIE
Status Affected:
None
Encoding:
00
NOP
0000
0xx0
0000
RETFIE
Description:
No operation.
Encoding:
Words:
1
Description:
Cycles:
1
Return from Interrupt. Stack is POPed
and Top of Stack (TOS) is loaded in the
PC. Interrupts are enabled by setting
Global Interrupt Enable bit, GIE
(INTCON<7>). This is a two cycle
instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
Example
Q2
Q3
Q4
NoNoNoOperation Operation Operation
NOP
Q Cycle Activity:
1st Cycle
2nd Cycle
Example
00
0000
0000
1001
Q1
Q2
Q3
Q4
Decode
NoOperation
Set the
GIE bit
Pop from
the Stack
NoNoNoNoOperation Operation Operation Operation
RETFIE
After Interrupt
PC =
GIE =
OPTION
Load Option Register
Syntax:
[ label ]
Operands:
None
Operation:
(W) → OPTION
TOS
1
OPTION
Status Affected: None
Encoding:
00
0000
0110
0010
Description:
The contents of the W register are
loaded in the OPTION register. This
instruction is supported for code compatibility with PIC16C5X products.
Since OPTION is a readable/writable
register, the user can directly address
it.
Words:
1
Cycles:
1
Example
To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
 1997 Microchip Technology Inc.
DS30234D-page 153
PIC16C6X
RETLW
Return with Literal in W
RETURN
Return from Subroutine
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
None
Operation:
k → (W);
TOS → PC
Operation:
TOS → PC
Status Affected:
None
Status Affected:
None
Encoding:
RETLW k
Encoding:
11
Description:
01xx
kkkk
kkkk
The W register is loaded with the eight
bit literal 'k'. The program counter is
loaded from the top of the stack (the
return address). This is a two cycle
instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
1st Cycle
2nd Cycle
Q2
Decode
Read
literal 'k'
Q3
Q4
NoWrite to W,
Operation Pop from
the Stack
NoNoNoNoOperation Operation Operation Operation
0000
0000
1000
Description:
Return from subroutine. The stack is
POPed and the top of the stack (TOS)
is loaded into the program counter. This
is a two cycle instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
00
RETURN
1st Cycle
2nd Cycle
Example
Q1
Decode
Q2
Q3
Q4
NoNoPop from
Operation Operation the Stack
NoNoNoNoOperation Operation Operation Operation
RETURN
After Interrupt
Example
CALL TABLE
•
•
•
TABLE ADDWF PC
RETLW k1
RETLW k2
;W contains table
;offset value
;W now has table value
PC =
TOS
;W = offset
;Begin table
;
•
•
•
RETLW kn
; End of table
Before Instruction
W
=
0x07
After Instruction
W
DS30234D-page 154
=
value of k8
 1997 Microchip Technology Inc.
PIC16C6X
RLF
Rotate Left f through Carry
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
Operation:
See description below
Status Affected:
C
Status Affected:
C
Encoding:
Description:
RLF
00
f,d
1101
dfff
ffff
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is stored
back in register 'f'.
C
Encoding:
Description:
00
Register f
C
1
Words:
1
Cycles:
1
Cycles:
1
Example
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
RLF
REG1,0
 1997 Microchip Technology Inc.
dfff
ffff
Register f
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
RRF
REG1,0
Before Instruction
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
After Instruction
REG1
W
C
Q Cycle Activity:
Example
Before Instruction
REG1
C
1100
The contents of register 'f' are rotated
one bit to the right through the Carry
Flag. If 'd' is 0 the result is placed in the
W register. If 'd' is 1 the result is placed
back in register 'f'.
Words:
Q Cycle Activity:
RRF f,d
REG1
C
=
=
1110 0110
0
=
=
=
1110 0110
0111 0011
0
After Instruction
REG1
W
C
DS30234D-page 155
PIC16C6X
SLEEP
SUBLW
Subtract W from Literal
Syntax:
[ label ]
SUBLW k
Syntax:
[ label ]
Operands:
None
Operands:
0 ≤ k ≤ 255
Operation:
00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Operation:
k - (W) → (W)
Status Affected:
C, DC, Z
SLEEP
Encoding:
11
110x
kkkk
kkkk
Description:
The W register is subtracted (2’s complement method) from the eight bit literal 'k'.
The result is placed in the W register.
The power-down status bit, PD is
cleared. Time-out status bit, TO is
set. Watchdog Timer and its prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped. See
Section 13.8 for more details.
Words:
1
Cycles:
1
Words:
1
Example 1:
Cycles:
1
Status Affected:
TO, PD
Encoding:
Description:
Q Cycle Activity:
00
0000
0110
0011
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to W
SUBLW
0x02
Before Instruction
Q1
Decode
Q2
Q3
NoNoOperation Operation
Q4
W
C
Z
Go to
Sleep
=
=
=
1
?
?
After Instruction
Example:
SLEEP
W
C
Z
Example 2:
=
=
=
1
1; result is positive
0
Before Instruction
W
C
Z
=
=
=
2
?
?
After Instruction
W
C
Z
Example 3:
=
=
=
0
1; result is zero
1
Before Instruction
W
C
Z
=
=
=
3
?
?
After Instruction
W
C
Z
DS30234D-page 156
=
=
=
0xFF
0; result is negative
0
 1997 Microchip Technology Inc.
PIC16C6X
SUBWF
Subtract W from f
SWAPF
Swap Nibbles in f
Syntax:
[ label ]
Syntax:
[ label ] SWAPF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - (W) → (destination)
Operation:
Status Affected:
C, DC, Z
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected:
None
Encoding:
Description:
00
1
Cycles:
1
Example 1:
0010
dfff
ffff
Subtract (2’s complement method) W register from register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Words:
Q Cycle Activity:
SUBWF f,d
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
Write to
destination
SUBWF
Encoding:
00
REG1
W
C
Z
ffff
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
data
Write to
destination
Example
=
=
=
=
SWAPF REG,
REG1
W
C
Z
=
=
=
=
REG1
=
=
=
=
=
=
=
=
2
2
?
?
=
=
=
=
 1997 Microchip Technology Inc.
=
=
=
=
0xA5
0x5A
Load TRIS Register
Syntax:
[label]
Operands:
5≤f≤7
Operation:
(W) → TRIS register f;
TRIS
f
Status Affected: None
0
2
1; result is zero
1
1
2
?
?
After Instruction
REG1
W
C
Z
=
=
TRIS
Encoding:
0xFF
2
0; result is negative
0
00
0000
0110
0fff
Description:
The instruction is supported for code
compatibility with the PIC16C5X products. Since TRIS registers are readable and writable, the user can directly
address them.
Words:
1
Cycles:
1
Before Instruction
REG1
W
C
Z
0xA5
1
2
1; result is positive
0
After Instruction
REG1
W
C
Z
=
After Instruction
REG1
W
Before Instruction
REG1
W
C
Z
0
Before Instruction
3
2
?
?
After Instruction
Example 3:
dfff
The upper and lower nibbles of register
'f' are exchanged. If 'd' is 0 the result is
placed in W register. If 'd' is 1 the result
is placed in register 'f'.
REG1,1
Before Instruction
Example 2:
1110
Description:
Example
To maintain upward compatibility
with future PIC16CXX products, do
not use this instruction.
DS30234D-page 157
PIC16C6X
XORLW
Exclusive OR Literal with W
XORWF
Exclusive OR W with f
Syntax:
[label]
Syntax:
[label]
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
(W) .XOR. k → (W)
0 ≤ f ≤ 127
d ∈ [0,1]
Status Affected:
Z
Operation:
(W) .XOR. (f) → (destination)
Status Affected:
Z
Encoding:
11
XORLW k
1010
kkkk
kkkk
Description:
The contents of the W register are
XOR’ed with the eight bit literal 'k'.
The result is placed in the W register.
Words:
1
Cycles:
1
Q Cycle Activity:
Example:
Q1
Q2
Q3
Q4
Decode
Read
literal 'k'
Process
data
Write to
W
XORLW
Encoding:
00
XORWF
0110
f,d
dfff
ffff
Description:
Exclusive OR the contents of the W
register with register 'f'. If 'd' is 0 the
result is stored in the W register. If 'd' is
1 the result is stored back in register 'f'.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register
'f'
Process
data
Write to
destination
0xAF
Before Instruction
W
=
Example
0xB5
After Instruction
W
=
0x1A
XORWF
REG
1
Before Instruction
REG
W
=
=
0xAF
0xB5
=
=
0x1A
0xB5
After Instruction
REG
W
DS30234D-page 158
 1997 Microchip Technology Inc.
PIC16C6X
15.0
DEVELOPMENT SUPPORT
15.1
Development Tools
The PIC16/17 microcontrollers are supported with a full
range of hardware and software development tools:
• PICMASTER/PICMASTER CE Real-Time
In-Circuit Emulator
• ICEPIC Low-Cost PIC16C5X and PIC16CXXX
In-Circuit Emulator
• PRO MATE II Universal Programmer
• PICSTART Plus Entry-Level Prototype
Programmer
• PICDEM-1 Low-Cost Demonstration Board
• PICDEM-2 Low-Cost Demonstration Board
• PICDEM-3 Low-Cost Demonstration Board
• MPASM Assembler
• MPLAB-SIM Software Simulator
• MPLAB-C (C Compiler)
• Fuzzy logic development system (fuzzyTECH−MP)
15.2
PICMASTER: High Performance
Universal In-Circuit Emulator with
MPLAB IDE
15.3
ICEPIC: Low-cost PIC16CXXX
In-Circuit Emulator
ICEPIC is a low-cost in-circuit emulator solution for the
Microchip PIC16C5X and PIC16CXXX families of 8-bit
OTP microcontrollers.
ICEPIC is designed to operate on PC-compatible
machines ranging from 286-AT through Pentium
based machines under Windows 3.x environment.
ICEPIC features real time, non-intrusive emulation.
15.4
PRO MATE II: Universal Programmer
The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone
mode as well as PC-hosted mode.
The PRO MATE II has programmable VDD and VPP
supplies which allows it to verify programmed memory
at VDD min and VDD max for maximum reliability. It has
an LCD display for displaying error messages, keys to
enter commands and a modular detachable socket
assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC16C5X, PIC16CXXX, PIC17CXX and
PIC14000 devices. It can also set configuration and
code-protect bits in this mode.
The PICMASTER Universal In-Circuit Emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for all
microcontrollers in the PIC12C5XX, PIC14C000,
PIC16C5X, PIC16CXXX and PIC17CXX families.
PICMASTER is supplied with the MPLAB Integrated
Development Environment (IDE), which allows editing,
“make” and download, and source debugging from a
single environment.
15.5
Interchangeable target probes allow the system to be
easily reconfigured for emulation of different processors. The universal architecture of the PICMASTER
allows expansion to support all new Microchip microcontrollers.
PICSTART Plus supports all PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX and PIC17CXX devices with
up to 40 pins. Larger pin count devices such as the
PIC16C923 and PIC16C924 may be supported with an
adapter socket.
PICSTART Plus Entry Level
Development System
The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via
one of the COM (RS-232) ports. MPLAB Integrated
Development Environment software makes using the
programmer simple and efficient. PICSTART Plus is
not recommended for production programming.
The PICMASTER Emulator System has been
designed as a real-time emulation system with
advanced features that are generally found on more
expensive development tools. The PC compatible 386
(and higher) machine platform and Microsoft Windows
3.x environment were chosen to best make these features available to you, the end user.
A CE compliant version of PICMASTER is available for
European Union (EU) countries.
 1997 Microchip Technology Inc.
DS30234D-page 159
PIC16C6X
15.6
PICDEM-1 Low-Cost PIC16/17
Demonstration Board
The PICDEM-1 is a simple board which demonstrates
the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X
(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,
PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and
PIC17C44. All necessary hardware and software is
included to run basic demo programs. The users can
program the sample microcontrollers provided with
the PICDEM-1 board, on a PRO MATE II or
PICSTART-16B programmer, and easily test firmware. The user can also connect the PICDEM-1
board to the PICMASTER emulator and download
the firmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller
socket(s). Some of the features include an RS-232
interface, a potentiometer for simulated analog input,
push-button switches and eight LEDs connected to
PORTB.
15.7
PICDEM-2 Low-Cost PIC16CXX
Demonstration Board
The PICDEM-2 is a simple demonstration board that
supports the PIC16C62, PIC16C64, PIC16C65,
PIC16C73 and PIC16C74 microcontrollers. All the
necessary hardware and software is included to
run the basic demonstration programs. The user
can program the sample microcontrollers provided
with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-16C, and easily test firmware.
The PICMASTER emulator may also be used with the
PICDEM-2 board to test firmware. Additional prototype
area has been provided to the user for adding additional hardware and connecting it to the microcontroller
socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate
usage of the I2C bus and separate headers for connection to an LCD module and a keypad.
15.8
PICDEM-3 Low-Cost PIC16CXXX
Demonstration Board
The PICDEM-3 is a simple demonstration board that
supports the PIC16C923 and PIC16C924 in the PLCC
package. It will also support future 44-pin PLCC
microcontrollers with a LCD Module. All the necessary hardware and software is included to run the
basic demonstration programs. The user can program the sample microcontrollers provided with
the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and
easily test firmware. The PICMASTER emulator may
also be used with the PICDEM-3 board to test firmware.
Additional prototype area has been provided to the
user for adding hardware and connecting it to the
microcontroller socket(s). Some of the features include
DS30234D-page 160
an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and
separate headers for connection to an external LCD
module and a keypad. Also provided on the PICDEM-3
board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature
and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for
showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.
15.9
MPLAB Integrated Development
Environment Software
The MPLAB IDE Software brings an ease of software
development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application
which contains:
• A full featured editor
• Three operating modes
- editor
- emulator
- simulator
• A project manager
• Customizable tool bar and key mapping
• A status bar with project information
• Extensive on-line help
MPLAB allows you to:
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PIC16/17 tools (automatically updates all
project information)
• Debug using:
- source files
- absolute listing file
• Transfer data dynamically via DDE (soon to be
replaced by OLE)
• Run up to four emulators on the same PC
The ability to use MPLAB with Microchip’s simulator
allows a consistent platform and the ability to easily
switch from the low cost simulator to the full featured
emulator with minimal retraining due to development
tools.
15.10
Assembler (MPASM)
The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000,
PIC16C5X, PIC16CXXX, and PIC17CXX families.
MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats.
It generates various object code formats to support
Microchip's development tools as well as third party
programmers.
MPASM allows full symbolic debugging from
PICMASTER, Microchip’s Universal Emulator
System.
 1997 Microchip Technology Inc.
PIC16C6X
MPASM has the following features to assist in developing software for specific use applications.
• Provides translation of Assembler source code to
object code for all Microchip microcontrollers.
• Macro assembly capability.
• Produces all the files (Object, Listing, Symbol,
and special) required for symbolic debug with
Microchip’s emulator systems.
• Supports Hex (default), Decimal and Octal source
and listing formats.
MPASM provides a rich directive language to support
programming of the PIC16/17. Directives are helpful in
making the development of your assemble source code
shorter and more maintainable.
15.11
Software Simulator (MPLAB-SIM)
The MPLAB-SIM Software Simulator allows code
development in a PC host environment. It allows the
user to simulate the PIC16/17 series microcontrollers
on an instruction level. On any given instruction, the
user may examine or modify any of the data areas or
provide external stimulus to any of the pins. The input/
output radix can be set by the user and the execution
can be performed in; single step, execute until break, or
in a trace mode.
MPLAB-SIM fully supports symbolic debugging using
MPLAB-C and MPASM. The Software Simulator offers
the low cost flexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.
15.12
C Compiler (MPLAB-C)
The MPLAB-C Code Development System is a
complete ‘C’ compiler and integrated development
environment for Microchip’s PIC16/17 family of microcontrollers. The compiler provides powerful integration
capabilities and ease of use not found with other
compilers.
For easier source level debugging, the compiler provides symbol information that is compatible with the
MPLAB IDE memory display (PICMASTER emulator
software versions 1.13 and later).
15.13
15.14
MP-DriveWay – Application Code
Generator
MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can
visually configure all the peripherals in a PIC16/17
device and, with a click of the mouse, generate all the
initialization and many functional code modules in C
language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is
highly modular and allows easy integration of your own
code. MP-DriveWay is intelligent enough to maintain
your code through subsequent code generation.
15.15
SEEVAL Evaluation and
Programming System
The SEEVAL SEEPROM Designer’s Kit supports all
Microchip 2-wire and 3-wire Serial EEPROMs. The kit
includes everything necessary to read, write, erase or
program special features of any Microchip SEEPROM
product including Smart Serials and secure serials.
The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can
significantly reduce time-to-market and result in an
optimized system.
15.16
TrueGauge Intelligent Battery
Management
The TrueGauge development tool supports system
development with the MTA11200B TrueGauge Intelligent Battery Management IC. System design verification can be accomplished before hardware prototypes
are built. User interface is graphically-oriented and
measured data can be saved in a file for exporting to
Microsoft Excel.
15.17
KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing
codes, a decoder to decode transmissions, and a programming interface to program test transmitters.
Fuzzy Logic Development System
(fuzzyTECH-MP)
fuzzyTECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version,
MP Explorer, for designers to gain a comprehensive
working knowledge of fuzzy logic system design; and a
full-featured version, fuzzyTECH-MP, edition for implementing more complex systems.
Both versions include Microchip’s fuzzyLAB demonstration board for hands-on experience with fuzzy logic
systems implementation.
 1997 Microchip Technology Inc.
DS30234D-page 161
Emulator Products
Software Tools
DS30234D-page 162
Programmers
✔
KEELOQ
Evaluation Kit

PICDEM-3
PICDEM-2
PICDEM-1
SEEVAL
Designers Kit

KEELOQ
Programmer
PRO MATE II
Universal
Programmer

PICSTART
Plus Low-Cost
Universal Dev. Kit

PICSTART
Lite Ultra Low-Cost
Dev. Kit
Total Endurance
Software Model
✔
✔
✔
fuzzyTECH-MP
Explorer/Edition
Fuzzy Logic
Dev. Tool
MP-DriveWay
Applications
Code Generator
✔
MPLAB C
Compiler
✔
✔
MPLAB
Integrated
Development
Environment
ICEPIC Low-Cost
In-Circuit Emulator
PICMASTER/
PICMASTER-CE
In-Circuit Emulator
✔
✔
✔
✔
✔
✔
PIC14000
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
PIC16C5X
✔
✔
✔
✔
✔
✔
✔
✔
✔
PIC16CXXX
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X
✔
✔
✔
✔
Available
3Q97
PIC17C75X
✔
✔
✔
24CXX
25CXX
93CXX
✔
✔
✔
HCS200
HCS300
HCS301
TABLE 15-1:
Demo Boards
PIC12C5XX
PIC16C6X
DEVELOPMENT TOOLS FROM MICROCHIP
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
16.0
ELECTRICAL CHARACTERISTICS FOR PIC16C61
Absolute Maximum Ratings †
Ambient temperature under bias............................................................................................................. .-55˚C to +125˚C
Storage temperature ............................................................................................................................... -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) .............................................................................................. 0V to +14V
Voltage on RA4 pin with respect to Vss ........................................................................................................... 0V to +14V
Total power dissipation (Note 1)............................................................................................................................800 mW
Maximum current out of VSS pin ............................................................................................................................150 mA
Maximum current into VDD pin ...............................................................................................................................100 mA
Input clamp current, IIK (VI < 0 or VI > VDD) .....................................................................................................................± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................± 20 mA
Maximum output current sunk by any I/O pin...........................................................................................................25 mA
Maximum output current sourced by any I/O pin .....................................................................................................20 mA
Maximum current sunk by PORTA ...........................................................................................................................80 mA
Maximum current sourced by PORTA......................................................................................................................50 mA
Maximum current sunk by PORTB.........................................................................................................................150 mA
Maximum current sourced by PORTB ...................................................................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 16-1:
OSC
RC
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C61-04
PIC16C61-20
PIC16LC61-04
JW Devices
VDD:
IDD:
IPD:
Freq:
VDD:
IDD:
IPD:
Freq:
VDD:
IDD:
IPD:
Freq:
VDD:
IDD:
4.0V to 6.0V
VDD: 4.5V to 5.5V
VDD: 3.0V to 6.0V
VDD: 4.0V to 6.0V
3.3 mA max. at 5.5V
IDD: 1.8 mA typ. at 5.5V IDD: 1.4 mA typ. at 3.0V
IDD: 3.3 mA max. at 5.5V
14 µA max. at 4V
IPD: 1.0 µA typ. at 4V
IPD: 0.6 µA typ. at 3V
IPD: 14 µA max. at 4V
4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
XT
4.0V to 6.0V
VDD: 4.5V to 5.5V
VDD: 3.0V to 6.0V
VDD: 4.0V to 6.0V
3.3 mA max. at 5.5V
IDD: 1.8 mA typ. at 5.5V IDD: 1.4 mA typ. at 3.0V
IDD: 3.3 mA max. at 5.5V
14 µA max. at 4V
IPD: 1.0 µA typ. at 4V
IPD: 0.6 µA typ. at 3V
IPD: 14 µA max. at 4V
4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
Freq: 4 MHz max.
HS
4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
13.5 mA typ. at 5.5V
IDD: 30 mA max. at 5.5V Not recommended for use in IDD: 30 mA max. at 5.5V
HS mode
1.0 µA typ. at 4.5V
IPD: 1.0 µA typ. at 4.5V
IPD: 1.0 µA typ. at 4.5V
4 MHz max.
Freq: 20 MHz max.
Freq: 20 MHz max.
LP
4.0V to 6.0V
VDD: 3.0V to 6.0V
VDD: 3.0V to 6.0V
15 µA typ. at 32 kHz,
IDD: 32 µA max. at 32 kHz, IDD: 32 µA max. at 32 kHz,
Not recommended for
4.0V
3.0V
3.0V
use in LP mode
IPD: 0.6 µA typ. at 4.0V
IPD: 9 µA max. at 3.0V
IPD: 9 µA max. at 3.0V
Freq: 200 kHz max.
Freq: 200 kHz max.
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications.
It is recommended that the user select the device type that ensures the specifications required.
 1997 Microchip Technology Inc.
DS30234D-page 163
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
16.1
DC Characteristics:
PIC16C61-04 (Commercial, Industrial, Extended)
PIC16C61-20 (Commercial, Industrial, Extended)
DC CHARACTERISTICS
Param
No.
D001
D001A
D002*
D003
D004*
D010
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym
Min Typ† Max Units
Conditions
Supply Voltage
VDD
RAM Data Retention
Voltage (Note 1)
VDD start voltage to
ensure internal Poweron Reset signal
VDD rise rate to ensure
internal Power-on
Reset signal
Supply Current (Note 2)
D013
1.5
6.0
5.5
-
V
V
V
XT, RC and LP osc configuration
HS osc configuration
VDR
4.0
4.5
-
VPOR
-
VSS
-
V
See section on Power-on Reset for details
SVDD
0.05
-
-
-
1.8
3.3
mA
FOSC = 4 MHz, VDD = 5.5V (Note 4)
-
13.5
30
mA
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
VDD = 4.0V, WDT enabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -0°C to +70°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -40°C to +125°C
IDD
V/ms See section on Power-on Reset for details
µA
28
Power-down Current
IPD
7
D020
µA
14
(Note 3)
1.0
D021
µA
16
1.0
D021A
µA
20
1.0
D021B
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
DS30234D-page 164
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
16.2
DC Characteristics:
DC CHARACTERISTICS
Param
No.
D001
D002*
D003
D004*
D010
Characteristic
PIC16LC61-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym Min Typ† Max Units
Conditions
Supply Voltage
VDD
RAM Data Retention Volt- VDR
age (Note 1)
VPOR
VDD start voltage to
ensure internal Power-on
Reset signal
SVDD
VDD rise rate to ensure
internal Power-on Reset
signal
Supply Current (Note 2)
IDD
D010A
D020
D021
D021A
*
†
Note 1:
2:
3:
4:
3.0
-
1.5
6.0
-
V
V
XT, RC, and LP osc configuration
-
VSS
-
V
See section on Power-on Reset for details
0.05
-
-
-
1.4
2.5
mA
FOSC = 4 MHz, VDD = 3.0V (Note 4)
-
15
32
µA
FOSC = 32 kHz, VDD = 3.0V, WDT disabled,
LP osc configuration
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
V/ms See section on Power-on Reset for details
5
20
µA
0.6
9
µA
0.6
12
µA
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
This is the limit to which VDD can be lowered without losing RAM data.
The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
Power-down Current
(Note 3)
 1997 Microchip Technology Inc.
IPD
DS30234D-page 165
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
16.3
DC Characteristics:
PIC16C61-04 (Commercial, Industrial, Extended)
PIC16C61-20 (Commercial, Industrial, Extended)
PIC16LC61-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
D030
D030A
D031
with Schmitt Trigger buffer
D032 MCLR, OSC1 (in RC mode)
D033 OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
D040
with TTL buffer
D040A
D041
D042
D042A
D043
D070
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 16.1 and
Section 16.2.
Sym
Min Typ† Max Units
Conditions
VIL
Vss
VSS
Vss
Vss
Vss
VIH
2.0
0.25VDD
+ 0.8V
D060
with Schmitt Trigger buffer
MCLR
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
PORTB weak pull-up current
IPURB
Input Leakage Current (Notes 2, 3)
I/O ports
IIL
D061
D063
MCLR, RA4/T0CKI
OSC1
D080
Output Low Voltage
I/O ports
D080A
D083
OSC2/CLKOUT (RC osc config)
D083A
VOL
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
-
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
VDD
VDD
VDD
VDD
† 400
V
V
V
V
µA
For entire VDD range
0.85VDD 0.85VDD 0.7VDD
0.9VDD
50
250
-
-
±1
µA
-
-
±5
±5
µA
µA
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
Note1
Note1
VDD = 5V, VPIN = VSS
Vss ≤ VPIN ≤ VDD, Pin at hiimpedance
Vss ≤ VPIN ≤ VDD
Vss ≤ VPIN ≤ VDD, XT, HS and
LP osc configuration
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
*
†
The parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30234D-page 166
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
DC CHARACTERISTICS
Param
No.
D090
Characteristic
Output High Voltage
I/O ports (Note 3)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 16.1 and
Section 16.2.
Sym
Min Typ† Max Units
Conditions
VOH
D090A
D092
OSC2/CLKOUT (RC osc config)
D092A
D150*
D100
Open-Drain High Voltage
Capacitive Loading Specs on
Output Pins
OSC2 pin
VOD
COSC2
VDD-0.7
-
-
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
-
-
14
V
15
pF
IOH = -3.0 mA,
VDD = 4.5V, -40°C to +85°C
IOH = -2.5 mA,
VDD = 4.5V, -40°C to +125°C
IOH = -1.3 mA,
VDD = 4.5V, -40°C to +85°C
IOH = -1.0 mA,
VDD = 4.5V, -40°C to +125°C
RA4 pin
In XT, HS and LP modes when
external clock is used to drive
OSC1.
D101
*
†
All I/O pins and OSC2 (in RC mode) CIO
50
pF
The parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
 1997 Microchip Technology Inc.
DS30234D-page 167
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
16.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
FIGURE 16-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF
15 pF
DS30234D-page 168
for all pins except OSC2/CLKOUT
for OSC2 output
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
16.5
Timing Diagrams and Specifications
FIGURE 16-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
3
1
3
4
4
2
CLKOUT
TABLE 16-2:
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Fosc
External CLKIN Frequency
(Note 1)
DC
—
4
MHz
XT and RC osc mode
DC
—
4
MHz
HS osc mode (-04)
DC
—
20
MHz
HS osc mode (-20)
DC
—
200
kHz
LP osc mode
Oscillator Frequency
(Note 1)
1
Tosc
External CLKIN Period
(Note 1)
Oscillator Period
(Note 1)
DC
—
4
MHz
RC osc mode
0.1
—
4
MHz
XT osc mode
1
—
4
MHz
HS osc mode (-04)
1
—
20
MHz
HS osc mode (-20)
250
—
—
ns
XT and RC osc mode
250
—
—
ns
HS osc mode (-04)
50
—
—
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
250
—
—
ns
RC osc mode
250
—
10,000
ns
XT osc mode
250
—
1,000
ns
HS osc mode (-04)
50
—
1,000
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
Instruction Cycle Time (Note 1)
1.0
TCY
DC
µs
TCY = 4/Fosc
TosL,
TosH
External Clock in (OSC1) High or
Low Time
50
—
—
ns
XT oscillator
2.5
—
—
µs
LP oscillator
10
—
—
ns
HS oscillator
TosR,
TosF
External Clock in (OSC1) Rise or
Fall Time
25
—
—
ns
XT oscillator
50
—
—
ns
LP oscillator
2
TCY
3
4
Units Conditions
15
—
—
ns
HS oscillator
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
 1997 Microchip Technology Inc.
DS30234D-page 169
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 16-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 16-1 for load conditions.
TABLE 16-3:
Parameter
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
10*
TosH2ckL
11*
TosH2ckH
12*
TckR
CLKOUT rise time
—
5
15
ns
Note 1
13*
TckF
CLKOUT fall time
—
5
15
ns
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
—
—
0.5TCY + 20
ns
Note 1
15*
TioV2ckH
Port in valid before CLKOUT ↑
0.25TCY + 25
—
—
ns
Note 1
16*
TckH2ioI
Port in hold after CLKOUT ↑
0
—
—
ns
Note 1
17*
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
—
—
80 - 100
ns
18*
TosH2ioI
OSC1↑ (Q2 cycle) to Port input invalid
(I/O in hold time)
TBD
—
—
ns
19*
TioV2osH
Port input valid to OSC1↑ (I/O in setup
time)
TBD
—
—
ns
20*
TioR
Port output rise time
21*
TioF
Min
Typ†
Max
OSC1↑ to CLKOUT↓
—
15
30
ns
Note 1
OSC1↑ to CLKOUT↑
—
15
30
ns
Note 1
Port output fall time
Units Conditions
PIC16C61
—
10
25
ns
PIC16LC61
—
—
60
ns
PIC16C61
—
10
25
ns
PIC16LC61
—
—
60
ns
22††*
Tinp
RB0/INT pin high or low time
20
—
—
ns
23††*
Trbp
RB7:RB4 change int high or low time
20
—
—
ns
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
††
These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30234D-page 170
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 16-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 16-1 for load conditions.
TABLE 16-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units
30*
TmcL
MCLR Pulse Width (low)
200
—
—
ns
VDD = 5V, -40˚C to +125˚C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40˚C to +125˚C
32
Tost
Oscillation Start-up Timer Period
—
1024TOSC
—
33*
Tpwrt
Power-up Timer Period
28
72
132
ms
34*
TIOZ
I/O Hi-impedance from MCLR Low
—
—
100
ns
*
†
Conditions
TOSC = OSC1 period
VDD = 5V, -40˚C to +125˚C
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 171
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 16-5: TIMER0 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
TMR0
Note: Refer to Figure 16-1 for load conditions.
TABLE 16-5:
Parameter
No.
40*
TIMER0 EXTERNAL CLOCK REQUIREMENTS
Sym Characteristic
Tt0H T0CKI High Pulse Width
Min
No Prescaler
With Prescaler
41*
Tt0L T0CKI Low Pulse Width
No Prescaler
With Prescaler
42*
Tt0P T0CKI Period
No Prescaler
With Prescaler
*
†
Typ† Max Units Conditions
0.5TCY + 20
—
—
ns
10
—
—
ns
0.5TCY + 20
—
—
ns
10
—
—
ns
TCY + 40
—
—
ns
Greater of:
20 ns or
TCY + 40
N
—
—
ns
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4, ..., 256)
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 172
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
17.0
DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES FOR PIC16C61
Note:
The data presented in this section is a statistical summary of data collected on units
from different lots over a period of time and
matrix samples. 'Typical' represents the
mean of the distribution while 'max' or 'min'
represents (mean +3σ) and (mean -3σ)
respectively where σ is standard deviation.
The graphs and tables provided in this section are for
design guidance and are not tested or guaranteed.
In some graphs or tables the data presented are
outside specified operating range (i.e., outside
specified VDD range). This is for information only
and devices are guaranteed to operate properly
only within the specified range.
FIGURE 17-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE
FOSC
FOSC (25°C)
Frequency Normalized TO +25°C
1.050
REXT = 10 kΩ
CEXT = 100 pF
1.025
1.00
VDD = 5.5V
0.975
0.950
0.925
VDD = 3.5V
0.900
0.875
0.850
0
10
20
25
30
40
50
60
70
T (°C)
TABLE 17-1:
RC OSCILLATOR FREQUENCIES
Cext
Rext
20 pF
4.7k
10k
100k
3.3k
4.7k
10k
100k
3.3k
4.7k
10k
100k
100 pF
300 pF
Average
Fosc @ 5V, 25°C
4.52 MHz
2.47 MHz
290.86 kHz
1.92 MHz
1.48 MHz
788.77 kHz
88.11 kHz
726.89 kHz
573.95 kHz
307.31 kHz
33.82 kHz
± 17.35%
± 10.10%
± 11.90%
± 9.43%
± 9.83%
± 10.92%
± 16.03%
± 10.97%
± 10.14%
± 10.43%
± 11.24%
The percentage variation indicated here is part to part variation due to normal process distribution. The variation indicated is ±3 standard deviation from average value for VDD = 5V.
 1997 Microchip Technology Inc.
DS30234D-page 173
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 17-2: TYPICAL RC OSCILLATOR
FREQUENCY VS. VDD
FIGURE 17-4: TYPICAL RC OSCILLATOR
FREQUENCY VS. VDD
8.0
5.0
R = 3.3k
4.5
R = 4.7k
7.0
4.0
6.0
R = 4.7k
5.0
3.0
Fosc (MHz)
Fosc (MHz)
3.5
R = 10k
2.5
4.0
R = 10k
2.0
3.0
1.5
2.0
1.0
Cext = 300 pF, T = 25°C
1.0
0.5
R = 100k
R = 100k
0.0
3.0
3.5
4.0
4.5
5.0
5.5
0.0
3.0
6.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
VDD (Volts)
FIGURE 17-3: TYPICAL RC OSCILLATOR
FREQUENCY VS. VDD
2.0
FIGURE 17-5: TYPICAL IPD VS. VDD
WATCHDOG TIMER
DISABLED 25°C
0.6
R = 3.3k
1.8
1.6
0.5
1.4
R = 4.7k
1.2
0.4
1.0
IPD (µA)
Fosc (MHz)
Data based on matrix samples. See first page of this section for details.
Cext = 20 pF, T = 25°C
0.8
R = 10k
0.3
0.6
0.2
0.4
Cext = 100 pF, T = 25°C
0.2
0.0
0.1
R = 100k
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
6.0
0.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (Volts)
DS30234D-page 174
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 17-6: TYPICAL IPD VS. VDD
WATCHDOG TIMER ENABLED
25°C
FIGURE 17-7: MAXIMUM IPD VS. VDD
WATCHDOG DISABLED
25
14
125°C
12
20
10
IPD (µA)
IPD (µA)
15
8
6
10
70°C
5
2
0
3.0
0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
3.5
4.0
4.5
5.0
VDD (Volts)
5.5
0°C
-40°C
-55°C
6.0
VDD (Volts)
 1997 Microchip Technology Inc.
DS30234D-page 175
Data based on matrix samples. See first page of this section for details.
85°C
4
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 17-8: MAXIMUM IPD VS. VDD
WATCHDOG ENABLED*
FIGURE 17-9: VTH (INPUT THRESHOLD
VOLTAGE) OF I/O PINS VS.
VDD
45
-55°C
-40°C
40
2.00
1.80
IPD (µA)
30
125°C
25
VTH (Volts)
35
Max (-40°C to 85°C)
1.60
25°C, Typ
1.40
1.20
Min (-40°C to 85°C)
1.00
0.80
20
0°C
15
70°C
85°C
0.60
2.5
3.0
3.5
4.0 4.5 5.0
VDD (Volts)
5.5
6.0
10
Data based on matrix samples. See first page of this section for details.
5
0
3.0
3.5
4.0
4.5
5.0
VDD (Volts)
5.5
6.0
*IPD, with Watchdog Timer enabled, has two components: The leakage current which increases with higher
temperature and the operating current of the Watchdog
Timer logic which increases with lower temperature. At
-40°C, the latter dominates explaining the apparently
anomalous behavior.
DS30234D-page 176
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 17-10: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) VS. VDD
4.5
VIH, Max (-40°C to 85°C)
VIH, Typ (25°C)
4.0
VIH, Min (-40°C to 85°C)
VIH, VIL (Volts)
3.5
3.0
2.5
2.0
1.5
VIL, Max (-40°C to 85°C)
1.0
VIL, Typ (25°C)
VIL, Min (-40°C to 85°C)
0.5
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
These pins have Schmitt Trigger input buffers.
FIGURE 17-11: VTH (INPUT THRESHOLD VOLTAGE) OF OSC1 INPUT (IN XT, HS, AND LP MODES)
VS. VDD
3.6
Max (-40°C to 85°C)
3.4
Typ (25°C)
3.2
Min (-40°C to 85°C)
3.0
VTH (Volts)
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VDD (Volts)
 1997 Microchip Technology Inc.
DS30234D-page 177
Data based on matrix samples. See first page of this section for details.
VDD (Volts)
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 17-12: TYPICAL IDD VS. FREQUENCY (EXTERNAL CLOCK, 25°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
IDD (µA)
1,000
100
1
10,000
100,000
1,000,000
100,000,000
10,000,000
Frequency (Hz)
FIGURE 17-13: MAXIMUM IDD VS. FREQUENCY (EXTERNAL CLOCK, -40° TO +85°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
1,000
IDD (µA)
Data based on matrix samples. See first page of this section for details.
10
100
10
10,000
100,000
1,000,000
10,000,000
100,000,000
Frequency (Hz)
DS30234D-page 178
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 17-14: MAXIMUM IDD VS. FREQUENCY (EXTERNAL CLOCK, -55° TO +125°C)
10,000
6.0
5.5
5.0
4.5
4.0
3.5
3.0
IDD (µA)
1,000
10
10,000
100,000
1,000,000
100,000,000
10,000,000
Frequency (Hz)
FIGURE 17-15: WDT TIMER TIME-OUT
PERIOD VS. VDD
FIGURE 17-16: TRANSCONDUCTANCE (gm)
OF HS OSCILLATOR VS. VDD
50
9000
45
8000
40
7000
Max. -40°C
6000
gm (µA/V)
WDT period (ms)
35
30
Max. 85°C
5000
4000
25
Typ. 25°C
Max. 70°C
3000
20
Typ. 25°C
MIn. 85°C
2000
15
Min. 0°C
1000
10
Min. -40°C
0
5
2
2
3
4
5
6
7
3
4
5
6
7
VDD (Volts)
VDD (Volts)
 1997 Microchip Technology Inc.
DS30234D-page 179
Data based on matrix samples. See first page of this section for details.
100
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 17-17: TRANSCONDUCTANCE (gm)
OF LP OSCILLATOR VS. VDD
FIGURE 17-19: IOH VS. VOH, VDD = 3V
0
225
-5
200
MIn. 85°C
Max. -40°C
175
150
-10
IOH (mA)
gm (µA/V)
Typ. 25°C
125
100
Typ. 25°C
-15
MIn. 85°C
75
-20
25
Max. -40°C
0
3.0
3.5
4.0
4.5
VDD (Volts)
5.0
5.5
-25
6.0
0
FIGURE 17-18: TRANSCONDUCTANCE (gm)
OF XT OSCILLATOR VS. VDD
0.5
1.0
1.5
2.0
VOH (Volts)
2.5
3.0
FIGURE 17-20: IOH VS. VOH, VDD = 5V
0
2500
-5
Max. -40°C
-10
200
IOH (mA)
-15
1500
gm (µA/V)
Data based on matrix samples. See first page of this section for details.
50
Typ. 25°C
-20
Min @ 85°C
-25
Typ @ 25°C
-30
100
-35
MIn. 85°C
-40
500
Max @ -40°C
-45
-50
0.0 0.5
0
2
3
4
5
VDD (Volts)
DS30234D-page 180
6
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
7
VOH (Volts)
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 17-21: IOL VS. VOL, VDD = 3V
FIGURE 17-22: IOL VS. VOL, VDD = 5V
90
35
80
Min @ -40°C
30
Min @ -40°C
70
25
60
Typ @ 25°C
Typ @ 25°C
IOL (mA)
IOL (mA)
20
15
50
Min @ +85°C
40
Min @ +85°C
30
10
5
10
0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOL (Volts)
TABLE 17-2:
VOL (Volts)
INPUT CAPACITANCE*
Pin Name
Typical Capacitance (pF)
18L PDIP
18L SOIC
RA port
5.0
4.3
RB port
5.0
4.3
MCLR
17.0
17.0
4.0
3.5
OSC1/CLKIN
OSC2/CLKOUT
4.3
3.5
T0CKI
3.2
2.8
*All capacitance values are typical at 25°C. A part to part variation of ±25% (three standard deviations) should be
taken into account.
 1997 Microchip Technology Inc.
DS30234D-page 181
Data based on matrix samples. See first page of this section for details.
20
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
NOTES:
DS30234D-page 182
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
18.0
ELECTRICAL CHARACTERISTICS FOR PIC16C62/64
Absolute Maximum Ratings †
Ambient temperature under bias............................................................................................................... .-55˚C to +85˚C
Storage temperature ............................................................................................................................... -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ............................................................................................... 0V to +14V
Voltage on RA4 with respect to Vss ................................................................................................................ 0V to +14V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin ............................................................................................................................300 mA
Maximum current into VDD pin ...............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...............................................................................................................±20 mA
Maximum output current sunk by any I/O pin...........................................................................................................25 mA
Maximum output current sourced by any I/O pin .....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE* (combined) .................................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE* (combined) ............................................................200 mA
Maximum current sunk by PORTC and PORTD* (combined)................................................................................200 mA
Maximum current sourced by PORTC and PORTD* (combined) ..........................................................................200 mA
* PORTD and PORTE not available on the PIC16C62.
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 18-1:
OSC
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C62-04
PIC16C64-04
PIC16C62-10
PIC16C64-10
PIC16C62-20
PIC16C64-20
PIC16LC62-04
PIC16LC64-04
JW Devices
RC
VDD: 4.0V to 6.0V
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 3.0V to 6.0V
VDD: 4.0V to 6.0V
IDD: 3.8 mA max. at 5.5V IDD: 2.0 mA typ. at 5.5V IDD: 2.0 mA typ. at 5.5V IDD: 3.8 mA max. at 3.0V IDD: 3.8 mA max. at 5.5V
IPD: 21 µA max. at 4V
IPD: 1.5 µA typ. at 4V
IPD: 1.5 µA typ. at 4V
IPD: 13.5 µA max. at 3V IPD: 21 µA max. at 4V
Freq:4 MHz max.
Freq:4 MHz max.
Freq:4 MHz max.
Freq: 4 MHz max.
Freq:4 MHz max.
XT VDD: 4.0V to 6.0V
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 3.0V to 6.0V
VDD: 4.0V to 6.0V
IDD: 3.8 mA max. at 5.5V IDD: 2.0 mA typ. at 5.5V IDD: 2.0 mA typ. at 5.5V IDD: 3.8 mA max. at 3.0V IDD: 3.8 mA max. at 5.5V
IPD: 21 µA max. at 4V
IPD: 1.5 µA typ. at 4V
IPD: 1.5 µA typ. at 4V
IPD: 13.5 µA max. at 3.0V IPD: 21 µA max. at 4V
Freq:4 MHz max.
Freq:4 MHz max.
Freq:4 MHz max.
Freq: 4 MHz max.
Freq:4 MHz max.
HS VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at 5.5V IDD: 15 mA max. at 5.5V IDD: 30 mA max. at 5.5V
Not recommended for IDD: 30 mA max. at 5.5V
use in HS mode
IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
IPD: 1.5 µA typ. at 4.5V
Freq:4 MHz max.
Freq: 10 MHz max.
Freq: 20 MHz max.
Freq: 20 MHz max.
LP VDD: 4.0V to 6.0V
VDD: 3.0V to 6.0V
VDD: 3.0V to 6.0V
IDD: 52.5 µA typ.
IDD: 48 µA max.
IDD: 48 µA max.
Not recommended for
Not recommended for
at 32 kHz, 4.0V
at 32 kHz, 3.0V
at 32 kHz, 3.0V
use in LP mode
use in LP mode
IPD: 0.9 µA typ. at 4.0V
IPD: 13.5 µA max. at 3.0V IPD:13.5 µA max. at 3.0V
Freq:200 kHz max.
Freq:200 kHz max.
Freq:200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended
that the user select the device type that ensures the specifications required.
 1997 Microchip Technology Inc.
DS30234D-page 183
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
18.1
DC Characteristics:
DC CHARACTERISTICS
Param
No.
Characteristic
PIC16C62/64-04 (Commercial, Industrial)
PIC16C62/64-10 (Commercial, Industrial)
PIC16C62/64-20 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym
Min
Typ† Max Units
Conditions
D001
D001A
Supply Voltage
VDD
4.0
4.5
-
6.0
5.5
V
V
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VPOR
VDD start voltage to
ensure internal Poweron Reset signal
-
VSS
-
V
D004*
VDD rise rate to ensure SVDD
internal Power-on
Reset signal
0.05
-
-
D010
Supply Current
(Note 2, 5)
-
2.7
5.0
mA
XT, RC, osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
-
13.5
30
mA
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
-
10.5
1.5
1.5
42
21
24
µA
µA
µA
VDD = 4.0V, WDT enabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -0°C to +70°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
IDD
D013
D020
D021
D021A
Power-down Current
(Note 3, 5)
IPD
XT, RC and LP osc configuration
HS osc configuration
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
DS30234D-page 184
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
18.2
DC Characteristics:
DC CHARACTERISTICS
Param
No.
D001
D002*
D003
D004*
D010
Characteristic
Supply Voltage
RAM Data Retention
Voltage (Note 1)
VDD start voltage to
ensure internal Poweron Reset signal
VDD rise rate to ensure
internal Power-on
Reset signal
Supply Current
(Note 2, 5)
D010A
PIC16LC62/64-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym Min Typ† Max Units
Conditions
VDD
VDR
3.0
-
1.5
6.0
-
V
V
LP, XT, RC osc configuration (DC - 4 MHz)
VPOR
-
VSS
-
V
See section on Power-on Reset for details
SVDD
0.05
-
-
-
2.0
3.8
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
-
22.5
48
µA
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
IDD
V/ms See section on Power-on Reset for details
D020
Power-down Current
IPD
7.5
30
µA
D021
(Note 3, 5)
0.9 13.5 µA
D021A
0.9
18
µA
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
 1997 Microchip Technology Inc.
DS30234D-page 185
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
18.3
DC Characteristics:
PIC16C62/64-04 (Commercial, Industrial)
PIC16C62/64-10 (Commercial, Industrial)
PIC16C62/64-20 (Commercial, Industrial)
PIC16LC62/64-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
D030
D030A
D031
with Schmitt Trigger buffer
D032
MCLR, OSC1 (in RC mode)
D033
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
D040
with TTL buffer
D040A
D041
D042
D042A
D043
D070
D060
with Schmitt Trigger buffer
MCLR
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
PORTB weak pull-up current
Input Leakage Current (Notes 2, 3)
I/O ports
D061
D063
MCLR, RA4/T0CKI
OSC1
D080
Output Low Voltage
I/O ports
D083
OSC2/CLKOUT (RC osc config)
D090
Output High Voltage
I/O ports (Note 3)
D092
OSC2/CLKOUT (RC osc config)
D150*
Open-Drain High Voltage
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 18.1
and Section 18.2
Sym
Min
Typ Max
Units
Conditions
†
VIL
VSS
VSS
VSS
Vss
Vss
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
2.0
0.25VDD
+ 0.8V
-
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
VDD
VDD
VDD
VDD
400
V
V
V
µA
Note1
VIH
IPURB
IIL
VOL
VOH
VOD
0.8VDD
0.8VDD
0.7VDD 0.9VDD 50
200
For entire VDD range
-
-
±1
µA
-
-
±5
±5
µA
µA
-
-
0.6
V
-
-
0.6
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
-
-
14
V
Note1
VDD = 5V, VPIN = VSS
Vss ≤ VPIN ≤ VDD, Pin at hiimpedance
Vss ≤ VPIN ≤ VDD
Vss ≤ VPIN ≤ VDD, XT, HS and
LP osc configuration
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
RA4 pin
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30234D-page 186
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
DC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 18.1
and Section 18.2
Sym
Min
Typ Max
Units
Conditions
†
D100
Capacitive Loading Specs on Output
Pins
OSC2 pin
COSC2
D101
D102
SCL, SDA in I2C mode
All I/O pins and OSC2 (in RC mode)
CIO
Cb
-
-
15
pF
-
-
50
400
pF
pF
In XT, HS and LP modes
when external clock is used to
drive OSC1.
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
 1997 Microchip Technology Inc.
DS30234D-page 187
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
18.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
FIGURE 18-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF
15 pF
for all pins except OSC2/CLKOUT
but including D and E outputs as ports
Note 1: PORTD and PORTE are not implemented on the PIC16C62.
for OSC2 output
DS30234D-page 188
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
18.5
Timing Diagrams and Specifications
FIGURE 18-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
3
1
3
4
4
2
CLKOUT
TABLE 18-2:
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Fosc
External CLKIN Frequency
(Note 1)
Min
Typ†
Max
Units Conditions
DC
—
4
MHz XT and RC osc mode
DC
—
4
MHz HS osc mode (-04)
DC
—
10
MHz HS osc mode (-10)
DC
—
20
MHz HS osc mode (-20)
DC
—
200
kHz LP osc mode
Oscillator Frequency
DC
—
4
MHz RC osc mode
(Note 1)
0.1
—
4
MHz XT osc mode
4
—
20
MHz HS osc mode
5
—
200
kHz LP osc mode
1
Tosc External CLKIN Period
250
—
—
ns
XT and RC osc mode
(Note 1)
250
—
—
ns
HS osc mode (-04)
100
—
—
ns
HS osc mode (-10)
50
—
—
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
Oscillator Period
250
—
—
ns
RC osc mode
(Note 1)
250
—
10,000
ns
XT osc mode
250
—
250
ns
HS osc mode (-04)
100
—
250
ns
HS osc mode (-10)
50
—
1,000
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
TCY
DC
ns
TCY = 4/FOSC
2
TCY Instruction Cycle Time (Note 1) 200
3
TosL, External Clock in (OSC1) High
100
—
—
ns
XT oscillator
TosH or Low Time
2.5
—
—
µs
LP oscillator
15
—
—
ns
HS oscillator
4
TosR, External Clock in (OSC1) Rise
—
—
25
ns
XT oscillator
TosF or Fall Time
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
 1997 Microchip Technology Inc.
DS30234D-page 189
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 18-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 18-1 for load conditions.
TABLE 18-3:
Parameters
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
10*
TosH2ckL
OSC1↑ to CLKOUT↓
—
75
200
ns
Note 1
11*
TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns
Note 1
12*
TckR
CLKOUT rise time
—
35
100
ns
Note 1
13*
TckF
CLKOUT fall time
—
35
100
ns
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
—
—
0.5TCY + 20
ns
Note 1
15*
TioV2ckH
Port in valid before CLKOUT ↑
TOSC + 200
—
—
ns
Note 1
16*
TckH2ioI
Port in hold after CLKOUT ↑
0
—
—
ns
Note 1
17*
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
18*
TosH2ioI
OSC1↑ (Q2 cycle) to Port
PIC16C62/64
input invalid (I/O in hold time)
PIC16LC62/64
19*
TioV2osH
Port input valid to OSC1↑
(I/O in setup time)
20*
TioR
Port output rise time
21*
TioF
Port output fall time
Units Conditions
—
50
150
ns
100
—
—
ns
200
—
—
ns
0
—
—
ns
PIC16C62/64
—
10
40
ns
PIC16LC62/64
—
—
80
ns
PIC16C62/64
—
10
40
ns
PIC16LC62/64
—
—
80
ns
22††*
Tinp
INT pin high or low time
TCY
—
—
ns
23††*
Trbp
RB7:RB4 change INT high or low time
TCY
—
—
ns
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30234D-page 190
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 18-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 18-1 for load conditions.
TABLE 18-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max
Units
30*
TmcL
MCLR Pulse Width (low)
100
—
—
ns
VDD = 5V, -40˚C to +85˚C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40˚C to +85˚C
32
Tost
Oscillation Start-up Timer Period
—
1024TOSC
—
—
TOSC = OSC1 period
33*
Tpwrt
Power-up Timer Period
28
72
132
ms
VDD = 5V, -40˚C to +85˚C
34*
TIOZ
I/O Hi-impedance from MCLR Low
—
—
100
ns
*
†
Conditions
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 191
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 18-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSI/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 18-1 for load conditions.
TABLE 18-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
T0CKI Low Pulse Width
With Prescaler
No Prescaler
With Prescaler
41*
42*
45*
46*
47*
48
*
†
Tt0L
Min
Typ†
Max
0.5TCY + 20
—
—
ns
10
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
0.5TCY + 20
10
Tt0P
T0CKI Period
TCY + 40
No Prescaler
With Prescaler Greater of:
20 or TCY + 40
N
Tt1H
T1CKI High Time Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16C6X
15
Prescaler =
PIC16LC6X
25
2,4,8
Asynchronous PIC16C6X
30
PIC16LC6X
50
Tt1L
T1CKI Low Time
Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16C6X
15
Prescaler =
PIC16LC6X
25
2,4,8
Asynchronous PIC16C6X
30
PIC16LC6X
50
Tt1P
T1CKI input period Synchronous PIC16C6X
Greater of:
30 OR TCY + 40
N
Greater of:
PIC16LC6X
50 OR TCY + 40
N
Asynchronous PIC16C6X
60
PIC16LC6X
100
Ft1
Timer1 oscillator input frequency range
DC
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
Units Conditions
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4, ..., 256)
Must also meet
parameter 47
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
N = prescale value
(1, 2, 4, 8)
—
—
—
—
—
200
ns
ns
kHz
—
7Tosc
—
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 192
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 18-6: CAPTURE/COMPARE/PWM TIMINGS (CCP1)
RC2/CCP1
(Capture Mode)
50
51
52
RC2/CCP1
(Compare or
PWM Mode)
54
53
Note: Refer to Figure 18-1 for load conditions.
TABLE 18-6:
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)
Parameter
No.
Sym Characteristic
50*
TccL CCP1
input low time
Min
No Prescaler
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
3TCY + 40
N
—
—
ns
PIC16C62/64
—
10
25
ns
PIC16LC62/64
—
25
45
ns
PIC16C62/64
—
10
25
ns
PIC16LC62/64
—
25
45
ns
With Prescaler PIC16C62/64
PIC16LC62/64
51*
TccH CCP1
input high time
No Prescaler
With Prescaler PIC16C62/64
PIC16LC62/64
52*
TccP CCP1 input period
53
TccR CCP1 output rise time
54
*
†
TccF CCP1 output fall time
Typ† Max Units Conditions
N = prescale value
(1,4 or 16)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 193
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 18-7: PARALLEL SLAVE PORT TIMING (PIC16C64)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 18-1 for load conditions
TABLE 18-7:
PARALLEL SLAVE PORT REQUIREMENTS (PIC16C64)
Parameter
No.
Sym
62
TdtV2wrH
63*
TwrH2dtI
*
†
Characteristic
Min
Typ†
Max
Units
Data in valid before WR↑ or CS↑ (setup time)
20
—
—
ns
WR↑ or CS↑ to data–in invalid PIC16C64
(hold time)
PIC16LC64
20
—
—
ns
35
—
—
ns
64
TrdL2dtV
RD↓ and CS↓ to data–out valid
—
—
80
ns
65
TrdH2dtI
RD↑ or CS↑ to data–out invalid
10
—
30
ns
Conditions
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 194
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 18-8: SPI MODE TIMING
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
SDO
77
75, 76
SDI
74
73
Note: Refer to Figure 18-1 for load conditions
TABLE 18-8:
Parameter
No.
SPI MODE REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
TCY
—
—
ns
70
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
71
TscH
SCK input high time (slave mode)
TCY + 20
—
—
ns
72
TscL
SCK input low time (slave mode)
TCY + 20
—
—
ns
73
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK
edge
50
—
—
ns
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK
edge
50
—
—
ns
75
TdoR
SDO data output rise time
—
10
25
ns
76
TdoF
SDO data output fall time
—
10
25
ns
77
TssH2doZ
SS↑ to SDO output hi-impedance
10
—
50
ns
78
TscR
SCK output rise time (master mode)
—
10
25
ns
79
TscF
SCK output fall time (master mode)
—
10
25
ns
Conditions
80
†
TscH2doV,
SDO data output valid after SCK
—
—
50
ns
TscL2doV
edge
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 195
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 18-9: I2C BUS START/STOP BITS TIMING
SCL
91
93
92
90
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 18-1 for load conditions
TABLE 18-9:
I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
90
TSU:STA
91
92
93
THD:STA
TSU:STO
THD:STO
DS30234D-page 196
Characteristic
Min
Typ Max
START condition
100 kHz mode
4700
—
—
Setup time
400 kHz mode
600
—
—
START condition
100 kHz mode
4000
—
—
Hold time
400 kHz mode
600
—
—
STOP condition
100 kHz mode
4700
—
—
Setup time
400 kHz mode
600
—
—
STOP condition
100 kHz mode
4000
—
—
Hold time
400 kHz mode
600
—
—
Units
Conditions
ns
Only relevant for repeated START
condition
ns
After this period the first clock
pulse is generated
ns
ns
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 18-10:
I2C
BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 18-1 for load conditions
TABLE 18-10: I2C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
100
THIGH
Clock high time
101
102
103
TLOW
TR
TF
Clock low time
SDA and SCL rise
time
SDA and SCL fall time
90
TSU:STA
START condition
setup time
91
THD:STA
START condition hold
time
106
THD:DAT
Data input hold time
107
TSU:DAT
Data input setup time
92
TSU:STO
STOP condition setup
time
109
TAA
Output valid from
clock
110
TBUF
Bus free time
Min
Max
Units
Conditions
100 kHz mode
4.0
—
µs
400 kHz mode
0.6
—
µs
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
SSP Module
100 kHz mode
1.5TCY
4.7
—
—
µs
400 kHz mode
1.3
—
µs
SSP Module
100 kHz mode
400 kHz mode
1.5TCY
—
20 + 0.1Cb
—
1000
300
ns
ns
100 kHz mode
400 kHz mode
—
20 + 0.1Cb
300
300
ns
ns
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
—
—
—
—
0.9
—
—
—
—
3500
—
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
Cb is specified to be from
10 to 400 pF
Cb is specified to be from
10 to 400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can
start
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
tsu;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max. + tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
 1997 Microchip Technology Inc.
DS30234D-page 197
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
NOTES:
DS30234D-page 198
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
19.0
ELECTRICAL CHARACTERISTICS FOR PIC16C62A/R62/64A/R64
Absolute Maximum Ratings †
Ambient temperature under bias............................................................................................................. .-55˚C to +125˚C
Storage temperature ............................................................................................................................... -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ............................................................................................... 0V to +14V
Voltage on RA4 with respect to Vss ................................................................................................................. 0V to +14V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin ............................................................................................................................300 mA
Maximum current into VDD pin ...............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...............................................................................................................±20 mA
Maximum output current sunk by any I/O pin...........................................................................................................25 mA
Maximum output current sourced by any I/O pin .....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined)...................................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) .............................................................200 mA
Maximum current sunk by PORTC and PORTD (combined) .................................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined)............................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 19-1:
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C62A-10
PIC16CR62-10
PIC16C64A-10
PIC16CR64-10
PIC16C62A-20
PIC16CR62-20
PIC16C64A-20
PIC16CR64-20
PIC16LC62A-04
PIC16LCR62-04
PIC16LC64A-04
PIC16LCR64-04
RC VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq:4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.0 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.0 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 6.0V
IDD: 3.8 mA max. at 3.0V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq:4 MHz max.
XT VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.0 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.0 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 6.0V
IDD: 3.8 mA max. at 3.0V
IPD: 5 µA max. at 3.0V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
HS VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
OSC
PIC16C62A-04
PIC16CR62-04
PIC16C64A-04
PIC16CR64-04
JW Devices
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at 5.5V IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V Not recommended for use IDD: 20 mA max. at 5.5V
in HS mode
IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max.
LP
Freq: 10 MHz max.
VDD: 4.0V to 6.0V
IDD: 52.5 µA typ.
at 32 kHz, 4.0V
IPD: 0.9 µA typ. at 4.0V
Freq: 200 kHz max.
Not recommended for
use in LP mode
Freq: 20 MHz max.
Not recommended for
use in LP mode
Freq: 20 MHz max.
VDD: 2.5V to 6.0V
IDD: 48 µA max. at 32
kHz, 3.0V
IPD: 5 µA max. at 3.0V
Freq: 200 kHz max.
VDD: 2.5V to 6.0V
IDD: 48 µA max.
at 32 kHz, 3.0V
IPD: 5 µA max. at 3.0V
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended
that the user select the device type that ensures the specifications required.
 1997 Microchip Technology Inc.
DS30234D-page 199
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
19.1
DC Characteristics:
DC CHARACTERISTICS
Param
No.
Characteristic
PIC16C62A/R62/64A/R64-04 (Commercial, Industrial, Extended)
PIC16C62A/R62/64A/R64-10 (Commercial, Industrial, Extended)
PIC16C62A/R62/64A/R64-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym
Min
Typ† Max Units
D001
D001A
Supply Voltage
VDD
4.0
4.5
-
6.0
5.5
V
V
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VDD start voltage to
ensure internal Power-on
Reset signal
VPOR
-
VSS
-
V
D004*
VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
D005
Brown-out Reset Voltage
BVDD
3.7
4.0
4.3
3.7
4.0
4.4
V
D010
Supply Current (Note 2, 5) IDD
-
2.7
5
mA
-
10
20
mA
D013
Conditions
XT, RC and LP osc configuration
HS osc configuration
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
V
BODEN bit in configuration word enabled
Extended Range Only
XT, RC, osc configuration FOSC = 4 MHz,
VDD = 5.5V (Note 4)
HS osc configuration FOSC = 20 MHz,
VDD = 5.5V
D015*
Brown-out Reset Current
(Note 6)
∆ IBOR
-
350
425
µA
BOR enabled, VDD = 5.0V
D020
D021
D021A
D021B
Power-down Current
(Note 3, 5)
IPD
-
10.5
1.5
1.5
2.5
42
16
19
19
µA
µA
µA
µA
VDD = 4.0V, WDT enabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -0°C to +70°C
VDD = 4.0V, WDT disabled, -40°C to +85°C
VDD = 4.0V, WDT disabled, -40°C to +125°C
D023*
Brown-out Reset Current
(Note 6)
∆ IBOR
-
350
425
µA
BOR enabled, VDD = 5.0V
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
DS30234D-page 200
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
19.2
DC Characteristics:
PIC16LC62A/R62/64A/R64-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
D001
D002*
D003
D004*
D005
D010
Characteristic
Supply Voltage
RAM Data Retention Voltage (Note 1)
VDD start voltage to
ensure internal Power-on
Reset signal
VDD rise rate to ensure
internal Power-on Reset
signal
Brown-out Reset Voltage
Supply Current (Note 2, 5)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym Min Typ† Max Units
Conditions
VDD
VDR
2.5
-
1.5
6.0
-
V
V
LP, XT, RC osc configuration (DC - 4 MHz)
VPOR
-
VSS
-
V
See section on Power-on Reset for details
SVDD
0.05
-
-
BVDD
IDD
3.7
-
4.0
2.0
4.3
3.8
V
mA
BODEN bit in configuration word enabled
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
-
22.5
48
µA
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
∆IBOR
-
350
425
µA
BOR enabled, VDD = 5.0V
IPD
-
7.5
0.9
0.9
30
5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D010A
D015*
D020
D021
D021A
Brown-out Reset Current
(Note 6)
Power-down Current
(Note 3, 5)
V/ms See section on Power-on Reset for details
µA BOR enabled, VDD = 5.0V
350 425
Brown-out Reset Current ∆IBOR
(Note 6)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added
to the base IDD or IPD measurement.
D023*
 1997 Microchip Technology Inc.
DS30234D-page 201
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
19.3
DC Characteristics:
PIC16C62A/R62/64A/R64-04 (Commercial, Industrial, Extended)
PIC16C62A/R62/64A/R64-10 (Commercial, Industrial, Extended)
PIC16C62A/R62/64A/R64-20 (Commercial, Industrial, Extended)
PIC16LC62A/R62/64A/R64-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
D030
D030A
D031
with Schmitt Trigger buffer
D032 MCLR, OSC1 (in RC mode)
D033 OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
D040
with TTL buffer
D040A
D041
D042
D042A
D043
D070
D060
with Schmitt Trigger buffer
MCLR
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
PORTB weak pull-up current
Input Leakage Current (Notes 2, 3)
I/O ports
D061
D063
MCLR, RA4/T0CKI
OSC1
D080
Output Low Voltage
I/O ports
D080A
D083
OSC2/CLKOUT (RC osc config)
D083A
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 19.1 and
Section 19.2
Sym
Min Typ Max Units
Conditions
†
VIL
Vss
VSS
Vss
Vss
Vss
VIH
2.0
0.25VDD
+ 0.8V
IPURB
IIL
VOL
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
-
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
VDD
VDD
VDD
VDD
400
V
V
V
V
µA
For entire VDD range
Vss ≤ VPIN ≤ VDD, Pin at hi-impedance
Vss ≤ VPIN ≤ VDD
Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
0.8VDD 0.8VDD 0.7VDD 0.9VDD 50
250
-
-
±1
µA
-
-
±5
±5
µA
µA
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
Note1
Note1
VDD = 5V, VPIN = VSS
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30234D-page 202
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
DC CHARACTERISTICS
Param
No.
D090
Characteristic
Output High Voltage
I/O ports (Note 3)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 19.1 and
Section 19.2
Sym
Min Typ Max Units
Conditions
†
VOH
D090A
D092
OSC2/CLKOUT (RC osc config)
D092A
D150* Open-Drain High Voltage
VOD
Capacitive Loading Specs on Output Pins
D100 OSC2 pin
COSC2
VDD-0.7
-
-
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
-
-
14
V
-
-
15
pF
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
RA4 pin
In XT, HS and LP modes when
external clock is used to drive
OSC1.
D101
D102
All I/O pins and OSC2 (in RC mode) CIO
50
pF
Cb
400
pF
SCL, SDA in I2C mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
 1997 Microchip Technology Inc.
DS30234D-page 203
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
19.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
FIGURE 19-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
VSS
RL = 464Ω
CL = 50 pF
Note 1: PORTD and PORTE are not
implemented on the
PIC16C62A/R62.
DS30234D-page 204
15 pF
for all pins except OSC2/CLKOUT
but including D and E outputs as ports
for OSC2 output
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
19.5
Timing Diagrams and Specifications
FIGURE 19-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
3
1
3
4
4
2
CLKOUT
TABLE 19-2:
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Fosc
External CLKIN Frequency
(Note 1)
Min
Typ†
Max
Units Conditions
DC
—
4
MHz XT and RC osc mode
DC
—
4
MHz HS osc mode (-04)
DC
—
10
MHz HS osc mode (-10)
DC
—
20
MHz HS osc mode (-20)
DC
—
200
kHz LP osc mode
Oscillator Frequency
DC
—
4
MHz RC osc mode
(Note 1)
0.1
—
4
MHz XT osc mode
4
—
20
MHz HS osc mode
5
—
200
kHz LP osc mode
1
Tosc External CLKIN Period
250
—
—
ns
XT and RC osc mode
(Note 1)
250
—
—
ns
HS osc mode (-04)
100
—
—
ns
HS osc mode (-10)
50
—
—
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
Oscillator Period
250
—
—
ns
RC osc mode
(Note 1)
250
—
10,000
ns
XT osc mode
250
—
250
ns
HS osc mode (-04)
100
—
250
ns
HS osc mode (-10)
50
—
250
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
200
TCY
DC
ns
TCY = 4/FOSC
2
TCY Instruction Cycle Time (Note 1)
3
TosL, External Clock in (OSC1) High or
100
—
—
ns
XT oscillator
TosH Low Time
2.5
—
—
µs
LP oscillator
15
—
—
ns
HS oscillator
4
TosR, External Clock in (OSC1) Rise or
—
—
25
ns
XT oscillator
TosF Fall Time
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
 1997 Microchip Technology Inc.
DS30234D-page 205
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 19-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
10
11
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 19-1 for load conditions.
TABLE 19-3:
CLKOUT AND I/O TIMING REQUIREMENTS
Parameters Sym
Min
Typ†
Max
10*
TosH2ckL
OSC1↑ to CLKOUT↓
Characteristic
—
75
200
Units Conditions
ns
Note 1
11*
TosH2ckH
OSC1↑ to CLKOUT↑
—
75
200
ns
Note 1
12*
TckR
CLKOUT rise time
—
35
100
ns
Note 1
13*
TckF
CLKOUT fall time
—
35
100
ns
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
—
—
0.5TCY + 20
ns
Note 1
15*
TioV2ckH
Port in valid before CLKOUT ↑
Tosc + 200
—
—
ns
Note 1
16*
TckH2ioI
Port in hold after CLKOUT ↑
0
—
—
ns
Note 1
17*
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
—
50
150
ns
18*
TosH2ioI
OSC1↑ (Q2 cycle) to Port input PIC16C62A/
invalid (I/O in hold time)
R62/64A/R64
100
—
—
ns
PIC16LC62A/
R62/64A/R64
200
—
—
ns
19*
TioV2osH
Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TioR
Port output rise time
PIC16C62A/
R62/64A/R64
—
10
40
ns
PIC16LC62A/
R62/64A/R64
—
—
80
ns
PIC16C62A/
R62/64A/R64
—
10
40
ns
PIC16LC62A/
R62/64A/R64
—
—
80
ns
21*
TioF
Port output fall time
22††*
Tinp
RB0/INT pin high or low time
TCY
—
—
ns
23††*
Trbp
RB7:RB4 change int high or low time
TCY
—
—
ns
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30234D-page 206
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 19-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 19-1 for load conditions.
FIGURE 19-5: BROWN-OUT RESET TIMING
BVDD
VDD
TABLE 19-4:
35
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym
Characteristic
30
TmcL
31*
*
†
Min
Typ†
Max
Units
Conditions
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40˚C to +125˚C
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40˚C to +125˚C
32
Tost
Oscillation Start-up Timer Period
—
1024TOSC
—
—
TOSC = OSC1 period
33*
Tpwrt
Power-up Timer Period
28
72
132
ms
VDD = 5V, -40˚C to +125˚C
34
TIOZ
I/O Hi-impedance from MCLR Low
or WDT Reset
—
—
2.1
µs
35
TBOR
Brown-out Reset Pulse Width
100
—
—
µs
VDD ≤ BVDD (param. D005)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 207
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 19-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 19-1 for load conditions.
TABLE 19-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
T0CKI Low Pulse Width
With Prescaler
No Prescaler
With Prescaler
41*
42*
45*
46*
47*
48
*
†
Tt0L
Min
Typ†
Max
0.5TCY + 20
—
—
ns
10
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
0.5TCY + 20
10
Tt0P
T0CKI Period
TCY + 40
No Prescaler
With Prescaler Greater of:
20 or TCY + 40
N
Tt1H
T1CKI High Time Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16C6X
15
Prescaler =
PIC16LC6X
25
2,4,8
Asynchronous PIC16C6X
30
PIC16LC6X
50
Tt1L
T1CKI Low Time
Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16C6X
15
Prescaler =
PIC16LC6X
25
2,4,8
Asynchronous PIC16C6X
30
PIC16LC6X
50
Tt1P
T1CKI input period Synchronous PIC16C6X
Greater of:
30 OR TCY + 40
N
Greater of:
PIC16LC6X
50 OR TCY + 40
N
Asynchronous PIC16C6X
60
PIC16LC6X
100
Ft1
Timer1 oscillator input frequency range
DC
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
Units Conditions
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4, ..., 256)
Must also meet
parameter 47
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
N = prescale value
(1, 2, 4, 8)
—
—
—
—
—
200
ns
ns
kHz
—
7Tosc
—
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 208
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 19-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1)
RC2/CCP1
(Capture Mode)
50
51
52
RC2/CCP1
(Compare or
PWM Mode)
53
54
Note: Refer to Figure 19-1 for load conditions.
TABLE 19-6:
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)
Parameter Sym Characteristic
No.
50*
TccL CCP1
input low time
Min
No Prescaler
With Prescaler PIC16C62A/R62/
64A/R64
PIC16LC62A/R62/
64A/R64
51*
TccH CCP1
input high time
No Prescaler
53*
TccR CCP1 output rise time
54*
*
†
TccF CCP1 output fall time
—
—
ns
10
—
—
ns
20
—
—
ns
—
—
ns
10
—
—
ns
20
—
—
ns
3TCY + 40
N
—
—
ns
PIC16C62A/R62/
64A/R64
—
10
25
ns
PIC16LC62A/R62/
64A/R64
—
25
45
ns
PIC16C62A/R62/
64A/R64
—
10
25
ns
PIC16LC62A/R62/
64A/R64
—
25
45
ns
PIC16LC62A/R62/
64A/R64
TccP CCP1 input period
0.5TCY + 20
0.5TCY + 20
With Prescaler PIC16C62A/R62/
64A/R64
52*
Typ† Max Units Conditions
N = prescale value
(1,4 or 16)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 209
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 19-8: PARALLEL SLAVE PORT TIMING (PIC16C64A/R64)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 19-1 for load conditions
TABLE 19-7:
Parameter
No.
62
63*
64
65*
*
†
PARALLEL SLAVE PORT REQUIREMENTS (PIC16C64A/R64)
Sym
Characteristic
Min
Typ†
Max
Units
20
—
—
ns
25
—
—
ns
PIC16C64A/R64
20
—
—
ns
PIC16LC64A/R64
35
—
—
ns
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
TwrH2dtI
TrdL2dtV
TrdH2dtI
WR↑ or CS↑ to data–in invalid (hold
time)
RD↓ and CS↓ to data–out valid
RD↑ or CS↑ to data–out invalid
—
—
80
ns
—
—
90
ns
10
—
30
ns
Conditions
Extended
Range Only
Extended
Range Only
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 210
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 19-9: SPI MODE TIMING
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
SDO
77
75, 76
SDI
74
73
Note: Refer to Figure 19-1 for load conditions
TABLE 19-8:
Parameter
No.
70*
SPI MODE REQUIREMENTS
Sym
TssL2scH,
TssL2scL
Characteristic
Min
Typ†
Max
Units
SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
71*
TscH
SCK input high time (slave mode)
TCY + 20
—
—
ns
72*
TscL
SCK input low time (slave mode)
TCY + 20
—
—
ns
73*
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK
edge
50
—
—
ns
74*
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK
edge
50
—
—
ns
75*
TdoR
SDO data output rise time
—
10
25
ns
76*
TdoF
SDO data output fall time
—
10
25
ns
77*
TssH2doZ
SS↑ to SDO output hi-impedance
10
—
50
ns
78*
TscR
SCK output rise time (master mode)
—
10
25
ns
79*
TscF
SCK output fall time (master mode)
—
10
25
ns
Conditions
80*
*
†
TscH2doV,
SDO data output valid after SCK
—
—
50
ns
TscL2doV
edge
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 211
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 19-10: I2C BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 19-1 for load conditions
TABLE 19-9:
I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
90*
TSU:STA
91*
THD:STA
92*
TSU:STO
93*
THD:STO
Characteristic
START condition
Setup time
START condition
Hold time
STOP condition
Setup time
STOP condition
Hold time
Min
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
4000
600
4700
600
4000
600
Typ Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
Conditions
ns
Only relevant for repeated START
condition
ns
After this period the first clock
pulse is generated
ns
ns
*These parameters are characterized but not tested.
DS30234D-page 212
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 19-11:
I2C
BUS DATA TIMING
103
102
100
101
SCL
90
106
107
92
91
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 19-1 for load conditions
TABLE 19-10: I2C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
100*
THIGH
Clock high time
101*
102*
103*
TLOW
TR
TF
Clock low time
SDA and SCL rise
time
SDA and SCL fall time
90*
TSU:STA
91*
THD:STA
106*
THD:DAT
START condition
setup time
START condition hold
time
Data input hold time
107*
TSU:DAT
Data input setup time
92*
TSU:STO
109*
TAA
110*
TBUF
STOP condition setup
time
Output valid from
clock
Bus free time
Min
Max
Units
Conditions
100 kHz mode
4.0
—
µs
400 kHz mode
0.6
—
µs
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
SSP Module
100 kHz mode
1.5TCY
4.7
—
—
µs
400 kHz mode
1.3
—
µs
SSP Module
100 kHz mode
400 kHz mode
1.5TCY
—
20 + 0.1Cb
—
1000
300
ns
ns
100 kHz mode
400 kHz mode
—
20 + 0.1Cb
300
300
ns
ns
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
—
—
—
—
0.9
—
—
—
—
3500
—
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
Cb is specified to be from
10-400 pF
Cb is specified to be from
10-400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can
start
Cb
Bus capacitive loading
—
400
pF
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
tsu;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
 1997 Microchip Technology Inc.
DS30234D-page 213
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
NOTES:
DS30234D-page 214
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
20.0
ELECTRICAL CHARACTERISTICS FOR PIC16C65
Absolute Maximum Ratings †
Ambient temperature under bias............................................................................................................... .-55˚C to +85˚C
Storage temperature ............................................................................................................................... -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ............................................................................................... 0V to +14V
Voltage on RA4 with respect to Vss ................................................................................................................. 0V to +14V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin ............................................................................................................................300 mA
Maximum current into VDD pin ...............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...............................................................................................................±20 mA
Maximum output current sunk by any I/O pin...........................................................................................................25 mA
Maximum output current sourced by any I/O pin .....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (combined)...................................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (combined) .............................................................200 mA
Maximum current sunk by PORTC and PORTD (combined) .................................................................................200 mA
Maximum current sourced by PORTC and PORTD (combined)............................................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus,
a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 20-1:
OSC
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C65-04
PIC16C65-10
PIC16C65-20
RC VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 21 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 3.0V to 6.0V
IDD: 3.8 mA max. at 3V
IPD: 800 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 21 µA max. at 4V
Freq: 4 MHz max.
XT
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 3.0V to 6.0V
IDD: 3.8 mA max. at 3V
IPD: 800 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 21 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 21 µA max. at 4V
Freq: 4 MHz max.
HS VDD: 4.5V to 5.5V
LP
IDD: 13.5 mA typ. at
5.5V
IDD: 15 mA max. at 5.5V IDD: 30 mA max. at
5.5V
IPD: 1.5 µA typ. at 4.5V
IPD 1.0 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max.
Freq: 10 MHz max.
VDD: 4.0V to 6.0V
IDD: 52.5 µA typ.
at 32 kHz, 4.0V
IPD: 0.9 µA typ. at 4.0V
Freq: 200 kHz max.
Not recommended for
use in LP mode
PIC16LC65-04
JW Devices
VDD: 4.5V to 5.5V
Not recommended for
use in HS mode
Freq: 20 MHz max.
VDD: 3.0V to 6.0V
IDD: 105 µA max.
Not recommended for
at 32 kHz, 3.0V
use in LP mode
IPD: 800 µA max. at
3.0V
Freq: 200 kHz max.
IDD: 30 mA max. at 5.5V
IPD: 1.5 µA typ. at 4.5V
Freq: 20 MHz max.
VDD: 3.0V to 6.0V
IDD: 105 µA max.
at 32 kHz, 3.0V
IPD: 800 µA max. at
3.0V
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
 1997 Microchip Technology Inc.
DS30234D-page 215
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
20.1
DC Characteristics:
DC CHARACTERISTICS
Param
No.
Characteristic
PIC16C65-04 (Commercial, Industrial)
PIC16C65-10 (Commercial, Industrial)
PIC16C65-20 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym
Min
Typ† Max Units
Conditions
D001
D001A
Supply Voltage
VDD
4.0
4.5
-
6.0
5.5
V
V
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VDD start voltage to
ensure internal Power-on
Reset signal
VPOR
-
VSS
-
V
D004*
VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
D010
Supply Current (Note 2, 5) IDD
-
2.7
5
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 5.5V (Note 4)
-
13.5
30
mA
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V
-
10.5
1.5
1.5
800
800
800
µA
µA
µA
VDD = 4.0V, WDT enabled,-40°C to +85°C
VDD = 4.0V, WDT disabled,-0°C to +70°C
VDD = 4.0V, WDT disabled,-40°C to +85°C
D013
D020
D021
D021A
Power-down Current
(Note 3, 5)
IPD
XT, RC and LP osc configuration
HS osc configuration
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
DS30234D-page 216
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
20.2
DC Characteristics:
DC CHARACTERISTICS
Param
No.
Characteristic
D001
D002*
Supply Voltage
RAM Data Retention
Voltage (Note 1)
VDD start voltage to
ensure internal Power-on
Reset signal
VDD rise rate to ensure
internal Power-on Reset
signal
Supply Current (Note 2, 5)
D003
D004*
D010
D010A
PIC16LC65-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym Min Typ† Max Units
Conditions
VDD
VDR
3.0
-
1.5
6.0
-
V
V
LP, XT, RC osc configuration (DC - 4 MHz)
VPOR
-
VSS
-
V
See section on Power-on Reset for details
SVDD
0.05
-
-
-
2.0
3.8
mA
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
-
22.5
105
µA
LP osc configuration
FOSC = 32 kHz, VDD = 4.0V, WDT disabled
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
IDD
V/ms See section on Power-on Reset for details
D020 Power-down Current
IPD
7.5 800
µA
D021 (Note 3, 5)
0.9 800
µA
D021A
0.9 800
µA
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
 1997 Microchip Technology Inc.
DS30234D-page 217
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
20.3
DC Characteristics:
PIC16C65-04 (Commercial, Industrial)
PIC16C65-10 (Commercial, Industrial)
PIC16C65-20 (Commercial, Industrial)
PIC16LC65-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
D030
D030A
D031
D032
D033
D040
D040A
D041
D042
D042A
D043
D070
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR, OSC1(in RC mode)
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
with TTL buffer
D060
with Schmitt Trigger buffer
MCLR
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
PORTB weak pull-up current
Input Leakage Current
(Notes 2, 3)
I/O ports
D061
D063
MCLR, RA4/T0CKI
OSC1
D080
Output Low Voltage
I/O ports
D083
OSC2/CLKOUT (RC osc config)
D090
Output High Voltage
I/O ports (Note 3)
D092
OSC2/CLKOUT (RC osc config)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 20.1 and
Section 20.2
Sym
Min
Typ Max
Units
Conditions
†
VIL
VSS
VSS
VSS
Vss
Vss
VIH
2.0
0.25VDD
+ 0.8V
IPURB
IIL
VOL
VOH
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
-
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
VDD
VDD
VDD
VDD
400
V
V
V
µA
0.8VDD
0.8VDD
0.7 VDD 0.9VDD
50
250
Note1
For entire VDD range
-
-
±1
µA
-
-
±5
±5
µA
µA
-
-
0.6
V
-
-
0.6
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
Note1
VDD = 5V, VPIN = VSS
Vss ≤ VPIN ≤ VDD, Pin at hiimpedance
Vss ≤ VPIN ≤ VDD
Vss ≤ VPIN ≤ VDD, XT, HS, and
LP osc configuration
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
RA4 pin
D150* Open-Drain High Voltage
VOD
14
V
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30234D-page 218
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
DC CHARACTERISTICS
Param
No.
D100
Characteristic
Capacitive Loading Specs on
Output Pins
OSC2 pin
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 20.1 and
Section 20.2
Sym
Min
Typ Max
Units
Conditions
†
COSC2
-
-
15
pF
In XT, HS and LP modes when
external clock is used to drive
OSC1.
D101
D102
All I/O pins and OSC2 (in RC mode) CIO
50
pF
Cb
400
pF
SCL, SDA in I2C mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
 1997 Microchip Technology Inc.
DS30234D-page 219
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
20.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
FIGURE 20-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 2
Load condition 1
VDD/2
CL
Pin
RL
VSS
CL
Pin
RL = 464Ω
VSS
CL = 50 pF
15 pF
DS30234D-page 220
for all pins except OSC2/CLKOUT
but including D and E outputs as ports
for OSC2 output
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
20.5
Timing Diagrams and Specifications
FIGURE 20-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
3
1
3
4
4
2
CLKOUT
TABLE 20-2:
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Fosc
External CLKIN Frequency
(Note 1)
Min
Typ†
Max
Units Conditions
DC
—
4
MHz XT and RC osc mode
DC
—
4
MHz HS osc mode (-04)
DC
—
10
MHz HS osc mode (-10)
DC
—
20
MHz HS osc mode (-20)
DC
—
200
kHz LP osc mode
Oscillator Frequency
DC
—
4
MHz RC osc mode
(Note 1)
0.1
—
4
MHz XT osc mode
4
—
20
MHz HS osc mode
5
—
200
kHz LP osc mode
1
Tosc External CLKIN Period
250
—
—
ns
XT and RC osc mode
(Note 1)
250
—
—
ns
HS osc mode (-04)
100
—
—
ns
HS osc mode (-10)
50
—
—
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
Oscillator Period
250
—
—
ns
RC osc mode
(Note 1)
250
—
10,000
ns
XT osc mode
250
—
250
ns
HS osc mode (-04)
100
—
250
ns
HS osc mode (-10)
50
—
250
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
200
TCY
DC
ns
TCY = 4/FOSC
2
TCY Instruction Cycle Time (Note 1)
3
TosL, External Clock in (OSC1) High or
50
—
—
ns
XT oscillator
TosH Low Time
2.5
—
—
µs
LP oscillator
15
—
—
ns
HS oscillator
4
TosR, External Clock in (OSC1) Rise or
—
—
25
ns
XT oscillator
TosF Fall Time
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
 1997 Microchip Technology Inc.
DS30234D-page 221
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 20-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 20-1 for load conditions.
TABLE 20-3:
CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
OSC1↑ to CLKOUT↓
—
75
200
ns
Note 1
10*
TosH2ckL
11*
TosH2ckH
OSC1↑ to CLKOUT↑
—
75
200
ns
Note 1
12*
TckR
CLKOUT rise time
—
35
100
ns
Note 1
13*
TckF
CLKOUT fall time
—
35
100
ns
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
—
—
0.5TCY + 20
ns
Note 1
15*
TioV2ckH
Port in valid before CLKOUT ↑
0.25TCY + 25
—
—
ns
Note 1
16*
TckH2ioI
Port in hold after CLKOUT ↑
0
—
—
ns
Note 1
17*
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
—
50
150
ns
18*
TosH2ioI
OSC1↑ (Q2 cycle) to Port
input invalid (I/O in hold time)
PIC16C65
100
—
—
ns
PIC16LC65
200
—
—
ns
19*
TioV2osH
Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TioR
Port output rise time
PIC16C65
—
10
25
ns
PIC16LC65
—
—
60
ns
PIC16C65
—
10
25
ns
PIC16LC65
—
—
60
ns
21*
TioF
Port output fall time
22††*
Tinp
RB0/INT pin high or low time
TCY
—
—
ns
23††*
Trbp
RB7:RB4 change int high or low time
TCY
—
—
ns
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30234D-page 222
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 20-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 20-1 for load conditions.
TABLE 20-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
30*
TmcL
MCLR Pulse Width (low)
100
—
—
ns
VDD = 5V, -40˚C to +85˚C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40˚C to +85˚C
Oscillation Start-up Timer Period
—
1024TOSC
—
—
TOSC = OSC1 period
Power-up Timer Period or WDT
reset
28
72
132
ms
VDD = 5V, -40˚C to +85˚C
I/O Hi-impedance from MCLR Low
—
—
100
ns
*
†
32
Tost
33*
Tpwrt
34
TIOZ
Typ†
Max
Units
Conditions
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 223
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 20-5: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 20-1 for load conditions.
TABLE 20-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
40*
Tt0H
T0CKI High Pulse Width
41*
42*
45*
46*
47*
48
*
†
No Prescaler
Typ†
Max
0.5TCY + 20
—
—
ns
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
10
0.5TCY + 20
10
Tt0P
T0CKI Period
TCY + 40
No Prescaler
With Prescaler Greater of:
20 or TCY + 40
N
Tt1H
T1CKI High Time Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16C6X
15
Prescaler =
PIC16LC6X
25
2,4,8
Asynchronous PIC16C6X
30
PIC16LC6X
50
Tt1L
T1CKI Low Time
Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16C6X
15
Prescaler =
PIC16LC6X
25
2,4,8
Asynchronous PIC16C6X
30
PIC16LC6X
50
Tt1P
T1CKI input period Synchronous PIC16C6X
Greater of:
30 OR TCY + 40
N
Greater of:
PIC16LC6X
50 OR TCY + 40
N
Asynchronous PIC16C6X
60
PIC16LC6X
100
Ft1
Timer1 oscillator input frequency range
DC
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
Tt0L
T0CKI Low Pulse Width
With Prescaler
No Prescaler
With Prescaler
Min
Units Conditions
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4, ..., 256)
Must also meet
parameter 47
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
N = prescale value
(1, 2, 4, 8)
—
—
—
—
—
200
ns
ns
kHz
—
7Tosc
—
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 224
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 20-6: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or
PWM Mode)
53
54
Note: Refer to Figure 20-1 for load conditions.
TABLE 20-6:
Parameter
No.
50*
51*
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Sym Characteristic
TccL CCP1 and CCP2
input low time
TccH CCP1 and CCP2
input high time
Min
No Prescaler
With Prescaler
0.5TCY + 20
—
—
ns
PIC16C65
10
—
—
ns
PIC16LC65
20
—
—
ns
No Prescaler
With Prescaler
PIC16C65
PIC16LC65
*
†
52*
TccP CCP1 and CCP2 input period
53
TccR CCP1 and CCP2 output rise time
54
TccF CCP1 and CCP2 output fall time
Typ† Max Units Conditions
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
3TCY + 40
N
—
—
ns
PIC16C65
—
10
25
ns
PIC16LC65
—
25
45
ns
PIC16C65
—
10
25
ns
PIC16LC65
—
25
45
ns
N = prescale value
(1,4, or 16)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 225
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 20-7: PARALLEL SLAVE PORT TIMING
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 20-1 for load conditions
TABLE 20-7:
Parameter
No.
*
†
PARALLEL SLAVE PORT REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
62
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
20
—
—
ns
63*
TwrH2dtI
PIC16C65
20
—
—
ns
PIC16LC65
35
—
—
ns
WR↑ or CS↑ to data–in invalid (hold
time)
64
TrdL2dtV
RD↓ and CS↓ to data–out valid
—
—
80
ns
65
TrdH2dtI
RD↑ or CS↑ to data–out invalid
10
—
30
ns
Conditions
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 226
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 20-8: SPI MODE TIMING
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
SDO
77
75, 76
SDI
74
73
Note: Refer to Figure 20-1 for load conditions
TABLE 20-8:
Parameter
No.
SPI MODE REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
TCY
—
—
ns
70
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
71
TscH
SCK input high time (slave mode)
TCY + 20
—
—
ns
72
TscL
SCK input low time (slave mode)
TCY + 20
—
—
ns
73
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK
edge
50
—
—
ns
74
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK
edge
50
—
—
ns
75
TdoR
SDO data output rise time
—
10
25
ns
76
TdoF
SDO data output fall time
—
10
25
ns
77
TssH2doZ
SS↑ to SDO output hi-impedance
10
—
50
ns
78
TscR
SCK output rise time (master mode)
—
10
25
ns
79
TscF
SCK output fall time (master mode)
—
10
25
ns
Conditions
80
†
TscH2doV,
SDO data output valid after SCK
—
—
50
ns
TscL2doV
edge
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 227
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 20-9: I2C BUS START/STOP BITS TIMING
SCL
91
93
92
90
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 20-1 for load conditions
TABLE 20-9:
I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
90
TSU:STA
91
THD:STA
92
TSU:STO
93
THD:STO
DS30234D-page 228
Characteristic
START condition
Setup time
START condition
Hold time
STOP condition
Setup time
STOP condition
Hold time
Min
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
4000
600
4700
600
4000
600
Typ Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
Conditions
ns
Only relevant for repeated START
condition
ns
After this period the first clock
pulse is generated
ns
ns
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 20-10:
I2C
BUS DATA TIMING
103
102
100
101
SCL
106
90
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 20-1 for load conditions
TABLE 20-10: I2C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
100
THIGH
Clock high time
101
102
103
TLOW
TR
TF
Clock low time
SDA and SCL rise
time
SDA and SCL fall time
90
TSU:STA
START condition
setup time
91
THD:STA
START condition hold
time
106
THD:DAT
Data input hold time
107
TSU:DAT
Data input setup time
92
TSU:STO
STOP condition setup
time
109
TAA
Output valid from
clock
110
TBUF
Bus free time
Min
Max
Units
Conditions
100 kHz mode
4.0
—
µs
400 kHz mode
0.6
—
µs
Device must operate at a minimum of 1.5 MHz
Devce must operate at a minimum of 10 MHz
SSP Module
100 kHz mode
1.5TCY
4.7
—
—
µs
400 kHz mode
1.3
—
µs
SSP Module
100 kHz mode
400 kHz mode
1.5TCY
—
20 + 0.1Cb
—
1000
300
ns
ns
100 kHz mode
400 kHz mode
—
20 + 0.1Cb
300
300
ns
ns
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
—
—
—
—
0.9
—
—
—
—
3500
—
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
Cb is specified to be from
10-400 pF
Cb is specified to be from
10-400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission
can start
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
tsu;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
 1997 Microchip Technology Inc.
DS30234D-page 229
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 20-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 20-1 for load conditions
TABLE 20-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
120
TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid
PIC16C65
—
—
80
ns
PIC16LC65
—
—
100
ns
121
Tckrf
Clock out rise time and fall time
(Master Mode)
PIC16C65
—
—
45
ns
PIC16LC65
—
—
50
ns
Data out rise time and fall time
PIC16C65
—
—
45
ns
PIC16LC65
—
—
50
ns
122
†:
Tdtrf
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 20-12: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
125
126
Note: Refer to Figure 20-1 for load conditions
TABLE 20-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
125
126
†:
Sym
Characteristic
TdtV2ckL
TckL2dtl
Min
Typ†
Max
Units Conditions
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
—
—
ns
Data hold after CK ↓ (DT hold time)
15
—
—
ns
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 230
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
21.0
ELECTRICAL CHARACTERISTICS FOR PIC16C63/65A
Absolute Maximum Ratings (†)
Ambient temperature under bias............................................................................................................. .-55˚C to +125˚C
Storage temperature ............................................................................................................................... -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ............................................................................................... 0V to +14V
Voltage on RA4 with respect to Vss ................................................................................................................. 0V to +14V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin ............................................................................................................................300 mA
Maximum current into VDD pin ...............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...............................................................................................................±20 mA
Maximum output current sunk by any I/O pin...........................................................................................................25 mA
Maximum output current sourced by any I/O pin .....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined).....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined) ...............................................200 mA
Maximum current sunk by PORTC and PORTD (Note 3) (combined) ...................................................................200 mA
Maximum current sourced by PORTC and PORTD (Note 3) (combined) ..............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
Note 3: PORTD and PORTE not available on the PIC16C63.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 21-1:
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C63-04
PIC16C65A-04
PIC16C63-10
PIC16C65A-10
PIC16C63-20
PIC16C65A-20
PIC16LC63-04
PIC16LC65A-04
JW Devices
RC
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 6.0V
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
XT
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 6.0V
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
HS
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at
5.5V
IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V
OSC
IPD: 1.5 µA typ. at 4.5V IPD 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max.
Freq: 10 MHz max.
Freq: 20 MHz max.
VDD: 4.5V to 5.5V
Not recommended for
use in HS mode
IDD: 20 mA max. at
5.5V
IPD: 1.5 µA typ. at 4.5V
Freq: 20 MHz max.
LP
VDD: 4.0V to 6.0V
VDD: 2.5V to 6.0V
VDD: 2.5V to 6.0V
IDD: 52.5 µA typ.
I
DD: 48 µA max. at 32 IDD: 48 µA max.
Not recommended for
Not recommended for
at 32 kHz, 4.0V
kHz, 3.0V
at 32 kHz, 3.0V
use in LP mode
use in LP mode
IPD: 0.9 µA typ. at 4.0V
IPD: 5 µA max. at 3.0V IPD: 5 µA max. at 3.0V
Freq: 200 kHz max.
Freq: 200 kHz max.
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
 1997 Microchip Technology Inc.
DS30234D-page 231
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
21.1
DC Characteristics:
DC CHARACTERISTICS
Param
No.
Characteristic
PIC16C63/65A-04 (Commercial, Industrial, Extended)
PIC16C63/65A-10 (Commercial, Industrial, Extended)
PIC16C63/65A-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym
Min
Typ† Max Units
Conditions
D001 Supply Voltage
D001A
VDD
4.0
4.5
-
6.0
5.5
V
V
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VDD start voltage to
ensure internal Power-on
Reset signal
VPOR
-
VSS
-
V
D004*
VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
D005
Brown-out Reset Voltage
BVDD
3.7
4.0
4.3
3.7
4.0
4.4
V
D010
Supply Current (Note 2, 5) IDD
-
2.7
5
mA
XT, RC, osc config FOSC = 4 MHz,
VDD = 5.5V (Note 4)
-
10
20
mA
HS osc config FOSC = 20 MHz, VDD = 5.5V
∆IBOR
-
350
425
µA
BOR enabled, VDD = 5.0V
D020 Power-down Current
D021 (Note 3, 5)
D021A
D021B
IPD
-
10.5
1.5
1.5
2.5
42
16
19
19
µA
µA
µA
µA
VDD = 4.0V, WDT enabled,-40°C to +85°C
VDD = 4.0V, WDT disabled,-0°C to +70°C
VDD = 4.0V, WDT disabled,-40°C to +85°C
VDD = 4.0V, WDT disabled,-40°C to +125°C
D023*
∆IBOR
-
350
425
µA
BOR enabled, VDD = 5.0V
D013
D015*
Brown-out Reset Current
(Note 6)
Brown-out Reset Current
(Note 6)
XT, RC and LP osc configuration
HS osc configuration
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
V
BODEN configuration bit is enabled
Extended Range Only
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and
are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
DS30234D-page 232
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
21.2
DC Characteristics:
PIC16LC63/65A-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
D001
D002*
D003
D004*
D005
D010
Characteristic
Supply Voltage
RAM Data Retention
Voltage (Note 1)
VDD start voltage to
ensure internal Power-on
Reset signal
VDD rise rate to ensure
internal Power-on Reset
signal
Brown-out Reset Voltage
Supply Current (Note 2, 5)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym Min Typ† Max Units
Conditions
VDD
VDR
2.5
-
1.5
6.0
-
V
V
LP, XT, RC osc configuration (DC - 4 MHz)
VPOR
-
VSS
-
V
See section on Power-on Reset for details
SVDD
0.05
-
-
BVDD
IDD
3.7
-
4.0
2.0
4.3
3.8
V
mA
BODEN configuration bit is enabled
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
-
22.5
48
µA
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
∆IBOR
-
350
425
µA
BOR enabled, VDD = 5.0V
IPD
-
7.5
0.9
0.9
30
5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D010A
D015*
D020
D021
D021A
Brown-out Reset Current
(Note 6)
Power-down Current
(Note 3, 5)
V/ms See section on Power-on Reset for details
µA BOR enabled, VDD = 5.0V
350 425
Brown-out Reset Current ∆IBOR
(Note 6)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
D023*
 1997 Microchip Technology Inc.
DS30234D-page 233
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
21.3
DC Characteristics:
PIC16C63/65A-04 (Commercial, Industrial, Extended)
PIC16C63/65A-10 (Commercial, Industrial, Extended)
PIC16C63/65A-20 (Commercial, Industrial, Extended)
PIC16LC63/65A-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
D030
D030A
D031
D032
D033
D040
D040A
D041
D042
D042A
D043
D070
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR, OSC1 (in RC mode)
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
with TTL buffer
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 21.1 and
Section 21.2
Sym
Min Typ Max
Units
Conditions
†
VIL
VSS
VSS
VSS
Vss
Vss
VIH
2.0
0.25VDD
+ 0.8V
D060
with Schmitt Trigger buffer
MCLR
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
PORTB weak pull-up current
IPURB
Input Leakage Current (Notes 2, 3)
I/O ports
IIL
D061
D063
MCLR, RA4/T0CKI
OSC1
D080
Output Low Voltage
I/O ports
D080A
D083
OSC2/CLKOUT (RC osc config)
D083A
VOL
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
-
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
VDD
VDD
VDD
VDD
400
V
V
V
V
µA
For entire VDD range
Vss ≤ VPIN ≤ VDD, Pin at hiimpedance
Vss ≤ VPIN ≤ VDD
Vss ≤ VPIN ≤ VDD, XT, HS and
LP osc configuration
0.8VDD 0.8VDD 0.7VDD 0.9VDD 50
250
-
-
±1
µA
-
-
±5
±5
µA
µA
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
Note1
Note1
VDD = 5V, VPIN = VSS
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30234D-page 234
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
DC CHARACTERISTICS
Param
No.
D090
Characteristic
Output High Voltage
I/O ports (Note 3)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 21.1 and
Section 21.2
Sym
Min Typ Max
Units
Conditions
†
VOH
VDD-0.7
-
-
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
-
-
14
V
D100
Open-Drain High Voltage
VOD
Capacitive Loading Specs on Output Pins
OSC2 pin
COSC2
-
-
15
pF
D101
D102
All I/O pins and OSC2 (in RC mode) CIO
Cb
SCL, SDA in I2C mode
-
-
50
400
pF
pF
D090A
D092
OSC2/CLKOUT (RC osc config)
D092A
D150*
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
RA4 pin
In XT, HS and LP modes when
external clock is used to drive
OSC1.
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
 1997 Microchip Technology Inc.
DS30234D-page 235
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
21.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
FIGURE 21-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464Ω
VSS
Note 1: PORTD and PORTE are not implemented on the PIC16C63.
DS30234D-page 236
CL = 50 pF
15 pF
for all pins except OSC2/CLKOUT
but including D and E outputs as ports
for OSC2 output
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
21.5
Timing Diagrams and Specifications
FIGURE 21-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
3
1
3
4
4
2
CLKOUT
TABLE 21-2:
Param
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Fosc
External CLKIN Frequency
(Note 1)
Min
Typ†
Max
Units Conditions
DC
—
4
MHz XT and RC osc mode
DC
—
4
MHz HS osc mode (-04)
DC
—
10
MHz HS osc mode (-10)
DC
—
20
MHz HS osc mode (-20)
DC
—
200
kHz LP osc mode
Oscillator Frequency
DC
—
4
MHz RC osc mode
(Note 1)
0.1
—
4
MHz XT osc mode
4
—
20
MHz HS osc mode
5
—
200
kHz LP osc mode
1
Tosc External CLKIN Period
250
—
—
ns
XT and RC osc mode
(Note 1)
250
—
—
ns
HS osc mode (-04)
100
—
—
ns
HS osc mode (-10)
50
—
—
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
Oscillator Period
250
—
—
ns
RC osc mode
(Note 1)
250
—
10,000
ns
XT osc mode
250
—
250
ns
HS osc mode (-04)
100
—
250
ns
HS osc mode (-10)
50
—
250
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
200
TCY
DC
ns
TCY = 4/FOSC
2
TCY Instruction Cycle Time (Note 1)
3*
TosL, External Clock in (OSC1) High or
100
—
—
ns
XT oscillator
TosH Low Time
2.5
—
—
µs
LP oscillator
15
—
—
ns
HS oscillator
4*
TosR, External Clock in (OSC1) Rise or
—
—
25
ns
XT oscillator
TosF Fall Time
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
 1997 Microchip Technology Inc.
DS30234D-page 237
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 21-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-3:
CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
TosH2ckL
OSC1↑ to CLKOUT↓
—
75
200
ns
Note 1
11*
TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns
Note 1
12*
TckR
CLKOUT rise time
—
35
100
ns
Note 1
13*
TckF
CLKOUT fall time
—
35
100
ns
Note 1
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
15*
TioV2ckH
Port in valid before CLKOUT ↑
16*
TckH2ioI
17*
18*
—
—
0.5TCY + 20
ns
Tosc + 200
—
—
ns
Note 1
Port in hold after CLKOUT ↑
0
—
—
ns
Note 1
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
—
50
150
ns
TosH2ioI
OSC1↑ (Q2 cycle) to Port input
invalid (I/O in hold time)
PIC16C63/65A
100
—
—
ns
PIC16LC63/65A
200
—
—
ns
19*
TioV2osH
Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TioR
Port output rise time
—
10
40
ns
ns
21*
TioF
Port output fall time
PIC16C63/65A
PIC16LC63/65A
—
—
80
PIC16C63/65A
—
10
40
ns
PIC16LC63/65A
—
—
80
ns
22††*
Tinp
INT pin high or low time
TCY
—
—
ns
23††*
Trbp
RB7:RB4 change INT high or low time
TCY
—
—
ns
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30234D-page 238
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 21-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 21-1 for load conditions.
FIGURE 21-5: BROWN-OUT RESET TIMING
BVDD
VDD
TABLE 21-4:
35
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym
Min
Typ†
Max
Units
Conditions
30
TmcL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40˚C to +125˚C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40˚C to +125˚C
32
Tost
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
33*
Tpwrt
Power-up Timer Period
28
72
132
ms
VDD = 5V, -40˚C to +125˚C
34
TIOZ
I/O Hi-impedance from MCLR Low
or WDT reset
—
—
2.1
µs
TBOR
Brown-out Reset Pulse Width
100
—
—
µs
35
*
†
Characteristic
VDD ≤ BVDD (D005)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 239
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 21-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
T0CKI Low Pulse Width
With Prescaler
No Prescaler
With Prescaler
41*
42*
45*
46*
47*
48
*
†
Tt0L
Min
Typ†
Max
0.5TCY + 20
—
—
ns
10
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
0.5TCY + 20
10
Tt0P
T0CKI Period
TCY + 40
No Prescaler
With Prescaler Greater of:
20 or TCY + 40
N
Tt1H
T1CKI High Time Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16C6X
15
Prescaler =
PIC16LC6X
25
2,4,8
Asynchronous PIC16C6X
30
PIC16LC6X
50
Tt1L
T1CKI Low Time
Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16C6X
15
Prescaler =
PIC16LC6X
25
2,4,8
Asynchronous PIC16C6X
30
PIC16LC6X
50
Tt1P
T1CKI input period Synchronous PIC16C6X
Greater of:
30 OR TCY + 40
N
PIC16LC6X
Greater of:
50 OR TCY + 40
N
Asynchronous PIC16C6X
60
PIC16LC6X
100
Ft1
Timer1 oscillator input frequency range
DC
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
Units Conditions
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4, ..., 256)
Must also meet
parameter 47
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
N = prescale value
(1, 2, 4, 8)
—
—
—
—
—
200
ns
ns
kHz
—
7Tosc
—
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 240
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 21-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or
PWM Mode)
54
53
Note: Refer to Figure 21-1 for load conditions.
TABLE 21-6:
Parameter
No.
50*
51*
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Sym Characteristic
TccL CCP1 and CCP2
input low time
TccH CCP1 and CCP2
input high time
Min
No Prescaler
With Prescaler
0.5TCY + 20
*
†
TccP CCP1 and CCP2 input period
53*
TccR CCP1 and CCP2 output rise time
54*
TccF CCP1 and CCP2 output fall time
—
ns
PIC16C63/65A
10
—
—
ns
20
—
—
ns
0.5TCY + 20
—
—
ns
10
—
—
ns
PIC16C63/65A
PIC16LC63/65A
52*
—
PIC16LC63/65A
No Prescaler
With Prescaler
Typ† Max Units Conditions
20
—
—
ns
3TCY + 40
N
—
—
ns
PIC16C63/65A
—
10
25
ns
PIC16LC63/65A
—
25
45
ns
PIC16C63/65A
—
10
25
ns
PIC16LC63/65A
—
25
45
ns
N = prescale value
(1,4, or 16)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 241
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 21-8: PARALLEL SLAVE PORT TIMING (PIC16C65A)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 21-1 for load conditions
TABLE 21-7:
Parameter
No.
62*
63*
64
65*
*
†
PARALLEL SLAVE PORT REQUIREMENTS (PIC16C65A)
Sym
Characteristic
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
TwrH2dtI
TrdL2dtV
TrdH2dtI
WR↑ or CS↑ to data–in invalid (hold
time)
RD↓ and CS↓ to data–out valid
RD↑ or CS↑ to data–out invalid
Min
Typ†
Max
Units
20
—
—
ns
25
—
—
ns
PIC16C65A
20
—
—
ns
PIC16LC65A
35
—
—
ns
—
—
80
ns
—
—
90
ns
10
—
30
ns
Conditions
Extended
Range Only
Extended
Range Only
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 242
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 21-9: SPI MODE TIMING
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
SDO
77
75, 76
SDI
74
73
Note: Refer to Figure 21-1 for load conditions
TABLE 21-8:
Parameter
No.
*
†
SPI MODE REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
TCY
—
—
ns
70*
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
71*
TscH
SCK input high time (slave mode)
TCY + 20
—
—
ns
72*
TscL
SCK input low time (slave mode)
TCY + 20
—
—
ns
73*
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK
edge
50
—
—
ns
74*
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK
edge
50
—
—
ns
75*
TdoR
SDO data output rise time
—
10
25
ns
76*
TdoF
SDO data output fall time
—
10
25
ns
77*
TssH2doZ
SS↑ to SDO output hi-impedance
10
—
50
ns
78*
TscR
SCK output rise time (master mode)
—
10
25
ns
79*
TscF
SCK output fall time (master mode)
—
10
25
ns
80*
TscH2doV,
TscL2doV
SDO data output valid after SCK
edge
—
—
50
ns
Conditions
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 243
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 21-10: I2C BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 21-1 for load conditions
TABLE 21-9:
*
I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
90*
TSU:STA
91*
THD:STA
92*
TSU:STO
93
THD:STO
Characteristic
START condition
Setup time
START condition
Hold time
STOP condition
Setup time
STOP condition
Hold time
Min
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
4000
600
4700
600
4000
600
Typ Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
Conditions
ns
Only relevant for repeated START
condition
ns
After this period the first clock
pulse is generated
ns
ns
These parameters are characterized but not tested.
DS30234D-page 244
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 21-11:
I2C
BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 21-1 for load conditions
TABLE 21-10: I2C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
100*
THIGH
Clock high time
101*
102*
103*
TLOW
TR
TF
Clock low time
SDA and SCL rise
time
SDA and SCL fall time
90*
TSU:STA
91*
THD:STA
106*
THD:DAT
START condition
setup time
START condition hold
time
Data input hold time
107*
TSU:DAT
Data input setup time
92*
TSU:STO
109*
TAA
110*
TBUF
STOP condition setup
time
Output valid from
clock
Bus free time
Min
Max
Units
Conditions
100 kHz mode
4.0
—
µs
400 kHz mode
0.6
—
µs
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
SSP Module
100 kHz mode
1.5TCY
4.7
—
—
µs
400 kHz mode
1.3
—
µs
SSP Module
100 kHz mode
400 kHz mode
1.5TCY
—
20 + 0.1Cb
—
1000
300
ns
ns
100 kHz mode
400 kHz mode
—
20 + 0.1Cb
300
300
ns
ns
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
—
—
—
—
0.9
—
—
—
—
3500
—
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
Cb is specified to be from
10-400 pF
Cb is specified to be from
10-400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can
start
Cb
Bus capacitive loading
—
400
pF
*
These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
 1997 Microchip Technology Inc.
DS30234D-page 245
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 21-12: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 21-1 for load conditions
TABLE 21-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Parameter
No.
120*
Sym
Characteristic
Min
Typ†
TckH2dtV
Max
Units Conditions
SYNC XMIT (MASTER & SLAVE) PIC16C63/65A
Clock high to data out valid
PIC16LC63/65A
—
—
80
ns
—
—
100
ns
121*
Tckrf
Clock out rise time and fall time
(Master Mode)
PIC16C63/65A
—
—
45
ns
PIC16LC63/65A
—
—
50
ns
122*
Tdtrf
Data out rise time and fall time
PIC16C63/65A
—
—
45
ns
PIC16LC63/65A
—
—
50
ns
*
†:
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 21-13: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
125
126
Note: Refer to Figure 21-1 for load conditions
TABLE 21-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
125*
126*
*
†:
Sym
Characteristic
TdtV2ckL
TckL2dtl
Min
Typ†
Max
Units Conditions
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
—
—
ns
Data hold after CK ↓ (DT hold time)
15
—
—
ns
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 246
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
22.0
ELECTRICAL CHARACTERISTICS FOR PIC16CR63/R65
Absolute Maximum Ratings (†)
Ambient temperature under bias............................................................................................................. .-55˚C to +125˚C
Storage temperature ............................................................................................................................... -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ............................................................................................... 0V to +14V
Voltage on RA4 with respect to Vss ................................................................................................................. 0V to +14V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin ............................................................................................................................300 mA
Maximum current into VDD pin ...............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...............................................................................................................±20 mA
Maximum output current sunk by any I/O pin...........................................................................................................25 mA
Maximum output current sourced by any I/O pin .....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined).....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined) ...............................................200 mA
Maximum current sunk by PORTC and PORTD (Note 3) (combined) ...................................................................200 mA
Maximum current sourced by PORTC and PORTD (Note 3) (combined) ..............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
Note 3: PORTD and PORTE not available on the PIC16CR63.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 22-1:
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16CR63-04
PIC16CR65-04
PIC16CR63-10
PIC16CR65-10
PIC16CR63-20
PIC16CR65-20
PIC16LCR63-04
PIC16LCR65-04
JW Devices
RC
VDD: 4.0V to 5.5V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 3.0V to 5.5V
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 5.5V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
XT
VDD: 4.0V to 5.5V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 3.0V to 5.5V
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 5.5V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
HS
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at
5.5V
IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V
OSC
IPD: 1.5 µA typ. at 4.5V IPD 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max.
Freq: 10 MHz max.
Freq: 20 MHz max.
VDD: 4.5V to 5.5V
Not recommended for
use in HS mode
IDD: 20 mA max. at
5.5V
IPD: 1.5 µA typ. at 4.5V
Freq: 20 MHz max.
LP
VDD: 4.0V to 5.5V
VDD: 3.0V to 5.5V
VDD: 3.0V to 5.5V
IDD: 52.5 µA typ.
I
DD: 48 µA max. at 32 IDD: 48 µA max.
Not recommended for
Not recommended for
at 32 kHz, 4.0V
kHz, 3.0V
at 32 kHz, 3.0V
use in LP mode
use in LP mode
IPD: 0.9 µA typ. at 4.0V
IPD: 5 µA max. at 3.0V IPD: 5 µA max. at 3.0V
Freq: 200 kHz max.
Freq: 200 kHz max.
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
 1997 Microchip Technology Inc.
Preliminary
DS30234D-page 247
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
22.1
DC Characteristics:
DC CHARACTERISTICS
Param
No.
Characteristic
PIC16CR63/R65-04 (Commercial, Industrial)
PIC16CR63/R65-10 (Commercial, Industrial)
PIC16CR63/R65-20 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym
Min
Typ† Max Units
Conditions
D001 Supply Voltage
D001A
VDD
4.0
4.5
-
5.5
5.5
V
V
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VDD start voltage to
ensure internal Power-on
Reset signal
VPOR
-
VSS
-
V
D004*
VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
D005
Brown-out Reset Voltage
BVDD
3.7
4.0
4.3
V
BODEN configuration bit is enabled
D010
Supply Current (Note 2, 5) IDD
-
2.7
5
mA
XT, RC, osc config FOSC = 4 MHz,
VDD = 5.5V (Note 4)
-
10
20
mA
HS osc config
FOSC = 20 MHz, VDD = 5.5V
∆IBOR
-
350
425
µA
BOR enabled, VDD = 5.0V
D020 Power-down Current
D021 (Note 3, 5)
D021A
IPD
-
10.5
1.5
1.5
42
16
19
µA
µA
µA
VDD = 4.0V, WDT enabled,-40°C to +85°C
VDD = 4.0V, WDT disabled,-0°C to +70°C
VDD = 4.0V, WDT disabled,-40°C to +85°C
D023*
∆IBOR
-
350
425
µA
BOR enabled, VDD = 5.0V
D013
D015*
Brown-out Reset Current
(Note 6)
Brown-out Reset Current
(Note 6)
XT, RC and LP osc configuration
HS osc configuration
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
DS30234D-page 248
Preliminary
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
22.2
DC Characteristics:
PIC16LCR63/R65-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
D001
D002*
D003
D004*
D005
D010
Characteristic
Supply Voltage
RAM Data Retention
Voltage (Note 1)
VDD start voltage to
ensure internal Power-on
Reset signal
VDD rise rate to ensure
internal Power-on Reset
signal
Brown-out Reset Voltage
Supply Current (Note 2, 5)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym Min Typ† Max Units
Conditions
VDD
VDR
3.0
-
1.5
5.5
-
V
V
LP, XT, RC osc configuration (DC - 4 MHz)
VPOR
-
VSS
-
V
See section on Power-on Reset for details
SVDD
0.05
-
-
BVDD
IDD
3.7
-
4.0
2.0
4.3
3.8
V
mA
BODEN configuration bit is enabled
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
-
22.5
48
µA
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
∆IBOR
-
350
425
µA
BOR enabled, VDD = 5.0V
IPD
-
7.5
0.9
0.9
30
5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D010A
D015*
D020
D021
D021A
Brown-out Reset Current
(Note 6)
Power-down Current
(Note 3, 5)
V/ms See section on Power-on Reset for details
µA BOR enabled, VDD = 5.0V
350 425
Brown-out Reset Current ∆IBOR
(Note 6)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
D023*
 1997 Microchip Technology Inc.
Preliminary
DS30234D-page 249
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
22.3
DC Characteristics:
PIC16CR63/R65-04 (Commercial, Industrial)
PIC16CR63/R65-10 (Commercial, Industrial)
PIC16CR63/R65-20 (Commercial, Industrial)
PIC16LCR63/R65-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
D030
D030A
D031
with Schmitt Trigger buffer
D032
MCLR, OSC1 (in RC mode)
D033
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
D040
with TTL buffer
D040A
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 22.1 and
Section 22.2
Sym
Min Typ Max
Units
Conditions
†
VIL
VSS
VSS
VSS
Vss
Vss
VIH
2.0
0.25VDD
+ 0.8V
D041
with Schmitt Trigger buffer
D042
MCLR
D042A OSC1 (XT, HS and LP)
D043
OSC1 (in RC mode)
D070
PORTB weak pull-up current
IPURB
Input Leakage Current (Notes 2, 3)
D060
I/O ports
IIL
D061
D063
MCLR, RA4/T0CKI
OSC1
D080
Output Low Voltage
I/O ports
D083
OSC2/CLKOUT (RC osc config)
D090
Output High Voltage
I/O ports (Note 3)
D092
OSC2/CLKOUT (RC osc config)
D150*
Open-Drain High Voltage
VOL
VOH
VOD
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
-
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
VDD
VDD
VDD
VDD
400
V
V
V
V
µA
For entire VDD range
Vss ≤ VPIN ≤ VDD, Pin at hiimpedance
Vss ≤ VPIN ≤ VDD
Vss ≤ VPIN ≤ VDD, XT, HS and
LP osc configuration
0.8VDD 0.8VDD 0.7VDD 0.9VDD 50
250
-
-
±1
µA
-
-
±5
±5
µA
µA
-
-
0.6
V
-
-
0.6
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
-
-
14
V
Note1
Note1
VDD = 5V, VPIN = VSS
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
RA4 pin
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30234D-page 250
Preliminary
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
DC CHARACTERISTICS
Param
No.
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 22.1 and
Section 22.2
Sym
Min Typ Max
Units
Conditions
†
D100
Capacitive Loading Specs on Output Pins
OSC2 pin
COSC2
-
-
15
pF
D101
D102
SCL, SDA in I2C mode
All I/O pins and OSC2 (in RC mode) CIO
Cb
-
-
50
400
pF
pF
In XT, HS and LP modes when
external clock is used to drive
OSC1.
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
 1997 Microchip Technology Inc.
Preliminary
DS30234D-page 251
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
22.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
FIGURE 22-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464Ω
VSS
Note 1: PORTD and PORTE are not implemented on the PIC16CR63.
DS30234D-page 252
CL = 50 pF
15 pF
Preliminary
for all pins except OSC2/CLKOUT
but including D and E outputs as ports
for OSC2 output
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
22.5
Timing Diagrams and Specifications
FIGURE 22-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
3
1
3
4
4
2
CLKOUT
TABLE 22-2:
Param
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Fosc
External CLKIN Frequency
(Note 1)
Min
Typ†
Max
Units Conditions
DC
—
4
MHz XT and RC osc mode
DC
—
4
MHz HS osc mode (-04)
DC
—
10
MHz HS osc mode (-10)
DC
—
20
MHz HS osc mode (-20)
DC
—
200
kHz LP osc mode
Oscillator Frequency
DC
—
4
MHz RC osc mode
(Note 1)
0.1
—
4
MHz XT osc mode
4
—
20
MHz HS osc mode
5
—
200
kHz LP osc mode
1
Tosc External CLKIN Period
250
—
—
ns
XT and RC osc mode
(Note 1)
250
—
—
ns
HS osc mode (-04)
100
—
—
ns
HS osc mode (-10)
50
—
—
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
Oscillator Period
250
—
—
ns
RC osc mode
(Note 1)
250
—
10,000
ns
XT osc mode
250
—
250
ns
HS osc mode (-04)
100
—
250
ns
HS osc mode (-10)
50
—
250
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
200
TCY
DC
ns
TCY = 4/FOSC
2
TCY Instruction Cycle Time (Note 1)
3*
TosL, External Clock in (OSC1) High or
100
—
—
ns
XT oscillator
TosH Low Time
2.5
—
—
µs
LP oscillator
15
—
—
ns
HS oscillator
4*
TosR, External Clock in (OSC1) Rise or
—
—
25
ns
XT oscillator
TosF Fall Time
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
 1997 Microchip Technology Inc.
Preliminary
DS30234D-page 253
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 22-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 22-1 for load conditions.
TABLE 22-3:
Param
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
10*
TosH2ckL
11*
12*
TckR
13*
TckF
OSC1↑ to CLKOUT↓
—
75
200
ns
Note 1
TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns
Note 1
CLKOUT rise time
—
35
100
ns
Note 1
CLKOUT fall time
—
35
100
ns
Note 1
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
15*
TioV2ckH
Port in valid before CLKOUT ↑
16*
TckH2ioI
17*
18*
Units Conditions
—
—
0.5TCY + 20
ns
Tosc + 200
—
—
ns
Note 1
Port in hold after CLKOUT ↑
0
—
—
ns
Note 1
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
—
50
150
ns
TosH2ioI
OSC1↑ (Q2 cycle) to Port input
invalid (I/O in hold time)
PIC16CR63/R65
100
—
—
ns
PIC16LCR63/R65
200
—
—
ns
19*
TioV2osH
Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TioR
Port output rise time
PIC16CR63/R65
—
10
40
ns
PIC16LCR63/R65
—
—
80
ns
21*
TioF
Port output fall time
PIC16CR63/R65
—
10
40
ns
PIC16LCR63/R65
—
—
80
ns
22††*
Tinp
INT pin high or low time
TCY
—
—
ns
23††*
Trbp
RB7:RB4 change INT high or low time
TCY
—
—
ns
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30234D-page 254
Preliminary
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 22-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 22-1 for load conditions.
FIGURE 22-5: BROWN-OUT RESET TIMING
BVDD
VDD
TABLE 22-4:
35
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym
Min
Typ†
Max
Units
Conditions
30
TmcL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40˚C to +125˚C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40˚C to +125˚C
32
Tost
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
33*
Tpwrt
Power-up Timer Period
28
72
132
ms
VDD = 5V, -40˚C to +125˚C
34
TIOZ
I/O Hi-impedance from MCLR Low
or WDT reset
—
—
2.1
µs
TBOR
Brown-out Reset Pulse Width
100
—
—
µs
35
*
†
Characteristic
VDD ≤ BVDD (D005)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
Preliminary
DS30234D-page 255
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 22-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 22-1 for load conditions.
TABLE 22-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
T0CKI Low Pulse Width
With Prescaler
No Prescaler
With Prescaler
41*
42*
45*
46*
47*
48
*
†
Tt0L
Min
Typ†
Max
0.5TCY + 20
—
—
ns
10
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
0.5TCY + 20
10
Tt0P
T0CKI Period
TCY + 40
No Prescaler
With Prescaler Greater of:
20 or TCY + 40
N
Tt1H
T1CKI High Time Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16C6X
15
Prescaler =
PIC16LC6X
25
2,4,8
Asynchronous PIC16C6X
30
PIC16LC6X
50
Tt1L
T1CKI Low Time
Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16C6X
15
Prescaler =
PIC16LC6X
25
2,4,8
Asynchronous PIC16C6X
30
PIC16LC6X
50
Tt1P
T1CKI input period Synchronous PIC16C6X
Greater of:
30 OR TCY + 40
N
Greater of:
PIC16LC6X
50 OR TCY + 40
N
Asynchronous PIC16C6X
60
PIC16LC6X
100
Ft1
Timer1 oscillator input frequency range
DC
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
Units Conditions
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4, ..., 256)
Must also meet
parameter 47
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
N = prescale value
(1, 2, 4, 8)
—
—
—
—
—
200
ns
ns
kHz
—
7Tosc
—
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 256
Preliminary
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 22-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or
PWM Mode)
53
54
Note: Refer to Figure 22-1 for load conditions.
TABLE 22-6:
Param
No.
50*
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Sym Characteristic
TccL CCP1 and CCP2
input low time
Min
No Prescaler
With Prescaler
PIC16CR63/R65
PIC16LCR63/R65
51*
TccH CCP1 and CCP2
input high time
52*
TccP CCP1 and CCP2 input period
53*
TccR CCP1 and CCP2 output rise time
54*
*
†
TccF CCP1 and CCP2 output fall time
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
0.5TCY + 20
—
—
ns
PIC16CR63/R65
10
—
—
ns
PIC16LCR63/R65
20
—
—
ns
3TCY + 40
N
—
—
ns
No Prescaler
With Prescaler
Typ† Max Units Conditions
PIC16CR63/R65
—
10
25
ns
PIC16LCR63/R65
—
25
45
ns
PIC16CR63/R65
—
10
25
ns
PIC16LCR63/R65
—
25
45
ns
N = prescale value
(1,4, or 16)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
Preliminary
DS30234D-page 257
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 22-8: PARALLEL SLAVE PORT TIMING (PIC16CR65)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 22-1 for load conditions
TABLE 22-7:
Parameter
No.
*
†
PARALLEL SLAVE PORT REQUIREMENTS (PIC16CR65)
Sym
Characteristic
Min
Typ†
Max
Units
62*
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
20
—
—
ns
63*
TwrH2dtI
PIC16CR65
20
—
—
ns
PIC16LCR65
35
—
—
ns
WR↑ or CS↑ to data–in invalid (hold
time)
64
TrdL2dtV
RD↓ and CS↓ to data–out valid
—
—
80
ns
65*
TrdH2dtI
RD↑ or CS↑ to data–out invalid
10
—
30
ns
Conditions
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 258
Preliminary
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 22-9: SPI MODE TIMING
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
SDO
77
75, 76
SDI
74
73
Note: Refer to Figure 22-1 for load conditions
TABLE 22-8:
Parameter
No.
*
†
SPI MODE REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
TCY
—
—
ns
70*
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
71*
TscH
SCK input high time (slave mode)
TCY + 20
—
—
ns
72*
TscL
SCK input low time (slave mode)
TCY + 20
—
—
ns
73*
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK
edge
50
—
—
ns
74*
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK
edge
50
—
—
ns
75*
TdoR
SDO data output rise time
—
10
25
ns
76*
TdoF
SDO data output fall time
—
10
25
ns
77*
TssH2doZ
SS↑ to SDO output hi-impedance
10
—
50
ns
78*
TscR
SCK output rise time (master mode)
—
10
25
ns
79*
TscF
SCK output fall time (master mode)
—
10
25
ns
80*
TscH2doV,
TscL2doV
SDO data output valid after SCK
edge
—
—
50
ns
Conditions
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
Preliminary
DS30234D-page 259
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 22-10: I2C BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 22-1 for load conditions
TABLE 22-9:
*
I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
90*
TSU:STA
91*
THD:STA
92*
TSU:STO
93
THD:STO
Characteristic
START condition
Setup time
START condition
Hold time
STOP condition
Setup time
STOP condition
Hold time
Min
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
4000
600
4700
600
4000
600
Typ Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
Conditions
ns
Only relevant for repeated START
condition
ns
After this period the first clock
pulse is generated
ns
ns
These parameters are characterized but not tested.
DS30234D-page 260
Preliminary
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 22-11:
I2C
BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 22-1 for load conditions
TABLE 22-10: I2C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
100*
THIGH
Clock high time
101*
102*
103*
TLOW
TR
TF
Clock low time
SDA and SCL rise
time
SDA and SCL fall time
90*
TSU:STA
91*
THD:STA
106*
THD:DAT
START condition
setup time
START condition hold
time
Data input hold time
107*
TSU:DAT
Data input setup time
92*
TSU:STO
109*
TAA
110*
TBUF
STOP condition setup
time
Output valid from
clock
Bus free time
Min
Max
Units
Conditions
100 kHz mode
4.0
—
µs
400 kHz mode
0.6
—
µs
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
SSP Module
100 kHz mode
1.5TCY
4.7
—
—
µs
400 kHz mode
1.3
—
µs
SSP Module
100 kHz mode
400 kHz mode
1.5TCY
—
20 + 0.1Cb
—
1000
300
ns
ns
100 kHz mode
400 kHz mode
—
20 + 0.1Cb
300
300
ns
ns
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
—
—
—
—
0.9
—
—
—
—
3500
—
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
Cb is specified to be from
10-400 pF
Cb is specified to be from
10-400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can
start
Cb
Bus capacitive loading
—
400
pF
*
These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
 1997 Microchip Technology Inc.
Preliminary
DS30234D-page 261
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 22-12: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 22-1 for load conditions
TABLE 22-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Sym
Characteristic
120*
TckH2dtV
121*
Tckrf
122*
*
†:
Tdtrf
Min
Typ†
Max
Units Conditions
SYNC XMIT (MASTER & SLAVE) PIC16CR63/R65
Clock high to data out valid
PIC16LCR63/R65
—
—
80
ns
—
—
100
ns
Clock out rise time and fall time
(Master Mode)
PIC16CR63/R65
—
—
45
ns
PIC16LCR63/R65
—
—
50
ns
Data out rise time and fall time
PIC16CR63/R65
—
—
45
ns
PIC16LCR63/R65
—
—
50
ns
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 22-13: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
125
126
Note: Refer to Figure 22-1 for load conditions
TABLE 22-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
*
†:
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125*
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
—
—
ns
126*
TckL2dtl
Data hold after CK ↓ (DT hold time)
15
—
—
ns
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 262
Preliminary
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
23.0
ELECTRICAL CHARACTERISTICS FOR PIC16C66/67
Absolute Maximum Ratings (†)
Ambient temperature under bias............................................................................................................. .-55˚C to +125˚C
Storage temperature ............................................................................................................................... -65˚C to +150˚C
Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ..........................................-0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +7.5V
Voltage on MCLR with respect to VSS (Note 2) ............................................................................................... 0V to +14V
Voltage on RA4 with respect to Vss ................................................................................................................. 0V to +14V
Total power dissipation (Note 1).................................................................................................................................1.0W
Maximum current out of VSS pin ............................................................................................................................300 mA
Maximum current into VDD pin ...............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD) ......................................................................................................................±20 mA
Output clamp current, IOK (VO < 0 or VO > VDD)...............................................................................................................±20 mA
Maximum output current sunk by any I/O pin...........................................................................................................25 mA
Maximum output current sourced by any I/O pin .....................................................................................................25 mA
Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined).....................................................200 mA
Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined) ...............................................200 mA
Maximum current sunk by PORTC and PORTD (Note 3) (combined) ...................................................................200 mA
Maximum current sourced by PORTC and PORTD (Note 3) (combined) ..............................................................200 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up.
Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather
than pulling this pin directly to VSS.
Note 3: PORTD and PORTE not available on the PIC16C66.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 23-1:
CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS
AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)
PIC16C66-04
PIC16C67-04
PIC16C66-10
PIC16C67-10
PIC16C66-20
PIC16C67-20
PIC16LC66-04
PIC16LC67-04
JW Devices
RC
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 6.0V
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
XT
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 4.5V to 5.5V
IDD: 2.7 mA typ. at 5.5V
IPD: 1.5 µA typ. at 4V
Freq: 4 MHz max.
VDD: 2.5V to 6.0V
IDD: 3.8 mA max. at 3V
IPD: 5 µA max. at 3V
Freq: 4 MHz max.
VDD: 4.0V to 6.0V
IDD: 5 mA max. at 5.5V
IPD: 16 µA max. at 4V
Freq: 4 MHz max.
HS
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
VDD: 4.5V to 5.5V
IDD: 13.5 mA typ. at
5.5V
IDD: 10 mA max. at 5.5V IDD: 20 mA max. at 5.5V
OSC
IPD: 1.5 µA typ. at 4.5V IPD 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V
Freq: 4 MHz max.
Freq: 10 MHz max.
Freq: 20 MHz max.
VDD: 4.5V to 5.5V
Not recommended for
use in HS mode
IDD: 20 mA max. at
5.5V
IPD: 1.5 µA typ. at 4.5V
Freq: 20 MHz max.
LP
VDD: 4.0V to 6.0V
VDD: 2.5V to 6.0V
VDD: 2.5V to 6.0V
IDD: 52.5 µA typ.
I
DD: 48 µA max. at 32 IDD: 48 µA max.
Not recommended for
Not recommended for
at 32 kHz, 4.0V
kHz, 3.0V
at 32 kHz, 3.0V
use in LP mode
use in LP mode
IPD: 0.9 µA typ. at 4.0V
IPD: 5 µA max. at 3.0V IPD: 5 µA max. at 3.0V
Freq: 200 kHz max.
Freq: 200 kHz max.
Freq: 200 kHz max.
The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recommended that the user select the device type that ensures the specifications required.
 1997 Microchip Technology Inc.
DS30234D-page 263
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
23.1
DC Characteristics:
DC CHARACTERISTICS
Param
No.
Characteristic
PIC16C66/67-04 (Commercial, Industrial, Extended)
PIC16C66/67-10 (Commercial, Industrial, Extended)
PIC16C66/67-20 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym
Min
Typ† Max Units
Conditions
D001 Supply Voltage
D001A
VDD
4.0
4.5
-
6.0
5.5
V
V
D002*
RAM Data Retention
Voltage (Note 1)
VDR
-
1.5
-
V
D003
VDD start voltage to
ensure internal Power-on
Reset signal
VPOR
-
VSS
-
V
D004*
VDD rise rate to ensure
internal Power-on Reset
signal
SVDD
0.05
-
-
D005
Brown-out Reset Voltage
BVDD
3.7
4.0
4.3
3.7
4.0
4.4
V
D010
Supply Current (Note 2, 5) IDD
-
2.7
5
mA
XT, RC, osc config FOSC = 4 MHz, VDD = 5.5V
(Note 4)
-
10
20
mA
HS osc config
FOSC = 20 MHz, VDD = 5.5V
∆IBOR
-
350
425
µA
BOR enabled, VDD = 5.0V
D020 Power-down Current
D021 (Note 3, 5)
D021A
D021B
IPD
-
10.5
1.5
1.5
2.5
42
16
19
19
µA
µA
µA
µA
VDD = 4.0V, WDT enabled,-40°C to +85°C
VDD = 4.0V, WDT disabled,-0°C to +70°C
VDD = 4.0V, WDT disabled,-40°C to +85°C
VDD = 4.0V, WDT disabled,-40°C to +125°C
D023*
∆IBOR
-
350
425
µA
BOR enabled, VDD = 5.0V
D013
D015*
Brown-out Reset Current
(Note 6)
Brown-out Reset Current
(Note 6)
XT, RC and LP osc configuration
HS osc configuration
See section on Power-on Reset for details
V/ms See section on Power-on Reset for details
V
BODEN configuration bit is enabled
Extended Range Only
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
DS30234D-page 264
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
23.2
DC Characteristics:
PIC16LC66/67-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
D001
D002*
D003
D004*
D005
D010
Characteristic
Supply Voltage
RAM Data Retention
Voltage (Note 1)
VDD start voltage to
ensure internal Power-on
Reset signal
VDD rise rate to ensure
internal Power-on Reset
signal
Brown-out Reset Voltage
Supply Current (Note 2, 5)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40˚C
≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Sym Min Typ† Max Units
Conditions
VDD
VDR
2.5
-
1.5
6.0
-
V
V
LP, XT, RC osc configuration (DC - 4 MHz)
VPOR
-
VSS
-
V
See section on Power-on Reset for details
SVDD
0.05
-
-
BVDD
IDD
3.7
-
4.0
2.0
4.3
3.8
V
mA
BODEN configuration bit is enabled
XT, RC osc configuration
FOSC = 4 MHz, VDD = 3.0V (Note 4)
-
22.5
48
µA
LP osc configuration
FOSC = 32 kHz, VDD = 3.0V, WDT disabled
∆IBOR
-
350
425
µA
BOR enabled, VDD = 5.0V
IPD
-
7.5
0.9
0.9
30
5
5
µA
µA
µA
VDD = 3.0V, WDT enabled, -40°C to +85°C
VDD = 3.0V, WDT disabled, 0°C to +70°C
VDD = 3.0V, WDT disabled, -40°C to +85°C
D010A
D015*
D020
D021
D021A
Brown-out Reset Current
(Note 6)
Power-down Current
(Note 3, 5)
V/ms See section on Power-on Reset for details
µA BOR enabled, VDD = 5.0V
350 425
Brown-out Reset Current ∆IBOR
(Note 6)
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.
4: For RC osc configuration, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm.
5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from characterization and is for design guidance only. This is not tested.
6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
D023*
 1997 Microchip Technology Inc.
DS30234D-page 265
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
23.3
DC Characteristics:
PIC16C66/67-04 (Commercial, Industrial, Extended)
PIC16C66/67-10 (Commercial, Industrial, Extended)
PIC16C66/67-20 (Commercial, Industrial, Extended)
PIC16LC66/67-04 (Commercial, Industrial)
DC CHARACTERISTICS
Param
No.
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
D030
D030A
D031
with Schmitt Trigger buffer
D032
MCLR, OSC1 (in RC mode)
D033
OSC1 (in XT, HS and LP)
Input High Voltage
I/O ports
D040
with TTL buffer
D040A
D041
D042
D042A
D043
D070
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 23.1 and
Section 23.2
Sym
Min Typ Max
Units
Conditions
†
VIL
VSS
VSS
VSS
Vss
Vss
VIH
2.0
0.25VDD
+ 0.8V
D060
with Schmitt Trigger buffer
MCLR
OSC1 (XT, HS and LP)
OSC1 (in RC mode)
PORTB weak pull-up current
IPURB
Input Leakage Current (Notes 2, 3)
I/O ports
IIL
D061
D063
MCLR, RA4/T0CKI
OSC1
D080
Output Low Voltage
I/O ports
D080A
D083
OSC2/CLKOUT (RC osc config)
D083A
VOL
-
0.15VDD
0.8V
0.2VDD
0.2VDD
0.3VDD
V
V
V
V
V
For entire VDD range
4.5V ≤ VDD ≤ 5.5V
-
VDD
VDD
V
V
4.5V ≤ VDD ≤ 5.5V
For entire VDD range
VDD
VDD
VDD
VDD
400
V
V
V
V
µA
For entire VDD range
Vss ≤ VPIN ≤ VDD, Pin at hiimpedance
Vss ≤ VPIN ≤ VDD
Vss ≤ VPIN ≤ VDD, XT, HS and
LP osc configuration
0.8VDD 0.8VDD 0.7VDD 0.9VDD 50
250
-
-
±1
µA
-
-
±5
±5
µA
µA
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
-
-
0.6
V
Note1
Note1
VDD = 5V, VPIN = VSS
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 7.0 mA, VDD = 4.5V,
-40°C to +125°C
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +85°C
IOL = 1.2 mA, VDD = 4.5V,
-40°C to +125°C
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS30234D-page 266
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
DC CHARACTERISTICS
Param
No.
D090
Characteristic
Output High Voltage
I/O ports (Note 3)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40˚C ≤ TA ≤ +125˚C for extended,
-40˚C ≤ TA ≤ +85˚C for industrial and
0˚C
≤ TA ≤ +70˚C for commercial
Operating voltage VDD range as described in DC spec Section 23.1 and
Section 23.2
Sym
Min Typ Max
Units
Conditions
†
VOH
VDD-0.7
-
-
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
VDD-0.7
-
-
V
-
-
14
V
D100
Open-Drain High Voltage
VOD
Capacitive Loading Specs on Output Pins
OSC2 pin
COSC2
-
-
15
pF
D101
D102
All I/O pins and OSC2 (in RC mode) CIO
Cb
SCL, SDA in I2C mode
-
-
50
400
pF
pF
D090A
D092
OSC2/CLKOUT (RC osc config)
D092A
D150*
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -2.5 mA, VDD = 4.5V,
-40°C to +125°C
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +85°C
IOH = -1.0 mA, VDD = 4.5V,
-40°C to +125°C
RA4 pin
In XT, HS and LP modes when
external clock is used to drive
OSC1.
*
†
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the
PIC16C6X be driven with external clock in RC mode.
2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
 1997 Microchip Technology Inc.
DS30234D-page 267
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
23.4
Timing Parameter Symbology
The timing parameter symbols have been created following one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
FIGURE 23-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464Ω
VSS
Note 1: PORTD and PORTE are not implemented on the PIC16C66.
DS30234D-page 268
CL = 50 pF
15 pF
for all pins except OSC2/CLKOUT
but including D and E outputs as ports
for OSC2 output
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
23.5
Timing Diagrams and Specifications
FIGURE 23-2: EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
3
1
3
4
4
2
CLKOUT
TABLE 23-2:
Param
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Fosc
External CLKIN Frequency
(Note 1)
Min
Typ†
Max
Units Conditions
DC
—
4
MHz XT and RC osc mode
DC
—
4
MHz HS osc mode (-04)
DC
—
10
MHz HS osc mode (-10)
DC
—
20
MHz HS osc mode (-20)
DC
—
200
kHz LP osc mode
Oscillator Frequency
DC
—
4
MHz RC osc mode
(Note 1)
0.1
—
4
MHz XT osc mode
4
—
20
MHz HS osc mode
5
—
200
kHz LP osc mode
1
Tosc External CLKIN Period
250
—
—
ns
XT and RC osc mode
(Note 1)
250
—
—
ns
HS osc mode (-04)
100
—
—
ns
HS osc mode (-10)
50
—
—
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
Oscillator Period
250
—
—
ns
RC osc mode
(Note 1)
250
—
10,000
ns
XT osc mode
250
—
250
ns
HS osc mode (-04)
100
—
250
ns
HS osc mode (-10)
50
—
250
ns
HS osc mode (-20)
5
—
—
µs
LP osc mode
200
TCY
DC
ns
TCY = 4/FOSC
2
TCY Instruction Cycle Time (Note 1)
3*
TosL, External Clock in (OSC1) High or
100
—
—
ns
XT oscillator
TosH Low Time
2.5
—
—
µs
LP oscillator
15
—
—
ns
HS oscillator
4*
TosR, External Clock in (OSC1) Rise or
—
—
25
ns
XT oscillator
TosF Fall Time
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing code.
Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin.
When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.
 1997 Microchip Technology Inc.
DS30234D-page 269
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 23-3: CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note: Refer to Figure 23-1 for load conditions.
TABLE 23-3:
CLKOUT AND I/O TIMING REQUIREMENTS
Parameter Sym
No.
Characteristic
Min
Typ†
Max
Units Conditions
10*
TosH2ckL
OSC1↑ to CLKOUT↓
—
75
200
ns
Note 1
11*
TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns
Note 1
12*
TckR
CLKOUT rise time
—
35
100
ns
Note 1
13*
TckF
CLKOUT fall time
—
35
100
ns
Note 1
Note 1
14*
TckL2ioV
CLKOUT ↓ to Port out valid
15*
TioV2ckH
Port in valid before CLKOUT ↑
16*
TckH2ioI
17*
18*
—
—
0.5TCY + 20
ns
Tosc + 200
—
—
ns
Note 1
Port in hold after CLKOUT ↑
0
—
—
ns
Note 1
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
—
50
150
ns
TosH2ioI
OSC1↑ (Q2 cycle) to Port input
invalid (I/O in hold time)
PIC16C66/67
100
—
—
ns
PIC16LC66/67
200
—
—
ns
19*
TioV2osH
Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TioR
Port output rise time
PIC16C66/67
—
10
40
ns
PIC16LC66/67
—
—
80
ns
21*
TioF
Port output fall time
PIC16C66/67
—
10
40
ns
PIC16LC66/67
—
—
80
ns
22††*
Tinp
INT pin high or low time
TCY
—
—
ns
23††*
Trbp
RB7:RB4 change INT high or low time
TCY
—
—
ns
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
†† These parameters are asynchronous events not related to any internal clock edge.
Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x TOSC.
DS30234D-page 270
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 23-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
Note: Refer to Figure 23-1 for load conditions.
FIGURE 23-5: BROWN-OUT RESET TIMING
BVDD
VDD
TABLE 23-4:
35
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Parameter
No.
Sym
Min
Typ†
Max
Units
Conditions
30
TmcL
MCLR Pulse Width (low)
2
—
—
µs
VDD = 5V, -40˚C to +125˚C
31*
Twdt
Watchdog Timer Time-out Period
(No Prescaler)
7
18
33
ms
VDD = 5V, -40˚C to +125˚C
32
Tost
Oscillation Start-up Timer Period
—
1024 TOSC
—
—
TOSC = OSC1 period
33*
Tpwrt
Power-up Timer Period
28
72
132
ms
VDD = 5V, -40˚C to +125˚C
34
TIOZ
I/O Hi-impedance from MCLR Low
or WDT reset
—
—
2.1
µs
TBOR
Brown-out Reset Pulse Width
100
—
—
µs
35
*
†
Characteristic
VDD ≤ BVDD (D005)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 271
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 23-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RC0/T1OSO/T1CKI
46
45
47
48
TMR0 or
TMR1
Note: Refer to Figure 23-1 for load conditions.
TABLE 23-5:
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
Sym
Characteristic
40*
Tt0H
T0CKI High Pulse Width
No Prescaler
T0CKI Low Pulse Width
With Prescaler
No Prescaler
With Prescaler
41*
42*
45*
46*
47*
48
*
†
Tt0L
Min
Typ†
Max
0.5TCY + 20
—
—
ns
10
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
ns
ns
ns
0.5TCY + 20
10
Tt0P
T0CKI Period
TCY + 40
No Prescaler
With Prescaler Greater of:
20 or TCY + 40
N
Tt1H
T1CKI High Time Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16C6X
15
Prescaler =
PIC16LC6X
25
2,4,8
Asynchronous PIC16C6X
30
PIC16LC6X
50
Tt1L
T1CKI Low Time
Synchronous, Prescaler = 1
0.5TCY + 20
Synchronous, PIC16C6X
15
Prescaler =
PIC16LC6X
25
2,4,8
Asynchronous PIC16C6X
30
PIC16LC6X
50
Tt1P
T1CKI input period Synchronous PIC16C6X
Greater of:
30 OR TCY + 40
N
Greater of:
PIC16LC6X
50 OR TCY + 40
N
Asynchronous PIC16C6X
60
PIC16LC6X
100
Ft1
Timer1 oscillator input frequency range
DC
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
2Tosc
Units Conditions
Must also meet
parameter 42
Must also meet
parameter 42
N = prescale value
(2, 4, ..., 256)
Must also meet
parameter 47
Must also meet
parameter 47
N = prescale value
(1, 2, 4, 8)
N = prescale value
(1, 2, 4, 8)
—
—
—
—
—
200
ns
ns
kHz
—
7Tosc
—
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 272
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 23-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2
and RC2/CCP1
(Capture Mode)
50
51
52
RC1/T1OSI/CCP2
and RC2/CCP1
(Compare or
PWM Mode)
54
53
Note: Refer to Figure 23-1 for load conditions.
TABLE 23-6:
Parameter
No.
50*
51*
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Sym Characteristic
TccL CCP1 and CCP2
input low time
TccH CCP1 and CCP2
input high time
Min
No Prescaler
With Prescaler
0.5TCY + 20
—
—
ns
PIC16C66/67
10
—
—
ns
PIC16LC66/67
20
—
—
ns
No Prescaler
With Prescaler
PIC16C66/67
PIC16LC66/67
*
†
52*
TccP CCP1 and CCP2 input period
53*
TccR CCP1 and CCP2 output rise time
54*
TccF CCP1 and CCP2 output fall time
Typ† Max Units Conditions
0.5TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
3TCY + 40
N
—
—
ns
PIC16C66/67
—
10
25
ns
PIC16LC66/67
—
25
45
ns
PIC16C66/67
—
10
25
ns
PIC16LC66/67
—
25
45
ns
N = prescale value
(1,4, or 16)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 273
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 23-8: PARALLEL SLAVE PORT TIMING (PIC16C67)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 23-1 for load conditions
TABLE 23-7:
Parameter
No.
62*
63*
64
65*
*
†
PARALLEL SLAVE PORT REQUIREMENTS (PIC16C67)
Sym
Characteristic
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
TwrH2dtI
TrdL2dtV
TrdH2dtI
WR↑ or CS↑ to data–in invalid (hold
time)
RD↓ and CS↓ to data–out valid
RD↑ or CS↑ to data–out invalid
Min
Typ†
Max
Units
20
—
—
ns
25
—
—
ns
PIC16C67
20
—
—
ns
PIC16LC67
35
—
—
ns
—
—
80
ns
—
—
90
ns
10
—
30
ns
Conditions
Extended
Range Only
Extended
Range Only
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 274
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 23-9: SPI MASTER MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
BIT6 - - - - - -1
MSB
SDO
LSB
75, 76
SDI
MSB IN
BIT6 - - - -1
LSB IN
74
73
Refer to Figure 23-1 for load conditions.
FIGURE 23-10: SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
BIT6 - - - - - -1
MSB
LSB
75, 76
SDI
MSB IN
BIT6 - - - -1
LSB IN
74
Refer to Figure 23-1 for load conditions.
 1997 Microchip Technology Inc.
DS30234D-page 275
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 23-11: SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
MSB
SDO
LSB
BIT6 - - - - - -1
77
75, 76
SDI
MSB IN
BIT6 - - - -1
LSB IN
74
73
Refer to Figure 23-1 for load conditions.
FIGURE 23-12: SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
SDO
MSB
BIT6 - - - - - -1
LSB
75, 76
SDI
MSB IN
77
BIT6 - - - -1
LSB IN
74
Refer to Figure 23-1 for load conditions.
DS30234D-page 276
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
TABLE 23-8:
Parameter
No.
70*
71*
72*
73*
74*
75*
76*
77*
78*
79*
80*
81*
82*
SPI MODE REQUIREMENTS
Sym
TssL2scH,
TssL2scL
TscH
TscL
TdiV2scH,
TdiV2scL
TscH2diL,
TscL2diL
TdoR
TdoF
TssH2doZ
TscR
TscF
TscH2doV,
TscL2doV
TdoV2scH,
TdoV2scL
TssL2doV
83*
*
†
Characteristic
Min
Typ†
Max
Units
SS↓ to SCK↓ or SCK↑ input
TCY
—
—
ns
—
—
—
—
—
—
ns
ns
ns
—
—
ns
10
10
—
10
10
—
25
25
50
25
25
50
ns
ns
ns
ns
ns
ns
—
—
ns
—
50
ns
SCK input high time (slave mode)
TCY + 20
SCK input low time (slave mode)
TCY + 20
Setup time of SDI data input to SCK
100
edge
Hold time of SDI data input to SCK
100
edge
SDO data output rise time
—
SDO data output fall time
—
SS↑ to SDO output hi-impedance
10
SCK output rise time (master mode)
—
SCK output fall time (master mode)
—
SDO data output valid after SCK
—
edge
SDO data output setup to SCK
TCY
edge
SDO data output valid after SS↓
—
edge
SS ↑ after SCK edge
1.5TCY + 40
Conditions
TscH2ssH,
—
—
ns
TscL2ssH
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not
tested.
 1997 Microchip Technology Inc.
DS30234D-page 277
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 23-13: I2C BUS START/STOP BITS TIMING
SCL
91
93
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 23-1 for load conditions
TABLE 23-9:
*
I2C BUS START/STOP BITS REQUIREMENTS
Parameter
No.
Sym
90*
TSU:STA
91*
THD:STA
92*
TSU:STO
93
THD:STO
Characteristic
START condition
Setup time
START condition
Hold time
STOP condition
Setup time
STOP condition
Hold time
Min
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4700
600
4000
600
4700
600
4000
600
Typ Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
Conditions
ns
Only relevant for repeated START
condition
ns
After this period the first clock
pulse is generated
ns
ns
These parameters are characterized but not tested.
DS30234D-page 278
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 23-14:
I2C
BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
110
109
109
SDA
Out
Note: Refer to Figure 23-1 for load conditions
TABLE 23-10: I2C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
100*
THIGH
Clock high time
101*
102*
103*
TLOW
TR
TF
Clock low time
SDA and SCL rise
time
SDA and SCL fall time
90*
TSU:STA
91*
THD:STA
106*
THD:DAT
START condition
setup time
START condition hold
time
Data input hold time
107*
TSU:DAT
Data input setup time
92*
TSU:STO
109*
TAA
110*
TBUF
STOP condition setup
time
Output valid from
clock
Bus free time
Min
Max
Units
Conditions
100 kHz mode
4.0
—
µs
400 kHz mode
0.6
—
µs
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
SSP Module
100 kHz mode
1.5TCY
4.7
—
—
µs
400 kHz mode
1.3
—
µs
SSP Module
100 kHz mode
400 kHz mode
1.5TCY
—
20 + 0.1Cb
—
1000
300
ns
ns
100 kHz mode
400 kHz mode
—
20 + 0.1Cb
300
300
ns
ns
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
—
—
4.7
1.3
—
—
—
—
—
0.9
—
—
—
—
3500
—
—
—
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Device must operate at a minimum of 1.5 MHz
Device must operate at a minimum of 10 MHz
Cb is specified to be from
10-400 pF
Cb is specified to be from
10-400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission can
start
Cb
Bus capacitive loading
—
400
pF
*
These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement
Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is
released.
 1997 Microchip Technology Inc.
DS30234D-page 279
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 23-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
121
121
RC7/RX/DT
pin
120
122
Note: Refer to Figure 23-1 for load conditions
TABLE 23-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Parameter
No.
Sym
Characteristic
120*
TckH2dtV
SYNC XMIT (MASTER & SLAVE) PIC16C66/67
Clock high to data out valid
PIC16LC66/67
121*
Tckrf
Clock out rise time and fall time
(Master Mode)
PIC16C66/67
Data out rise time and fall time
122*
*
†:
Tdtrf
Min
Typ†
Max
Units Conditions
—
—
80
ns
—
—
100
ns
—
—
45
ns
PIC16LC66/67
—
—
50
ns
PIC16C66/67
—
—
45
ns
PIC16LC66/67
—
—
50
ns
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 23-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
RC6/TX/CK
pin
RC7/RX/DT
pin
125
126
Note: Refer to Figure 23-1 for load conditions
TABLE 23-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter
No.
*
†:
Sym
Characteristic
Min
Typ†
Max
Units Conditions
125*
TdtV2ckL
SYNC RCV (MASTER & SLAVE)
Data setup before CK ↓ (DT setup time)
15
—
—
ns
126*
TckL2dtl
Data hold after CK ↓ (DT hold time)
15
—
—
ns
These parameters are characterized but not tested.
Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
DS30234D-page 280
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
24.0
DC AND AC CHARACTERISTICS GRAPHS AND TABLES FOR:
PIC16C62, PIC16C62A, PIC16CR62, PIC16C63, PIC16C64, PIC16C64A,
PIC16CR64, PIC16C65A, PIC16C66, PIC16C67
The graphs and tables provided in this section are for design guidance and are not tested or guaranteed.
In some graphs or tables the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are guaranteed to operate properly only within the specified
range.
Note:
The data presented in this section is a statistical summary of data collected on units from different lots over
a period of time and matrix samples. 'Typical' represents the mean of the distribution at, 25°C, while 'max'
or 'min' represents (mean +3σ) and (mean -3σ) respectively where σ is standard deviation.
FIGURE 24-1: TYPICAL IPD vs. VDD (WDT DISABLED, RC MODE)
35
30
IPD(nA)
25
20
15
10
5
0
2.5
3.0
3.5
4.0
4.5
VDD(Volts)
5.0
5.5
6.0
FIGURE 24-2: MAXIMUM IPD vs. VDD (WDT DISABLED, RC MODE)
10.000
85°C
70°C
IPD(µA)
1.000
25°C
0.100
0°C
-40°C
0.010
0.001
2.5
 1997 Microchip Technology Inc.
3.0
3.5
4.0
4.5
VDD(Volts)
5.0
5.5
6.0
DS30234D-page 281
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 24-3: TYPICAL IPD vs. VDD @ 25°C
(WDT ENABLED, RC MODE)
FIGURE 24-5: TYPICAL RC OSCILLATOR
FREQUENCY vs. VDD
Cext = 22 pF, T = 25°C
6.0
25
5.5
5.0
4.5
Fosc(MHz)
IPD(µA)
20
15
10
R = 5k
4.0
3.5
3.0
R = 10k
2.5
2.0
5
1.5
1.0
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.0
2.5
VDD(Volts)
FIGURE 24-4: MAXIMUM IPD vs. VDD (WDT
ENABLED, RC MODE)
35
3.0
3.5
4.0
4.5
VDD(Volts)
5.0
0°C
Cext = 100 pF, T = 25°C
2.4
2.2
R = 3.3k
2.0
20
1.8
70°C
Fosc(MHz)
IPD(µA)
6.0
Shaded area is beyond recommended range.
25
15
85°C
10
5
1.6
R = 5k
1.4
1.2
1.0
R = 10k
0.8
0.6
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.4
6.0
R = 100k
0.2
VDD(Volts)
0.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD(Volts)
FIGURE 24-7: TYPICAL RC OSCILLATOR
FREQUENCY vs. VDD
Cext = 300 pF, T = 25°C
1000
900
800
Fosc(kHz)
Data based on matrix samples. See first page of this section for details.
5.5
FIGURE 24-6: TYPICAL RC OSCILLATOR
FREQUENCY vs. VDD
-40°C
30
R = 100k
0.5
6.0
R = 3.3k
700
600
R = 5k
500
400
R = 10k
300
200
R = 100k
100
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD(Volts)
DS30234D-page 282
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 24-8: TYPICAL IPD vs. VDD BROWNOUT DETECT ENABLED (RC
MODE)
FIGURE 24-10: TYPICAL IPD vs. TIMER1
ENABLED (32 kHz, RC0/RC1
= 33 pF/33 pF, RC MODE)
1400
1200
30
25
Device NOT in
Brown-out Reset
800
20
600
400
200
0
2.5
IPD(µA)
IPD(µA)
1000
Device in
Brown-out
Reset
15
10
3.0
3.5
4.0
4.5
VDD(Volts)
5.0
5.5
5
6.0
0
2.5
The shaded region represents the built-in hysteresis of the
brown-out reset circuitry.
FIGURE 24-9: MAXIMUM IPD vs. VDD
BROWN-OUT DETECT
ENABLED
(85°C TO -40°C, RC MODE)
3.0
3.5
4.0
4.5
VDD(Volts)
5.0
5.5
6.0
FIGURE 24-11: MAXIMUM IPD vs. TIMER1
ENABLED
(32 kHz, RC0/RC1 = 33 pF/33
pF, 85°C TO -40°C, RC MODE)
1600
1400
1200
45
40
Device NOT in
Brown-out Reset
800
35
30
400
Device in
Brown-out
Reset
20
15
200
4.3
0
2.5
25
3.0
3.5
4.0
4.5
VDD(Volts)
10
5.0
5.5
6.0
The shaded region represents the built-in hysteresis of the
brown-out reset circuitry.
 1997 Microchip Technology Inc.
5
0
2.5
3.0
3.5
4.0
4.5
VDD(Volts)
5.0
5.5
6.0
DS30234D-page 283
Data based on matrix samples. See first page of this section for details.
600
IPD(µA)
IPD(µA)
1000
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 24-12: TYPICAL IDD vs. FREQUENCY (RC MODE @ 22 pF, 25°C)
2000
6.0V
1800
5.5V
5.0V
1600
4.5V
IDD(µA)
1400
4.0V
1200
3.5V
1000
3.0V
800
2.5V
600
400
200
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Frequency(MHz)
3.5
4.0
4.5
Shaded area is
beyond recommended range
FIGURE 24-13: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 22 pF, -40°C TO 85°C)
2000
6.0V
1800
5.5V
5.0V
1600
4.5V
IDD(µA)
Data based on matrix samples. See first page of this section for details.
1400
4.0V
1200
3.5V
1000
3.0V
800
2.5V
600
400
200
0
0.0
0.5
1.0
1.5
2.0
2.5
Frequency(MHz)
DS30234D-page 284
3.0
3.5
4.0
4.5
Shaded area is
beyond recommended range
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 24-14: TYPICAL IDD vs. FREQUENCY (RC MODE @ 100 pF, 25°C)
1600
6.0V
1400
5.5V
5.0V
1200
4.5V
4.0V
1000
IDD(µA)
3.5V
3.0V
800
2.5V
600
400
200
0
0
200
400
Shaded area is
beyond recommended range
600
800
1000
1200
1400
1600
1800
Frequency(kHz)
FIGURE 24-15: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 100 pF, -40°C TO 85°C)
1600
6.0V
1400
5.0V
1200
4.5V
4.0V
1000
IDD(µA)
3.5V
3.0V
800
2.5V
600
400
200
0
0
200
400
Shaded area is
beyond recommended range
 1997 Microchip Technology Inc.
600
800
1000
1200
1400
1600
1800
Frequency(kHz)
DS30234D-page 285
Data based on matrix samples. See first page of this section for details.
5.5V
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 24-16: TYPICAL IDD vs. FREQUENCY (RC MODE @ 300 pF, 25°C)
1200
6.0V
5.5V
1000
5.0V
4.5V
4.0V
800
3.5V
IDD(µA)
3.0V
600
2.5V
400
200
0
0
100
200
300
400
500
600
700
Frequency(kHz)
FIGURE 24-17: MAXIMUM IDD vs. FREQUENCY (RC MODE @ 300 pF, -40°C TO 85°C)
1200
6.0V
5.5V
5.0V
4.5V
4.0V
800
3.5V
IDD(µA)
Data based on matrix samples. See first page of this section for details.
1000
3.0V
600
2.5V
400
200
0
0
100
200
300
400
500
600
700
Frequency(kHz)
DS30234D-page 286
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 24-18: TYPICAL IDD vs.
CAPACITANCE @ 500 kHz
(RC MODE)
FIGURE 24-19: TRANSCONDUCTANCE(gm)
OF HS OSCILLATOR vs. VDD
600
4.0
500
3.5
3.0
gm(mA/V)
4.0V
400
IDD(µA)
Max -40°C
5.0V
3.0V
300
200
2.5
Typ 25°C
2.0
Min 85°C
1.5
1.0
100
0.5
100 pF
RC OSCILLATOR
FREQUENCIES
100
300 pF
5.0
5.5
6.0
6.5
7.0
5k
4.12 MHz
± 1.4%
10k
2.35 MHz
± 1.4%
100k
268 kHz
± 1.1%
80
70
60
1.80 MHz
± 1.0%
5k
1.27 MHz
± 1.0%
10k
688 kHz
± 1.2%
20
100k
77.2 kHz
± 1.0%
10
3.3k
707 kHz
± 1.4%
5k
501 kHz
± 1.2%
269 kHz
± 1.6%
100k
28.3 kHz
± 1.1%
The percentage variation indicated here is part to
part variation due to normal process distribution. The
variation indicated is ±3 standard deviation from
average value for VDD = 5V.
Typ 25°C
50
3.3k
10k
Max -40°C
90
gm(µA/V)
100 pF
4.5
110
Rext
Fosc @ 5V, 25°C
22 pF
4.0
FIGURE 24-20: TRANSCONDUCTANCE(gm)
OF LP OSCILLATOR vs. VDD
Average
Cext
3.5
VDD(Volts)
Shaded area is
beyond recommended range
Capacitance(pF)
TABLE 24-1:
0.0
3.0
300 pF
40
30
0
2.0
Min 85°C
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
7.0
VDD(Volts)
Shaded areas are
beyond recommended range
FIGURE 24-21: TRANSCONDUCTANCE(gm)
OF XT OSCILLATOR vs. VDD
1000
900
Max -40°C
800
gm(µA/V)
700
600
Typ 25°C
500
400
300
Min 85°C
200
100
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
7.0
VDD(Volts)
Shaded areas are
beyond recommended range
 1997 Microchip Technology Inc.
DS30234D-page 287
Data based on matrix samples. See first page of this section for details.
0
20 pF
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 24-22: TYPICAL XTAL STARTUP
TIME vs. VDD (LP MODE, 25°C)
FIGURE 24-24: TYPICAL XTAL STARTUP
TIME vs. VDD (XT MODE, 25°C)
3.5
70
3.0
60
50
Startup Time(ms)
Startup Time(Seconds)
2.5
2.0
32 kHz, 33 pF/33 pF
1.5
1.0
40
200 kHz, 68 pF/68 pF
30
200 kHz, 47 pF/47 pF
20
1 MHz, 15 pF/15 pF
10
0.5
4 MHz, 15 pF/15 pF
200 kHz, 15 pF/15 pF
0.0
2.5
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
6.0
4.0
4.5
VDD(Volts)
5.0
5.5
6.0
VDD(Volts)
FIGURE 24-23: TYPICAL XTAL STARTUP
TIME vs. VDD (HS MODE,
25°C)
TABLE 24-2:
7
Osc Type
Startup Time(ms)
Data based on matrix samples. See first page of this section for details.
6
LP
20 MHz, 33 pF/33 pF
5
XT
4
8 MHz, 33 pF/33 pF
3
20 MHz, 15 pF/15 pF
8 MHz, 15 pF/15 pF
2
1
4.0
4.5
DS30234D-page 288
5.0
VDD(Volts)
5.5
HS
CAPACITOR SELECTION
FOR CRYSTAL
OSCILLATORS
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
32 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
20 MHz
15-33 pF
15-33 pF
6.0
Crystals
Used
32 kHz
Epson C-001R32.768K-A
± 20 PPM
200 kHz
STD XTL 200.000KHz
± 20 PPM
1 MHz
ECS ECS-10-13-1
± 50 PPM
4 MHz
ECS ECS-40-20-1
± 50 PPM
8 MHz
EPSON CA-301 8.000M-C
± 30 PPM
20 MHz
EPSON CA-301 20.000M-C
± 30 PPM
 1997 Microchip Technology Inc.
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 24-25: TYPICAL IDD vs. FREQUENCY
(LP MODE, 25°C)
FIGURE 24-27: TYPICAL IDD vs. FREQUENCY
(XT MODE, 25°C)
1800
1600
6.0V
1400
5.5V
120
100
5.0V
1200
4.5V
1000
4.0V
60
40
20
0
0
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
IDD(µA)
IDD(µA)
80
3.5V
800
3.0V
600
2.5V
400
50
100
150
200
200
Frequency(kHz)
0
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
Frequency(MHz)
FIGURE 24-26: MAXIMUM IDD vs.
FREQUENCY
(LP MODE, 85°C TO -40°C)
FIGURE 24-28: MAXIMUM IDD vs.
FREQUENCY
(XT MODE, -40°C TO 85°C)
1800
6.0V
1600
120
1400
100
1200
80
1000
4.0V
800
3.5V
40
20
0
0
6.0V
5.5V
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
5.5V
5.0V
4.5V
3.0V
600
2.5V
400
200
50
100
Frequency(kHz)
150
200
0
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
Frequency(MHz)
 1997 Microchip Technology Inc.
DS30234D-page 289
Data based on matrix samples. See first page of this section for details.
60
IDD(µA)
IDD(µA)
140
PIC16C6X
Applicable Devices 61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
FIGURE 24-29: TYPICAL IDD vs. FREQUENCY
(HS MODE, 25°C)
7.0
FIGURE 24-30: MAXIMUM IDD vs.
FREQUENCY
(HS MODE, -40°C TO 85°C)
7.0
6.0
6.0
5.0
IDD(mA)
IDD(mA)
5.0
4.0
3.0
2.0
1.0
0.0
1 2
6.0V
5.5V
5.0V
4.5V
4.0V
4.0
3.0
2.0
1.0
4
6
8
10
12
Frequency(MHz)
14
16
18
20
0.0
1 2
6.0V
5.5V
5.0V
4.5V
4.0V
4
6
8
10
12
14
16
18
20
Data based on matrix samples. See first page of this section for details.
Frequency(MHz)
DS30234D-page 290
 1997 Microchip Technology Inc.
PIC16C6X
25.0
PACKAGING INFORMATION
25.1
18-Lead Plastic Dual In-line (300 mil) (P)
N
α
C
E1 E
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
Base
Plane
Seating
Plane
L
B1
A1 A2 A
e1
B
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Symbol
Min
α
0°
10°
0°
10°
A
A1
A2
B
B1
C
D
D1
E
E1
e1
eA
eB
L
N
S
S1
–
0.381
3.048
0.355
1.524
0.203
22.479
20.320
7.620
6.096
2.489
7.620
7.874
3.048
18
0.889
0.127
4.064
–
3.810
0.559
1.524
0.381
23.495
20.320
8.255
7.112
2.591
7.620
9.906
3.556
18
–
–
–
0.015
0.120
0.014
0.060
0.008
0.885
0.800
0.300
0.240
0.098
0.300
0.310
0.120
18
0.035
0.005
0.160
–
0.150
0.022
0.060
0.015
0.925
0.800
0.325
0.280
0.102
0.300
0.390
0.140
18
–
–
 1997 Microchip Technology Inc.
Max
Inches
Notes
Reference
Typical
Reference
Typical
Reference
Min
Max
Notes
Reference
Typical
Reference
Typical
Reference
DS30234D-page 291
PIC16C6X
25.2
28-Lead Plastic Dual In-line (300 mil) (SP)
N
α
E1 E
C
eA
eB
Pin No. 1
Indicator
Area
B2
D
B1
S
Base
Plane
Seating
Plane
L
Detail A
B3
A1 A2 A
e1
B
Detail A
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Symbol
Min
Max
α
0°
A
A1
A2
B
B1
B2
B3
C
D
D1
E
E1
e1
eA
eB
L
N
S
3.632
0.381
3.175
0.406
1.016
0.762
0.203
0.203
34.163
33.020
7.874
7.112
2.540
7.874
8.128
3.175
28
0.584
DS30234D-page 292
Inches
Notes
Min
Max
10°
0°
10°
4.572
–
3.556
0.559
1.651
1.016
0.508
0.331
35.179
33.020
8.382
7.493
2.540
7.874
9.652
3.683
28
1.220
0.143
0.015
0.125
0.016
0.040
0.030
0.008
0.008
1.385
1.300
0.310
0.280
0.100
0.310
0.320
0.125
28
0.023
0.180
–
0.140
0.022
0.065
0.040
0.020
0.013
1.395
1.300
0.330
0.295
0.100
0.310
0.380
0.145
28
0.048
Typical
4 places
4 places
Typical
Reference
Typical
Reference
Notes
Typical
4 places
4 places
Typical
Reference
Typical
Reference
 1997 Microchip Technology Inc.
PIC16C6X
25.3
40-Lead Plastic Dual In-line (600 mil) (P)
N
α
E1 E
C
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
Base
Plane
Seating
Plane
L
B1
A1 A2 A
e1
B
D1
Package Group: Plastic Dual In-Line (PLA)
Millimeters
Symbol
Min
Max
α
0°
A
A1
A2
B
B1
C
D
D1
E
E1
e1
eA
eB
L
N
S
S1
–
0.381
3.175
0.355
1.270
0.203
51.181
48.260
15.240
13.462
2.489
15.240
15.240
2.921
40
1.270
0.508
 1997 Microchip Technology Inc.
Inches
Notes
Min
Max
10°
0°
10°
5.080
–
4.064
0.559
1.778
0.381
52.197
48.260
15.875
13.970
2.591
15.240
17.272
3.683
40
–
–
–
0.015
0.125
0.014
0.050
0.008
2.015
1.900
0.600
0.530
0.098
0.600
0.600
0.115
40
0.050
0.020
0.200
–
0.160
0.022
0.070
0.015
2.055
1.900
0.625
0.550
0.102
0.600
0.680
0.145
40
–
–
Typical
Typical
Reference
Typical
Reference
Notes
Typical
Typical
Reference
Typical
Reference
DS30234D-page 293
PIC16C6X
25.4
18-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body) (SO)
e
B
h x 45°
N
Index
Area
E
H
α
C
Chamfer
h x 45°
L
1
2
3
D
Seating
Plane
Base
Plane
CP
A1
A
Package Group: Plastic SOIC (SO)
Millimeters
Symbol
Min
Max
Inches
Notes
Min
Max
α
0°
8°
0°
8°
A
A1
B
C
D
E
e
H
h
L
N
CP
2.362
0.101
0.355
0.241
11.353
7.416
1.270
10.007
0.381
0.406
18
–
2.642
0.300
0.483
0.318
11.735
7.595
1.270
10.643
0.762
1.143
18
0.102
0.093
0.004
0.014
0.009
0.447
0.292
0.050
0.394
0.015
0.016
18
–
0.104
0.012
0.019
0.013
0.462
0.299
0.050
0.419
0.030
0.045
18
0.004
DS30234D-page 294
Reference
Notes
Reference
 1997 Microchip Technology Inc.
PIC16C6X
25.5
28-Lead Plastic Surface Mount (SOIC - Wide, 300 mil Body) (SO)
e
B
h x 45°
N
Index
Area
E
H
α
C
Chamfer
h x 45°
L
1
2
3
D
Seating
Plane
Base
Plane
CP
A1
A
Package Group: Plastic SOIC (SO)
Millimeters
Symbol
Min
Max
Inches
Notes
Min
Max
α
0°
8°
0°
8°
A
A1
B
C
D
E
e
H
h
L
N
CP
2.362
0.101
0.355
0.241
17.703
7.416
1.270
10.007
0.381
0.406
28
–
2.642
0.300
0.483
0.318
18.085
7.595
1.270
10.643
0.762
1.143
28
0.102
0.093
0.004
0.014
0.009
0.697
0.292
0.050
0.394
0.015
0.016
28
–
0.104
0.012
0.019
0.013
0.712
0.299
0.050
0.419
0.030
0.045
28
0.004
 1997 Microchip Technology Inc.
Typical
Notes
Typical
DS30234D-page 295
PIC16C6X
25.6
18-Lead Ceramic CERDIP Dual In-line with Window (300 mil) (JW)
N
α
C
E1 E
eA
eB
Pin No. 1
Indicator
Area
D
S
S1
Base
Plane
Seating
Plane
L
B1
A1 A3 A
e1
B
A2
D1
Package Group: Ceramic CERDIP Dual In-Line (CDP)
Millimeters
Symbol
Min
Max
α
0°
A
A1
A2
A3
B
B1
C
D
D1
E
E1
e1
eA
eB
L
N
S
S1
—
0.381
3.810
3.810
0.355
1.270
0.203
22.352
20.320
7.620
5.588
2.540
7.366
7.620
3.175
18
0.508
0.381
DS30234D-page 296
Inches
Notes
Min
Max
10°
0°
10°
5.080
1.778
4.699
4.445
0.585
1.651
0.381
23.622
20.320
8.382
7.874
2.540
8.128
10.160
3.810
18
1.397
1.270
—
0.015
0.150
0.150
0.014
0.050
0.008
0.880
0.800
0.300
0.220
0.100
0.290
0.300
0.125
18
0.020
0.015
0.200
0.070
0.185
0.175
0.023
0.065
0.015
0.930
0.800
0.330
0.310
0.100
0.320
0.400
0.150
18
0.055
0.050
Typical
Typical
Reference
Reference
Typical
Notes
Typical
Typical
Reference
Reference
Typical
 1997 Microchip Technology Inc.
PIC16C6X
25.7
28-Lead Ceramic CERDIP Dual In-line with Window (300 mil)) (JW)
N
E1 E
α
C
Pin No. 1
Indicator
Area
eA
eB
D
D1
Base
Plane
Seating
Plane
L
B1
A1 A2 A
e1
B
D2
Package Group: Ceramic CERDIP Dual In-Line (CDP)
Millimeters
Symbol
Min
Max
α
0°
A
A1
A2
B
B1
C
D
D2
E
E1
e
eA
eB
L
N
D1
3.30
0.38
2.92
0.35
1.14
0.20
34.54
32.97
7.62
6.10
2.54
7.62
—
2.92
28
0.13
 1997 Microchip Technology Inc.
Inches
Notes
Min
Max
10°
0°
10°
5.84
—
4.95
0.58
1.78
0.38
37.72
33.07
8.25
7.87
2.54
7.62
11.43
5.08
28
—
.130
0.015
0.115
0.014
0.045
0.008
1.360
1.298
0.300
0.240
0.100
0.300
—
0.115
28
0.005
0.230
—
0.195
0.023
0.070
0.015
1.485
1.302
0.325
0.310
0.100
0.300
0.450
0.200
28
—
Typical
Typical
Reference
Typical
Reference
Notes
Typical
Typical
Reference
Typical
Reference
DS30234D-page 297
PIC16C6X
25.8
40-Lead Ceramic CERDIP Dual In-line with Window (600 mil) (JW)
N
E1 E
α
C
Pin No. 1
Indicator
Area
eA
eB
D
S
S1
Base
Plane
Seating
Plane
L
B1
A1 A3 A A2
e1
B
D1
Package Group: Ceramic CERDIP Dual In-Line (CDP)
Millimeters
Symbol
Min
Max
α
0°
A
A1
A2
A3
B
B1
C
D
D1
E
E1
e1
eA
eB
L
N
S
S1
4.318
0.381
3.810
3.810
0.355
1.270
0.203
51.435
48.260
15.240
12.954
2.540
14.986
15.240
3.175
40
1.016
0.381
DS30234D-page 298
Inches
Notes
Min
Max
10°
0°
10°
5.715
1.778
4.699
4.445
0.585
1.651
0.381
52.705
48.260
15.875
15.240
2.540
16.002
18.034
3.810
40
2.286
1.778
0.170
0.015
0.150
0.150
0.014
0.050
0.008
2.025
1.900
0.600
0.510
0.100
0.590
0.600
0.125
40
0.040
0.015
0.225
0.070
0.185
0.175
0.023
0.065
0.015
2.075
1.900
0.625
0.600
0.100
0.630
0.710
0.150
40
0.090
0.070
Typical
Typical
Reference
Reference
Typical
Notes
Typical
Typical
Reference
Reference
Typical
 1997 Microchip Technology Inc.
PIC16C6X
25.9
28-Lead Ceramic Side Brazed Dual In-Line with Window (300 mil) (JW)
N
C
E1 E
eA
eB
α
Pin #1
Indicator Area
D
S1
S
Base
Plane
Seating
Plane
L
B1
A3
A2
A
A1
e1
B
D1
Package Group: Ceramic Side Brazed Dual In-Line (CER)
Millimeters
Inches
Symbol
α
A
A1
A2
A3
B
B1
C
D
D1
E
E1
e1
eA
eB
L
N
S
S1
Min
Max
0°
3.937
1.016
2.921
1.930
0.406
1.219
0.228
35.204
32.893
7.620
7.366
2.413
7.366
7.594
3.302
28
1.143
0.533
10°
5.030
1.524
3.506
2.388
0.508
1.321
0.305
35.916
33.147
8.128
7.620
2.667
7.874
8.179
4.064
28
1.397
0.737
 1997 Microchip Technology Inc.
Notes
Typical
Typical
Reference
Typical
Reference
Min
Max
0°
0.155
0.040
0.115
0.076
0.016
0.048
0.009
1.386
1.295
0.300
0.290
0.095
0.290
0.299
0.130
28
0.045
0.021
10°
0.198
0.060
0.138
0.094
0.020
0.052
0.012
1.414
1.305
0.320
0.300
0.105
0.310
0.322
0.160
28
0.055
0.029
Notes
DS30234D-page 299
PIC16C6X
25.10
28-Lead Plastic Surface Mount (SSOP - 209 mil Body 5.30 mm) (SS)
N
Index
area
E
H
α
C
L
1 2 3
B
e
A
Base plane
CP
Seating plane
D
A1
Package Group: Plastic SSOP
Millimeters
Symbol
Min
Max
Inches
Notes
Min
Max
α
0°
8°
0°
8°
A
A1
B
C
D
E
e
H
L
N
CP
1.730
0.050
0.250
0.130
10.070
5.200
0.650
7.650
0.550
28
-
1.990
0.210
0.380
0.220
10.330
5.380
0.650
7.900
0.950
28
0.102
0.068
0.002
0.010
0.005
0.396
0.205
0.026
0.301
0.022
28
-
0.078
0.008
0.015
0.009
0.407
0.212
0.026
0.311
0.037
28
0.004
DS30234D-page 300
Reference
Notes
Reference
 1997 Microchip Technology Inc.
PIC16C6X
25.11
44-Lead Plastic Leaded Chip Carrier (Square) (PLCC)
D
-A-
D1
-D-
3
-F-
0.812/0.661 N Pics
.032/.026
1.27
.050
2 Sides
0.177
.007 S B D-E S
-HA
A1
3
D3/E3
D2
0.38
.015
3
-G-
8
F-G S
0.177
.007 S B A S
2 Sides
9
0.101 Seating
.004 Plane
D
-C-
4
E2
E1
E
0.38
.015
F-G S
4
-B-
3
-E-
0.177
.007 S A F-G S
10
0.254
.010 Max
2
0.254
.010 Max
11
-H-
11
0.508
.020
0.508
.020
-H-
2
0.812/0.661
3
.032/.026
1.524
.060 Min
6
6
-C1.651
.065
1.651
.065
R 1.14/0.64
.045/.025
R 1.14/0.64
.045/.025
5
0.533/0.331
.021/.013
0.64 Min
.025
0.177
, D-E S
.007 M A F-G S
Package Group: Plastic Leaded Chip Carrier (PLCC)
Millimeters
Symbol
Min
Max
A
4.191
A1
D
D1
D2
D3
E
E1
E2
E3
N
CP
LT
2.413
17.399
16.510
15.494
12.700
17.399
16.510
15.494
12.700
44
–
0.203
 1997 Microchip Technology Inc.
Inches
Notes
Min
Max
4.572
0.165
0.180
2.921
17.653
16.663
16.002
12.700
17.653
16.663
16.002
12.700
44
0.102
0.381
0.095
0.685
0.650
0.610
0.500
0.685
0.650
0.610
0.500
44
–
0.008
0.115
0.695
0.656
0.630
0.500
0.695
0.656
0.630
0.500
44
0.004
0.015
Reference
Reference
Notes
Reference
Reference
DS30234D-page 301
PIC16C6X
25.12
44-Lead Plastic Surface Mount (MQFP 10x10 mm Body 1.6/0.15 mm Lead Form) (PQ)
4 D
D1 5
0.20 M C A-B S
D S
0.20 M H A-B S
D S
7
0.20 min.
0.05 mm/mm A-B
D3
0.13 R min.
Index
area 6
9
PARTING
LINE
0.13/0.30 R
α
b
L
C
E3
E1 E
1.60 Ref.
0.20 M C A-B S
D S
4
TYP 4x
10
e
0.20 M H A-B S
B
D S
5
7
0.05 mm/mm D
A2
A
Base
Plane
Seating
Plane
A1
Package Group: Plastic MQFP
Millimeters
Symbol
Min
Max
Inches
Notes
Min
Max
α
0°
7°
0°
7°
A
A1
A2
b
C
D
D1
D3
E
E1
E3
e
L
N
CP
2.000
0.050
1.950
0.300
0.150
12.950
9.900
8.000
12.950
9.900
8.000
0.800
0.730
44
0.102
2.350
0.250
2.100
0.450
0.180
13.450
10.100
8.000
13.450
10.100
8.000
0.800
1.030
44
–
0.078
0.002
0.768
0.011
0.006
0.510
0.390
0.315
0.510
0.390
0.315
0.031
0.028
44
0.004
0.093
0.010
0.083
0.018
0.007
0.530
0.398
0.315
0.530
0.398
0.315
0.032
0.041
44
–
DS30234D-page 302
Typical
Reference
Reference
Notes
Typical
Reference
Reference
 1997 Microchip Technology Inc.
PIC16C6X
25.13
44-Lead Plastic Surface Mount (TQFP 10x10 mm Body 1.0/0.10 mm Lead Form) (TQ)
D
D1
1.0ø (0.039ø) Ref.
Pin#1
2
11°/13°(4x)
Pin#1
2
E
0° Min
E1
Θ
11°/13°(4x)
Detail B
e
3.0ø (0.118ø) Ref.
Option 1 (TOP side)
A2
A
L
Detail A
R 0.08/0.20
Option 2 (TOP side)
A1
Detail B
R1 0.08 Min
Base Metal
Lead Finish
b
L
c
1.00 Ref.
Gage Plane
0.250
c1
L1
1.00 Ref
b1
Detail A
S
0.20
Min
Detail B
Package Group: Plastic TQFP
Millimeters
Inches
Symbol
Min
Max
A
A1
A2
D
D1
E
E1
L
e
b
b1
c
c1
N
1.00
0.05
0.95
11.75
9.90
11.75
9.90
0.45
1.20
0.15
1.05
12.25
10.10
12.25
10.10
0.75
Notes
Min
Max
0.039
0.002
0.037
0.463
0.390
0.463
0.390
0.018
0.047
0.006
0.041
0.482
0.398
0.482
0.398
0.030
0.30
0.30
0.09
0.09
44
0.45
0.40
0.20
0.16
44
0.012
0.012
0.004
0.004
44
0.018
0.016
0.008
0.006
44
Θ
0°
7°
0°
7°
0.80 BSC
Notes
0.031 BSC
Note 1: Dimensions D1 and E1 do not include mold protrusion. Allowable mold protrusion is 0.25m/m (0.010”) per
side. D1 and E1 dimensions including mold mismatch.
2: Dimension “b” does not include Dambar protrusion, allowable Dambar protrusion shall be 0.08m/m
(0.003”)max.
3: This outline conforms to JEDEC MS-026.
 1997 Microchip Technology Inc.
DS30234D-page 303
PIC16C6X
25.14
Package Marking Information
18-Lead PDIP
Example
MMMMMMMMMMMMM
XXXXXXXXXXXXXXXX
PIC16C61-04/P
9450CBA
AABBCDE
18-Lead SOIC
Example
MMMMMMMMMM
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16C61
-20/SO
AABBCDE
9449CBA
18-Lead CERDIP Windowed
Example
MMMMMM
XXXXXXXX
PIC16C61
/JW
9440CBT
AABBCDE
28-Lead PDIP (.300 MIL)
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
PIC16C63-04I/SP
AABBCAE
Legend:
MM...M
XX...X
AA
BB
C
D1
D2
E
Note:
9452CAN
Microchip part number information
Customer specific information*
Year code (last 2 digits of calender year)
Week code (week of January 1 is week '01’)
Facility code of the plant at which wafer is manufactured.
C = Chandler, Arizona, U.S.A.
S = Tempe, Arizona, U.S.A.
Mask revision number for microcontroller
Mask revision number for EEPROM
Assembly code of the plant or country of origin in which
part was assembled.
In the event the full Microchip part number cannot be marked on one
line, it will be carried over to the next line thus limiting the number of
available characters for customer specific information.
* Standard OTP marking consists of Microchip part number, year code, week code,
facility code, mask revision number, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
DS30234D-page 304
 1997 Microchip Technology Inc.
PIC16C6X
Package Marking Information (Cont’d)
28-Lead SOIC
Example
MMMMMMMMMMMMMMMMMMXX
XXXXXXXXXXXXXXXXXXXX
PIC16C62-20/S0111
AABBCAE
9515SBA
28-Lead CERDIP Skinny Windowed
Example
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
PIC16C62/JW
9517SBT
AABBCDE
28-Lead Side Brazed Skinny Windowed
Example
XXXXXXXXXXX
XXXXXXXXXXX
PIC16C66/JW
AABBCDE
28-Lead SSOP
9517CAT
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
PIC16C62
20I/SS025
AABBCAE
9517SBP
Example
40-Lead PDIP
MMMMMMMMMMMMMM
XXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXX
AABBCDE
Legend:
Note:
PIC16C65-04/P
9510CAA
MM...M
XX...X
AA
BB
C
Microchip part number information
Customer specific information*
Year code (last 2 digits of calender year)
Week code (week of January 1 is week '01’)
Facility code of the plant at which wafer is manufactured.
C = Chandler, Arizona, U.S.A.
S = Tempe, Arizona, U.S.A.
D1
E
Mask revision number for microcontroller
Assembly code of the plant or country of origin in which
part was assembled.
In the event the full Microchip part number cannot be marked on one
line, it will be carried over to the next line thus limiting the number of
available characters for customer specific information.
* Standard OTP marking consists of Microchip part number, year code, week code,
facility code, mask revision number, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
 1997 Microchip Technology Inc.
DS30234D-page 305
PIC16C6X
Package Marking Information (Cont’d)
40-Lead CERDIP Windowed
Example
PIC16C67/JW
MMMMMMMMM
XXXXXXXXXXX
XXXXXXXXXXX
9450CAT
AABBCDE
44-Lead PLCC
Example
MMMMMMMM
XXXXXXXXXX
PIC16C64
-20/L
XXXXXXXXXX
AABBCDE
9442CAN
Example
44-Lead MQFP
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
PIC16C64
-04/PQ
9444CAP
44-Lead TQFP
Example
MMMMMMMM
XXXXXXXXXX
XXXXXXXXXX
AABBCDE
Legend:
Note:
PIC16C64A
-10/TQ
AABBCDE
MM...M
XX...X
AA
BB
C
Microchip part number information
Customer specific information*
Year code (last 2 digits of calender year)
Week code (week of January 1 is week '01’)
Facility code of the plant at which wafer is manufactured.
C = Chandler, Arizona, U.S.A.
S = Tempe, Arizona, U.S.A.
D1
E
Mask revision number for microcontroller
Assembly code of the plant or country of origin in which
part was assembled.
In the event the full Microchip part number cannot be marked on one
line, it will be carried over to the next line thus limiting the number of
available characters for customer specific information.
* Standard OTP marking consists of Microchip part number, year code, week code,
facility code, mask revision number, and assembly code. For OTP marking beyond
this, certain price adders apply. Please check with your Microchip Sales Office.
For QTP devices, any special marking adders are included in QTP price.
DS30234D-page 306
 1997 Microchip Technology Inc.
PIC16C6X
APPENDIX A: MODIFICATIONS
APPENDIX B: COMPATIBILITY
The following are the list of modifications over the
PIC16C5X microcontroller family:
To convert code written for PIC16C5X to PIC16CXX,
the user should take the following steps:
1.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
Instruction word length is increased to 14-bits.
This allows larger page sizes both in program
memory (2K now as opposed to 512 before) and
register file (128 bytes now versus 32 bytes
before).
A PC high latch register (PCLATH) is added to
handle program memory paging. PA2, PA1, PA0
bits are removed from STATUS register.
Data memory paging is redefined slightly. STATUS register is modified.
Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for compatibility with PIC16C5X.
OPTION and TRIS registers are made addressable.
Interrupt capability is added. Interrupt vector is
at 0004h.
Stack size is increased to 8 deep.
Reset vector is changed to 0000h.
Reset of all registers is revisited. Five different
reset (and wake-up) types are recognized. Registers are reset differently.
Wake-up from SLEEP through interrupt is
added.
Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT), are
included for more reliable power-up. These timers are invoked selectively to avoid unnecessary
delays on power-up and wake-up.
PORTB has weak pull-ups and interrupt on
change feature.
Timer0 pin is also a port pin (RA4/T0CKI) now.
FSR is made a full 8-bit register.
“In-circuit programming” is made possible. The
user can program PIC16CXX devices using only
five pins: VDD, VSS, VPP, RB6 (clock) and RB7
(data in/out).
Power Control register (PCON) is added with a
Power-on Reset status bit (POR).(Not on the
PIC16C61).
Brown-out Reset has been added to the following devices:
PIC16C62A/R62/63/R63/64A/R64/65A/R65/66/
67.
 1997 Microchip Technology Inc.
2.
3.
4.
5.
Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL,
GOTO.
Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
Eliminate any data memory page switching.
Redefine data variables to reallocate them.
Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
Change reset vector to 0000h.
DS30234D-page 307
PIC16C6X
APPENDIX C: WHAT’S NEW
APPENDIX D: WHAT’S CHANGED
Added PIC16CR63 and PIC16CR65 devices.
Minor changes, spelling and grammatical changes.
Added PIC16C66 and PIC16C67 devices. The
PIC16C66/67 devices have 368 bytes of data memory
distributed in 4 banks and 8K of program memory in 4
pages. These two devices have an enhanced SPI that
supports both clock phase and polarity. The USART
has been enhanced.
Divided SPI section into SPI for the PIC16C66/67
(Section 11.3) and SPI for all other devices
(Section 11.2).
When upgrading to the PIC16C66/67 please note that
the upper 16 bytes of data memory in banks 1,2, and 3
are mapped into bank 0. This may require relocation of
data memory usage in the user application code.
Q-cycles for instruction execution were added to Section 14.0 Instruction Set Summary.
DS30234D-page 308
Added the following note for the USART. This applies to
all devices except the PIC16C66 and PIC16C67.
For the PIC16C63/R63/65/65A/R65 the asynchronous
high speed mode (BRGH = 1) may experience a high
rate of receive errors. It is recommended that BRGH =
0. If you desire a higher baud rate than BRGH = 0 can
support, refer to the device errata for additional information or use the PIC16C66/67.
 1997 Microchip Technology Inc.
PIC16C6X
APPENDIX E: PIC16/17 MICROCONTROLLERS
E.1
PIC12CXXX Family of Devices
PIC12C508
Clock
Memory
Peripherals
Features
PIC12C509
PIC12C671
PIC12C672
Maximum Frequency
of Operation (MHz)
4
4
4
4
EPROM Program Memory
512 x 12
1024 x 12
1024 x 14
2048 x 14
Data Memory (bytes)
25
41
128
128
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
A/D Converter (8-bit) Channels
—
—
4
4
Wake-up from SLEEP on
pin change
Yes
Yes
Yes
Yes
I/O Pins
5
5
5
5
Input Pins
1
1
1
1
Internal Pull-ups
Yes
Yes
Yes
Yes
Voltage Range (Volts)
2.5-5.5
2.5-5.5
2.5-5.5
2.5-5.5
In-Circuit Serial Programming
Yes
Yes
Yes
Yes
Number of Instructions
33
33
35
35
Packages
8-pin DIP, SOIC
8-pin DIP, SOIC
8-pin DIP, SOIC
8-pin DIP, SOIC
All PIC12C5XX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC12C5XX devices use serial programming with data pin GP1 and clock pin GP0.
E.2
PIC14C000 Family of Devices
PIC14C000
Clock
Memory
Peripherals
Features
Maximum Frequency of Operation (MHz)
20
EPROM Program Memory (x14 words)
4K
Data Memory (bytes)
192
Timer Module(s)
TMR0
ADTMR
Serial Port(s)
(SPI/I2C, USART)
I2C with SMBus
Support
Slope A/D Converter Channels
8 External; 6 Internal
Interrupt Sources
11
I/O Pins
22
Voltage Range (Volts)
2.7-6.0
In-Circuit Serial Programming
Yes
Additional On-chip Features
Internal 4MHz Oscillator, Bandgap Reference,Temperature Sensor,
Calibration Factors, Low Voltage Detector, SLEEP, HIBERNATE,
Comparators with Programmable References (2)
Packages
28-pin DIP (.300 mil), SOIC, SSOP
 1997 Microchip Technology Inc.
DS30234D-page 309
PIC16C6X
E.3
PIC16C15X Family of Devices
PIC16C154
Clock
Memory
PIC16C156
PIC16CR156
PIC16C158
PIC16CR158
20
20
20
20
20
20
EPROM Program Memory
(x12 words)
512
—
1K
—
2K
—
ROM Program Memory
(x12 words)
—
512
—
1K
—
2K
25
25
25
73
73
RAM Data Memory (bytes) 25
Peripherals Timer Module(s)
I/O Pins
Features
PIC16CR154
Maximum Frequency
of Operation (MHz)
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
12
12
12
12
12
12
Voltage Range (Volts)
3.0-5.5
2.5-5.5
3.0-5.5
2.5-5.5
3.0-5.5
2.5-5.5
Number of Instructions
33
33
33
33
33
33
Packages
18-pin DIP, 18-pin DIP,
18-pin DIP, 18-pin DIP,
18-pin DIP,
18-pin DIP,
SOIC;
SOIC;
SOIC;
SOIC;
SOIC;
SOIC;
20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability.
E.4
PIC16C5X Family of Devices
PIC16C52
Clock
Memory
PIC16C54A
20
20
20
EPROM Program Memory
(x12 words)
384
512
512
—
512
1K
ROM Program Memory
(x12 words)
—
—
—
512
—
—
25
25
25
25
25
24
TMR0
TMR0
TMR0
TMR0
TMR0
TMR0
I/O Pins
12
12
12
12
20
12
Voltage Range (Volts)
2.5-6.25
2.5-6.25
2.0-6.25
2.0-6.25
2.5-6.25
2.5-6.25
Number of Instructions
33
33
33
33
Packages
18-pin DIP, 18-pin DIP,
18-pin DIP,
18-pin DIP,
SOIC
SOIC;
SOIC;
SOIC;
20-pin SSOP 20-pin SSOP 20-pin SSOP
PIC16CR57B
33
33
28-pin DIP,
SOIC,
SSOP
18-pin DIP,
SOIC;
20-pin SSOP
PIC16C58A
PIC16CR58A
Maximum Frequency
of Operation (MHz)
20
20
20
20
EPROM Program Memory
(x12 words)
2K
—
2K
—
ROM Program Memory
(x12 words)
—
2K
—
2K
73
RAM Data Memory (bytes)
72
72
73
TMR0
TMR0
TMR0
TMR0
I/O Pins
20
20
12
12
Voltage Range (Volts)
2.5-6.25
2.5-6.25
2.0-6.25
2.5-6.25
33
Peripherals Timer Module(s)
Features
PIC16C56
20
PIC16C57
Memory
PIC16C55
20
RAM Data Memory (bytes)
Clock
PIC16CR54A
4
Peripherals Timer Module(s)
Features
PIC16C54
Maximum Frequency
of Operation (MHz)
Number of Instructions
33
33
33
Packages
28-pin DIP,
SOIC,
SSOP
28-pin DIP, SOIC,
SSOP
18-pin DIP, SOIC; 18-pin DIP, SOIC;
20-pin SSOP
20-pin SSOP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectable code protect and high
I/O current capability.
DS30234D-page 310
 1997 Microchip Technology Inc.
PIC16C6X
E.5
PIC16C55X Family of Devices
PIC16C556(1)
PIC16C554
Clock
Memory
20
20
20
EPROM Program Memory (x14 words)
512
1K
2K
Data Memory (bytes)
80
80
128
Timer Module(s)
TMR0
TMR0
TMR0
—
—
—
—
—
—
Peripherals Comparators(s)
Internal Reference Voltage
Features
PIC16C558
Maximum Frequency of Operation (MHz)
Interrupt Sources
3
3
3
I/O Pins
13
13
13
Voltage Range (Volts)
2.5-6.0
2.5-6.0
2.5-6.0
Brown-out Reset
—
—
—
Packages
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C5XX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip sales office for availability of these devices.
E.6
PIC16C62X and PIC16C64X Family of Devices
PIC16C620
Clock
Memory
PIC16C622
PIC16C642
PIC16C662
Maximum Frequency
of Operation (MHz)
20
20
20
20
20
EPROM Program Memory
(x14 words)
512
1K
2K
4K
4K
Data Memory (bytes)
80
80
128
176
176
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
TMR0
2
Peripherals Comparators(s)
Features
PIC16C621
2
2
2
2
Internal Reference Voltage
Yes
Yes
Yes
Yes
Yes
Interrupt Sources
4
4
4
4
5
I/O Pins
13
13
13
22
33
Voltage Range (Volts)
2.5-6.0
2.5-6.0
2.5-6.0
3.0-6.0
3.0-6.0
Brown-out Reset
Yes
Yes
Yes
Yes
Yes
Packages
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
28-pin PDIP,
SOIC,
Windowed
CDIP
40-pin PDIP,
Windowed
CDIP;
44-pin PLCC,
MQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C62X and PIC16C64X Family devices use serial programming with clock pin RB6 and data pin RB7.
 1997 Microchip Technology Inc.
DS30234D-page 311
PIC16C6X
E.7
PIC16C7XX Family of Devces
PIC16C710
PIC16C71
PIC16C711
PIC16C715
PIC16C72
PIC16CR72(1)
Maximum Frequency
of Operation (MHz)
20
20
20
20
20
20
EPROM Program Memory
(x14 words)
512
1K
1K
2K
2K
—
ROM Program Memory
(14K words)
—
—
—
—
—
2K
Data Memory (bytes)
36
36
68
128
128
128
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Compare/
Peripherals PWM Module(s)
—
—
—
—
1
1
Serial Port(s)
(SPI/I2C, USART)
—
—
—
—
SPI/I2C
SPI/I2C
Parallel Slave Port
—
—
—
—
—
—
Clock
Memory
Features
A/D Converter (8-bit) Channels 4
4
4
4
5
5
Interrupt Sources
4
4
4
4
8
8
I/O Pins
13
13
13
13
22
22
Voltage Range (Volts)
3.0-6.0
3.0-6.0
3.0-6.0
3.0-5.5
2.5-6.0
3.0-5.5
In-Circuit Serial Programming
Yes
Yes
Yes
Yes
Yes
Yes
Brown-out Reset
Yes
—
Yes
Yes
Yes
Yes
Packages
18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, 28-pin SDIP, 28-pin SDIP,
SOIC;
SOIC
SOIC;
SOIC;
SOIC, SSOP SOIC, SSOP
20-pin SSOP
20-pin SSOP 20-pin SSOP
PIC16C73A
Clock
Memory
PIC16C76
PIC16C77
Maximum Frequency of Oper- 20
ation (MHz)
20
20
20
EPROM Program Memory
(x14 words)
4K
4K
8K
8K
Data Memory (bytes)
192
192
368
368
Timer Module(s)
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
2
2
2
Serial Port(s) (SPI/I2C, US- SPI/I2C, USART
ART)
SPI/I2C, USART
SPI/I2C, USART
SPI/I2C, USART
Parallel Slave Port
Yes
—
Yes
8
5
8
Capture/Compare/PWM Mod- 2
Peripherals ule(s)
—
A/D Converter (8-bit) Channels 5
Features
PIC16C74A
Interrupt Sources
11
12
11
12
I/O Pins
22
33
22
33
Voltage Range (Volts)
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
In-Circuit Serial Programming
Yes
Yes
Yes
Yes
Brown-out Reset
Yes
Yes
Yes
Yes
Packages
28-pin SDIP,
SOIC
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
28-pin SDIP,
SOIC
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7.
Note 1: Please contact your local Microchip sales office for availability of these devices.
DS30234D-page 312
 1997 Microchip Technology Inc.
PIC16C6X
E.8
PIC16C8X Family of Devices
PIC16F83
Clock
Memory
Peripherals
Features
PIC16CR83
PIC16F84
PIC16CR84
Maximum Frequency
of Operation (MHz)
10
10
10
10
Flash Program Memory
512
—
1K
—
EEPROM Program Memory
—
—
—
—
ROM Program Memory
—
512
—
1K
Data Memory (bytes)
36
36
68
68
Data EEPROM (bytes)
64
64
64
64
Timer Module(s)
TMR0
TMR0
TMR0
TMR0
Interrupt Sources
4
4
4
4
I/O Pins
13
13
13
13
Voltage Range (Volts)
2.0-6.0
2.0-6.0
2.0-6.0
2.0-6.0
Packages
18-pin DIP,
SOIC
18-pin DIP,
SOIC
18-pin DIP,
SOIC
18-pin DIP,
SOIC
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C8X Family devices use serial programming with clock pin RB6 and data pin RB7.
E.9
PIC16C9XX Family Of Devices
PIC16C923
Clock
Memory
8
8
EPROM Program Memory
4K
4K
Data Memory (bytes)
176
176
Timer Module(s)
TMR0,
TMR1,
TMR2
TMR0,
TMR1,
TMR2
Capture/Compare/PWM Module(s)
1
1
SPI/I2C
SPI/I2C
Parallel Slave Port
—
—
A/D Converter (8-bit) Channels
—
5
LCD Module
4 Com,
32 Seg
4 Com,
32 Seg
Interrupt Sources
8
9
I/O Pins
25
25
Input Pins
27
27
Voltage Range (Volts)
3.0-6.0
3.0-6.0
In-Circuit Serial Programming
Yes
Yes
Serial Port(s)
Peripherals (SPI/I2C, USART)
Features
PIC16C924
Maximum Frequency of Operation (MHz)
Brown-out Reset
—
—
Packages
64-pin SDIP(1),
TQFP;
68-pin PLCC,
Die
64-pin SDIP(1),
TQFP;
68-pin PLCC,
Die
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC16C9XX Family devices use serial programming with clock pin RB6 and data pin RB7.
 1997 Microchip Technology Inc.
DS30234D-page 313
PIC16C6X
E.10
PIC17CXXX Family of Devices
PIC17C42A
Clock
Memory
Clock
Memory
PIC17CR43
PIC17C44
33
33
33
33
EPROM Program Memory
(words)
2K
—
4K
—
8K
ROM Program Memory
(words)
—
2K
—
4K
—
RAM Data Memory (bytes)
232
232
454
454
454
Timer Module(s)
TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
Captures/PWM Module(s)
2
2
2
2
2
Serial Port(s) (USART)
Yes
Yes
Yes
Yes
Yes
Hardware Multiply
Yes
Yes
Yes
Yes
Yes
External Interrupts
Yes
Yes
Yes
Yes
Yes
Interrupt Sources
11
11
11
11
11
I/O Pins
33
33
33
33
33
Voltage Range (Volts)
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
2.5-6.0
Number of Instructions
58
58
58
58
58
Packages
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
40-pin DIP;
44-pin PLCC,
MQFP, TQFP
PIC17C752
PIC17C756
Maximum Frequency
of Operation (MHz)
33
33
EPROM Program Memory
(words)
8K
16K
ROM Program Memory
(words)
—
—
RAM Data Memory (bytes)
454
902
Timer Module(s)
TMR0,
TMR1,
TMR2,
TMR3
TMR0,
TMR1,
TMR2,
TMR3
Peripherals
Features
PIC17C43
33
Peripherals
Features
PIC17CR42
Maximum Frequency
of Operation (MHz)
Captures/PWM Module(s)
4/3
4/3
Serial Port(s) (USART)
2
2
Hardware Multiply
Yes
Yes
External Interrupts
Yes
Yes
Interrupt Sources
18
18
I/O Pins
50
50
Voltage Range (Volts)
3.0-6.0
3.0-6.0
Number of Instructions
58
58
Packages
64-pin DIP;
68-pin LCC,
68-pin TQFP
64-pin DIP;
68-pin LCC,
68-pin TQFP
All PIC16/17 Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability.
DS30234D-page 314
 1997 Microchip Technology Inc.
PIC16C6X
PIN COMPATIBILITY
Devices that have the same package type and VDD,
VSS and MCLR pin locations are said to be pin
compatible. This allows these different devices to
operate in the same socket. Compatible devices may
only requires minor software modification to allow
proper operation in the application socket
(ex., PIC16C56 and PIC16C61 devices). Not all
devices in the same package size are pin compatible;
for example, the PIC16C62 is compatible with the
PIC16C63, but not the PIC16C55.
Pin compatibility does not mean that the devices offer
the same features. As an example, the PIC16C54 is
pin compatible with the PIC16C71, but does not have
an A/D converter, weak pull-ups on PORTB, or
interrupts.
TABLE E-1:
PIN COMPATIBLE DEVICES
Pin Compatible Devices
Package
PIC12C508, PIC12C509, PIC12C671, PIC12C672
8-pin
PIC16C154, PIC16CR154, PIC16C156,
PIC16CR156, PIC16C158, PIC16CR158,
PIC16C52, PIC16C54, PIC16C54A,
PIC16CR54A,
PIC16C56,
PIC16C58A, PIC16CR58A,
PIC16C61,
PIC16C554, PIC16C556, PIC16C558
PIC16C620, PIC16C621, PIC16C622
PIC16C641, PIC16C642, PIC16C661, PIC16C662
PIC16C710, PIC16C71, PIC16C711, PIC16C715
PIC16F83, PIC16CR83,
PIC16F84A, PIC16CR84
18-pin,
20-pin
PIC16C55, PIC16C57, PIC16CR57B
28-pin
PIC16CR62, PIC16C62A, PIC16C63, PIC16CR63,
PIC16C66, PIC16C72, PIC16C73A, PIC16C76
28-pin
PIC16CR64, PIC16C64A, PIC16C65A,
PIC16CR65, PIC16C67, PIC16C74A, PIC16C77
40-pin
PIC17CR42, PIC17C42A,
PIC17C43, PIC17CR43, PIC17C44
40-pin
PIC16C923, PIC16C924
64/68-pin
PIC17C756, PIC17C752
64/68-pin
 1997 Microchip Technology Inc.
DS30234D-page 315
PIC16C6X
NOTES:
DS30234D-page 316
 1997 Microchip Technology Inc.
PIC16C6X
INDEX
Numerics
9-bit Receive Enable bit, RX9 ........................................... 106
9-bit Transmit Enable bit, TX9 .......................................... 105
9th bit of received data, RX9D .......................................... 106
9th bit of transmit data, TX9D ........................................... 105
A
Absolute Maximum
Ratings.............................. 163, 183, 199, 215, 231, 247, 263
ACK..................................................................... 96, 100, 101
ALU ....................................................................................... 9
Application Notes
AN552 (Implementing Wake-up on Key Stroke) ......... 53
AN556 (Implementing a Table Read) ......................... 48
AN594 (Using the CCP Modules) ............................... 77
Architectural Overview .......................................................... 9
B
Baud Rate Formula........................................................... 107
Baud Rate Generator........................................................ 107
Baud Rates
Asynchronous Mode ................................................. 108
Error, Calculating ...................................................... 107
RX Pin Sampling, Timing Diagrams.................. 110, 111
Sampling ................................................................... 110
Synchronous Mode ................................................... 108
BF ......................................................................... 84, 89, 100
Block Diagrams
Capture Mode Operation ............................................ 78
Compare Mode ........................................................... 79
Crystal Oscillator, Ceramic Resonator...................... 125
External Brown-out Protection .................................. 135
External Parallel Resonant Crystal Circuit ................ 127
External Power-on Reset .......................................... 135
External Series Resonant Crystal Circuit.................. 127
I2C Mode..................................................................... 99
In-circuit Programming Connections......................... 142
Interrupt Logic ........................................................... 137
On-chip Reset Circuit................................................ 128
Parallel Slave Port, PORTD-PORTE .......................... 61
PIC16C61 ................................................................... 10
PIC16C62 ................................................................... 11
PIC16C62A ................................................................. 11
PIC16C63 ................................................................... 12
PIC16C64 ................................................................... 11
PIC16C64A ................................................................. 11
PIC16C65 ................................................................... 12
PIC16C65A ................................................................. 12
PIC16C66 ................................................................... 13
PIC16C67 ................................................................... 13
PIC16CR62................................................................. 11
PIC16CR63................................................................. 12
PIC16CR64................................................................. 11
PIC16CR65................................................................. 12
PORTC ....................................................................... 55
PORTD (I/O Mode) ..................................................... 57
PORTE (I/O Mode) ..................................................... 58
PWM ........................................................................... 80
RA3:RA0 pins ............................................................. 51
RA4/T0CKI pin ............................................................ 51
RA5 pin ....................................................................... 51
RB3:RB0 pins ............................................................. 54
RB7:RB4 pins ....................................................... 53, 54
RC Oscillator Mode................................................... 127
 1997 Microchip Technology Inc.
SPI Master/Slave Connection......................................87
SSP in I2C Mode .........................................................99
SSP in SPI Mode...................................................86, 91
Timer0 .........................................................................65
Timer0/WDT Prescaler ................................................68
Timer1 .........................................................................72
Timer2 .........................................................................75
USART Receive ........................................................114
USART Transmit .......................................................112
Watchdog Timer ........................................................140
BOR...................................................................................129
BOR.............................................................................47, 131
BRGH ................................................................................105
Brown-out Reset (BOR).....................................................129
Brown-out Reset Status bit, BOR ........................................47
Buffer Full Status bit, BF................................................84, 89
C
C ..........................................................................................35
C Compiler.........................................................................161
Capture
Block Diagram .............................................................78
Mode............................................................................78
Pin Configuration .........................................................78
Prescaler .....................................................................79
Software Interrupt ........................................................78
Capture Interrupt .................................................................78
Capture/Compare/PWM (CCP)
Capture Mode..............................................................78
Capture Mode Block Diagram .....................................78
CCP1 ...........................................................................77
CCP2 ...........................................................................77
Compare Mode............................................................79
Compare Mode Block Diagram ...................................79
Overview......................................................................63
Prescaler .....................................................................79
PWM Block Diagram ...................................................80
PWM Mode..................................................................80
PWM, Example Frequencies/Resolutions ...................81
Section.........................................................................77
Carry......................................................................................9
Carry bit ...............................................................................35
CCP Module Interaction ......................................................77
CCP pin Configuration.........................................................78
CCP to Timer Resource Use ...............................................77
CCP1 Interrupt Enable bit, CCP1IE.....................................38
CCP1 Interrupt Flag bit, CCP1IF .........................................41
CCP1 Mode Select bits .......................................................78
CCP1CON .............................................24, 26, 28, 30, 32, 34
CCP1IE................................................................................38
CCP1IF................................................................................41
CCP1M3:CCM1M0..............................................................78
CCP1X:CCP1Y....................................................................78
CCP2 Interrupt Enable bit, CCP2IE.....................................45
CCP2 Interrupt Flag bit, CCP2IF .........................................46
CCP2 Mode Select bits .......................................................78
CCP2CON .............................................24, 26, 28, 30, 32, 34
CCP2IE................................................................................45
CCP2IF................................................................................46
CCP2M3:CCP2M0 ..............................................................78
CCP2X:CCP2Y....................................................................78
CCPR1H................................................24, 26, 28, 30, 32, 34
CCPR1L ................................................24, 26, 28, 30, 32, 34
CCPR2H................................................24, 26, 28, 30, 32, 34
CCPR2L ................................................24, 26, 28, 30, 32, 34
CKE .....................................................................................89
CKP ...............................................................................85, 90
DS30234D-page 317
PIC16C6X
Clearing Interrupts............................................................... 53
Clock Polarity Select bit, CKP ....................................... 85, 90
Clock Polarity, SPI Mode .................................................... 87
Clock Source Select bit, CSRC......................................... 105
Clocking Scheme ................................................................ 18
Code Examples
Changing Between Capture Prescalers...................... 79
Ensuring Interrupts are Globally Disabled ................ 136
Indirect Addressing ..................................................... 49
Initializing PORTA....................................................... 51
Initializing PORTB....................................................... 53
Initializing PORTC....................................................... 55
Loading the SSPBUF Register ................................... 86
Loading the SSPBUF register..................................... 91
Reading a 16-bit Free-running Timer.......................... 73
Read-Modify-Write on an I/O Port............................... 60
Saving Status, W, and PCLATH Registers ............... 139
Subroutine Call, Page0 to Page1................................ 49
Code Protection ................................................................ 142
Compare
Block Diagram............................................................. 79
Mode ........................................................................... 79
Pin Configuration ........................................................ 79
Software Interrupt ....................................................... 79
Special Event Trigger.................................................. 79
Computed GOTO ................................................................ 48
Configuration Bits.............................................................. 123
Configuration Word, Diagram............................................ 124
Connecting Two Microcontrollers........................................ 87
Continuous Receive Enable bit, CREN............................. 106
CREN ................................................................................ 106
CSRC ................................................................................ 105
D
D/A ................................................................................ 84, 89
Data/Address bit, D/A.................................................... 84, 89
Data Memory
Organization................................................................ 20
Section ........................................................................ 20
Data Sheet
Compatibility ............................................................. 307
Modifications ............................................................. 307
What’s New............................................................... 308
DC ....................................................................................... 35
DC CHARACTERISTICS .. 164, 184, 200, 216, 232, 248, 264
Development Support ....................................................... 159
Development Tools ........................................................... 159
Device Drawings
18-Lead Ceramic CERDIP Dual In-line
with Window (300 mil) ............................................... 296
18-Lead Plastic Dual In-line (300 mil) ....................... 291
18-Lead Plastic Surface Mount
(SOIC - Wide, 300 mil Body).................................... 294
28-Lead Ceramic CERDIP Dual In-line with
Window (300 mil)) ..................................................... 297
28-Lead Ceramic Side Brazed Dual In-Line
with Window (300 mil) ............................................... 299
28-Lead Plastic Dual In-line (300 mil) ....................... 292
28-Lead Plastic Surface Mount
(SOIC - Wide, 300 mil Body)..................................... 295
28-Lead Plastic Surface Mount
(SSOP - 209 mil Body 5.30 mm)............................... 300
40-Lead Ceramic CERDIP Dual In-line
with Window (600 mil) ............................................... 298
40-Lead Plastic Dual In-line (600 mil) ....................... 293
44-Lead Plastic Leaded Chip Carrier (Square)......... 301
DS30234D-page 318
44-Lead Plastic Surface Mount (MQFP
10x10 mm Body 1.6/0.15 mm Lead Form) ....... 302, 303
Device Varieties.................................................................... 7
Digit Carry............................................................................. 9
Digit Carry bit ...................................................................... 35
Direct Addressing ............................................................... 49
E
Electrical Characteristics .. 163, 183, 199, 215, 231, 247, 263
External Clock Synchronization, TMR0 .............................. 67
F
Family of Devices
PIC12CXXX.............................................................. 309
PIC14C000 ............................................................... 309
PIC16C15X............................................................... 310
PIC16C55X............................................................... 311
PIC16C5X................................................................. 310
PIC16C62X and PIC16C64X.................................... 311
PIC16C6X..................................................................... 6
PIC16C7XX .............................................................. 312
PIC16C8X................................................................. 313
PIC16C9XX .............................................................. 313
PIC17CXX ................................................................ 314
FERR ................................................................................ 106
Framing Error bit, FERR ................................................... 106
FSR......................... 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
Fuzzy Logic Dev. System (fuzzyTECH-MP)........... 159, 161
G
General Description .............................................................. 5
General Purpose Registers ................................................ 20
GIE...................................................................................... 37
Global Interrupt Enable bit, GIE.......................................... 37
Graphs
PIC16C6X................................................................. 281
PIC16C61 ................................................................. 173
H
High Baud Rate Select bit, BRGH .................................... 105
I
I/O Ports, Section................................................................ 51
I2C
Addressing................................................................ 100
Addressing I2C Devices.............................................. 96
Arbitration ................................................................... 98
Block Diagram ............................................................ 99
Clock Synchronization ................................................ 98
Combined Format....................................................... 97
I2C Operation.............................................................. 99
I2C Overview .............................................................. 95
Initiating and Terminating Data Transfer .................... 95
Master Mode............................................................. 103
Master-Receiver Sequence ........................................ 97
Master-Transmitter Sequence .................................... 97
Mode........................................................................... 99
Mode Selection........................................................... 99
Multi-master................................................................ 98
Multi-Master Mode.................................................... 103
Reception ................................................................. 101
Reception Timing Diagram ....................................... 101
SCL and SDA pins.................................................... 100
Slave Mode............................................................... 100
START........................................................................ 95
STOP.................................................................... 95, 96
 1997 Microchip Technology Inc.
PIC16C6X
Transfer Acknowledge ................................................ 96
Transmission............................................................. 102
ID Locations ...................................................................... 142
IDLE_MODE ..................................................................... 104
In-circuit Serial Programming............................................ 142
INDF...................................................... 24, 26, 28, 30, 32, 34
Indirect Addressing ............................................................. 49
Instruction Cycle ................................................................. 18
Instruction Flow/Pipelining .................................................. 18
Instruction Format ............................................................. 143
Instruction Set
ADDLW ..................................................................... 145
ADDWF..................................................................... 145
ANDLW ..................................................................... 145
ANDWF..................................................................... 145
BCF........................................................................... 146
BSF ........................................................................... 146
BTFSC ...................................................................... 146
BTFSS ...................................................................... 147
CALL ......................................................................... 147
CLRF......................................................................... 148
CLRW ....................................................................... 148
CLRWDT................................................................... 148
COMF ....................................................................... 149
DECF ........................................................................ 149
DECFSZ.................................................................... 149
GOTO ....................................................................... 150
INCF.......................................................................... 150
INCFSZ ..................................................................... 151
IORLW ...................................................................... 151
IORWF ...................................................................... 152
MOVF........................................................................ 152
MOVLW .................................................................... 152
MOVWF .................................................................... 152
NOP .......................................................................... 153
OPTION .................................................................... 153
RETFIE ..................................................................... 153
RETLW ..................................................................... 154
RETURN ................................................................... 154
RLF ........................................................................... 155
RRF........................................................................... 155
SLEEP ...................................................................... 156
SUBLW ..................................................................... 156
SUBWF ..................................................................... 157
SWAPF ..................................................................... 157
TRIS.......................................................................... 157
XORLW..................................................................... 158
XORWF..................................................................... 158
Section ...................................................................... 143
Summary Table......................................................... 144
INTCON .................. 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
INTE.................................................................................... 37
INTEDG .............................................................................. 36
Interrupt Edge Select bit, INTEDG...................................... 36
Interrupt on Change Feature............................................... 53
Interrupts
Section ...................................................................... 136
CCP ............................................................................ 78
CCP1 .......................................................................... 38
CCP1 Flag bit.............................................................. 41
CCP2 Enable bit ......................................................... 45
CCP2 Flag bit.............................................................. 46
Context Saving.......................................................... 139
Parallel Slave Port Flag bit.......................................... 43
Parallel Slave Prot Read/Write Enable bit .................. 39
Port RB ....................................................................... 53
RB0/INT .............................................................. 54, 138
 1997 Microchip Technology Inc.
RB0/INT Timing Diagram ..........................................138
Receive Flag bit...........................................................42
Timer0 .........................................................................65
Timer0, Timing.............................................................66
Timing Diagram, Wake-up from SLEEP ....................142
TMR0.........................................................................138
USART Receive Enable bit .........................................39
USART Transmit Enable bit ........................................39
USART Transmit Flag bit.............................................42
Wake-up ....................................................................141
Wake-up from SLEEP ...............................................141
INTF.....................................................................................37
IRP.......................................................................................35
L
Loading the Program Counter .............................................48
M
MPASM Assembler ...................................................159, 160
MPLAB-C...........................................................................161
MPSIM Software Simulator .......................................159, 161
O
OERR ................................................................................106
One-Time-Programmable Devices ........................................7
OPCODE ...........................................................................143
Open-Drain ..........................................................................51
OPTION.................................................25, 27, 29, 31, 33, 34
Oscillator Start-up Timer (OST) .................................123, 129
Oscillators
Block Diagram, External Parallel Resonant Crystal ..127
Capacitor Selection .....................................................73
Configuration .............................................................125
External Crystal Circuit ..............................................127
HS......................................................................125, 130
LP ......................................................................125, 130
RC, Block Diagram ....................................................127
RC, Section ...............................................................127
XT ..............................................................................125
Overrun Error bit, OERR ...................................................106
P
P ....................................................................................84, 89
Packaging Information.......................................................291
Parallel Slave Port
PORTD ........................................................................57
Section.........................................................................61
Parallel Slave Port Interrupt Flag bit, PSPIF .......................43
Parallel Slave Port Read/Write Interrupt Enable bit, PSPIE 39
PCL..........................24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
PCLATH ............24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 48
PCON ............................................25, 27, 29, 31, 33, 34, 130
PD................................................................................35, 131
PEIE ....................................................................................37
Peripheral Interrupt Enable bit, PEIE...................................37
PICDEM-1 Low-Cost PIC16/17 Demo Board ............159, 160
PICDEM-2 Low-Cost PIC16CXX Demo Board..........159, 160
PICDEM-3 Low-Cost PIC16C9XXX Demo Board .............160
PICMASTER In-Circuit Emulator.......................................159
PICSTART Low-Cost Development System .....................159
PIE1.......................................................25, 27, 29, 31, 33, 34
PIE2.......................................................25, 27, 29, 31, 33, 34
Pin Compatible Devices ....................................................315
Pin Functions
MCLR/VPP ...................................................................16
DS30234D-page 319
PIC16C6X
OSC1/CLKIN............................................................... 16
OSC2/CLKOUT........................................................... 16
PORTA........................................................................ 52
PORTB........................................................................ 54
PORTC ....................................................................... 55
PORTD ....................................................................... 57
PORTE........................................................................ 59
RA4/T0CKI............................................................ 16, 52
RA5/SS ................................................................. 16, 52
RB0/INT ................................................................ 16, 54
RB6 ........................................................................... 142
RB7 ........................................................................... 142
RC0/T1OSI/T1CKI ...................................................... 55
RC0/T1OSO/T1CKI .............................................. 16, 55
RC1/T1OSI ................................................................. 55
RC1/T1OSI/CCP2................................................. 16, 55
RC1/T1OSO................................................................ 55
RC2/CCP1 ...................................................... 16, 55, 56
RC3/SCK/SCL ................................................ 16, 55, 56
RC4/SDI/SDA ................................................. 16, 55, 56
RC5/SDO ........................................................ 16, 55, 56
RC6/TX/CK ..................................... 16, 55, 56, 105–120
RC7/RX/DT ..................................... 16, 55, 56, 105–120
RD7/PSP7:RD0/PSP0 .......................................... 17, 57
RE0/RD........................................................... 17, 59, 61
RE1/WR .......................................................... 17, 59, 61
RE2/CS ........................................................... 17, 59, 61
SCK....................................................................... 86–88
SDI ........................................................................ 86–88
SDO ...................................................................... 86–88
SS ......................................................................... 86–88
VDD ............................................................................. 17
VSS .............................................................................. 17
PIR1 ...................................................... 24, 26, 28, 30, 32, 34
PIR2 ...................................................... 24, 26, 28, 30, 32, 34
POP..................................................................................... 48
POR ............................................................................ 47, 131
POR Time-Out Sequence on Power-Up ........................... 134
Port RB Interrupt ................................................................. 53
PORTA............................................ 24, 26, 28, 30, 32, 34, 51
PORTB............................................ 24, 26, 28, 30, 32, 34, 53
PORTB Interrupt on Change............................................. 138
PORTB Pull-up Enable bit, RBPU....................................... 36
PORTC............................................ 24, 26, 28, 30, 32, 34, 55
PORTD............................................ 24, 26, 28, 30, 32, 34, 57
PORTE............................................ 24, 26, 28, 30, 32, 34, 58
Ports
Bi-directional ............................................................... 60
I/O Programming Considerations................................ 60
PORTA........................................................................ 16
PORTB........................................................................ 16
PORTC ....................................................................... 16
PORTD ....................................................................... 17
PORTE........................................................................ 17
Successive Operations on an I/O Port........................ 60
Power/Control Status Register, PCON ............................. 130
Power-down bit ................................................................... 35
Power-down Mode ............................................................ 141
Power-on Reset (POR) ..................................................... 129
Power-on Reset Status bit, POR......................................... 47
Power-up Timer (PWRT)........................................... 123, 129
PR2 ....................................................... 25, 27, 29, 31, 33, 34
Prescaler ............................................................................. 68
Prescaler Assignment bit, PSA ........................................... 36
Prescaler Rate Select bits, PS2:PS0 .................................. 36
PRO MATE Universal Programmer .................................. 159
Program Memory
DS30234D-page 320
Map....................................................................... 19, 20
Organization ............................................................... 19
Paging ........................................................................ 48
Section........................................................................ 19
Programming While In-circuit............................................ 142
PS2:PS0 ............................................................................. 36
PSA..................................................................................... 36
PSPIE ................................................................................. 39
PSPIF ................................................................................. 43
Pull-ups............................................................................... 53
PUSH.................................................................................. 48
PWM
Block Diagram ............................................................ 80
Calculations ................................................................ 81
Mode........................................................................... 80
Output Timing ............................................................. 80
PWM Least Significant bits ................................................. 78
Q
Quadrature Clocks.............................................................. 18
Quick-Turnaround-Production .............................................. 7
R
R/W bit ............................................ 84, 89, 96, 100, 101, 102
RA0 pin ............................................................................... 51
RA1 pin ............................................................................... 51
RA2 pin ............................................................................... 51
RA3 pin ............................................................................... 51
RA4/T0CKI pin.................................................................... 51
RA5 pin ............................................................................... 51
RB Port Change Interrupt Enable bit, RBIE........................ 37
RB Port Change Interrupt Flag bit, RBIF ............................ 37
RB0..................................................................................... 54
RB0/INT ............................................................................ 138
RB0/INT External Interrupt Enable bit, INTE ...................... 37
RB0/INT External Interrupt Flag bit, INTF........................... 37
RB1..................................................................................... 54
RB2..................................................................................... 54
RB3..................................................................................... 54
RB4..................................................................................... 53
RB5..................................................................................... 53
RB6..................................................................................... 53
RB7..................................................................................... 53
RBIE ................................................................................... 37
RBIF.................................................................................... 37
RBPU............................................................................ 36, 53
RC Oscillator..................................................................... 130
RCIE ................................................................................... 39
RCIF ................................................................................... 42
RCREG................................................. 24, 26, 28, 30, 32, 34
RCSTA.......................................... 24, 26, 28, 30, 32, 34, 106
RCV_MODE ..................................................................... 104
Read Only Memory............................................................... 7
Read/Write bit Information, R/W ................................... 84, 89
Receive and Control Register........................................... 106
Receive Overflow Detect bit, SSPOV ................................. 85
Receive Overflow Indicator bit, SSPOV.............................. 90
Register Bank Select bit, Indirect........................................ 35
Register Bank Select bits. Direct ........................................ 35
 1997 Microchip Technology Inc.
PIC16C6X
Registers
CCP1CON
Diagram .............................................................. 78
Section................................................................ 78
Summary .................................... 24, 26, 28, 30, 32
CCP2CON
Diagram .............................................................. 78
Section................................................................ 78
Summary ................................................ 26, 30, 32
CCPR1H
Summary .................................... 24, 26, 28, 30, 32
CCPR1L
Summary .................................... 24, 26, 28, 30, 32
CCPR2H
Summary ................................................ 26, 30, 32
CCPR2L
Summary ................................................ 26, 30, 32
FSR
Indirect Addressing ............................................. 49
Summary .............................. 24, 26, 28, 30, 32, 34
INDF
Indirect Addressing ............................................. 49
Summary .............................. 24, 26, 28, 30, 32, 34
INTCON
Diagram .............................................................. 37
Section................................................................ 37
Summary .............................. 24, 26, 28, 30, 32, 34
OPTION
Diagram .............................................................. 36
Section................................................................ 36
Summary .............................. 25, 27, 29, 31, 33, 34
PCL
Section................................................................ 48
Summary .............................. 24, 26, 28, 30, 32, 34
PCLATH
Section................................................................ 48
Summary .............................. 24, 26, 28, 30, 32, 34
PCON
Diagram .............................................................. 47
Section................................................................ 47
Summary .................................... 25, 27, 29, 31, 33
PIE1
Diagram .............................................................. 40
Section................................................................ 38
Summary .................................... 25, 27, 29, 31, 33
PIE2
Diagram .............................................................. 45
Section................................................................ 45
Summary ................................................ 27, 31, 33
PIR1
Diagram .............................................................. 44
Section................................................................ 41
Summary .................................... 24, 26, 28, 30, 32
PIR2
Diagram .............................................................. 46
Section................................................................ 46
Summary ................................................ 26, 30, 32
PORTA
Section................................................................ 51
Summary .................................... 24, 26, 28, 30, 32
PORTB
Section................................................................ 53
Summary .............................. 24, 26, 28, 30, 32, 34
PORTC
Section................................................................ 55
Summary .................................... 24, 26, 28, 30, 32
 1997 Microchip Technology Inc.
PORTD
Section ................................................................57
Summary .................................................28, 30, 32
PORTE
Section ................................................................58
Summary .................................................28, 30, 32
PR2
Summary .....................................25, 27, 29, 31, 33
RCREG
Summary .................................................26, 30, 32
RCSTA
Diagram.............................................................106
Summary .................................................26, 30, 32
SPBRG
Summary .................................................27, 31, 33
SSPBUF
Section ................................................................86
Summary .....................................24, 26, 28, 30, 32
SSPCON
Diagram...............................................................85
Summary .....................................24, 26, 28, 30, 32
SSPSR
Section ................................................................86
SSPSTAT ....................................................................89
Diagram...............................................................84
Section ................................................................84
Summary .....................................25, 27, 29, 31, 33
STATUS
Diagram...............................................................35
Section ................................................................35
Summary ...............................24, 26, 28, 30, 32, 34
T1CON
Diagram...............................................................71
Section ................................................................71
Summary .....................................24, 26, 28, 30, 32
T2CON
Diagram...............................................................75
Section ................................................................75
Summary .....................................24, 26, 28, 30, 32
TMR0
Summary ...............................24, 26, 28, 30, 32, 34
TMR1H
Summary .....................................24, 26, 28, 30, 32
TMR1L
Summary .....................................24, 26, 28, 30, 32
TMR2...........................................................................75
Summary .....................................24, 26, 28, 30, 32
TRISA
Section ................................................................51
Summary .....................................25, 27, 29, 31, 33
TRISB
Section ................................................................53
Summary ...............................25, 27, 29, 31, 33, 34
TRISC
Section ................................................................55
Summary .....................................25, 27, 29, 31, 33
TRISD
Section ................................................................57
Summary .................................................29, 31, 33
TRISE
Diagram...............................................................58
Section ................................................................58
Summary .................................................29, 31, 33
TXREG
Summary .................................................26, 30, 32
DS30234D-page 321
PIC16C6X
TXSTA
Diagram ............................................................ 105
Section .............................................................. 105
Summary....................................................... 31, 33
W................................................................................... 9
Special Function Registers, Initialization
Conditions ................................................................. 132
Special Function Registers, Reset Conditions.......... 131
Special Function Register Summary... 24, 26, 28, 30, 32
File Maps .................................................................... 21
Resets ............................................................................... 128
ROM...................................................................................... 7
RP0 bit .......................................................................... 20, 35
RP1 ..................................................................................... 35
RX9 ................................................................................... 106
RX9D................................................................................. 106
S
S.................................................................................... 84, 89
SCI - See Universal Synchronous Asynchronous Receiver
Transmitter (USART)
SCK..................................................................................... 86
SCL ................................................................................... 100
SDI ...................................................................................... 86
SDO .................................................................................... 86
Serial Port Enable bit, SPEN............................................. 106
Serial Programming .......................................................... 142
Serial Programming, Block Diagram ................................. 142
Serialized Quick-Turnaround-Production .............................. 7
Single Receive Enable bit, SREN ..................................... 106
Slave Mode
SCL ........................................................................... 100
SDA........................................................................... 100
SLEEP Mode............................................................. 123, 141
SMP .................................................................................... 89
Software Simulator (MPSIM)............................................. 161
SPBRG.................................................. 25, 27, 29, 31, 33, 34
Special Features, Section ................................................. 123
SPEN ................................................................................ 106
SPI
Block Diagram....................................................... 86, 91
Master Mode ............................................................... 92
Master Mode Timing ................................................... 93
Mode ........................................................................... 86
Serial Clock................................................................. 91
Serial Data In .............................................................. 91
Serial Data Out ........................................................... 91
Slave Mode Timing ..................................................... 94
Slave Mode Timing Diagram....................................... 93
Slave Select ................................................................ 91
SPI clock ..................................................................... 92
SPI Mode .................................................................... 91
SSPCON..................................................................... 90
SSPSTAT.................................................................... 89
SPI Clock Edge Select bit, CKE.......................................... 89
SPI Data Input Sample Phase Select bit, SMP................... 89
SPI Mode ............................................................................ 86
SREN ................................................................................ 106
SS ....................................................................................... 86
SSP
Module Overview ........................................................ 83
Section ........................................................................ 83
SSPBUF...................................................................... 92
SSPCON..................................................................... 90
SSPSR........................................................................ 92
SSPSTAT.................................................................... 89
DS30234D-page 322
SSP in I2C Mode - See I2C
SSPADD ......................................... 25, 27, 29, 31, 33, 34, 99
SSPBUF ......................................... 24, 26, 28, 30, 32, 34, 99
SSPCON................................... 24, 26, 28, 30, 32, 34, 85, 90
SSPEN.......................................................................... 85, 90
SSPIE ................................................................................. 38
SSPIF ................................................................................. 41
SSPM3:SSPM0 ............................................................ 85, 90
SSPOV ................................................................. 85, 90, 100
SSPSTAT ................................. 25, 27, 29, 31, 33, 34, 84, 99
SSPSTAT Register ............................................................. 89
Stack................................................................................... 48
Start bit, S ..................................................................... 84, 89
STATUS.................. 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34
Status bits ................................................................. 130, 131
Status Bits During Various Resets.................................... 131
Stop bit, P ..................................................................... 84, 89
Switching Prescalers .......................................................... 69
SYNC,USART Mode Select bit, SYNC............................. 105
Synchronizing Clocks, TMR0.............................................. 67
Synchronous Serial Port (SSP)
Block Diagram, SPI Mode .......................................... 86
SPI Master/Slave Diagram ......................................... 87
SPI Mode.................................................................... 86
Synchronous Serial Port Enable bit, SSPEN................ 85, 90
Synchronous Serial Port Interrupt Enable bit, SSPIE ......... 38
Synchronous Serial Port Interrupt Flag bit, SSPIF ............. 41
Synchronous Serial Port Mode Select bits,
SSPM3:SSPM0 ............................................................ 85, 90
Synchronous Serial Port Module ........................................ 83
Synchronous Serial Port Status Register ........................... 89
T
T0CS................................................................................... 36
T0IE .................................................................................... 37
T0IF .................................................................................... 37
T0SE................................................................................... 36
T1CKPS1:T1CKPS0........................................................... 71
T1CON.................................................. 24, 26, 28, 30, 32, 34
T1OSCEN........................................................................... 71
T1SYNC.............................................................................. 71
T2CKPS1:T2CKPS0........................................................... 75
T2CON............................................ 24, 26, 28, 30, 32, 34, 75
TIme-out ........................................................................... 130
Time-out bit......................................................................... 35
Time-out Sequence .......................................................... 130
Timer Modules
Overview, all ............................................................... 63
Timer0
Block Diagram .................................................... 65
Counter Mode..................................................... 65
External Clock .................................................... 67
Interrupt .............................................................. 65
Overview............................................................. 63
Prescaler ............................................................ 68
Section................................................................ 65
Timer Mode ........................................................ 65
Timing DiagramTiiming Diagrams
Timer0 ................................................................ 65
TMR0 register..................................................... 65
Timer1
Block Diagram .................................................... 72
Capacitor Selection ............................................ 73
Counter Mode, Asynchronous ............................ 73
Counter Mode, Synchronous.............................. 72
External Clock .................................................... 73
Oscillator............................................................. 73
 1997 Microchip Technology Inc.
PIC16C6X
Overview............................................................. 63
Prescaler............................................................. 72
Read/Write in Asynchronous Counter Mode ...... 73
Section................................................................ 71
Synchronizing with External Clock...................... 72
Timer Mode......................................................... 72
TMR1 Register Pair ............................................ 71
Timer2
Block Diagram .................................................... 75
Overview............................................................. 63
Postscaler ........................................................... 75
Prescaler............................................................. 75
Timer0 Clock Synchronization, Delay ................................. 67
TImer0 Interrupt ................................................................ 138
Timer1 Clock Source Select bit, TMR1CS .......................... 71
Timer1 External Clock Input Synchronization
Control bit, T1SYNC ........................................................... 71
Timer1 Input Clock Prescale Select bits ............................. 71
Timer1 Mode Selection ....................................................... 78
Timer1 On bit, TMR1ON ..................................................... 71
Timer1 Oscillator Enable Control bit, T1OSCEN ................ 71
Timer2 Clock Prescale Select bits,
T2CKPS1:T2CKPS0 ........................................................... 75
Timer2 Module .................................................................... 75
Timer2 On bit, TMR2ON ..................................................... 75
Timer2 Output Postscale Select bits,
TOUTPS3:TOUTPS0.......................................................... 75
Timing Diagrams
Brown-out Reset ....................................................... 129
I2C Clock Synchronization .......................................... 98
I2C Data Transfer Wait State ...................................... 96
I2C Multi-Master Arbitration......................................... 98
I2C Reception (7-bit Address) ................................... 101
PIC16C61
CLKOUT and I/O .............................................. 170
External Clock................................................... 169
Oscillator Start-up Timer ................................... 171
Power-up Timer ................................................ 171
Reset ................................................................ 171
Timer0............................................................... 172
Watchdog Timer ............................................... 171
PIC16C62
Capture/Compare/PWM ................................... 193
CLKOUT and I/O .............................................. 190
External Clock................................................... 189
I2C Bus Data..................................................... 197
I2C Bus Start/Stop Bits ..................................... 196
Oscillator Start-up Timer ................................... 191
Power-up Timer ................................................ 191
Reset ................................................................ 191
SPI Mode .......................................................... 195
Timer0............................................................... 192
Timer1............................................................... 192
Watchdog Timer ............................................... 191
PIC16C62A
Brown-out Reset ............................................... 207
Capture/Compare/PWM ................................... 209
CLKOUT and I/O .............................................. 206
External Clock................................................... 205
I2C Bus Data..................................................... 213
I2C Bus Start/Stop Bits ..................................... 212
Oscillator Start-up Timer ................................... 207
Power-up Timer ................................................ 207
Reset ................................................................ 207
SPI Mode .......................................................... 211
Timer0............................................................... 208
Timer1............................................................... 208
 1997 Microchip Technology Inc.
Watchdog Timer ................................................207
PIC16C63
Brown-out Reset................................................239
Capture/Compare/PWM ....................................241
CLKOUT and I/O ...............................................238
External Clock ...................................................237
I2C Bus Data .....................................................245
I2C Bus Start/Stop Bits ......................................244
Oscillator Start-up Timer ...................................239
Power-up Timer.................................................239
Reset .................................................................239
SPI Mode...........................................................243
Timer0 ...............................................................240
Timer1 ...............................................................240
USART Synchronous Receive
(Master/Slave) ..................................................246
Watchdog Timer ................................................239
PIC16C64
Capture/Compare/PWM ....................................193
CLKOUT and I/O ...............................................190
External Clock ...................................................189
I2C Bus Data .....................................................197
I2C Bus Start/Stop Bits ......................................196
Oscillator Start-up Timer ...................................191
Parallel Slave Port.............................................194
Power-up Timer.................................................191
Reset .................................................................191
SPI Mode...........................................................195
Timer0 ...............................................................192
Timer1 ...............................................................192
Watchdog Timer ................................................191
PIC16C64A
Brown-out Reset................................................207
Capture/Compare/PWM ....................................209
CLKOUT and I/O ...............................................206
External Clock ...................................................205
I2C Bus Data .....................................................213
I2C Bus Start/Stop Bits ......................................212
Oscillator Start-up Timer ...................................207
Parallel Slave Port.............................................210
Power-up Timer.................................................207
Reset .................................................................207
SPI Mode...........................................................211
Timer0 ...............................................................208
Timer1 ...............................................................208
Watchdog Timer ................................................207
PIC16C65
Capture/Compare/PWM ....................................225
CLKOUT and I/O ...............................................222
External Clock ...................................................221
I2C Bus Data .....................................................229
I2C Bus Start/Stop Bits ......................................228
Oscillator Start-up Timer ...................................223
Parallel Slave Port.............................................226
Reset .................................................................223
SPI Mode...........................................................227
Timer0 ...............................................................224
Timer1 ...............................................................224
USART Synchronous Receive
(Master/Slave) ...................................................230
Watchdog Timer ................................................223
PIC16C65A
Brown-out Reset................................................239
Capture/Compare/PWM ....................................241
CLKOUT and I/O ...............................................238
External Clock ...................................................237
I2C Bus Data .....................................................245
DS30234D-page 323
PIC16C6X
I2C Bus Start/Stop Bits...................................... 244
Oscillator Start-up Timer ................................... 239
Parallel Slave Port ............................................ 242
Power-up Timer ................................................ 239
Reset................................................................. 239
SPI Mode .......................................................... 243
Timer0............................................................... 240
Timer1............................................................... 240
USART Synchronous Receive
(Master/Slave)................................................... 246
Watchdog Timer................................................ 239
PIC16C66
Brown-out Reset ............................................... 271
Capture/Compare/PWM.................................... 273
CLKOUT and I/O............................................... 270
External Clock................................................... 269
I2C Bus Data ..................................................... 279
I2C Bus Start/Stop Bits...................................... 278
Oscillator Start-up Timer ................................... 271
Power-up Timer ................................................ 271
Reset................................................................. 271
Timer0............................................................... 272
Timer1............................................................... 272
USART Synchronous Receive
(Master/Slave)................................................... 280
Watchdog Timer................................................ 271
PIC16C67
Brown-out Reset ............................................... 271
Capture/Compare/PWM.................................... 273
CLKOUT and I/O............................................... 270
External Clock................................................... 269
I2C Bus Data ..................................................... 279
I2C Bus Start/Stop Bits...................................... 278
Oscillator Start-up Timer ................................... 271
Parallel Slave Port ............................................ 274
Power-up Timer ................................................ 271
Reset................................................................. 271
Timer0............................................................... 272
Timer1............................................................... 272
USART Synchronous Receive
(Master/Slave)................................................... 280
Watchdog Timer................................................ 271
PIC16CR62
Capture/Compare/PWM.................................... 209
CLKOUT and I/O............................................... 206
External Clock................................................... 205
I2C Bus Data ..................................................... 213
I2C Bus Start/Stop Bits...................................... 212
Oscillator Start-up Timer ................................... 207
Power-up Timer ................................................ 207
Reset................................................................. 207
SPI Mode .......................................................... 211
Timer0............................................................... 208
Timer1............................................................... 208
Watchdog Timer................................................ 207
DS30234D-page 324
PIC16CR63
Brown-out Reset............................................... 255
Capture/Compare/PWM ................................... 257
CLKOUT and I/O .............................................. 254
External Clock .................................................. 253
I2C Bus Data..................................................... 261
I2C Bus Start/Stop Bits ..................................... 260
Oscillator Start-up Timer................................... 255
Power-up Timer ................................................ 255
Reset ................................................................ 255
SPI Mode.......................................................... 259
Timer0 .............................................................. 256
Timer1 .............................................................. 256
USART Synchronous Receive
(Master/Slave) ................................................. 262
Watchdog Timer ............................................... 255
PIC16CR64
Capture/Compare/PWM ................................... 209
CLKOUT and I/O .............................................. 206
External Clock .................................................. 205
I2C Bus Data..................................................... 213
I2C Bus Start/Stop Bits ..................................... 212
Oscillator Start-up Timer................................... 207
Parallel Slave Port ............................................ 210
Power-up Timer ................................................ 207
Reset ................................................................ 207
SPI Mode.......................................................... 211
Timer0 .............................................................. 208
Timer1 .............................................................. 208
Watchdog Timer ............................................... 207
PIC16CR65
Brown-out Reset............................................... 255
Capture/Compare/PWM ................................... 257
CLKOUT and I/O .............................................. 254
External Clock .................................................. 253
I2C Bus Data..................................................... 261
I2C Bus Start/Stop Bits ..................................... 260
Oscillator Start-up Timer................................... 255
Parallel Slave Port ............................................ 258
Power-up Timer ................................................ 255
Reset ................................................................ 255
SPI Mode.......................................................... 259
Timer0 .............................................................. 256
Timer1 .............................................................. 256
USART Synchronous Receive
(Master/Slave) .................................................. 262
Watchdog Timer ............................................... 255
Power-up Timer ........................................................ 223
PWM Output ............................................................... 80
RB0/INT Interrupt ..................................................... 138
RX Pin Sampling .............................................. 110, 111
SPI Master Mode........................................................ 93
SPI Mode, Master/Slave Mode,
No SS Control............................................................. 88
SPI Mode, Slave Mode With SS Control .................... 88
SPI Slave Mode (CKE = 1) ......................................... 94
SPI Slave Mode Timing (CKE = 0) ............................. 93
Timer0 with External Clock......................................... 67
TMR0 Interrupt Timing................................................ 66
USART Asynchronous Master Transmission ........... 113
USART Asynchronous Master Transmission
(Back to Back) .......................................................... 113
USART Asynchronous Reception ............................ 114
USART Synchronous Reception in
Master Mode............................................................. 119
USART Synchronous Tranmission........................... 117
Wake-up from SLEEP Through Interrupts................ 142
 1997 Microchip Technology Inc.
PIC16C6X
TMR0 .................................................... 24, 26, 28, 30, 32, 34
TMR0 Clock Source Select bit, T0CS................................. 36
TMR0 Interrupt.................................................................... 65
TMR0 Overflow Interrupt Enable bit, T0IE .......................... 37
TMR0 Overflow Interrupt Flag bit, T0IF .............................. 37
TMR0 Prescale Selection Table ......................................... 36
TMR0 Source Edge Select bit, T0SE.................................. 36
TMR1 Overflow Interrupt Enable bit, TMR1IE .................... 38
TMR1 Overflow Interrupt Flag bit, TMR1IF ......................... 41
TMR1CS ............................................................................. 71
TMR1H.................................................. 24, 26, 28, 30, 32, 34
TMR1IE............................................................................... 38
TMR1IF ............................................................................... 41
TMR1L .................................................. 24, 26, 28, 30, 32, 34
TMR1ON............................................................................. 71
TMR2 .................................................... 24, 26, 28, 30, 32, 34
TMR2 Register.................................................................... 75
TMR2 to PR2 Match Interrupt Enable bit, TMR2IE............. 38
TMR2 to PR2 Match Interrupt Flag bit, TMR2IF ................. 41
TMR2IE............................................................................... 38
TMR2IF ............................................................................... 41
TMR2ON............................................................................. 75
TO ............................................................................... 35, 131
TOUTPS3:TOUTPS0.......................................................... 75
Transmit Enable bit, TXEN ............................................... 105
Transmit Shift Register Status bit, TRMT ......................... 105
Transmit Status and Control Register............................... 105
TRISA ............................................. 25, 27, 29, 31, 33, 34, 51
TRISB ............................................. 25, 27, 29, 31, 33, 34, 53
TRISC ....................................... 25, 27, 29, 31, 33, 34, 55, 94
TRISD ............................................. 25, 27, 29, 31, 33, 34, 57
TRISE ............................................. 25, 27, 29, 31, 33, 34, 58
TRMT ................................................................................ 105
TX9 ................................................................................... 105
TX9D................................................................................. 105
TXEN ................................................................................ 105
TXIE .................................................................................... 39
TXIF .................................................................................... 42
TXREG.................................................. 24, 26, 28, 30, 32, 34
TXSTA .......................................... 25, 27, 29, 31, 33, 34, 105
Synchronous Slave Mode
Reception ..........................................................120
Section ..............................................................120
Setting Up Reception ........................................120
Setting Up Transmission ...................................120
Transmit ............................................................120
Transmit Block Diagram ............................................112
Update Address bit, UA .................................................84, 89
USART Receive Interrupt Enable bit, RCIE ........................39
USART Receive Interrupt Flag bit, RCIF.............................42
USART Transmit Interrupt Enable bit, TXIE ........................39
USART Transmit Interrupt Flag bit, TXIF ............................42
UV Erasable Devices.............................................................7
W
Wake-up from Sleep..........................................................141
Wake-up on Key Depression...............................................53
Wake-up Using Interrupts..................................................141
Watchdog Timer (WDT)
Block Diagram ...........................................................140
Period ........................................................................140
Programming Considerations ....................................140
Section.......................................................................140
WCOL............................................................................85, 90
Weak Internal Pull-ups ........................................................53
Write Collision Detect bit, WCOL...................................85, 90
X
XMIT_MODE .....................................................................104
XT ......................................................................................130
Z
Z ..........................................................................................35
Zero bit ............................................................................9, 35
U
UA ................................................................................. 84, 89
Universal Synchronous Asynchronous Receiver Transmitter
(USART)
Asynchronous Mode
Setting Up Transmission................................... 113
Timing Diagram, Master Transmission ............. 113
Transmitter........................................................ 112
Asynchronous Receiver
Setting Up Reception........................................ 115
Timing Diagram ................................................ 114
Asynchronous Receiver Mode
Block Diagram .................................................. 114
Section.............................................................. 114
Section ...................................................................... 105
Synchronous Master Mode
Reception.......................................................... 118
Section.............................................................. 116
Setting Up Reception........................................ 118
Setting Up Transmission................................... 116
Timing Diagram, Reception .............................. 119
Timing Diagram, Transmission ......................... 117
Transmission .................................................... 116
 1997 Microchip Technology Inc.
DS30234D-page 325
PIC16C6X
LIST OF EQUATION AND EXAMPLES
Figure 4-15:
Example 3-1: Instruction Pipeline Flow............................. 18
Example 4-1: Call of a Subroutine in Page 1
from Page 0 ................................................ 49
Example 4-2: Indirect Addressing ..................................... 49
Example 5-1: Initializing PORTA....................................... 51
Example 5-2: Initializing PORTB....................................... 53
Example 5-3: Initializing PORTC ...................................... 55
Example 5-4: Read-Modify-Write Instructions on an
I/O Port ....................................................... 60
Example 7-1: Changing Prescaler (Timer0→WDT) .......... 69
Example 7-2: Changing Prescaler (WDT→Timer0) .......... 69
Example 8-1: Reading a 16-bit
Free-running Timer ..................................... 73
Example 10-1: Changing Between
Capture Prescalers ..................................... 79
Example 10-2: PWM Period and Duty
Cycle Calculation ........................................ 81
Example 11-1: Loading the SSPBUF
(SSPSR) Register....................................... 86
Example 11-2: Loading the SSPBUF
(SSPSR) Register (PIC16C66/67).............. 91
Example 12-1: Calculating Baud Rate Error ..................... 107
Example 13-1: Saving Status and W
Registers in RAM...................................... 139
Example 13-2: Saving Status, W, and
PCLATH Registers in RAM
(All other PIC16C6X devices) ................... 139
Figure 4-16:
Figure 4-17:
Figure 4-18:
Figure 4-19:
Figure 4-20:
Figure 4-21:
Figure 4-22:
Figure 4-23:
Figure 4-24:
Figure 4-25:
Figure 5-1:
Figure 5-2:
Figure 5-3:
Figure 5-4:
Figure 5-5:
Figure 5-6:
Figure 5-7:
LIST OF FIGURES
Figure 5-8:
Figure 3-1:
Figure 3-2:
Figure 3-3:
Figure 3-4:
Figure 3-5:
Figure 4-1:
Figure 4-2:
Figure 4-3:
Figure 4-4:
Figure 4-5:
Figure 4-6:
Figure 4-7:
Figure 4-8:
Figure 4-9:
Figure 4-10:
Figure 4-11:
Figure 4-12:
Figure 4-13:
Figure 4-14:
PIC16C61 Block Diagram........................... 10
PIC16C62/62A/R62/64/64A/R64
Block Diagram ............................................ 11
PIC16C63/R63/65/65A/R65
Block Diagram ............................................ 12
PIC16C66/67 Block Diagram...................... 13
Clock/Instruction Cycle ............................... 18
PIC16C61 Program Memory Map
and Stack.................................................... 19
PIC16C62/62A/R62/64/64A/
R64 Program Memory Map and Stack ....... 19
PIC16C63/R63/65/65A/R65 Program
Memory Map and Stack.............................. 19
PIC16C66/67 Program Memory
Map and Stack............................................ 20
PIC16C61 Register File Map ...................... 20
PIC16C62/62A/R62/64/64A/
R64 Register File Map ................................ 21
PIC16C63/R63/65/65A/R65
Register File Map........................................ 21
PIC16C66/67 Data Memory Map................ 22
STATUS Register
(Address 03h, 83h, 103h, 183h) ................. 35
OPTION Register
(Address 81h, 181h) ................................... 36
INTCON Register
(Address 0Bh, 8Bh, 10Bh 18Bh)................. 37
PIE1 Register for PIC16C62/62A/R62
(Address 8Ch)............................................. 38
PIE1 Register for PIC16C63/R63/66
(Address 8Ch)............................................. 39
PIE1 Register for PIC16C64/64A/R64
(Address 8Ch)............................................. 39
DS30234D-page 326
Figure 5-9:
Figure 5-10:
Figure 5-11:
Figure 5-12:
Figure 5-13:
Figure 7-1:
Figure 7-2:
Figure 7-3:
Figure 7-4:
Figure 7-5:
Figure 7-6:
Figure 8-1:
Figure 8-2:
Figure 9-1:
Figure 9-2:
Figure 10-1:
Figure 10-2:
Figure 10-3:
Figure 10-4:
Figure 10-5:
Figure 11-1:
PIE1 Register for PIC16C65/65A/R65/67
(Address 8Ch) ............................................ 40
PIR1 Register for PIC16C62/62A/R62
(Address 0Ch) ............................................ 41
PIR1 Register for PIC16C63/R63/66
Address 0Ch) ............................................. 42
PIR1 Register for PIC16C64/64A/R64
(Address 0Ch) ............................................ 43
PIR1 Register for PIC16C65/65A/R65/67
(Address 0Ch) ............................................ 44
PIE2 Register (Address 8Dh) ..................... 45
PIR2 Register (Address 0Dh)..................... 46
PCON Register for PIC16C62/64/65
(Address 8Eh) ............................................ 47
PCON Register for PIC16C62A/R62/63/
R63/64A/R64/65A/R65/66/67
(Address 8Eh) ............................................ 47
Loading of PC in Different Situations ......... 48
Direct/Indirect Addressing .......................... 49
Block Diagram of the
RA3:RA0 Pins and the RA5 Pin ................. 51
Block Diagram of the RA4/T0CKI Pin......... 51
Block Diagram of the
RB7:RB4 Pins for PIC16C61/62/64/65....... 53
Block Diagram of the
RB7:RB4 Pins for PIC16C62A/63/R63/
64A/65A/R65/66/67 .................................... 54
Block Diagram of the
RB3:RB0 Pins ............................................ 54
PORTC Block Diagram .............................. 55
PORTD Block Diagram
(In I/O Port Mode)....................................... 57
PORTE Block Diagram
(In I/O Port Mode)...................................... 58
TRISE Register (Address 89h)................... 58
Successive I/O Operation........................... 60
PORTD and PORTE as a Parallel
Slave Port................................................... 61
Parallel Slave Port Write Waveforms ......... 62
Parallel Slave Port Read Waveforms ......... 62
Timer0 Block Diagram................................ 65
Timer0 Timing: Internal Clock/No
Prescaler .................................................... 65
Timer0 Timing: Internal
Clock/Prescale 1:2 ..................................... 66
TMR0 Interrupt Timing ............................... 66
Timer0 Timing With External Clock ............ 67
Block Diagram of the Timer0/WDT
Prescaler .................................................... 68
T1CON: Timer1 Control Register
(Address 10h)............................................. 71
Timer1 Block Diagram................................ 72
Timer2 Block Diagram................................ 75
T2CON: Timer2 Control Register
(Address 12h)............................................. 75
CCP1CON Register (Address 17h) /
CCP2CON Register (Address 1Dh) ........... 78
Capture Mode Operation
Block Diagram ............................................ 78
Compare Mode Operation
Block Diagram ............................................ 79
Simplified PWM Block Diagram.................. 80
PWM Output............................................... 80
SSPSTAT: Sync Serial Port Status
Register (Address 94h) .............................. 84
 1997 Microchip Technology Inc.
PIC16C6X
Figure 11-2:
Figure 11-3:
Figure 11-4:
Figure 11-5:
Figure 11-6:
Figure 11-7:
Figure 11-8:
Figure 11-9:
Figure 11-10:
Figure 11-11:
Figure 11-12:
Figure 11-13:
Figure 11-14:
Figure 11-15:
Figure 11-16:
Figure 11-17:
Figure 11-18:
Figure 11-19:
Figure 11-20:
Figure 11-21:
Figure 11-22:
Figure 11-23:
Figure 11-24:
Figure 11-25:
Figure 11-26:
Figure 11-27:
Figure 12-1:
Figure 12-2:
Figure 12-3:
Figure 12-4:
Figure 12-5:
Figure 12-6:
Figure 12-7:
Figure 12-8:
Figure 12-9:
Figure 12-10:
Figure 12-11:
Figure 12-12:
Figure 12-13:
Figure 12-14:
Figure 13-1:
SSPCON: Sync Serial Port
Control Register (Address 14h) .................. 85
SSP Block Diagram (SPI Mode) ................. 86
SPI Master/Slave Connection..................... 87
SPI Mode Timing, Master Mode or
Slave Mode w/o SS Control........................ 88
SPI Mode Timing, Slave Mode with
SS Control .................................................. 88
SSPSTAT: Sync Serial Port Status
Register (Address 94h)(PIC16C66/67)....... 89
SSPCON: Sync Serial Port Control
Register (Address 14h)(PIC16C66/67)....... 90
SSP Block Diagram (SPI Mode)
(PIC16C66/67)............................................ 91
SPI Master/Slave Connection
(PIC16C66/67)............................................ 92
SPI Mode Timing, Master Mode
(PIC16C66/67)............................................ 93
SPI Mode Timing (Slave Mode With
CKE = 0) (PIC16C66/67) ............................ 93
SPI Mode Timing (Slave Mode With
CKE = 1) (PIC16C66/67) ............................ 94
Start and Stop Conditions........................... 95
7-bit Address Format .................................. 96
I2C 10-bit Address Format .......................... 96
Slave-receiver Acknowledge ...................... 96
Data Transfer Wait State ............................ 96
Master-transmitter Sequence ..................... 97
Master-receiver Sequence.......................... 97
Combined Format ....................................... 97
Multi-master Arbitration
(Two Masters)............................................. 98
Clock Synchronization ................................ 98
SSP Block Diagram (I2C Mode).................. 99
I2C Waveforms for Reception
(7-bit Address) .......................................... 101
I2C Waveforms for Transmission
(7-bit Address) .......................................... 102
Operation of the I2C Module in
IDLE_MODE, RCV_MODE or
XMIT_MODE ............................................ 104
TXSTA: Transmit Status and
Control Register (Address 98h) ................ 105
RCSTA: Receive Status and
Control Register (Address 18h) ................ 106
RX Pin Sampling Scheme (BRGH = 0)
PIC16C63/R63/65/65A/R65) .................... 110
RX Pin Sampling Scheme (BRGH = 1)
(PIC16C63/R63/65/65A/R65) ................... 110
RX Pin Sampling Scheme (BRGH = 1)
(PIC16C63/R63/65/65A/R65) ................... 110
RX Pin Sampling Scheme (BRGH = 0 or = 1)
(PIC16C66/67).......................................... 111
USART Transmit Block Diagram .............. 112
Asynchronous Master Transmission......... 113
Asynchronous Master Transmission
(Back to Back) .......................................... 113
USART Receive Block Diagram ............... 114
Asynchronous Reception.......................... 114
Synchronous Transmission ...................... 117
Synchronous Transmission
through TXEN ........................................... 117
Synchronous Reception
(Master Mode, SREN) .............................. 119
Configuration Word for PIC16C61 ............ 123
 1997 Microchip Technology Inc.
Figure 13-2:
Figure 13-3:
Figure 13-4:
Figure 13-5:
Figure 13-6:
Figure 13-7:
Figure 13-8:
Figure 13-9:
Figure 13-10:
Figure 13-11:
Figure 13-12:
Figure 13-13:
Figure 13-14:
Figure 13-15:
Figure 13-16:
Figure 13-17:
Figure 13-18:
Figure 13-19:
Figure 13-20:
Figure 13-21:
Figure 13-22:
Figure 13-23:
Figure 14-1:
Figure 16-1:
Figure 16-2:
Figure 16-3:
Figure 16-4:
Figure 16-5:
Figure 17-1:
Figure 17-2:
Figure 17-3:
Figure 17-4:
Figure 17-5:
Figure 17-6:
Figure 17-7:
Figure 17-8:
Figure 17-9:
Configuration Word for
PIC16C62/64/65........................................124
Configuration Word for
PIC16C62A/R62/63/R63/64A/R64/
65A/R65/66/67 ..........................................124
Crystal/Ceramic Resonator Operation
(HS, XT or LP OSC Configuration)............125
External Clock Input Operation
(HS, XT or LP OSC Configuration)............125
External Parallel Resonant
Crystal Oscillator Circuit ............................127
External Series Resonant
Crystal Oscillator Circuit ............................127
RC Oscillator Mode ...................................127
Simplified Block Diagram of
On-chip Reset Circuit ................................128
Brown-out Situations .................................129
Time-out Sequence on Power-up
(MCLR not Tied to VDD): Case 1...............134
Time-out Sequence on Power-up
(MCLR Not Tied To VDD): Case 2 .............134
Time-out Sequence on Power-up
(MCLR Tied to VDD) ..................................134
External Power-on Reset Circuit
(For Slow VDD Power-up)..........................135
External Brown-out
Protection Circuit 1 ....................................135
External Brown-out
Protection Circuit 2 ....................................135
Interrupt Logic for PIC16C61.....................137
Interrupt Logic for PIC16C6X ....................137
INT Pin Interrupt Timing ............................138
Watchdog Timer Block Diagram................140
Summary of Watchdog
Timer Registers .........................................140
Wake-up from Sleep
Through Interrupt.......................................142
Typical In-circuit Serial
Programming Connection..........................142
General Format for Instructions.................143
Load Conditions for Device Timing
Specifications ............................................168
External Clock Timing ...............................169
CLKOUT and I/O Timing ...........................170
Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer
Timing........................................................171
Timer0 External Clock Timings .................172
Typical RC Oscillator
Frequency vs. Temperature .....................173
Typical RC Oscillator
Frequency vs. VDD ....................................174
Typical RC Oscillator
Frequency vs. VDD ....................................174
Typical RC Oscillator
Frequency vs. VDD ....................................174
Typical IPD vs. VDD Watchdog Timer
Disabled 25°C ...........................................174
Typical IPD vs. VDD Watchdog Timer
Enabled 25°C ............................................175
Maximum IPD vs. VDD Watchdog
Disabled ....................................................175
Maximum IPD vs. VDD Watchdog
Enabled*....................................................176
VTH (Input Threshold Voltage) of
I/O Pins vs. VDD ........................................176
DS30234D-page 327
PIC16C6X
Figure 17-10: VIH, VIL of MCLR, T0CKI and OSC1
(in RC Mode) vs. VDD ............................... 177
Figure 17-11: VTH (Input Threshold Voltage) of
OSC1 Input (in XT, HS,
and LP Modes) vs. VDD ............................ 177
Figure 17-12: Typical IDD vs. Frequency
(External Clock, 25°C) .............................. 178
Figure 17-13: Maximum IDD vs. Frequency
(External Clock, -40° to +85°C) ................ 178
Figure 17-14: Maximum IDD vs. Frequency
(External Clock, -55° to +125°C) .............. 179
Figure 17-15: WDT Timer Time-out Period vs. VDD ........ 179
Figure 17-16: Transconductance (gm) of HS
Oscillator vs. VDD ...................................... 179
Figure 17-17: Transconductance (gm) of LP
Oscillator vs. VDD ...................................... 180
Figure 17-18: Transconductance (gm) of XT
Oscillator vs. VDD ...................................... 180
Figure 17-19: IOH vs. VOH, VDD = 3V .............................. 180
Figure 17-20: IOH vs. VOH, VDD = 5V .............................. 180
Figure 17-21: IOL vs. VOL, VDD = 3V ............................... 181
Figure 17-22: IOL vs. VOL, VDD = 5V ............................... 181
Figure 18-1: Load Conditions for Device
Timing Specifications................................ 188
Figure 18-2: External Clock Timing............................... 189
Figure 18-3: CLKOUT and I/O Timing........................... 190
Figure 18-4: Reset, Watchdog Timer,
Oscillator Start-up Timer and
Power-up Timer Timing ............................ 191
Figure 18-5: Timer0 and Timer1 External
Clock Timings ........................................... 192
Figure 18-6: Capture/Compare/PWM Timings
(CCP1)...................................................... 193
Figure 18-7: Parallel Slave Port Timing
(PIC16C64)............................................... 194
Figure 18-8: SPI Mode Timing ...................................... 195
Figure 18-9: I2C Bus Start/Stop Bits Timing.................. 196
Figure 18-10: I2C Bus Data Timing ................................. 197
Figure 19-1: Load Conditions for Device
Timing Specifications................................ 204
Figure 19-2: External Clock Timing............................... 205
Figure 19-3: CLKOUT and I/O Timing........................... 206
Figure 19-4: Reset, Watchdog Timer,
Oscillator Start-up Timer and
Power-up Timer Timing ............................ 207
Figure 19-5: Brown-out Reset Timing ........................... 207
Figure 19-6: Timer0 and Timer1 External
Clock Timings ........................................... 208
Figure 19-7: Capture/Compare/PWM Timings
(CCP1)...................................................... 209
Figure 19-8: Parallel Slave Port Timing
(PIC16C64A/R64)..................................... 210
Figure 19-9: SPI Mode Timing ...................................... 211
Figure 19-10: I2C Bus Start/Stop Bits Timing.................. 212
Figure 19-11: I2C Bus Data Timing ................................. 213
Figure 20-1: Load Conditions for Device Timing
Specifications............................................ 220
Figure 20-2: External Clock Timing............................... 221
Figure 20-3: CLKOUT and I/O Timing........................... 222
Figure 20-4: Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer
Timing ....................................................... 223
Figure 20-5: Timer0 and Timer1 External Clock
Timings ..................................................... 224
Figure 20-6: Capture/Compare/PWM Timings
(CCP1 and CCP2) .................................... 225
DS30234D-page 328
Figure 20-7:
Figure 20-8:
Figure 20-9:
Figure 20-10:
Figure 20-11:
Figure 20-12:
Figure 21-1:
Figure 21-2:
Figure 21-3:
Figure 21-4:
Figure 21-5:
Figure 21-6:
Figure 21-7:
Figure 21-8:
Figure 21-9:
Figure 21-10:
Figure 21-11:
Figure 21-12:
Figure 21-13:
Figure 22-1:
Figure 22-2:
Figure 22-3:
Figure 22-4:
Figure 22-5:
Figure 22-6:
Figure 22-7:
Figure 22-8:
Figure 22-9:
Figure 22-10:
Figure 22-11:
Figure 22-12:
Figure 22-13:
Figure 23-1:
Figure 23-2:
Figure 23-3:
Figure 23-4:
Figure 23-5:
Figure 23-6:
Figure 23-7:
Figure 23-8:
Figure 23-9:
Figure 23-10:
Figure 23-11:
Parallel Slave Port Timing ........................ 226
SPI Mode Timing...................................... 227
I2C Bus Start/Stop Bits Timing ................. 228
I2C Bus Data Timing................................. 229
USART Synchronous Transmission
(Master/Slave) Timing .............................. 230
USART Synchronous Receive
(Master/Slave) Timing .............................. 230
Load Conditions for Device Timing
Specifications ........................................... 236
External Clock Timing .............................. 237
CLKOUT and I/O Timing .......................... 238
Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer
Timing....................................................... 239
Brown-out Reset Timing........................... 239
Timer0 and Timer1 External Clock
Timings..................................................... 240
Capture/Compare/PWM Timings
(CCP1 and CCP2)................................... 241
Parallel Slave Port Timing
(PIC16C65A) ............................................ 242
SPI Mode Timing...................................... 243
I2C Bus Start/Stop Bits Timing ................. 244
I2C Bus Data Timing................................. 245
USART Synchronous Transmission
(Master/Slave) Timing .............................. 246
USART Synchronous Receive
(Master/Slave) Timing .............................. 246
Load Conditions for Device Timing
Specifications ........................................... 252
External Clock Timing .............................. 253
CLKOUT and I/O Timing .......................... 254
Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer
Timing....................................................... 255
Brown-out Reset Timing........................... 255
Timer0 and Timer1 External Clock
Timings..................................................... 256
Capture/Compare/PWM Timings
(CCP1 and CCP2).................................... 257
Parallel Slave Port Timing
(PIC16CR65)............................................ 258
SPI Mode Timing...................................... 259
I2C Bus Start/Stop Bits Timing ................. 260
I2C Bus Data Timing................................. 261
USART Synchronous Transmission
(Master/Slave) Timing .............................. 262
USART Synchronous Receive
(Master/Slave) Timing .............................. 262
Load Conditions for Device Timing
Specifications ........................................... 268
External Clock Timing .............................. 269
CLKOUT and I/O Timing .......................... 270
Reset, Watchdog Timer, Oscillator
Start-up Timer and Power-up Timer
Timing....................................................... 271
Brown-out Reset Timing........................... 271
Timer0 and Timer1 External Clock
Timings..................................................... 272
Capture/Compare/PWM Timings
(CCP1 and CCP2).................................... 273
Parallel Slave Port Timing (PIC16C67) .... 274
SPI Master Mode Timing (CKE = 0) ......... 275
SPI Master Mode Timing (CKE = 1) ......... 275
SPI Slave Mode Timing (CKE = 0) ........... 276
 1997 Microchip Technology Inc.
PIC16C6X
Figure 23-12:
Figure 23-13:
Figure 23-14:
Figure 23-15:
Figure 23-16:
Figure 24-1:
Figure 24-2:
Figure 24-3:
Figure 24-4:
Figure 24-5:
Figure 24-6:
Figure 24-7:
Figure 24-8:
Figure 24-9:
Figure 24-10:
Figure 24-11:
Figure 24-12:
Figure 24-13:
Figure 24-14:
Figure 24-15:
Figure 24-16:
Figure 24-17:
Figure 24-18:
Figure 24-19:
Figure 24-20:
Figure 24-21:
Figure 24-22:
Figure 24-23:
Figure 24-24:
Figure 24-25:
Figure 24-26:
Figure 24-27:
Figure 24-28:
SPI Slave Mode Timing (CKE = 1) ........... 276
I2C Bus Start/Stop Bits Timing.................. 278
I2C Bus Data Timing ................................. 279
USART Synchronous Transmission
(Master/Slave) Timing............................... 280
USART Synchronous Receive
(Master/Slave) Timing............................... 280
Typical IPD vs. VDD
(WDT Disabled, RC Mode) ....................... 281
Maximum IPD vs. VDD
(WDT Disabled, RC Mode) ....................... 281
Typical IPD vs. VDD @ 25°C
(WDT Enabled, RC Mode)........................ 282
Maximum IPD vs. VDD
(WDT Enabled, RC Mode)........................ 282
Typical RC Oscillator
Frequency vs. VDD.................................... 282
Typical RC Oscillator
Frequency vs. VDD.................................... 282
Typical RC Oscillator
Frequency vs. VDD.................................... 282
Typical IPD vs. VDD Brown-out
Detect Enabled (RC Mode)....................... 283
Maximum IPD vs. VDD Brown-out
Detect Enabled
(85°C to -40°C, RC Mode) ........................ 283
Typical IPD vs. Timer1 Enabled
(32 kHz, RC0/RC1 = 33 pF/33 pF,
RC Mode) ................................................ 283
Maximum IPD vs. Timer1 Enabled
(32 kHz, RC0/RC1 = 33 pF/33 pF,
85°C to -40°C, RC Mode) ......................... 283
Typical IDD vs. Frequency
(RC Mode @ 22 pF, 25°C) ....................... 284
Maximum IDD vs. Frequency
(RC Mode @ 22 pF, -40°C to 85°C) ......... 284
Typical IDD vs. Frequency
(RC Mode @ 100 pF, 25°C) ..................... 285
Maximum IDD vs. Frequency
(RC Mode @ 100 pF, -40°C to 85°C) ....... 285
Typical IDD vs. Frequency
(RC Mode @ 300 pF, 25°C) ..................... 286
Maximum IDD vs. Frequency
(RC Mode @ 300 pF, -40°C to 85°C) ....... 286
Typical IDD vs. Capacitance @ 500 kHz
(RC Mode) ................................................ 287
Transconductance(gm) of HS
Oscillator vs. VDD...................................... 287
Transconductance(gm) of LP
Oscillator vs. VDD...................................... 287
Transconductance(gm) of XT
Oscillator vs. VDD...................................... 287
Typical XTAL Startup Time vs. VDD
(LP Mode, 25°C) ....................................... 288
Typical XTAL Startup Time vs. VDD
(HS Mode, 25°C) ...................................... 288
Typical XTAL Startup Time vs. VDD
(XT Mode, 25°C)....................................... 288
Typical Idd vs. Frequency
(LP Mode, 25°C) ....................................... 289
Maximum IDD vs. Frequency
(LP Mode, 85°C to -40°C)......................... 289
Typical IDD vs. Frequency
(XT Mode, 25°C)....................................... 289
Maximum IDD vs. Frequency
(XT Mode, -40°C to 85°C) ........................ 289
 1997 Microchip Technology Inc.
Figure 24-29: Typical IDD vs. Frequency
(HS Mode, 25°C) .......................................290
Figure 24-30: Maximum IDD vs. Frequency
(HS Mode, -40°C to 85°C).........................290
DS30234D-page 329
PIC16C6X
LIST OF TABLES
Table 12-2:
Table 1-1:
Table 3-1:
Table 3-2:
Table 12-3:
Table 12-4:
Table 3-3:
Table 4-1:
Table 4-2:
Table 4-3:
Table 4-4:
Table 4-5:
Table 4-6:
Table 5-1:
Table 5-2:
Table 5-3:
Table 5-4:
Table 5-5:
Table 5-6:
Table 5-7:
Table 5-8:
Table 5-9:
Table 5-10:
Table 5-11:
Table 5-12:
Table 5-13:
Table 7-1:
Table 8-1:
Table 8-2:
Table 9-1:
Table 10-1:
Table 10-2:
Table 10-3:
Table 10-4:
Table 10-5:
Table 11-1:
Table 11-2:
Table 11-3:
Table 11-4:
Table 11-5:
Table 12-1:
PIC16C6X Family of Devices ....................... 6
PIC16C61 Pinout Description ..................... 14
PIC16C62/62A/R62/63/R63/66
Pinout Description....................................... 15
PIC16C64/64A/R64/65/65A/R65/67
Pinout Description....................................... 16
Special Function Registers for the
PIC16C61 ................................................... 23
Special Function Registers for the
PIC16C62/62A/R62 .................................... 24
Special Function Registers for the
PIC16C63/R63............................................ 26
Special Function Registers for the
PIC16C64/64A/R64 .................................... 28
Special Function Registers for the
PIC16C65/65A/R65 .................................... 30
Special Function Registers for the
PIC16C66/67 .............................................. 32
PORTA Functions....................................... 52
Registers/Bits Associated with
PORTA ....................................................... 52
PORTB Functions....................................... 54
Summary of Registers Associated with
PORTB ....................................................... 54
PORTC Functions for PIC16C62/64........... 55
PORTC Functions for
PIC16C62A/R62/64A/R64 .......................... 56
PORTC Functions for
PIC16C63/R63/65/65A/R65/66/67.............. 56
Summary of Registers Associated with
PORTC ....................................................... 56
PORTD Functions....................................... 57
Summary of Registers Associated with
PORTD ....................................................... 57
PORTE Functions....................................... 59
Summary of Registers Associated with
PORTE ....................................................... 59
Registers Associated with
Parallel Slave Port ...................................... 62
Registers Associated with Timer0 .............. 69
Capacitor Selection for the
Timer1 Oscillator......................................... 73
Registers Associated with
Timer1 as a Timer/Counter ......................... 74
Registers Associated with
Timer2 as a Timer/Counter ......................... 76
CCP Mode - Timer Resource ..................... 77
Interaction of Two CCP Modules ................ 77
Example PWM Frequencies
and Resolutions at 20 MHz......................... 81
Registers Associated with Timer1,
Capture and Compare ................................ 81
Registers Associated with PWM
and Timer2.................................................. 82
Registers Associated with SPI
Operation .................................................... 88
Registers Associated with SPI
Operation (PIC16C66/67) ........................... 94
I2C Bus Terminology................................... 95
Data Transfer Received Byte
Actions ...................................................... 100
Registers Associated with I2C
Operation .................................................. 103
Baud Rate Formula................................... 107
DS30234D-page 330
Table 12-5:
Table 12-6:
Table 12-7:
Table 12-8:
Table 12-9:
Table 12-10:
Table 12-11:
Table 13-1:
Table 13-2:
Table 13-3:
Table 13-4:
Table 13-5:
Table 13-6:
Table 13-7:
Table 13-8:
Table 13-9:
Table 13-10:
Table 13-11:
Table 13-12:
Table 14-1:
Table 14-2:
Table 15-1:
Table 16-1:
Table 16-2:
Table 16-3:
Table 16-4:
Table 16-5:
Table 17-1:
Table 17-2:
Registers Associated with Baud
Rate Generator......................................... 107
Baud Rates for Synchronous Mode ......... 108
Baud Rates for Asynchronous Mode
(BRGH = 0)............................................... 108
Baud Rates for Asynchronous Mode
(BRGH = 1)............................................... 109
Registers Associated with
Asynchronous Transmission .................... 113
Registers Associated with
Asynchronous Reception ......................... 115
Registers Associated with
Synchronous Master Transmission .......... 117
Registers Associated with
Synchronous Master Reception ............... 118
Registers Associated with
Synchronous Slave Transmission ............ 121
Registers Associated with
Synchronous Slave Reception ................. 121
Ceramic Resonators PIC16C61 ............... 126
Ceramic Resonators
PIC16C62/62A/R62/63/R63/
64/64A/R64/65/65A/R65/66/67 ................ 126
Capacitor Selection for Crystal
Oscillator for PIC16C61............................ 126
Capacitor Selection for Crystal
Oscillator for PIC16C62/62A/R62/63/R63/
64/64A/R64/65/65A/R65/66/67 ................ 126
Time-out in Various Situations,
PIC16C61/62/64/65.................................. 130
Time-out in Various Situations,
PIC16C62A/R62/63/R63/
64A/R64/65A/R65/66/67 .......................... 130
Status Bits and Their Significance,
PIC16C61................................................. 130
Status bits and Their Significance,
PIC16C62/64/65....................................... 130
Status Bits and Their Significance for
PIC16C62A/R62/63/R63/
64A/R64/65A/R65/66/67 .......................... 131
Reset Condition for Special
Registers on PIC16C61/62/64/65............. 131
Reset Condition for Special
Registers on
PIC16C62A/R62/63/R63/
64A/R64/65A/R65/66/67 .......................... 131
Initialization Conditions for
all Registers.............................................. 132
Opcode Field Descriptions ....................... 143
PIC16CXX Instruction Set ........................ 144
Development Tools from Microchip.......... 162
Cross Reference of Device
Specs for Oscillator Configurations
and Frequencies of Operation
(Commercial Devices) .............................. 163
External Clock Timing
Requirements ........................................... 169
CLKOUT and I/O Timing
Requirements ........................................... 170
Reset, Watchdog Timer,
Oscillator Start-up Timer and
Power-up Timer Requirements ................ 171
Timer0 External Clock Requirements....... 172
RC Oscillator Frequencies ....................... 173
Input Capacitance* ................................... 181
 1997 Microchip Technology Inc.
PIC16C6X
Table 18-1:
Table 18-2:
Table 18-3:
Table 18-4:
Table 18-5:
Table 18-6:
Table 18-7:
Table 18-8:
Table 18-9:
Table 18-10:
Table 19-1:
Table 19-2:
Table 19-3:
Table 19-4:
Table 19-5:
Table 19-6:
Table 19-7:
Table 19-8:
Table 19-9:
Table 19-10:
Table 20-1:
Table 20-2:
Table 20-3:
Table 20-4:
Table 20-5:
Table 20-6:
Table 20-7:
Table 20-8:
Table 20-9:
Table 20-10:
Table 20-11:
Cross Reference of Device Specs
for Oscillator Configurations and
Frequencies of Operation
(Commercial Devices) .............................. 183
External Clock Timing
Requirements ........................................... 189
CLKOUT and I/O Timing
Requirements ........................................... 190
Reset, Watchdog Timer,
Oscillator Start-up Timer and
Power-up Timer Requirements................. 191
Timer0 and Timer1 External
Clock Requirements ................................. 192
Capture/Compare/PWM
Requirements (CCP1) .............................. 193
Parallel Slave Port Requirements
(PIC16C64)............................................... 194
SPI Mode Requirements........................... 195
I2C Bus Start/Stop Bits
Requirements ........................................... 196
I2C Bus Data Requirements ..................... 197
Cross Reference of Device Specs
for Oscillator Configurations and
Frequencies of Operation
(Commercial Devices) .............................. 199
External Clock Timing
Requirements ........................................... 205
CLKOUT and I/O Timing
Requirements ........................................... 206
Reset, Watchdog Timer,
Oscillator Start-up Timer,
Power-up Timer, and Brown-out
Reset Requirements ................................. 207
Timer0 and Timer1 External
Clock Requirements ................................. 208
Capture/Compare/PWM
Requirements (CCP1) .............................. 209
Parallel Slave Port Requirements
(PIC16C64A/R64)..................................... 210
SPI Mode Requirements........................... 211
I2C Bus Start/Stop Bits
Requirements ........................................... 212
I2C Bus Data Requirements ..................... 213
Cross Reference of Device Specs
for Oscillator Configurations and
Frequencies of Operation
(Commercial Devices) .............................. 215
External Clock Timing
Requirements ........................................... 221
CLKOUT and I/O Timing
Requirements ........................................... 222
Reset, Watchdog Timer,
Oscillator Start-up Timer and
Power-up Timer Requirements................. 223
Timer0 and Timer1 External
Clock Requirements ................................. 224
Capture/Compare/PWM
Requirements (CCP1 and CCP2)............. 225
Parallel Slave Port Requirements............. 226
SPI Mode Requirements........................... 227
I2C Bus Start/Stop Bits
Requirements ........................................... 228
i2C Bus Data Requirements...................... 229
USART Synchronous Transmission
Requirements ........................................... 230
 1997 Microchip Technology Inc.
Table 20-12:
Table 21-1:
Table 21-2:
Table 21-3:
Table 21-4:
Table 21-5:
Table 21-6:
Table 21-7:
Table 21-8:
Table 21-9:
Table 21-10:
Table 21-11:
Table 21-12:
Table 22-1:
Table 22-2:
Table 22-3:
Table 22-4:
Table 22-5:
Table 22-6:
Table 22-7:
Table 22-8:
Table 22-9:
Table 22-10:
Table 22-11:
Table 22-12:
Table 23-1:
Table 23-2:
Table 23-3:
Table 23-4:
USART Synchronous Receive
Requirements ............................................230
Cross Reference of Device
Specs for Oscillator Configurations
and Frequencies of Operation
(Commercial Devices) ...............................231
External Clock Timing
Requirements ............................................237
CLKOUT and I/O Timing
Requirements ............................................238
Reset, Watchdog Timer, Oscillator
Start-up Timer, Power-up Timer, and
Brown-out Reset Requirements ................239
Timer0 and Timer1 External
Clock Requirements ..................................240
Capture/Compare/PWM
Requirements (CCP1 and CCP2) .............241
Parallel Slave Port Requirements
(PIC16C65A) .............................................242
SPI Mode Requirements ...........................243
I2C Bus Start/Stop Bits
Requirements ............................................244
I2C Bus Data Requirements ......................245
USART Synchronous
Transmission Requirements......................246
USART Synchronous Receive
Requirements ...........................................246
Cross Reference of Device Specs
for Oscillator Configurations and
Frequencies of Operation
(Commercial Devices) ...............................247
External Clock Timing
Requirements ............................................253
CLKOUT and I/O Timing
Requirements ............................................254
Reset, Watchdog Timer,
Oscillator Start-up Timer,
Power-up Timer, and Brown-out
Reset Requirements..................................255
Timer0 and Timer1 External
Clock Requirements ..................................256
Capture/Compare/PWM
Requirements (CCP1 and CCP2) .............257
Parallel Slave Port Requirements
(PIC16CR65).............................................258
SPI Mode Requirements ...........................259
I2C Bus Start/Stop Bits
Requirements ............................................260
I2C Bus Data Requirements ......................261
USART Synchronous Transmission
Requirements ............................................262
USART Synchronous Receive
Requirements ...........................................262
Cross Reference of Device Specs
for Oscillator Configurations and
Frequencies of Operation
(Commercial Devices) ...............................263
External Clock Timing
Requirements ............................................269
CLKOUT and I/O Timing
Requirements ............................................270
Reset, Watchdog Timer,
Oscillator Start-up Timer,
Power-up Timer, and Brown-out
Reset Requirements..................................271
DS30234D-page 331
PIC16C6X
Table 23-5:
Table 23-6:
Table 23-7:
Table 23-8:
Table 23-9:
Table 23-10:
Table 23-11:
Table 23-12:
Table 24-1:
Table 24-2:
Table E-1:
Timer0 and Timer1 External
Clock Requirements ................................. 272
Capture/Compare/PWM
Requirements (CCP1 and CCP2)............. 273
Parallel Slave Port Requirements
(PIC16C67)............................................... 274
SPI Mode Requirements........................... 277
I2C Bus Start/Stop Bits
Requirements ........................................... 278
I2C Bus Data Requirements ..................... 279
USART Synchronous Transmission
Requirements ........................................... 280
USART Synchronous Receive
Requirements ........................................... 280
RC Oscillator Frequencies........................ 287
Capacitor Selection for Crystal
Oscillators ................................................. 288
Pin Compatible Devices............................ 315
DS30234D-page 332
 1997 Microchip Technology Inc.
PIC16C6X
ON-LINE SUPPORT
Microchip provides two methods of on-line support.
These are the Microchip BBS and the Microchip World
Wide Web (WWW) site.
Use Microchip's Bulletin Board Service (BBS) to get
current information and help about Microchip products.
Microchip provides the BBS communication channel
for you to use in extending your technical staff with
microcontroller and memory experts.
To provide you with the most responsive service possible,
the Microchip systems team monitors the BBS, posts
the latest component data and software tool updates,
provides technical help and embedded systems
insights, and discusses how Microchip products provide project solutions.
The web site, like the BBS, is used by Microchip as a
means to make files and information easily available to
customers. To view the site, the user must have access
to the Internet and a web browser, such as Netscape or
Microsoft Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet Web Site
The Microchip web site is available by using your
favorite Internet browser to attach to:
www.microchip.com
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.futureone.com/pub/microchip
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
Connecting to the Microchip BBS
Connect worldwide to the Microchip BBS using either
the Internet or the CompuServe communications network.
Internet:
You can telnet or ftp to the Microchip BBS at the
address: mchipbbs.microchip.com
CompuServe Communications Network:
When using the BBS via the Compuserve Network,
in most cases, a local call is your only expense. The
Microchip BBS connection does not use CompuServe
membership services, therefore you do not need
CompuServe membership to join Microchip's BBS.
There is no charge for connecting to the Microchip BBS.
 1997 Microchip Technology Inc.
The procedure to connect will vary slightly from country
to country. Please check with your local CompuServe
agent for details if you have a problem. CompuServe
service allow multiple users various baud rates
depending on the local point of access.
The following connect procedure applies in most locations.
1. Set your modem to 8-bit, No parity, and One stop
(8N1). This is not the normal CompuServe setting
which is 7E1.
2. Dial your local CompuServe access number.
3. Depress the <Enter> key and a garbage string will
appear because CompuServe is expecting a 7E1
setting.
4. Type +, depress the <Enter> key and “Host Name:”
will appear.
5. Type MCHIPBBS, depress the <Enter> key and you
will be connected to the Microchip BBS.
In the United States, to find the CompuServe phone
number closest to you, set your modem to 7E1 and dial
(800) 848-4480 for 300-2400 baud or (800) 331-7166
for 9600-14400 baud connection. After the system
responds with “Host Name:”, type NETWORK, depress
the <Enter> key and follow CompuServe's directions.
For voice information (or calling from overseas), you
may call (614) 723-1550 for your local CompuServe
number.
Microchip regularly uses the Microchip BBS to distribute
technical information, application notes, source code,
errata sheets, bug reports, and interim patches for
Microchip systems software products. For each SIG, a
moderator monitors, scans, and approves or disapproves files submitted to the SIG. No executable files
are accepted from the user community in general to
limit the spread of computer viruses.
Systems Information and Upgrade Hot Line
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive any currently available upgrade kits.The
Hot Line Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-602-786-7302 for the rest of the world.
970301
Trademarks: The Microchip name, logo, PIC, PICSTART,
PICMASTER and PRO MATE are registered trademarks
of Microchip Technology Incorporated in the U.S.A. and
other countries. FlexROM, MPLAB and fuzzyLAB, are
trademarks and SQTP is a service mark of Microchip in
the U.S.A.
fuzzyTECH is a registered trademark of Inform Software
Corporation. IBM, IBM PC-AT are registered trademarks
of International Business Machines Corp. Pentium is a
trademark of Intel Corporation. Windows is a trademark
and MS-DOS, Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated.
All other trademarks mentioned herein are the property of
their respective companies.
DS30234D-page 333
PIC16C6X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.
Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
To:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Device: PIC16C6X
Y
N
Literature Number: DS30234D
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this data sheet easy to follow? If not, why?
4. What additions to the data sheet do you think would enhance the structure and subject?
5. What deletions from the data sheet could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
8. How would you improve our software, systems, and silicon products?
DS30234D-page 334
 1997 Microchip Technology Inc.
PIC16C6X
PIC16C6X Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
PART NO.
-XX
X /XX XXX
Pattern:
3-Digit Pattern Code for QTP (blank otherwise)
Package:
L
SP
P
SO
PQ
TQ
JW*
SS
=
=
=
=
=
=
=
=
PLCC
Skinny DIP
PDIP
SOIC (Gull Wing, 300 mil body)
MQFP (Metric PQFP)
TQFP
Windowed CERDIP
Shrink SOIC (Gull Wing, 300 mil body)
Temperature
Range:
I
E
=
=
=
0˚C to +70˚C (T for tape/reel)
– 40˚C to +85˚C (S for tape/reel)
– 40˚C to +125˚C
Frequency
Range:
04
04
10
20
=
=
=
=
200 kHz (PIC16C6X-04)
4 MHz
10 MHz
20 MHz
Device:
PIC16C6X :VDD range 4.0V to 6.0V
PIC16C6XT :VDD range 4.0V to 6.0V (Tape and Reel)
PIC16LC6X :VDD range 2.5V to 6.0V
PIC16LC6XT :VDD range 2.5V to 6.0V (Tape and Reel)
PIC16CR6X :VDD range 4.0V to 6.0V
PIC16CR6XT :VDD range 4.0V to 6.0V (Tape and Reel)
PIC16LCR6X :VDD range 2.5V to 6.0V
PIC16LCR6XT:VDD range 2.5V to 6.0V
Examples:
a)PIC16C62A - 04/P 301 = Commercial temp., PDIP package, 4 MHz, normal VDD limits, QTP pattern #301
b)PIC16LC65A - 04I/PQ = Industrial temp., MQFP package, 4 MHz, extended VDD limits
c)PIC16C67 - 10E/P
= Extended temp., PDIP package, 10 MHz, normal VDD limits
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type (including LC devices).
Sales and Support
Products supported by a preliminary Data Sheet may possibly have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. The Microchip Website at www.microchip.com
2. Your local Microchip sales office (see following page)
3. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
4. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
For latest version information and upgrade kits for Microchip Development Tools, please call 1-800-755-2345 or 1-602-786-7302.
 1997 Microchip Technology Inc.
DS30234D-page 335
WORLDWIDE SALES AND SERVICE
AMERICAS
AMERICAS (continued)
Corporate Office
Toronto
Singapore
Microchip Technology Inc.
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-786-7200 Fax: 480-786-7277
Technical Support: 480-786-7627
Web Address: http://www.microchip.com
Microchip Technology Inc.
5925 Airport Road, Suite 200
Mississauga, Ontario L4V 1W1, Canada
Tel: 905-405-6279 Fax: 905-405-6253
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Tel: 65-334-8870 Fax: 65-334-8850
Atlanta
Microchip Asia Pacific
Unit 2101, Tower 2
Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2-401-1200 Fax: 852-2-401-3431
Microchip Technology Inc.
500 Sugar Mill Road, Suite 200B
Atlanta, GA 30350
Tel: 770-640-0034 Fax: 770-640-0307
Boston
Microchip Technology Inc.
5 Mount Royal Avenue
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Tel: 508-480-9990 Fax: 508-480-8575
Chicago
Microchip Technology Inc.
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Tel: 630-285-0071 Fax: 630-285-0075
Dallas
Microchip Technology Inc.
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Tel: 972-818-7423 Fax: 972-818-2924
Dayton
Microchip Technology Inc.
Two Prestige Place, Suite 150
Miamisburg, OH 45342
Tel: 937-291-1654 Fax: 937-291-9175
Detroit
Microchip Technology Inc.
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Los Angeles
Microchip Technology Inc.
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Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
New York
Microchip Technology Inc.
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Hauppauge, NY 11788
Tel: 631-273-5305 Fax: 631-273-5335
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
ASIA/PACIFIC
Hong Kong
ASIA/PACIFIC (continued)
Taiwan, R.O.C
Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Beijing
United Kingdom
Microchip Technology, Beijing
Unit 915, 6 Chaoyangmen Bei Dajie
Dong Erhuan Road, Dongcheng District
New China Hong Kong Manhattan Building
Beijing 100027 PRC
Tel: 86-10-85282100 Fax: 86-10-85282104
Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5858 Fax: 44-118 921-5835
India
Denmark
Microchip Technology Inc.
India Liaison Office
No. 6, Legacy, Convent Road
Bangalore 560 025, India
Tel: 91-80-229-0061 Fax: 91-80-229-0062
Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
Japan
France
Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Korea
Germany
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Shanghai
Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
Microchip Technology
RM 406 Shanghai Golden Bridge Bldg.
2077 Yan’an Road West, Hong Qiao District
Shanghai, PRC 200335
Tel: 86-21-6275-5700 Fax: 86 21-6275-5060
Italy
11/15/99
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99
Printed on recycled paper.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed
by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products
as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip
logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.
 1999 Microchip Technology Inc.
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