LMH0034 SMPTE 292M / 259M Adaptive Cable Equalizer LMH0034 FEATURES DESCRIPTION

LMH0034 SMPTE 292M / 259M Adaptive Cable Equalizer LMH0034 FEATURES DESCRIPTION
LMH0034
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SNLS213H – JANUARY 2006 – REVISED APRIL 2013
LMH0034 SMPTE 292M / 259M Adaptive Cable Equalizer
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FEATURES
DESCRIPTION
•
The LMH0034 SMPTE 292M / 259M adaptive cable
equalizer is a monolithic integrated circuit for
equalizing data transmitted over cable (or any media
with similar dispersive loss characteristics). The
equalizer operates over a wide range of data rates
from 125 Mbps to 1.485 Gbps and supports SMPTE
292M, SMPTE 344M and SMPTE 259M.
1
2
•
•
•
•
•
•
•
•
•
SMPTE 292M, SMPTE 344M and SMPTE 259M
Compliant
Supports DVB-ASI at 270 Mbps
Data Rates: 125 Mbps to 1.485 Gbps
Equalizes up to 200 Meters of Belden 1694A at
1.485 Gbps or up to 400 Meters of Belden
1694A at 270 Mbps
Manual Bypass, Cable Length Indicator, and
Output Mute with a Programmable Threshold
Single-Ended or Differential Input
50Ω Differential Outputs
Single 3.3V Supply Operation
208 mW Typical Power Consumption with 3.3V
Supply
Replaces the GS1524 and GS1524A
The LMH0034 implements DC restoration to correctly
handle pathological data conditions. DC restoration
can be bypassed for low data rate applications. The
equalizer is flexible in allowing either single-ended or
differential input drive.
Additional features include a combined carrier detect
and output mute pin which mutes the output when no
signal is present. A programmable mute reference is
used to mute the output at a selectable level of signal
degradation. A cable length indicator is provided to
determine the amount of cable being equalized.
APPLICATIONS
•
•
•
SMPTE 292M, SMPTE 344M, and SMPTE 259M
Serial Digital Interfaces
Serial Digital Data Equalization and Reception
Data Recovery Equalization
Typical Application
6.8 nH
LMH0034 Adaptive
Cable Equalizer
Coaxial Cable
1 PF
4.7 PF
SDI
SDO
SDI
SDO
75:
Outputs
75:
4.7 PF
1 PF
37.4:
CD/MUTE
CD/MUTE
CLI
MUTEREF AEC+
AECBYPASS
1 PF
CLI
MUTEREF
BYPASS
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LMH0034
SNLS213H – JANUARY 2006 – REVISED APRIL 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
−0.5V to 3.6V
Supply Voltage
−0.3V to VCC+0.3V
Input Voltage (all inputs)
−65°C to +150°C
Storage Temperature Range
Junction Temperature
+150°C
Lead Temperature (Soldering 4 Sec)
+260°C
Package Thermal Resistance
θJA 16-pin SOIC
+115°C/W
θJC 16-pin SOIC
+105°C/W
ESD Rating (HBM)
8 kV
ESD Rating (MM)
250V
(1)
Absolute Maximum Ratings are those parameter values beyond which the life and operation of the device cannot be ensured. The
stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values.
The table of Electrical Characteristics specifies acceptable device operating conditions.
Recommended Operating Conditions
Supply Voltage (VCC – VEE)
3.3V ±5%
Input Coupling Capacitance
1.0 µF
AEC Capacitor (Connected between AEC+ and AEC-)
1.0 µF
Operating Free Air Temperature (TA)
0°C to +85°C
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2).
Symbol Parameter
Conditions
VCMIN
Input Common Mode Voltage
VSDI
Input Voltage Swing
VCMOUT
Output Common Mode Voltage
VSDO
Output Voltage Swing
50Ω load, differential
CLI DC Voltage
0m cable (5)
Reference
Min
Typ
720
800
SDI, SDI
At LMH0034 input (3) (4)
CLI
Max cable (5)
MUTEREF
MUTEREF Range
CD/MUTE Output Voltage
Carrier not present
CD/MUTE
Min to mute outputs
ICC
(1)
(2)
(3)
(4)
(5)
(6)
2
Supply Current
.
mVP−P
V
V
750
mVP-P
2.5
V
1.9
V
1.3
V
0.7
V
2.6
V
0.4
3.0
V
V
Max to force outputs active
(6)
950
VCC –
VSDO/2
Carrier present
CD/MUTE Input Voltage
Units
1.9
SDO, SDO
MUTEREF DC Voltage (floating)
Max
63
2.0
V
77
mA
Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to VEE = 0 Volts.
Typical values are stated for VCC = +3.3V and TA = +25°C.
Specification is ensured by characterization.
The maximum input voltage swing assumes a nonstressing, DC-balance signal; specifically, the SMPTE-recommended color bar test
signal. Pathological or other stressing signals may not be used. This specification is for 0m cable only.
Input signal must be present for valid CLI. Refer to Figure 2 for typical results.
Supply current depends on the amount of cable being equalized. The current is highest for short cable and decreases as the cable
length is increased. Refer to Figure 3 and Figure 4.
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AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1).
Symbol
Parameter
BRMIN
Minimum Input Data Rate
BRMAX
Maximum Input Data Rate
Jitter for various cable lengths
(with equalizer pathological)
tr,tf
tOS
Conditions
Typ
Max
125
Units
Mbps
1485
Mbps
270 Mbps, Belden 1694A,
400 meters (2)
0.2
UI
270 Mbps, Belden 8281,
280 meters (2)
0.2
UI
1.485 Gbps, Belden 1694A,
140 meters (2)
0.25
UI
1.485 Gbps, Belden 8281,
100 meters (2)
0.25
UI
1.485 Gbps, Belden 1694A,
200 meters (2)
0.3
UI
Output Rise Time, Fall Time
20% – 80% (2)
100
220
ps
Mismatch in Rise/Fall Time
(2)
2
15
ps
Output Overshoot
(2)
1
5
%
Output Resistance
single-ended
RLIN
Input Return Loss
. (4)
RIN
Input Resistance
single-ended
(1)
(2)
(3)
(4)
Min
SDI, SDI
ROUT
CIN
Reference
Input Capacitance
SDO, SDO
(3)
SDI, SDI
single-ended
(3)
15
50
Ω
18-20
dB
1.3
kΩ
1
pF
Typical values are stated for VCC = +3.3V and TA = +25°C.
Specification is ensured by characterization.
Specification is ensured by design.
Input return loss is dependent on board design. The LMH0034 meets this specification on the SD034 evaluation board from 5MHz to
1.5GHz.
Connection Diagram
2
3
4
5
6
7
8
CLI
CD/MUTE
VCC
VCC
VEE
SDI
SDI
VEE
LMH0034
1
VEE
SDO
SDO
VEE
AEC+
MUTEREF
AEC-
BYPASS
16
15
14
13
12
11
10
9
Figure 1. 16-Pin SOIC
See D Package
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PIN DESCRIPTIONS
Pin #
Name
Description
1
CLI
Cable length indicator. Provides a voltage inversely proportional to the cable length being equalized.
2
VCC
Positive power supply (+3.3V).
3
VEE
Negative power supply (ground).
4
SDI
Serial data true input.
5
SDI
Serial data complement input.
6
VEE
Negative power supply (ground).
7
AEC+
AEC loop filter external capacitor (1µF) positive connection.
8
AEC-
AEC loop filter external capacitor (1µF) negative connection.
9
BYPASS
Bypasses equalization and DC restoration when high. No equalization occurs in this mode.
10
MUTEREF
Mute reference. Determines the maximum cable to be equalized before muting. May be unconnected
for maximum equalization.
11
VEE
Negative power supply (ground).
12
SDO
Serial data complement output.
13
SDO
Serial data true output.
14
VEE
Negative power supply (ground).
15
VCC
Positive power supply (+3.3V).
16
CD/MUTE
Bi-directional carrier detect and output mute. CD/MUTE is high when no signal is present. If
unconnected, MUTE is controlled automatically by carrier detect. To force MUTE on, tie to VCC. To
disable MUTE, tie to GND. CD/MUTE has no function in BYPASS mode.
Block Diagram
BYPASS
Output
Driver
SDI
SDI
DC
Restoration/
Level Control
Equalizer
Filter
Energy
Detect
SDO
SDO
Energy
Detect
6
CLI
Automatic
Equalization
Control
AEC+
4
Carrier
Detect/
Mute
CD/MUTE
MUTEREF
AEC-
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DEVICE OPERATION
BLOCK DESCRIPTION
The Equalizer Filter block is a multi-stage adaptive filter. If Bypass is high, the equalizer filter is disabled.
The DC Restoration / Level Control block receives the differential signals from the equalizer filter block. This
block incorporates a self-biasing DC restoration circuit to fully DC restore the signals. If Bypass is high, this
function is disabled.
The signals before and after the DC Restoration / Level Control block are used to generate the Automatic
Equalization Control (AEC) signal. This control signal sets the gain and bandwidth of the equalizer filter. The
loop response in the AEC block is controlled by an external 1µF capacitor placed across the AEC+ and AECpins. Cable Length Indicator (CLI) is derived from this block.
The Carrier Detect / Mute block generates the carrier detect signal and controls the mute function of the output.
This block utilizes the bi-directional CD/MUTE signal along with Mute Reference (MUTEREF).
The Output Driver produces SDO and SDO.
CABLE LENGTH INDICATOR (CLI)
The cable length indicator provides a voltage to indicate the length of cable being equalized. The CLI voltage
decreases as the cable length increases. Figure 2 shows the typical CLI voltage vs. Belden 1694A cable length.
Note: CLI is only valid when an input signal is present.
2.6
2.5
CLI (V)
2.4
2.3
2.2
2.1
2.0
1.9
1.8
0 50 100 150 200 250 300 350 400
BELDEN 1694A CABLE LENGTH (m)
Figure 2. CLI vs. Belden 1694A Cable Length
MUTE REFERENCE (MUTEREF)
The mute reference determines the amount of cable to equalize before automatically muting the outputs. This is
set by applying a voltage inversely proportional to the length of cable to equalize. As the applied MUTEREF
voltage is increased, the amount of cable that can be equalized before carrier detect is de-asserted and the
outputs are muted is decreased. MUTEREF may be left unconnected for maximum equalization before muting.
CARRIER DETECT / MUTE (CD/MUTE)
Carrier Detect / Mute is bi-directional, serving as both a carrier detect (output function) and mute (input function).
When used as an output, CD/MUTE determines if a valid signal is present at the LMH0034 input. If MUTEREF is
used, the carrier detect threshold will be altered accordingly. CD/MUTE provides a high voltage when no signal is
present at the LMH0034 input, and the outputs are automatically muted. CD/MUTE is low when a valid input
signal has been detected, and the outputs are automatically enabled.
As an input, CD/MUTE can be used to override the carrier detect and manually mute or enable the LMH0034
outputs. Applying a high input to CD/MUTE will mute the LMH0034 outputs. Applying a low input will force the
outputs to be active regardless of the length of cable or the state of MUTEREF.
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INPUT INTERFACING
The LMH0034 accepts either differential or single-ended input. The input must be AC coupled. Transformer
coupling is not supported.
The LMH0034 correctly handles equalizer pathological signals for standard definition and high definition serial
digital video, as described in SMPTE RP 178 and RP 198, respectively.
OUTPUT INTERFACING
The SDO and SDO outputs are internally loaded with 50Ω. They produce a 750 mVP-P differential output, or a
375 mVP-P single-ended output.
APPLICATION INFORMATION
PCB LAYOUT RECOMMENDATIONS
Please refer to the following Application Note: AN-1372 (SNLA071) “LMH0034 PCB Layout Techniques.”
REPLACING THE GENNUM GS1524
The LMH0034 is form-fit-function compatible with the Gennum GS1524 and GS1524A.
SUPPLY CURRENT VS. CABLE LENGTH
The supply current (ICC) depends on the amount of cable being equalized. The current is highest for short cable
and decreases as the cable length is increased. Figure 3 shows supply current vs. Belden 1694A cable length for
1.485 Gbps data and Figure 4 shows supply current vs. Belden 1694A cable length for 270 Mbps data.
SUPPLY CURRENT (mA)
75
70
65
60
55
0
50
100
150
200
BELDEN 1694A CABLE LENGTH (m)
Figure 3. Supply Current vs. Belden 1694A Cable Length, 1.485 Gbps
6
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SUPPLY CURRENT (mA)
75
70
65
60
55
0
100
200
300
400
BELDEN 1694A CABLE LENGTH (m)
Figure 4. Supply Current vs. Belden 1694A Cable Length, 270 Mbps
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REVISION HISTORY
Changes from Revision G (April 2013) to Revision H
•
8
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 7
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Aug-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMH0034MA
NRND
SOIC
D
16
48
TBD
Call TI
Call TI
0 to 85
L034
LMH0034MA/NOPB
ACTIVE
SOIC
D
16
48
Green (RoHS
& no Sb/Br)
CU SN | Call TI
Level-1-260C-UNLIM
0 to 85
L034
LMH0034MAX/NOPB
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
0 to 85
L034
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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16-Aug-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LMH0034MAX/NOPB
Package Package Pins
Type Drawing
SOIC
D
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
10.3
2.3
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMH0034MAX/NOPB
SOIC
D
16
2500
367.0
367.0
35.0
Pack Materials-Page 2
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