datasheet for VL391T5663A
Product Specifications
PART NO:
REV: 1.0
VL391T5663A-E6/D5/CC
General Information
2GB 256Mx72 DDR2 SDRAM UNBUFFERED ECC 240 PIN DIMM
Description
The VL391T5663A is a 256M X 72 DDR2 SDRAM high density DIMM. This memory module consists of
eighteen CMOS 128MX8 bit with 8 banks DDR2 Synchronous DRAMs in BGA packages and a 2K EEPROM
in an 8-pin TSSOP package. This module is a 240-pin dual in-line memory module and is intended for mounting
into a connector socket. Decoupling capacitors are mounted on the printed circuit board for each DDR2
SDRAM.
Features
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
240-pin, dual in-line memory module (DIMM)
Fast data transfer rates: PC2-5300, PC2-4200, PC2-3200
Supports ECC error detection and correction
VDD = VDDQ = 1.8V
VDDSPD = 1.7V to 3.6V
JEDEC standard 1.8V I/O (SSTL_18 compatible)
Differential data strobe (DQS, DQS# ) option
Four-bit prefetch architecture
DLL aligns DQ and DQS transition with CK
Programmable CAS# Latency (CL): 3, 4, 5
Write latency = Read latency - 1 tCK
Programmable burst; length (4, 8)
Adjustable data-output drive strength
On-die termination (ODT)
Auto & self refresh, (8K/64ms refresh)
Serial presence detect (SPD) with EEPROM
Gold edge contacts
Lead-free RoHS
PCB: Height 30.00mm (1.181”), double sided components
Order Information:
VL391T5663A-E6 S X
DRAM DIE (option)
DRAM MANUFACTURER
S - SAMSUNG
M - MICRON
MODULE SPEED
E6: PC2-5300 @ CL5
D5: PC2-4200 @ CL4
CC: PC2-3200 @ CL3
Pin Name
Function
A 0 ~ A 13
Address Inputs
BA0 ~ BA2
Bank Address Inputs
DQ0 ~ DQ63
Data Input/Output
C B0 ~ C B7
Check Bits
DQS0 ~ DQS8
Data Strobes
DQS0# ~ DQS8#
Data Strobes Complement
ODT0, ODT1
On-die Termination Control
CK0,CK0# ~ CK2,CK2#
Differential Clock Input
C K E 0, C K E 1
Clock Enables
C S 0#, C S 1#
Chip Selects
RAS#
Row Address Strobes
C AS#
Column Address Strobes
WE#
Write Enable
VD D
Voltage Supply 1.8V +/- 0.1V
VD D Q
I/O Power 1.8V +/- 0.1V
VSS
Ground
SA0 ~ SA2
SPD Address
SD A
SPD Data Input/Output
SC L
SPD Clock Input
DM0 ~ DM8
Data Masks
A10/AP
Address Input/Autoprecharge
VREF
SSTL_18 Reference Voltage
VD D SPD
SPD Voltage Supply 1.7V to
3.6V
NC
No Connect
VL : Lead-free/RoHS
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 1 OF 12
Product Specifications
PART NO:
REV: 1.0
VL391T5663A-E6/D5/CC
Pin Configuration
240-PIN DDR2 DIMM FRONT
240-PIN DDR2 DIMM BACK
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
31
DQ19
61
A4
91
VSS
121
VSS
151
VSS
18 1
VD D Q
211
DM5
2
VSS
32
VSS
62
VD D Q
92
DQS5#
122
DQ4
152
DQ28
182
A3
212
NC
3
DQ0
33
DQ24
63
A2
93
DQS5
123
DQ5
153
DQ29
183
A1
213
VSS
4
DQ1
34
DQ25
64
VD D
94
VSS
124
VSS
154
VSS
184
VD D
214
DQ46
5
VSS
35
VSSD
65
VSS
95
DQ42
125
DM0
155
DM3
185
C K0
215
DQ47
6
DQS0#
36
DQS3#
66
VSS
96
DQ43
126
NC
156
NC
186
C K 0#
216
VSS
7
DQS0
37
DQS3
67
VD D
97
VSS
127
VSS
157
VSS
187
VD D
217
DQ52
8
VSS
38
VSS
68
NC
98
DQ48
128
DQ6
158
DQ30
188
A0
218
DQ53
9
DQ2
39
DQ26
69
VD D
99
DQ49
129
DQ7
159
DQ31
189
VD D
219
VSS
10
DQ3
40
DQ27
70
A10/AP
100
VSS
130
VSS
160
VSS
190
BA1
220
C K2
11
VSS
41
VSS
71
BA0
101
SA2
131
DQ12
161
C B4
191
VD D Q
221
C K 2#
12
DQ8
42
C B0
72
VD D Q
102
NC
132
DQ13
162
C B5
192
RAS#
222
VSS
13
DQ9
43
C B1
73
WE#
103
VSS
133
VSS
163
VSS
193
C S 0#
223
DM6
14
VSS
44
VSS
74
C AS#
104
DQS6#
134
DM1
164
DM8
194
VD D Q
224
NC
15
DQS1#
45
DQS8#
75
VD D Q
105
DQS6
135
NC
165
NC
195
ODT0
225
VSS
16
DQS1
46
DQS8
76
C S 1#
106
VSS
136
VSS
166
VSS
196
A 13
226
DQ54
17
VSS
47
VSS
77
ODT1
107
DQ50
137
C K1
167
C B6
197
VD D
227
DQ55
18
NC
48
C B2
78
VD D Q
108
DQ51
138
C K 1#
168
C B7
198
VSS
228
VSS
19
NC
49
C B3
79
VSS
109
VSS
139
VSS
169
VSS
199
DQ36
229
DQ60
20
VSS
50
VSS
80
DQ32
110
DQ56
140
DQ14
170
VD D Q
200
DQ37
230
DQ61
21
DQ10
51
VD D Q
81
DQ33
111
DQ57
141
DQ15
171
C KE1
201
VSS
231
VSS
22
DQ11
52
C KE0
82
VSS
112
VSS
142
VSS
172
VD D
202
DM4
232
DM7
23
VSS
53
VD D
83
DSQ4#
113
DQS7#
143
DQ20
17 3
NC
203
NC
233
NC
24
DQ16
54
BA2
84
DSQ4
114
DQS7
144
DQ21
174
NC
204
VSS
234
VSS
25
DQ17
55
NC
85
VSS
115
VSS
145
VSS
175
VD D Q
205
DQ38
235
DQ62
26
VSS
56
VD D Q
86
DQ34
116
DQ58
146
DM2
176
A 12
206
DQ39
236
DQ63
27
DQS2#
57
A11
87
DQ35
117
DQ59
147
NC
177
A9
207
VSS
237
VSS
28
DQS2
58
A7
88
VSS
118
VSS
148
VSS
178
VD D
208
DQ44
238
VD D SPD
29
VSS
59
VD D
89
DQ40
119
SD A
149
DQ22
179
A8
209
DQ45
239
SA0
30
DQ18
60
A5
90
DQ41
120
SC L
150
DQ23
180
A6
210
VSS
240
SA1
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 2 OF 12
Product Specifications
PART NO:
REV: 1.0
VL391T5663A-E6/D5/CC
Functional Block Diagram
CS1#
CS0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM/
RDQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
D0
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D9
DQS1
DQS1#
DM1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
D13
DQS5
DQS5#
DM5
DM/
RDQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
D1
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D10
DQS2
DQS2#
DM2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
D14
DQS6
DQS6#
DM6
DM/
RDQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
D2
DM/
RDQS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
CS# DQS DQS#
DM/
RDQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D11
DQS3
DQS3#
DM3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
D15
DQS7
DQS7#
DM7
DM/
RDQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
D3
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
DM/
RDQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
CS# DQS DQS#
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
D16
DQS8
DQS8#
DM8
DM/
RDQS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS0#
CS1#
BA0-BA2
A0-A13
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
3 Ohms
>
>
>
>
>
>
>
>
>
>
>
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS# DQS DQS#
D8
DM/
RDQS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS0#: DDR 2 SDRAMs D0-D8
CS1#: DDR2 SDRAMs D9-D17
BA0-BA2: DDR2 SDRAMs D0-D17
A0-A13: DDR2 SDRAMs D0-D17
RAS#: DDR2 SDRAMs D0-D17
CAS#: DDR2 SDRAMs D0-D17
WE#: DDR2 SDRAMs D0-D17
CKE0: DDR2 SDRAMs D0-D8
CKE1: DDR2 SDRAMs D9-D17
ODT0: DDR2 SDRAMs D0-D8
ODT1: DDR2 SDRAMs D9-D17
* Clock Wiring
CS# DQS DQS#
D17
Clock
Input
DDR2 SDRAMs
*CK0/CK0#
*CK1/CK1#
*CK2/CK2#
6 DDR2 SDRAMs
6 DDR2 SDRAMs
6 DDR2 SDRAMs
*Wire per Clock Loading
Table/Wiring Diagrams
VDDSPD
Serial PD
VDD/VDDQ
D0 - D17
VREF
D0 - D17
VSS
D0 - D17
SCL
WP
Serial PD
A0
A1
SDA
A2
SA0 SA1 SA2
Notes : Unless otherwise noted, resistor values are 22 Ohms +/- 5%
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 3 OF 12
Product Specifications
PART NO:
REV: 1.0
VL391T5663A-E6/D5/CC
Absolute Maximum Ratings
Symbol
Parameter
MIN
MAX
Unit
VDD
Voltage on VDD pin relative to VSS
-1.0
2.3
V
VDDQ
Voltage on VDDQ pin relative to VSS
-0.5
2.3
V
VDDL
Voltage on VDDL pin relative to VSS
-0.5
2.3
V
Voltage on any pin relative to VSS
-0.5
2.3
V
Storage temperature
-55
100
0
C
0
85
0
C
Command/Address,
RAS#, CAS#, WE#, BA
-90
90
uA
CS#, CKE, ODT
-45
45
uA
C K, C K#
-30
30
uA
DM
-10
10
uA
DQ, DQS, DQS#
-10
10
uA
-36
36
uA
VIN, VOUT
TSTG
TCASE
Device operating temperature
Input leakage current; Any input
0V<VIN<VDD; VREF input
0V<VIN<0.95V; Other pins not under
test = 0V
IL
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT
are disabled
IOZ
IVREF
VREF leakage current; VREF = Valid VREF level
DC Operating Conditions
All voltages referenced to VSS
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Supply voltage
VDD
1.7
1.8
1.9
V
1
I/O Supply voltage
VDDQ
1.7
1.8
1.9
V
4
VDDL Supply voltage
VDDL
1.7
1.8
1.9
V
4
I/O Reference voltage
VREF
0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V
2
I/O Termination voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
3
Notes: 1. VDD, VDDQ must track each other. VDDQ must be less than or equal to VDD.
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-topeak noise on VREF may not exceed +/-1percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2
percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF and must track variations in the DC level of VREF.
4. VDDQ tracks with VDD; VDDL tracks with VDD.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 4 OF 12
Product Specifications
PART NO:
REV: 1.0
VL391T5663A-E6/D5/CC
Operating Temperature Condition
Parameter
Symbol
Rating
TOPER
0 to 85
Operating temperature
Units
0
Notes
C
1,2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JEDEC JESD51.2
2. At 0 - 850C, operation temperature range, all DRAM specifications will be supported.
Input DC Logic Level
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
Input High (Logic 1) Voltage
VIH(DC)
VREF + 0.125
VDDQ + 0.300
V
Input Low (Logic 0) Voltage
VIL(DC)
-0.300
VREF - 0.125
V
Input AC Logic Level
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
AC Input High (Logic 1) Voltage DDR2-533, DDR2-400
VIH(AC)
VREF + 0.250
-
V
AC Input High (Logic 1) Voltage DDR2-667
VIH(AC)
VREF + 0.200
-
V
AC Input Low (Logic 0) Voltage DDR2-533, DDR2-400
VIL(AC)
-
VREF - 0.250
V
AC Input Low (Logic 0) Voltage DDR2-667
VIL(AC)
-
VREF - 0.200
V
Input/Output Capacitance
TA=250C, f=100MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A13, BA0 ~ BA2, RAS#, CAS#, WE#)
CIN1
22
40
pF
Input capacitance (CKE0, CKE1), (ODT0, ODT1)
CIN2
22
40
pF
Input capacitance (CS0#, CS1#)
CIN3
13
22
pF
Input capacitance (CK0, CK0# ~ CK2, CK2#)
CIN4
10
16
pF
Input capacitance (DM0 ~ DM8), (CB0 ~ CB7)
CIN5
9
12
pF
COUT1
9
12
pF
Input capacitance (DQ0 ~ DQ63), (DQS0 ~ DQS8)
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 5 OF 12
Product Specifications
PART NO:
REV: 1.0
VL391T5663A-E6/D5/CC
IDD Specification
Condition
Symbol
-E6
-D5
-CC
Unit
Operating one bank active-precharge;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD0*
900
855
810
mA
Operating one bank active-read-precharge;
IOUT = 0mA; BL = 4; CL = CL(IDD);tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH,
CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus
inputs are SWITCHING; Data pattern is sames as IDD4W.
IDD1*
990
945
900
mA
Precharge pow er-dow n current;
All banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
IDD2P**
270
270
270
mA
Precharge quiet standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
IDD2Q**
720
720
630
mA
Precharge standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; CS# is HIGH; Other control and address bus inputs
are STABLE; Data bus inputs are SWITCHING.
IDD2N**
810
810
720
mA
Ac t iv e p o w er -d o w n c u r r en t ;
All banks open; tCK= tCK(IDD); CKE is LOW; Other control
and address bus inputs are STABLE; Data bus inputs
are FLOATING.
720
630
630
mA
IDD3P**
324
324
324
mA
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
Active standby current;
All banks open;tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD));CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
IDD3N**
1080
1080
990
mA
Operating burst w rite current;
All banks open; Continuous burst writes; BL = 4; CL = CL(IDD); AL = 0; tCK= tCK(IDD);
tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands; Address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD4W*
1305
1215
1080
mA
Operating burst read current;
All banks open; Continuous burst reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = 0;
tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.
IDD4R*
1395
1305
1170
mA
Burst auto refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH; CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs
are SWITCHING.
IDD5**
2700
2700
2610
mA
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and
address bus inputs are FLOATING; Data bus inputs are
FLOATING.
IDD6**
270
270
270
mA
IDD7*
2295
2295
2160
mA
Normal
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 4; CL = CL(IDD); AL = tRCD(IDD) - 1*tCK(IDD);
tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ; CKE is HIGH; CS# is HIGH between
valid commands; Address bus inputs are STABLE during DESELECTs; Data bus inputs are
SWITCHING.
Note: IDD is based on Samsung D-die component. Other DRAM Manufacturer specification may be different.
* : Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P ( CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 6 OF 12
Product Specifications
PART NO:
REV: 1.0
VL391T5663A-E6/D5/CC
AC Timing Parameters & Specifications
-E6
Parameter
Clock
Data
-CC
Min
Max
Min
Max
Min
Max
Unit
CL=5
tCK (5)
3000
8000
-
-
-
-
ps
CL=4
tCK (4)
3750
8000
3,750
8,000
5,000
8,000
ps
CL=3
tCK (3)
5000
8000
5,000
8,000
5,000
8,000
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Half clock period
tHP
MIN
(tCH,tCL)
Clock jitter
tJIT
-125
125
-125
125
-125
125
ps
DQ output access time from CK/CK#
tAC
-450
+450
-500
+500
-600
+600
ps
Data-out high impedance window from CK/CK#
tHZ
tAC (MAX)
ps
Data-out low-impedance window from CK/CK#
tLZ
tAC (MIN)
tAC (MAX)
ps
DQ and DM input setup time relative to DQS
tDS
100
100
150
DQ and DM input hold time relative to DQS
tDH
175
225
275
DQ and DM input pulse width (for each input)
tDIPW
0.35
0.35
0.35
Data hold skew factor
tQHS
DQ–DQS hold, DQS to first DQ to go nonvalid,
p e r a cce ss
tQH
tHP - tQHS
tHP - tQHS
tHP - tQHS
ps
Data valid output window (DVW)
tDVW
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
ns
DQS input high pulse width
tDQSH
0.35
0.35
0.35
tCK
DQS input low pulse width
tDQSL
0.35
0.35
0.35
tCK
DQS output access time fromCK/CK#
tDQSCK
-400
DQS falling edge to CK rising – setup time
tDSS
0.2
0.2
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
0.2
0.2
0.2
tCK
DQS–DQ skew, DQS to last DQ valid, per group,
p e r a cce ss
tDQSQ
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
DQS write preamble setup time
tWPRES
0
0
0
ps
DQS write preamble
tWPRE
0.35
0.35
0.35
tCK
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
Clock cycle time
Data Strobe
-D5
Symbol
MIN
(tCH,tCL)
tAC (MAX)
tAC (MAX)
tAC (MAX)
tAC (MIN)
340
+400
MIN
(tCH,tCL)
tAC (MAX)
tAC (MIN)
400
-450
240
+450
tCK
450
-500
300
+500
ps
ps
350
ps
0.9
1.1
tCK
0.4
0.6
tCK
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 7 OF 12
ps
Product Specifications
PART NO:
REV: 1.0
VL391T5663A-E6/D5/CC
AC Timing Parameters & Specifications ( cont')
-E6
Parameter
Min
Min
0.6
0.6
Address and control input setup time
tIS
200
Address and control input hold time
tIH
275
-CC
Max
Min
Max
Unit
0.6
tCK
250
350
ps
375
475
ps
CAS# to CAS# command delay
tCCD
2
2
2
ps
ACTIVE to ACTIVE (same bank) command
tRC
60
60
55
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
7.5
7.5
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
15
15
15
ns
Four Bank Activate period
tFAW
37.5
37.5
ACTIVE to PRECHARGE command
tRAS
45
70,000
Internal READ to precharge command delay
tRTP
7.5
37.5
37.5
45
70,000
7.5
37.5
37.5
40
70,000
7.5
ns
ns
ns
Write recovery time
tWR
15
15
15
ns
Auto precharge write recovery + precharge time
tDAL
tWR+tRP
tWR+tRP
tWR+tRP
ns
Internal WRITE to READ command delay
tWTR
7.5
7.5
10
ns
PRECHARGE command period
tRP
15
15
15
ns
PRECHARGE ALL command period
tRPA
tRP+tCK
tRP+tCK
tRP+tCK
ns
LOAD MODE command cycle time
tMRD
2
2
2
tCK
CKE low to CK,CK# uncertainty
tDELAY
tIS+tCK+tIH
tIS+tCK+tIH
tIS+tCK+tIH
ns
REFRESH to Active or Refresh to Refresh
command interval
tRFC
127.5
Average periodic refresh interval
tREFI
70,000
127.5
7.8
70,000
127.5
7.8
70,000
ns
7.8
us
Exit self refresh to non-READ command
tXSNR
tRFC(MIN)+10
tRFC(MIN)+10
tRFC(MIN)+10
ns
Exit self refresh to READ
tXSRD
200
200
200
tCK
Exit self refresh timing reference
tISXR
tIS
ODT turn-on delay
tAOND
2
2
2
2
2
2
tCK
ODT turn-on
tAON
tAC(MIN)
tAC(MAX)+
700
tAC(MIN)
tAC(MAX)+
1000
tAC(MIN)
tAC(MAX)+
1000
ps
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
tCK
ODT turn-off
tAOF
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
tAC(MIN)
tAC(MAX)+
600
ps
tAONPD
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2 x tCK +
tAC(MAX)+
1000
ps
ODT turn-off (power-down mode)
tAOFPD
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
tAC(MIN)+
2000
2.5 x tCK +
tAC(MAX)+
1000
ps
ODT to power-down entry latency
tANPD
3
3
3
tCK
ODT power-down exit latency
tAXPD
8
8
8
tCK
Exit active power-down to READ command,
MR[bit12=0]
tXARD
2
2
2
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
7-AL
6-AL
6-AL
tCK
Exit precharge power-down to any non-READ
command.
tXP
2
2
2
tCK
CKE minimum high/low time
tCKE
3
3
3
tCK
ODT turn-on (power-down mode)
Power-Down
Max
tIPW
ODT
Self Refresh
Command and Address
Address and control input pulse width for each
input
-D5
Symbol
tIS
tIS
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 8 OF 12
ps
Product Specifications
PART NO:
REV: 1.0
VL391T5663A-E6/D5/CC
Package Dimensions
FRONT VIEW
3.67
MAX
133.35
3.00 (4X)
TYP.
4.00 +/- 0.10 (4X)
30.00
+ 0.50
- 0.15
17.80
TYP.
5.175 (2X)
PIN 1
TYP.
1.27 +/- 0.10
1.00
10.00
TYP.
1.50
TYP.
0.80
PIN 120
123.00
TYP.
BACK VIEW
PIN 240
3.80
TYP.
PIN 121
5.00 TYP.
55.00
TYP.
63.00
TYP.
NOTE:
All dimensions are in millimeters with tolerance +/- 0.13mm unless otherwise specified.
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 9 OF 12
Product Specifications
PART NO:
VL391T5663A-E6/D5/CC
Revision History:
Date
Rev.
P ag e
C h an g es
03/05/09
0.1
All
Engineering Sample
07/15/09
1.0
All
Spec Release
Virtium Technology, Inc. 30052 Tomas, Rancho Santa Margarita, CA 92688
Tel: 949-888-2444 Fax: 949-888-2445
PAGE 10 OF 12
REV: 1.0
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement