ADXL362 DATASHEET

ADXL362 DATASHEET
Micropower, 3-Axis, ±2 g/±4 g/±8 g
Digital Output MEMS Accelerometer
ADXL362
Data Sheet
FEATURES
GENERAL DESCRIPTION
Ultralow power
Power can be derived from coin cell battery
1.8 µA @ 100 Hz ODR, 2.0 V supply
3.0 µA @ 400 Hz ODR, 2.0 V supply
270 nA motion activated wake-up mode
10 nA standby current
High resolution: 1 mg/LSB
Built-in features for system-level power savings:
Adjustable threshold sleep/wake modes for motion
activation
Autonomous interrupt processing, without need for
microcontroller intervention, to allow the rest of the
system to be turned off completely
Deep embedded FIFO minimizes host processor load
Awake state output enables implementation of
standalone, motion activated switch
Low noise down to 175 µg/√Hz
Wide supply and I/O voltage ranges: 1.6 V to 3.5 V
Operates off 1.8 V to 3.3 V rails
Acceleration sample synchronization via external trigger
On-chip temperature sensor
SPI digital interface
Measurement ranges selectable via SPI command
Small and thin 3 mm × 3.25 mm × 1.06 mm package
The ADXL362 is an ultralow power, 3-axis MEMS accelerometer
that consumes less than 2 µA at a 100 Hz output data rate and
270 nA when in motion triggered wake-up mode. Unlike
accelerometers that use power duty cycling to achieve low power
consumption, the ADXL362 does not alias input signals by
undersampling; it samples the full bandwidth of the sensor at all
data rates.
The ADXL362 always provides 12-bit output resolution; 8-bit
formatted data is also provided for more efficient single-byte
transfers when a lower resolution is sufficient. Measurement
ranges of ±2 g, ±4 g, and ±8 g are available, with a resolution of
1 mg/LSB on the ±2 g range. For applications where a noise level
lower than the normal 550 µg/√Hz of the ADXL362 is desired,
either of two lower noise modes (down to 175 µg/√Hz typical)
can be selected at minimal increase in supply current.
In addition to its ultralow power consumption, the ADXL362
has many features to enable true system level power reduction.
It includes a deep multimode output FIFO, a built-in micropower
temperature sensor, and several activity detection modes including
adjustable threshold sleep and wake-up operation that can run
as low as 270 nA at a 6 Hz (approximate) measurement rate. A
pin output is provided to directly control an external switch when
activity is detected, if desired. In addition, the ADXL362 has
provisions for external control of sampling time and/or an
external clock.
APPLICATIONS
Hearing aids
Home healthcare devices
Motion enabled power save switches
Wireless sensors
Motion enabled metering devices
The ADXL362 operates on a wide 1.6 V to 3.5 V supply range,
and can interface, if necessary, to a host operating on a separate,
lower supply voltage. The ADXL362 is available in a 3 mm ×
3.25 mm × 1.06 mm package.
FUNCTIONAL BLOCK DIAGRAM
VS
VDDI/O
INT1
INT2
3-AXIS
MEMS
SENSOR
12-BIT
ADC
DIGITAL
LOGIC,
FIFO,
AND
SPI
MOSI
MISO
CS
SCLK
AXIS
DEMODULATORS
ANTIALIASING
FILTERS
ADXL362
10776-001
TEMPERATURE
SENSOR
GND
Figure 1.
Rev. A
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Technical Support
www.analog.com
ADXL362
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Device ID Register ..................................................................... 24
Applications ....................................................................................... 1
Device ID: 0x1D Register .......................................................... 24
General Description ......................................................................... 1
Part ID: 0xF2 Register................................................................ 24
Functional Block Diagram .............................................................. 1
Silicon Revision ID Register ..................................................... 24
Revision History ............................................................................... 3
X-Axis Data (8 MSB) Register .................................................. 24
Specifications..................................................................................... 4
Y-Axis Data (8 MSB) Register .................................................. 24
Absolute Maximum Ratings............................................................ 6
Z-Axis Data (8 MSB) Register .................................................. 24
Thermal Resistance ...................................................................... 6
Status Register ............................................................................. 25
Package Information .................................................................... 6
FIFO Entries Registers ............................................................... 26
Recommended Soldering Profile ............................................... 6
X-Axis Data Registers ................................................................ 26
ESD Caution .................................................................................. 6
Y-Axis Data Registers ................................................................ 26
Pin Configuration and Function Descriptions ............................. 7
Z-Axis Data Registers ................................................................ 26
Typical Performance Characteristics ............................................. 8
Temperature Data Registers ...................................................... 26
Theory of Operation ...................................................................... 13
Soft Reset Register ...................................................................... 26
Mechanical Device Operation .................................................. 13
Activity Threshold Registers ..................................................... 27
Operating Modes ........................................................................ 13
Activity Time Register ............................................................... 27
Selectable Measurement Ranges ............................................... 13
Inactivity Threshold Registers .................................................. 27
Selectable Output Data Rates .................................................... 13
Inactivity Time Registers ........................................................... 27
Power/Noise Tradeoff ................................................................ 14
Activity/Inactivity Control Register ........................................ 29
Power Savings Features .................................................................. 15
FIFO Control Register ............................................................... 30
Ultralow Power Consumption in All Modes .......................... 15
FIFO Samples Register .............................................................. 31
Motion Detection ....................................................................... 15
INT1/INT2 Function Map Registers ....................................... 31
FIFO ............................................................................................. 17
Filter Control Register ............................................................... 33
Communications ........................................................................ 17
Power Control Register ............................................................. 34
Additional Features ........................................................................ 18
Self Test Register ......................................................................... 35
Free Fall Detection ..................................................................... 18
Applications Information .............................................................. 36
External Clock ............................................................................ 18
Application Examples ................................................................ 36
Synchronized Data Sampling .................................................... 18
Power............................................................................................ 37
Self Test ........................................................................................ 18
FIFO Modes ................................................................................ 38
User Register Protection ............................................................ 18
Interrupts ..................................................................................... 39
Temperature Sensor ................................................................... 18
Using Synchronized Data Sampling ........................................ 40
Serial Communications ................................................................. 19
Using an External Clock ............................................................ 41
SPI Commands ........................................................................... 19
Using Self Test ............................................................................. 41
Multibyte Transfers .................................................................... 19
Operation at Voltages Other Than 2.0 V ................................ 41
Invalid Addresses and Address Folding .................................. 19
Mechanical Considerations for Mounting .............................. 41
Latency Restrictions ................................................................... 19
Axes of Acceleration Sensitivity ............................................... 42
Invalid Commands ..................................................................... 19
Layout and Design Recommendations ................................... 42
Register Map.................................................................................... 23
Outline Dimensions ....................................................................... 43
Register Details ............................................................................... 24
Ordering Guide .......................................................................... 43
Rev. A | Page 2 of 44
Data Sheet
ADXL362
REVISION HISTORY
9/12—Rev. 0 to Rev. A
Moved Revision History Section ..................................................... 3
Changes to Linking Activity and Inactivity Detection Section;
Added Figure 31, Figure 32, and Figure 33, Renumbered
Sequentially ...................................................................................... 16
Change to Table 13 .......................................................................... 29
Changes to Figure 44 ...................................................................... 36
Moved Power Supply Decoupling Section ................................... 37
Added Power Section, Power Supply Requirements Section, and
Figure 47 ........................................................................................... 37
Updated Outline Dimensions ........................................................ 43
Changes to Ordering Guide ........................................................... 43
8/12—Revision 0: Initial Version
Rev. A | Page 3 of 44
ADXL362
Data Sheet
SPECIFICATIONS
TA = 25°C, VS = 2.0 V, VDD I/O = 2.0 V, 100 Hz ODR, acceleration = 0 g, default register settings, unless otherwise noted. 1
Table 1.
Parameter
SENSOR INPUT
Measurement Range
Nonlinearity
Sensor Resonant Frequency
Cross Axis Sensitivity 2
OUTPUT RESOLUTION
All g Ranges
SENSITIVITY
Sensitivity Calibration Error
Sensitivity at XOUT, YOUT, ZOUT
Scale Factor at XOUT, YOUT, ZOUT
Sensitivity Change Due to Temperature 3
0 g OFFSET
0 g Output
0 g Offset vs. Temperature3
Normal Operation
Low Noise Mode and Ultralow Noise
Mode
NOISE PERFORMANCE
Noise Density
Normal Operation
Low Noise Mode
Ultralow Noise Mode
BANDWIDTH
Low Pass (Antialiasing) Filter, −3 dB
Corner
Output Data Rate (ODR)
SELF TEST
Output Change 4
Test Conditions/Comments
Each axis
User selectable
Percentage of full scale
Min
Typ
Max
Unit
±2, ±4, ±8
±0.5
3500
±1.5
g
%
Hz
%
12
Bits
Each axis
Each axis
2 g range
4 g range
8 g range
2 g range
4 g range
8 g range
−40°C to +85°C
Each axis
XOUT, YOUT
ZOUT
±10
%
mg/LSB
mg/LSB
mg/LSB
LSB/g
LSB/g
LSB/g
%/°C
+150
+250
mg
mg
1
2
4
1000
500
250
0.05
−150
−250
±35
±50
XOUT, YOUT
ZOUT
XOUT, YOUT, ZOUT
±0.5
±0.6
±0.35
mg/°C
mg/°C
mg/°C
XOUT, YOUT
ZOUT
XOUT, YOUT
ZOUT
XOUT, YOUT
ZOUT
VS = 3.5 V; XOUT, YOUT
VS = 3.5 V; ZOUT
550
920
400
550
250
350
175
250
µg/√Hz
µg/√Hz
µg/√Hz
µg/√Hz
µg/√Hz
µg/√Hz
µg/√Hz
µg/√Hz
HALF_BW = 0
HALF_BW = 1
User selectable in 8 steps
ODR/2
ODR/4
12.5
400
Hz
Hz
Hz
XOUT
YOUT
ZOUT
450
−710
350
580
−580
500
710
−450
650
mg
mg
mg
1.6
1.6
2.0
2.0
3.5
VS
V
V
POWER SUPPLY
Operating Voltage Range (VS)
I/O Voltage Range (VDD I/O)
Rev. A | Page 4 of 44
Data Sheet
Parameter
Supply Current
Measurement Mode
Normal Operation
Low Noise Mode
Ultralow Noise Mode
Wake-Up Mode
Standby
Power Supply Rejection Ratio (PSRR)
Input Frequency 100 Hz to 1 kHz
Input Frequency 1 kHz to 250 kHz
Turn-On Time
Power-Up to Standby
Measurement Mode Instruction to
Valid Data
TEMPERATURE SENSOR
Bias
Standard Deviation
Sensitivity Average
Standard Deviation
Sensitivity Repeatability
Resolution
ENVIRONMENTAL
Operating Temperature Range
ADXL362
Test Conditions/Comments
Min
Typ
Max
Unit
100 Hz ODR (50 Hz bandwidth) 5
1.8
3.3
13
0.27
0.01
µA
µA
µA
µA
µA
−13
−20
dB
dB
5
4/ODR
ms
350
290
0.065
0.0025
±0.5
12
LSB
LSB
°C/LSB
°C/LSB
°C
Bits
CS = 1.0 µF, RS = 100 Ω, CIO = 1.1 µF, input
is 100 mV sine wave on VS
100 Hz ODR (50 Hz bandwidth)
@ 25°C
@ 25°C
@ 25°C
−40
All minimum and maximum specifications are guaranteed. Typical specifications may not be guaranteed.
Cross axis sensitivity is defined as coupling between any two axes.
−40°C to +25°C or +25°C to +85°C.
4
Self test change is defined as the output change in g when self test is asserted.
5
Refer to Figure 30 for current consumption at other bandwidth settings.
1
2
3
Rev. A | Page 5 of 44
+85
°C
ADXL362
Data Sheet
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED SOLDERING PROFILE
Table 2.
Rating
5000 g
5000 g
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to VS
Indefinite
Figure 3 and Table 5 provide details about the recommended
soldering profile.
RAMP-UP
150°C
260°C
−50°C to +150°C
−50°C to +150°C
Figure 2 and Table 4 provide details about the package branding
for the ADXL362. For a complete listing of product availability,
see the Ordering Guide section.
Table 5. Recommended Soldering Profile
Profile Feature
Average Ramp Rate (TL to TP)
Preheat
Minimum Temperature (TSMIN)
Maximum Temperature (TSMAX)
Time (TSMIN to TSMAX)(tS)
TSMAX to TL Ramp-Up Rate
Time Maintained Above
Liquidous (TL)
Liquidous Temperature (TL)
Time (tL)
Peak Temperature (TP)
Time Within 5°C of Actual
Peak Temperature (tP)
Ramp-Down Rate
Time 25°C to Peak
Temperature
10776-002
ESD CAUTION
Figure 2. Product Information on Package (Top View)
Table 4. Package Branding Information
Branding Key
●362B
vvvv
yyww
RAMP-DOWN
TIME
PACKAGE INFORMATION
v v vv
yyww
tS
Figure 3. Recommended Soldering Profile
Device Weight
18 mg
•362B
TSMIN
t25°C TO PEAK
Table 3. Package Characteristics
θJC
85°C/W
tL
TSMAX
PREHEAT
THERMAL RESISTANCE
θJA
150°C/W
TL
10776-003
2000 V (HBM)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Package Type
16-Terminal LGA
CRITICAL ZONE
TL TO TP
tP
TP
TEMPERATURE
Parameter
Acceleration (Any Axis, Unpowered)
Acceleration (Any Axis, Powered)
VS
VDD I/O
All Other Pins
Output Short-Circuit Duration
(Any Pin to Ground)
ESD
Short Term Maximum Temperature
Four Hours
One Minute
Temperature Range (Powered)
Temperature Range (Storage)
Field Description
Pin 1 indicator and part
identifier
Factory lot code
Date code
Rev. A | Page 6 of 44
Sn63/Pb37
3°C/sec max
Condition
Pb-Free
3°C/sec max
100°C
150°C
60 sec to 120 sec
3°C/sec max
150°C
200°C
60 sec to 180 sec
3°C/sec max
183°C
60 sec to 150 sec
240 + 0/−5°C
10 sec to 30 sec
217°C
60 sec to 150 sec
260 + 0/−5°C
20 sec to 40 sec
6°C/sec max
6 minutes max
6°C/sec max
8 minutes max
Data Sheet
ADXL362
RESERVED
3
SCLK
4
RESERVED
5
NC
VS
14
ADXL362
TOP VIEW
(Not to Scale)
13
GND
12
GND
11
INT1
10
RESERVED
9
6
7
8
INT2
NOTES
1. NC = NO CONNECT. THIS PIN IS NOT
INTERNALLY CONNECTED.
10776-004
2
15
CS
NC
16
MISO
1
MOSI
VDDI/O
GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration (Top View)
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
VDD I/O
NC
Reserved
SCLK
Reserved
MOSI
MISO
CS
INT2
Reserved
INT1
GND
GND
VS
NC
GND
Description
Supply Voltage for Digital I/O.
No Connect. Not internally connected.
Reserved. May be left unconnected or connected to GND.
SPI Communications Clock.
Reserved. Can be left unconnected or connected to GND.
Master Output, Slave Input. SPI serial data input.
Master Input, Slave Output. SPI serial data output.
SPI Chip Select, Active Low. Must be low during SPI communications.
Interrupt 2 Output. INT2 also serves as an input for synchronized sampling.
Reserved. Can be left unconnected, or connected to GND.
Interrupt 1 Output. INT1 also serves as an input for external clocking.
Ground. This pin must be grounded.
Ground. This pin must be grounded.
Supply Voltage.
No Connect. Not internally connected.
Ground. This pin must be grounded.
Rev. A | Page 7 of 44
ADXL362
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
40
PERCENTAGE OF POPULATION (%)
PERCENT OF POPULATION (%)
25
20
15
10
5
35
30
25
20
15
10
–80 –70 –60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80
ZERO g OFFSET (mg)
0
10776-005
0
930
950
970
990 1010 1030 1050 1070 1090 1110 1130
SENSITIVITY (mg/LSB)
Figure 5. X-Axis Zero g Offset at 25°C, VS = 2 V
10776-008
5
Figure 8. X-Axis Sensitivity at 25°C, VS = 2 V, ±2 g Range
50
30
PERCENTAGE OF POPULATION (%)
PERCENT OF POPULATION (%)
45
25
20
15
10
5
40
35
30
25
20
15
10
–80 –70 –60 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80
ZERO g OFFSET (mg)
0
10776-006
0
970
990 1010 1030 1050 1070 1090 1110 1130
SENSITIVITY (mg/LSB)
60
20
55
PERCENTAGE OF POPULATION (%)
18
16
14
12
10
8
6
4
2
50
45
40
35
30
25
20
15
10
–170 –140
–110
–80
–50
–20
10
40
70
ZERO g OFFSET (mg)
100
0
930
950
970
990 1010 1030 1050 1070 1090 1110 1130
SENSITIVITY (mg/LSB)
Figure 10. Z-Axis Sensitivity at 25°C, VS = 2 V, ±2 g Range
Figure 7. Z-Axis Zero g Offset at 25°C, VS = 2.5 V
Rev. A | Page 8 of 44
10776-010
5
10776-007
PERCENT OF POPULATION (%)
950
Figure 9. Y-Axis Sensitivity at 25°C, VS = 2 V, ±2 g Range
Figure 6. Y-Axis Zero g Offset at 25°C, VS = 2 V
0
930
10776-009
5
Data Sheet
ADXL362
50
25
30
20
OUTPUT (mg)
PERCENT OF POPULATION (%)
40
20
15
10
10
0
–10
–20
–30
5
–40
0.2
0.4
0.6
0.8
1.0
ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/°C)
–60
–60
20
25
0
OUTPUT (mg)
30
20
15
5
–80
0.4
0.6
0.8
1.0
ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/°C)
–100
–60
60
80
100
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 12. Y-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V
Figure 15. Y-Axis Zero g Offset vs. Temperature—
16 Parts Soldered to PCB, ODR = 100 Hz, VS = 2 V
150
20
100
OUTPUT (mg)
25
15
10
5
50
0
0
–0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
ZERO g OFFSET TEMPERATURE COEFFICIENT (mg/°C)
–100
–60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 13. Z-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V
Figure 16. Z-Axis Zero g Offset vs. Temperature—
16 Parts Soldered to PCB, ODR = 100 Hz, VS = 2 V
Rev. A | Page 9 of 44
100
10776-016
–50
10776-013
PERCENT OF POPULATION (%)
40
–40
–60
0.2
20
–20
10
10776-012
PERCENT OF POPULATION (%)
40
0
0
Figure 14. X-Axis Zero g Offset vs. Temperature—
16 Parts Soldered to PCB, ODR = 100 Hz, VS = 2 V
35
–1.0 –0.8 –0.6 –0.4 –0.2
–20
TEMPERATURE (°C)
Figure 11. X-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V
0
–40
10776-015
0
10776-011
–1.0 –0.8 –0.6 –0.4 –0.2
10776-014
–50
0
ADXL362
Data Sheet
40
8
35
PERCENT OF POPULATION (%)
6
4
2
0
–2
–4
–6
25
20
15
10
–20
0
20
40
60
80
100
TEMPERATURE (°C)
0
550
575
600
625
650
675
700
PERCENT OF POPULATION (%)
35
6
4
2
0
–2
–4
–6
30
25
20
15
10
–40
–20
0
20
40
60
80
100
0
–700 –675 –650 –625 –600 –575 –550 –525 –500 –475 –450
SELF TEST DELTA (mg)
10776-021
5
–8
10776-018
SENSITIVITY DEVIATION FROM 25°C (%)
525
40
8
TEMPERATURE (°C)
Figure 21. Y-Axis Self Test Response at 25°C, VS = 2 V
Figure 18. Y-Axis Sensitivity Deviation from 25°C vs. Temperature—
16 Parts Soldered to PCB, ODR = 100 Hz, VS = 2 V
40
8
35
PERCENT OF POPULATION (%)
10
6
4
2
0
–2
–4
–6
30
25
20
15
10
5
–8
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
10776-019
SENSITIVITY DEVIATION FROM 25°C (%)
500
Figure 20. X-Axis Self Test Response at 25°C, VS = 2 V
10
–10
–60
475
SELF TEST DELTA (mg)
Figure 17. X-Axis Sensitivity Deviation from 25°C vs. Temperature—
16 Parts Soldered to PCB, ODR = 100 Hz, VS = 2 V
–10
–60
450
10776-020
–40
0
350 375 400 425 450 475 500 525 550 575 600 625 650
SELF TEST DELTA (mg)
Figure 22. Z-Axis Self Test Response at 25°C, VS = 2 V
Figure 19. Z-Axis Sensitivity Deviation from 25°C vs. Temperature—
16 Parts Soldered to PCB, ODR = 100 Hz, VS = 2 V
Rev. A | Page 10 of 44
10776-022
–10
–60
30
5
–8
10776-017
SENSITIVITY DEVIATION FROM 25°C (%)
10
ADXL362
35
70
30
60
PERCENT OF POPULATION (%)
25
20
15
10
20
25
10
PERCENT OF POPULATION (%)
12
20
15
10
5
200
250
400
350
300
10776-026
150
8
6
4
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
0
10776-024
2.7
–200
0
200
400
600
800
1000
TEMPERATURE SENSOR BIAS AT 25°C (LSB)
Figure 24. Current Consumption at 25°C, Low Noise Mode,
ODR = 100 Hz, VS = 2 V
10776-027
2
CURRENT CONSUMPTION (µA)
Figure 27. Temperature Sensor Response at 25°C, VS = 2 V
40
30
35
PERCENT OF POPULATION (%)
35
25
20
15
10
5
30
25
20
15
10
5
8
9
10
11
12
13
14
15
16
CURRENT CONSUMPTION (µA)
10776-025
0
100
Figure 26. Current Consumption at 25°C, Wake-Up Mode, VS = 2 V
30
0
50
CURRENT CONSUMPTION (nA)
Figure 23. Current Consumption at 25°C, Normal Mode,
ODR = 100 Hz, VS = 2 V
PERCENT OF POPULATION (%)
30
0
10776-023
1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05
CURRENT CONSUMPTION (µA)
PERCENT OF POPULATION (%)
40
10
5
0
50
Figure 25. Current Consumption at 25°C, Ultralow Noise Mode,
ODR = 100 Hz, VS = 2 V
0
14.4 14.6 14.8 15.0 15.2 15.4 15.6 15.8 16.0 16.2 16.4 16.6 16.8
TEMPERATURE SENSOR SCALE FACTOR (LSB/°C)
Figure 28. Temperature Sensor Scale Factor, VS = 2 V
Rev. A | Page 11 of 44
10776-028
PERCENT OF POPULATION (%)
Data Sheet
ADXL362
Data Sheet
25
20
15
10
5
0
–20
–16
–12
–8
–4
0
4
8
12
16
20
CLOCK FREQUENCY DEVIATION FROM IDEAL (%)
10776-029
PERCENT OF POPULATION (%)
30
Figure 29. Clock Frequency Deviation from Ideal at 25°C, VS = 2 V
Rev. A | Page 12 of 44
Data Sheet
ADXL362
THEORY OF OPERATION
The ADXL362 is a complete 3-axis acceleration measurement
system that operates at extremely low power consumption
levels. It measures both dynamic acceleration, resulting from
motion or shock, and static acceleration, such as tilt. Acceleration
is reported digitally and the device communicates via the SPI
protocol. Built-in digital logic enables autonomous operation
and implements functionality that enhances system level power
savings.
MECHANICAL DEVICE OPERATION
The moving component of the sensor is a polysilicon surfacemicromachined structure that is built on top of a silicon wafer.
Polysilicon springs suspend the structure over the surface of the
wafer and provide a resistance against acceleration forces.
Deflection of the structure is measured using differential
capacitors that consist of independent fixed plates and plates
attached to the moving mass. Acceleration deflects the structure
and unbalances the differential capacitor, resulting in a sensor
output whose amplitude is proportional to acceleration. Phase
sensitive demodulation determines the magnitude and polarity
of the acceleration.
OPERATING MODES
The ADXL362 has two operating modes: measurement mode for
continuous, wide bandwidth sensing; and wake-up mode for
limited bandwidth activity detection. In addition, measurement can
be suspended altogether by placing the device in standby.
Wake-Up Mode
Wake-up mode is ideal for simple detection of the presence or
absence of motion at extremely low power consumption (270 nA
at a 2.0 V supply voltage). Wake-up mode is useful particularly for
implementation of a motion activated on/off switch, allowing the
rest of the system to be powered down until activity is detected.
Wake-up mode reduces current consumption to a very low level
by measuring acceleration only about six times per second to
determine whether motion is present. If motion is detected, the
accelerometer can respond autonomously in the following ways:
•
•
•
Switch into full bandwidth measurement mode
Signal an interrupt to a microcontroller
Wake up downstream circuitry, depending on the
configuration
In wake-up mode, all accelerometer features are available with
the exception of the activity timer. All registers can be accessed,
and real-time data can be read and/or stored in the FIFO.
Standby
Placing the ADXL362 in standby suspends measurement and
reduces current consumption to 10 nA (typical). Pending
interrupts and data are preserved and no new interrupts are
generated.
The ADXL362 powers up in standby with all sensor functions
turned off.
Measurement Mode
SELECTABLE MEASUREMENT RANGES
Measurement mode is the normal operating mode of the
ADXL362. In this mode, acceleration data is read continuously
and the accelerometer consumes less than 3 µA (typical) across
its entire range of output data rates of up to 400 Hz using a 2.0 V
supply. All features described in this datasheet are available
when operating the ADXL362 in this mode.
The ADXL362 has selectable measurement ranges of ±2 g, ±4 g,
and ±8 g. Acceleration samples are always converted by a 12-bit
ADC; therefore, sensitivity scales with g range. Ranges and
corresponding sensitivity values are listed in Table 1.
The ability to continuously output data from the minimum
12.5 Hz to the maximum 400 Hz data rate while still delivering
less than 3 µA (typical) of current consumption is what defines
the ADXL362 as an ultralow power accelerometer. Other accelerometers derive low current by using a specific low power mode
that power cycles acceleration sensing. The result is a small
effective bandwidth in the low power modes and undersampling
of input data; therefore, unwanted aliasing can occur. Undersampling and aliasing do not occur with the ADXL362 because
it continuously samples the full bandwidth of its sensor at all
data rates.
When acceleration exceeds the measurement extremes, data is
clipped at the full-scale value (0x0FFF), and no damage is caused to
the accelerometer. Table 2 lists the absolute maximum ratings
for acceleration, indicating the acceleration level that can cause
permanent damage to the device.
SELECTABLE OUTPUT DATA RATES
The ADXL362 can report acceleration data at various data rates
ranging from 12.5 Hz to 400 Hz. The internal low-pass filter
pole is automatically set to ¼ or ½ the selected ODR (based on
the HALF_BW setting) to ensure the Nyquist sampling
criterion is met and no aliasing occurs.
Rev. A | Page 13 of 44
ADXL362
Data Sheet
Current consumption varies somewhat with output data rate as
shown in Figure 30, remaining below 5.0 µA over the entire
range of data rates and operating voltages.
CURRENT CONSUMPTION (µA)
6
4
3
Table 7 lists the current consumption and noise densities obtained
for normal operation and the two lower noise modes at a typical
2.0 V supply.
2
1
0
100
200
300
400
OUTPUT DATA RATE (Hz)
Table 7. Noise and Current Consumption: Normal Operation,
Low Noise Mode, and Ultralow Noise Mode @ VS = 2.0 V
10776-030
0
The ADXL362 offers a few options for decreasing noise at the
expense of only a small increase in current consumption.
The noise performance of the ADXL362 in normal operation,
typically 7 LSB rms at 100 Hz bandwidth, is adequate for most
applications, depending upon bandwidth and the desired resolution. For cases where lower noise is needed, the ADXL362
provides two lower noise operating modes that trade reduced
noise for a somewhat higher current consumption.
VS = 1.6V
VS = 2.0V
VS = 2.5V
VS = 3.0V
VS = 3.5V
5
POWER/NOISE TRADEOFF
Figure 30. Current Consumption vs. Output Data Rate at Several
Supply Voltages
Antialiasing
The analog-to-digital converter (ADC) of the ADXL362 samples
at the (user selected) output data rate. In the absence of antialiasing filtering, it aliases any input signals whose frequency is
more than half the data rate. To mitigate this, a two-pole lowpass filter is provided at the input of the ADC.
The user can set this antialiasing filter to a bandwidth that is at
½ the data rate or ¼ the data rate. Setting the antialiasing filter
pole to ½ of the output data rate provides less aggressive
antialiasing filtering, but maximizes bandwidth and is adequate
for most applications. Setting the pole to ¼ of the data rate
reduces bandwidth for a given data rate, but provides more
aggressive antialiasing.
The antialiasing filter of the ADXL362 defaults to the more
conservative setting, where bandwidth is set to one-fourth the
output data rate.
Mode
Normal Operation
Low Noise
Ultralow Noise
Noise
(µg/√Hz)
Typical
550
400
250
Current
Consumption (µA)
Typical
1.8
3.0
10
Operating the ADXL362 at a higher supply voltage also decreases
noise. Table 8 lists the current consumption and noise densities
obtained for normal operation and the two lower noise modes
at the highest recommended supply, 3.3 V.
Table 8. Noise and Current Consumption: Normal Operation,
Low Noise Mode, and Ultralow Noise Mode @ VS = 3.3 V
Mode
Normal Operation
Low Noise
Ultralow Noise
Rev. A | Page 14 of 44
Noise
(µg/√Hz)
Typical
380
280
175
Current
Consumption (µA)
Typical
2.7
4.5
15
Data Sheet
ADXL362
POWER SAVINGS FEATURES
Designed for the most power conscious applications, the ADXL362
includes several features (as described in this section) for enabling
power savings at the system level, as well as at the device level.
ULTRALOW POWER CONSUMPTION IN ALL
MODES
At the device level, the most obvious power saving feature of the
ADXL362 is its ultralow current consumption in all configurations.
The ADXL362 consumes between 1.1 µA (typical) and 5 µA
(typical) across all data rates up to 400 Hz and all supply voltages
up to 3.5 V (see Figure 30). An even lower power, 270 nA (typical)
motion triggered wake-up mode is provided for simple motion
detection applications that require a power consumption lower
than 1 µA.
At these current levels, the accelerometer consumes less power
in full operation than the standby currents of many other
system components, and is, therefore, optimal for applications that
require continuous acceleration monitoring and very long
battery life. Because the accelerometer is always on, it can act as
a motion activation switch. The accelerometer signals to the rest
of the system when to turn on, thereby managing power at the
system level.
As important as its low operating current, the 10 nA (typical)
standby current of the ADXL362 contributes to a much longer
battery life in applications that spend most of their time in a
sleep state and wake up via an external trigger.
In many applications, it is advantageous for activity detection to
be based not on an absolute threshold, but on a deviation from
a reference point or orientation. This is particularly useful
because it removes the effect on activity detection of the static
1 g imposed by gravity. When an accelerometer is stationary, its
output can reach 1 g, even when it is not moving. In absolute
activity, when the threshold is set to less than 1 g, activity is
immediately detected in this case.
In the referenced configuration, activity is detected when
acceleration samples are at least a user set amount above an
internally defined reference for the user defined amount of time,
as described in Equation 1.
ABS(Acceleration − Reference) > Threshold
(1)
Consequently, activity is detected only when the acceleration
has deviated sufficiently from the initial orientation. The
reference for activity detection is calculated when activity
detection is engaged in the following scenarios:
• When the activity function is turned on and measurement
mode is engaged;
• If link mode is enabled: when inactivity is detected and
activity detection begins; or
• If link mode is not enabled: when activity is detected and
activity detection repeats.
The referenced configuration results in a very sensitive activity
detection that detects even the most subtle motion events.
MOTION DETECTION
Fewer False Positives
The ADXL362 features built-in logic that detects activity (presence
of acceleration above a threshold) and inactivity (lack of
acceleration above a threshold). Activity and inactivity events
can be used as triggers to manage the accelerometer mode of
operation, trigger an interrupt to a host processor, and/or
autonomously drive a motion switch.
Ideally, the intent of activity detection is to wake up a system
only when motion is intentional, ignoring noise or small,
unintentional movements. In addition to being sensitive to
subtle motion events, the ADXL362 activity detection algorithm
is designed to be robust in filtering out undesired triggers.
Detection of an activity or inactivity event is indicated in the
status register and can be configured to generate an interrupt.
In addition, the activity status of the device, that is, whether it is
moving or stationary, is indicated by the AWAKE bit, described
in the Using the AWAKE Bit section.
Activity and inactivity detection can be used when the accelerometer is in either measurement mode or wake-up mode.
Activity Detection
An activity event is detected when acceleration remains above a
specified threshold for a specified time period.
Referenced and Absolute Configurations
Activity detection can be configured as referenced or absolute.
When using absolute activity detection, acceleration samples are
compared to a user set threshold to determine whether motion
is present. For example, if a threshold of 0.5 g is set and the
acceleration on the z-axis is 1 g for longer than the user defined
activity time, the activity status asserts.
The ADXL362 activity detection functionality includes a timer
to filter out unwanted motion and ensure that only sustained
motion is recognized as activity. The duration of this timer, as
well as the acceleration threshold, are user adjustable from one
sample (that is, no timer) to up to 20 seconds of motion.
Note that the activity timer is operational in measurement mode
only. In wake-up mode, one-sample activity detection is used.
Inactivity Detection
An inactivity event is detected when acceleration remains below
a specified threshold for a specified time. Inactivity detection is
also configurable as referenced or absolute.
When using absolute inactivity detection, acceleration samples
are compared to a user set threshold for the user set time to
determine the absence of motion. Inactivity is detected when
enough consecutive samples are all below the threshold. The
absolute configuration of inactivity should be used for
implementing free fall detection.
Rev. A | Page 15 of 44
ADXL362
Data Sheet
When using referenced inactivity detection, inactivity is
detected when acceleration samples are within a user specified
amount of an internally defined reference (as described by
Equation 2) for a user defined amount of time.
WAIT FOR
PROCESSOR TO
CLEAR INTERRUPT
AWAKE = 1
INACTIVITY
INTERRUPT
TRIGGERS
(2)
Referenced inactivity, like referenced activity, is particularly
useful for eliminating the effects of the static acceleration due to
gravity. With absolute inactivity, if the inactivity threshold is set
lower than 1 g, a device resting motionless may never detect
inactivity. With referenced inactivity, the same device under the
same configuration detects inactivity.
The inactivity timer can be set to anywhere from 2.5 ms (a single
sample at 400 Hz ODR) to almost 90 minutes (65,535 samples
at 12.5 Hz ODR) of inactivity. A requirement for inactivity detection is that for whatever period of time the inactivity timer has
been configured, the accelerometer detects inactivity only when
it has been stationary for that amount of time.
For example, if the accelerometer has been configured for
90 minutes, the accelerometer detects inactivity when it has
been stationary for 90 minutes. The wide range of timer settings
means that in applications where power conservation is critical,
the system can be put to sleep after very short periods of
inactivity. In applications where continuous operation is critical, the
system stays on for as long as any motion is present.
Linking Activity and Inactivity Detection
ACTIVITY
INTERRUPT
TRIGGERS
AWAKE = 1
WAIT FOR
PROCESSOR TO
CLEAR INTERRUPT
10776-131
WAIT FOR
INACTIVITY
EVENT
Figure 31. Flowchart Illustrating Activity and Inactivity Operation in Default Mode
In linked mode, each interrupt must be serviced by a host
processor before the next interrupt is enabled.
Linked mode operation is illustrated in the flowchart in Figure 32.
WAIT FOR
PROCESSOR TO
CLEAR INTERRUP
WAIT FOR
ACTIVITY
EVENT
ACTIVITY
INTERRUPT
AWAKE = 1
AWAKE = 0
WAIT FOR
PROCESSOR TO
CLEAR INTERRUPT
INACTIVITY
INTERRUPT
WAIT FOR
INACTIVITY
EVENT
10776-132
ABS(Acceleration − Reference) < Threshold
WAIT FOR
ACTIVITY
EVENT
Figure 32. Flowchart Illustrating Activity and Inactivity Operation in Linked Mode
Loop Mode
Default Mode
The user must enable the activity and inactivity functions
because these functions are not automatically enabled by
default. After the user enables the activity and inactivity
functions, the ADXL362 exhibits the following behavior when it
enters default mode: Both activity and inactivity detection
remain enabled and all interrupts must be serviced by a host
processor; that is, a processor must read each interrupt before it
is cleared and can be used again.
In loop mode, motion detection operates as described in the
Linked Mode section, but interrupts do not need to be serviced
by a host processor. This configuration simplifies the implementation of commonly used motion detection and enhances power
savings by reducing the amount of power used in bus communication.
Loop mode operation is illustrated in the flowchart in Figure 33.
AWAKE = 1
WAIT FOR
ACTIVITY
EVENT
WAIT FOR
INACTIVITY
EVENT
Loop mode operation is illustrated in the flowchart in Figure 32.
AWAKE = 0
Linked Mode
10776-133
The activity and inactivity detection functions can be used
concurrently and processed manually by a host processor, or
they can be configured to interact in several other ways, as
follows.
Figure 33. Flowchart Illustrating Activity and Inactivity Operation in Loop Mode
In linked mode, activity and inactivity detection are linked to
each other such that only one of the functions is enabled at any
given time. As soon as activity is detected, the device is assumed
to be moving (or awake) and stops looking for activity; rather,
inactivity is expected as the next event. Therefore, only inactivity
detection operates.
Similarly, when inactivity is detected, the device is assumed to
be stationary (or asleep). Thus, activity is expected as the next
event; therefore, only activity detection operates.
Autosleep
When in linked or loop mode, enabling autosleep causes the
device to enter wake-up mode autonomously (see the Wake-Up
Mode section) when inactivity is detected, and to reenter
measurement mode when activity is detected.
The autosleep configuration is active only if linked or loop modes
are enabled. In the default mode, the autosleep setting is ignored.
Rev. A | Page 16 of 44
Data Sheet
ADXL362
Using the AWAKE Bit
COMMUNICATIONS
The AWAKE bit is a status bit that indicates whether the ADXL362
is awake or asleep. The device is awake when it has experienced
an activity condition, and it is asleep when it has experienced an
inactivity condition.
SPI Instructions
The awake signal can be mapped to the INT1 or INT2 pin,
allowing the pin to serve as a status output to connect or disconnect power to downstream circuitry based on the awake
status of the accelerometer. Used in conjunction with loop
mode, this configuration implements a trivial, autonomous
motion activated switch, as shown in Figure 43.
•
If the turn-on time of downstream circuitry can be tolerated,
this motion switch configuration can save significant system
level power by eliminating the standby current consumption of
the remainder of the application. This standby current can often
exceed the full operating current of the ADXL362.
The digital interface of the ADXL362 is implemented with
system level power savings in mind. The following features
enhance power savings:
•
•
FIFO
The ADXL362 includes a deep 512-sample first in, first out (FIFO)
buffer. The FIFO provides benefits primarily in two ways, as
follows.
System Level Power Savings
Appropriate use of the FIFO enables system level power savings
by enabling the host processor to sleep for extended periods of
time while the accelerometer autonomously collects data. Alternatively, using the FIFO to collect data can unburden the host
while it tends to other tasks.
Data Recording/Event Context
The FIFO can be used in a triggered mode to record all data
leading up to an activity detection event, thereby providing context for the event. In the case of a system that identifies impact
events, for example, the accelerometer can keep the entire system
off while it stores acceleration data in its FIFO and looks for an
activity event. When the impact event occurs, data that was
collected prior to the event is frozen in the FIFO. The accelerometer can then wake the rest of the system and transfer this
data to the host processor, thereby providing context for the
impact event.
Generally, the more context available, the more intelligent
decisions a system can achieve, making a deep FIFO especially
useful. The ADXL362 FIFO can store up to more than 13 seconds
of data, providing a clear picture of events prior to an activity
trigger.
All FIFO modes of operation, as well as the structure of the FIFO
and instructions for retrieving data from it, are described in further
detail in the FIFO Modes section of this data sheet.
Burst reads and writes reduce the number of SPI
communication cycles required to configure the part
and retrieve data.
Concurrent operation of activity and inactivity detection
enables “set it and forget it” operation. Linked and loop
modes further reduce communications power by enabling
the clearing of interrupts without processor intervention.
The FIFO is implemented such that consecutive samples
can be read continuously via a multibyte read of unlimited
length; thus, one read FIFO instruction can clear the entire
contents of the FIFO. In many other accelerometers, each
read instruction retrieves a single sample only. In addition, the
ADXL362 FIFO construction allows the use of direct memory
access (DMA) to read the FIFO contents.
Bus Keepers
The ADXL362 includes bus keepers on all digital interface pins:
MISO, MOSI, SCLK, CS, INT1, and INT2. Bus keepers are used
to prevent tristate bus lines from floating when nothing is driving
them, thus preventing through current in any gate inputs that
are on the bus.
MSB Registers
Acceleration and temperature measurements are converted to
12-bit values and transmitted via SPI using two registers per
measurement. To read a full sample set of 3-axis acceleration
data, six registers must be read.
Many applications do not require the accuracy that 12-bit data
provides and prefer, instead, to save system level power. The MSB
registers XDATA, YDATA, and ZDATA enable this tradeoff.
These registers contain the eight MSBs of the x-, y-, and z-axis
acceleration data; reading them effectively provides 8-bit acceleration values. Importantly, only three (consecutive) registers
must be read to retrieve a full data set, significantly reducing the
time during which the SPI bus is active and drawing current.
12-bit and 8-bit data are available simultaneously so that both
data formats can be used in a single application, depending on
the needs of the application at a given time. For example, the processor can read 12-bit data when higher resolution is required, and
switch to 8-bit data (simply by reading a different set of registers)
when application requirements change.
Rev. A | Page 17 of 44
ADXL362
Data Sheet
ADDITIONAL FEATURES
FREE FALL DETECTION
SYNCHRONIZED DATA SAMPLING
Many digital output accelerometers include a built-in free fall
detection feature. In the ADXL362, this function can be implemented using the inactivity interrupt. Refer to the Applications
Information section for more details, including suggested
threshold and timing values.
For applications that require a precisely timed acceleration
measurement, the ADXL362 features an option to synchronize
acceleration sampling to an external trigger.
EXTERNAL CLOCK
The ADXL362 has a built-in 51.2 kHz (typical) clock that, by
default, serves as the time base for internal operations.
ODR and bandwidth scale proportionally with the clock. The
ADXL362 provides a discrete number of options for ODR, such
as 100 Hz, 50 Hz, 25 Hz, and so forth, in factors of 2, (see the
Filter Control Register section for a complete listing). To
achieve data rates other than those provided, an external clock
can be used at the appropriate clock frequency. The output data
rate scales with the clock frequency, as shown in Equation 3.
ODR ACTUAL = ODRSELECTED ×
f
51.2 kHz
(3)
For example, to achieve an 80 Hz ODR, select the 100 Hz ODR
setting and provide a clock frequency that is 80% of nominal, or
41.0 kHz.
The ADXL362 can operate with external clock frequencies
ranging from the nominal 51.2 kHz down to 25.6 kHz to allow
the user to achieve any desired output data rate.
Alternatively, an external clock can be used to improve clock
frequency accuracy. The distribution of clock frequencies
among a sampling of >1000 parts has a standard deviation of
approximately 3%. To achieve tighter tolerances, a more
accurate clock can be provided externally.
Bandwidth automatically scales to ½ or ¼ of the ODR (based
on the HALF_BW setting), and this ratio is preserved, regardless
of clock frequency. Power consumption also scales with clock
frequency: higher clock rates increase power consumption.
Figure 34 shows how power consumption varies with clock rate.
2.5
2.0
The ADXL362 incorporates a self test feature that effectively
tests its mechanical and electronic systems simultaneously.
When the self test function is invoked, an electrostatic force is
applied to the mechanical sensor. This electrostatic force moves the
mechanical sensing element in the same manner as acceleration,
and it is additive to the acceleration experienced by the device.
This added electrostatic force results in an output change on all
three axes.
USER REGISTER PROTECTION
The ADXL362 includes user register protection for single event
upsets (SEUs). An SEU is a change of state caused by ions or
electromagnetic radiation striking a sensitive node in a microelectronic device. The state change is a result of the free charge
created by ionization in or close to an important node of a logic
element (for example, a memory bit). The SEU, itself, is not considered permanently damaging to transistor or circuit functionality,
but it can create erroneous register values. The ADXL362 registers
that are protected from SEU are Register 0x20 to Register 0x2E.
SEU protection is implemented via a 99-bit error correcting
(Hamming-type) code that detects both single- and double-bit
errors. The check bits are recomputed any time a write to any of
the protected registers occurs. At any time, if the stored version
of the check bits is not in agreement with the current check bit
calculation, the ERR_USER_REGS status bit is set.
The SEU bit in the status register is set on power-up prior to
device configuration; it clears upon the first register write to
that device.
TEMPERATURE SENSOR
The ADXL362 includes an integrated temperature sensor that
can monitor internal system temperature or improve the temperature stability of the device via calibration. For example, acceleration
outputs vary with temperature at a rate of ±0.5 mg/°C (typical),
but the relationship to temperature is repeatable and can be
calibrated.
To use the temperature sensor to monitor absolute temperature,
it is recommended that its initial bias (its output at some known
temperature) is measured and calibrated.
1.5
1.0
0.5
VS = 1.6V
VS = 2.0V
VS = 3.5V
0
43
44
45
46
47
48
49
50
51
EXTERNAL CLOCK FREQUENCY (kHz)
52
10776-031
CURRENT CONSUMPTION (µA)
3.0
SELF TEST
Figure 34. Current Consumption vs. External Clock Rate
Rev. PrA Page 4 of 8
Data Sheet
ADXL362
SERIAL COMMUNICATIONS
The ADXL362 communicates via a 4-wire SPI and operates as a
slave. Ignore data that is transmitted from the ADXL362 to the
master device during writes to the ADXL362.
As shown in Figure 36 to Figure 40, the MISO pin is in a high
impedance state, held by a bus keeper, except when the ADXL362
is sending read data (to conserve bus power).
Wire the ADXL362 for SPI communication as shown in the
connection diagram in Figure 35. The recommended SPI clock
speeds are 1 MHz to 5 MHz, with 12 pF maximum loading.
The SPI timing scheme follows CPHA = CPOL = 0.
For correct operation of the part, the logic thresholds and timing
parameters in Table 9 and Table 10 must be met at all times.
Refer to Figure 41 and Figure 42 for visual diagrams of the
timing parameters.
MULTIBYTE TRANSFERS
Multibyte transfers, also known as burst transfers, are supported
for all SPI commands: register read, register write, and FIFO
read commands. It is recommended that data be read using
multibyte transfers to ensure that a concurrent and complete set
of x-, y-, and z-acceleration (and temperature, where applicable)
data is read.
CS
DOUT
MOSI
DOUT
The FIFO runs on the serial port clock during FIFO reads and
can sustain bursting at the SPI clock rate as long as the SPI clock
is 1 MHz or faster.
MISO
DIN
Register Read/Write Auto-Increment
SCLK
DOUT
PROCESSOR
10776-032
ADXL362
Figure 35. 4-Wire SPI Connection Diagram
SPI COMMANDS
The SPI port uses a multibyte structure wherein the first byte is
a command. The ADXL362 command set is
•
•
•
It is recommended that an even number of bytes be read (using
a multibyte transaction) because each sample consists of two
bytes: 2 bits of axis information and 14 bits of data. If an odd
number of bytes is read, it is assumed that the desired data was
read; therefore, the second half of the last sample is discarded so
a read from the FIFO always starts on a properly aligned evenbyte boundary. Data is presented least significant byte first,
followed by the most significant byte.
0x0A: write register
0x0B: read register
0x0D: read FIFO
Read and Write Register Commands
The command structure for the read register and write register
commands is as follows (see Figure 36 and Figure 37):
</CS down> <command byte (0x0A or 0x0B)> <address
byte> <data byte> <additional data bytes for multi-byte> …
</CS up>
The read and write register commands support multibyte
(burst) read/write access. The waveform diagrams for multibyte read and write commands are shown in Figure 38 and
Figure 39.
Read FIFO Command
Reading from the FIFO buffer is a command structure that does
not have an address.
</CS down> <command byte (0x0D)> <data byte> <data
byte> … </CS up>
A register read or write command begins with the address
specified in the command and auto-increments for each
additional byte in the transfer. To avoid address wrapping and
side effects of reading registers multiple times, the autoincrement halts at the invalid Register Address 63 (0x3F).
INVALID ADDRESSES AND ADDRESS FOLDING
The ADXL362 has a 6-bit address bus, mapping only 64
registers in the possible 256 register address space. The
addresses do not fold to repeat the registers at addresses above
64. Attempted access to register addresses above 64 are mapped
to the invalid register at 63 (0x3F) and have no functional effect.
Address 0x00 to Address 0x2E are for customer access, as
described in the register map. Address 0x2F to Address 0x3F are
reserved for factory use.
LATENCY RESTRICTIONS
Reading any of the data registers (0x08 to 0x0A or 0x0E to
0x15) clears the data ready interrupt. There can be as much as
an 80 µs delay from reading a register to the clearing of the data
ready interrupt.
Other register reads, register writes, and FIFO reads have no
latency restrictions.
INVALID COMMANDS
Commands other than 0x0A, 0x0B, and 0x0D have no effect.
The MISO output remains in a high impedance state, and the
bus keeper holds the MISO line at its last value.
Rev. A | Page 19 of 44
ADXL362
Data Sheet
CS
0
1
2
0
0
0
3
4
5
6
7
8
9
1
1
7
6
10
11
12
13
14
15
1
0
16
17
18
7
6
5
19
20
21
22
23
2
1
0
SCLK
INSTRUCTION
1
0
8-BIT
ADDRESS
8
BI
BIT AD
DD
DRES
ES
SS
0
5
4
3
2
10776-033
MOSI
DATA OUT
MISO
4
3
Figure 36. Register Read
CS
0
1
2
0
0
0
3
5
6
7
8
9
10
0
1
0
7
6
5
4
11
12
13
14
15
16
17
18
1
0
7
6
5
19
20
21
22
23
2
1
0
7
6
5
7
6
5
SCLK
RE
ES
SS
ES
DDR
AD
BIT ADDRESS
8 BI
8-BIT
0
1
4
3
DATA BYTE
2
4
3
10776-034
INSTRUCTION
MOSI
HIGH IMPEDANCE
MISO
Figure 37. Register Write
CS
0
1
0
0
2
3
4
5
6
7
8
9
1
1
7
6
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
8-BIT ADDRESS
0
0
1
0
5
4
3
2
1
0
OUT BYTE 1
7
MISO
6
5
4
3
2
OUT BYTE n
1
0
4
3
2
1
0
1
0
10776-035
INSTRUCTION
MOSI
Figure 38. Burst Read
CS
0
1
0
0
2
3
4
5
6
7
8
9
7
6
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
0
1
0
1
0
5
4
3
2
1
7
0
6
5
4
3
2
DATA BYTE n
1
0
4
3
2
10776-036
0
DATA BYTE 1
8-BIT ADDRESS
INSTRUCTION
MOSI
HIGH IMPEDANCE
MISO
Figure 39. Burst Write
CS
0
1
2
0
0
0
3
4
5
6
7
1
0
1
8
9
10
7
6
5
11
12
13
14
15
2
1
0
SCLK
0
1
OUT BYTE 1
MISO
4
3
OUT BYTE n
Figure 40. FIFO Read
Rev. A | Page 20 of 44
7
6
5
4
3
2
1
0
10776-037
INSTRUCTION
MOSI
Data Sheet
ADXL362
tCSD
CS
tR
CSS
tCSH
tF
tCLE
tCLD
SCLK
tSU
MSB IN
LSB IN
10776-038
MOSI
tHD
HIGH IMPEDANCE
MISO
Figure 41. Timing Diagram for SPI Write Instructions
CS
tHIGH
tLOW
tCSH
SCLK
tV
MSB OUT
LSB OUT
10776-039
MOSI
tDIS
tHO
DON’T CARE
MISO
Figure 42. Timing Diagram for SPI Read Instructions
Table 9. SPI Digital Input/Output
Parameter
Digital Input
Low Level Input Voltage (VIL)
High Level Input Voltage (VIH)
Low Level Input Current (IIL)
High Level Input Current (IIH)
Digital Output
Low Level Output Voltage (VOL)
High Level Output Voltage (VOH)
Low Level Output Current (IOL)
High Level Output Current (IOH)
1
Test Conditions/Comments
Min
Limit 1
Max
0.3 × VDD I/O
0.7 × VDD I/O
VIN = VDD I/O
VIN = 0 V
IOL = 10 mA
IOH = −4 mA
VOL = VOL, max
VOH = VOH, min
Limits based on characterization results, not production tested.
Rev. A | Page 21 of 44
0.1
−0.1
0.2 × VDD I/O
0.8 × VDD I/O
10
−4
Unit
V
V
µA
µA
V
V
mA
mA
ADXL362
Data Sheet
Table 10. SPI Timing (TA = 25°C, VS = 2.0 V, VDD I/O = 2.0 V) 1
Parameter
fCLK
Min
CSS
Limit 2, 3
Max
1
Unit
MHz
Description
Clock Frequency
100
ns
CS Setup Time
tCSH
100
ns
CS Hold Time
tCSD
10
ns
CS Disable Time
tSU
50
ns
Data Setup Time
tHD
50
ns
Data Hold Time
tR
0
100
ns
SCLK Rise Time
tF
0
100
ns
SCLK Fall Time
tHIGH
100
ns
Clock High Time
tLOW
100
ns
Clock Low Time
tCLD
100
ns
Clock Delay Time
tCLE
100
ns
Clock Enable Time
tV
0
ns
Output Valid from Clock Low
tHO
0
200
ns
Output Hold Time
tDIS
0
200
ns
Output Disable Time
The CS, SCLK, MOSI, and MISO pins are not internally pulled up or down; they must be driven for proper operation.
Limits based on design targets; not production tested.
3
The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 9.
1
2
Rev. A | Page 22 of 44
Data Sheet
ADXL362
REGISTER MAP
Table 11. Register Summary
Reg
0x00
0x01
0x02
0x03
0x08
0x09
0x0A
0x0B
Name
DEVID_AD
DEVID_MST
PARTID
REVID
XDATA
YDATA
ZDATA
STATUS
Bits Bit 7
Bit 6
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0] ERR_USER_ AWAKE
REGS
0x0C FIFO_ENTRIES_L [7:0]
0x0D FIFO_ENTRIES_H [7:0]
0x0E XDATA_L
[7:0]
0x0F XDATA_H
[7:0]
0x10 YDATA_L
[7:0]
0x11 YDATA_H
[7:0]
0x12 ZDATA_L
[7:0]
0x13 ZDATA_H
[7:0]
0x14 TEMP_L
[7:0]
0x15 TEMP_H
[7:0]
0x16 Reserved
[7:0]
0x17 Reserved
[7:0]
0x1F SOFT_RESET
[7:0]
0x20 THRESH_ACT_L
[7:0]
0x21 THRESH_ACT_H [7:0]
0x22 TIME_ACT
[7:0]
0x23 THRESH_INACT_L [7:0]
0x24 THRESH_INACT_H [7:0]
0x25 TIME_INACT_L
[7:0]
0x26 TIME_INACT_H
[7:0]
0x27 ACT_INACT_CTL [7:0]
RES
0x28 FIFO_CONTROL
[7:0]
0x29 FIFO_SAMPLES
[7:0]
0x2A INTMAP1
[7:0] INT_LOW
AWAKE
0x2B INTMAP2
0x2C FILTER_CTL
0x2D POWER_CTL
0x2E SELF_TEST
Bit 5
Bit 4
Bit 3
DEVID_AD[7:0]
DEVID_MST[7:0]
PARTID[7:0]
REVID[7:0]
XDATA[7:0]
YDATA[7:0]
ZDATA[7:0]
ACT
FIFO_OVERRUN
FIFO_ENTRIES_L[7:0]
UNUSED
XDATA_L[7:0]
Reset
0xAD
0x1D
0xF2
0x01
0x00
0x00
0x00
INACT
FIFO_WATER- FIFO_READY DATA_READY 0x40
MARK
0x00
FIFO_ENTRIES_H[1:0]
0x00
0x00
SX
XDATA_H[3:0]
0x00
YDATA_L[7:0]
0x00
SX
YDATA_H[3:0]
0x00
ZDATA_L[7:0]
0x00
SX
ZDATA_H[3:0]
0x00
TEMP_L[7:0]
0x00
SX
TEMP_H[3:0]
0x00
Reserved[7:0]
0x00
Reserved[7:0]
0x00
SOFT_RESET[7:0]
0x00
THRESH_ACT_L[7:0]
0x00
UNUSED
THRESH_ACT_H[2:0]
0x00
TIME_ACT[7:0]
0x00
THRESH_INACT_L[7:0]
0x00
UNUSED
THRESH_INACT_H[2:0]
0x00
TIME_INACT_L[7:0]
0x00
TIME_INACT_H[7:0]
0x00
LINKLOOP
INACT_REF
INACT_EN
ACT_REF
ACT_EN
0x00
UNUSED
AH
FIFO_TEMP
FIFO_MODE
0x00
FIFO_SAMPLES[7:0]
0x80
INACT
ACT
FIFO_OVER- FIFO_WATER- FIFO_READY DATA_READY 0x00
RUN
MARK
[7:0] INT_LOW
AWAKE
INACT
ACT
FIFO_OVER- FIFO_WATER- FIFO_READY DATA_READY 0x00
RUN
MARK
[7:0]
RANGE
RES
HALF_BW
EXT_SAMPLE
ODR
0x13
[7:0] RES
EXT_CLK
LOW_NOISE
WAKEUP
AUTOSLEEP
MEASURE
0x00
[7:0]
UNUSED
ST
0x00
Rev. A | Page 23 of 44
Bit 2
Bit 1
Bit 0
RW
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
W
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
ADXL362
Data Sheet
REGISTER DETAILS
This section describes the functions of the ADXL362 registers.
The ADXL362 powers up with default register values in the as
shown in the Reset column of Table 11 in the Register Map
section.
Note that any changes to the registers before the POWER_CTL
register (Register 0x00 to Register 0x2C) should be made with
the device in standby. If changes are made while the ADXL362
is in measurement mode, they may be effective for only part of
a measurement.
X-AXIS DATA (8 MSB) REGISTER
Address: 0x08, Reset: 0x00, Name: XDATA
This register holds the eight most significant bits of the x-axis
acceleration data. This limited resolution data register is used in
power conscious applications where eight bits of data are sufficient:
energy can be conserved by reading only one byte of data per
axis, rather than two.
DEVICE ID REGISTER
Address: 0x00, Reset: 0xAD, Name: DEVID_AD
Y-AXIS DATA (8 MSB) REGISTER
This register contains the Analog Devices device ID, 0xAD.
Address: 0x09, Reset: 0x00, Name: YDATA
This register holds the eight most significant bits of the y-axis
acceleration data. This limited resolution data register is used in
power conscious applications where eight bits of data are sufficient:
energy can be conserved by reading only one byte of data per
axis, rather than two.
DEVICE ID: 0x1D REGISTER
Address: 0x01, Reset: 0x1D, Name: DEVID_MST
This register contains the Analog Devices MEMS device
ID, 0x1D.
Z-AXIS DATA (8 MSB) REGISTER
Address: 0x0A, Reset: 0x00, Name: ZDATA
PART ID: 0xF2 REGISTER
This register holds the eight most significant bits of the z-axis
acceleration data. This limited resolution data register is used in
power conscious applications where eight bits of data are sufficient:
energy can be conserved by reading only one byte of data per
axis, rather than two.
Address: 0x02, Reset: 0xF2, Name: PARTID
This register contains the device ID, 0xF2 (362 octal).
SILICON REVISION ID REGISTER
Address: 0x03, Reset: 0x01, Name: REVID
This register contains the product revision ID, beginning with
0x01 and incrementing for each subsequent revision.
Rev. A | Page 24 of 44
Data Sheet
ADXL362
STATUS REGISTER
Address: 0x0B, Reset: 0x40, Name: STATUS
This register includes the following bits that describe various conditions of the ADXL362.
Table 12. Bit Descriptions for STATUS
Bits
7
Bit Name
ERR_USER_REGS
6
AWAKE
5
INACT
4
ACT
3
FIFO_OVERRUN
2
FIFO_WATERMARK
1
FIFO_READY
0
DATA_READY
Settings
Description
SEU Error Detect. 1 indicates one of two conditions: either an SEU event,
such as an alpha particle of a power glitch, has disturbed a user register
setting or the ADXL362 is not configured. This bit is high upon both
startup and soft reset, and resets as soon as any register write commands
are performed.
Indicates whether the accelerometer is in an active (AWAKE = 1) or
inactive (AWAKE = 0) state, based on the activity and inactivity
functionality. To enable autosleep, activity and inactivity detection must
be in linked mode or loop mode (LINK/LOOP bits in the ACT_INACT_CTL
register); otherwise, this bit defaults to 1 and should be ignored.
Inactivity. 1 indicates that the inactivity detection function has detected
an inactivity or a free fall condition.
Activity. 1 indicates that the activity detection function has detected an
overthreshold condition.
FIFO Overrun. 1 indicates that the FIFO has overrun or overflowed, such
that new data replaces unread data. See the Using FIFO Interrupts
section for details.
FIFO Watermark. 1 indicates that the FIFO contains at least the desired
number of samples, as set in the FIFO_SAMPLES register. See the Using
FIFO Interrupts section for details.
FIFO Ready. 1 indicates that there is at least one sample available in the
FIFO output buffer. See the Using FIFO Interrupts section for details.
Data Ready. 1 indicates that a new valid sample is available to be read.
This bit clears when a FIFO read is performed. See the Data Ready
Interrupt section for more details.
Rev. A | Page 25 of 44
Reset
0x0
Access
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
ADXL362
Data Sheet
FIFO ENTRIES REGISTERS
Z-AXIS DATA REGISTERS
These registers indicate the number of valid data samples
present in the FIFO buffer. This number ranges from 0 to 512
or 0x00 to 0x200. FIFO_ENTRIES_L contains the least significant
byte. FIFO_ENTRIES_H contains the two most significant bits.
Bits[15:10] of FIFO_ENTRIES_H are unused (represented as X
= don’t care).
These two registers contain the sign extended (SX) z-axis
acceleration data. ZDATA_L contains the eight LSBs, and
ZDATA_H contains the four MSBs of the 12-bit value.
The sign extension bits (B[15:12], denoted as SX in the
ZDATA_H bit map that follows) have the same value as the
MSB (B11).
Address: 0x0C, Reset: 0x00, Name: FIFO_ENTRIES_L
Address: 0x12, Reset: 0x00, Name: ZDATA_L
Address: 0x0D, Reset: 0x00, Name: FIFO_ENTRIES_H
Address: 0x13, Reset: 0x00, Name: ZDATA_H
X-AXIS DATA REGISTERS
TEMPERATURE DATA REGISTERS
These two registers contain the sign extended (SX) x-axis
acceleration data. XDATA_L contains the eight least significant
bits (LSBs), and XDATA_H contains the four most significant
bits (MSBs) of the 12-bit value.
These two registers contain the sign extended (SX) temperature sensor output data. TEMP_L contains the eight LSBs, and
TEMP_H contains the four MSBs of the 12-bit value. The value is
sign extended; therefore, Bits[B15:B12] of TEMP_H are all 0s or
all 1s, based on the value of Bit B11.
The sign extension bits (B[15:12], denoted as SX in the
XDATA_H bit map that follows) have the same value as the
MSB (B11).
The sign extension bits (B[15:12], denoted as SX in the TEMP_H
bit map that follows) have the same value as the MSB (B11).
Address: 0x0E, Reset: 0x00, Name: XDATA_L
Address: 0x14, Reset: 0x00, Name: TEMP_L
Address: 0x0F, Reset: 0x00, Name: XDATA_H
Address: 0x15, Reset: 0x00, Name: TEMP_H
Y-AXIS DATA REGISTERS
These two registers contain the sign extended (SX) y-axis
acceleration data. YDATA_L contains the eight LSBs and
YDATA_H contains the four MSBs of the 12-bit value.
The sign extension bits (B[15:12], denoted as SX in the
YDATA_H bit map that follows) have the same value as the
MSB (B11).
Address: 0x10, Reset: 0x00, Name: YDATA_L
SOFT RESET REGISTER
Address: 0x1F, Reset: 0x00, Name: SOFT_RESET
Writing Code 0x52 (representing the letter, R, in ASCII or
unicode) to this register immediately resets the ADXL362. All
register settings are cleared, and the sensor is placed in standby.
Interrupt pins are configured to a high output impedance mode
and held to a valid state by bus keepers.
This is a write-only register. If read, data in it is always 0x00.
Address: 0x11, Reset: 0x00, Name: YDATA_H
Rev. A | Page 26 of 44
Data Sheet
ADXL362
ACTIVITY THRESHOLD REGISTERS
To detect activity, the ADXL362 compares the absolute value of
the 12-bit (signed) acceleration data with the 11-bit (unsigned)
THRESH_ACT value. See the Motion Detection section for
more information on activity detection.
The term, THRESH_ACT, refers to an 11-bit unsigned value comprising the THRESH_ACT_L register, which holds its eight LSBs;
and the THRESH_ACT_H register, which holds its three MSBs.
THRESH_ACT is set in codes; the value in g depends on the
measurement range setting that is selected.
THRESH_ACT [g] = THRESH_ACT [codes]/Sensitivity
[codes per g]
Address: 0x20, Reset: 0x00, Name: THRESH_ACT_L
When the accelerometer is in wake-up mode, the TIME_ACT
value is ignored and activity is detected based on a single
acceleration sample.
INACTIVITY THRESHOLD REGISTERS
To detect inactivity, the absolute value of the 12-bit acceleration
data is compared with the 11-bit (unsigned) THRESH_INACT
value. See the Motion Detection section for more information.
The term, THRESH_INACT, refers to an 11-bit unsigned value
comprised of the THRESH_INACT_L registers, which holds its
eight LSBs and the THRESH_INACT_H register, which holds
its three MSBs.
This 11-bit unsigned value sets the threshold for inactivity
detection. This value is set in codes; the value (in g) depends on
the measurement range setting selected:
Address: 0x21, Reset: 0x00, Name: THRESH_ACT_H
THRESH_INACT [g] =
THRESH_INACT [codes]/Sensitivity [codes per g]
Address: 0x23, Reset: 0x00, Name: THRESH_INACT_L
ACTIVITY TIME REGISTER
Address: 0x22, Reset: 0x00, Name: TIME_ACT
The activity timer implements a robust activity detection that
minimizes false positive motion triggers. When the timer is
used, only sustained motion can trigger activity detection. Refer
to the Fewer False Positives section for additional information.
The value in this register sets the number of consecutive
samples that must have at least one axis greater than the activity
threshold (set by THRESH_ACT) for an activity event to be
detected.
The time (in seconds) is given by the following equation:
Time = TIME_ACT/ODR
Address: 0x24, Reset: 0x00, Name: THRESH_INACT_H
INACTIVITY TIME REGISTERS
The 16-bit value in these registers sets the number of consecutive samples that must have all axes lower than the inactivity
threshold (set by THRESH_INACT) for an inactivity event to
be detected.
The TIME_INACT_L register holds the eight LSBs and the
TIME_INACT_H register holds the eight MSBs of the 16-bit
TIME_INACT value.
where:
TIME_ACT is the value set in this register.
ODR is the output data rate set in the FILTER_CTL register
(Address 0x2C).
The time in seconds can be calculated as
Setting the activity time to 0x00 has the same result as setting
this time to 0x01: Activity is detected when a single acceleration
sample has at least one axis greater than the activity threshold
(THRESH_ACT).
Time = TIME_INACT/ODR
where:
TIME_INACT is the 16-bit value set by the TIME_INACT_L register (eight LSBs) and the TIME_INACT_H register (eight MSBs).
ODR is the output data rate set in the FILTER_CTL register
(Address 0x2C).
Rev. A | Page 27 of 44
ADXL362
Data Sheet
The 16-bit value allows for long inactivity detection times. The
maximum value is 0xFFFF or 65,535 samples. At the lowest output
data rate, 12.5 Hz, this equates to almost 90 minutes. In this configuration, the accelerometer must be stationary for 90 minutes
before putting its system to sleep.
Setting the activity time to 0x00 has the same result as setting
this time to 0x01: Activity is detected when a single acceleration
sample has at least one axis greater than the activity threshold
(THRESH_INACT).
Address: 0x25, Reset: 0x00, Name: TIME_INACT_L
Address: 0x26, Reset: 0x00, Name: TIME_INACT_H
Rev. A | Page 28 of 44
Data Sheet
ADXL362
ACTIVITY/INACTIVITY CONTROL REGISTER
Address: 0x27, Reset: 0x00, Name: ACT_INACT_CTL
Table 13. Bit Descriptions for ACT_INACT_CTL
Bits
[7:6]
[5:4]
Bit Name
UNUSED
LINK/LOOP
Settings
0X
01
11
3
INACT_REF
2
INACT_EN
1
ACT_REF
0
ACT_EN
Description
Unused Bits.
Default Mode.
Activity and inactivity detection are both enabled, and their interrupts (if
mapped) must be acknowledged by the host processor by reading the
STATUS register. Autosleep is disabled in this mode. Use this mode for free
fall detection applications.
Linked Mode.
Activity and inactivity detection are linked sequentially such that only one
is enabled at a time. Their interrupts (if mapped) must be acknowledged
by the host processor by reading the STATUS register.
Loop Mode.
Activity and inactivity detection are linked sequentially such that only one
is enabled at a time, and their interrupts are internally acknowledged (do
not need to be serviced by the host processor).
To use either linked or looped mode, both ACT_EN (Bit 0) and INACT_EN
(Bit 2) must be set to 1; otherwise, the default mode is used. For additional
information, refer to the Linking Activity and Inactivity Detection section.
Referenced/Absolute Inactivity Select.
1 = inactivity detection function operates in referenced mode.
0= inactivity detection function operates in absolute mode.
Inactivity Enable.
1 = enables the inactivity (underthreshold) functionality.
Referenced/Absolute Activity Select.
1 = activity detection function operates in referenced mode.
0 = activity detection function operates in absolute mode.
Activity Enable.
1 = enables the activity (overthreshold) functionality.
Rev. A | Page 29 of 44
Reset
0x0
0x0
Access
RW
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
ADXL362
Data Sheet
FIFO CONTROL REGISTER
Address: 0x28, Reset: 0x00, Name: FIFO_CONTROL
Table 14. Bit Descriptions for FIFO_CONTROL
Bits
[7:4]
3
Bit Name
UNUSED
AH
2
FIFO_TEMP
[1:0]
FIFO_MODE
Settings
00
01
10
11
Description
Unused Bits.
Above Half.
This bit is the MSB of the FIFO_SAMPLES register, allowing FIFO samples a
range of 0 to 511.
Store Temperature Data to FIFO. 1 = temperature data is stored in the FIFO
together with x-, y-, and z-axis acceleration data.
Enable FIFO and Mode Selection.
FIFO is disabled.
Oldest saved mode.
Stream mode.
Triggered mode.
Rev. A | Page 30 of 44
Reset
0x0
0x0
Access
RW
RW
0x0
RW
0x0
RW
Data Sheet
ADXL362
FIFO SAMPLES REGISTER
INT1/INT2 FUNCTION MAP REGISTERS
Address: 0x29, Reset: 0x80, Name: FIFO_SAMPLES
The INT1 and INT2 registers configure the INT1/INT2
interrupt pins, respectively. Bits[B6:B0] select which function(s)
generate an interrupt on the pin. If its corresponding bit is set to
1, the function generates an interrupt on the INT pin. Bit B7
configures whether the pin operates in active high (B7 low) or
active low (B7 high) mode.
The value in this register specifies the number of samples to
store in the FIFO. The AH bit in the FIFO_CONTROL register
(Address 0x28) is used as the MSB of this value. The full range
of FIFO samples is 0 to 511.
The default value of this register is 0x80 to avoid triggering the
FIFO watermark interrupt (see the FIFO Watermark section for
more information).
The following bit map is duplicated from the FIFO Control
Register section to indicate the AH bit.
Any number of functions can be selected simultaneously for
each pin. If multiple functions are selected, their conditions are
OR'ed together to determine the INT pin state. The status of
each individual function can be determined by reading the
STATUS register. If no interrupts are mapped to an INT pin, the
pin remains in a high impedance state, held to a valid logic state
by a bus keeper.
Address: 0x2A, Reset: 0x00, Name: INTMAP1
Table 15. Bit Descriptions for INTMAP1
Bits
7
6
5
4
3
2
1
0
Bit Name
INT_LOW
AWAKE
INACT
ACT
FIFO_OVERRUN
FIFO_WATERMARK
FIFO_READY
DATA_READY
Settings
Description
1 = INT1 pin is active low.
1 = maps the awake status to INT1 pin.
1 = maps the inactivity status to INT1 pin.
1 = maps the activity status to INT1 pin.
1 = maps the FIFO overrun status to INT1 pin.
1 = maps the FIFO watermark status to INT1 pin.
1 = maps the FIFO ready status to INT1 pin.
1 = maps the data ready status to INT1 pin.
Rev. A | Page 31 of 44
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
ADXL362
Data Sheet
Address: 0x2B, Reset: 0x00, Name: INTMAP2
Table 16. Bit Descriptions for INTMAP2
Bits
7
6
5
4
3
2
1
0
Bit Name
INT_LOW
AWAKE
INACT
ACT
FIFO_OVERRUN
FIFO_WATERMARK
FIFO_READY
DATA_READY
Settings
Description
1 = INT2 pin is active low.
1 = maps the awake status to INT2 pin.
1 = maps the inactivity status to INT2 pin.
1 = maps the activity status to INT2 pin.
1 = maps the FIFO overrun status to INT2 pin.
1 = maps the FIFO watermark status to INT2 pin.
1 = maps the FIFO ready status to INT2 pin.
1 = maps the data ready status to INT2 pin.
Rev. A | Page 32 of 44
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
Access
RW
RW
RW
RW
RW
RW
RW
RW
Data Sheet
ADXL362
FILTER CONTROL REGISTER
Address: 0x2C, Reset: 0x13, Name: FILTER_CTL
Table 17. Bit Descriptions for FILTER_CTL
Bits
[7:6]
Bit Name
RANGE
Settings
00
01
1X
5
4
RES
HALF_BW
3
EXT_SAMPLE
[2:0]
ODR
000
001
010
011
100
101…111
Description
Measurement Range Selection.
±2 g (reset default)
±4 g
±8 g
Reserved.
Halved Bandwidth. Additional information is provided in the Antialiasing section.
1 = the bandwidth of the antialiasing filters is set to ¼ the output data rate (ODR) for
more conservative filtering.
0 = the bandwidth of the filters is set to ½ the ODR for a wider bandwidth.
External Sampling Trigger. 1 = the INT2 pin is used for external conversion timing
control. Refer to the Using Synchronized Data Sampling section for more
information.
Output Data Rate. Selects ODR and configures internal filters to a bandwidth of ½ or
¼ the selected ODR, depending on the HALF_BW bit setting.
12.5 Hz
25 Hz
50 Hz
100 Hz (reset default)
200 Hz
400 Hz
Rev. A | Page 33 of 44
Reset
0x0
Access
RW
0x0
0x1
RW
0x0
RW
0x0
RW
ADXL362
Data Sheet
POWER CONTROL REGISTER
Address: 0x2D, Reset: 0x00, Name: POWER_CTL
Table 18. Bit Descriptions for POWER_CTL
Bits
7
6
Bit Name
Reserved
EXT_CLK
[5:4]
LOW_NOISE
Settings
00
01
10
11
3
WAKEUP
2
AUTOSLEEP
[1:0]
MEASURE
00
01
10
11
Description
Reserved.
External Clock. See the Using an External Clock section for additional details.
1 = the accelerometer runs off the external clock provided on the INT1 pin.
Selects Power vs. Noise Tradeoff:
Normal operation (reset default).
Low noise mode.
Ultralow noise mode.
Reserved.
Wake-Up Mode. See the Operating Modes section for a detailed
description of wake-up mode.
1 = the part operates in wake-up mode.
Autosleep. Activity and inactivity detection must be in linked mode or
loop mode (LINK/LOOP bits in ACT_INACT_CTL register) to enable
autosleep; otherwise, the bit is ignored. See the Motion Detection section
for details.
1 = autosleep is enabled, and the device enters wake-up mode
automatically upon detection of inactivity.
Selects Measurement Mode or Standby.
Standby.
Reserved.
Measurement mode.
Reserved.
Rev. A | Page 34 of 44
Reset
0x0
0x0
Access
RW
RW
0x0
RW
0x0
RW
0x0
RW
0x0
RW
Data Sheet
ADXL362
SELF TEST REGISTER
Address: 0x2E, Reset: 0x00, Name: SELF_TEST
Refer to the Self Test section for information on the operation of the self test feature, and see the Using Self Test section for guidelines on
how to use this functionality.
Table 19. Bit Descriptions for SELF_TEST
Bits
[7:1]
0
Bit Name
UNUSED
ST
Settings
Description
Self Test.
1 = a self test force is applied to the x-, y-, and z-axes.
Rev. A | Page 35 of 44
Reset
0x0
0x0
Access
RW
RW
ADXL362
Data Sheet
APPLICATIONS INFORMATION
APPLICATION EXAMPLES
Startup Routine
This section includes a few application circuits, highlighting
useful features of the ADXL362.
This routine assumes a ±2 g measurement range and operation
in wake-up mode.
Device Configuration
1.
This section outlines the procedure for configuring the device
and acquiring data. In general, the procedure follows the
sequence of the register map, starting with Register 0x20,
THRESH_ACT_L.
3.
4.
5.
6.
4.
5.
6.
Using External Timing Triggers
Figure 44 shows an application diagram for using the INT1 pin
as the input for an external clock. In this mode, the external
clock determines all accelerometer timing, including the output
data rate and bandwidth.
Settings for each of the registers vary based on application
requirements. For more information, see the Register Details
section.
To enable this feature, at the end of the desired start-up routine,
set Bit 6 in the POWER_CTL register; for example, write 0x42
to this register to enable the use of an external clock and place
the accelerometer into measurement mode.
VDD I/O
ADXL362
MOSI
INTERRUPT
CONTROL
MISO
INT1
SCLK
INT2
AWAKE
ADXL362
MOSI
GND
EXTERNAL
CLOCK
INT1
INTERRUPT
CONTROL
INT2
MISO
SPI
INTERFACE
CS
ADP195
VS
VIN
Figure 44. INT1 Pin as the Input for the External Clock
VDD I/O
CS
CIO
VOUT
VS
GND
VDD I/O
ADXL362
LEVEL SHIFT
AND SLEW
RATE CONTROL
INTERRUPT
CONTROL
LOAD
10776-041
EN
CS
GND
VS
REVERSE
POLARITY
PROTECTION
SPI
INTERFACE
SCLK
Figure 45 is an application diagram for using the INT2 pin as a
trigger for synchronized sampling. Acceleration samples are
produced every time this trigger is activated. To enable this
feature, near the end of the desired start-up routine, set Bit 3 in
the FILTER_CTL register; for example, write 0x4B to this register
to enable the trigger and configure the accelerometer for ±8 g
measurement range and 100 Hz ODR.
CIO
VS
VDD I/O
VS
VDD I/O
CS
CIO
CS
The features of the ADXL362 make it ideal for use as an
autonomous motion switch. The example outlined here
implements a switch that, once configured, operates without the
intervention of a host processor to intelligently manage system
power. In this example, the awake signal, mapped to the INT2
pin, drives a high-side power switch, such as the ADP195, to
control power to the downstream circuitry.
VS
VDD I/O
VS
Autonomous Motion Switch
10776-042
2.
Set activity and inactivity thresholds and timers.
a. Write to Register 0x20 to Register 0x26.
b. To minimize false positive motion triggers, set the
TIME_ACT register greater than 1.
Configure activity and inactivity functions.
a. Write to Register 0x27.
Configure FIFO.
a. Write to Register 0x28 and Register 0x29.
Map interrupts.
a. Write to Register 0x2A and Register 0x2B.
Configure general device settings.
a. Write to Register 0x2C.
Turn measurement on.
a. Write to Register 0x2D.
3.
Figure 43. Awake Signal to Control Power to Downstream Circuitry
SAMPLING
TRIGGER
MOSI
MISO
INT1
SCLK
INT2
GND
SPI
INTERFACE
CS
Figure 45. Using the INT2 Pin to Trigger Synchronized Sampling
Rev. A | Page 36 of 44
10776-043
1.
2.
Write 250 decimal (0xFA) to Register 0x20, and write 0 to
Register 0x21: sets activity threshold to 250 mg.
Write 150 decimal (0x96) to Register 0x23, and write 0 to
Register 0x24: sets inactivity threshold to 150 mg.
Write 30 decimal (0x1E) to Register 0x25: sets inactivity
timer to 30 samples or about 5 seconds.
Write 0x3F to Register 0x27: configures motion detection
in loop mode and enables referenced activity and inactivity
detection.
Write 0x40 to Register 0x2B: map the AWAKE bit to INT2.
The INT2 pin is tied to the gate of the switch.
Write 0x0A to Register 0x2D: begins the measurement in
wake-up mode.
Data Sheet
ADXL362
Example: Implementing Free Fall Detection
VS
Many digital output accelerometers include a built-in free fall
detection feature. In the ADXL362, implement this function
using the inactivity interrupt.
To use inactivity to implement free fall detection, set the value
in THRESH_INACT to the desired free fall threshold. Values
between 300 mg and 600 mg are recommended; the register
setting for these values varies based on the g range setting of the
device, as follows:
THRESH_INACT =
Threshold Value [g] × Scale Factor [LSB per g]
TIME_INACT = Time [sec] × Data Rate [Hz]
When a free fall condition is detected, the inactivity status is set
to 1 and, if the function is mapped to an interrupt pin, an
inactivity interrupt triggers on that pin.
Startup Routine
The following startup routine configures the ADXL362 for a
typical free fall application. This routine assumes a ±8 g
measurement range and 100 Hz output data rate. Thresholds
and timing values can be modified to suit particular application
needs.
4.
5.
6.
VS
Write 0x58 (150 codes) to Register 0x23: sets free fall
threshold to 600 mg.
Write 0x03 to Register 0x25: sets free fall time to 30 ms.
Write 0x0C to Register 0x27: enables absolute inactivity
detection.
Write 0x20 to Register 0x2A or Register 0x2B to map the
inactivity interrupt to INT1 or INT2, respectively.
Write 0x83 to Register 0x2C: configures the accelerometer
to ±8 g range, 100 Hz ODR (output data rate).
Write 0x02 to Register 0x2D to begin measurement.
MOSI
INTERRUPT
CONTROL
SPI
INTERFACE
SCLK
INT2
CS
GND
Figure 46. Recommended Bypass Capacitors
A 0.1 µF ceramic capacitor (CS) at VS and a 0.1 µF ceramic capacitor
(CIO) at VDD I/O placed as close as possible to the ADXL362. Supply
pins are recommended to adequately decouple the accelerometer
from noise on the power supply. It is also recommended that VS
and VDD I/O be separate supplies to minimize digital clocking
noise on the VS supply. If this is not possible, additional filtering
of the supplies may be necessary.
Ensure that the connection from the ADXL362 ground to the
power supply ground has low impedance because noise
transmitted through ground has an effect similar to noise
transmitted through VS.
Power Supply Requirements
The ADXL362 is designed to operate using supply voltage rails
ranging from 1.8 V to 3.3 V. The operating voltage range (VS),
specified in Table 1, ranges from 1.6 V to 3.5 V to account for
inaccuracies and transients of up to ±10% on the supply voltage.
The ADXL362 does not require any particular startup transient
characteristics, except that it must always be started up from 0 V.
When the device is in operation, any time power is removed
from the ADXL362, or falls below the operating voltage range,
the supplies (VS, VDD I/O, and any bypass capacitors) must be
discharged completely before power is reapplied. To enable
supply discharge, it is recommended to power the device from
a microcontroller GPIO, connect a shutdown discharge switch
to the supply (Figure 47), or use a voltage regulator with a
shutdown discharge feature, such as the ADP160.
VDD I/O
VS
VIN
CIO
CS
VDD I/O
VS
R1
ADXL362
MOSI
MISO
INT1
SHUTDOWN
Power Supply Decoupling
Figure 46 shows the recommended bypass capacitors for use
with the ADXL362.
MISO
INT1
Implementation of a complete fall detection application is
described in the AN-1023 Application Note, Fall Detection
Application by Using 3-Axis Accelerometer ADXL345.
POWER
VDD I/O
ADXL362
SCLK
INT2
GND
SPI
INTERFACE
CS
NOTES
1. THE ADXL362 SUPPLIES MUST BE DISCHARGED FULLY EACH TIME
THE VOLTAGE ON THEM DROPS BELOW THE SPECIFIED OPERATING
RANGE. A SHUTDOWN SWITCH IS ONE WAY TO DISCHARGE THE SUPPLIES.
Figure 47. Using a Switch to Discharge the ADXL362 Supplies
Rev. A | Page 37 of 44
10776-141
2.
3.
CIO
If additional decoupling is necessary, place a resistor or ferrite bead,
no larger than 100 Ω, in series with VS. Additionally, increasing the
bypass capacitance on VS to a 1 µF tantalum capacitor in parallel
with a 0.1 µF ceramic capacitor may also improve noise.
Set the value in TIME_INACT to implement the minimum
amount of time that the acceleration on all axes must be less
than the free fall threshold to generate a free fall condition.
Values between 100 ms and 350 ms are recommended; the
register setting for this varies based on the output data rate.
1.
CS
10776-040
When an object is in true free fall, acceleration on all axes is 0 g.
Thus, free fall detection is achieved by looking for acceleration
on all axes to fall below a certain threshold (close to 0 g) for a
certain amount of time. The inactivity detection functionality,
when used in absolute mode, does exactly this.
VDD I/O
ADXL362
Data Sheet
FIFO MODES
FIFO Configuration
The FIFO is a 512-sample memory buffer that can be used to
save power, unburden the host processor, and autonomously
record data.
The FIFO is configured via Register 0x28 and Register 0x29.
Settings are described in detail in the FIFO Control Register
section.
The 512 FIFO samples can be allotted as either:
FIFO Interrupts
•
•
The FIFO can generate interrupts to indicate when samples are
available, when a specified number of samples has been collected,
and when the FIFO overflows and samples are lost. See the
Using FIFO Interrupts section for more information.
170 sample sets of concurrent 3-axis data; or
128 sample sets of concurrent 3-axis and temperature data
The FIFO operates in one of the four modes described in this
section.
Retrieving Data from FIFO
FIFO Disabled
FIFO data is read by issuing a FIFO read command, described
in the SPI Commands section. Data is formatted as a 16-bit
value as represented in Table 20.
When the FIFO is disabled, no data is stored in it and any data
already stored in it is cleared.
The FIFO is disabled by setting the FIFO_MODE bits in the
FIFO_CONTROL register (Address 0x28) to Binary Value 0b00.
Oldest Saved Mode
In oldest saved mode, the FIFO accumulates data until it is full
and then stops. Additional data is collected only when space is
made available by reading samples out of the FIFO buffer. (This
mode of operation is sometimes referred to as “First N.”)
The FIFO is placed into oldest saved mode by setting the
FIFO_MODE bits in the FIFO_CONTROL register (Address
0x28) to Binary Value 0b01.
Stream Mode
In stream mode, the FIFO always contains the most recent data.
The oldest sample is discarded when space is needed to make
room for a newer sample. (This mode of operation is sometimes
referred to as “Last N.”)
Stream mode is useful for unburdening a host processor. The
processor can tend to other tasks while data is being collected in
the FIFO. When the FIFO fills to a certain number of samples
(specified by the FIFO_SAMPLES register along with the AH
bit in the FIFO_CONTROL register), it triggers a FIFO
watermark interrupt (if this interrupt is enabled). At this point,
the host processor can read the contents of the entire FIFO and
then return to its other tasks as the FIFO fills again.
The FIFO is placed into stream mode by setting the FIFO_MODE
bits in the FIFO_CONTROL register (Address 0x28) to Binary
Value 0b10.
Triggered Mode
In triggered mode, the FIFO saves samples surrounding an
activity detection event. The operation is similar to a one-time
run trigger on an oscilloscope. The number of samples to be
saved prior to the activity event is specified in FIFO_SAMPLES
(Register 0x29, along with the AH bit in the FIFO_CONTROL
register, Address 0x28).
Place the FIFO into triggered mode by setting the FIFO_MODE
bits in the FIFO_CONTROL register (Address 0x28) to Binary
Value 0b11.
When reading data, the least significant byte (Bits[B7:B0]) is
read first, followed by the most significant byte (Bits[B15:B8]).
Bits[B11:B0] represent the 12-bit, twos complement
acceleration or temperature data. Bits[B13:B12] are sign
extension bits, and Bits[B15:B14] indicate the type of data, as
listed in Table 20.
Table 20. FIFO Buffer Data Format
B15
B14
Data Type:
00: X-Axis
01: Y-Axis
10: Z-Axis
11: Temp
B13
B7
B5
B6
B12
Sign
Extension
B4
Data
B11
MSB
B10
B9
Data
B8
B3
B2
B1
B0
LSB
Because the data format is 16-bit, the data must be read from
the FIFO two bytes at a time. When a multibyte read is
performed, the number of bytes read should always be an even
number. Multibyte reads of FIFO data can be performed with
no limit on the number of bytes read. If additional bytes are
read after the FIFO is empty, the data in the additional bytes are
read as 0x00.
As each sample set is acquired, it is written into the FIFO in the
following order:
•
•
•
•
X-axis
Y-axis
Z-axis
Temperature (optional)
This pattern repeats until the FIFO is full, at which point the
behavior depends on the FIFO mode (see the FIFO section). If
the FIFO has insufficient space for four data entries (or three
entries if temperature is not being stored), then an incomplete
sample set can be stored.
Rev. A | Page 38 of 44
Data Sheet
ADXL362
FIFO data is output on a per datum basis. As each data item is
read, the same amount of space is freed up in the stack. Again,
this can lead to incomplete sample sets being present in the FIFO.
For additional system level FIFO applications, refer to the
AN-1025 Application Note, Utilization of the First In, First Out
(FIFO) Buffer in Analog Devices, Inc. Digital Accelerometers.
INTERRUPTS
active low by setting the INT_LOW bit in the appropriate
INTMAPx register.
The INT pins can be connected to the interrupt input of a host
processor where interrupts are responded to with an interrupt
routine. Because multiple functions can be mapped to the same
pin, the STATUS register can be used to determine which
condition caused the interrupt to trigger.
Several of the built-in functions of the ADXL362 can trigger
interrupts to alert the host processor of certain status conditions.
This section describes the functionality of these interrupts.
Clear interrupts in one of several ways, as follows:
Interrupt Pins
•
Interrupts can be mapped to either (or both) of two designated
output pins, INT1 and INT2, by setting the appropriate bits in
the INTMAP1 and INTMAP2 registers, respectively. All functions
can be used simultaneously. If multiple interrupts are mapped
to one pin, the OR combination of the interrupts determines
the status of the pin.
If no functions are mapped to an interrupt pin, that pin is
automatically configured to a high impedance (high-Z) state.
The pins are also placed in the high-Z state upon a reset.
When a certain status condition is detected, the pin that
condition is mapped to is activated. The configuration of the
pin is active high by default so that when it is activated, the pin
goes high. However, this configuration can be switched to
Table 21. Interrupt Pin Digital Output
Parameter
Digital Output
Low Level Output Voltage (VOL)
High Level Output Voltage (VOH)
Low Level Output Current (IOL)
High Level Output Current (IOH)
1
•
Reading the STATUS register (Address 0x0B) clears
activity and inactivity interrupts.
Reading from the data registers. Address 0x08 to
Address 0x0A or Address 0x0E to Address 0x15 clears
the data ready interrupt.
Reading enough data from the FIFO buffer so that
interrupt conditions are no longer met clears the FIFO
ready, FIFO watermark, and FIFO overrun interrupts.
•
Both interrupt pins are push-pull low impedance pins with an
output impedance of about 500 Ω (typical) and digital output
specifications, as shown in Table 21. Both pins have bus keepers
that hold them to a valid logic state when they are in a high
impedance mode.
To prevent interrupts from being falsely triggered during
configuration, disable interrupts while their settings, such as
thresholds, timings, or other values, are configured.
Test Conditions
Min
IOL = 500 µA
IOH = −300 µA
VOL = VOL, max
VOH = VOH, min
0.8 × VDD I/O
500
Limit 1
Max
0.2 × VDD I/O
Limits based on design, not production tested.
Rev. A | Page 39 of 44
−300
Unit
V
V
µA
µA
ADXL362
Data Sheet
Alternate Functions of Interrupt Pins
Overrun
The INT1 and INT2 pins can be configured for use as input
pins instead of for signaling interrupts. INT1 is used as an
external clock input when the EXT_CLK bit (Bit 6) in the
POWER_CTL register (Address 0x2D) is set. INT2 is used
as the trigger input for synchronized sampling when the
EXT_SAMPLE bit (Bit 3) in the FILTER_CTL register
(Address 0x2C) is set. One or both of these alternate functions
can be used concurrently; however, if an interrupt pin is used
for its alternate function, it cannot simultaneously be used for
its primary function, to signal interrupts.
The FIFO_OVERRUN bit (Bit 3) is set when the FIFO has
overrun or overflowed, such that new data replaces unread data.
This may indicate a full FIFO that has not yet been emptied or a
clocking error caused by a slow SPI transaction. If the FIFO is
configured to oldest saved mode, an overrun event indicates
that there is insufficient space available for a new sample.
External clocking and data synchronization are described in the
Applications Information section.
Activity and Inactivity Interrupts
The ACT bit (Bit 4) and INACT bit (Bit 5) in the STATUS
register are set when activity and inactivity are detected,
respectively. Detection procedures and criteria are described in
the Motion Detection section.
Data Ready Interrupt
The DATA_READY bit (Bit 0) is set when new valid data is
available, and it is cleared when no new data is available.
The DATA_READY bit is not set while any of the data registers,
Address 0x08 to Address 0x0A and Address 0x0E to Address 0x15,
are being read. If DATA_READY = 0 prior to a register read
and new data becomes available during the register read,
DATA_READY remains at 0 until the read is complete and,
only then, is set to 1.
If DATA_READY = 1 prior to a register read, it is cleared at the
start of the register read.
If DATA_READY = 1 prior to a register read and new data
becomes available during the register read, DATA_READY is
cleared to 0 at the start of the register read and remains at 0
throughout the read. When the read is complete, DATA_READY is
set to 1.
Using FIFO Interrupts
FIFO Watermark
The FIFO_WATERMARK bit (Bit 2) is set when the number of
samples stored in the FIFO is equal to or exceeds the number specified in the FIFO_SAMPLES register (Address 0x29) together with
the AH bit in the FIFO_CONTROL register (Bit 3, Address 0x28).
The FIFO_WATERMARK bit is cleared automatically when
enough samples are read from the FIFO, such that the number
of samples remaining is lower than that specified.
The FIFO_OVERRUN bit is cleared automatically when the
contents of the FIFO are read. Likewise, when the FIFO is
disabled, the FIFO_OVERRUN bit is cleared.
USING SYNCHRONIZED DATA SAMPLING
For applications that require a precisely timed acceleration
measurement, the ADXL362 features an option to synchronize
acceleration sampling to an external trigger. The EXT_SAMPLE
bit (Bit 3) in the FILTER_CTL Register (Address 0x2C) enables
this feature. When the EXT_SAMPLE bit is set to 1, the INT2
pin is automatically reconfigured for use as the sync trigger input.
When external triggering is enabled, it is up to the system
designer to ensure that the sampling frequency meets system
requirements. Sampling too infrequently causes aliasing. Noise
can be lowered by oversampling; however, sampling at too high
a frequency may not allow enough time for the accelerometer to
process the acceleration data and convert it to valid digital output.
When Nyquist criteria are met, signal integrity is maintained.
An internal antialiasing filter is available in the ADXL362 and
can assist the system designer in maintaining signal integrity. To
prevent aliasing, set the filter bandwidth to a frequency no
greater than ½ the sampling rate. For example, when sampling
at 100 Hz, set the filter pole to no higher than 50 Hz. The filter
pole is set via the ODR bits in the FILTER_CTL register
(Address 0x2C). The filter bandwidth is set to ½ the ODR and is
set via these bits. Even though the ODR is ignored (as the data
rate is set by the external trigger), the filter is still applied at the
specified bandwidth.
Because of internal timing requirements, the trigger signal
applied to pin INT2 must meet the following criteria:
•
•
•
•
•
If the number of FIFO samples is set to 0, the FIFO watermark
interrupt is set. To avoid unexpectedly triggering this interrupt,
the default value of the FIFO_SAMPLES register is 0x80.
FIFO Ready
The FIFO_READY bit (Bit 1) is set when there is at least one
valid sample available in the FIFO output buffer. This bit is
cleared when no valid data is available in the FIFO.
Rev. A | Page 40 of 44
The trigger signal is active high.
The pulse width of the trigger signal must be at least 25 µs.
The trigger must be deasserted for at least 25 µs before it is
reasserted.
The maximum sampling frequency that is supported is
625 Hz (typical).
The minimum sampling frequency is set only by system
requirements. Samples need not be polled at any minimum
rate; however, if samples are polled at a rate lower than the
bandwidth set by the antialiasing filter, then aliasing may
occur.
Data Sheet
ADXL362
USING AN EXTERNAL CLOCK
OPERATION AT VOLTAGES OTHER THAN 2.0 V
The ADXL362 has a built-in clock that, by default, is used for
clocked internal operations. If desired, an external clock can be
provided and used.
The ADXL362 is tested and specified at a supply voltage of VS =
2.0 V; however, it can be powered with a VS as high as 3.3 V
nominal (3.5 V maximum) or as low as 1.8 V nominal (1.6 V
minimum). Some performance parameters change as the supply
voltage changes, including the supply current (see Figure 30),
noise (see Table 7 and Table 8), offset, sensitivity, and self test
output change (see Table 22).
1.
2.
3.
4.
5.
6.
Read acceleration data for the x-, y-, and z-axes.
Assert self test by setting the ST bit in the SELF_TEST
register, Address 0x2E.
Wait 1/ODR for the output to settle to its new value.
Read acceleration data for the x-, y-, and z-axes.
Compare to the values from Step 1, and convert the
difference from LSB to mg by multiplying by the sensitivity.
If the observed difference falls within the self test output
change specification listed in Table 1, then the device
passes self test and is deemed operational.
Deassert self test by clearing the ST bit in the SELF_TEST
register, Address 0x2E.
The self test output change specification is given for VS = 2.0 V.
Because the electrostatic force is proportional to VS2 and the
sensitivity of the device is ratiometric to VS, the output change
varies with VS. The scale factors shown in Table 22 can be used
to adjust the expected self test output limits for different supply
voltages, VS.
Note that at higher voltages, self test deltas may exceed 1 g. If
the measurement is performed with one axis experiencing 1 g
due to gravity, and if the accelerometer is configured for a ±2 g
measurement range, the axis that is aligned with the field of
gravity may reach 2 g and its output clips (saturates to its fullscale value). To alleviate this, self test can be measured with the
y-axis aligned with gravity (where the y-axis self test output
change is negative), or with the accelerometer configured for a
±4 g or ±8 g measurement range.
200
X-AXIS
Y-AXIS
Z-AXIS
150
50
0
–50
–100
1.5
2.0
2.5
3.0
3.5
VS (V)
Figure 48. 0 g Offset vs. Supply Voltage
MECHANICAL CONSIDERATIONS FOR MOUNTING
Mount the ADXL362 on the printed circuit board (PCB) in a
location close to a hard mounting point of the PCB to the case.
Mounting the ADXL362 at an unsupported PCB location, as
shown in Figure 49, can result in large, apparent measurement
errors due to undampened PCB vibration. Locating the accelerometer near a hard mounting point ensures that any PCB
vibration at the accelerometer is above the mechanical sensor
resonant frequency of the accelerometer and, therefore, effectively invisible to the accelerometer. Multiple mounting points,
close to the sensor, and/or a thicker PCB also help to reduce the
effect of system resonance on the performance of the sensor.
Table 22. Self Test Output Scale Factors for Different Supply
Voltages, VS
Supply Voltage, VS (V)
1.6
2.0
2.5
3.0
3.5
100
10776-144
The self test function, described in the Self Test section, is
enabled via the ST bit in the SELF_TEST register, Address 0x2E.
The recommended procedure for using the self test functionality is
as follows:
Self Test Output Scale Factor
0.62
1.0
1.6
2.4
3.4
Rev. A | Page 41 of 44
ACCELEROMETERS
PCB
MOUNTING POINTS
Figure 49. Incorrectly Placed Accelerometers
10776-044
USING SELF TEST
Figure 48 shows the potential effect on 0 g offset at varying
supply voltage. Data for this figure was calibrated to show 0 mg
offset at 2.0 V.
ZERO g OFFSET (mg)
To use an external clock, the EXT_CLK bit (Bit 6) in the
POWER_CTL register (Address 0x2D) must be set. Setting
this bit reconfigures the INT1 pin to an input pin on which the
clock can be provided. The external clock must operate at or
below 51.2 kHz. Further information is provided in the External
Clock section.
ADXL362
Data Sheet
AXES OF ACCELERATION SENSITIVITY
AZ
AX
10776-045
AY
Figure 50. Axes of Acceleration Sensitivity (Corresponding Output Increases When Accelerated Along the Sensitive Axis)
XOUT = –1g
YOUT = 0g
ZOUT = 0g
TOP
XOUT = 0g
YOUT = 1g
ZOUT = 0g
TOP
TOP
XOUT = 0g
YOUT = –1g
ZOUT = 0g
GRAVITY
TOP
XOUT = 0g
YOUT = 0g
ZOUT = 1g
XOUT = 0g
YOUT = 0g
ZOUT = –1g
Figure 51. Output Response vs. Orientation to Gravity
LAYOUT AND DESIGN RECOMMENDATIONS
Figure 52 shows the recommended PCB land pattern.
0.9250
0.3000
3.3500
0.5000
3.3500
Figure 52. Recommended PCB Land Pattern
(Dimensions shown in millimeters)
Rev. A | Page 42 of 44
10776-047
0.8000
10776-046
XOUT = 1g
YOUT = 0g
ZOUT = 0g
Data Sheet
ADXL362
OUTLINE DIMENSIONS
3.30
3.25
3.15
0.10
REF
0.50
BSC
3.10
3.00
2.90
0.375
REF
TOP VIEW
1.14
MAX
END VIEW
SEATING
PLANE
0.3375
REF
1.00
REF
13
9
0.35 × 0.25
REF
14
16
8
6
1
5
0.475 × 0.25
REF
BOTTOM VIEW
0.85
REF
0.25
0.21
0.17
10-23-2012-A
PIN 1
CORNER
Figure 53. 16-Terminal Land Grid Array [LGA]
(CC-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADXL362BCCZ-RL
ADXL362BCCZ-RL7
ADXL362BCCZ-R2
EVAL-ADXL362Z
EVAL-ADXL362Z-DB
EVAL-ADXL362Z-MLP
EVAL-ADXL362Z-S
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Terminal Land Grid Array [LGA]
16-Terminal Land Grid Array [LGA]
16-Terminal Land Grid Array [LGA]
Breakout Board
Datalogger and Development Board
Low Power Real-Time Evaluation System
Satellite Board for Evaluation System
Z = RoHS Compliant Part.
Rev. A | Page 43 of 44
Package Option
CC-16-4
CC-16-4
CC-16-4
Quantity
5,000
1,500
250
ADXL362
Data Sheet
NOTES
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10776-0-9/12(A)
Rev. A | Page 44 of 44
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