LXT901/907 Datasheet Universal 10BASE-T and AUI Transceivers

LXT901/907 Datasheet Universal 10BASE-T and AUI Transceivers
LXT901/907
Universal 10BASE-T and AUI Transceivers
Datasheet
The LXT901 and LXT907 Universal 10BASE-T and AUI Transceivers are designed for IEEE
802.3 physical layer applications. They provide all the active circuitry to interface most standard
802.3 controllers to either the 10BASE-T media or Attachment Unit Interface (AUI). In
addition to standard 10 Mbps Ethernet, they also support full-duplex operation at 20 Mbps.
The LXT901 and LXT907 are identical except for the function of one pin. The LXT901 offers
selectable termination impedance to allow the use of either shielded or unshielded twisted-pair
cable. The LXT907 offers a signal quality error (SQE) disable function.
Common LXT901 and LXT907 functions include Manchester encoding/decoding, receiver
squelch and transmit pulse shaping, jabber, link testing and reversed polarity detection/
correction. Integrated filters simplify the design work required for FCC-compliant EMI
performance.
Applications
■
10BASE-T hub and switching products
■
Computer/Workstation 10BASE-T LAN
adapters
Product Features
Functional Features
■
■
■
■
Integrated Manchester Encoder/Decoder
10BASE-T Transceiver
AUI Transceiver
Full-Duplex Capable (20 Mbps)
Diagnostic Features
■
■
■
Four LED Drivers
AUI/RJ45 Loopback
Remote Signaling of Link Down and
Jabber conditions
Convenience Features
■
■
■
■
■
■
■
Automatic/Manual AUI/RJ45 Selection
Automatic Polarity Correction
SQE Disable function (LXT907 only)
Programmable Impedance Driver (LXT901
only)
Power Down Mode and four loopback
modes
LXT901 available in 64-pin LQFP and 44pin PLCC
LXT907 available in 44-pin PLCC
As of January 15, 2001, this document replaces the Level One document
LXT901/907 — Universal 10BASE-T and AUI Transceivers.
Order Number: 249097-001
January 2001
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT901/907 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 2001
*Third-party brands and names are the property of their respective owners.
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
Contents
1.0
Pin Assignments and Signal Descriptions ...................................................... 8
2.0
Functional Description...........................................................................................12
2.1
2.2
2.3
2.4
2.5
3.0
Application Information .........................................................................................20
3.1
3.2
3.3
3.4
4.0
4.2
4.3
4.4
Datasheet
Twisted-Pair Impedance Matching ......................................................................20
Crystal Information ..............................................................................................20
Magnetics Information .........................................................................................21
Typical Applications.............................................................................................21
3.4.1 Auto Port Select with External Loopback Control...................................21
3.4.2 Full Duplex Support................................................................................24
3.4.3 Dual Network Support - 10Base-T and Token Ring ...............................25
3.4.4 Manual Port Select with Link Test Function ...........................................26
3.4.5 Three Media Application.........................................................................28
3.4.6 AUI Encoder/Decoder ONLY..................................................................29
3.4.7 150 Ω Shielded Twisted-Pair Only (LXT901 only)..................................30
Test Specifications ..................................................................................................31
4.1
5.0
Controller Compatibility Modes ...........................................................................13
Transmit Function................................................................................................13
2.2.1 Jabber Control Function .........................................................................14
2.2.2 SQE Function .........................................................................................14
2.2.2.1 SQE Disable Function (LXT907 only) ......................................15
Receive Function.................................................................................................15
2.3.1 Polarity Reverse Function ......................................................................16
2.3.2 Collision Detection Function...................................................................16
Loopback Functions ............................................................................................17
2.4.1 Standard TP Loopback...........................................................................17
2.4.2 External Loopback..................................................................................17
2.4.3 Forced TP Loopback ..............................................................................17
2.4.4 AUI Loopback.........................................................................................17
Link Integrity Test Function .................................................................................17
2.5.1 Remote Signaling ...................................................................................19
Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low)
Figure 17 through Figure 22................................................................................35
Timing Diagrams for Mode 2 (MD1=Low, MD0=High)
Figure 23 through Figure 28................................................................................37
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)
Figure 29 through Figure 36................................................................................39
Timing Diagrams for Mode 4 (MD1 = High, MD0 = High)
Figure 37 through Figure 42................................................................................42
Mechanical Specifications....................................................................................44
3
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
4
LXT901/907 Block Diagram .................................................................................. 7
LXT901/907 Pin Assignments............................................................................... 8
LXT901/907 TPO Output Waveform .................................................................. 13
Jabber Control Function ..................................................................................... 14
SQE Function ..................................................................................................... 15
Collision Detection Function ............................................................................... 16
Link Integrity Test Function ................................................................................ 18
Remote Signaling Link Integrity Pulse Timing .................................................... 19
LAN Adapter Board - Auto Port Select with External LPBK Control .................. 23
Full-Duplex Operation ........................................................................................ 24
380C26 Interface for Dual Network Support of 10BASE-T and Token Ring ...... 25
LAN Adapter Board - Manual Port Select with Link Test Function ..................... 26
Manual Port Select with Seeq 8005 Controller .................................................. 27
Three Media Application .................................................................................... 28
AUI Encoder/Decoder Only Application ............................................................. 29
150 Ω Shielded Twisted-Pair Only Application (LXT901) ................................... 30
Mode 1 RCLK/Start-of-Frame Timing ................................................................ 35
Mode 1 RCLK/End-of-Frame Timing .................................................................. 35
Mode 1 Transmit Timing .................................................................................... 36
Mode 1 Collision Detect Timing ......................................................................... 36
Mode 1 COL/CI Output Timing ........................................................................... 36
Mode 1 Loopback Timing ................................................................................... 36
Mode 2 RCLK/Start-of-Frame Timing ................................................................ 37
Mode 2 RCLK/End-of-Frame Timing .................................................................. 37
Mode 2 Transmit Timing .................................................................................... 38
Mode 2 Collision Detect Timing ......................................................................... 38
Mode 2 COL/CI Output Timing ........................................................................... 38
Mode 2 Loopback Timing ................................................................................... 38
Mode 3 RCLK/Start-of-Frame Timing (LXT901 only) ....................................... 39
Mode 3 RCLK/End-of-Frame Timing (LXT901 only) .......................................... 39
Mode 3 RCLK/Start-of-Frame Timing (LXT907 only) ....................................... 40
Mode 3 RCLK/End-of-Frame Timing (LXT907 only) .......................................... 40
Mode 3 Transmit Timing .................................................................................... 41
Mode 3 Collision Detect Timing ......................................................................... 41
Mode 3 COL/CI Output Timing ........................................................................... 41
Mode 3 Loopback Timing ................................................................................... 41
Mode 4 RCLK/Start-of-Frame Timing ................................................................ 42
Mode 4 RCLK/End-of-Frame Timing .................................................................. 42
Mode 4 Transmit Timing .................................................................................... 43
Mode 4 Collision Detect Timing ......................................................................... 43
Mode 4 COL/CI Output Timing ........................................................................... 43
Mode 4 Loopback Timing ................................................................................... 43
LXT901/907 Package Specifications .................................................................. 44
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Datasheet
LXT901/907 Signal Descriptions ........................................................................... 9
Controller Compatibility Modes ...........................................................................13
Crystal Specifications ..........................................................................................20
Suitable Crystals .................................................................................................20
Suitable Magnetics ..............................................................................................21
Absolute Maximum Ratings.................................................................................31
Recommended Operating Conditions .................................................................31
I/O Electrical Characteristics ...............................................................................31
AUI Electrical Characteristics ..............................................................................32
TP Electrical Characteristics ...............................................................................32
Switching Characteristics ....................................................................................33
RCLK/Start-of-Frame Timing...............................................................................33
RCLK/End-of-Frame Timing................................................................................33
Transmit Timing...................................................................................................34
Collision, COL/CI Output and Loopback Timing..................................................34
5
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Revision History
Revision
6
Date
Description
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
Figure 1. LXT901/907 Block Diagram
MD0
MODE SELECT LOGIC
Controller Compatibility
Port Select
Loopback
Link test
AUTOSEL
PAUI
LBK
LI
MD1
TCLK
CLKI
WATCHDOG
TIMER
XTAL
OSC
CLKO
TEN
TWISTED PAIR
INTERFACE
Select:
PLS Only
or
PLS / MAU
CMOS
TX
AMP
PULSE SHAPER
AND FILTER
TPOPB
TPOPA
TPONA
TPONB
RC
DO
COLLISION/
POLARITY
DETECT
CORRECT
MANCHESTER
ENCODER
*STP
*(LXT901 only)
RC
RX
SLICER
TPIP
TPIN
TXD
DROP CABLE
INTERFACE
RLD
REMOTE SIGNALING
RJAB
RCMPT
CD
LEDL
ECL
TX
AMP
SQUELCH / LINK
DETECT
DOP
DON
LPBK
RXD
MANCHESTER
DECODER
RCLK
+
DI
RX
SLICER
CI
COLLISION
RECEIVER
DIP
DIN
COLLISION LOGIC
CIP
CIN
COL
LEDR LEDT/PDN
Datasheet
LEDC/FDE *DSQE
NTH JAB
*(LXT907 only)
PLR
7
LXT901/907 — Universal 10BASE-T and AUI Transceivers
1.0
Pin Assignments and Signal Descriptions
MD1
MD0
NTH
CIN
CIP
VCC1
DON
DOP
DIN
DIP
PAUI
6
5
4
3
2
1
44
43
42
41
40
Figure 2. LXT901/907 Pin Assignments
RLD
7
39
TPIN
LI
8
38
TPIP
JAB
9
37
DSQE (907) or STP (901)
TPONB
TEST
10
36
TCLK
11
35
TPONA
TXD
12
34
VCC2
TEN
13
33
GND2
32
TPOPA
31
TPOPB
CLKO
Rev #
Part #
LOT #
FPO #
14
LXT901/907PC XX
XXXXXX
XXXXXXXX
28
RCLK
n/c
n/c
TPIN
TPIP
n/c
DSQE (907) or STP (901)
TPONB
TPONA
VCC2
GND2
TPOPA
TPOPB
PLR
RJAB
n/c
n/c
27
CD
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
26
RXD
24
RBIAS
25
23
RCMPT
22
GND1
RJAB
21
29
LEDC/FDE
LBK
17
20
PLR
AUTOSEL
19
30
18
16
LEDR
15
COL
LEDT/PDN
LEDL
CLKI
Rev #
Part #
LOT #
FPO #
LXT901LC XX
XXXXXX
XXXXXXXX
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
n/c
RCLK
CD
RXD
RCMPT
n/c
RBIAS
n/c
GNDA
GND1
LBK
LEDC/FDE
LEDL
LEDT/PDN
LEDR
n/c
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
n/c
RLD
LI
n/c
JAB
TEST
TCLK
TXD
TEN
CLKO
CLKI
COL
AUTOSEL
n/c
n/c
n/c
n/c
n/c
PAUI
DIP
DIN
n/c
DOP
DON
VCCA
VCC1
CIP
CIN
NTH
MD0
MD1
n/c
8
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
Table 1.
LXT901/907 Signal Descriptions
PLCC
LQFP
Symbol
I/O
1
10
VCC1
I
34
56
VCC2
I
Description
Power Inputs. Power supply inputs of +5 volts.
(LQFP Only)
-
9
VCCA
I
2
11
CIP
I
3
12
CIN
I
4
13
NTH
I
5
14
MD0
I
6
15
MD1
I
7
18
RLD
O
Remote Link Down. Output goes high to signal to the controller that the remote
port is in link down condition.
8
19
LI
1
Link Test Enable. Controls Link Integrity Test; enabled when LI = High, disabled
when LI = Low
9
21
JAB
O
Jabber Indicator. Output goes High to indicate Jabber state.
10
22
TEST
I
Test. For Intel internal use only. It is recommended to tie this pin High externally.
11
23
TCLK
O
Transmit Clock. A 10 MHz clock output. This clock signal should be directly
connected to the transmit clock input of the controller.
12
24
TXD
I
Transmit Data. Input signal containing NRZ data to be transmitted on the
network. Connect TXD directly to the transmit data output of the controller.
13
25
TEN
I
Transmit Enable. Enables data transmission and starts the watchdog timer.
Synchronous to TCLK (see Test Specifications for details).
14
26
CLKO
O
15
27
CLKI
I
Crystal Oscillator. A 20 MHz crystal must be connected across these pins, or a
20 MHz clock applied at CLKI with CLKO left open.
16
28
COL
O
Collision Detect. Output which drives the collision detect input of the controller.
AUI Collision Pair. Differential input to the AUI transceiver CI circuit. The input is
collision signaling or SQE.
Normal Threshold. Selects normal or reduced threshold.
When NTH is High, the normal TP squelch threshold is in effect.
When NTH is Low, the normal TP squelch threshold is reduced by 4.5 dB.
Mode Select 0 (MD0), Mode Select 1 (MD1). Mode select pins determine the
controller compatibility mode in accordance with Table 2.
Automatic Port Select.
17
29
AUTOSEL
I
When High, automatic port selection is enabled (the 901/907 defaults to the AUI
port only if TP link integrity = Fail).
When Low, manual port selection is enabled (the PAUI pin determines the active
port).
18
19
34
LEDR
OD
35
LEDT/
PDN
OD
I
Receive LED. Open drain driver for the receive indicator LED. Output is pulled
Low during receive.
Transmit LED (LEDT)/Power Down (PDN). Open drain driver for the transmit
indicator. Output is pulled Low during transmit. Do not allow this pin to float. If
unused, tie High.
If externally pulled Low, the LXT901/907 goes to power down state.
20
36
LEDL
OD
I
Link LED. Open drain driver for link integrity indicator. Output is pulled Low
during link test pass.
If externally tied Low, internal circuitry is forced to “Link Pass” state and the 901/
907 will transmit link test pulses continuously.
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
Datasheet
9
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Table 1.
PLCC
LXT901/907 Signal Descriptions (Continued)
LQFP
Symbol
I/O
Description
Collision LED (LEDC)/Full Duplex Enable (FDE). Open drain driver for the
collision indicator pulls Low during collision. LED “On”(i.e., Low output) time is
extended by approximately 100 ms.
21
37
LEDC/
FDE
OD
I
If externally tied Low, the LXT901/907 enables full duplex operation by disabling
the internal TP loopback and collision detection circuits in anticipation of external
TP loopback or full duplex operation.
If this pin is not used, tie high or directly to VCC.
Loopback. Enables internal loopback mode.
22
38
LBK
I
23
39
GND1
–
33
55
GND2
–
–
40
GNDA
–
24
42
RBIAS
I
Bias Control. A 12.4 kΩ 1% resistor to ground at this pin controls operating
circuit bias.
25
44
RCMPT
O
Remote Compatibility. Output goes High to signal the controller that the remote
port is compatible with the LXT901/LXT907 remote signaling features.
26
45
RXD
O
Receive Data. Connect RXD directly to the receive data input of the controller.
27
46
CD
O
Carrier Detect. An output to notify the controller of activity on the network.
Refer to Functional Descriptions for details.
Ground Returns. Grounds
(LQFP Only)
28
47
RCLK
O
Receive Clock. A recovered 10 MHz clock which is synchronous to the received
data. Connect to the controller receive clock input.
29
51
RJAB
O
Remote Jabber. Output goes High to indicate the remote port is in Jabber
condition.
30
52
PLR
O
Polarity Reverse. Output goes High to indicate reversed polarity at the TP input.
31
53
TPOPB
O
36
58
TPONB
O
32
54
TPOPA
O
35
57
TPONA
O
Twisted-Pair Transmit Pairs A & B. Two differential driver pair outputs (A and B)
to the twisted-pair cable. The outputs are pre-equalized. Each pair must be
shorted together and tied to the transformer with a 24.9Ω 1% series resistor to
match impedance of 100Ω.
Refer to Figure 16 in the Applications Section for information on 150Ω
configurations.
STP Select (LXT901 only).
37
59
STP
(LXT901)
I
When STP is Low, 150Ω termination for shielded TP is selected.
When STP is High, 100Ω termination for unshielded TP is selected.
LXT907 is designed for 100Ω UTP termination (not selectable).
Disable SQE (LXT907 only).
DSQE
(LXT907)
When DSQE is High, the SQE function is disabled.
I
When DSQE is Low, the SQE function is enabled.
SQE must be disabled for normal operation in Hub/Switch applications.
LXT901operates with SQE enabled (not selectable).
38
61
TPIP
I
39
62
TPIN
I
Twisted-Pair Receive Pair. A differential input pair from the TP cable. Receive
filter is integrated on-chip. No external filters are required.
Port/AUI Select. In Manual Port Select mode (AUTOSEL Low), PAUI selects the
active port.
40
3
PAUI
I
When PAUI is High, the AUI port is selected.
When PAUI is Low, the TP port is selected.
In Auto Port Select mode, PAUI must be tied to ground.
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
10
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
Table 1.
LXT901/907 Signal Descriptions (Continued)
PLCC
LQFP
Symbol
I/O
41
42
43
44
–
Description
4
DIP
I
5
DIN
I
7
DOP
O
8
DON
O
AUI Transmit Pair. A differential output driver pair for the AUI transceiver cable.
The output is Manchester encoded.
1, 2, 6,
16, 17,
20, 30,
31, 32,
33, 41,
43, 48,
49, 50,
60, 63,
64
N/C
–
No Connect (Internally tied to ground).
AUI Receive Pair. Differential input pair from the AUI transceiver DI circuit. The
input is Manchester encoded.
1. I/O Column Coding: I = Input, O = Output, OD = Open Drain
Datasheet
11
LXT901/907 — Universal 10BASE-T and AUI Transceivers
2.0
Functional Description
The LXT901/907 Universal 10BASE-T and AUI Transceivers perform the physical layer
signaling (PLS) and Media Attachment Unit (MAU) functions as defined by the IEEE 802.3
specification. They function as PLS-Only devices (for use with 10BASE-2 or 10BASE-5 coaxial
cable networks) or as Integrated PLS/MAU devices (for use with 10BASE-T twisted-pair
networks). In addition to standard 10 Mbps operation, they also support full-duplex 20 Mbps
operation. Unless otherwise noted, all the information in this data sheet applies to both the
LXT901 and LXT907.
The LXT901/907 interfaces a back end controller to either an AUI drop cable or a twisted-pair
(TP) cable. The controller interface includes transmit and receive clock and NRZ data channels, as
well as mode control logic and signaling. The AUI interface comprises three circuits: Data Output
(DO), Data Input (DI) and Collision (CI). The twisted-pair interface comprises two circuits:
Twisted-Pair Input (TPI) and Twisted-Pair Output (TPO). In addition to the three basic interfaces,
the LXT901/907 contains an internal crystal oscillator and four LED drivers for visual status
reporting.
Functions are defined from the back end controller side of the interface. The Transmit function
refers to data transmitted by the back end to the AUI cable (PLS-Only mode) or to the twisted-pair
network (Integrated PLS/MAU mode). The Receive function refers to data received by the back
end from the AUI cable (PLS-Only) or from the twisted-pair network (Integrated PLS/MAU
mode). In the integrated PLS/MAU mode, the LXT901/907 performs all required MAU functions
defined by the IEEE 802.3 10BASE–T specification such as collision detection, link integrity
testing, signal quality error messaging, jabber control and loopback. In the PLS-Only mode, the
LXT901/907 receives incoming signals from the AUI DI circuit with ± 18 ns of jitter and drives the
AUI DO circuit.
12
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
2.1
Controller Compatibility Modes
The LXT901/907 are compatible with most industry standard controllers including devices
produced by Motorola, AMD, Intel, Fujitsu, National Semiconductor, Seeq and Texas Instruments.
Four different control signal timing and polarity schemes (Modes 1 through 4) are required to
achieve this compatibility. Mode select pins (MD0 and MD1) determine controller compatibility
modes as listed in Table 2. Refer to Test Specifications for a complete set of timing diagrams for
each mode.
Table 2.
Controller Compatibility Modes
Setting
Controller Mode
MD1
MD0
Mode 1
For Motorola 68EN360, MPC860, Advanced Micro Devices AM7990, or compatible controllers
Low
Low
Mode 2
For Intel 82596 or compatible controllers1
Low
High
Mode 3
For Fujitsu MB86950, MB86960 or compatible controllers (Seeq 8005)2
High
Low
Mode 4
For National Semiconductor 8390 or compatible controllers (TI TMS380C26)
High
High
1. Refer to Intel Application Note 51 when designing with Intel controllers.
2. SEEQ controllers require inverters on CLKI, LBK, RCLK and COL.
2.2
Transmit Function
The LXT901/907 receives NRZ data from the controller at the TXD input as shown in the block
diagram on the first page of this Data Sheet, and passes it through a Manchester encoder. The
encoded data is then transferred to either the AUI cable (the DO circuit) or the twisted-pair network
(the TPO circuit). The advanced integrated pulse shaping and filtering network produces the
output signal on TPON and TPOP, shown in Figure 3. The TPO output is pre-distorted and
prefiltered to meet the 10BASE-T jitter template. An internal continuous resistor-capacitor filter is
used to remove any high-frequency clocking noise from the pulse shaping circuitry. Integrated
filters simplify the design work required for FCC compliant EMI performance. During idle
periods, the LXT901/907 transmits link integrity test pulses on the TPO circuit (if LI is enabled and
integrated PLS/ MAU mode is selected). External resistors control the termination impedance for
LXT907. External resistors and the STP pin control termination impedance on the LXT901.
Figure 3. LXT901/907 TPO Output Waveform
Datasheet
13
LXT901/907 — Universal 10BASE-T and AUI Transceivers
2.2.1
Jabber Control Function
Figure 4 is a state diagram of the LXT901/907 Jabber control function. The on-chip watchdog
timer prevents the DTE from locking into a continuous transmit mode. When a transmission
exceeds the time limit, the watchdog timer disables the transmit and loopback functions, and
activates the JAB pin. Once the LXT901/907 is in the jabber state, the TXD circuit must remain
idle for a period of 250 to 750ms before it will exit the jabber state.
Figure 4. Jabber Control Function
Power On
No Output
DO=Active
Nonjabber Output
Start_XMIT_MAX_Timer
DO=Idle
DO=Active*
XMIT_Max_Timer_Done
Jab
XMIT=Disable
LPBK=Disable
CI=SQE
DO=Idle
Unjab Wait
Start_Unjab_Timer
XMIT=Disable
LPBK=Disable
CI=SQE
Unjab_ Timer_Done
2.2.2
DO=Active*
Unjab_Timer_Not_Done
SQE Function
In the integrated PLS/MAU mode, the LXT901/907 supports the signal quality error (SQE)
function as shown in Figure 5. After every successful transmission on the 10BASE-T network
when SQE is enabled, the LXT901/907 transmits the SQE signal for 10BT ± 5BT over the internal
CI circuit which is indicated on the COL pin of the device. When using the 10BASE-2 port of the
LXT901/907, the SQE function is determined by the external MAU attached.
14
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
2.2.2.1
SQE Disable Function (LXT907 only)
SQE must be disabled for normal operation in hub and switch applications. The LXT907 offers an
SQE disable function. The SQE function is disabled when DSQE is set High, and enabled when
DSQE is Low.
Figure 5. SQE Function
Power On
Output Idle
DO=Active
Output Detected
DO=Idle
SQE Wait Test
Start_SQE_Test__Wait_Timer
XMIT=Disable
SQE_Test__Wait_Timer_Done∗
XMIT=Enable
SQE Test
Start_SQE_Test_Timer
CI=SQE
SQE_Test_Timer_Done
2.3
Receive Function
The LXT901/907 receive function acquires timing and data from the twisted-pair network (the TPI
circuit) or from the AUI (the DI circuit). Valid received signals are passed through the on-chip
filters and Manchester decoder then output as decoded NRZ data and receive timing on the RXD
and RCLK pins, respectively.
An internal RC filter and an intelligent squelch function discriminate noise from link test pulses
and valid data streams. The receive function is activated only by valid data streams above the
squelch level and with proper timing. If the differential signal at the TPI or the DI circuit inputs
falls below 75% of the threshold level (unsquelched) for 8 bit times (typical), the LXT901/907
receive function enters the idle state. If the polarity of the TPI circuit is reversed, LXT901/907
detects the polarity reverse and reports it via the PLR output. The LXT901/907 automatically
corrects reversed polarity.
Datasheet
15
LXT901/907 — Universal 10BASE-T and AUI Transceivers
2.3.1
Polarity Reverse Function
The LXT901/907 polarity reverse function uses both link pulses and end-of-frame data to
determine the polarity of the received signal. If Link Integrity Testing is disabled, polarity
detection is based only on received data. A reversed polarity condition is detected when eight
opposite receive link pulses are detected without receipt of a link pulse of the expected polarity.
Reversed polarity is also detected if four frames are received with a reversed start-of-idle.
Whenever a correct polarity frame or a correct link pulse is received, these two counters are reset to
zero. If the LXT901/907 enters the link fail state and no valid data or link pulses are received
within 96 to 128 ms, the polarity is reset to the default non-flipped condition. Polarity correction is
always enabled.
2.3.2
Collision Detection Function
The collision detection function operates on the twisted pair side of the interface. For standard
(half-duplex) 10BASE-T operation, a collision is defined as the simultaneous presence of valid
signals on both the TPI circuit and the TPO circuit. The LXT901/907 reports collisions to the
back-end via the COL pin. If the TPI circuit becomes active while there is activity on the TPO
circuit, the TPI data is passed to the back-end over the RXD circuit, disabling normal loopback.
Figure 6 is a state diagram of the LXT901/907 collision detection function. Refer to Test
Specifications for collision detection and COL/CI output timing. (NOTE: For full-duplex
operation on TP and AUI ports, the collision detection circuitry must be disabled.)
Figure 6. Collision Detection Function
A
DO=Active∗
TPI=Idle∗
XMIT=Enable
Power On
Idle
TPI=Active
Output
Input
TPO=DO
DI=DO
DI=TPI
DO=Active∗
TPI=Active∗
XMIT=Enable
DO=Active∗
TPI=Active∗
XMIT=Enable
Collision
A
DO=Idle+
XMIT=Disable
TPO=DO
DI=TPI
CI=SQE
DO=Active∗
TPI=Idle
16
A
TPI=Idle
DO=Idle
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
2.4
Loopback Functions
2.4.1
Standard TP Loopback
The LXT901/907 provides the standard loopback function defined by the 10BASE-T specification
for the twisted-pair port. The loopback function operates in conjunction with the transmit function.
Data transmitted by the back-end is internally looped back within the LXT901/907 from the TXD
pin through the Manchester encoder/decoder to the RXD pin and returned to the back-end. This
standard loopback function is disabled when a data collision occurs, clearing the RXD circuit for
the TPI data. Standard loopback is also disabled during link fail and jabber states. The LXT901/
907 also provides three additional loopback functions.
2.4.2
External Loopback
An external loopback mode, useful for system-level testing, is controlled by the LEDC pin. When
LEDC is tied Low, the LXT901/907 disables the collision detection and internal loopback circuits,
to allow external loopback. External loopback mode can be set on either TP or AUI ports.
2.4.3
Forced TP Loopback
“Forced” TP loopback is controlled by the LBK pin. When the TP port is selected and LBK is
High, TP loopback is “forced”, overriding collisions on the TP circuit. When LBK is Low, normal
loopback is in effect.
2.4.4
AUI Loopback
AUI loopback is also controlled by the LBK pin. When the AUI port is selected and LBK is High,
data transmitted by the back-end is internally looped back from the TXD pin through the
Manchester encoder/decoder to the RXD pin. When LBK is Low, no AUI loopback occurs.
2.5
Link Integrity Test Function
Figure 7 is a state diagram of the LXT901/907 Link Integrity test function. The link integrity test is
used to determine the status of the receive side twisted-pair cable. Link integrity testing is enabled
when the LI pin is tied High. When enabled, the receiver recognizes link integrity pulses which are
transmitted in the absence of receive traffic. If no serial data stream or link integrity pulses are
detected within 50 - 150 ms, the chip enters a link fail state and disables the transmit and normal
loopback functions. The LXT901/907 ignores any link integrity pulse with interval less than 2 - 7
ms. The LXT901/907 will remain in the link fail state until it detects either a serial data packet or
two or more link integrity pulses.
Datasheet
17
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Figure 7. Link Integrity Test Function
Power On
Idle Test
Start_Link_Loss_Timer
Start_Link_Test_Min_Timer
Link_Loss_Timer_Done
∗TPI=Idle
∗Link_Test_Rcvd=False
TPI=Active+
(Link_Test_Rcvd=True
∗Link_Test_Min_Timer_Done)
Link Test Fail Reset
Link Test Fail Wait
Link_Count=0
XMIT=Disable
RCVR=Disable
LPBK=Disable
TPI=Active
XMIT=Disable
RCVR=Disable
LPBK=Disable
Link_Count=Link_Count + 1
Link_Test_Rcvd=False
∗TPI=Idle
TPI=Active
Link_Test_Rcvd=Idle
∗TPI=Idle
Link Test Fail
Start_Link_Test_Min_Timer
Start_Link_Test_Max_Timer
XMIT=Disable
RCVR=Disable
LPBK=Disable
TPI=Active +
Link_Count=LC_Max
Link_Test_Min_Timer_Done
∗Link_Test_Rcvd=True
Link Test Fail Extended
XMIT=Disable
RCVR=Disable
LPBK=Disable
(TPI=Idle∗ Link_Test_Max_Timer_Done) +
(Link_Test_Min_Timer_Not_Done
∗Link_Test_Rcvd=True)
TPI=Idle∗
DO=Idle
18
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
2.5.1
Remote Signaling
The LXT901/907 transmits standard link pulses which meet the 10BASE-T specification.
However, the LXT901/907 encodes additional status information into the link pulse by varying the
link pulse timing. This is referred to as remote signaling. Using alternate pulse intervals, the
LXT901/907 can signal three local conditions: link down, jabber and remote signaling
compatibility. Figure 8 shows the interval variations used to signal local status to the other end of
the line. The LXT901/907 also recognizes these alternate pulse intervals when received from a
remote unit. Remote status conditions are reported to the controller over the RLD, RJAB and
RCMPT output pins.
Figure 8. Remote Signaling Link Integrity Pulse Timing
10 ms
15 ms
20 ms
10 ms
15 ms
20 ms
10 ms
20 ms
15 ms
LI-RLD
(note 1)
20 ms
15 ms
10 ms
20 ms
15 ms
10 ms
20 ms
15 ms
10 ms
LI-RJAB
(note 2)
10 ms
20 ms
10 ms
20 ms
10 ms
20 ms
10 ms
20 ms
10 ms
LI-RCMPT
(note 3)
907F07.VSD
NOTES:
1. For Remote Link Down (RLD) signaling, the interval between LI pulses increments from 10ms to 15ms, and then the cycle
starts over.
2. For Remote Jabber (RJAB) signaling, the interval between LI pulses decrements from 20ms to 15ms to 10ms, and then the
cycle starts over.
3. For Remote Compatibility (RCMPT) signaling, the interval between LI pulses continually switches between 10ms and 20ms.
Datasheet
19
LXT901/907 — Universal 10BASE-T and AUI Transceivers
3.0
Application Information
3.1
Twisted-Pair Impedance Matching
Resistors must be installed on each input and output pair to match impedance of the network media
being used. LXT907 is configured with 100Ω termination for Unshielded Twisted-Pair (UTP). In
this case, the positive and negative sides of both output pairs are shorted together (TPOPA/TPOPB
and TPONA/TPONB) and tied to the transformer through a 24.9Ω 1% series resistor.
The LXT901 is designed with an STP Select pin that allows the device to match both 100Ω and
150Ω media. A dual resistor combination can be configured to accommodate either line
termination as shown in Figure 16. When 100Ω termination is selected, both A and B pairs are
driven in parallel. When 150Ω termination is selected, the B pair is tri-stated and only the A pair is
driven.
3.2
Crystal Information
Designers should test and validate crystals to system requirements before committing to a specific
component. Crystal specifications for LXT901/907 are shown in
Table 3. Based on limited evaluation, Table 4 lists some suitable crystals.
Table 3.
Crystal Specifications
Parameter
Min
Nom
Max
Units
Frequency
–
25.0
–
MHz
–
+/-80
ppm
1
Frequency Stability
–
o
1. Test condition = -40 - 85 C
Table 4.
Suitable Crystals
Manufacturer
Part Number
MP-1
MTRON
MP-2
20
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
3.3
Magnetics Information
The LXT901 and LXT907 require a 1:1 ratio for the receive transformer and a 1:√2 ratio for the
transmit transformer on the twisted-pair interface. The AUI Interface requires a 1:1 ratio for both
the transmit and receive transformers. Designers should test and validate magnetics for system
requirements before committing to a specific component. Table 5 lists some suitable magnetics.
Table 5.
Suitable Magnetics
Manufacturer
Part Number
23Z128
Fil-Mag
23Z128SM
PT4069
Valor
ST7011
Twisted-Pair
A553-0716
Belfuse
S553-0716
TD42-2006Q
HALO
TG42-1406N1
23Z90
Fil-Mag
23Z90SM
LT6032
AUI
Valor
ST7032
TD01-0756K
HALO
TG01-0756N
3.4
Typical Applications
Figure 9 through Figure 16 show typical LXT901/907 applications.
3.4.1
Auto Port Select with External Loopback Control
Figure 9 is a typical LXT901/907 application. The diagram is arranged to group similar pins
together; it does not represent the actual LXT901/907 pinout. The controller interface pins
(transmit data, clock and enable; receive data and clock; and the collision detect, carrier detect and
loopback control pins) are shown at the top left.
Datasheet
21
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Programmable option pins are grouped center left. The PAUI pin is tied Low and all other option
pins are tied High. This set-up selects the following options:
• Automatic Port Selection
(PAUI Low and AUTOSEL High)
•
•
•
•
•
Normal Receive Threshold (NTH High)
Mode 4, compatible with National NS8390 controllers (MD0 High, MD1 High)
SQE Disabled (DSQE High on LXT907 only)
100Ω termination UTP cable (STP High on LXT901 only)
Link Testing Enabled (LI High)
Status outputs are grouped at lower left. Local status outputs drive LED indicators and remote
status indicators are available as required.
Power and ground pins are shown at the bottom of the diagram. A single power supply is used for
both VCC1 and VCC2 with a decoupling capacitor installed between the power and ground busses.
The TP and AUI interfaces are shown at upper and lower right, respectively. Impedance matching
resistors for 100Ω UTP are installed in each I/O pair but no external filters are required.
22
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
Figure 9. LAN Adapter Board - Auto Port Select with External LPBK Control
TXE
TXC
NS8390 BACK-END
CONTROLLER
INTERFACE
RXC
RXD
CRS
COL
LOOPBACK
ENABLE
LBK
Green Red
Red Red
1 : 1 16
6
50 Ω
50 Ω
TPIP
CD
COL
LBK
PAUI
330
1
TPIN
TEN
TCLK
RCLK
RXD
5
3
14
4
TPONB
TPONA
24.9 Ω 1% 6 1 : 2
3
11
2
TPOPB
TPOPA
LXT901/907
LINE STATUS
330
RJ45
TXD
DSQE (907)
STP (901)
LI
RJAB
RLD
RCMPT
JAB
PLR
REMOTE
STATUS
330
2
CLKO
AUTOSEL
NTH
MD0
MD1
PROGRAMMING
OPTIONS
330
CLKI
0.1 µF
20 pF
78 Ω
CIN
8
9
1
1
1
16
9
2
10
CIP
LEDC/FDE
LEDR
LEDT/PDN
LEDL
24.9 Ω 1%
DON
2
3
15
78 Ω 4 1 : 1 13
11
4
12
5
DOP
DIN
5
12
78 Ω 7 1 : 1 10
D - CONNECTOR to
AUI DROP CABLE
TXD
20 MHz
To 10 BASE-T TWISTEDPAIR NETWORK
20 pF
13
6
14
7
15
8
TEST
+5 V
8
DIP
VCC1
RBIAS
VCC2
GND1
GND2
12.4 kΩ 1%
1
1
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
2
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
Datasheet
Fuse
9
Chassis
Gnd
+ 12 V
23
LXT901/907 — Universal 10BASE-T and AUI Transceivers
3.4.2
Full Duplex Support
Figure 10 shows the LXT907 with a Texas Instruments 380C24 CommProcessor. The 380C24 is
compatible with Mode 4 (MD0 and MD1 both High). When used with the 380C24 or other full
duplex-capable controller, the LXT907 supports full-duplex Ethernet, effectively doubling the
available bandwidth of the network. In this application the SQE function is enabled (DSQE tied
Low), and the AUI port is not used.
Figure 10. Full-Duplex Operation
CLKI
3
4
CLKO
TXD
TEN
TXD
TXEN
TXC
RXC
RXD
CSN
COLL
0.1 µF
20 pF
20 MHz
RJ45
1
TPIN
6
50 Ω
TCLK
RCLK
RXD
50 Ω
TPIP
5
3
14
CD
COL
LPBK
*TEST0
OUTSEL0
1N914
4
LBK
TPONB
LEDC/FDE
1
TPONA
TPOPB
TPOPA
MD0
4.7 KΩ
MD1
LI
24.9 Ω 1%
DSQE (907)
CIN
RJAB
RLD
RCMPT
CIP
1
330
330
Green Red Red
PLR
DON
PAUI
DOP
LEDR
LEDT/PDN
LEDL
8
9
1
Half/Full Duplex Selection controlled by TMS380C24 Pins
Test0 and OUTSEL0.
2
Bias resistor RBIAS should be located close to the pin
and isolated from other signals.
3
The TMS380C26 may be substituted for dual network
support of 10BASE-T and Token Ring.
4
Optional: Centertap capacitor may improve EMC
depending on board layout and system design.
JAB
LINE STATUS
3
LXT907
NTH
REMOTE
STATUS
11
2
AUTOSEL
PROGRAMMING
OPTIONS
24.9 Ω 1% 6 1 : 2
10 KΩ
*Open Collector
Driver
330
1 : 1 16
To 10 BASE-T TWISTEDPAIR NETWORK
20 pF
TMS380C24
DIN
DIP
TEST
+5 V
VCC1
12.4 kΩ 1 %
RBIAS
VCC2
GND1 GND2
24
2
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
3.4.3
Dual Network Support - 10Base-T and Token Ring
Figure 11 shows the LXT901/907 with a Texas Instruments 380C26 CommProcessor. The 380C26
is compatible with Mode 4 (MD0 and MD1 both High). When used with the 380C26, both the
LXT901/907 and a TMS38054 Token Ring transceiver can be tied to a single RJ45 allowing dual
network support from a single connector. The LXT901/907 AUI port is not used. The LXT901
STP is High and the LXT907 DSQE is Low.
Figure 11. 380C26 Interface for Dual Network Support of 10BASE-T and Token Ring
From TI TMS38054 Token Ring
Transceiver
To TI TMS38054 Token Ring
Transceiver
380C26
CLKI
TXD
TXD
1
RCLK
RXD
COL
LBK
COL
14
3
4
TPONB
TPOPA
Green Red Red
Red
TEST
PAUI
LEDC/FDE
LEDR
LEDT/PDN
LEDL
LXT901/907
330
24.9 Ω 1%
8
1: 2
11
3
9
1
TPOPB
STP (LXT901)
DSQE (LXT907)
LI
RJAB
RLD
RCMPT
JAB
330
6
2
MD1
PLR
24.9 Ω 1%
TPONA
MD0
LINE STATUS
330
5
50 Ω
TPIP
LBK
REMOTE
STATUS
RJ45
6
CD
PROGRAMMING
OPTIONS
2
50 Ω
TCLK
RXC
RXD
CRS
1 : 1 16
TPIN
AUTOSEL
NTH
330
3
CLKO
TEN
TXE
TXC
0.1 µF
20 pF
20 MHz
To 10 BASE-T TWISTEDPAIR NETWORK
20 pF
CIN
CIP
1
Bias resistor RBIAS should be located close to the p
and isolated from other signals.
2
Additional magnetics and switching logic (not shown)
are required to implement the dual network solution.
DON
DOP
3
Optional: Centertap capacitor may improve EMC
depending on board layout and system design.
DIN
DIP
+5 V
12.4 kΩ 1%
VCC1
RBIAS
VCC2
GND1
Datasheet
GND2
1
25
LXT901/907 — Universal 10BASE-T and AUI Transceivers
3.4.4
Manual Port Select with Link Test Function
With MD0 Low and MD1 tied High, the LXT901/907 logic and framing are set to Mode 3
(compatible with Fujitsu MB86950 and MB86960, and Seeq 8005 controllers). Figure 12 shows
the setup for Fujitsu controllers. Figure 12 on page 26 shows the four inverters required to
interface with the Seeq 8005 controller. As in Figure 9 on page 23, both these Mode 3 applications
show the LI pin tied High, enabling Link Testing; and the STP (LXT901 only) and NTH pins are
both tied High, selecting the standard receiver threshold and 100 Ω termination for unshielded TP
cable. However, in these applications AUTOSEL is tied Low, allowing external port selection
through the PAUI pin. The remote status outputs are inverted to drive LED indicators.
Figure 12. LAN Adapter Board - Manual Port Select with Link Test Function
20 pF
0.1 µF
20 pF
20 MHz
TCKN
MB86950 or MB86960
BACK-END/
CONTROLLER
INTERFACE
RCKN
RXD
XCD
XCOL
LBC
Port Selection
Amber
330
330
Amber Amber
REMOTE & LINE
STATUS
330
330
Green
Red
330
Red
6
5
50 Ω
Red
14
3
TPIP
4
TPONB
TPONA
24.9 Ω 1%
6
1: 2
3
11
2
24.9 Ω 1%
8
9
1
TPOPA
TPOPB
78 Ω
CIN
1
1
16
9
2
10
330
LEDC/FDE
LEDR
LEDT/PDN
LEDL
16
50 Ω
LXT901/907
330
1:1
TPIN
RXD
CD
COL
LBK
DSQE (907)
STP (901)
LI
RJAB
RLD
RCMPT
JAB
PLR
RJ45
1
PAUI
AUTOSEL
NTH
MD0
MD1
PROGRAMMING
OPTIONS
2
CLKO
2
CIP
78 Ω
DON
3
15
11
4
1:1
4
13
12
5
DOP
78 Ω
DIN
To 10 BASE-T TWISTEDPAIR NETWORK
TEN
CLKI
TXD
TEN
TCLK
RCLK
5
12
7
1 : 1 10
D - CONNECTOR to
AUI DROP CABLE
TXD
13
6
14
7
15
8
TEST
+5 V
8
DIP
Fuse
9
12.4 kΩ
VCC1
RBIAS
VCC2
1%
GND1 GND2
1
Chassis
Gnd
+ 12 V
1
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
2
26
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
Figure 13. Manual Port Select with Seeq 8005 Controller
External
20 MHz
Source
RxC
TxC
TxD
TPONB
TPONA
RJAB
RLD
RCMPT
Amber Amber
REMOTE & LINE
STATUS
330
330
330
JAB
PLR
330
24.9 Ω 1% 6 1 : 2
TPOPA
24.9 Ω 1%
Red
Red
Red
LEDC/FDE
LEDR
LEDT/PDN
LEDL
TEST
8
9
1
TPOPB
1
78 Ω
1
CIN
16
9
2
10
2
Green
3
11
2
LXT901/907
Amber
DSQE (907)
STP (901)
LI
330
330
14
4
NTH
MD0
MD1
330
5
3
TPIP
PAUI
AUTOSEL
Port Selection
6
50 Ω
TEN
TCLK
TXD
TxEN
16
50 Ω
RCLK
COL
COLL
1:1
TPIN
CD
RXD
RxD
RJ45
1
To 10 BASE-T TWISTEDPAIR NETWORK
CSN
2
CLKO
CLKI
LBK
LPBK
8005
0.1 µF
CIP
3
15
11
78 Ω
4
DON
1:1
4
13
12
5
5
12
7
1 : 1 10
13
6
DOP
78 W
DIN
D - CONNECTOR to
AUI DROP CABLE
CLKI
Left Open
14
7
15
8
8
DIP
+5 V
VCC1
RBIAS
VCC2
GND1 GND2
12.4 kΩ 1 %
1
1
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
2
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
Datasheet
Fuse
9
Chassis
Gnd
+ 12 V
27
28
0.1 µF
+5 V
10 k Ω
Power Down
10 k Ω
LINE STATUS
MODE SELECT
LinkTest
Enable
PROGRAMMING
OPTIONS
LBK
CDT
CRS
RXD
RXC
RTS
TXC
CLK
TXD
1
CLKO
12.4 Ω
1%
RBIAS
TEST
VCC2
VCC1
LEDL
LEDT/PDN
LEDC/FDE
LEDR
PLR
JAB
MD0
MD1
LI
PAUI
DSQE (907)
NTH
AUTOSEL
LBK
COL
CD
RXD
RCLK
TCLK
TEN
TXD
CLKI
GND1
GND2
DIP
DIN
DOP
DON
CIP
CIN
TPOPB
TPOPA
TPONA
TPONB
TPIP
TPIN
50 Ω
24.9 Ω 1%
24.9 Ω 1%
50 Ω
2
1:1
8
6 1:2
3
1
9
11
14
16
78 Ω
78 Ω
78 Ω
1
2
3
4
5
6
10
9
8
12
13
15
16
7
5
4
2
1
9
10
8
12
13
15
7
1:1
1:1
16
To 10BASE-T
TWISTEDPAIR
NETWORK
5
4
2
1
RJ45
8
7
6
5
4
3
2
Chassis
Gnd
15
14
13
12
11
10
9
1
1.5 kΩ
+ 12 V
Fuse
D - CONNECTOR to
AUI DROP CABLE
(Thick Coax)
HBE
GND
RXRX+
RR+
RR-
VEE
RXI
TXD
CDS
TX+
VEE
VEE
TX-
CD+
CD-
0.01 µF
1/2 W
1 MΩ
-9V
1 kΩ 1%
1N916
0V
9
13
12
V-
N/C
V+
24
23
3
1
2
75 µF / 1 kV
GND
GND
EN
5V
5V
PM6044
BNC to THIN
COAX
NETWORK
2
DP8392
Bias resistor RBIAS should be located close to the pin and isolated
from other signals.
Optional: Centertap capacitor may improve EMC depending on board
layout and system design.
1
+5 V
3.4.5
82596 BACK-END/
CONTROLLER
INTERFACE
20 MHz
System
Clock
0.1 µF
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Three Media Application
Figure 14 shows the LXT907 in Mode 2 (compatible with Intel 82596 controllers) with additional
media options for the AUI port. Two transformers are used to couple the AUI port to either a Dconnector or a BNC connector. (A DP8392 coax transceiver with PM6044 power supply are
required to drive the thin coax network through the BNC.)
Figure 14. Three Media Application
LXT907
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
3.4.6
AUI Encoder/Decoder ONLY
In Figure 15, the DTE is connected to a coaxial network through the AUI. AUTOSEL is tied Low
and PAUI is tied High, manually selecting the AUI port. The twisted-pair port is not used. With
MD1 and MD0 both Low, the logic and framing are set to Mode 1 (compatible with AMD
AM7990 controllers). The LI pin is tied Low, disabling the link test function. The DSQE pin is
also Low, enabling the SQE function on the LXT907. The LBK input controls loopback. A 20
MHz system clock is supplied at CLK1 with CLK0 left open.
Figure 15. AUI Encoder/Decoder Only Application
Left Open
20 MHz
TX
TENA
TCLK
RCLK
AM7990 BACK-END/
CONTROLLER
INTERFACE
RX
RENA
CLSN
LOOPBACK
CONTROL
LBK
CLKI
CLKO
TXD
TEN
TCLK
RCLK
RXD
CD
COL
LBK
AUTOSEL
78 Ω
PAUI
NTH
PROGRAMMING
OPTIONS
CIN
CIP
330
330
330
LXT907
LINE STATUS
9
10
DSQE (907)
REMOTE
STATUS
16
2
MD0
MD1
LI
RJAB
RLD
RCMPT
JAB
PLR
1
1
DON
2
78 Ω 4
3
15
11
4
1:1 13
12
5
DOP
DIN
5
12
78 Ω 7
1:1 10
330
13
6
14
D - CONNECTOR to
AUI DROP CABLE
SYSTEM
CLOCK
7
15
8
GREEN
Red
Red Red
LEDC/FDE
LEDR
LEDT/PDN
LEDL
8
DIP
Fuse
9
Chassis
Gnd
+ 12 V
TEST
+5 V
VCC1
RBIAS
VCC2
GND1 GND2
1
Datasheet
12.4 Ω 1%
1
Bias resistor RBIAS should be located close to the pin and isolated from the other signals.
29
LXT901/907 — Universal 10BASE-T and AUI Transceivers
150 Ω Shielded Twisted-Pair Only (LXT901 only)
3.4.7
Figure 16 shows the LXT901 in a typical twisted-pair only application. The DTE is connected to a
10BASE-T network through the twisted-pair RJ45 connector. (The AUI port is not used). With
MD0 tied High and MD1 Low, the LXT901 logic and framing are set to Mode 2 (compatible with
Intel 82596 controllers).
A 20 MHz system clock input at CLK1 is used in place of the crystal oscillator. (CLK0 is left
open). The L1 pin externally controls the link test function. The UTP/STP and NTH pins are both
tied Low, selecting the reduced receiver threshold and 150 Ω termination for shielded TP cable.
The switch at LEDT/PDN manually controls the power down mode.
Figure 16. 150 Ω Shielded Twisted-Pair Only Application (LXT901)
CLK
TXD
RTS
TXC
RXC
RXD
CRS
CDT
LBK
82596
BACK-END/
CONTROLLER
INTERFACE
0.1 µF
CLK1
TXD
TEN
TCLK
RCLK
RXD
RCLK
CD
COL
LBK
AUTOSEL
PAUI
NTH
MD0
MD1
STP
PROGRAMMING
OPTIONS
LI
Link Test Enable
REMOTE
STATUS
RJAB
RLD
RCMPT
LINE STATUS
JAB
PLR
10K
10K
2
CLK0
RJ45
1
30
16
TPIN
6
75 Ω
5
75 Ω
14
3
TPIP
4
75 Ω 1%
TPONB
6
TPONA
1: 2
11
37.5 Ω 1%
37.5 Ω 1%
TPOPA
3
2
8
9
1
TPOPB
75 Ω 1%
TEST
LEDC/FDE
LEDR
LEDL
+5 V
1:1
To 10 BASE-T TWISTEDPAIR NETWORK
Left Open
LXT901
20 MHz
SYSTEM
CLOCK
LEDT/PDN
VCC1
VCC2
RBIAS
GND1
GND2
12.4 kΩ
1%
1
1
Bias resistor RBIAS should be located close to the pin and isolated from other signals.
2
Optional: Centertap capacitor may improve EMC depending on board layout and system design.
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
4.0
Test Specifications
Note:
Table 6.
Table 6 through Table 15 and Figure 17 through Figure 42 represent the performance specifications
of the LXT901/907. These specifications are guaranteed by test except where noted “by design.”
Minimum and maximum values listed in Table 8 through Table 15 apply over the recommended
operating conditions specified in Table 7.
Absolute Maximum Ratings
Parameter
Supply voltage
Ambient operating temperature
Storage temperature
Symbol
Min
Max
Units
VCC
-0.3
6
V
TA
0
70
ºC
TSTG
-65
+150
ºC
Caution: Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 7.
Recommended Operating Conditions
Parameter
Recommended supply voltage
1
Recommended operating temperature
Symbol
Min
Typ
Max
Units
VCC
4.75
5.0
5.25
V
TOP
0
–
70
ºC
1. Voltages with respect to ground unless otherwise specified. Power supply should be filtered to suppress high frequency
transients, consistent with good PCB design.
Table 8.
I/O Electrical Characteristics
Parameter
Sym
Min
Typ1
Max
Units
Test Conditions
Input low voltage2
VIL
–
–
0.8
V
Input high voltage2
VIH
2.0
–
–
V
Output low voltage
VOL
–
–
0.4
V
IOL = 1.6 mA
VOL
–
–
10
%VCC
IOL < 10 µA
Output low voltage
(Open drain LED driver)
VOLL
–
–
0.7
%VCC
IOLL = 10 mA
Output high voltage
VOH
2.4
–
–
V
IOH = 40 µA
VOH
90
–
–
%VCC
IOH < 10 µA
CMOS
–
–
3
12
ns
CLOAD = 20 pF
TCLK & RCLK
TTL
–
–
2
8
ns
Output fall time
CMOS
–
–
3
12
ns
TCLK & RCLK
TTL
–
–
2
8
ns
CLKI rise time (externally driven)
–
–
–
10
ns
CLKI duty cycle (externally driven)
–
–
50/50
40/60
%
Output rise time
CLOAD= 20 pF
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed at levels of 0V and
3V.
Datasheet
31
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Table 8.
I/O Electrical Characteristics (Continued)
Parameter
Supply current
Normal Mode
Power Down Mode
Sym
Min
Typ1
ICC
–
ICC
–
ICC
ICC
Max
Units
Test Conditions
65
85
mA
Idle Mode
90
110
mA
Transmitting on TP
–
70
90
mA
Transmitting on AUI
–
0.75
2
mA
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. Limited functional tests are performed at these input levels. The majority of functional tests are performed at levels of 0V and
3V.
Table 9.
AUI Electrical Characteristics
Symbol
Min
Typ1
Max
Units
Input Low current
IIL
–
–
-700
µA
Input High current
IIH
–
–
500
µA
Differential output voltage
VOD
±550
–
±1200
mV
Differential squelch threshold
VDS
150
250
350
mV
Parameter
Test Conditions
5 MHz square wave input
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 10. TP Electrical Characteristics
Symbol
Min
Typ1
Max
Units
ZOUT
–
5
–
Ω
Transmit timing jitter addition
–
–
±3.3
±10
ns
0 line length for internal MAU
Transmit timing jitter added by the MAU
and PLS sections
–
–
±3.3
±5.5
ns
After line model specified by
IEEE 802.3 for 10BASE-T
internal MAU
ZIN
–
20
–
kΩ
Between TPIP/TPIN, CIP/
CIN & DIP/DIN
Normal
Threshold;
NTH = High
VDS
300
400
585
mV
5 MHz square wave input
Reduced
Threshold;
NTH = Low
VDS
180
250
345
mV
5 MHz square wave input
Parameter
Transmit output impedance
Receive input impedance
Differential Squelch
Threshold
Test Conditions
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
32
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
Table 11. Switching Characteristics
Parameter
Symbol
Minimum
Typical1
Maximum
Units
Maximum transmit time
–
20
–
150
ms
Unjab time
–
250
–
750
ms
Time link loss receive
–
50
–
150
ms
Link min receive
–
2
–
7
ms
Link max receive
–
50
–
150
ms
Link transmit period
–
8
10
24
ms
Jabber Timing
Link Integrity
Timing
1. Typical values are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
Table 12. RCLK/Start-of-Frame Timing
Symbol
Minimum
Typical1
Maximum
Units
AUI
tDATA
–
900
1100
ns
TP
tDATA
–
1200
1500
ns
Parameter
Decoder acquisition time
AUI
tCD
–
25
200
ns
TP
tCD
–
425
550
ns
CD turn-on delay
Receive data setup from
RCLK
Mode 1
tRDS
60
70
–
ns
Modes 2, 3 and 4
tRDS
30
45
–
ns
Receive data hold from
RCLK
Mode 1
tRDH
10
20
–
ns
Modes 2, 3 and 4
tRDH
30
45
–
ns
tsws
–
±90
–
ns
RCLK shut off delay from CD assert
(LXT907 only; Mode 3)
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Table 13. RCLK/End-of-Frame Timing
Parameter
Type
Sym
Mode 1
Mode 2
Mode 3
Mode 4
Units
RCLK after CD off
Min
tRC
5
1
27
5
bt
Rcv data throughput delay
Max
tRD
400
375
375
375
ns
2
Max
tCDOFF
500
475
475
475
ns
Receive block out after TEN off
Typ1
tIFG
5
50
–
–
bt
RCLK switching delay after CD off
(LXT907 only; Mode 3)
Typ1
tSWE
–
–
120(±80)
–
ns
CD turn off delay
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
2. CD turn-off delay measured from middle of last bit: timing specification is unaffected by the value of the last bit.
Datasheet
33
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Table 14. Transmit Timing
Parameter
Symbol
Minimum
Typical 1
Maximum
Units
TEN setup from TCLK
tEHCH
22
–
–
ns
TXD setup from TCLK
tDSCH
22
–
–
ns
TEN hold after TCLK
tCHEL
5
–
–
ns
TXD hold after TCLK
tCHDU
5
–
–
ns
Transmit start-up delay - AUI
tSTUD
–
220
450
ns
Transmit start-up delay - TP
tSTUD
–
430
450
ns
Transmit through-put delay - AUI
tTPD
–
–
300
ns
Transmit through-put delay - TP
tTPD
–
300
350
ns
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Table 15. Collision, COL/CI Output and Loopback Timing
Parameter
Typical1
Symbol
Minimum
Maximum
Units
COL turn-on delay
tCOLD
–
40
500
ns
COL turn-off delay
tCOLOFF
–
420
500
ns
COL (SQE) Delay after TEN off
tSQED
0.65
1.2
1.6
µs
COL (SQE) Pulse Duration
tSQEP
500
1000
1500
ns
LBK setup from TEN
tKHEH
10
25
–
ns
LBK hold after TEN
tKHEL
10
0
–
ns
1. Typical values are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
34
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
4.1
Timing Diagrams for Mode 1 (MD1 = Low, MD0 = Low)
Figure 17 through Figure 22
Figure 17. Mode 1 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
0
1
0
1
1
1
TPIP/TPIN
or DIP/DIN
tCD
CD
RCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
0
1
Figure 18. Mode 1 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
tRC
RCLK
RXD
1
Datasheet
0
1
0
1
0
1
0
0
35
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Figure 19. Mode 1 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tDSCH
tCHDU
TXD
tSTUD
tTPD
TPO
Figure 20. Mode 1 Collision Detect Timing
CI
tCOLD
tCOLOFF
COL
Figure 21. Mode 1 COL/CI Output Timing
TEN
tSQED
COL
tSQEP
Figure 22. Mode 1 Loopback Timing
LBK
tKHEH
tKHEL
TEN
36
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
4.2
Timing Diagrams for Mode 2 (MD1=Low, MD0=High)
Figure 23 through Figure 28
Figure 23. Mode 2 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
0
1
0
1
1
1
TPIP/TPIN
or DIP/DIN
tCD
CD
RCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
0
1
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 24. Mode 2 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
CD
tCDOFF
tRD
RCLK
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Datasheet
37
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Figure 25. Mode 2 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tDSCH
tCHDU
TXD
tSTUD
tTPD
TPO
Figure 26. Mode 2 Collision Detect Timing
CI
tCOLD
tCOLOFF
COL
Figure 27. Mode 2 COL/CI Output Timing
tIFG
TEN
tSQED
COL
tSQEP
Figure 28. Mode 2 Loopback Timing
LBK
tKHEH
tKHEL
TEN
38
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
4.3
Timing Diagrams for Mode 3 (MD1 = High, MD0 = Low)
Figure 29 through Figure 36
Figure 29. Mode 3 RCLK/Start-of-Frame Timing (LXT901 only)
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
0
1
0
1
1
TPIP/TPIN
or DIP/DIN
tCD
CD
RCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
1
0
1
Figure 30. Mode 3 RCLK/End-of-Frame Timing (LXT901 only)
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
RCLK
27 bits
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Datasheet
39
LXT901/907 — Universal 10BASE-T and AUI Transceivers
Figure 31. Mode 3 RCLK/Start-of-Frame Timing (LXT907 only)
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
or DIP/DIN
tCD
CD
tSWS
Recovered from Input Data Stream
RCLK
tRDS
Generated from TCLK
tRDH
tDATA
RXD
1
0
1
0
1
0
1
0
1
1
1
0
1
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 32. Mode 3 RCLK/End-of-Frame Timing (LXT907 only)
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
tSWE
RCLK
Recovered Clock
Generated from TCLK
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
40
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
Figure 33. Mode 3 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tDSCH
tCHDU
TXD
tSTUD
tTPD
TPO
Figure 34. Mode 3 Collision Detect Timing
CI
tCOLOFF
tCOLD
COL
Figure 35. Mode 3 COL/CI Output Timing
TEN
tSQED
tSQEP
COL
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 36. Mode 3 Loopback Timing
LBK
tKHEH
tKHEL
TEN
Datasheet
41
LXT901/907 — Universal 10BASE-T and AUI Transceivers
4.4
Timing Diagrams for Mode 4 (MD1 = High, MD0 = High)
Figure 37 through Figure 42
Figure 37. Mode 4 RCLK/Start-of-Frame Timing
1
0
1
0
1
0
1
0
1
1
1
0
1
0
0
0
1
0
1
TPIP/TPIN
or DIP/DIN
tCD
CD
RCLK
tRDS
tRDH
tDATA
RXD
1
0
1
0
1
0
1
0
1
1
1
0
1
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
Figure 38. Mode 4 RCLK/End-of-Frame Timing
1
0
1
0
1
0
1
0
0
TPIP/TPIN
or DIP/DIN
tCDOFF
CD
tRD
RCLK
RXD
1
0
1
0
1
0
1
0
0
NOTE:
1. RXD changes at the rising edge of RCLK. The controller is sampled at the falling edge.
42
Datasheet
Universal 10BASE-T and AUI Transceivers — LXT901/907
Figure 39. Mode 4 Transmit Timing
TEN
tCHEL
tEHCH
TCLK
tDSCH
tCHDU
TXD
tTPD
tSTUD
TPO
Figure 40. Mode 4 Collision Detect Timing
CI
tCOLOFF
tCOLD
COL
Figure 41. Mode 4 COL/CI Output Timing
TEN
tSQED
COL
tSQEP
Figure 42. Mode 4 Loopback Timing
LBK
tKHEH
tKHEL
TEN
Datasheet
43
LXT901/907 — Universal 10BASE-T and AUI Transceivers
5.0
Mechanical Specifications
Figure 43. LXT901/907 Package Specifications
44-Pin PLCC
64-Pin LQFP
• Part Number LXT901PC and LXT907PC
• Commercial Temp Range (0oC to 70oC)
• Part Number LXT901LC
• Commercial Temp Range (0oC to 70oC)
CL
D
D1
C
B
E1
e
e/
2
for sides with
even
number of pins
for sides with odd
number of pins
D1
D
θ3
L1
A2
A1
A
A1
L
F
Inches
A2
A
D
θ
θ3
B
Inches
Millimeters
Millimeters
Dim
Min
Max
Min
Max
A
–
0.063
–
1.60
A1
0.002
0.006
0.05
0.15
A2
0.053
0.057
1.35
1.45
2.108
B
0.007
.011
0.17
0.27
–
D
0.472 BSC
12.00 BSC
0.660
0.813
D1
0.394 BSC
10.00 BSC
0.695
17.399
17.653
E
0.472 BSC
12.00 BSC
0.650
0.656
16.510
16.662
E1
0.394 BSC
10.00 BSC
0.013
0.021
0.330
0.533
e
0.020 BSC
0.50 BSC
Dim
Min
Max
Min
Max
A
0.165
0.180
4.191
4.572
A1
0.090
0.120
2.286
3.048
A2
0.062
0.083
1.575
B
0.050
–
1.270
C
0.026
0.032
D
0.685
D1
F
L
L1
44
E
0.018
0.030
0.45
0.039 REF
0.75
1.00 REF
θ3
11o
13o
11o
13o
θ
0o
7o
0o
7o
Datasheet
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