datasheet for SST39SF020A by Microchip Technology Inc.

datasheet for SST39SF020A by Microchip Technology Inc.
1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash
A Microchip Technology Company
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
The SST39SF010A / SST39SF020A / SST39SF040 are CMOS Multi-Purpose
Flash (MPF) devices manufactured with SST proprietary, high performance
CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate
approaches. The SST39SF010A / SST39SF020A / SST39SF040 write (Program
or Erase) with a 4.5-5.5V power supply, and conforms to JEDEC standard pinouts
for x8 memories
Features
• Organized as 128K x8 / 256K x8 / 512K x8
• Single 4.5-5.5V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
(typical values at 14 MHz)
– Active Current: 10 mA (typical)
– Standby Current: 30 µA (typical)
• Sector-Erase Capability
– Uniform 4 KByte sectors
• Fast Read Access Time:
– 45 ns
– 55 ns
– 70 ns
• Latched Address and Data
• Automatic Write Timing
• Fast Erase and Byte-Program
– Sector-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Chip Rewrite Time:
2 seconds (typical) for SST39SF010A
4 seconds (typical) for SST39SF020A
8 seconds (typical) for SST39SF040
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32-lead PLCC
– 32-lead TSOP (8mm x 14mm)
– 32-pin PDIP
• All devices are RoHS compliant
– Internal VPP Generation
©2011 Silicon Storage Technology, Inc.
www.microchip.com
DS25022A
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
Product Description
The SST39SF010A/020A/040 are CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The
SST39SF010A/020A/040 devices write (Program or Erase) with a 4.5-5.5V power supply. The
SST39SF010A/020A/040 devices conform to JEDEC standard pinouts for x8 memories.
Featuring high performance Byte-Program, the SST39SF010A/020A/040 devices provide a maximum
Byte-Program time of 20 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of
applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data
retention is rated at greater than 100 years.
The SST39SF010A/020A/040 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, they significantly
improve performance and reliability, while lowering power consumption. They inherently use less
energy during erase and program than alternative flash technologies. The total energy consumed is a
function of the applied voltage, current, and time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and has a shorter erase time, the total energy
consumed during any Erase or Program operation is less than alternative flash technologies. These
devices also improve flexibility while lowering the cost for program, data, and configuration storage
applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the SST39SF010A/020A/040 are offered in 32-lead
PLCC and 32-lead TSOP packages. A 600 mil, 32-pin PDIP is also available. See Figures 2, 3, and 4
for pin assignments.
©2011 Silicon Storage Technology, Inc.
DS25022A
2
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
Block Diagram
X-Decoder
Memory Address
SuperFlash
Memory
Address Buffers Latches
Y-Decoder
CE#
OE#
Control Logic
I/O Buffers and Data Latches
WE#
DQ7 - DQ0
1147 B1.2
Figure 1: Functional Block Diagram
©2011 Silicon Storage Technology, Inc.
DS25022A
3
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
A4
A3
A17
WE#
VDD
A18
A16
A15
A12
A17
A4
WE#
A5
NC
A5
WE#
A5
VDD
6
VDD
A6
NC
A6
A16
A6
NC
5
A16
A7
A15
A7
A15
A7
A12
SST39SF020A
SST39SF010A
SST39SF040 SST39SF020A SST39SF010A
A12
SST39SF040
Pin Assignment
4
3
2
1
32 31 30
29
SST39SF010A SST39SF020A
SST39SF040
A14
A14
28
A13
A13
A13
7
27
A8
A8
A8
A4
8
26
A9
A9
A9
A3
A3
9
25
A11
A11
A11
A2
A2
A2
10
24
OE#
OE#
OE#
A1
A1
A1
11
23
A10
A10
A10
A0
A0
A0
12
22
CE#
CE#
CE#
DQ0
DQ0
DQ0
13
21
14 15 16 17 18 19 20
DQ7
DQ7
DQ7
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
DQ2
VSS
DQ3
DQ4
DQ5
DQ6
32-lead PLCC
Top View
DQ1
SST39SF040
SST39SF020A SST39SF010A
A14
1147 32-plcc P2.4
Figure 2: Pin Assignments for 32-lead PLCC
©2011 Silicon Storage Technology, Inc.
DS25022A
4
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
SST39SF040 SST39SF020A
A11
A9
A8
A13
A14
A17
WE#
VDD
A18
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
A17
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
SST39SF010A
A11
A9
A8
A13
A14
NC
WE#
VDD
NC
A16
A15
A12
A7
A6
A5
A4
SST39SF010A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Standard Pinout
Top View
Die Up
SST39SF020A
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
SST39SF040
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
1147 32-tsop P1.1
Figure 3: Pin Assignments for 32-lead TSOP (8mm x 14mm)
SST39SF040 SST39SF020A SST39SF010A
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
32-pin
6
PDIP
7
8 Top View
9
10
11
12
13
14
15
16
SST39SF010A SST39SF020A
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
SST39SF040
VDD
WE#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
1147 32-pdip P3.2
Figure 4: Pin Assignments for 32-pin PDIP
©2011 Silicon Storage Technology, Inc.
DS25022A
5
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
Table 1: Pin Description
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During Sector-Erase AMS-A12 address lines will select the sector.
DQ7-DQ0
Data Input/output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable
To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
VDD
Power Supply
To provide 5.0V supply (4.5-5.5V)
VSS
Ground
NC
No Connection
Unconnected pins.
T1.2 25022
1. AMS = Most significant address
AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
©2011 Silicon Storage Technology, Inc.
DS25022A
6
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
Device Operation
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39SF010A/020A/040 is controlled by CE# and OE#, both have to be
low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high,
the chip is deselected and only standby power is consumed. OE# is the output control and is used to
gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is
high. Refer to the Read cycle timing diagram (Figure 5) for further details.
Byte-Program Operation
The SST39SF010A/020A/040 are programmed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps.
The first step is the three-byte load sequence for Software Data Protection. The second step is to load
byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either
CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated
after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once
initiated, will be completed, within 20 µs. See Figures 6 and 7 for WE# and CE# controlled Program
operation timing diagrams and Figure 16 for flowcharts. During the Program operation, the only valid
reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The
sector architecture is based on uniform sector size of 4 KByte. The Sector-Erase operation is initiated
by executing a six-byte command load sequence for Software Data Protection with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling
edge of the sixth WE# pulse, while the command (30H) is latched on the rising edge of the sixth WE#
pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 10 for timing waveforms. Any commands written during the Sector-Erase operation will be ignored.
Chip-Erase Operation
The SST39SF010A/020A/040 provide Chip-Erase operation, which allows the user to erase the entire
memory array to the “1s” state. This is useful when the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six- byte Software Data Protection command
sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal
Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the
internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 11 for timing diagram, and Figure 19 for the flowchart. Any commands written
during the Chip-Erase operation will be ignored.
©2011 Silicon Storage Technology, Inc.
DS25022A
7
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
Write Operation Status Detection
The SST39SF010A/020A/040 provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes
two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled
after the rising edge of WE# which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the SST39SF010A/020A/040 are in the internal Program operation, any attempt to read DQ7 will
produce the complement of the true data. Once the Program operation is completed, DQ7 will produce
true data. Note that even though DQ7 may have valid data immediately following the completion of an
internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data
bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase
operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed,
DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for
Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth
WE# (or CE#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 17 for a flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce
alternating 0s and 1s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is
completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid
after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase,
the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for Toggle Bit timing diagram and Figure 17 for a flowchart.
Data Protection
The SST39SF010A/020A/040 provide both hardware and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
©2011 Silicon Storage Technology, Inc.
DS25022A
8
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
Software Data Protection (SDP)
The SST39SF010A/020A/040 provide the JEDEC approved Software Data Protection scheme for all
data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a
series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation,
providing optimal protection from inadvertent Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of six-byte load sequence. The
SST39SF010A/020A/040 devices are shipped with the Software Data Protection permanently
enabled. See Table 4 for the specific software command codes. During SDP command sequence,
invalid commands will abort the device to read mode, within TRC.
Product Identification
The Product Identification mode identifies the device as the SST39SF040, SST39SF010A, or
SST39SF020A and manufacturer as SST. This mode may be accessed by software operations. Users
may wish to use the software Product Identification operation to identify the part (i.e., using the device
ID) when using multiple manufacturers in the same socket. For details, Table 4 for software operation,
Figure 12 for the software ID entry and read timing diagram and Figure 18 for the ID entry command
sequence flowchart.
Table 2: Product Identification
Address
Data
0000H
BFH
SST39SF010A
0001H
B5H
SST39SF020A
0001H
B6H
SST39SF040
0001H
B7H
Manufacturer’s ID
Device ID
T2.2 25022
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the Exit ID command sequence, which returns the device to the Read
operation. Please note that the software reset command is ignored during an internal Program or
Erase operation. See Table 4 for software command codes, Figure 13 for timing waveform and Figure
18 for a flowchart.
©2011 Silicon Storage Technology, Inc.
DS25022A
9
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
Operations
Table 3: Operation Modes Selection
Mode
CE#
OE#
WE#
Read
Program
DQ
Address
VIL
VIL
VIL
VIH
VIH
DOUT
AIN
VIL
DIN
AIN
X1
Sector address, XXH for Chip-Erase
High Z
X
Erase
VIL
VIH
VIL
Standby
VIH
X
X
X
VIL
X
High Z/ DOUT
X
X
X
VIH
High Z/ DOUT
X
VIL
VIL
VIH
Write Inhibit
Product Identification
Software Mode
See Table 4
T3.3 25022
1. X can be VIL or VIH, but no other value.
Table 4: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1
Addr1
Addr1
Data
Addr1
Data
Addr1
Data
Addr1
Data
BA2
Data
Data
Data
Byte-Program
5555H AAH 2AAAH
55H
5555H
A0H
Sector-Erase
5555H AAH 2AAAH
55H
5555H
80H
5555H AAH 2AAAH
55H
SAX3
30H
Chip-Erase
5555H AAH 2AAAH
55H
5555H
80H
5555H AAH 2AAAH
55H
5555H
10H
5555H AAH 2AAAH
55H
5555H
90H
55H
5555H
F0H
Software ID
Entry4,5
Software ID Exit6
Software ID Exit6
XXH
F0H
5555H AAH 2AAAH
T4.2 25022
1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence.
AMS = Most significant address
AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
2. BA = Program Byte address
3. SAX for Sector-Erase; uses AMS-A12 address lines
4. The device does not remain in Software Product ID mode if powered down.
5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,
SST39SF010A Device ID = B5H, is read with A0 = 1
SST39SF020A Device ID = B6H, is read with A0 = 1
SST39SF040 Device ID = B7H, is read with A0 = 1
6. Both Software ID Exit operations are equivalent
©2011 Silicon Storage Technology, Inc.
DS25022A
10
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute
Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these conditions or conditions greater than those defined in the
operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Through Hold Lead Soldering Temperature (10 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
Table 5: Operating Range
Range
Ambient Temp
Commercial
Industrial
VDD
0°C to +70°C
4.5-5.5V
-40°C to +85°C
4.5-5.5V
T5.1 25022
Table 6: AC Conditions of Test1
Input Rise/Fall Time
Output Load
5ns
CL = 30 pF for 45 ns
CL = 100 pF for 70 ns
T6.1 25022
1. See Figures 14 and 15
©2011 Silicon Storage Technology, Inc.
DS25022A
11
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
Table 7: DC Operating Characteristics VDD = 4.5-5.5V1
Limits
Symbol
Parameter
IDD
Power Supply Current
Min
Max
Units
Test Conditions
Address input=VILT/VIHT, at f=1/TRC Min
VDD=VDD Max
Read2
25
mA
CE#=VIL, OE#=WE#=VIH, all I/Os open
Program and Erase
35
mA
CE#=WE#=VIL, OE#=VIH
ISB1
Standby VDD Current
(TTL input)
3
mA
CE#=VIH, VDD=VDD Max
ISB2
Standby VDD Current
(CMOS input)
100
µA
CE#=VIHC, VDD=VDD Max
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
10
µA
VOUT=GND to VDD, VDD=VDD Max
VIL
Input Low Voltage
VIH
Input High Voltage
VIHC
Input High Voltage (CMOS)
VOL
Output Low Voltage
VOH
Output High Voltage
0.8
2.0
VDD-0.3
0.4
2.4
V
VDD=VDD Min
V
VDD=VDD Max
V
VDD=VDD Max
V
IOL=2.1 mA, VDD=VDD Min
V
IOH=-400 µA, VDD=VDD Min
T7.10 25022
1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C
(room temperature), and VDD = 5V for SF devices. Not 100% tested.
2. Values are for 70 ns conditions. See the Dat Shea
t e
S
application note for further information.
Table 8: Recommended System Power-up Timings
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100
µs
Power-up to Program/Erase Operation
100
µs
TPU-WRITE
1
T8.1 25022
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 9: Capacitance (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
CI/O
1
CIN1
Description
Test Condition
Maximum
I/O Pin Capacitance
VI/O = 0V
12 pF
Input Capacitance
VIN = 0V
6 pF
T9.0 25022
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 10:Reliability Characteristics
Symbol
NEND
TDR1
ILTH
1
1,2
Parameter
Minimum Specification
Units
Test Method
Endurance
10,000
Cycles
JEDEC Standard A117
100
Years
JEDEC Standard A103
100 + IDD
mA
JEDEC Standard 78
Data Retention
Latch Up
T10.2 25022
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would
result in a higher minimum specification.
©2011 Silicon Storage Technology, Inc.
DS25022A
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1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
AC Characteristics
Table 11:Read Cycle Timing Parameters VDD = 4.5-5.5V
SST39SF010A/020A/040-45
Symbol Parameter
Min
Read Cycle Time
TRC
Max
45
SST39SF010A/020A/040-70
Min
Max
Units
70
ns
TCE
Chip Enable Access Time
45
70
ns
TAA
Address Access Time
45
70
ns
35
ns
TOE
Output Enable Access Time
TCLZ1
CE# Low to Active Output
0
OE# Low to Active Output
0
TOLZ
1
TCHZ1
30
CE# High to High-Z Output
TOHZ1
OE# High to High-Z Output
TOH1
Output Hold from Address Change
0
ns
0
ns
15
25
15
0
ns
25
ns
0
ns
T11.4 25022
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
Table 12:Program/Erase Cycle Timing Parameters
Symbol
Parameter
TBP
Byte-Program Time
Min
Max
Units
20
µs
TAS
Address Setup Time
0
ns
TAH
Address Hold Time
30
ns
TCS
WE# and CE# Setup Time
0
ns
TCH
WE# and CE# Hold Time
0
ns
TOES
OE# High Setup Time
0
ns
TOEH
OE# High Hold Time
10
ns
TCP
CE# Pulse Width
40
ns
TWP
WE# Pulse Width
40
ns
TWPH1
WE# Pulse Width High
30
ns
TCPH1
CE# Pulse Width High
30
ns
TDS
Data Setup Time
40
ns
TDH1
Data Hold Time
0
ns
TIDA1
Software ID Access and Exit Time
150
ns
TSE
Sector-Erase
25
ms
TSCE
Chip-Erase
100
ms
T12.1 25022
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
©2011 Silicon Storage Technology, Inc.
DS25022A
13
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
TRC
TAA
ADDRESS AMS-0
TCE
CE#
TOE
OE#
TOHZ
TOLZ
VIH
WE#
TOH
TCLZ
DQ7-0
HIGH-Z
TCHZ
DATA VALID
HIGH-Z
DATA VALID
1147 F03.1
Note: AMS = Most significant address
AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
Figure 5: Read Cycle Timing Diagram
INTERNAL PROGRAM OPERATION STARTS
TBP
ADDRESS AMS-0
5555
2AAA
5555
ADDR
TAH
TDH
TWP
WE#
TAS
TDS
TWPH
OE#
TCH
CE#
TCS
DQ7-0
AA
55
A0
DATA
SW0
SW1
SW2
BYTE
(ADDR/DATA)
1147 F04.1
Note: AMS = Most significant address
AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
Figure 6: WE# Controlled Program Cycle Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25022A
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07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
TBP
ADDRESS AMS-0
5555
TAH
2AAA
5555
ADDR
TDH
TCP
CE#
TDS
TCPH
TAS
OE#
TCH
WE#
TCS
DQ7-0
AA
SW0
55
A0
SW1
SW2
DATA
BYTE
(ADDR/DATA)
1147 F05.1
Note: AMS = Most significant address
AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
Figure 7: CE# Controlled Program Cycle Timing Diagram
ADDRESS AMS-0
TCE
CE#
TOES
TOEH
OE#
TOE
WE#
DQ7
D
D#
D#
D
1147 F06.1
Note: AMS = Most significant address
AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
Figure 8: Data# Polling Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25022A
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07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
ADDRESS AMS-0
TCE
CE#
TOEH
TOES
TOE
OE#
WE#
Note
DQ6
TWO READ CYCLES
WITH SAME OUTPUTS
1147 F07.1
Note: Toggled bit output is always high first.
AMS = Most significant address
AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
Figure 9: Toggle Bit Timing Diagram
TSE
SIX-BYTE CODE FOR SECTOR-ERASE
ADDRESS AMS-0
5555
2AAA
5555
5555
2AAA
SAX
CE#
OE#
TWP
WE#
DQ7-0
AA
55
80
AA
55
30
SW0
SW1
SW2
SW3
SW4
SW5
1147 F08.1
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable
as long as minimum timings are met. (See Table 10)
SAXX = Sector Address
Toggled bit output is always high first.
AMS = Most significant address
AMS = A16 for SST39SF010A, A17 for SST39SF020A, and A18 for SST39SF040
Figure 10:WE# Controlled Sector-Erase Timing Diagram
©2011 Silicon Storage Technology, Inc.
DS25022A
16
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
TSCE
SIX-BYTE CODE FOR CHIP-ERASE
ADDRESS AMS-0
5555
2AAA
5555
5555
2AAA
5555
CE#
OE#
TWP
WE#
DQ7-0
AA
SW0
55
80
AA
55
10
SW1
SW2
SW3
SW4
SW5
1147 F17.1
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchangeable
as long as minimum timings are met. (See Table 10)
SAXX = Sector Address
Toggled bit output is always high first.
AMS = Most significant address
Figure 11:WE# Controlled Chip-Erase Timing Diagram
Three-byte Sequence for
Software ID Entry
ADDRESS A14-0
5555
2AAA
5555
0000
0001
CE#
OE#
TIDA
TWP
WE#
TWPH
DQ7-0
AA
55
SW0
SW1
TAA
90
BF
Device ID
SW2
1147 F09.2
Note: Device ID = B5H for SST39SF010A, B6H for SST39SF020A, and B7H for SST39SF040
Figure 12:Software ID Entry and Read
©2011 Silicon Storage Technology, Inc.
DS25022A
17
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
ADDRESS A14-0
5555
DQ7-0
2AAA
5555
AA
55
F0
TIDA
CE#
OE#
TWP
WE#
TWHP
SW0
SW1
SW2
1147 F10.0
Figure 13:Software ID Exit and Reset
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
1147 F11.1
AC test inputs are driven at VIHT (3.0V) for a logic “1” and VILT (0V) for a logic “0”.
Measurement reference points for inputs and outputs are VIT (1.5V) and VOT (1.5V). Input rise
and fall times (10%  90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
Figure 14:AC Input/Output Reference Waveforms
VDD
TO TESTER
RL HIGH
TO DUT
RL LOW
CL
1147 F12.0
Figure 15:A Test Load Example
©2011 Silicon Storage Technology, Inc.
DS25022A
18
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
Start
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: A0H
Address: 5555H
Load Byte
Address/Byte
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
1147 F13.1
Figure 16:Byte-Program Algorithm
©2011 Silicon Storage Technology, Inc.
DS25022A
19
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
Internal Timer
Toggle Bit
Data# Polling
Byte
Program/Erase
Initiated
Byte
Program/Erase
Initiated
Byte
Program/Erase
Initiated
Read byte
Read DQ7
Wait TBP,
TSCE, or TSE
Read same
byte
Program/Erase
Completed
No
Is DQ7 =
true data
Yes
No
Does DQ6
match
Program/Erase
Completed
Yes
Program/Erase
Completed
1147 F14.0
Figure 17:Wait Options
©2011 Silicon Storage Technology, Inc.
DS25022A
20
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
Software Product ID Entry
Command Sequence
Software Product ID Exit
Reset Command Sequence
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: F0H
Address: XXH
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Wait TIDA
Load data: 90H
Address: 5555H
Load data: F0H
Address: 5555H
Return to normal
operation
Wait TIDA
Wait TIDA
Read Software ID
Return to normal
operation
1147 F15.1
Figure 18:Software Product Command Flowcharts
©2011 Silicon Storage Technology, Inc.
DS25022A
21
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
Chip-Erase
Command Sequence
Sector-Erase
Command Sequence
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Load data: 80H
Address: 5555H
Load data: 80H
Address: 5555H
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Load data: 10H
Address: 5555H
Load data: 30H
Address: SAX
Wait TSCE
Wait TSE
Chip erased
to FFH
Sector erased
to FFH
1147 F16.1
Figure 19:Erase Command Sequence
©2011 Silicon Storage Technology, Inc.
DS25022A
22
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
Product Ordering Information
SST
39 SF
XX XX
010A XXXX -
70 XX -
4C
XX
-
NHE
XXX
Environmental Attribute
E1 = non-Pb
Package Modifier
H = 32 pins or leads
Package Type
N = PLCC
P = PDIP
W = TSOP (type 1, die up, 8mm x 14mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
45 = 45 ns
55 = 55 ns
70 = 70 ns
Version
A = Special Feature Version
Device Density
040 = 4 Mbit
020 = 2 Mbit
010 = 1 Mbit
Voltage
S = 4.5-5.5V
Product Series
39 = Multi-Purpose Flash
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
©2011 Silicon Storage Technology, Inc.
DS25022A
23
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
A Microchip Technology Company
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
Valid combinations for SST39SF010A
SST39SF010A-45-4C-NHE
SST39SF010A-45-4C-WHE
SST39SF010A-55-4C-NHE
SST39SF010A-55-4C-WHE
SST39SF010A-70-4C-NHE
SST39SF010A-70-4C-WHE
SST39SF010A-45-4I-NHE
SST39SF010A-45-4I-WHE
SST39SF010A-55-4I-NHE
SST39SF010A-55-4I-WHE
SST39SF010A-70-4I-NHE
SST39SF010A-70-4I-WHE
SST39SF010A-70-4C-PHE
Valid combinations for SST39SF020A
SST39SF020A-45-4C-NHE
SST39SF020A-45-4C-WHE
SST39SF020A-55-4C-NHE
SST39SF020A-55-4C-WHE
SST39SF020A-70-4C-NHE
SST39SF020A-70-4C-WHE
SST39SF020A-45-4I-NHE
SST39SF020A-45-5I-WHE
SST39SF020A-55-4I-NHE
SST39SF020A-55-5I-WHE
SST39SF020A-70-4I-NHE
SST39SF020A-70-4I-WHE
SST39SF020A-70-4C-PHE
Valid combinations for SST39SF040
SST39SF040-45-4C-NHE
SST39SF040-45-4C-WHE
SST39SF040-55-4C-NHE
SST39SF040-55-4C-WHE
SST39SF040-70-4C-NHE
SST39SF040-70-4C-WHE
SST39SF040-45-4I-NHE
SST39SF040-45-4I-WHE
SST39SF040-55-4I-NHE
SST39SF040-55-4I-WHE
SST39SF040-70-4I-NHE
SST39SF040-70-4I-WHE
SST39SF040-70-4C-PHE
Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST
sales representative to confirm availability of valid combinations and to determine availability of new combinations.
©2011 Silicon Storage Technology, Inc.
DS25022A
24
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
Packaging Diagrams
TOP VIEW
Optional
Pin #1
Identifier .048
.042
.495
.485
.453
.447
2
1
32
SIDE VIEW
.112
.106
.020 R. .029 x 30°
MAX. .023
.040 R.
.030
.042
.048
.595 .553
.585 .547
BOTTOM VIEW
.021
.013
.400 .530
BSC .490
.032
.026
.050
BSC
.015 Min.
.095
.075
.050
BSC
.140
.125
.032
.026
Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches.
32-plcc-NH-3
4. Coplanarity: 4 mils.
Figure 20:32-lead Plastic Lead Chip Carrier (PLCC)
SST Package Code: NH
©2011 Silicon Storage Technology, Inc.
DS25022A
25
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
1.05
0.95
Pin # 1 Identifier
0.50
BSC
8.10
7.90
0.27
0.17
0.15
0.05
12.50
12.30
DETAIL
1.20
max.
0.70
0.50
14.20
13.80
0°- 5°
0.70
0.50
Note:
1. Complies with JEDEC publication 95 MO-142 BA dimensions,
although some dimensions may be more stringent.
32-tsop-WH-7
1mm
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
Figure 21:32-lead Thin Small Outline Package (TSOP) 8mm x 14mm
SST Package Code: WH
©2011 Silicon Storage Technology, Inc.
DS25022A
26
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
32
CL
Pin #1 Identifier
1
1.655
1.645
.075
.065
7°
4 PLCS.
Base
Plane
Seating
Plane
.625
.600
.550
.530
.200
.170
.050
.015
.080
.070
.065
.045
.022
.016
.100 BSC
.150
.120
0°
15°
.012
.008
.600 BSC
Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in inches (max/min).
3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches.
32-pdip-PH-3
Figure 22:32-pin Plastic Dual In-line Pins (PDIP)
SST Package Code: PH
©2011 Silicon Storage Technology, Inc.
DS25022A
27
07/11
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
A Microchip Technology Company
Data Sheet
Table 13:Revision History
Revision
02
03
•
•
•
•
•
04
•
•
05
06
07
08
09
A
•
•
•
Description
Date
2002 Data Book
Changes to Table 7 on page 12
Added footnote for MPF power usage and Typical conditions
Clarified the Test Conditions for Power Supply Current and Read
parameters
Clarified IDD Write to be Program and Erase
May 2002
Document status changed from “Preliminary Specification” to “Data
Sheet”
Changed IDD Program and Erase max values from 25 to 35 in Table 7
on page 12
2004 Data Book
Added non-Pb MPNs and removed footnote (See page 24)
Corrected Revision History for Version 04:
IDD max value was incorrectly stated as 30 mA instead of 35 mA
Oct 2003
Mar 2003
•
•
Removed leaded parts from valid combinations. See PSN-D0PB0001
Changed endurance from 10,000 to 100,000 in Product Description,
page 1
•
•
•
•
•
•
End of Life for all 45 ns valid combinations. See S71147(02).
Added replacement 55 ns valid combinations
All 45 ns parts reinstated.
Applied new document format
Released document under letter revision system
Updated spec number from S71147 to DS25022
Nov 2003
Aug 2004
Mar 2009
Sep 2009
Jan 2010
Jul 2011
ISBN:978-1-61341-377-7
© 2011 Silicon Storage Technology, Inc–a Microchip Technology Company. All rights reserved.
SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and
registered trademarks mentioned herein are the property of their respective owners.
Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current
package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.
Memory sizes denote raw storage capacity; actual usable capacity may be less.
SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of
Sale.
For sales office locations and information, please see www.microchip.com.
Silicon Storage Technology, Inc.
A Microchip Technology Company
www.microchip.com
©2011 Silicon Storage Technology, Inc.
DS25022A
28
07/11
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