Atmel AT42QT1070 Seven-channel QTouch® Touch Sensor IC DATASHEET Features Configurations: Comms mode Standalone mode Number of Keys: Comms mode: 1 – 7 keys (or 1 – 6 keys plus a Guard Channel) Standalone mode: 1 – 4 keys plus a fixed Guard Channel on key 0 Number of I/O Lines: Standalone mode: 5 outputs Technology: Patented spread-spectrum charge-transfer Key Outline Sizes: 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and shapes possible Layers Required: One Electrode Materials: Etched copper; Silver; Carbon; Indium Tin Oxide (ITO) Panel Materials: Plastic; Glass; Composites; Painted surfaces (low particle density metallic paints possible Panel Thickness: Up to 10 mm glass; Up to 5 mm plastic (electrode size dependent) Key Sensitivity: Comms mode: individually settable via simple commands over I2C-compatible interface Standalone mode: settings are fixed Interface: I2C-compatible slave mode (400 kHz). Discrete detection outputs Signal Processing: Self-calibration Auto drift compensation Noise filtering Adjacent Key Suppression® (AKS®) – up to three groups possible Power: 1.8 V – 5.5 V Package: 14-pin SOIC RoHS compliant IC 20-pin VQFN RoHS compliant IC 9596C–AT42–05/2013 1. Pinouts and Schematics 1.1 Pinout Configuration – Comms Mode (14-pin SOIC) 1.2 VDD 1 14 VSS MODE (Vss) 2 13 KEY0 SDA 3 12 KEY1 RESET 4 11 KEY2 CHANGE 5 10 KEY3 SCL 6 9 KEY4 KEY6 7 8 KEY5 QT1070 Pinout Configuration – Standalone Mode (14-pin SOIC) VDD 1 MODE (Vdd) 2 QT1070 14 VSS 13 KEY0 12 KEY1 OUT0 3 RESET 4 11 KEY2 OUT4 5 10 KEY3 OUT3 6 9 KEY4 OUT2 7 8 OUT1 AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 2 NC NC KEY5 KEY6 Pinout Configuration – Comms Mode (20-pin VQFN) NC 20 19 18 17 16 KEY4 1 15 SCL KEY3 2 14 CHANGE KEY2 3 13 RESET KEY1 4 12 SDA KEY0 5 11 10 9 VDD 8 NC NC NC OUT1 OUT2 Pinout Configuration – Standalone Mode (20-pin VQFN) 20 19 18 17 16 KEY4 1 15 OUT3 KEY3 2 14 OUT4 KEY2 3 13 RESET KEY1 4 12 OUT0 KEY0 5 11 10 7 8 9 VSS VDD MODE (Vdd) NC 6 NC QT1070 NC 1.4 7 VSS NC 6 MODE (Vss) NC QT1070 NC 1.3 AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 3 1.5 Pin Descriptions Table 1-1. Pin Listings (14-pin SOIC) Pin Name (Comms Mode) Name (Standalone Mode) Type 1 VDD VDD P If Unused, Connect To... Description Power – Mode selection pin 2 MODE MODE I – Comms Mode – connect to Vss Standalone Mode – connect to Vdd Comms Mode – I2C data line 3 SDA OUT0 OD 4 RESET RESET I Standalone Mode – open drain output for guard channel Open RESET – has internal pull-up 60 k resistor Open CHANGE line for controlling the communications flow 5 CHANGE OUT4 OD Comms Mode – connect to CHANGE line Open Standalone Mode – connect to output I OD Comms Mode – connect to I2C clock 6 SCL OUT3 OD 7 KEY6 OUT2 O/OD 8 KEY5 OUT1 O/OD 9 KEY4 KEY4 O Key 4 Open 10 KEY3 KEY3 O Key 3 Open 11 KEY2 KEY2 O Key 2 Open 12 KEY1 KEY1 O Key 1 Open 13 KEY0 KEY0 O Key 0 Open 14 VSS VSS P Ground Input only Open drain output O P Standalone Mode – connect to output Comms Mode – connect to Key 6 Standalone Mode – connect to output Comms Mode – connect to Key 5 Standalone Mode – connect to output Open Open Open – Output only, push-pull Ground or power AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 4 Table 1-2. Pin Listings (20-pin VQFN) Pin Name (Comms Mode) Name (Standalone Mode) If Unused, Connect To... Type 1 KEY4 KEY4 O Key 4 Open 2 KEY3 KEY3 O Key 3 Open 3 KEY2 KEY2 O Key 2 Open 4 KEY1 KEY1 O Key 1 Open 5 KEY0 KEY0 O Key 0 Open 6 NC NC – Not connected – 7 NC NC – Not connected – 8 VSS VSS P Ground – 9 VDD VDD P Power – 10 NC NC – Not connected – Description Mode selection pin 11 MODE MODE I – Comms Mode – connect to Vss Standalone Mode – connect to Vdd Comms Mode – I2C data line 12 SDA OUT0 OD 13 RESET RESET I Standalone Mode – open drain output for guard channel Open RESET – has internal pull-up 60 k resistor Open CHANGE line for controlling the communications flow 14 CHANGE OUT4 OD Comms Mode – connect to CHANGE line Open Standalone Mode – connects to output I OD Comms Mode – connect to I2C clock 15 SCL OUT3 OD 16 KEY6 OUT2 O/OD 17 KEY5 OUT1 O/OD 18 NC NC – Not connected – 19 NC NC – Not connected – 20 NC NC – Not connected – Input only Open drain output O P Standalone Mode – connect to output Comms Mode – connect to Key 6 Standalone Mode – connect to output Comms Mode – connect to Key 5 Standalone Mode – connect to output Open Open Open Output only, push-pull Ground or power AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 5 1.6 Schematics Figure 1-1. Typical Circuit – Comms (14-pin SOIC) Vdd C1 Vdd 1 Vss RSCL Vdd Vdd RSDA RCHG SCL QT1070 RRST 6 7 Rs6 8 Rs5 9 Rs4 10 Rs3 11 Rs2 12 Rs1 13 Rs0 KEY6 KEY5 SDA 3 CHANGE 5 RESET 4 SDA KEY4 CHANGE KEY3 RESET KEY2 KEY1 KEY0 SCL K6 K5 K4 K3 K2 K1 K0 MODE (Vss) Vss 14 2 Vss Figure 1-2. Typical Circuit – Standalone (14-pin SOIC) Vdd C1 OUTPUTS OUTPUTS 2 COUT0 and 4 are optional MODE (Vdd) COUT0 QT1070 COUT4 Vdd ROUT0 Vss 3 R1 ROUT4 RESET 1 5 4 Vss COUT1, 2 and 3 are optional COUT3 Vdd OUT3 6 ROUT3 OUT2 7 ROUT2 OUT1 8 ROUT1 9 Rs4 OUT0 KEY4 OUT4 KEY3 10 Rs3 RESET KEY2 11 Rs2 KEY1 12 Rs1 KEY0 13 Rs0 COUT2 COUT1 Vss K4 K3 K2 K1 K0 Vss 14 Vss AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 6 Figure 1-3. Typical Circuit – Comms (20-pin VQFN) Vdd C1 9 Vss Vdd Vdd Vdd RCHG RSDA RSCL QT1070 RRST SCL SDA 12 CHANGE 14 RESET 13 6 7 10 18 19 20 SDA KEY6 CHANGE KEY5 RESET KEY4 N/C KEY3 N/C KEY2 N/C KEY1 N/C KEY0 15 16 Rs6 17 Rs5 1 Rs4 K6 K5 K4 2 Rs3 3 Rs2 4 Rs1 5 Rs0 K3 K2 K1 K0 N/C N/C Vss MODE (Vss) 8 11 Vss Figure 1-4. Typical Circuit – Standalone (20-pin VQFN) Vdd C1 OUTPUTS OUTPUTS 11 COUT0 and 4 are optional ROUT0 Vdd 9 MODE (Vdd) COUT0 15 RsOUT3 16 RsOUT2 17 RLOUT1 KEY4 1 Rs4 OUT4 KEY3 2 Rs3 12 RESET RESET KEY2 3 Rs2 KEY1 4 Rs1 KEY0 5 Rs0 OUT2 OUT1 Vss ROUT4 OUT3 14 13 6 7 10 18 19 20 OUT0 N/C N/C COUT1, 2 and 3 are optional COUT3 Vdd QT1070 COUT4 R1 Vss COUT2 COUT1 Vss K4 K3 K2 K1 K0 N/C N/C N/C N/C Vss 8 Vss For component values in Figure 1-1, 1-2, 1-3, and 1-4, check the following sections: Section 3.1 on page 12: Series resistors (Rs0 – Rs6 for comms mode and Rs0 – Rs4 for standalone mode) Section 3.2 on page 12: LED traces Section 3.4 on page 12: Power Supply (voltage levels) Section 4.4 on page 14: SDA, SCL pull-up resistors AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 7 2. Overview 2.1 Introduction The AT42QT1070 (QT1070) is a digital burst mode charge-transfer (QT™) capacitive sensor driver. The device can sense from one to seven keys, dependent on mode. The QT1070 includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions, and the outputs are fully debounced. Only a few external parts are required for operation and no external Cs capacitors are required. The QT1070 modulates its bursts in a spread-spectrum fashion in order to heavily suppress the effects of external noise, and to suppress RF emissions. The QT1070 uses a dual-pulse method of acquisition. This provides greater noise immunity and eliminates the need for external sampling capacitors, allowing touch sensing using a single pin. 2.2 Modes 2.2.1 Comms Mode The QT1070 can operate in comms mode where a host can communicate with the device via an I2C bus. This allows the user to configure settings for Threshold, Adjacent Key Suppression (AKS), Detect Integrator, Low Power (LP) Mode, Guard Channel and Max Time On for keys. 2.2.2 Standalone Mode The QT1070 can operate in a standalone mode where an I2C interface is not required. To enter standalone mode, connect the Mode pin to Vdd before powering up the QT1070. In standalone mode, the start-up values are hard coded in firmware and cannot be changed. The default start-up values are used. This means that key detection is reported via their respective IOs. The Guard channel feature is automatically implemented on key 0 in standalone mode. This means that this channel gets priority over all other keys going into touch. 2.3 Keys Dependent on mode, the QT1070 can have a minimum of one key and a maximum of seven keys. These can be constructed in different shapes and sizes. See “Features” on page 1 for the recommended dimensions. Comms mode – 1 to 7 keys (or 1 to 6 keys plus Guard Channel) Standalone mode – 1 to 4 keys plus a Guard Channel Unused keys should be disabled by setting the averaging factor to zero (see Section 5.9 on page 18). The status register can be read to determine the touch status of the corresponding key. It is recommended using the open-drain CHANGE line to detect when a change of status has occurred. 2.4 Input/Output (IO) Lines There are no IO lines in comms mode. In Standalone mode pins OUT0 – OUT4 can be used as open drain outputs for driving LEDs. 2.5 Acquisition/Low Power Mode (LP) There are 255 different acquisition times possible. These are controlled via the LP mode byte (see Section 5.11 on page 19) which can be written to via I2C communication. LP mode controls the intervals between acquisition measurements. Longer intervals consume lower power but have an increased response time. During calibration, touch and during the detect integrator (DI) period, the LP mode is temporarily set to LP mode 1 for a faster response. AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 8 The QT1070 operation is based on a fixed cycle time of approximately 8 ms. The LP mode setting indicates how many of these periods exist per measurement cycle. For example, If LP mode = 1, there is an acquisition every cycle (8 ms). If LP mode = 3, there is an acquisition every 3 cycles (24 ms). If a high Averaging Factor (see Section 5.9 on page 18) setting is selected then the acquisition time may exceed 8 ms. LP settings above mode 32 (256 ms) result in slower thermal drift compensation and should be avoided in applications where fast thermal transients occur. 2.6 Adjacent Key Suppression (AKS) Technology The device includes the Atmel-patented Adjacent Key Suppression (AKS) technology, to allow the use of tightly spaced keys on a keypad with no loss of selectability by the user. There can be up to three AKS groups, implemented so that only one key in the group may be reported as being touched at any one time. Once a key in a particular AKS group is in detect no other key in that group can go into detect. Only when the key in detect goes out of detection can another key go into detect state. The keys which are members of the AKS groups can be set (see Section 5.9 on page 18). Keys outside the group may be in detect simultaneously. 2.7 CHANGE Line (Comms Mode Only) The CHANGE line is active low and signals when there is a change of state in the Detection or Input key status bytes. It is cleared (allowed to float high) when the host reads the status bytes. If the status bytes change back to their original state before the host has read the status bytes (for example, a touch followed by a release), the CHANGE line will be held low. In this case, a read to any memory location will clear the CHANGE line. The CHANGE line is open-drain and should be connected via a 47 k resistor to Vdd. It is necessary for minimum power operation as it ensures that the QT1070 can sleep for as long as possible. Communications wake up the QT1070 from sleep causing a higher power consumption if the part is randomly polled. Note: The CHANGE line is pulled low 100 ms after power-up or reset. 2.8 Types of Reset 2.8.1 External Reset An external reset logic line can be used if desired, fed into the RESET pin. However, under most conditions it is acceptable to tie RESET to Vdd. 2.8.2 Soft Reset The host can cause a device reset by writing a nonzero value to the RESET byte. This soft reset triggers the internal watchdog timer on a 125 ms interval. After 125 ms the device resets and wakes again. The device NACKs any attempts to communicate with it during the first 30 ms of its initialization period. 2.9 Calibration Writing a non-zero value to the calibration byte can force a recalibration at any time. This can be useful to clear out a stuck key condition after a prolonged period of uninterrupted detection. Note: A calibrate command clears all key status bits and the overflow bit (until it is checked on the next cycle). AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 9 2.10 Guard Channel A guard channel to help prevent false detection is available in both modes. This is fixed on key 0 for standalone mode and programmable for comms mode. Guard channel keys should be more sensitive than the other keys (physically bigger). Because the guard channel key is physically bigger it becomes more susceptible to noise so it has a higher Averaging Factor (see Section 5.9 on page 18) and a lower Threshold (see Section 5.8 on page 18) than the other keys. In standalone mode it has an Averaging Factor of 16 and a Threshold of 10 counts. A channel set as the guard channel (there can only be one) is prioritised when the filtering of keys going into detect is taking place. So if a normal key is filtering into touch (touch present but DI has not been reached) and the key set as the guard key begins filtering in, then the normal key’s filter is reset and the guard key filters in first. The guard channel is connected to a sensor pad which detects the presence of touch and overrides any output from the other keys. Figure 2-1. Guard Channel Example Guard channel 2.11 Signal Processing 2.11.1 Detect Threshold The device detects a touch when the signal has crossed a threshold level and remained there for a specified number of counts (see Section 5.10 on page 19). This can be altered on a key-by-key basis using the key threshold I2C commands. In standalone mode the detect threshold is set to a fixed value of 10 counts of change with respect to the internal reference level for the guard channel and 20 counts for the other four keys. The reference level has the ability to adjust itself slowly in accordance with the drift compensation mechanism. The drift mechanism will drift toward touch at a rate of 160 ms × 18 = 2.88 seconds and away from touch at a rate of 160 ms × 6 = 0.96 seconds. The 160 ms is based on 20 × 8 ms cycles. If the cycle time exceeds 8 ms then the overall times will be extended to match. 2.11.2 Detect Integrator The device features a fast detection integrator counter (DI filter), which acts to filter out noise at the small expense of a slower response time. The DI filter requires a programmable number of consecutive samples confirmed in detection before the key is declared to be touched. The minimum number for the DI filter is 2. Settings of 0 and 1 for the DI also default to 2. The DI is also implemented when a touch is removed. This uses the Fast Out DI option. When bit 5 of Address 53 is set the a key filters out with an integrator of 4. AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 10 2.11.3 Cx Limitations The recommended range for key capacitance Cx is 1 pF – 30 pF. Larger values of Cx will give reduced sensitivity. 2.11.4 Max On Duration If an object or material obstructs the sense pad the signal may rise enough to create a detection, preventing further operation. To prevent this, the sensor includes a timer which monitors detections. If a detection exceeds the timer setting the sensor performs a key recalibration. This is known as the Max On duration feature and is set to approximately 30 s in standalone mode. In comms mode this feature can be changed by setting a value in the range 1 – 255 (160 ms – 40,800 ms) in steps of 160 ms. A setting of 0 disables the Max On Duration recalibration feature. Note: If bit 4 of address 53 is clear then a recalibration of all keys occurs on Max On Duration, otherwise individual key recalibration occurs. 2.11.5 Positive Recalibration If a keys signal jumps in the negative direction (with respect to its reference) by more than the Positive Recalibration setting (4 counts), then a recalibration of that key takes place. 2.11.6 Drift Hold Time Drift Hold Time (DHT) is used to restrict drift on all keys while one or more keys are activated. DHT restricts the drifting on all keys until approximately four seconds after all touches have been removed. This feature is particularly useful in cases of high-density keypads where touching a key or hovering a finger over the keypad would cause untouched keys to drift, and therefore create a sensitivity shift, and ultimately inhibit touch detection. 2.11.7 Hysteresis Hysteresis is fixed at 12.5% of the Detect Threshold. When a key enters a detect state once the DI count has been reached, the NTHR value is changed by a small amount (12.5% of NTHR) in the direction away from touch. This is done to affect hysteresis and so makes it less likely a key will dither in and out of detect. NTHR is restored once the key drops out of detect.+ AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 11 3. Wiring and Parts 3.1 Rs Resistors Series resistors Rs (Rs0 – Rs6 for comms mode and Rs0 – Rs4 for standalone mode) are in line with the electrode connections and should be used to limit electrostatic discharge (ESD) currents and to suppress radio frequency interference (RFI). Series resistors are recommended for noise reduction. They should be approximately 4.7 k to 20 k each. 3.2 LED Traces and Other Switching Signals Digital switching signals near the sense lines induce transients into the acquired signals, deteriorating the signal-tonoise (SNR) performance of the device. Such signals should be routed away from the sensing traces and electrodes, or the design should be such that these lines are not switched during the course of signal acquisition (bursts). LED terminals which are multiplexed or switched into a floating state, and which are within, or physically very near, a key (even if on another nearby PCB) should be bypassed to either Vss or Vdd with at least a 10 nF capacitor. This is to suppress capacitive coupling effects which can induce false signal shifts. The bypass capacitor does not need to be next to the LED, in fact it can be quite distant. The bypass capacitor is noncritical and can be of any type. LED terminals which are constantly connected to Vss or Vdd do not need further bypassing. 3.3 PCB Cleanliness Modern no-clean flux is generally compatible with capacitive sensing circuits. CAUTION: If a PCB is reworked in any way, it is highly likely that the behavior of the no-clean flux will change. This can mean that the flux changes from an inert material to one that can absorb moisture and dramatically affect capacitive measurements due to additional leakage currents. If so, the circuit can become erratic and exhibit poor environmental stability. If a PCB is reworked in any way, clean it thoroughly to remove all traces of the flux residue around the capacitive sensor components. Dry it thoroughly before any further testing is conducted. 3.4 Power Supply See Section 6.2 on page 22 for the power supply range. If the power supply fluctuates slowly with temperature, the device tracks and compensates for these changes automatically with only minor changes in sensitivity. If the supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity anomalies or false detections. The usual power supply considerations with QT parts apply to the device. The power should be clean and come from a separate regulator if possible. However, this device is designed to minimize the effects of unstable power, and except in extreme conditions should not require a separate Low Dropout (LDO) regulator. CAUTION: A regulator IC shared with other logic can result in erratic operation and is not advised. A single ceramic 0.1 µF bypass capacitor, with short traces, should be placed very close to the power pins of the IC. Failure to do so can result in device oscillation, high current consumption and erratic operation. It is assumed that a larger bypass capacitor (such as1 µF) is somewhere else in the power circuit; for example, near the regulator. AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 12 4. I2C Communications (Comms Mode Only) 4.1 I2C Protocol 4.1.1 Protocol The I2C protocol is based around access to an address table (see Table 5-1 on page 15) and supports multibyte reads and writes. The maximum clock rate is 400 kHz. See Section A. on page 29 for an overview of I2C bus operation. 4.1.2 Signals The I2C interface requires two signals to operate: SDA - Serial Data SCL - Serial Clock A third line, CHANGE, is used to signal when the device has seen a change in the status byte: CHANGE: Open-drain, active low when any capacitive key has changed state since the last I2C read. After reading the two status bytes, this pin floats (high) again if it is pulled up with an external resistor. If the status bytes change back to their original state before the host has read the status bytes (for example, a touch followed by a release), the CHANGE line is held low. In this case, a read to any memory location clears the CHANGE line. 4.2 I2C Address There is one preset I2C address of 0x1B. This is not changeable. 4.3 Data Read/Write 4.3.1 Writing Data to the Device The sequence of events required to write data to the device is shown next. Host to Device S SLA+W Table 4-1. A MemAddress Device Tx to Host A Data A P Description of Write Data Bits Key Description S START condition SLA+W Slave address plus write bit A Acknowledge bit MemAddress Target memory address within device Data Data to be written P Stop condition 1. The host initiates the transfer by sending the START condition 2. The host follows this by sending the slave address of the device together with the WRITE bit. 3. The device sends an ACK. AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 13 4. The host then sends the memory address within the device it wishes to write to. 5. The device sends an ACK if the write address is in the range 0x00 – 0x7F, otherwise it sends a NACK. 6. The host transmits one or more data bytes; each is acknowledged by the device (unless trying to write to an invalid address). 7. If the host sends more than one data byte, they are written to consecutive memory addresses. 8. The device automatically increments the target memory address after writing each data byte. 9. After writing the last data byte, the host should send the STOP condition. Note: the host should not try to write to addresses outside the range 0x20 to 0x39 because this is the limit of the device internal memory address. 4.3.2 Reading Data From the Device The sequence of events required to read data from the device is shown next. Host to Device S SLA+W A Data 1 A Device Tx to Host MemAddress A P Data 2 S A SLA+R A Data n A P 1. The host initiates the transfer by sending the START condition 2. The host follows this by sending the slave address of the device together with the WRITE bit. 3. The device sends an ACK. 4. The host then sends the memory address within the device it wishes to read from. 5. The device sends an ACK if the address to be read from is less than 0x80 otherwise it sends a NACK). 6. The host must then send a STOP and a START condition followed by the slave address again but this time accompanied by the READ bit. Note: 7. Alternatively, instead of step 6 a repeated START can be sent so the host does not need to relinquish control of the bus. The device returns an ACK, followed by a data byte. 8. The host must return either an ACK or NACK. 9. Note: 4.4 1. If the host returns an ACK, the device subsequently transmits the data byte from the next address. Each time a data byte is transmitted, the device automatically increments the internal address. The device continues to return data bytes until the host responds with a NACK. 2. If the host returns a NACK, it should then terminate the transfer by issuing the STOP condition. The device resets the internal address to the location indicated by the memory address sent to it previously. Therefore, there is no need to send the memory address again when reading from the same location. Reading the 16-bit reference and signal values is not an automatic operation; reading the first byte of a 16bit value does not lock the other byte. As a result glitches in the reported value may be seen as values increase from 255 to 256, or decrease from 256 to 255. SDA, SCL The I2C bus transmits data and clock with SDA and SCL respectively. They are open-drain; that is I2C master and slave devices can only drive these lines low or leave them open. The termination resistors pull the line up to Vdd if no I2C device is pulling it down. The termination resistors commonly range from 1 k to 10 k and should be chosen so that the rise times on SDA and SCL meet the I2C specifications (1 µs maximum). Standalone mode: if I2C communications are not required, then standalone mode can be enabled by connecting the MODE pin to Vdd. See Section 2.4 on page 8 for more information. AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 14 5. Setups 5.1 Introduction The device calibrates and processes signals using a number of algorithms specifically designed to provide for high survivability in the face of adverse environmental challenges. User-defined Setups are employed to alter these algorithms to suit each application. These Setups are loaded into the device over the I 2 C serial interfaces. In standalone mode these settings are fixed to predetermined values. Table 5-1. Internal Register Address Allocation Address Use 0 Chip ID 1 Firmware Version 2 Detection status 3 Key status Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Major ID (= 2) Bit 1 Bit 0 R/W R Minor ID (= E) R Firmware version number CALIBRATE OVERFLOW – – – – – TOUCH R Reserved Key 6 Key 5 Key 4 Key 3 Key 2 Key 1 Key 0 R 4–5 Key signal 0 Key signal 0 (MSByte) – Key signal 0 (LSByte) R 6–7 Key signal 1 Key signal 1 (MSByte) – Key signal 1 (LSByte) R 8–9 Key signal 2 Key signal 2 (MSByte) – Key signal 2 (LSByte) R 10 – 11 Key signal 3 Key signal 3 (MSByte) – Key signal 3 (LSByte) R 12 – 13 Key signal 4 Key signal 4 (MSByte) – Key signal 4 (LSByte) R 14 – 15 Key signal 5 Key signal 5 (MSByte) – Key signal 5 (LSByte) R 16 – 17 Key signal 6 Key signal 6 (MSByte) – Key signal 6 (LSByte) R 18 – 19 Reference data 0 Reference data 0 (MSByte) – Reference data 0 (LSByte) R 20 – 21 Reference data 1 Reference data 1 (MSByte) – Reference data 1 (LSByte) R 22 – 23 Reference data 2 Reference data 2 (MSByte) – Reference data 2 (LSByte) R 24 – 25 Reference data 3 Reference data 3 (MSByte) – Reference data 3 (LSByte) R 26 – 27 Reference data 4 Reference data 4 (MSByte) – Reference data 4 (LSByte) R 28 – 29 Reference data 5 Reference data 5 (MSByte) – Reference data 5 (LSByte) R 30 – 31 Reference data 6 Reference data 6 (MSByte) – Reference data 6 (LSByte) R 32 NTHR key 0 Negative Threshold level for key 0 R/W 33 NTHR key 1 Negative Threshold level for key 1 R/W 34 NTHR key 2 Negative Threshold level for key 2 R/W 35 NTHR key 3 Negative Threshold level for key 3 R/W 36 NTHR key 4 Negative Threshold level for key 4 R/W 37 NTHR key 5 Negative Threshold level for key 5 R/W 38 NTHR key 6 Negative Threshold level for key 6 R/W 39 AVE/AKS key 0 Adjacent key suppression level for key 0 R/W 40 AVE/AKS key 1 Adjacent key suppression level for key 1 R/W AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 15 Table 5-1. Internal Register Address Allocation (Continued) Address Use Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W 41 AVE/AKS key 2 Adjacent key suppression level for key 2 R/W 42 AVE/AKS key 3 Adjacent key suppression level for key 3 R/W 43 AVE/AKS key 4 Adjacent key suppression level for key 4 R/W 44 AVE/AKS key 5 Adjacent key suppression level for key 5 R/W 45 AVE/AKS key 6 Adjacent key suppression level for key 6 R/W 46 DI key 0 Detection integrator counter for key 0 R/W 47 DI key 1 Detection integrator counter for key 1 R/W 48 DI key 2 Detection integrator counter for key 2 R/W 49 DI key 3 Detection integrator counter for key 3 R/W 50 DI key 4 Detection integrator counter for key 4 R/W 51 DI key 5 Detection integrator counter for key 5 R/W 52 DI key 6 Detection integrator counter for key 6 R/W 53 FO/MO/Guard No FastOutDI/ Max Cal/Guard Channel R/W 54 LP Low Power (LP) Mode R/W 55 Max On Duration Maximum On Duration R/W 56 Calibrate Calibrate R/W 57 RESET RESET R/W 5.2 Address 0: Chip ID Table 5-2. Address Chip ID b7 0 b6 b5 b4 b3 b2 MAJOR ID b1 b0 b1 b0 MINOR ID MAJOR ID: Reads back as 2 MINOR ID: Reads back as E 5.3 Address 1: Firmware Version Table 5-3. Address 1 Firmware Version b7 b6 b5 b4 b3 b2 FIRMWARE VERSION FIRMWARE VERSION: this shows the 8-bit firmware version 1.5 (0x15). AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 16 5.4 Address 2: Detection Status Table 5-4. Detection Status Address b7 b6 b5 b4 b3 b2 b1 b0 2 CALIBRATE OVERFLO W – – – – – TOUCH CALIBRATE: This bit is set during a calibration sequence. OVERFLOW: This bit is set if the time to acquire all key signals exceeds 8 ms. TOUCH: This bit is set if any keys are in detect. 5.5 Address 3: Key Status Table 5-5. Key Status Address b7 b6 b5 b4 b3 b2 b1 b0 3 Reserved KEY6 KEY5 KEY4 KEY3 KEY2 KEY1 KEY0 KEY0 – 6: bits 0 to 6 indicate which keys are in detection, if any. Touched keys report as 1, untouched or disabled keys report as 0. 5.6 Address 4 – 17: Key Signal Table 5-6. Address Key Signal b7 b6 b5 b4 b3 b2 4 MSByte OF KEY SIGNAL FOR KEY 0 5 LSByte OF KEY SIGNAL FOR KEY 0 6 – 17 MSByte/LSByte OF KEY SIGNAL FOR KEYS 1 – 6 b1 b0 KEY SIGNAL: addresses 4 – 17 allow key signals to be read for each key, starting with key 0. There are two bytes of data for each key. These are the key’s 16-bit key signals which are accessed as two 8-bit bytes, stored MSByte first. These addresses are read-only. AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 17 5.7 Address 18 – 31: Reference Data Table 5-7. Reference Data Address b7 b6 b5 b4 b3 b2 b1 18 MSByte OF REFERENCE DATA FOR KEY 0 19 LSByte OF REFERENCE DATA FOR KEY 0 20 – 31 MSByte/LSByte OF REFERENCE DATA FOR KEYS 1 – 6 b0 REFERENCE DATA: addresses 18 – 31 allow reference data to be read for each key, starting with key 0. There are two bytes of data for each key. These are the key’s 16-bit reference data which is accessed as two 8-bit bytes, stored MSByte first. These addresses are read-only. 5.8 Address 32 – 38: Negative Threshold (NTHR) Table 5-8. NTHR Address b7 b6 b5 32 – 38 b4 b3 b2 b1 b0 NEGATIVE THRESHOLD FOR KEYS 0 – 6 NTHR Keys 0 – 6: these 8-bit values set the threshold value for each key to register a detection. Default: 20 counts Note: 5.9 Do not use a setting of 0 as this causes a key to go into detection when its signal is equal to its reference. Address 39 – 45: Averaging Factor/Adjacent Key Suppression (AVE/AKS) Table 5-9. AVE/AKS Address b7 b6 b5 b4 b3 b2 b1 b0 39 – 45 AVE5 AVE4 AVE3 AVE2 AVE1 AVE0 AKS1 AKS0 AVE 0 – 5: The Averaging Factor (AVE) is the number of pulses which are added together and averaged to get the final signal value for that channel. For example, if AVE = 8 then 8 ADC samples are taken and added together. The result is divided by the original number of pulses (8). If sixteen pulses are used then the result is divided by sixteen. This provides a better signal-to-noise ratio but requires longer acquire times. Values for AVE are restricted internally to 1, 2, 4, 8, 16 or 32. Default: 8 (In standalone mode key 0 is 16) AKS 0 – 1: these bits control which keys are included in an AKS group. There can be up to three groups, each containing any number of keys (up to the maximum allowed for the mode). Each key can have a value between 0 and 3, which assigns it to an AKS group of that number. A key may only go into detect when it has the largest signal change of any key in its group. A value of 0 means the key is not in any AKS group. Default: 0x01 AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 18 5.10 Address 46 – 52: Detection Integrator (DI) Table 5-10. Detection Integrator Address b7 b6 b5 46 – 52 b4 b3 b2 b1 b0 DETECTION INTEGRATOR DETECTION INTEGRATOR: addresses 46 – 52 allow the DI level to be set for each key. This 8-bit value controls the number of consecutive measurements that must be confirmed as having passed the key threshold before that key is registered as being in detect. The minimum value for the DI filter is 2. Settings of 0 and 1 for the DI also default to 2 because a minimum of two consecutive measurements must be confirmed. Default: 4 5.11 Address 53: FastOutDI/Max Cal/Guard Channel Table 5-11. Max Cal/Guard Channel Address b7 53 b6 – b5 b4 FO MAX CAL b3 b2 b1 b0 GUARD CHANNEL FO: Fast Out DI – when bit 5 is set then a key filters out with an integrator of 4. Could have a DI in of 100 but filter out with DI of 4 (global setting for all keys). MAX CAL: if this bit is clear then all keys recalibrate after a Max On Duration timeout, otherwise only the key with the incorrect timing gets recalibrated. GUARD CHANNEL: bits 0 – 3 are used to set a key as the guard channel (which gets priority filtering). Valid values are 0 – 6, with any larger value disabling the guard key feature. 5.12 Address 54: Low Power (LP) Mode Table 5-12. LP Mode Address 54 b7 b6 b5 b4 b3 b2 b1 b0 LOW POWER MODE AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 19 LP MODE: this 8-bit value determines the number of 8 ms intervals between key measurements. Longer intervals between measurements yield a lower power consumption but at the expense of a slower response to touch. Setting Time 0 8 ms 1 8 ms 2 16 ms 3 24 ms 4 32 ms 254 2.032s 255 2.040s Default: 2 (16 ms between key acquisitions) 5.13 Address 55: Max On Duration Table 5-13. Max Time On Address b7 b6 b5 b4 55 b3 b2 b1 b0 MAX ON DURATION MAX ON DURATION: this is a 8-bit value which determines how long any key can be in touch before it recalibrates itself. A value of 0 turns Max On Duration off. Setting Time 0 Off 1 160 ms 2 320 ms 3 480 ms 4 640 ms 255 40.8s Default: 180 (160 ms × 180 = 28.8s) AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 20 5.14 Address 56: Calibrate Table 5-14. Calibrate Address b7 b6 56 b5 b4 b3 b2 b1 b0 Writing a nonzero value forces a calibration Writing any nonzero value into this address triggers the device to start a calibration cycle. The CALIBRATE flag in the detection status register is set when the calibration begins and clears when the calibration has finished. 5.15 Address 57: RESET Table 5-15. RESET Address 57 b7 b6 b5 b4 b3 b2 b1 b0 Writing a nonzero value forces a reset Writing any nonzero value to this address triggers the device to reset. AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 21 6. Specifications 6.1 Absolute Maximum Specifications Vdd –0.5 to +6 V Max continuous pin current, any control or drive pin ±10 mA Short circuit duration to ground, any pin infinite Short circuit duration to Vdd, any pin infinite Voltage forced onto any pin –0.5 V to (Vdd + 0.5) V CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum specification conditions for extended periods may affect device reliability. 6.2 Recommended Operating Conditions Operating temperature –40oC to +85oC Storage temperature –55oC to +125oC Vdd +1.8 V to 5.5 V Supply ripple+noise ±25 mV Cx load capacitance per key 1 to 30 pF 6.3 DC Specifications Vdd = 3.3 V, Cs = 10 nF, load = 5 pF, 32 ms default sleep, Ta = recommended range, unless otherwise noted Parameter Description Minimum Typical Maximum Units Vil Low input logic level – – 0.2 × Vdd V Vih High input logic level 0.7 × Vdd – Vdd + 0.5 V Vol Low output voltage – – 0.6 V Voh High output voltage Vdd – 0.7V – – V – – ±1 µA Iil Input leakage current Notes AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 22 6.4 Power Consumption Measurements Cx = 5 pF, Rs = 4.7 k Idd (µA) at Vdd = 6.5 LP Mode 5V 3.3 V 1.8 V 0 (8 ms) 1744 906 442 1 (16 ms) 1375 615 305 2 (24 ms) 1263 525 261 4 (32 ms) 1168 486 234 5 (40 ms) 1119 445 221 6 (48 ms) 1089 434 211 Timing Specifications Paramete r Description Minimum Typica l Maximum Units Notes DI setting × 8 ms – LP mode + (DI setting × 8 ms) ms Under host control Sample frequency 162 180 198 kHz Modulated spread-spectrum (chirp) TD Power-up delay to operate/calibration time – <230 – ms Can be longer if burst is very long. FI2C I2C clock rate – – 400 kHz – Fm Burst modulation, percentage % – µs – TR Response time FQT RESET pulse width ±8 5 – – AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 23 6.6 Mechanical Dimensions 6.7 AT42QT1070-SSU – 14-pin SOIC 4 F 4 < /,&* 4&* "55.(!54.!. >15 )?0# 9 5!. .5 57A 7 %6 B ;CC 7 B DC 9 % B 6 ( %%;E B % 6 % @5< 7 7 ( &* .+ 4 DE B E F 66C B 6 < ; B " ./4 /0) *1)) 1) 2)1)34(4"() *56& ) 71) 1) 6((8 0,))) 9))58 0,)) 9))0 : ;#,) % (4) 8 0),))!) 1 0 ,))0 :6 #,) <0010) 1)) 9) /0 *0 )%; #)) ) 9=0 , 0 : := 1; 6#,) $$% () *" + , ) *- !"# &' AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 24 6.8 AT42QT1070-MMH – 20-pin 3 × 3 mm VQFN ( " !( 4 7 7 (6 >15 )?# ;ECD6 "C CA# I"0 1) "%# 6 46 % % 6 9 DCE; H < %J1 :# 7 E C C 7 6 9 E 66 6E " 6 ( 6D % % (6 E 4 6D % % 46 E < % H 6 C $$% () *" + , ) *- 6, %:%:C< 0 :4:, /0) 40 &)/0' 8 .< &'8.# G8" 656 " AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 25 6.9 Marking 6.9.1 AT42QT1070-SSU – 14-pin SOIC Either part marking can be used. Abbreviated part number 1070 1R5 Pin 1 ID Date Code Code revision 1.5, released 1 Date Code Description W=Week code W week code number 1-52 where: A=1 B=2 .... Z=26 then using the underscore A=27...Z=52 Abbreviated part number ATMEL QT1070 1R5 YYWW Pin 1 ID Code revision 1.5, released 1 YYWW = Date code, variable text AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 26 6.9.2 AT42QT1070-MMH – 20-pin 3 × 3 mm VQFN Either part marking can be used. Shortened part number in hexadecimal Pin 1 ID Code Revision 1.5, released 42E = 1070 42E 15 Date Code, released Date Code Description W=Week code W week code number 1-52 where: A=1 B=2 .... Z=26 then using the underscore A=27...Z=52 Pin 1 ID 15 = Code Revision 1.5, released Abbreviation of part number: (AT42QT1070-MMH) 170 15X YZZ X = Assembly location code (variable text) Date Code, released YZZ = traceability code (variable text) Y = the last digit of the year (for example 0 for year 2010, 1 for year 2011), ZZ is the trace code for each assembly lot. AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 27 6.10 6.11 Part Number Part Number Description AT42QT1070-SSU 14-pin SOIC RoHS compliant IC AT42QT1070-MMH 20-pin 3 x 3 mm VQFN RoHS compliant IC Moisture Sensitivity Level (MSL) MSL Rating Peak Body Temperature Specifications MSL3 260oC IPC/JEDEC J-STD-020 AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 28 Appendix A. I2C Operation The device communicates with the host over an I2C bus. The following sections give an overview of the bus; more detailed information is available from www.i2C-bus.org. Devices are connected to the I2C bus as shown in Figure A1. Both bus lines are connected to Vdd via pull-up resistors. The bus drivers of all I2C devices must be open-drain type. This implements a wired AND function that allows any and all devices to drive the bus, one at a time. A low level on the bus is generated when a device outputs a zero. Figure A-1. I2C Interface Bus Vdd Device 1 Device 2 Device 3 Device n R1 R2 SDA SCL A.1 Transferring Data Bits Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high; the only exception to this rule is for generating START and STOP conditions. Figure A-2. Data Transfer SDA SCL Data Stable Data Stable Data Change AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 29 A.2 START and STOP Conditions The host initiates and terminates a data transmission. The transmission is initiated when the host issues a START condition on the bus, and is terminated when the host issues a STOP condition. Between the START and STOP conditions, the bus is considered busy. As shown in Figure A-3, START and STOP conditions are signaled by changing the level of the SDA line when the SCL line is high. Figure A-3. START and STOP Conditions SDA SCL START A.3 STOP Address Byte Format All address bytes are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is performed, otherwise a write operation is performed. When the device recognizes that it is being addressed, it will acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. An address byte consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively. The most significant bit of the address byte is transmitted first. The address sent by the host must be consistent with that selected with the option jumpers. Figure A-4. Address Byte Format Addr MSB Addr LSB R/W ACK 7 8 9 SDA SCL START 1 2 AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 30 A.4 Data Byte Format All data bytes are 9 bits long, consisting of 8 data bits and an acknowledge bit. During a data transfer, the host generates the clock and the START and STOP conditions, while the receiver is responsible for acknowledging the reception. An acknowledge (ACK) is signaled by the receiver pulling the SDA line low during the ninth SCL cycle. If the receiver leaves the SDA line high, a NACK is signaled. Figure A-5. Data Byte Format Data MSB Data LSB ACK 8 9 Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 2 7 Data Byte SLA+R/W A.5 Stop or Next Data Byte Combining Address and Data Bytes into a Transmission A transmission consists of a START condition, an SLA+R/W, one or more data bytes and a STOP condition. The wired ANDing of the SCL line is used to implement handshaking between the host and the device. The device extends the SCL low period by pulling the SCL line low whenever it needs extra time for processing between the data transmissions. Note: Each write or read cycle must end with a stop condition. The device may not respond correctly if a cycle is terminated by a new start condition. Figure A-6 shows a typical data transmission. Note that several data bytes can be transmitted between the SLA+R/W and the STOP. Figure A-6. Byte Transmission Addr MSB Addr LSB R/W ACK 7 8 9 Data MSB Data LSB ACK 8 9 SDA SCL 1 START 1 2 SLA+RW 2 7 Data Byte STOP AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 31 Associated Documents QTAN0062 – QTouch and QMatrix Sensitivity Tuning for Keys, Slider and Wheels Touch Sensors Design Guide Revision History Revision Number History Revision A – October 2010 Initial release of document for code revision 1.5 Revision B – November 2012 General updates Revision C – May 2013 Applied new template AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 32 Notes AT42QT1070 [DATASHEET] 9596C–AT42–05/2013 33 Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel München GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching bei München Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.com Tel: (+852) 2245-6100 Fax: (+49) 89-3194621 Fax: (+81) (3) 6417-0370 Fax: (+852) 2722-1369 © 2013 Atmel Corporation. All rights reserved. / Rev.: 9596C–AT42–05/2013 Atmel®, Atmel logo and combinations thereof, Adjacent Key Suppression®, AKS®, QTouch®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be registered trademarks or trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 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