Powering GSPS or RF Sampling ADCs: Switcher vs LDO

Powering GSPS or RF Sampling ADCs: Switcher vs LDO
TECHNICAL ARTICLE
POWERING GSPS OR
RF SAMPLING ADCS:
SWITCHER VS. LDO
Umesh Jayamohan
High Speed Converter
Application Engineer,
Analog Devices, Inc.
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Analog Introduction
The analog-to-digital converter (ADC) is an integral component in any
system that depends on gathering information from the outside (analog)
world for (digital) processing. These systems vary in applications from
communications receivers to electronic test and measurement, to military
and aerospace, to name a few. Advancements in silicon processing
technology (such as 65 nm CMOS and 28 nm CMOS) have enabled the high
speed ADC to cross the GSPS (gigasample per second) barrier. What this
provides the systems designer with is the ability to sample wider and wider
bandwidths for digital processing. Systems designers are constantly trying
to reduce overall power for environmental and cost reasons. Traditionally,
low noise LDO (low dropout) regulators have been recommended by ADC
manufacturers for powering GSPS (or RF sampling) ADCs in order to extract
maximum performance. However, this is not an efficient power delivery
network (PDN) implementation. Systems designers are increasingly
demanding to use switching power regulators to power the GSPS ADC
directly without a significant drop in ADC performance.
The solution lies in careful PDN implementation and layout to ensure
that the ADC performance is not compromised. This article discusses the
difference between linear and switching supplies and demonstrates that
12 V 1A
ADP2384
3.8 V
Filter
3.3 V 3A
combining a GSPS ADC with a dc-to-dc converter can significantly improve
system power efficiency without any penalty in ADC performance. This
article discusses the performance of the GSPS ADC using a combination
of power delivery networks and makes comparative analyses on cost
and performance.
Traditionally Recommended PDN for GSPS ADCs
A high bandwidth, high sample rate ADC (or GSPS ADC) can have multiple
power domains (such as AVDD or DVDD). With the shrinking geometries,
not only have the power domains increased in number, but the number of
different voltages required to power the ADC have increased as well. For
example, the AD9250,1 a 14-bit,170 MSPS/250 MSPS, JESD204B, dual
analog-to-digital converter, is built using the 180 nm CMOS process and
has three domains: AVDD, DVDD, and DRVDD. However, all three domains
are the same voltage: 1.8 V.
Now consider the AD9680,2 a 14-bit 1.25 GSPS/1 GSPS/820 MSPS/
500 MSPS JESD204B, dual analog-to-digital converter, which is built
on a 65 nm CMOS process. This GSPS ADC has seven different domains
(AVDD1, AVDD1_SR, AVDD2, AVDD3, DVDD, DRVDD, and SPIVDD) and
three different voltages: 1.25 V, 2.5 V, and 3.3 V.
The proliferation of these supply domains and the various voltages is
somewhat of a necessity for operation at these sample rates. They
ADP124
ADP1740
3.3 V
2.5 V
Filter
Filter
3.3 V
AVDD3
2.5 V
LDO
Switcher
Filter
Ferrite Bead
AVDD2
Optional
ADM7160
ADP2164
1.8 V
Filter
ADP1740
ADP130
Filter
ADP1740
ADP130
1.8 V
1.25 V
1.25 V
1.25 V
1.25 V
Filter
1.8 V
SPIVDD
Filter
1.25 V
AVDD1
Filter
1.25 V
AVDD1_SR
Filter
1.25 V
DVDD
Filter
1.25 V
DRVDD
Figure 1. Default PDN for the AD9680 evaluation board.
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Notes:
1. Switcher output stage filter
not shown.
2. LDO outputs have been
adjusted for the dc voltage
drops across ferrite bead.
3. SPIVDD supports 1.8 V to 3.3 V.
2
Powering GSPS or RF Sampling ADCs: Switcher vs. LDO
are required to ensure proper isolation between the various circuit
domains (such as sampling, clock, digital, and serializer) while providing
optimal performance. It is for this very reason that the ADC manufacturers
design the evaluation boards and recommend an elaborate power supply
design to ensure minimal risk and maximum performance. For example,
Figure 1 shows the block diagram representation of the default PDN used in
the AD9680 evaluation board. The power input is derived from the 12 V/1 A
and 3.3 V/3 A supplies offered by the FMC (FPGA mezzanine card) connector
using the Vita57.1 specification. The ADP23843 and ADP21644 dc-to-dc
converters were used to step down the voltages to a manageable level
so the LDOs can regulate without having to go into thermal shutdown.
It does not take much to realize that this is an expensive implementation,
with seven LDO regulators, one for each domain. This PDN may be the
most optimal in terms of performance, but it certainly is not the most cost
effective or efficient in terms of cost of operation. Systems designers find
it challenging to implement a system with multiple ADCs. For example, a
phased array radar implementation will contain hundreds of AD9680s all
working synchronously. It is unreasonable to ask the systems designer to
have one LDO regulator per voltage domain across hundreds of ADCs.
A Simpler PDN for GSPS ADCs
A more cost-effective approach to the PDN design would be to combine
the domains that have the same voltage value (say all 1.25 V analog
domains) and drive them from the same LDO. This reduces the component
count (and bill of material—BOM—cost) and may be suitable for some
designs. The simplified PDN is shown in Figure 2 as implemented on the
AD9680 evaluation board. In this implementation, the entire AD9680 can
be powered using a single 3.3 V input.
A DC-to-DC Converter Driving the AD9680
A further simplification to the PDN can be implemented by removing
the LDO that supplies the 1.25 V domains altogether. This would be the
most efficient and cost-effective solution. The challenge here is to ensure
stable operation to the dc-to-dc converter so as to not affect the ADC’s
performance. The PDN where the ADP2164 drives all the 1.25 V domains
(AVDD1, AVDD1_SR, DVDD, and DRVDD) of the AD9680 is shown in Figure 3.
3.3 V
PVIN
L1
SW
L2
C1
1.8 V
C2
ADP2164
C3
Cf
ADP1740/
ADP1741
1.25 V
C4
AVDD1
C5
E1
Rf1
AVDD1_SR
FB
Rb
C7
Rf2
C8
E2
DVDD
C10
C11
E3
DRVDD
C13
ADP1741
2.5 V
C16
C15
AVDD2
C17
E5
3.3 V
C18
C14
E4
AVDD3
E6
C19
Figure 2: Simplified PDN for the AD9680 evaluation board.
3.3 V
PVIN
SW
L1
L2
C1
1.25 V
C2
ADP2164
Cf
C4
AVDD1
E1
C5
Rf1
AVDD1_SR
FB
Rb
C7
Rf2
E2
C8
DVDD
C10
E3
C11
DRVDD
C13
ADP1741
C15
E4
2.5 V
C16
AVDD2
E5
3.3 V
C18
Figure 3: Using a dc-to-dc converter to power the AD9680.
C14
C17
AVDD3
E6
C19
Visit analog.com Comparing the Various PDNs
The three PDNs discussed above were put to test along with a fourth
network where the AD9680 evaluation board was powered from the bench
supplies. Table 1 lists the various power delivery networks implemented
on the AD9680 evaluation board.
Table 1. List of Power Delivery Networks
PDN Setup
Bench
PDN #1
PDN #2
PDN #3
Description
AD9680 run using bench supply
Default PDN on evaluation board (shown in Figure 1)
All 1.25 V domains driven from one LDO (shown in Figure 2)
All 1.25 V domains driven from a dc-to-dc converter
(shown in Figure 3)
Since SPIVDD could support 1.8 V to 3.3 V and was considered a
noncritical node, it was powered using a 1.8 V LDO output. In a regular
system implementation, the SPIVDD can be connected to the 2.5 V or
3.3 V domain. That said, the SPIVDD connection should still be monitored
in systems where the SPI bus is shared between many ADCs and DACs.
If this is the case, care must be taken to ensure that the normal SPI
operation does not cause supply transients on the SPIVDD domain. Their
supply transients might trigger a power-on reset (POR) situation if the
SPIVDD goes lower than the threshold level.
The PDN using just the dc-to-dc converter to power the AD9680’s
1.25 V domains (PDN #3) shows good performance over the input
frequencies. This proves that it is possible to combine domains and
power them efficiently and cost effectively without paying a huge
penalty in ADC performance. The PDN supplied from the bench provides
the best noise performance as it is the lowest noise power source.
However, it is worth noting that PDN #3 consistently shows better SNR
performance than the default network (PDN #1). This could be attributed
to the fact that LDOs are good for low frequency cleanup but do not do
much above a few 100 kHz even when they are in the circuit. This could
explain the 0.2 dB advantage in SNR when using the PDN #3.
FFT Plots
Figure 4 and Figure 5 show the single tone FFTs at 170 MHz and
785 MHz input, respectively. The FFT shows no spectral degradation
due to the fact that the 1.25 V domains have been powered from a
single dc-to-dc converter.
Table 2. SNR Performance Comparison (dBFS)
Frequency
(MHz)
63
170
340
450
765
985
1283
1725
1983
Bench
66.5
66.4
64.8
64.0
62.5
61.3
59.8
57.7
56.7
Default
(PDN #1)
66.5
66.1
64.5
63.7
62.2
61.0
59.5
57.4
56.4
Simplified
(PDN #2)
66.6
65.9
64.5
63.6
62.2
61.0
59.5
57.4
56.5
Switcher
(PDN #3)
66.7
66.2
64.7
63.8
62.3
61.1
59.5
57.5
56.6
Figure 4. Single-tone FFT at 170 MHz input, with PDN #3.
Table 3. SFDR Performance Comparison (dBFS)
Frequency
(MHz)
63
170
340
450
765
985
1283
1725
1983
Bench
83
86
77
72
77
77
74
67
60
Default
(PDN #1)
82
85
76
72
76
76
74
67
60
Simplified
(PDN #2)
88
85
76
71
76
76
74
68
60
Switcher
(PDN #3)
83
84
76
71
82
83
75
67
60
Table 2 and Table 3 show the SNR and SFDR performance respectively
of the AD9680 when using the various PDNs. The recommendations for
front-end network and register settings for various Nyquist zones were
followed as per the AD9680 data sheet.2
Figure 5. Single-tone FFT at 785 MHz input, with PDN #3.
3
4
Powering GSPS or RF Sampling ADCs: Switcher vs. LDO
Figure 6. 1.2 MHz sideband switching spur at 170 MHz input. Spur level = –105 dBFS.
Figure 7. 1.2 MHz sideband switching spur at 785 MHz input. Spur level = –94 dBFS.
Switching Spurs
PDN. ADIsimPE is a convenient and powerful tool that helps the systems
engineer design, optimize, and analyze power supply networks.
In addition to the noise performance, the dc-to-dc converter
implementation should also be checked for spurious content due to
the switching elements and the magnetics involved. This is where
careful layout techniques to reduce ground loops and ground bounce
will be beneficial. There are many resources that can help with
measurement of the switching supply noise.5,6 The sideband spurs
appear on either side of the fundamental offset by the switching
frequency (in this example, 1.2 MHz). It must be noted that the output
filter stage shown in Figure 2 or Figure 3 is a two-stage filter. This
two-stage filter is a main contributor in reducing the switching noise
(ripple) that helps improve the ADC noise (SNR) performance. In the
same token, the two-stage filter also helps in reducing the switching
spurs that manifest itself in the output FFT. These are shown in
Figure 6 and Figure 7 for 170 MHz and 785 MHz, respectively.
Figure 9 shows the output ripple at the output of the first stage and the
filtered output after the second stage of the circuit, simulated in ADIsimPE.
The ripple as shown here is around 3 mV p-p.
1.282
1.28
1.278
Stage 1 Output
Stage 2 Output
1.276
The level of the sideband spur can be estimated by understanding the
PSRR (power supply rejection ratio) or the ADC’s power supply domain.7
1.274
1.272
Simulating DC-to-DC Converter
Switching Circuits
The two-stage filter at the output of the dc-to-dc converter can be simulated
using a tool such as ADIsimPE.8 Figure 8 shows the ADIsimPE schematic
generated to simulate the output noise and stability characteristics of the
Leff =
dcr = 6 mΩ
470 nH
V3
CIN
LIN
10 µF
esr = 2 mΩ
n=1
10 Ω
RVIN
U1
VIN
En
1
J2
V2
V1
J3
Sync
2
RT
RT
45.3 kΩ
PVIN PGOOO
Figure 9. Stage 1 and Stage 2 outputs of the ADIsimPE simulation.
100 kΩ
Rpg
ADP2164
ADJ
ICstatus
• Run
• OVP
• ILim it
• Neg Ilim
• PSM
• Dropout
TRK
CVREG
100 nF
205.5 206 206.5 207 207.5 208 208.5 209 209.5
Time/µs
500 ns/Div
SW
SW Leff =
2.2 µH
VL1
L1
COUT1
22 µF
esr = 10 mΩ
n=2
FB
AGND
dcr = 13 mΩ
PGND
Leff =
1 µH
dcr = 6 mΩ
L2
COUT2
100 nF
esr = 2.1 mΩ
n=1
Rf1
Rf3
21 kΩ
5 kΩ
Rf2
23.2 kΩ
Figure 8. ADIsimPE schematic of ADP2164 driving the 1.25 V domains.
VOUT
COUT3
47 µ
esr = 2.1 mΩ
n=4
= Out/In
In
Out
VOUT
1.12 mΩ
R4
Visit analog.com Table 4. Bill of Material of PDN Shown in Figure 2
REFDES
C1
C2
Cf
C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, 14,
C15, C16, 17, C18, C19
E1, E2, E3, E4, E5, E6
L1
L2
Rf1
Rf2
Rb
ADP2164
ADP1741
ADP171
Qty
Description
MFG
Part Number
Value
1
4
1
22 μF, 6.3 V, X5R 0805 capacitor
22 μF, 6.3 V, X5R 0805 capacitor
0.1 μF, 10 V, X5R 0402 capacitor
Murata
Murata
Murata
GRM21BR60J226ME39L
GRM21BR60J226ME39L
GRM155R61A104KA01D
22 μF
22 μF
0.1 μF
17
4.7 μF, 6.3 V, X5R 0402 capacitor
Murata
GRM155R60J475ME47D
4.7 μF
6
1
1
1
1
1
1
3
2
Ferrite chip 10 Ω 0402
1.0 μH shielded power inductor, 10 mΩ
2.2 μH shielded power inductor, 0.1 Ω
4.99 kΩ, 1% 1, W/10 W 0402 resistor
41.2 kΩ, 1% 1, W/10 W 0402 resistor
23.2 kΩ, 1% 1, W/10 W 0402 resistor
IC, REG, buck ADJ, 4 A, sync, 16-lead LFCSP
IC, REG, LDO, ADJ, 2 A, 16-lead LFCSP
IC, REG, LDO, ADJ, 0.3 A, 5-lead TSOT-23
Murata
Coilcraft
Coilcraft
Panasonic
Panasonic
Panasonic
Analog Devices
Analog Devices
Analog Devices
BLM15AX100SN1D
XAL5030-102ME
ME3220-222ML
ERJ-2RKF4991X
ERJ-2RKF4122X
ERJ-2RKF2322X
ADP2164ACPZ-R7
ADP1741ACPZ-R7
ADP171AUJZ-R7
10 Ω
1.0 μH
2.2 μH
4.99 kΩ
41.2 kΩ
23.2 kΩ
Bill of Material
Table 4 shows the bill of material used for the simplified PDN of the
AD9680 evaluation board, which is shown in Figure 2. By using the
network shown in Figure 3, a systems designer can realize savings of up
to 40% to 45% in BOM cost. The BOM cost is estimated by calculating
the 1k unit prices of the components on a popular electronic component
vendor website.
Component Selection and Layout
The performance of the ADC when running on the various PDNs depends
on not only careful design, but also the selection of components and
their layout on the PCB. The high currents produced in a switching
power supply often lead to strong magnetic fields that can couple into
other magnetic components on the board, including inductors found in
matching networks and transformers used to couple analog and clock
signals. Careful board layout techniques must be utilized to prevent
these fields from coupling into critical signals.
Inductor Selection
Since the inductor and the capacitor that form the output filter stage
perform the bulk of the power delivery, they need to be selected carefully.
In this example, a mix of shielded and unshielded inductors were used.
The first filter stage used a shielded inductor. The second stage could do
with an unshielded inductor in this case. However, it is recommended to
use shielded inductors in both stages to minimize possible EMI emissions.
The inductors also were chosen to have enough headroom in terms of
saturation current (ISAT) and dc resistance (DCR) to make sure they didn’t
go into saturation or cause too much voltage drop across themselves.
Capacitor Selection
X5R or X7R capacitors are recommended for use as output filter
capacitors. The capacitors also have to have low ESR (equivalent series
resistance). The low ESR helps in reducing switching ripple at the
output. Another trick that is employed to minimize the total ESR and
ESI (equivalent series inductance) is to combine capacitors in parallel.
As shown in Figure 3 and Table 4, the first filter stage uses 2× 22 μF
capacitors, whereas the second filter stage 4× 22 μF capacitors. The
voltage rating of the capacitors is also an important factor in its selection.
This is because the dielectric of the ceramic capacitor degrades as the
dc bias increases. This means that a 6.3 V rated 22 μF capacitor could
degrade by up to 50% at a 4 V dc bias.9,10 In this example, the 6.3 V rated
capacitor is used for the 1.25 V supplies. Adding more capacitors at the
output does increase the BOM cost and board space slightly but this is
a good insurance against switching noise and ripple that could interfere
with ADC performance.
Ferrite Bead Selection
As shown in Figure 3, ferrite beads are used to isolate the various
domains. The selection of the ferrite bead is also critical, as a higher
than desired DCR (dc resistance) of the ferrite bead will cause lower
than optimal voltage at the domains. This low voltage results in less
than optimal ADC performance (SNR and SFDR). Sufficient attention
must be paid to the impedance characteristics, maximum dc carrying
capability, and the DCR of the ferrite bead.11
PCB Layout Considerations
In order to minimize the interactions between the switching regulator
and the ADC, the dc-to-dc converter and its switching elements should
be placed far away from any magnetics that interact with the ADC
(such as the front-end matching network or clock network). Within the
dc-to-dc converter layout, the two stage filter should be placed as close
to the dc-to-dc converter as possible so as to minimize loop currents.
Acknowledgement
The author would like to acknowledge Justin Correll for help with the
measurement and data collection.
Conclusion
RF sampling (or GSPS) ADCs offer a unique advantage in systems design
by allowing the digitization of wide swaths of bandwidth. The industry is
keen on reducing the complexity, size, and cost of power supply designs
for these GSPS ADCs. It is possible to have a low noise and cost-effective
PDN that can power a GSPS ADC by paying adequate attention to the design,
component selection, and PCN layout. Thus implemented, switching regulators
also help improve power system efficiency and provide operational cost and
BOM savings, without any penalty in performance.
5
References
About the Author
1
AD9250. Analog Devices.
2
AD9680. Analog Devices.
3
ADP2384. Analog Devices.
4
ADP2164. Analog Devices.
5
Akdrick Limjoco. “Understanding Switching Regulator Output
Artifacts Expedites Power Supply Design.” Analog Dialogue,
Volume 48, Number 3.
6
“Output Ripple and Noise Measurement Methods for Ericsson Power Modules.” Ericsson.
7
Rob Reeder. “Designing Power Supplies for High Speed ADC.”
Analog Devices.
8
ADIsimPE. Analog Devices.
9
GRM21BR60J226ME39L. Murata.
10
Istvan Novak, Kendrick Barry Williams, Jason R. Miller, Gustavo Blando,
and Nathaniel Shannon. “DC and AC Bias Dependence of Capacitors.”
DesignCon 2011.
11
Jefferson Eco and Akdrick Limjoco. AN-1368 Application Note. Ferrite
Bead Demystified. Analog Devices.
Umesh Jayamohan is an applications engineer with Analog Devices
in the High Speed Converter Group (Greensboro, NC). He has been a
part of Analog Devices since 2010. Umesh received his B.S.E.E. from
the University of Kerala, India, in 1998 and his M.S.E.E. from Arizona
State University in 2002. Umesh is a member of ADI’s EngineerZone®
in the High Speed ADC Support Community. Feel free to connect with
UmeshJ on EngineerZone. Sign up on EngineerZone for free.
REFDES
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Description MFG Part NumberValue
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