HD74ALVCH162270

HD74ALVCH162270
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HD74ALVCH162270
12-bit to 24-bit Registered Bus Exchanger with 3-state
Outputs
REJ03D0051-0300Z
(Previous ADE-205-178A(Z))
Rev.3.00
Oct.02.2003
Description
The HD74ALVCH162270 is used in applications where data must be transferred from a narrow high speed
bus to a wide lower frequency bus. The device provides synchronous data exchange between the two ports.
Data is stored in the internal registers on the low to high transition of the clock (CLK) input when the
appropriate CLKEN inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data
transfer in the A to B direction, a two stage pipeline is provided in the A to 1B path, with a single storage
register in the A to 2B path. Proper control of the CLKENA inputs allows two sequential 12-bit words to
be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active low output
enables (OEA, OEB). The control terminals are registered to synchronize the bus direction changes with
CLK. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All
outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and
undershoot.
Features
•
•
•
•
•
•
VCC = 2.3 V to 3.6 V
Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
High output current ±12 mA (@VCC = 3.0 V)
Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
All outputs have equivalent 26 Ω series resistors, so no external resistors are required.
Rev.3.00, Oct.02.2003, page 1 of 12
HD74ALVCH162270
Function Table
Inputs
Outputs
CLK
OEA
OEB
A
1B, 2B
↑
H
H
Z
Z
↑
H
L
Z
Active
↑
L
H
Active
Z
↑
L
L
Active
Active
Output enable
Inputs
Outputs
CLKENA1
CLKENA2
X
CLK
A
↑
H
1B
L
1B0
2B0 *1
*1, 2
2B0 *1
X
H
↑
H
1B0
L
L
↑
L
L *2
L
↑
L
H
↑
L
H
H
H
L
↑
L
H
H
H
X
X
2B
*1, 2
L
*2
H
1B0
*1
L
1B0
*1
H
1B0
*1
2B0 *1
A- to-B storage (OEB = L)
Note: This functional table describes the case of transferring the same data for A to 1B path. For the case
of transferring different data, see logic diagrams.
Inputs
Output A
CLKEN1B
CLKEN2B
CLK
SEL
1B
2B
H
X
X
H
X
X
A0 *1
X
H
X
L
X
X
A0 *1
L
X
↑
H
L
X
L
L
X
↑
H
H
X
H
X
L
↑
L
X
L
L
X
L
↑
L
X
H
H
B-to-A storage (OEA = L)
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑ : Low to high transition
Notes: 1. Output level before the indicated steady state input conditions were established.
2. Two CLK edges are needed to propagate data.
Rev.3.00, Oct.02.2003, page 2 of 12
HD74ALVCH162270
Pin Arrangement
1OE 1
48 2OE
1Y1 2
47 1A1
1Y2 3
46 1A2
GND 4
45 GND
1Y3 5
44 1A3
1Y4 6
43 1A4
VCC 7
42 VCC
2Y1 8
41 2A1
2Y2 9
40 2A2
GND 10
39 GND
2Y3 11
38 2A3
2Y4 12
37 2A4
3Y1 13
36 3A1
3Y2 14
35 3A2
GND 15
34 GND
3Y3 16
33 3A3
3Y4 17
32 3A4
VCC 18
31 VCC
4Y1 19
30 4A1
4Y2 20
29 4A2
GND 21
28 GND
4Y3 22
27 4A3
4Y4 23
26 4A4
4OE 24
25 3OE
(Top view)
Rev.3.00, Oct.02.2003, page 3 of 12
HD74ALVCH162270
Absolute Maximum Ratings
Item
Supply voltage
Input voltage
*1, 2
Symbol
Ratings
Unit
VCC
–0.5 to 4.6
V
VI
–0.5 to 4.6
V
–0.5 to VCC +0.5
Output voltage
*1, 2
Conditions
Except I/O ports
I/O ports
VO
–0.5 to VCC +0.5
V
Input clamp current
IIK
–50
mA
VI < 0
Output clamp current
IOK
±50
mA
VO < 0 or VO > VCC
Continuous output current
IO
±50
mA
VO = 0 to VCC
VCC, GND current / pin
ICC or IGND
±100
mA
Maximum power dissipation
*3
at Ta = 55°C (in still air)
PT
1
W
Storage temperature
Tstg
–65 to 150
°C
TSSOP
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any
other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
Recommended Operating Conditions
Item
Symbol
Min
Max
Unit
Supply voltage
VCC
2.3
3.6
V
Input voltage
VI
0
VCC
V
Output voltage
VO
0
VCC
V
High level output current
IOH
—
–6
mA
—
–8
VCC = 2.7 V
—
–12
VCC = 3.0 V
—
6
—
8
Low level output current
IOL
mA
VCC = 2.3 V
VCC = 2.3 V
VCC = 2.7 V
—
12
Input transition rise or fall rate
∆t / ∆v
0
10
ns / V
Operating temperature
Ta
–40
85
°C
VCC = 3.0 V
Note: Unused control inputs must be held high or low to prevent them from floating.
Rev.3.00, Oct.02.2003, page 4 of 12
Conditions
HD74ALVCH162270
Logic Diagram
29
CLK
CLKEN1B
2
CLKEN2B
27
CLKENA1
30
CLKENA2
55
OEB
56
C1
1D
28
SEL
1
OEA
CE
C1
1D
1D
23
C1
G1
A1
1
1
8
CE
C1
1D
CE
C1
1D
CE
C1
1D
CE
C1
1D
1 of 12 Channels
Rev.3.00, Oct.02.2003, page 5 of 12
6
1B1
2B1
HD74ALVCH162270
Electrical Characteristics
(Ta = –40 to 85°C)
Item
Symbol
VCC (V)
Input voltage
VIH
VIL
Output voltage
VOH
Min
Max
Unit Test Conditions
2.3 to 2.7 1.7
—
V
2.7 to 3.6 2.0
—
2.3 to 2.7 —
0.7
2.7 to 3.6 —
0.8
2.3 to 3.6 VCC–0.2 —
V
IOH = –100 µA
2.3
1.9
—
IOH = –4 mA, VIH = 1.7 V
2.3
1.7
—
IOH = –6 mA, VIH = 1.7 V
3.0
2.4
—
IOH = –6 mA, VIH = 2.0 V
2.7
2.0
—
IOH = –8 mA, VIH = 2.0 V
3.0
2.0
—
IOH = –12 mA, VIH = 2.0 V
2.3 to 3.6 —
0.2
IOL = 100 µA
2.3
—
0.4
IOL = 4 mA, VIL = 0.7 V
2.3
—
0.55
IOL = 6 mA, VIL = 0.7 V
3.0
—
0.55
IOL = 6 mA, VIL = 0.8 V
2.7
—
0.6
IOL = 8 mA, VIL = 0.8 V
3.0
—
0.8
IOL = 12 mA, VIL = 0.8 V
IIN
3.6
—
±5
IIN (hold)
2.3
45
—
VIN = 0.7 V
2.3
–45
—
VIN = 1.7 V
3.0
75
—
VIN = 0.8 V
3.0
–75
—
VIN = 2.0 V
3.6
—
±500
VIN = 0 to 3.6 V *1
IOZ
3.6
—
±10
µA
VOUT = VCC or GND
Quiescent supply current ICC
3.6
—
40
µA
VIN = VCC or GND
VOL
Input current
Off state output current
Note:
µA
VIN = VCC or GND
1. This is the bus hold maximum dynamic current required to switch the input from one state to
another.
Rev.3.00, Oct.02.2003, page 6 of 12
HD74ALVCH162270
Switching Characteristics
(Ta = 0 to +70°C)
Item
Symbol VCC (V)
Maximum clock frequency fmax
Propagation delay time
Output enable time
Output disable time
Min
Typ
Max
Unit
2.5±0.2 135
—
—
MHz
2.7
135
—
—
3.3±0.3 135
—
—
tPLH
2.5±0.2 2.5
—
6.9
tPHL
2.7
—
6.4
3.3±0.3 1.7
—
5.6
2.5±0.2 2.2
—
6.4
2.7
—
6.0
3.3±0.3 1.6
—
5.2
2.5±0.2 2.4
—
7.2
2.7
—
—
—
7.0
3.3±0.3 1.6
—
—
6.0
tZH
2.5±0.2 2.1
—
7.9
tZL
2.7
—
7.4
3.3±0.3 1.6
—
6.5
tHZ
2.5±0.2 3.0
—
7.8
tLZ
2.7
—
7.1
3.3±0.3 1.7
—
6.2
—
—
FROM
(Input)
TO
(Output)
CLK
B
CLK
A
SEL
A
ns
CLK
A or B
ns
CLK
A or B
ns
Input capacitance
CIN
3.3
—
3.5
—
pF
Control inputs
Output capacitance
CIN / O
3.3
—
9.0
—
pF
A or B ports
Rev.3.00, Oct.02.2003, page 7 of 12
HD74ALVCH162270
Switching Characteristics (cont.)
(Ta = –40 to 85°C)
Item
Symbol
VCC (V)
Min
Typ
Max
Unit
FROM (Input)
Setup time
tsu
2.5±0.2
4.1
—
—
ns
A data before CLK↑
2.7
3.8
—
—
3.3±0.3
3.1
—
—
2.5±0.2
0.9
—
—
2.7
1.2
—
—
3.3±0.3
0.9
—
—
2.5±0.2
3.5
—
—
CLKENA1 or
2.7
3.2
—
—
CLKENA2 before CLK↑
3.3±0.3
2.7
—
—
2.5±0.2
3.4
—
—
CLKEN1B or
2.7
3.0
—
—
CLKEN2B before CLK↑
3.3±0.3
2.6
—
—
Hold time
Pulse width
th
tw
2.5±0.2
4.4
—
—
2.7
3.9
—
—
3.3±0.3
3.2
—
—
2.5±0.2
0
—
—
2.7
0
—
—
3.3±0.3
0.2
—
—
2.5±0.2
1.4
—
—
2.7
1.0
—
—
B data before CLK↑
OE before CLK↑
ns
A data after CLK↑
B data after CLK↑
3.3±0.3
1.7
—
—
2.5±0.2
0
—
—
CLKENA1 or
2.7
0.1
—
—
CLKENA2 after CLK↑
3.3±0.3
0.3
—
—
2.5±0.2
0
—
—
CLKEN1B or
2.7
0
—
—
CLKEN2B after CLK↑
3.3±0.3
0.6
—
—
2.5±0.2
0
—
—
2.7
0
—
—
3.3±0.3
0.1
—
—
2.5±0.2
3.3
—
—
2.7
3.3
—
—
3.3±0.3
3.3
—
—
Rev.3.00, Oct.02.2003, page 8 of 12
OE after CLK↑
ns
CLK “H” or “L”
HD74ALVCH162270
• Test Circuit
See under table
500 Ω
S1
OPEN
GND
*1
C L = 50 pF
500 Ω
Load Circuit for Outputs
Symbol Vcc=2.5±0.2 V
t PLH / t PHL
OPEN
t su / t h / t w
t ZH/ t HZ
t ZL / t LZ
Vcc = 2.7 V,
3.3±0.3 V
OPEN
GND
GND
4.6 V
6.0 V
Note: 1. C L includes probe and jig capacitance.
Rev.3.00, Oct.02.2003, page 9 of 12
HD74ALVCH162270
• Waveforms – 1
tf
tr
VIH
90 %
Vref
90 %
Input
Vref
10 %
10 %
GND
t PHL
t PLH
VOH
Output
Vref
Vref
VOL
• Waveforms – 2
tr
VIH
90 %
Vref
Timing Input
10 %
tsu
GND
th
VIH
Data Input
Vref
Vref
GND
tw
VIH
Input
Vref
Vref
GND
Rev.3.00, Oct.02.2003, page 10 of 12
HD74ALVCH162270
• Waveforms – 3
Output
Control
tf
tr
90 %
Vref
VIH
90 %
Vref
10 %
t ZL
10 %
GND
t LZ
≈VOH1
Vref
Waveform - A
t ZH
Waveform - B
VOL + 0.3 V
t HZ
VOH – 0.3 V
Vref
VOL
VOH
≈VOL1
TEST
VIH
Vref
VOH1
VOL1
Vcc=2.5±0.2 V
Vcc=2.7 V,
3.3±0.3 V
2.3 V
2.7 V
1.2 V
2.3 V
1.5 V
3.0 V
GND
GND
Notes: 1. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
Rev.3.00, Oct.02.2003, page 11 of 12
HD74ALVCH162270
Package Dimensions
As of January, 2003
14.0
14.2 Max
56
Unit: mm
6.10
29
1
*0.19 ± 0.05
0.50
28
0.08 M
1.0
8.10 ± 0.20
0.65 Max
*Ni/Pd/Au plating
Rev.3.00, Oct.02.2003, page 12 of 12
0.10 ± 0.05
0.10
*0.15 ± 0.05
1.20 Max
0˚ – 8˚
0.50 ± 0.1
Package Code
JEDEC
JEITA
Mass (reference value)
TTP-56DAV
—
—
0.23 g
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
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Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11
Renesas Technology Hong Kong Ltd.
7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2375-6836
Renesas Technology Taiwan Co., Ltd.
FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology (Shanghai) Co., Ltd.
26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China
Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952
Renesas Technology Singapore Pte. Ltd.
1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
© 2003. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon 1.0
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