datasheet for LP62E16256E

datasheet for LP62E16256E
LP62E16256E-T Series
256K X 16 BIT LOW VOLTAGE CMOS SRAM
Document Title
256K X 16 BIT LOW VOLTAGE CMOS SRAM
Revision History
History
Issue Date
Remark
0.0
Initial issue
July 4, 2002
Preliminary
1.0
Final version release
July 17, 2003
Final
1.1
Modify 48LD CSP outline dimensions
November 18, 2003
1.2
Add Pb-Free package type
August 9, 2004
Rev. No.
(August, 2004, Version 1.2)
AMIC Technology, Corp.
LP62E16256E-T Series
256K X 16 BIT LOW VOLTAGE CMOS SRAM
Features
General Description
̈ Operating voltage: 1.65V to 2.2V
̈ Access times: 70ns (max.)
̈ Current:
Very low power version: Operating: 30mA (max.)
Standby:
10µA (max.)
The LP62E16256E-T is a low operating current 4,194,304bit static random access memory organized as 262,144
words by 16 bits and operates on low power voltage from
1.65V to 2.2V. It is built using AMIC's high performance
CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
The chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage as
low as 1.2V.
̈
̈
̈
̈
̈
Full static operation, no clock or refreshing required
All inputs and outputs are directly TTL-compatible
Common I/O using three-state output
Data retention voltage: 1.2V (min.)
Available in 44-pin TSOP and 48-ball CSP packages
Product Family
Power Dissipation
Product Family
Operating
Temperature
VCC Range
Speed
Data Retention
(ICCDR, Typ.)
Standby
(ISB1, Typ.)
Operating
(ICC2, Typ.)
LP62E16256E
-25°C ~ +85°C
1.65V~2.2V
70ns
0.2µA
1.4µA
2mA
Package
Type
44L TSOP
48B CSP
1. Typical values are measured at VCC = 2.0V, TA = 25°C and not 100% tested.
2. Data retention current VCC = 1.2V.
Pin Configurations
̈ TSOP
̈ CSP (Chip Size Package)
48-pin Top View
1
44
A5
2
43
A6
A2
3
42
A7
A1
4
41
OE
A0
5
40
HB
39
LB
38
I/O16
37
I/O15
36
I/O14
35
I/O13
34
GND
33
VCC
32
I/O12
31
I/O11
30
I/O10
29
I/O9
28
NC
27
A8
CE
6
I/O1
7
I/O2
8
I/O3
9
I/O4
10
VCC
11
GND
12
I/O5
13
I/O6
14
I/O7
15
I/O8
16
LP62E16256EV-T
A4
A3
WE
17
A17
18
A16
19
26
A9
A15
20
25
A10
A14
21
24
A11
A13
22
23
A12
(August, 2004, Version 1.2)
1
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
NC
B
I/O9
HB
A3
A4
CE
I/O1
C
I/O10
I/O11
A5
A6
I/O2
I/O3
D
GND
I/O12
A17
A7
I/O4
VCC
E
VCC
I/O13
NC
A16
I/O5
GND
F
I/O15
I/O14
A14
A15
I/O6
I/O7
G
I/O16
NC
A12
A13
WE
I/O8
H
NC
A8
A9
A10
A11
NC
AMIC Technology, Corp.
LP62E16256E-T Series
Block Diagram
VCC
A0
GND
512 X 8192
DECODER
MEMORY ARRAY
A16
A17
I/O1
I/O9
COLUMN I/O
INPUT
INPUT
DATA
CIRCUIT
DATA
CIRCUIT
I/O16
I/O8
CE
LB
HB
OE
WE
CONTROL
CIRCUIT
Pin Descriptions -- TSOP
Pin No.
Symbol
1 - 5, 18 - 27,
42 - 44
A0 - A17
6
CE
7 - 10, 13 - 16,
29 - 32, 35 - 38
I/O1 - I/O16
17
WE
Write Enable Input
39
LB
Lower Byte Enable Input (I/O1 to I/O8)
40
HB
Higher Byte Enable Input (I/O9 to I/O16)
41
OE
Output Enable Input
11, 33
VCC
Power
12, 34
GND
Ground
28
NC
(August, 2004, Version 1.2)
Description
Address Inputs
Chip Enable Input
Data Inputs/Outputs
No Connection
2
AMIC Technology, Corp.
LP62E16256E-T Series
Pin Description - CSP
Symbol
A0 - A17
CE
Description
Symbol
Description
Address Inputs
HB
Higher Byte Enable Input
(I/O9 - I/O16)
Chip Enable
OE
Output Enable
I/O1 - I/O16
Data Input/Output
VCC
Power Supply
WE
Write Enable Input
GND
Ground
LB
Byte Enable Input
(I/O1 - I/O8)
NC
No Connection
Recommended DC Operating Conditions
(TA = -25°C to + 85°C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
1.65
1.8 / 2.0
2.2
V
0
0
0
V
VCC
Supply Voltage
GND
Ground
VIH
Input High Voltage
1.4
-
VCC + 0.2
V
VIL
Input Low Voltage
-0.2
-
+0.4
V
CL
Output Load
-
-
30
pF
TTL
Output Load
-
-
1
-
(August, 2004, Version 1.2)
3
AMIC Technology, Corp.
LP62E16256E-T Series
Absolute Maximum Ratings*
*Comments
VCC to GND .............................................. -0.5V to +3.0V
IN, IN/OUT Volt to GND................... -0.5V to VCC + 0.5V
Operating Temperature, Topr ...................-25°C to +85°C
Storage Temperature, Tstg.....................-55°C to +125°C
Power Dissipation, PT....................................................................... 0.7W
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended.
Exposure to the absolute
maximum rating conditions for extended periods may affect
device reliability.
DC Electrical Characteristics (TA = -25°C to + 85°C, VCC = 1.65V to 2.2V, GND = 0V)
Symbol
Parameter
LP62E16256E-70LLT
Min.
Max.
Unit
Conditions
⏐ILI⏐
Input Leakage Current
-
1
µA
⏐ILO⏐
Output Leakage Current
-
1
µA
Active Power Supply Current
-
5
mA
CE = VIL, II/O = 0mA
-
30
mA
* Min. Cycle, Duty = 100%
ICC
ICC1
ISB
CE = VIL, VIH = VCC,
VIL = 0V, f = 1MHz,
II/O = 0 mA
-
10
mA
-
0.5
mA
CE = VIH
-
10
µA
CE ≥ VCC - 0.2V,
VIN ≥ 0V
Standby Current
ISB1
CE = VIH
HB = VIH or OE = VIH or
WE = VIH
VI/O = GND to VCC
CE = VI, II/O = 0mA
Dynamic Operating
Current
ICC2
VIN = GND to VCC
VOL
Output Low Voltage
-
0.2
V
IOL = 0.1 mA
VOH
Output High Voltage
1.4
-
V
IOH = -0.1 mA
(August, 2004, Version 1.2)
4
AMIC Technology, Corp.
LP62E16256E-T Series
Truth Table
I/O1 to I/O8 Mode
I/O9 to I/O16 Mode
VCC Current
CE
OE
WE
LB
HB
H
X
X
X
X
Not selected
Not selected
ISB1, ISB
X
X
X
H
H
High - Z
High - Z
ISB1, ISB
L
L
Read
Read
ICC1, ICC2, ICC
L
H
Read
High - Z
ICC1, ICC2, ICC
H
L
High - Z
Read
ICC1, ICC2, ICC
L
L
Write
Write
ICC1, ICC2, ICC
L
H
Write
High - Z
ICC1, ICC2, ICC
H
L
High - Z
Write
ICC1, ICC2, ICC
L
L
L
X
H
L
L
H
H
L
X
High - Z
High - Z
ICC1, ICC2, ICC
L
H
H
X
L
High - Z
High - Z
ICC1, ICC2, ICC
Note: X = H or L
Capacitance (TA = 25°C, f = 1.0MHz)
Symbol
Parameter
Min.
Max.
Unit
Conditions
CIN*
Input Capacitance
6
pF
VIN = 0V
CI/O*
Input/Output Capacitance
8
pF
VI/O = 0V
* These parameters are sampled and not 100% tested.
(August, 2004, Version 1.2)
5
AMIC Technology, Corp.
LP62E16256E-T Series
AC Characteristics (TA = -25°C to +85°C, VCC = 1.65V to 2.2V)
Symbol
LP62E16256E-70LLT
Parameter
Unit
Min.
Max.
70
-
ns
Read Cycle
tRC
Read Cycle Time
tAA
Address Access Time
-
70
ns
tACE
Chip Enable Access Time
-
70
ns
tBE
Byte Enable Access Time
-
70
ns
tOE
Output Enable to Output Valid
-
35
ns
tCLZ
Chip Enable to Output in Low Z
10
-
ns
tBLZ
Byte Enable to Output in Low Z
10
-
ns
tOLZ
Output Enable to Output in Low Z
5
-
ns
tCHZ
Chip Disable to Output in High Z
-
25
ns
tBHZ
Byte Disable to Output in High Z
-
25
ns
tOHZ
Output Disable to Output in High Z
-
25
ns
tOH
Output Hold from Address Change
5
-
ns
tWC
Write Cycle Time
70
-
ns
tCW
Chip Enable to End of Write
60
-
ns
tBW
Byte Enable to End of Write
60
-
ns
tAS
Address Setup Time
0
-
ns
tAW
Address Valid to End of Write
60
-
ns
tWP
Write Pulse Width
55
-
ns
tWR
Write Recovery Time
0
-
ns
tWHZ
Write to Output in High Z
-
25
ns
tDW
Data to Write Time Overlap
30
-
ns
tDH
Data Hold from Write Time
0
-
ns
tOW
Output Active from End of Write
5
-
ns
Write Cycle
Note: tCHZ, tBHZ and tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are
not referred to output voltage levels.
(August, 2004, Version 1.2)
6
AMIC Technology, Corp.
LP62E16256E-T Series
Timing Waveforms
Read Cycle 1(1, 2, 4)
tRC
Address
tAA
tOH
tOH
DOUT
Read Cycle 2(1, 2, 3)
tRC
Address
tAA
CE
tACE
tCHZ5
tCLZ5
tBE
HB, LB
tBLZ5
tBHZ5
OE
tOE
tOHZ5
tOLZ5
DOUT
Notes:
1. WE is high for Read Cycle.
2. Device is continuously enabled CE = VIL, HB = VIL and, or LB = VIL.
3. Address valid prior to or coincident with CE and ( HB and, or LB ) transition low.
4. OE = VIL.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
(August, 2004, Version 1.2)
7
AMIC Technology, Corp.
LP62E16256E-T Series
Timing Waveforms (continued)
Write Cycle 1
(Write Enable Controlled)
tWC
Address
tWR3
tAW
tCW
CE
tBW
HB, LB
tAS1
tWP2
WE
tDH
tDW
DATA IN
tWHZ4
tOW
DATA OUT
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
tAW
tAS1
tWR3
tCW2
CE
tBW
HB, LB
tWP
WE
tDW
tDH
DATA IN
tWHZ4
tOW
DATA OUT
(August, 2004, Version 1.2)
8
AMIC Technology, Corp.
LP62E16256E-T Series
Timing Waveforms (continued)
Write Cycle 3
(Byte Enable Controlled)
tWC
Address
tAW
tCW
CE
tAS1
tWR3
tBW2
HB, LB
tWP
WE
tDH
tDW
DATA IN
tWHZ4
tOW
DATA OUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP, tBW) of a low CE , WE and ( HB and , or LB ).
3. tWR is measured from the earliest of CE or WE or ( HB and , or LB ) going high to the end of the Write cycle.
4. OE level is high or low.
5. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
(August, 2004, Version 1.2)
9
AMIC Technology, Corp.
LP62E16256E-T Series
AC Test Conditions
Input Pulse Levels
0.2V to VCC -0.2V
Input Rise And Fall Time
5 ns
Input and Output Timing Reference Levels
0.9V
Output Load
See Figures 1 and 2
TTL
TTL
CL
CL
5pF
30pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ, tOLZ,
tCHZ, tOHZ, tWHZ, and tOW
Data Retention Characteristics (TA = -25°C to 85°C)
Symbol
Parameter
Min.
Max.
Unit
VDR
VCC for Data Retention
1.2
2.2
V
ICCDR
Data Retention Current
-
5*
µA
tCDR
Chip Disable to Data Retention Time
0
-
ns
tRC
-
ns
5
-
ms
tR
Operation Recovery Time
tVR
VCC Rising Time from Data Retention Voltage
to Operating Voltage
* LP62E16256E-70LLT
(August, 2004, Version 1.2)
ICCDR: max.
Conditions
CE ≥ VCC - 0.2V
VCC = 1.2V,
CE ≥ VCC - 0.2V
VIN ≥ 0V
See Retention Waveform
1µA at TA = 0°C to + 40°C
10
AMIC Technology, Corp.
LP62E16256E-T Series
Low VCC Data Retention Waveform
DATA RETENTION MODE
1.65V
1.65V
VCC
tCDR
tR
VDR ≥ 1.2V
tVR
VIH
CE
VIH
CE ≥ VDR - 0.2V
Ordering Information
Part No.
Access Time (ns)
Operating Current
Max. (mA)
Standby Current
Max. (µA)
LP62E16256EV-70LLT
Package
44L TSOP
LP62E16256EV-70LLTF
44L Pb-Free TSOP
70
30
10
LP62E16256EU-70LLT
48L CSP
LP62E16256EU-70LLTF
48L Pb-Free CSP
(August, 2004, Version 1.2)
11
AMIC Technology, Corp.
LP62E16256E-T Series
Package Information
TSOP 44L TYPE II Outline Dimensions
unit: inches/mm
HE
0.254
23
E
44
L
L1
1
22
B
e
D
S
Symbol
y
A
Dimension in inch
Min.
L1
L
A1
A2
c
D
Nom.
Max.
Dimension in mm
Min.
Nom.
Max.
A
-
-
0.047
-
-
1.20
A1
0.002
-
-
0.05
-
-
A2
0.037
0.039
0.041
0.95
1.00
1.05
B
0.010
0.014
0.018
0.25
0.35
0.45
c
-
0.006
-
-
0.15
-
D
0.721
0.725
0.729
18.31
18.41
18.51
E
0.396
0.400
0.404
10.06
10.16
10.26
e
-
0.031
-
-
0.80
-
HE
0.455
0.463
0.471
11.56
11.76
11.96
L
0.016
0.020
0.024
0.40
0.50
0.60
L1
-
0.031
-
-
0.80
-
S
-
-
0.036
-
-
0.93
y
-
-
0.004
-
-
0.10
θ
0°
-
5°
0°
-
5°
Notes:
1. Dimension D&E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
(August, 2004, Version 1.2)
12
AMIC Technology, Corp.
LP62E16256E-T Series
Package Information
48LD CSP ( 6 x 8 mm ) Outline Dimensions
unit: mm
(48TFBGA)
TOP VIEW
BOTTOM VIEW
Ball#A1 CORNER
0.10 S C
0.25 S C A B
Ball*A1 CORNER
b (48X)
6 5 4 3 2 1
1 2 3 4 5 6
A
B
A
C
D
E
D
E
E1
e
B
C
E
F
F
G
G
H
H
B
e
D1
A
0.10 C
A2
0.20(4X)
SEATING PLANE
A1
(0.36)
C
D
Symbol
A
A1
A2
D
E
D1
E1
e
b
A
// 0.25 C
SIDE VIEW
Dimensions in mm
MIN.
NOM.
MAX.
1.00
0.20
0.48
5.90
7.90
------0.30
1.10
0.25
0.53
6.00
8.00
3.75
5.25
0.75
0.35
1.20
0.30
0.58
6.10
8.10
------0.40
Note:
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS
OF THE SOLDER BALLS.
3. DIMENSION b IS MEASURED AT THE MAXIMUM.
THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF THE
SOLDER BALL AND THE BODY EDGE.
(August, 2004, Version 1.2)
13
AMIC Technology, Corp.
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