1203 kagiyama isqed

1203 kagiyama isqed
Bit Error Rate Estimation in SRAM Considering Temperature Fluctuation
Yuki Kagiyama1*, Shunsuke Okumura1, Ko ji Yanagida1, Shusuke Yoshimoto1
Yohei Nakata1, Shintaro Izumi1, Hiroshi Kawaguchi1, and Masahiko Yoshimoto 1, 2
1
Kobe University, Japan, 2JST CREST, Japan
*
E-mail: kagiyama@cs28.cs.kobe-u.ac.jp
Wordline (WL)
Abstract
SRAM performance varies depending on the operating
environment. This study specifically examines the bit error
rate (BER) when considering temperature fluctuation. The
SRAM performance is generally determined using a read
margin because a half-select issue must be considered even
in a write operation. As a metric of the SRAM’s
performance, we also adopt a static noise margin (SNM)
with which we evaluate three methods to estimate the BER
considering temperature fluctuation. Method 1 iterates
calculations for the SNM many times with Monte Carlo
simulation. BER is defined as the number of cells that have
no margin. Method 2 includes the assumption that SNM
forms a normal distribution. Its BER is defined as a
probability distribution function. Method 3 includes the
assumption that SNM is determined as either square but not
the smaller one of the two squares. The BER estimations are
compared with a test chip result implemented in a 65-nm
CMOS technology: Method 2 has 11.10% and Method 3 has
4.09% difference (unfortunately, Method 1 has no data
missing because of a lack of simulations). The shift of the
minimum operating voltage between the low and high
temperatures is 0.04 V at a 128-Kb capacity when the
temperature fluctuates from 25°C to 100°C.
n0
VDD
VDD
p0
p1
N0
N1
n2
n1
n3
Bitline (BL)
/Bitline (/BL)
Figure 1: Schematic of a 6T bitcell.
Figure 1 depicts a schematic of a commonly used sixtransistor (6T) bitcell. The 6T bitcell consists of load
transistors (p1 and p0), access transistors (n0 and n1), and
drive transistors (n2 and n3). The SNM is obtainable from
butterfly curves, which physically represent a metric of the
read operation stability [3]. The butterfly curves reflect the
two inverters’ and access transistors’ characteristics [4]. The
SNM is described in the next section.
As explained herein, we verify three BER estimation
methods and compare measured BER with results of these
estimation methods considering temperature fluctuation.
Keywords
2. Temperature Dependences in SRAM
2.1. Transistor characteristics
SRAM, bit error rate, static noise margin, temperature
fluctuation
First, we must understand the temperature characteristics
of a transistor to consider their impacts on the SNM. The
main temperature-dependent parameters are a threshold
voltage (Vth) and mobility () [5]. The temperature
dependence can be expressed as
1. Introduction
Recently, LSIs have been widely used in various
environments. The LSI performance varies depending on the
operating environment. The SRAM characteristics are also
affected b y the environment. Herein, we specificall y
examine the bit error rate (BER) of the SRAM when
considering temperature fluctuation. The BER can be a
metric determining a minimum operating voltage (Vmin) of
the SRAM if the SRAM capacity is known. It is necessary to
estimate the BER during a design phase for maintaining
SRAM reliability. In the SRAM, the read margin decreases
at high temperature, although a write margin has the
opposite characteristics [1]. We estimate the read
performance using a static noise margin (SNM) because the
operating margin of the SRAM is determined by the read
margin [2]. A half-select issue must be considered even for
the write operation.
Vth (T )  Vth (T0 )   (T  T0 ) and
T 

 T0 
 (T )   (T0 )
(1)
m
,
(2)
where T signifies a temperature, T0 stands for a reference
temperature, denotes a temperature coefficient, and m
represents a process-dependent parameter (ca. 2). Both Vth
and  decrease with T. Furthermore, the drain current (Ids)
changes along with the temperature fluctuation. In a
saturated region, Ids is
I ds (T ) 

2
 (T )(Vgs  Vth (T )) 2 ,
(3)
where  is a transistor coefficient [6]. Ids is affected
differently by either Vth or . A lower Vth increases Ids, but a
lower  decreases it. Ids decreases with T because  gives
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514
13th Int'l Symposium on Quality Electronic Design
more impact on Ids if Vgs (voltage between the gate and
source) is high (although Ids increases with T if Vgs is low).
2.2. Static noise margin and bit error rate
The temperature dependence of the SNM can be
described based on the transistor characteristics (particularly
Vth and Ids). To estimate SNM, two bitlines (BLs) and a
wordline (WL) are connected to a supply voltage (VDD). In
this state, the voltage of the other node (N1) is rapidly
decreased from a certain point if a voltage of an internal
node (N0) is forced to be increased to VDD from the ground.
Figure 2 presents this drop voltage (Vdrop), which depends on
Vth of n3. Similarly, the other curve of VN0 (N0’s voltage) is
obtainable by changing VN1 (N1’s voltage). These two
curves form butterfly curves with two eyes. The smaller
square inscribed in the eyes is generally defined as an SNM.
The SNM depends on VDD and Ids [7]. If a bitcell has no
SNM, then it is an unreadable cell. The ratio of unreadable
cells to overall SRAM capacity is the BER, which is an
important metric for estimating the minimum operating
voltage (Vmin). In fact, the temperature fluctuation and BER
affect Vmin.
TT corner, VDD = 1.0 V
SNM
@25℃
Vdrop
TT corner, Monte Carlo: 1000
0.1
μSNM
σSNM
0
0.6
0.7
VDD [V]
25℃
50℃
75℃
100℃
0.8
Figure 3: SNM and SNM at respective temperatures.
SNM
@100℃
4. BER Estimation Methods
VN1[V]
1.0
25℃
50℃
100℃
0
SNM degrades linearly according to the operating
voltage. Its slope shows similar dependence. This trend
exhibits the models of Vth, and Ids respectively in (1), (2),
and (3). In contrast, SNM is constant irrespective of the
voltage and temperature [8]. The SNM dependence of the
voltage and temperature is negligible. Based on the
discussion presented above, SNM and SNM
corresponding to a voltage and temperature can be estimated
easily by sampling a few simulations.
VN0[V]
Vfloat
1.0
Figure 2: SNM at each temperature at VDD = 1.0 V.
In Figure 2, at Vdrop, VN1 is pulled down by n3 in a
saturated region. As the temperature increases, VN1 decreases
considerably. When VN0 is VDD, VN1 is not turned off
completely. Therefore, it floats a little (= Vfloat). As Vdrop
does, Vfloat also depends on Ids of n3, and increases with T at
a high VDD. Actually, Vfloat decreases with T at a low VDD.
Consequently, SNM has temperature characteristics. The
figure presents an example of SNM when VDD = 1.0 V.
3. Voltage dependence of SNM
In an earlier section, it was explained that SNM has
temperature dependence. In addition, SNM has voltage
dependence [7]. To estimate BER, we obtain the trends of
SNM and SNM (average and standard deviation of the
SNM) at each temperature (25°C, 50°C, 75°C, and 100°C).
The voltage characteristics of the SNM were investigated
using Monte Carlo (MC) simulation at those temperatures.
The MC trials were 1000; VDD was 0.6–0.8 V, varying at
intervals of 0.02 V. Figure 3 presents simulation results.
Kagiyama, Bit Error Rate Estimation in SRAM …
We verify three BER estimation methods. Method 1
calculates the SNMs many times with the MC simulation. Its
BER is defined as a percentage of cells that have no SNM.
Method 2 assumes that the SNM forms a normal distribution.
Its BER is defined as a probability that the SNMs are less
than zero. Method 3 is almost identical to Method 2 except
for the SNM definition. For Method 3 SNM is determined as
another side of the two squares but not a smaller one.
Method 1 is accurate if the SRAM capacity is less than
the number of MC trials, but this means that a 10-Kb SRAM
requires tens of thousands of MC trials to estimate its BER
at a condition set of a voltage and temperature. More
simulation time is needed for more SRAM capacity, which
is increasing with a process technology trend. Figure 4
presents the distribution of the SNMs in Methods 2 and 3.
“Worst” corresponds to Method 2, and “Left” (or “Right”)
signifies Method 3. Table 1 presents average, standard
deviation, and skewness of the distributions.
Method 2 can save simulation time because this does not
require many iterations of the MC trials. It is sufficient to
obtain the average and standard deviation of the SNM by
running simulations a thousand times; the computation cost
is less than a tenth of that for Method 1. However, the SNM
distribution does not follow a normal distribution strictly
(Figure 4; Table 1). The definition of the “Worst” SNM in
Figure 4 and Table 1 takes a smaller square in both, but the
“Worst” case spreads lower than the “Left” and “Right”
cases. This can be recognized as skewness in the table,
which signifies a large negative value: the “Worst” case
distribution is asymmetry. Consequently, estimating the
SNM distribution is difficult when using the standard
deviation model.
3000
TT corner, 25℃, VDD = 0.8 V, Monte Carlo: 20000
Frequency
2500
5.1. Implementation
We implemented a 1-Mb SRAM in a 65-nm CMOS
process to measure a BER. Figure 6 displays a chip layout.
The SRAM configuration is 16-Kb block × 64 blocks, which
equals 1-M bits. The bitcell has a standard 6T topology.
Transistor sizing is  = 2 and  = 1, where  denotes the
ratio of a drive transistor to an access transistor, and 
represents the ratio of an access transistor to a load transistor.
Left
Right
2000
5. Measurement Results
Worst
1500
1000
500
0
0
0.05
0.1
0.15
0.2
0.25
SNM [V]
Figure 4: SNM distributions. “Left” and “Right” evaluate
only either square. “Worst” evaluates both squares.
1-Mb SRAM
(16-Kb block × 64)
Left
0.1176
0.0209
0.0032
Right
0.1179
0.0212
0.0034
Worst
0.1034
0.0157
0.3320
Decoder
Average [V]
S.D. [V]
Skewness
101 μm
Table 1: Average, standard deviation, and skewness of the
three distributions
16-Kb bitcell array
(128 rows × 8 columns
× 16 bits/words)
I/O
335 μm
Figure 6: Layout of a 1-Mb SRAM.
Method 3 uses only either square. The SNM distribution
is assumed as a normal distribution, although this method
does not represent an adequate margin of a cell. However, at
a very low SNM, the “Worst” case can be estimated as twice
of “Left” or “Right” (or a sum of “Left” and “Right”)
because the event of the very low SNM is rare.
Figure 5 presents probability density distributions of the
three methods. The MC trials are conducted 20000, 1000,
and 1000 times, respectively, in Methods 1, 2, and 3. The
distribution in Method 2 does not follow that of Method 1
because its distribution is skewed. However, Method 3 fits
with Method 1.
5.2. Bit Error Rates
We compare the BERs of estimation using the three
methods with the measured BER. Figure 7 presents the
results of comparison. In both the simulations and
measurements, the temperature condition is 25°C. The other
conditions are the same as those described in Section 4.
Assuming that the SNM is a normal distribution, SNM and
SNM are calculable in Methods 2 and 3. The SNM
probability density function becomes the following.
f ( SNM ) 
TT corner, 25℃
1.E-01
 SNM  SNM 2 
1
exp 

2SNM 2
2 SNM


(4)
TT corner, 25℃
1.E-01
Measurement
1.E-03
Method 1
1.E-03
1.E-04
Method 2
1.E-05
1.E-06
Method 2
Method 1
Method 3
0.03
0.04
0.05
SNM [V]
0.06
0.07
Figure 5: Probability density distributions of three methods.
BER
Probability
1.E-02
Method 3
1.E-05
1/128K
-4.09%
1.E-07
-11.10%
1.E-09
0.6
0.65
0.7
VDD [V]
0.75
Figure 7: BER Comparison.
Kagiyama, Bit Error Rate Estimation in SRAM …
0.8
The simulated BER is the probability at which the
calculated SNM is less than zero. Data in Method 1 cannot
be shown at a lower BER region because of the iteration of
the MC simulation. The BER slope in Method 2 does not fit
to the measurement because its SNM distribution is skewed
and not a normal distribution. The BER in Method 3 is the
closest to the measurement. The simulated BER still has an
error compared with the measurement, which is regarded as
a mismatch of the simulation model.
In addition, the simulated Vmin has an error between the
measurement and each method. At a capacity of 128 Kb, the
respective errors of Methods 2 and 3 to the measurement are
11.10% and 4.09%. In Method 2, the error will increase
more with the SRAM capacity.
Temperature characteristics of the BER were measured
using a thermograph streamer. Figure 8 portrays the
measured BERs and estimated ones in Method 3. These
results show that Method 3 is useful to estimate the BER
dependence on the temperature and voltage. The read
operation margin is degraded at high temperature.
Furthermore, Vmin becomes higher. The measured Vmin shift
(Vmin) is 0.04 V at a BER of 1/128K when the temperature
changes from 25°C to 100°C. The estimated Vmin using
Method 3 is as much as 0.04 V, which demonstrates that the
BER slope in Method 3 matches that of the measurement.
methods. About Method 2 and Method 3, the
difference value of Vmin is 11.10 % and 4.09 %
respectively. Compared BER of Method 3 with
measurement result, Vmin is same values, and is both
0.04 V at 128-Kb capacity when temperature fluctuates
from 25°C to 100°C. Furthermore, it is confirmed that
BER slope corresponding temperature fluctuation is
estimated exactly. Furthermore, Vmin is predictable
with increasingly memory capacity using Method 3.
We confirmed most suitable method which can
estimate BER shift depending on the temperature, and
the method does not need enormous time simulation.
Acknowledgments
The VLSI chips in this study were fabricated in the chip
fabrication program of the VLSI Design and Education
Center (VDEC), The University of Tokyo, in collaboration
with STARC, e-Shuttle Inc., and Fujitsu Ltd.
References
[1]
TT corner, 25℃ and 100℃
1.E-01
[2]
0.04V
BER
1.E-03
1.E-05
1/128K
[3]
Measurement (100℃)
Measurement (25℃)
Method 3 (100℃)
1.E-07
1.E-09
0.04V
[4]
Method 3 (25℃)
0.6
0.65
0.7
VDD [V]
0.75
0.8
[5]
Figure 8: BERs with temperature fluctuation.
6. Conclusion
Recently, advanced technology enables increasingly
large capacity SRAM. The verification and simulation
of SRAM performance are require enormous time as
increased the memory capacity. .This study also verify
about the SRAM performance depending on the
temperature. We estimate characteristics corresponding
temperature fluctuation. To obtain tendencies of
average and standard deviation of SNM enabled to get
BER without enormous time simulation. We
implemented a 1-Mb SRAM chip in 65-nm CMOS
technology and confirmed the accuracy of three
Kagiyama, Bit Error Rate Estimation in SRAM …
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