A 62-dB SNDR Second-Order Gated Ring Oscillator TDC with Two-Stage Dynamic D-Type Flipflops as A Quantization Noise Propagator Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, and Hiroshi Kawaguchi Kobe University 1-1 Rokkodai, Nada, Kobe, 657-8501 Japan E-mail: email@example.com Abstract—This paper presents a second-order noise shaping time-to-digital converter (TDC) with two gated ring oscillators (GROs). The oscillating outputs from the GROs are counted and digitized. As a quantization noise propagator (QNP) between the two GROs, two-stage dynamic d-type flipflops (DDFFs) a NOR gate are adopted. The proposed QNP does not propagate a time error caused by flipflop’s metastability to the next GRO, and thus improves its linearity over the conventional master-slave dtype flipflop. In a standard 65-nm CMOS process, an SNDR of 62-dB is achievable at a sampling rate of 65MS/s. I. INTRODUCTION Designing high-performance and low-power chips at lowcost is necessary to produce competitive information and communications equipment. Scaling in process technology has enabled the miniaturization of transistors. Consequently, the number of transistors in a device is increasing; low-cost functionality of digital systems can be developed. Low-power features are achieved by reducing supply voltage. For analog circuits, however, deriving benefits from scaling is difficult. Low-voltage operation reduces a dynamic range. Linearity becomes degraded, and gain in an opamp is lessened. To compensate for these disadvantages, transistor sizing and the area of passive components are ever-increasing; a mixed-signal chip comprising digital and analog circuitry can achieve neither low cost nor low power in a recent advanced process. An analog-to-digital converter (ADC) is a critical component of mixed-signal circuits, in which opamps and capacitors prevent merits derived from scaling, particularly in a ΔΣ ADC. Several ADCs operating in a time domain have been examined recently. A voltage-controlled oscillator (VCO) is used –, in which a VCO frequency varies depending on an analog input voltage. A multi-bit quantizer counts the rising edges of the oscillation. This type of ADC is called a VCObased ADC. Another type of ADC uses a time-to-digital converter (TDC) that converts an analog time into a digital datum. Combining a TDC with a voltage-controlled delay line (VCDL) and an asynchronous delta sigma modulator (ADSM) has been reported as an ADC . The TDC has been also developed and assessed as an internal circuit of a phase lock loop (PLL). As a TDC, the gated ring oscillator TDC (GROTDC) has been studied that uses a ring oscillator comprising gated inverters . Figure 1 portrays a GROTDC circuit diagram. A pulse width (TIN) is input to a GROTDC as a time-varying analog datum. During TIN, the GROTDC quantizes it with a counter by counting up the oscillation, GROOUT. Then, the count datum is shown as a discrete value. It is noteworthy that this GROTDC has a first-order noise shaping characteristic, but in the literature, its function as the first-order modulator is merely exhibited. TIN TIN GROOUT GROOUT TIN Counter RB TIN DOUT Figure 1 Gated ring oscillator time-to-digital converter (GROTDC). II. HIGH-ORDER GROTDC High-order noise shaping GROTDC architecture has been reported as presenting the possibility of propagating the quantization noise using a d-type flipflop (DFF) and of realizing higher performance using a GROTDC -. Figure 2 portrays a second-order multi-stage noise shaping (MASH) GROTDC architecture, which employs GROTDCs as ΔΣ modulators. The counters are quantizers. The quantization noise propagator (QNP) consists of a conventional masterslave d-type flipflop (MSDFF) propagates the quantization noise to the next stage. GROTDC QNP TIN “H” TQN D Q RB GROOUT1 III. PROPOSED LOW-JITTER DYNAMIC D-TYPE FLIPFLOP As shown in Figure 4, we propose a dynamic d-type flipflop (DDFF) to minimize the metastability; the DDFF can be comprised of only six transistors because a data input is fixed to “high”. The simple DDFF operates faster than the conventional MSDFF, and thus is resilient to the metastability. As well, its linearity and operating frequency are better than the MSDFF. GROOUT2 Counter RB DOUT1 The MSDFF QNP, however, produces a large jitter in a time domain because of its metastability. When a rising edge of GROOUT1 and a rising edge of TIN are close, the metastability occurs. The MSDFF QNP cannot propagate a correct quantization noise because it takes a long time to stabilize its output in the metastable state. As a result, the MSDFF QNP worsens the second-order noise shaping characteristic. T Counter RB TIN TIN DOUT2 QB Clock Clock DSP TDCOUT Figure 3 shows a timing diagram of the conventional second-order GROTDC. When TIN is high, the first-stage GRO oscillates. When is low, it ceases the oscillation and maintains the output phase state. The QNP is reset by a low state of TIN, and detects the first rising of GROOUT1. Thus, the QNP propagates TQN that contains a quantization noise to the next GRO. DOUT1 (DOUT2) denotes the number of GROOUT1 (GROOUT2) oscillations in the sampling period. DOUT1 (DOUT2) includes QN1 (QN2) representing a quantization noise of GROOUT1 (GROOUT2). By correctly propagating QN1 to the second-stage GRO and cancelling it using DOUT1 and DOUT2, the GROTDC achieves a second-order noise shaping characteristic. That is, the performance of the QNP as a propagator is crucial for the high-order GROTDC. Sampling period TIN[n]=DOUT1[n]−QN1[n−1]+QN1[n] TIN TIN[n−1] TIN[n] GROOUT1 QN1[n−1] DOUT1=9 QN1[n] DOUT1=10 DOUT1 TQN[n]=DOUT1[n]−1+QN1[n] TQN TQN[n−1] TQN[n] Clock QB Second-order MASH GROTDC architecture. Clock-to-QB delay Reset Figure 4 Schematic and timing diagram of the proposed DDFF. Figure 5 compares “Clock-to-QB” delay characteristics in the conventional MSDFF and proposed DDFF. In the figure, T is defined as a time interval from the rising edge of “Reset” to the first rising edge of “Clock”. If they are close each other, the metastability occurs. 500 MSDFF DDFF Clock-to-QB delay [ps] Figure 2 Reset 405.0 ps 400 Metastable region 76.6 ps 324.0 ps 300 277.0 ps 14.6 ps 200 129.0 ps 100 36.8 ps 0 -150 -100 -50 0 50 Time interval T [ps] GROOUT2 QN2[n−1] DOUT2=9 QN2[n] DOUT2=9 DOUT2 Figure 3 Timing diagram of GROTDC Figure 5 “Clock-to-QB” delay characterictics. Normally, the respective delays are 129.0 ps and 36.8 ps in the MSDFF and the DDFF; the proposed DDFF is four times faster. The delays are deteriorated in the metastable regions. IV. PROPOSED QNP WITH TWO-STAGE DDFFS To mask the metastable region and achieves the faster operation, we propose a novel QNP using the DDFFs. As shown in Figure 6, the proposed QNP has two DDFFs and a NOR gate. Figure 7 shows a timing diagram of the proposed QNP. D GROOUT1 QB 2.8 2.8 2.4 2.4 2.0 2.0 0 1.111 Ideal QN1 [ns] QB Figure 8 DDFF1OUT TQN DDFF R TIN Proposed QNP comprising two-stage DDFFs.. TIN GROOUT1 1 2 Transfer characteristics of MSDFF and two-stage DDFF V. IMPLEMENTATION RESULTS Figure 9 shows the negative impact of the metastability in the second-order MASH GROTDC with the conventional MSDFF in a 65-nm process. In this simulation, the GRO oscillates at 2.17 GHz (the oscillating period is 460 ps). The sampling rate is 65MS/s. In every sampling period, an incorrect quantization noise is injected at a possibility of 20%, which causes metastability. The second-order noise shaping characteristic is not achievable if the metastability exists. Figure 10 compares simulation results between the MSDFF and the proposed QNP. The GROTDC with the proposed QNP, which can accurately propagate a quantization noise, exhibits the second-order noise shaping characteristic. Its SNDR is 62 dB, whereas that in the GROTDC with the MSDFF is lowered to 52 dB. DDFF1OUT — With 20% of metastable states — No metastable state (ideal) Clock-to-QB delay DDFF2OUT TQN[n] Timing diagram of the proposed QNP. DDFF1OUT denotes the output of the first-stage DDFF. DDFF1OUT is delayed if metastability occurs. At the secondstage DDFF, however, metastability never occurs unless the oscillation period of GROOUT1 is shorter than 324.0 ps (see Figure 5 for a metastable delay of 324.0 ps in the DDFF). This is the reason why we prepare the two-stage DDFF, with which a correct quantization noise can be fed to the next GRO. Figure 8 shows propagation characteristics of the MSDFF and the proposed QNP; the linearity of QN1 is evaluated. The oscillating frequency of GROOUT1 is set to 900 MHz. In the MSDFF, the mismatch is as much as 277.0 ps (see Figure 5). Magnitude [dB] 0 TQN[n]=DOUT1[n]−2+QN1[n] Figure 7 1.111 DDFF D TQN 277 ps 1.6 1.6 DDFF2OUT R Figure 6 — MSDFF — Two-stage DDFFs Output QN1 [ns] The widths of the metastable regions are 76.6 ps and 14.6 ps, respectively in the MSDFF and DDFF; the metastable region, which is a sensitive timing, is five times narrower in the proposed DDFF. -20 -40 -60 -80 0.1 1 10 Frequency [MHz] Figure 9 Output spectra in the GROTDC with the conventional MSDFF. — MSDFF — Two-stage DDFFs Magnitude [dB] 0 the proposed TDC. A three-order or multiple-order TDC will be possible in our proposed TDC architecture. ACKNOWLEDGMENT -20 This study was granted by STARC. The chip design was supported by The VLSI Design and Education Center (VDEC) of The University of Tokyo in collaboration with Synopsys Inc., Cadence Design Systems Inc., and Mentor Graphics Corp. -40 -60 REFERENCES  -80 0.1 1 10  Frequency [MHz] Figure 10 Output spectra in the GROTDCs with the conventional and the proposed QNP. VI. SUMMARY We described a 62-dB second-order GROTDC. The second-order noise shaping characteristic is achieved by a novel QNP with two-stage DDFFs that propagate a correct quantization noise. The proposed architecture obviates analog circuits such as opamps and switched capacitors. The control of the TDC is implemented with digital circuits. The proposed TDC thereby maintains scalability with future advanced processes. As process technology advances, the ring oscillator frequency is expected to increase, which will be beneficial for      V. Dhanasekaran, M. Gambhir, M. M. Elsayed, E. Sanchez-Sinencio, J. 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