Managing Leakage in Charge-Based Analog Circuits with Low-V TH Transistors by Analog T-Switch (AT-Switch) and Super Cut

Managing Leakage in Charge-Based Analog Circuits with Low-V TH Transistors by Analog T-Switch (AT-Switch) and Super Cut
8-3
Managing Leakage in Charge-Based Analog Circuits with Low-VTH Transistors by
Analog T- Switch (AT-Switch) and Super Cut-off CMOS
Koichi Ishida1, Kouichi Kanda2, Atit Tamtrakarn1, Hiroshi Kawaguchi3, and Takayasu Sakurai1
1
2
Center for Collaborative Research, University of Tokyo, Tokyo, Japan
Center for Collaborative Research, University of Tokyo, currently with Fujitsu Labs. Ltd., Kawasaki, Japan
3
Institute of Industrial Science, University of Tokyo, Tokyo, Japan
Phone: +81-3-5452-6253, Fax: +81-3-5452-6632, E-mail: ishida@iis.u-tokyo.ac.jp
Abstract
Analog T-switch scheme is introduced to suppress
subthreshold-leakage problems in charge-based analog
circuits such as switched capacitor and sample and hold
circuits. A 0.5-V sigma-delta modulator is manufactured in a
0.15-µm FD-SOI process with low VTH of 0.1V using the
concept. The scheme is compared with another leakage
suppressed scheme based on Super Cut-off CMOS
(SCCMOS) and the conventional circuit which are also
fabricated. The sigma-delta modulator based on analog
T-switch realizes 6-bit resolution through reducing non-linear
leakage effects while the conventional circuit and the scheme
based on SCCMOS can achieve 4-bit and 5-bit resolution,
respectively.
Keywords: subthreshold leakage, low VTH, FD-SOI, switched
capacitor, and sigma-delta modulator
Introduction
Low-voltage, low-power yet inexpensive VLSI's are
getting focus recently. To this end, analog building blocks
tend to be embedded in scaled digital circuits as a part of SoC
implemented with advanced VLSI technology.
Several sub-1V sigma-delta modulators and ADCs are
reported but all are implemented in a high-threshold voltage
process [1,2,3]. The International Technology Roadmap for
Semiconductors (ITRS) predicts that the threshold voltage
(VTH) of high-performance logic technology will ever
decrease. In the above-mentioned environments, very low
VTH process compatible with the mainstream scaled digital
circuits are to be used. In the low VTH process, however,
non-linear subthreshold leakage current can be a critical issue
on analog circuits in press [4].
To suppress the subthreshold-leakage problems for
switched capacitor (SC) circuit, a scheme based on Super
Cut-off CMOS (SCCMOS) [5] was proposed in press [4].
This scheme, however, handles voltage outside the power
rails and thus oxide-stress relaxed level shifter and a negative
voltage generator such as charge pump circuit is required [6].
In this paper, analog T-switch scheme, which can realize
reverse gate-source voltage (VGS) without voltages outside the
power rails, is introduced to suppress subthreshold leakage
for charge-based analog circuits, and the performance and
advantages are discussed by comparing with the conventional
122
4-900784-01-X
scheme and the SCCMOS scheme.
Circuit Design
Figure 1 shows a schematic of a switched capacitor
integrator using the proposed analog T-switch scheme for
leakage suppression. M1a ~ c and M2a ~ c are the analog
T-switch that consists of two series-connected MOSFET’s and
intermediate voltage controlling MOSFET. Figure 2 explains
why the leakage can be suppressed. The analog ground is set
to a proper voltage between VSS to VDD. VDD/2 is used as an
example in this paper. All MOS switches are driven by
non-overlapping clocks whose swing is between VSS to VDD.
During the sampling phase, the gate voltage of M3b is set to
VSS and that of M3a is set to VDD to cut them off deeply. When
the input signal is around VDD, which corresponds to upper
left figure in Fig. 2, the node “A” is set to VIN through M2a
and M2b. Although M3a is still leaky, the gate-source of M3b is
reversely biased by VDD/2 and M3b is completely cut off. If
VDD/2 is 0.25V, the leakage is reduced by two orders of
magnitude.
When the input signal is around VSS, as in upper right
figure, the gate-source of M3a is reversely biased although the
M3b is leaky. In this case, M5 is also reversely biased since the
node “B” is always set to VDD/2 through M4.
During the evaluation phase shown in the lower figures, the
gates of M1a and M1b are both set to VSS and the gates of M2a
and M2b are set to VDD to cut them off. The node “C” and
node “D” are connected to VDD/2 in this phase through M1c
and M2c respectively. Then, both of the VGS of M1b and M2b
are reversely biased and they are deeply cut off even though
M1a and M2a are leaky. M4 is also reversely biased since the
node “B” is always set to VDD/2 through the M5. Since this
integrator scheme is insensitive to parasitic capacitances
integrator, added parasitic capacitance introduced by the
proposed scheme do not affect the operation [7].
Experimental Results and Discussion
Both of the analog T-switch scheme and the conventional
scheme are applied to 1st-order low-pass sigma-delta
modulators implemented in the afore-mentioned 0.15-µm
FD-SOI technology. The same circuit topology, parameters,
and layout style except for the switch array are adopted in
order to fairly compare various switched-capacitor circuits.
The circuit is operated under 0.5-V VDD.
2005 Symposium on VLSI Circuits Digest of Technical Papers
Figure 3 shows measured SNR’s and SNDR’s. For the
comparison, SNDR by SCCMOS scheme is also plotted. The
conventional scheme achieves the peak SNR of 44dB. The
SNDR of the conventional scheme, however, is degraded to
31.5dB which is below 5-bit resolution. The maximum power
consumption is 71µW. The proposed scheme achieves the
peak SNDR of 39.6dB which realizes more than the 6bit
resolution with the maximum power consumption of 75µW.
The peak SNDR and the dynamic range are improved over
the conventional approach at the same time. The SNDR by
the analog T–switch exceeds that of the SCCMOS by 5.8dB.
This result indicates that the analog T-switch scheme can cut
off the leakage more deeply than the SCCMOS approach
since more reverse VGS is applicable without voltage
over-stress across gate oxide.
The cause of the degradation of SNDR in the conventional
approach due to the charge loss associated with the leakage of
low-VTH transistors is shown in Fig. 4. This leakage current
introduces non-linear errors during the evaluation phase of SC
circuit and thus the error caused by the leakage current cannot
be compensated by digital manipulation.
Figure 5 shows measured output power spectra. The output
bit streams are processed using Matlab. The output spectrum
of the conventional scheme is taken at the input level of
–7.6dB and the large harmonic tones that degrade SNDR are
observed. This is due to the leakage current that introduces
non-linear errors. The proposed scheme shows the peak
SNDR at the input level of –7.6dB. It is seen that
higher-than-the-third order tones are greatly suppressed
compared with the conventional circuit.
The chip microphotographs of the sigma-delta modulator
using the analog T-switch, SCCMOS and the conventional
scheme are shown in Fig.6. Area is 130µm×190µm. Although
the switch transistor area of the analog T-switch increases to
3.3 times of the switch transistor area of the conventional
circuit, the switch array area is almost unchanged. This is
because the switch transistors are placed according to the
pitch of capacitors and even if the number of switch
transistors are more it does not give much area overhead.
TABLE I summarizes comparison between two types of
leakage suppressed switch scheme and the conventional
scheme.
There are two useful circuit configurations in the analog
T-switch family. One is an NMOS switch substitute and the
other is a PMOS switch substitute as shown in Fig. 7. The
analog T-switch version of the NMOS and PMOS switches
can be considered as leakage-suppressed NMOS and PMOS
switches, respectively, for wide range of applications. One of
such applications is found in a sample & hold circuit with
switched current configuration. SPICE simulation results on
the switched current sample & hold using the conventional
leaky switches and using the analog T-switch scheme are
shown in Fig.8. Device model employed is the
afore-mentioned 0.15-µm FD-SOI. The conventional leaky
switch cannot sufficiently cut off node TP from IN during a
hold phase. Since C1 is small, TP tends to tracks the voltage
of IN, and waveform is sinusoidal as a result. On the contrary,
TP is isolated from the node IN in the implementation with
the analog T-switches. The analog T-switch concept is
considered to be applicable to other charge-based analog
circuit.
Conclusion
Analog T-switch scheme is introduced and applied to a
0.5-V sigma-delta modulator implemented in a 0.1V-VTH
0.15-µm FD-SOI process and experimentally verified. The
analog T-switch realizes 6-bit resolution by reducing
non-linear leakage effects caused by the leakage and loss of
charge through low-VTH transistors. The performance of the
circuit based on the proposed analog T-switch exceeds that of
the SCCMOS and the conventional scheme. The analog
T-switch can be applied to extremely low-VTH devices even to
depletion MOSFET's, since reverse VGS is effectively
achieved without voltage over-stress to gate oxide.
The analog T-switch is shown to be also applicable to other
charge-based analog circuit using sample and hold circuit.
The proposed T-switch scheme and the SCCMOS both
suppress non-linear leakage-current effects in charge-based
analog circuits and boosts circuit performances in the
forthcoming leaky low-VTH transistor generations.
Acknowledgement
The authors would like to express deep appreciation to Mr.
F.Ichikawa, S.Baba, T.Chiba, K.Tani from Oki Electric
Industry Co., Ltd. for valuable support and chip fabrication,
and Dr. H.Ishikuro from Toshiba Corp. for fruitful
discussions.
References
[1] V. Peluso, P. Vancorenland, A. Marques, M. Steyaert, and W.
Sansen, "A 900-mV Low-Power �� A/D Converter with 77-dB
Dynamic Range," IEEE J. Solid-State Circuits, vol. 33, No. 12,
pp. 1887-1897, Dec. 1998.
[2] J.Sauerbrey, M. Wittig, D. Schmitt-Landsiedel, and R. Thewes,
"0.65V Sigma-Delta Modulators," Proc. of ISCAS, pp.
I1021-I1024, May 2003.
[3] J. Sauerbrey, D. Landsiedel, and R.Thewes, et al., “A 0.5-V
1-µW Successive Approximation ADC,” J. Solid State Circuits,
vol. 38, pp. 1261-1265, Jul. 2003.
[4] K. Ishida, K. Kanda, A. Tamtrakarn, H. Kawaguchi, and T.
Sakurai, "Subthreshold-Leakage Suppressed Switched Capacitor
Circuit Based on Super Cut-Off CMOS (SCCMOS)," Proc. of
ISCAS, 2005 (in press).
[5] H.Kawaguchi, K. Nose, and T. Sakurai, “A Super Cut-Off
CMOS (SCCMOS) Scheme for 0.5-V Supply Voltage with
Picoampere Stand-By Current,” J. Solid State Circuits, vol. 35,
pp. 1498-1501, Oct. 2000.
[6] K.Min, H. Kawaguchi, and T. Sakurai, “Zigzag Super Cut-off
CMOS (ZSCCMOS) Block Activation with Self-Adaptive
Voltage Level Controller: An Alternative to Clock-Gating
Scheme in Leakage Dominant Era,” ISSCC Dig. Tech.Papers,
pp.400-401, Feb. 2003.
[7] K. Martin, “Improved circuits for the realization of
switched-capacitor filters,” Trans. on CAS, pp. 237-244, Apr.
1980.
2005 Symposium on VLSI Circuits Digest of Technical Papers
123
�1
M1c
VDD/2
out
�2d
M3a M4
�2d
M3b
�1
VDD/2
VDD/2
VDD/2
VDD
VSS
VDD
VSS
�1
�1d
�1d
�2
�2d
�2
�2d
Sampling Phase(�1)
VDD
VIN � VSS
VDD/2
VDD
M1c
M1a
VIN
M1b
D
� VDD
A Cs
C
M2b
M2a
M3a
VDD
VSS
VSS
M5
B
M2c VSS
M3b
VDD/2
VDD/2
M4
VDD
VDD/2
VDD/2 ~ VDD
Reverse VGS
M1c
M1a
VIN
M1b
D
� VSS
A Cs B
C
M2b
M2a
M3a
VDD
VSS
M2c VSS
VDD/2
M3b
VDD/2
VSS
M5
M4
VDD
VDD/2
VDD/2 ~ VSS
Reverse VGS
Evaluating Phase (�2)
VDD/2
VSS
VDD/2
Reverse VGS
VSS
M1c
M1a
VIN
M2a
VDD
M1b
D
� VDD/2
A Cs B
C
M2b
VSS
M3a
M2c VDD
M3b
VDD/2
M1c
VDD
M4
M5
VSS
VDD/2
D
VDD/2
A Cs B
M2b
VSS
M3a
M2c VDD
M3b
VDD/2
Reverse VGS
� VDD/2
C
M2a
VDD
Reverse VGS
M1b
M1a
VIN
A
ILEAK
0.0
8% Error
VTH=0.1V
10-5
10-6
10-7
10-8
10-9
10-10
10-11
VDD
M5
M4
VSS
Leakage by M3
Leakage
by M1,M2
VTH=0.1V
VTH=0.3V
0.2 0.4
0.6
Time [µs]
0
-0.2
10
-0.4
100
-0.6
-0.8
0.8
0
-20
Measured SNR, SNDR [dB]
40
35
30
25
20
VDD :0.5V
FS :2MHz
BW :8kHz
Input:1.5kHz
10-1
@ 0.5MHz
@ 1MHz
@ 2MHz
10-2
0.25
0.4
Input Voltage VIN [V]
F S :2MHz, BW:8kHz
Input:1.5kHz,-7.6dB
-40
-60
-80
-100
-120
-140
0
-20
10
3
10 4
10
Frequency [Hz]
AT-Switch
5
10
6
F S :2MHz, BW:8kHz
Input:1.5kHz,-7.6dB
-40
-60
-80
-100
-120
-140
10
3
10 4
10
Frequency [Hz]
5
10
6
Fig.5. Measured output power spectra.
Opamp
VDD/2
Comparator
Reverse VGS
Capacitor Array
7bit
Output Buffer
Clock
Generator
6bit
8.1dB
5bit
Switch Array
4bit
(a) Whole sigma-delta modulator using proposed AT-switch
4.4dB
15
(b) Switch array of the SCCMOS
10
5
0
-50 -45 -40 -35 -30 -25 -20 -15 -10
Input Level [dB]
-5
0
Fig.3 Measured SNR’s and SNDR’s. The SNDR by SCCMOS is also
plotted for the comparison.
124
-1
0.1
Conventional
50
SNR by AT-Switch
SNDR by AT-Switch
SNR by Conventional
SNDR by Conventional
SNDR by SCCMOS
VDD : 0.5V 102
VTHP :- 0.2V
VTHN : 0.1V
AGND:0.25V
1
VDD/2
Fig.2. Principle of the analog AT-switch scheme. Subthreshold
leakage is suppressed by reverse-VGS handling voltage outside the
power rails.
45
103
0.2
�2
VTH=0.3V
VOUT
�1
Fig.4. Schematic, SPICE simulation, and Measured Leakage of a
conventional switched capacitor integrator.
VIN � VDD
Reverse VGS
0.2
0.1
0.0
M5
M3 M4
�1
0.0
Fig.1. Schematic of a switched capacitor integrator using the A
T-switch scheme. M1a-c and M2a-c are T-switch.
VDD/2
0.5
ILEAK [A]
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
�1
�1 ,�2[V]
M2c
�1d
M5
VOUT [V]
M2a
VDD/2
Cs
M1b
M2b
�2
Power Spectral Density [dB/bin]
M1a
in
M2
�2
VDD :0.5V
�1
FS :1MHz
VIN :0.2V
CS,CF:200fF
Power Spectral Density [dB/bin]
�1d
M1
VIN
(ILEAK × Sampling Time) / (CS × VIN)
Cf
Measured Leakage Current ILEAK [µA]
VDD/2
CF
�2
CS
4-900784-01-X
(c) Switch array of the conventional
Fig.6. The chip microphotographs of the sigma-delta modulator
analog T-switch, SCCMOS and the conventional
2005 Symposium on VLSI Circuits Digest of Technical Papers
TABLE I
SUMMARY OF COMPARISON ON LEAKAGE SUPPRESSED SWITCH SCHEME
AT -Switch
SCCMOS
Conventional
10 transistors
12 transistors
5 transistors
3.3**
4% of Total Area*
4.4**
5% of Total Area*
Required
3% of Total Area*
2**
5% of Total Area*
VSS to 1/2VDD (NMOS)
1/2VDD to VDD (PMOS)
VDDH(ex VDD+0.2V)
VSSL(ex VSS-0.2V)
(VDDH 0.6µW, VSSL 3.9µW)
Required
(Triple well, Deep n-well,
FDSOI))
Relaxed by Stack Structure
Low VTH
(ex. VTH=0.2V@0.5V VDD)
4**
1**
1% of Total Area*
Switch Array
Number of MOS in Each Integrator,
Schematic,
Layout
Level Shifter
1**
around 1/2VDD
Extra Supply Voltage
P-well Isolation
Oxide Stress
Inherently Free
Extremely Low-VTH (ex. <0.1V)
Depletion MOS
1**
Applicable VTH of MOS Switch
Parasitic Capacitance by M4, and M5
0.5V Sigma-Delta ADC
39.6dB
Peak SNDR
* Total area of sigma-delta modulator: 130µm×190µm
** Normalized by conventional
C1 [mV]
IIN [µA]
Leakage suppressed
NMOS Switch
VDD/2
NMOS Switch
Leakage suppressed
PMOS Switch
VDD/2
C1
OUT
TP
IIN
TP
OUT
C o n v e n t io n a l
0
-4 4 0
-4 6 0
1
1 .5
2
2 .5
3
T im e [ µ s ]
3 .5
4
4 .5
5
A T -S w itc h
0
-5 0 0
5
0
-5
VIN [mV]
IIN [µA]
0 .5
500
-3 5 0
-4 0 0
-4 5 0
-5 0 0
-2 0 0
0
-4 0 0
-4 2 0
-4 6 0
-5 0 0
0
Fig.7. Leakage suppressed switches using AT-switch scheme.
31.5dB
-5
TP [mV]
I2
C1
1**
5
-4 2 0
C1 [mV]
IIN
VDD/2
I1
Medium VTH
0
0
Leakage suppressed
Switched Current Sample & Hold
I2
Inherently Free
-5 0 0
-4 2 0
-4 4 0
-4 6 0
-4 8 0
OUT [mV]
I1
VSS to 1/2VDD (NMOS)
1/2VDD to VDD (PMOS)
500
-4 2 0
-4 4 0
-4 6 0
-4 8 0
PMOS Switch
Switched Current
Sample & Hold
1**
33.8dB
VIN [mV]
Applicable Analog GND
TP [mV]
Clock Bus Width
OUT [mV]
Switch Array Area
0 .5
1
1 .5
2
2 .5
3
T im e [ µ s ]
3 .5
4
4 .5
5
Fig. 8.Simulation results of switchet current sample & hold.
Upper: conventional leaky switch, Lower: AT-switch scheme.
2005 Symposium on VLSI Circuits Digest of Technical Papers
125
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