datasheet for XTR25010-BD by X
XTRM Series
XTR25010
HIGH TEMPERATURE POWER GATE DRIVER
FEATURES
DESCRIPTION
Supply voltage up to 40V.
Operational beyond the -60°C to +230°C temperature range.
Half-bridge driver.
Integrated charge pump.
Latch-up free.
Ruggedized SMT packages.
Also available as bare die.
Up to 6A peak current drive strength.
XTR25010 is a high-temperature, high reliability power transistor
driver integrated circuit designed to drive normally ON and normally-OFF power transistors in Silicon Carbide (SiC), Gallium
Nitride (GaN) and standard silicon, including JFETs,MOSFETs,
BJTs, SJTs and MESFETs.
For turning on the power transistors, the XTR25010 includes two
independent pull-up gate-drive-channels (PU_DR1 and PU_DR2)
capable of sourcing 3A peak current each. For turning off the
power transistors, the XTR25010 includes two pull-down gatedrive-channels capable of sinking 3A peak current each (PD_DR
and PD_MC).
For driving wide bandgap transistors, it is recommended to use
XTR25010 as a power stage extension for the XTR26010, which
generates the needed control signals and additional protection
functions (see XTR26010 datasheet and application note for
more details).
XTR25010 can also be used standalone as a half-bridge driver
for DC-DC converters and motor drive.
APPLICATIONS
Reliability-critical, Automotive, Aeronautics & Aerospace,
Down-hole.
Intelligent Power Modules (IPM).
Power inverters.
Power conversion and motor drive.
DC-DC converters and switched mode power supplies.
PRODUCT HIGHLIGHT
VDD
XTR40010
PWM_HS
VHV_BUS (1200V)
GND
VCC_HS
XTR25010
S_HS
VSUPPLY
XTR26010
VSS_HS
Isolated
Power
Supply
VCC_LS
XTR25010
S_LS
XTR26010
VSS_LS
GND
VDD (5V)
GND_BUS (0V)
VDD
PWM_LS
XTR40010
GND (0V)
GND
ORDERING INFORMATION
X

Source:
X = X-REL Semi
Product Reference
XTR25010-BD
XTR25011-LJ
TR

Process:
TR = HiTemp, HiRel
R = HiRel
Temperature Range
-60°C to +230°C
-60°C to +230°C
25

Part family
Package
Bare die
Ceramic LJCC52
010

Part number
Pin Count
Marking
52
XTR25011
Other packages and packaging configurations possible upon request.
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XTR25010
TYPICAL APPLICATION
Step-down (Buck) DC-DC Converter
CBST2
BST_DR2_P
BST_DR1_P
BST_DR1_N
CBST1
BST_DR2_N
VIN
7-40V
VCC
VCC_B
VCC_T
Cvin
Rswth
Cvdd
VIN
VDD
ENABLE
/LPMode
PVDD
IN_DR1
PVCC_DR2_2
IN_DR2
PVCC_DR2_1
Cpvdd
Rvin
Rpvdd
VCC_IO
PVCC_DR1_2
EN
XTR25010
HDrv
PU_DR1
PU_DR2
IN_MC
RT/SYNC
CKOUT
Cpvin
PVCC_DR1_1
Lout
SW
VOUT
IN_PD
SWT
PD_DR_2
LDrv
Resr
VDD
PD_MC_2
PVSS
AsyncEnbl
VSS
VOUT
PGND
DrvPol
GND
OCPMode
PVDD_PD
OCS
PVSS_PD_CAP
PVDD
Rocs
PSkipEnbl
PSkipTh
PD_DR_1
PVSS_MC_CAP
COMP
FB
PGood
IN_SSD
C3 C2 R4
PVDD_MC
XTR30011
Cout1
X7R
PD_MC_1
Cout2
NP0
PVSS_PD
PVSS_MC
SS/TR
Rss
CMC
R3
R2
CPD
C1
R1
Rsense
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XTR25010
ABSOLUTE MAXIMUM RATINGS
Supply voltage VCC_IO-PVSS
-0.5V to 44V
VCC, VCC_B, VCC_T, and PVCC_DRx_x
PVSS-0.5V to VCC_IO+0.5V
PVDD-PVSS
-0.5V to 5.5V
VDD, PVDD_PD and PVDD_MC
PVSS-0.5V to PVDD+0.5V
VSS, PVSS_MC, PVSS_PD
PVSS-0.5V to PVSS+0.5v
Inputs pins
EN, IN_SSD, IN_DR1, IN_DR2, IN_MC and IN_PD
PVSS-0.5V to PVDD+0.5V
Outputs pins
PD_MC_x and PD_DR_x
PVSS-0.5V to VCC_IO+0.5V
PU_DR1
PVSS-0.5V to PVCC_DR1+0.5V
PU_DR2
PVSS-0.5V to PVCC_DR2+0.5V
Storage Temperature Range
-70°C to +230°C
Operating Junction Temperature Range
-70°C to +300°C
ESD Classification
1kV HBM MIL-STD-883
Caution: Stresses beyond those listed in “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device. These are
stress ratings only and functionality of the device at these or any other condition beyond those indicated in the operational sections of
the specifications is not implied. Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may permanently
affect device reliability.
NC
IN_DR2
IN_DR1
IN_MC
PVSS_PD_CAP
PVDD_PD
PVSS_MC_CAP
PVDD_MC
PVSS
NC
VCC_B
20
IN_SSD
VCC_B
PACKAGING (LJCC52: J-FORMED LEADED CHIP CARRIER)
19
18
17
16
15
14
13
12
11
10
9
8
NC 21
7
PD_MC_2
NC 22
6
PVSS_MC
IN_PD 23
5
PD_MC_1
NC 24
4
PD_DR_2
VSS 25
3
PVSS_PD
VDD 26
2
PD_DR_1
1
PVCC_DR2_1
52
PU_DR2
EN 29
51
PVCC_DR2_2
NC 30
50
PVCC_DR1_1
NC 31
49
PU_DR1
NC 32
48
PVCC_DR1_2
47
NC
XTR25010
NC 27
NC
28
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© 2014 X-REL Semiconductor
39
40
41
42
PVDD
BST_DR2_N
BST_DR2_P
BST_DR1_N
BST_DR1_P
VCC
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PRELIMINARY
43
44
45
46
NC
38
VCC_B
37
VCC_T
36
VCC_IO
35
NC
VCC_B
34
PVSS
NC 33
www.x-relsemi.com
XTR25010
BLOCK DIAGRAM (XTR25010-BD)
Die level block diagram showing all available functionalities and bond-pads.
PIN DESCRIPTION (LJCC52: 52 LEAD J-SHAPED CHIP CARRIER)
Pin number
Name
Description
1
PVCC_DR2_1
Connect to positive supply voltage of PU_DR2 driver (PVCC_DR2).
2
PD_DR_1
Connect to output of the pull-down driver PD_DR_2.
3
PVSS_PD
Power VSS of PD driver. Connect to PVSS plane.
4
PD_DR_2
Connect to output of the pull-down driver PD_DR_1.
5
PD_MC_1
Connect to Miller Clamp pull-down driver PD_MC_2
6
PVSS_MC
Power VSS of MC driver. Connect to PVSS plane.
7
PD_MC_2
Connect to Miller Clamp pull-down driver PD_MC_1
8
VCC_B
Connect to power VCC plane.
9
NC
No internal connection.
10
PVSS
Power VSS. Connect to VSS through a local plane.
11
PVDD_MC
Top plate of bypassing capacitor of the Miller clamp (MC) pre-driver. Connect to PVDD plane.
12
PVSS_MC_CAP
Bottom plate of bypassing capacitor (100nF) of the Miller clamp (MC) pre-driver. This pin is internally
connected to PVSS_MC_1/PVSS_MC_2. Do not connect to VSS plane.
13
PVDD_PD
Top plate of bypassing capacitor of the pull-down (PD) pre-driver. Connect to PVDD plane.
14
PVSS_PD_CAP
Bottom plate of bypassing capacitor (100nF) of the pull-down (PD) pre-driver. This pin is internally
connected to PVSS_PD_1/PVSS_PD_2. Do not connect to VSS plane.
15
IN_MC
Digital Schmidt triggered input control signal of Active Miller Clamp pull-down driver PD_MC (0/5V vs.
VSS)
16
IN_DR1
Digital Schmidt triggered input control signal of pull-up driver PU_DR1 (0/5V vs. VSS).
17
IN_DR2
Digital Schmidt triggered input control signal of pull-up driver PU_DR2 (0/5V vs. VSS).
18
IN_SSD
Digital Schmidt triggered input control signal of soft-shutdown driver (0/5V vs. VSS).
19
NC
No internal connection.
20
VCC_B
Connect to power VCC plane.
21
NC
No internal connection.
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XTR25010
Pin number
Name
Description
22
NC
No internal connection.
23
IN_PD
Digital Schmidt triggered input control signal of pull-down driver PD_DR (0/5V vs. VSS).
24
NC
No internal connection.
25
VSS
Negative supply voltage of the driver (its value depends on the power transistor to be driven). Connect
to the reference ground plane of the circuit.
26
VDD
5V supply voltage versus VSS, supplying all logic except the output stage of the drivers. Connect to
the VDD supply plane.
27
NC
No internal connection.
28
NC
No internal connection.
29
EN
Digital Schmidt triggered input enable signal for the driver outputs (0/5V vs. VSS).
30
NC
No internal connection.
31
NC
No internal connection.
32
NC
No internal connection.
33
NC
No internal connection.
34
VCC_B
Connect to power VCC plane.
35
NC
No internal connection.
36
PVSS
Power VSS. Connect to VSS through a local plane.
37
PVDD
5V supply voltage versus VSS, supplying the 5V IO cells of the circuit. Connect to the VDD supply
plane through a local plane.
38
BST_DR2_N
Negative terminal of the (100nF) bootstrap capacitor of the PU_DR2 driver.
39
BST_DR2_P
Positive terminal of the (100nF) bootstrap capacitor of the PU_DR2 driver.
40
BST_DR1_N
Negative terminal of the (100nF) bootstrap capacitor of the PU_DR1 driver.
41
BST_DR1_P
Positive terminal of the (100nF) bootstrap capacitor of the PU_DR1 driver.
42
VCC
Positive supply voltage of the driver (its value depends on the power transistor to be driven). Connect
to power VCC plane.
43
VCC_T
Connect to power VCC plane.
44
VCC_IO
Connect to power VCC plane.
45
NC
No internal connection.
46
VCC_B
Connect to power VCC plane.
47
NC
No internal connection.
48
PVCC_DR1_2
Connect to positive supply voltage of PU_DR1 driver (PVCC_DR1).
49
PU_DR1
Output of the pull-up driver with 3A peak drive capability.
50
PVCC_DR1_1
Connect to positive supply voltage of PU_DR1 driver (PVCC_DR1).
51
PVCC_DR2_2
Connect to positive supply voltage of PU_DR2 driver (PVCC_DR2).
52
PU_DR2
Output of the pull-up driver with 3A peak drive capability.
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PRELIMINARY
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XTR25010
RECOMMENDED OPERATING CONDITIONS
BST_DR2_P
BST_DR1_P
BST_DR2_N
CBST2
100nf
BST_DR1_N
CBST1
100nF
VCC
[7V to 40V]
VCC
VCC_B
VCC_T
VCC_IO
Logic input pull_up DR1
[VSS to VDD]
IN_DR1
PVCC_DR2_2
Logic input pull_up DR2
[VSS to VDD]
IN_DR2
PVCC_DR2_1
PVCC_DR2
[7V to VCC]
PVCC_DR1
[7V to VCC]
PVCC_DR1_2
Logic input ENABLE driver
[VSS to VDD]
EN
PVCC_DR1_1
XTR25010
Logic input pull_down MC
[VSS to VDD]
IN_MC
Logic input pull_down PD
[VSS to VDD]
IN_PD
PU_DR1
Output pull-up DR1
PU_DR2
Output pull-up DR2
PD_DR_2
VDD
PD_MC_2
PVSS
VSS
PVDD_MC
PVDD
PVSS_PD_CAP
PD_DR_1
PVDD_PD
VDD
[4.5V to 5.5V]
IN_SSD
PVSS_MC_CAP
Logic input pull_down
SOFT SHUT DOWN
[VSS to VDD]
Output pull-down MC
PD_MC_1
PVSS_PD
PVSS_MC
VSS
VSS
CMC
100nF
CPD
100nF
Parameter
High voltage power supply VCC-VSS (VCC_B, VCC_T and VCC_IO connected to VCC)
High voltage driver power supplies: PVCC_DR1 (PVCC_DR1_1 connect to PVCC_DR1_2)
High voltage driver power supplies: PVCC_DR2 (PVCC_DR2_1 connect to PVCC_DR2_2)
Low voltage power supply VDD-VSS (PVDD, PVDD_PD and PVDD_MC connected to VDD)
Inputs: IN_DR1, IN_DR2, IN_MC, IN_PD, IN_SSD, EN
Junction Temperature1
Tj
1
Output pull-down DR
&
SOFT SHUT DOWN
Min
7
VSS+7
VSS+7
4.5
VSS
-60
Typ
Max
40
VCC
VCC
5.5
VDD
Units
V
V
V
V
230
°C
Operation beyond the specified temperature range is achieved
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XTR25010
ESD CLAMPING SCHEME
Pin Groups
High voltage power supply
High voltage group
Low voltage power supply
Low voltage group
Bootstrap voltages
Ground voltage group
Pins
VCC_IO-PVSS
PVCC_DR2_1, PD_DR_1, PD_DR_2, PU_DR2, PU_DR1, BST_DR1_N, BST_DR2_N, VCC_T,
VCC PD_MC_2, PD_MC_1, PVCC_DR1_2, PVCC_DR1_1, PVCC_DR2_2
PVDD-PVSS
IN_DR1, IN_DR2, IN_MC, IN_PD, IN_SSD, EN, PVDD_PD, PVDD_MC, VDD
BST_DRx_N: BST_DRx_P
VSS, PVSS_PD_CAP, PVSS_MC_CAP, PVSS_MC, PVSS_PD
BST_DRx_P
VCC_IO
HIGH
VOLTAGE
GROUP
BST_DRx_N
PVDD
GROUND
VOLTAGE
GROUP
LOW
VOLTAGE
GROUP
PVSS
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XTR25010
ELECTRICAL SPECIFICATIONS
Unless otherwise stated, specification applies for VCC-VSS=25V (PVCC_DR1 and PVCC_DR2 connected to VCC) and -60°C≤Tj≤230°C.
Parameter
Condition
Min
Typ
Max
Units
Supply voltage
VCC-VSS
7
40
V
VDD-VSS
4.5
5.5
V
IVCC
250
µA
Quiescent current consumption
No PWM modulation
IVDD
1.1
mA
Driver
Propagation delay/channel
from digital inputs to driver outputs
150
ns
Rise time
1nF output capacitor per driver channel
15
ns
Fall time
1nF output capacitor per driver channel
15
ns
Minimum ON time tON_min
1nF output capacitor per driver channel
0.5
µs
Minimum OFF time tOFF_min
1nF output capacitor per driver channel
0.5
µs
Peak output current of PU_DR1 driver
100nF output capacitor
3
A
Peak output current of PU_DR2 driver
100nF output capacitor
3
A
Continuous output current of PU_DR2
VCC-VSS=7V
0.5
A
Peak output current of PD_DR driver
100nF output capacitor
3
A
Peak output current of PD_MC driver
100nF output capacitor
Soft-shutdown transistor RON
Schmidt triggered inputs (IN_DR1, IN_DR2, IN_MC, IN_SSD)
VIH
VIH
VIL
VIL
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3
50
100
A
150
Ω
1
V
V
4
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XTR25010
THEORY OF OPERATION
Introduction
Truth table
XTR25010 is a high-temperature, high reliability power transistor
driver and controller integrated circuit specifically designed to
drive wide bandgap power transistors, such as Silicon Carbide
(SiC) (including normally-On and normally-Off JFETs), Gallium
Nitride (GaN) High Electron Mobility Transistors (HEMT), and
Power MOSFETs and BJTs. For turning on the power transistors, the XTR26010 includes two independent pull-up gate-drivechannels (PU_DR1 and PU_DR2) capable of sourcing 3A each.
For turning off the power transistors, the XTR25010 includes two
pull-down gate-drive-channels capable of sinking 3A peak current each (PD_DR and PD_MC). The PD_DR channel is used
for the effective turn-off, while PD_MC channel is used for Active
Miller Clamping (AMC).
For driving wide bandgap transistors, it is recommended to use
XTR25010 as a power stage extension for the XTR26010, which
generates the needed control signals and additional protection
functions (see XTR26010 for more details).
For DC/DC converters and motor drive, the XTR25010 can be
driven directly with suitable signals from PWM controllers such
as XTR30010.



The EN input is master over all other inputs.
IN_SSD is active low.
The outputs can be set to high impedance with a logic
1 on EN and IN_SSD, and logic 0 on all other inputs.
INPUTS
OUTPUTS
EN
IN_SSD
IN_DR1
IN_DR2
IN_PD
IN_MC
PU_DR1 PU_DR2
PD_DR
PD_MC
0
X
X
X
X
X
Z
Z
VSS
VSS
1
0
X
X
X
X
Z
Z
VSS
(SSD)
Z
1
1
1
0
X
X
PVCC_DR1
Z
Z
Z
1
1
0
1
X
X
Z
PVCC_DR2
Z
Z
1
1
1
1
X
X
PVCC_DR1 PVCC_DR2
Z
Z
1
1
0
0
0
0
Z
Z
Z
Z
1
1
0
0
0
1
Z
Z
Z
VSS
1
1
0
0
1
0
Z
Z
VSS
Z
1
1
0
0
1
1
Z
Z
VSS
VSS
PACKAGE OUTLINES: LJCC52 (J-FORMED LEADED CHIP CARRIER)
J-Formed Leaded Chip Carrier LJCC68
19.05 SQ
[0.750]
46
34
47
20.07 SQ
[0.790]
33
52
1
XTRPPPPP
YYWWANN
7
21
8
0.51 x45°
[0.020]
13.97
[0.550]
20
4x R 0.76 [0.03]
1.02 x45°
[0.040]
1.02 x45°
[0.040]
0.03
[0.001]
1.52
[0.060]
48x 1.27
[0.050]
DS-00395-13 rev1F 2014-04-03
© 2014 X-REL Semiconductor
52x 0.43
[0.017]
18.54±0.51
[0.730±0.020]
0.89
2.87
[0.035] [0.113]
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PRELIMINARY
BASE:
LID:
FINISHING:
AL2O3 90% BLACK
ALLOY 42
60µ" Au
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XTR25010
IMPORTANT NOTICE & DISCLAIMER
Information in this document supersedes and replaces all information previously supplied. Information in this document is provided solely in
connection with X-REL Semiconductor products.
The information contained herein is believed to be reliable. X-REL Semiconductor makes no warranties regarding the information contain
herein. X-REL Semiconductor assumes no responsibility or liability whatsoever for any of the information contained herein. X-REL Semiconductor assumes no responsibility or liability whatsoever for the use of the information contained herein. The information contained herein
is provided “AS IS, WHERE IS” and with all faults, and the entire risk associated with such information is entirely with the user. X-REL Semiconductor reserves the right to make changes, corrections, modifications or improvements, to this document and the information herein
without notice. Customers should obtain and verify the latest relevant information before placing orders for X-REL Semiconductor products.
The information contained herein or any use of such information does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other intellectual property rights, whether with regard to such information itself or anything described by such information.
Unless expressly approved in writing by an authorized representative of X-REL Semiconductor, X-REL Semiconductor products are not
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where failure or malfunction may result in personal injury, death, or property or environmental damage.
General Sales Terms & Conditions apply.
CONTACT US
For more information on X-REL Semiconductor’s products, technical support or ordering:
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