TPS7B4253-Q1 300-mA 40-V Low-Dropout Voltage-Tracking LDO With 4-mV Tracking Tolerance 1 Features

TPS7B4253-Q1 300-mA 40-V Low-Dropout Voltage-Tracking LDO With 4-mV Tracking Tolerance 1 Features
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TPS7B4253-Q1
SLVSCP3B – JANUARY 2015 – REVISED JANUARY 2016
TPS7B4253-Q1 300-mA 40-V Low-Dropout Voltage-Tracking LDO With 4-mV Tracking
Tolerance
1 Features
3 Description
•
•
For automotive off-board sensors and small current
off-board modules, the power supply is through a
long cable from the main board. In such cases,
protection is required in the power devices for the offboard loads to prevent the onboard components from
damage during a short to GND or short to battery
caused by a broken cable. Off-board sensors require
consistent power supply as onboard components to
secure high accuracy of data acquisition.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C6
–40 to 45-V Wide Input-Voltage Range
(Maximum)
Output Voltage Adjusts Down to:
– 1.5 to 40 V (HTSSOP)
– 2 to 40 V (SO PowerPAD™)
300-mA Output Current Capability
Very-Low Output Tracking Tolerance, ±4 mV
320-mV Low Dropout Voltage when IOUT = 200
mA
Separate Pins for Enable and Tracking Inputs
(HTSSOP only)
Low Quiescent Current (IQ):
– < 4 µA when EN = LOW
– 60 µA (Typical) at Light Loads
Extremely Wide ESR Range.
– Stable With 10- to 500-µF Ceramic Output
Capacitor, ESR 1 mΩ to 20 Ω
Reverse Polarity Protection
Current-Limit and Thermal-Shutdown Protection
Output Short-Circuit Proof to Ground and Supply
Inductive Clamp at OUT Pin
Available in the Following Packages:
– 8-Pin SO PowerPAD Package
– 20-Pin HTSSOP Package
The TPS7B4253-Q1 device is designed for
automotive applications with a 45-V load dump. The
device can either be used as one tracking lowdropout (LDO) regulator or voltage tracker to build
one closed power loop for off-board sensors with an
onboard main supply. The output of the device is
accurately regulated by a reference voltage at the
ADJ pin.
To provide an accurate power supply to the off-board
modules, the device offers a 4-mV ultralow tracking
tolerance between the ADJ and FB pins across
temperature. The back-to-back PMOS topology
eliminates the need for an external diode under
reverse polarity condition. The TPS7B4253-Q1
device also includes thermal shutdown, inductive
clamp, overload, and short-to-battery protection to
prevent damage to onboard components during
extreme conditions.
Device Information(1)
PART NUMBER
TPS7B4253-Q1
PACKAGE
4.89 mm × 3.90 mm
HTSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
Automotive
Battery
2 Applications
•
•
•
Off-Board Sensor Supply
High-Precision Voltage Tracking
Power Switch for Off-Board Load
BODY SIZE (NOM)
SO PowerPAD (8)
Main Board
DC-DC or LDO
VOUT
IN
ADJ
TPS7B4253-Q1
Long Cable
OUT
GND
C(OUT)
MCU
Off-Board
Sensor
ADC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7B4253-Q1
SLVSCP3B – JANUARY 2015 – REVISED JANUARY 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
15
8
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application ................................................. 16
9 Power Supply Recommendations...................... 19
10 Layout................................................................... 20
10.1 Layout Guidelines ................................................. 20
10.2 Layout Example .................................................... 20
10.3 Power Dissipation and Thermal Considerations ... 21
11 Device and Documentation Support ................. 22
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
12 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (August 2015) to Revision B
Page
•
Changed the note for the reference voltage minus the input voltage parameter in the Absolute Maximum Ratings
table ....................................................................................................................................................................................... 4
•
Added values for the SO PowerPAD package for the adjust signal valid parameters in the Electrical Characteristics
table ........................................................................................................................................................................................ 5
•
Changed the test condition for the adjust high signal valid parameter in the Electrical Characteristics table ....................... 5
Changes from Original (January 2015) to Revision A
•
2
Page
Changed the device status from Product Preview to Production Data .................................................................................. 1
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SLVSCP3B – JANUARY 2015 – REVISED JANUARY 2016
5 Pin Configuration and Functions
DDA Package
8-Pin SO PowerPAD
Top View
PWP Package
20-Pin HTSSOP With Exposed Thermal Pad
Top View
OUT
1
8
IN
NC
2
7
NC
Thermal
GND
FB
3
6
Pad
4
5
GND
ADJ
NC — No internal connection
OUT
1
20
IN
NC
2
19
EN
NC
3
18
NC
NC
4
17
NC
NC
5
16
NC
15
GND
Thermal
Pad
GND
6
NC
7
14
NC
NC
8
13
NC
NC
9
12
NC
FB
10
11
ADJ
NC — No internal connection
Pin Functions
PIN
NAME
TYPE (1)
DESCRIPTION
11
I
Connect the reference to this pin. A low signal disables the device and a high signal
enables the device. The reference voltage can be connected directly or by a voltage
divider for lower output voltages. To compensate for line influences, connect a
capacitor close to the device pins.
—
19
I
This pin is the enable pin. The device goes to the STANDBY state when the enable
pin goes lower than the threshold value.
4
10
I
This pin is the feedback pin which can connect to the external resistor divider to
select the output voltage.
G
Ground reference
I
This pin is the device supply. To compensate for line influences, connect a
capacitor close to the device pins.
SO PowerPAD
HTSSOP
ADJ
5
EN
FB
GND
IN
3
6
6
15
8
20
2
3
4
2
5
7
8
NC
9
NC
Not connected
12
13
7
14
16
17
18
OUT
1
Exposed thermal pad
(1)
1
O
Block to GND with a capacitor close to the device pins with respect to the
capacitance and ESR requirements listed in the Output Capacitor section.
—
Connect the thermal pad to the GND pin or leave it floating.
I = input, O = output, G = ground, NC = no connect
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
IN (2) (3)
Unregulated input voltage
(2) (3)
MIN
MAX
UNIT
–40
45
V
Enable input voltage
Enable input voltage
–40
45
V
Regulated output voltage
Regulated output voltage (2) (4)
–1
45
V
Voltage difference between the input and
output
IN – OUT
–40
45
V
–0.3
45
V
–1
45
V
18
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–65
150
°C
(2) (3)
Reference voltage
ADJ
Feedback input voltage for the tracker
FB (2) (3)
Reference voltage minus the input voltage
(1)
(2)
(3)
(4)
(5)
ADJ – IN
(5)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to the GND pin.
Absolute maximum voltage.
An internal diode is connected between the OUT and GND pins with 600-mA DC current capability for inductive clamp protection.
When the (ADJ – IN) voltage is higher than 18 V, the (ADJ – OUT) voltage should maintain lower than 18 V, otherwise the device can
be damaged.
6.2 ESD Ratings
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC
Q100-002 (1)
VALUE
UNIT
NC pins
±2000
kV
All pins except for NC
pins
±4000
kV
±1000
kV
Charged device model (CDM), per AEC Q100-011
(1)
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
4
40
UNIT
V
0
40
V
1.5
18
V
18
V
VIN
Unregulated input voltage (2)
VEN
Enable input voltage
VADJ
Adjust and enable input voltage
VFB
Feedback input voltage for the tracker
1.5
VOUT
Output voltage
1.5
40
V
C(OUT)
Output capacitor requirements (3)
10
500
µF
Output ESR requirements (4)
TJ
(1)
(2)
(3)
(4)
4
Operating junction temperature range
0.001
20
Ω
–40
150
°C
Within the functional range the device operates as described in the circuit description. The electrical characteristics are specified within
the conditions given in the related Electrical Characteristics table.
VIN > VADJ + V(DROPOUT)
The minimum output capacitance requirement is applicable for a worst-case capacitance tolerance of 30%, when a resistor divider is
connected between the OUT and FB pins (the output voltage is higher than reference voltage), a 47-nF feedforward capacitor is
required to be connected between the OUT and FB pins for loop stability, and the ESR range of the output capacitor is required to be
from 0.001 to 10 Ω.
Relevant ESR value at f = 10 kHz
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6.4 Thermal Information
TPS7B4253-Q1
THERMAL METRIC (1)
DDA (SO PowerPAD)
PWP (HTSSOP)
8 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
45.4
45.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.1
29.2
°C/W
RθJB
Junction-to-board thermal resistance
27
24.7
°C/W
ψJT
Junction-to-top characterization parameter
8.2
1.3
°C/W
ψJB
Junction-to-board characterization parameter
26.9
24.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.4
3.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
VIN = 13.5 V, VADJ ≥ 1.5 V for HTSSOP, VADJ ≥ 2 V for SO PowerPAD, VEN ≥ 2 V, TJ = –40ºC to 150ºC unless otherwise
stated
PARAMETER
VI(UVLO)
IN undervoltage detection
MAX
UNIT
VIN rising
TEST CONDITIONS
MIN
3.65
V
VIN falling
2.8
V
ΔVO
Output voltage tracking
accuracy (1)
IOUT = 100 µA to 300 mA, VIN = 4 to 40 V
VADJ < VIN – 1 V
1.5 V < VADJ < 18 V for HTSSOP
2 V < VADJ < 18 V for SO PowerPAD
ΔVO(ΔIO)
Load regulation steady-state
ΔVO(ΔVI)
Line regulation steady-state
PSRR
Power supply ripple rejection
ƒrip = 100 Hz, Vrip = 0.5 VPP, C(OUT) = 10 µF, IOUT = 100 mA
V(DROPOUT)
Dropout voltage
(V(DROPOUT) = VIN – VOUT)
IOUT = 200 mA, VIN = VADJ ≥ 4 V
IO(lim)
Output current limitation
VADJ = 5 V, OUT short to GND
IR(IN)
Reverse current at IN
VIN = 0 V, VOUT = 40 V, VADJ = 5 V
–2
IR(–IN)
Reverse current at negative IN
VIN = –40 V, VOUT = 0 V, VADJ = 5 V
–10
TSD
Thermal shutdown temperature TJ increases because of power dissipation generated by the IC
TSD_hys
Thermal shutdown hysteresis
TYP
–4
4
mV
IOUT = 0.1 to 300 mA, VADJ= 5 V
4
mV
IOUT= 10 mA, VIN = 6 to 40 V, VADJ = 5 V
4
mV
70
(2)
301
dB
320
520
mV
450
520
mA
0
µA
0
µA
175
°C
15
4 V ≤ VIN ≤ 40 V, VADJ = 0 V; VEN = 0 V
2
4 V ≤ VIN ≤ 40 V, VEN ≥ 2 V, VADJ < 0.8 V
°C
4
7
18
4 V ≤ VIN ≤ 40 V, IOUT < 100 µA, VADJ = 5 V
60
100
4 V ≤ VIN ≤ 40 V, IOUT < 300 mA, VADJ = 5V
350
400
70
140
IQ
Current consumption
IQ(DROPOUT
)
Current consumption in
dropout region
VIN = VADJ = 5 V, IOUT = 100 µA
II(ADJ)
Adjust input current
VADJ = VFB = 5 V
V(ADJ_LOW)
Adjust low signal valid
VOUT = 0 V
HTSSOP package
0.5
SO PowerPAD package
5.5
HTSSOP package
0
0.8
SO PowerPAD package
0
0.7
1.5
18
2
18
HTSSOP package
µA
µA
µA
V
V(ADJ_HIGH) Adjust high signal valid
|VOUT – VADJ| < 4 mV
V(EN_LOW)
Enable low signal valid
VOUT = 0 V
0
0.7
V(EN_HIGH)
Enable high Signal Valid
OUT settled
2
40
V
IEN
Enable pulldown current
2V < VEN < 40 V
5
µA
IFB
FB bias current
VADJ = VFB = 5 V
0.5
µA
(1)
(2)
SO PowerPAD package
V
V
The tracking accuracy is specified when the FB pin is directly connected to the OUT pin which means VADJ = VOUT, external resistor
divider variance is not included.
Measured when the output voltage, VOUT has dropped 10 mV from the nominal value.
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6.6 Typical Characteristics
VIN = 14 V, VADJ = 5 V, VFB = VOUT, unless otherwise specified
4
4
3
Change in Output Voltage (mV)
IOUT = 70 mA
IOUT = 300 mA
Accuracry (mV)
2
1
0
-1
-2
-3
-4
-40
IOUT = 10 mA
IOUT = 100 mA
3
2
1
0
-1
-2
-3
-4
-25
-10
5
20 35 50 65 80
Ambient Temperature (qC)
95
0
110 125
5
10
Figure 1. Tracking Accuracy vs Ambient Temperature
30
35
40
D005
Figure 2. Line Regulation
800
4
TA = 25qC
TA = 125qC
3
TA = 40qC
TA = 25qC
TA = 125qC
700
2
Dropout Voltage (mV)
Change in Output Voltage (mV)
15
20
25
Input Voltage (V)
D004
1
0
-1
-2
600
500
400
300
200
100
-3
0
-4
0
50
100
150
200
Output Current (mA)
250
0
300
50
100
150
200
Output Current (mA)
D006
250
300
D007
VIN = VADJ = 4 V
Figure 3. Load Regulation
Figure 4. Dropout Voltage vs Output Current
800
500
700
490
Current Limit (mA)
Dropout Voltage (mV)
480
600
500
400
300
470
460
450
440
430
200
420
100
410
0
-40
-25
-10
VIN = VADJ = 4 V
5
20 35 50 65 80
Ambient Temperature (qC)
95
110 125
-25
D008
-10
5
20 35 50 65 80
Ambient Temperature (qC)
95
110 125
D003
IOUT = 200 mA
Figure 5. Dropout Voltage vs Ambient Temperature
6
400
-40
Figure 6. Current Limit (IO(lim)) vs Ambient Temperature
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Typical Characteristics (continued)
VIN = 14 V, VADJ = 5 V, VFB = VOUT, unless otherwise specified
450
20
IQ (VEN = VADJ = 0 V)
IQ (VEN = 5 V, VADJ = 0 V, HTSSOP Only)
18
Quiescent Current (PA)
Shutdown Current (PA)
16
14
12
10
8
6
350
300
250
200
150
4
100
2
50
0
-40
TA = 40qC
TA = 25qC
TA = 125qC
400
0
-25
-10
5
20 35 50 65 80
Ambient Temperature (qC)
95
0
110 125
Figure 7. Shutdown Current vs Ambient Temperature
250
300
D010
500
IOUT = 300 mA
IOUT = 0.1 mA
450
IOUT = 1 mA
IOUT = 10 mA
IOUT = 100 mA
450
400
Quiescent Current (PA)
400
Quiescent Current (PA)
100
150
200
Output Current (mA)
Figure 8. Quiescent Current vs Output Current
500
350
300
250
200
150
350
300
250
200
150
100
100
50
50
0
-40
50
D009
0
-25
-10
5
20 35 50 65 80
Ambient Temperature (qC)
95
0
110 125
5
10
D011
15
20
25
Input Voltage (V)
30
35
40
D012
VADJ = VEN = 5 V
Figure 10. Quiescent Current vs Input Voltage
140
120
120
100
100
PSRR (dB)
PSRR (dB)
Figure 9. Quiescent Current vs Ambient Temperature
140
80
60
80
60
40
40
20
20
0
1E+1
1E+2
C(OUT) = 10 µF
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
IOUT = 1 mA
1E+7
1E+8
0
1E+1
1E+2
D013
TA = 25°C
C(OUT) = 10 µF
Figure 11. PSRR
1E+3
1E+4
1E+5
Frequency (Hz)
1E+6
IOUT = 100 mA
1E+7
1E+8
D014
TA = 25°C
Figure 12. PSRR
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Typical Characteristics (continued)
500
500
400
400
Load Capacitance (µF)
Load Capacitance (µF)
VIN = 14 V, VADJ = 5 V, VFB = VOUT, unless otherwise specified
300
Stable Region
200
100
300
Stable Region
200
100
10
10
0.001
5
10
ESR of C(OUT) (Ω)
15
20
0.001
2.5
D002
VFB = VOUT
5
ESR of C(OUT) (Ω)
7.5
10
D002
VFB < VOUT
Figure 13. ESR Stability vs Load Capacitance
Figure 14. ESR Stability vs Load Capacitance
500
Load Capacitance (µF)
400
300
10 V/div
Stable Region
VIN
200
100 mV/div
V(OUT_AC)
100
100 mA/div
IOUT
10
0.001
0.75
1.5
ESR of C(OUT) (Ω)
2.25
3
VIN = 6 to 40 V
VADJ = 5 V
IOUT = 100 mA, 20 µs/div
D015
Figure 15. ESR Stability vs Load Capacitance (Multiple
Output Capacitors)
C(OUT) = 10 µF
Figure 16. 6- to 40-V Line Transient
10 V/div
10 V/div
VIN
VIN
100 mV/div
V(OUT_AC)
100 mV/div
V(OUT_AC)
100 mA/div
100 mA/div
IOUT
IOUT
VIN = 40 to 6 V
VADJ = 5 V
IOUT = 100 mA, 20 µs/div
C(OUT) = 10 µF
VIN = 6 to 40 V
VADJ = 5 V
IOUT = 10 mA, 20 µs/div
Figure 17. 40- to 6-V Line Transient
8
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C(OUT) = 10 µF
Figure 18. 6- to 40-V Line Transient
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Typical Characteristics (continued)
VIN = 14 V, VADJ = 5 V, VFB = VOUT, unless otherwise specified
10 V/div
5 V/div
100 mV/div
V(OUT_AC)
VIN
100 mV/div
V(OUT_AC)
VIN
100 mA/div
IOUT
IOUT
50 mA/div
VIN = 40 to 6 V
VADJ = 5 V
IOUT = 10 mA, 20 µs/div
C(OUT) = 10 µF
Figure 19. 40- to 6-V Line Transient
VIN = 14 V
VADJ = 5 V
IOUT = 10 to 100 mA, 40 µs/div
C(OUT) = 10 µF
Figure 20. 10- to 100-mA Load Transient
5 V/div
100 mV/div
V(OUT_AC)
VIN
50 mA/div
IOUT
VIN = 14 V
VADJ = 5 V
IOUT = 100 to 10 mA, 40 µs/div
C(OUT) = 10 µF
Figure 21. 100- to 10-mA Load Transient
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7 Detailed Description
7.1 Overview
The TPS7B4253-Q1 device is a monolithic integrated low-dropout voltage tracker with an ultralow tracking
tolerance. Key protection circuits are integrated in the device, including output current limitation, reverse polarity
protection, inductive load clamp, output short-to-battery protection, and thermal shutdown in case of an
overtemperature event.
7.2 Functional Block Diagram
IN
OUT
Load
V(BAT)
Reverse
Current
Protection
Internal
Supply
Current
Limit
UVLO
Logic
Control
Thermal
Shutdown
±
+
EN
FB
ADJ
Vref
GND
7.3 Feature Description
7.3.1 Short Circuit and Overcurrent Protection
The TPS7B4253-Q1 device features integrated fault protection which makes the device ideal for automotive
applications. To keep the device in a safe area of operation during certain fault conditions, internal current-limit
protection is used to limit the maximum output current. This protection protects the device from excessive power
dissipation. For example, during a short-circuit condition on the output, the current through the pass element is
limited to IO(lim) to protect the device from excessive power dissipation.
7.3.2 Integrated Inductive Clamp Protection
During output turnoff, the cable inductance continues to source the current from the output of the device. The
device integrates an inductive clamp at the OUT pin to help to dissipate the inductive energy stored in the cable.
An internal diode is connected between the OUT and GND pins with a DC-current capability of 600 mA for
inductive clamp protection.
10
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Feature Description (continued)
7.3.3 OUT Short to Battery and Reverse Polarity Protection
The TPS7B4253-Q1 device can withstand a short to battery when the output is shorted to the battery, as shown
in Figure 22. Therefore, no damage to the device occurs.
Short to Battery
IN
Automotive
Battery
14 V (Typical)
TPS7B4253-Q1
OUT
Load
1 µF
10 µF
EN
ADJ
FB
GND
5V
100 nF
Figure 22. OUT Short to Battery, VIN = V(BAT)
A short to the battery can also occur when the device is powered by an isolated supply at lower voltage, as
shown in Figure 23. In this case, the TPS7B4253-Q1 supply-input voltage is set to 7 V when a short to battery
(14 V typical) occurs on the OUT pin which operates at 5 V. The internal back-to-back PMOS remains on for 1
ms during which the input voltage of the TPS7B4253-Q1 device charges up to the battery voltage. A diode
connected between the output of the DC-DC converter and the input of the TPS7B4253-Q1 device is required in
case the other loads connected behind the DC-DC converter cannot withstand the voltage of an automotive
battery. To achieve a lower dropout voltage, TI recommends using a Schottky diode. This diode can be
eliminated if the output of the DC-DC converter and the loads connect behind it withstand automotive battery
voltage.
The internal back-to-back PMOS is switched to OFF when reverse polarity or short to battery occur for 1 ms.
After that, the reverse current flows out through the IN pin with less than 10 µA. In the meanwhile, a special ESD
structure implemented at the input ensures the device can withstand –40 V.
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Feature Description (continued)
Short to Battery
Automotive
Battery
14 V (Typical)
IN
7V
TPS7B4253-Q1
OUT
DC-DC
Load
1 µF
EN
10 µF
FB
Other Loads
ADJ
GND
5V
100 nF
Figure 23. OUT Short to Battery, VIN < V(BAT)
In most cases, the output of the TPS7B4253-Q1 device is shorted to the battery through an automotive cable.
The parasitic inductance on the cable results in LC oscillation at the output of the TPS7B4253-Q1 device when
the short to battery occurs. Ideally, the peak voltage at the output of the TPS7B4253-Q1 device should be lower
than the absolute-maximum voltage rating (45 V) during LC oscillation.
7.3.4 Undervoltage Shutdown
The device has an internally fixed undervoltage-shutdown threshold. Undervoltage shutdown activates when the
input voltage on IN drops below UVLO. This activation ensures the regulator is not latched into an unknown state
during a low input-supply voltage. If the input voltage has a negative transient that drops below the UVLO
threshold and then recovers, the regulator shuts down and then powers up with a standard power-up sequence
when the input voltage is above the required levels.
7.3.5 Thermal Protection
The device incorporates a thermal shutdown (TSD) circuit as a protection from overheating. During continuous
normal operation, the junction temperature should not exceed the TSD trip point. If the junction temperature
exceeds the TSD trip point, the output turns off. When the junction temperature decreases to 15°C (typical) lower
than the TSD trip point, the output turns on.
NOTE
The purpose of the design of the internal protection circuitry of the TPS7B4253-Q1 device
is to protect against overload conditions and is not intended as a replacement for proper
heat-sinking. Continuously running the device into thermal shutdown degrades device
reliability.
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Feature Description (continued)
7.3.6 Regulated Output (OUT)
The OUT pin is the regulated output based on the required voltage. The output has current limitation. During
initial power up, the regulator has an incorporated soft-start feature to control the initial current through the pass
element.
7.3.7 Enable (EN)
The EN pin is a high-voltage-tolerant pin. A high input on the EN pin acitvates the device and turns on the
regulator. The device consumes a maximum of shutdown current 4 µA when the EN pin is low. The EN pin has a
maximum internal pulldown of 5 µA.
7.3.8 Adjustable Output Voltage (FB and ADJ)
7.3.8.1 OUT Voltage Equal to the Reference Voltage
With the reference voltage applied directly at the ADJ pin and the FB pin connected to the OUT pin, the voltage
at the OUT pin equals to the reference voltage at the ADJ pin, as shown in Figure 24.
VOUT = VADJ
(1)
IN
TPS7B4253-Q1
OUT
V(BAT)
Load
22 µF
10 µF
FB
EN
ADJ
GND
Vref
Figure 24. OUT Voltage Equal to the Reference Voltage
7.3.8.2 OUT Voltage Higher Than Reference Voltage
By using an external resistor divider connected between the OUT and FB pins, an output voltage higher than
reference voltage can be generated as shown in Figure 25. Use Equation 2 to calculate the value of the output
voltage. The recommended range for R1 and R2 is from 10 kΩ to 100 kΩ.
´ (R1 + R2)
V
VOUT = ADJ
(2)
R2
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Feature Description (continued)
TPS7B4253-Q1
IN
OUT
V(BAT)
Load
1 µF
10 µF
R1
47 nF
FB
EN
R2
ADJ
GND
Vref
Figure 25. OUT Voltage Higher Than the Reference Voltage
7.3.8.3 Output Voltage Lower Than Reference Voltage
By using an external resistor divider connected at the ADJ pin, an output voltage lower than reference voltage
can be generated as shown in Figure 26. Use Equation 3 to calculate the output voltage. The recommended
value for both R1 and R2 is less than 100 kΩ.
V ´ R2
VOUT = ref
(3)
R1 + R2
IN
TPS7B4253-Q1
OUT
V(BAT)
Load
1 µF
10 µF
EN
FB
Vref
R1
ADJ
GND
R2
Figure 26. OUT Voltage Lower Than the Reference Voltage
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7.4 Device Functional Modes
7.4.1 Operation With VIN < 4 V
The maximum UVLO voltage is 3.65 V, and the device generally operates at an input voltage above 4 V. The
device can also operate at a lower input voltage; no minimum UVLO voltage is specified. At an input voltage
below the actual UVLO voltage, the device does not operate.
7.4.2 Operation With EN Control
The enable rising edge threshold is 2 V (maximum). With the EN pin held above that voltage and the input
voltage above 4 V, the device becomes active. The falling edge of the EN pin is 0.7 V (minimum). Holding the
EN pin below that voltage disables the device, thus reducing the quiescent current of the device.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS7B4253-Q1 device is a 300-mA low-dropout tracking regulator with ultralow tracking tolerance. The
PSpice transient model is available for download on the product folder and can be used to evaluate the basic
function of the device.
8.2 Typical Application
8.2.1 Application With Output Voltage Equal to the Reference Voltage
Figure 27 shows the typical application circuit for the TPS7B4253-Q1 device. Different values of external
components can be used depending on the end application. An application may require a larger output capacitor
during fast load steps to prevent a large drop on the output voltage. TI recommends using a low-ESR ceramic
capacitor with a dielectric of type X5R or X7R.
IN
OUT
Load
(sensor)
Battery
1 µF
Reverse
Current
Protection
10 µF
Internal
Supply
Current
Limit
UVLO
MCU I/O
Logic
Control
Thermal
Shutdown
Vref
(5 V)
±
+
EN
FB
ADJ
100 nF
GND
Figure 27. Output Voltage Equals the Reference Voltage
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Typical Application (continued)
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the design parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
4 to 40 V
Output voltage
1.5 to 40 V
Enable voltage
2 to 40 V
ADJ voltage
1.5 to 18 V
Output capacitor
10 to 500 µF
Output capacitor ESR range
0.001 to 20 Ω
8.2.1.2 Detailed Design Procedure
To
•
•
•
•
•
begin the design process, determine the following:
Input voltage range
Output voltage
Reference voltage
Output current
Current limit
8.2.1.2.1 Input Capacitor
The device requires an input decoupling capacitor, the value of which depends on the application. The typical
recommended value for the decoupling capacitor is 2.2 µF. The voltage rating must be greater than the
maximum input voltage.
8.2.1.2.2 Output Capacitor
To ensure the stability of the TPS7B4253-Q1 device, the device requires an output capacitor with a value in the
range from 10 µF to 500 µF and with an ESR range from 0.001 Ω to 20 Ω when the FB pin is directly connected
to the OUT pin. TI recommends selecting a ceramic capacitor with low ESR to improve the load transient
response.
To achieve an output voltage higher than the reference voltage, a resistor divider is connected between the OUT
pin and the FB pin. In this case, a 47-nF feed forward capacitor must be connected between the OUT and FB
pins for loop stability. The ESR of the output capacitor must be from 0.001 Ω to 10 Ω.
When multiple capacitors (two or more) are connected in parallel at the OUT pin, the ESR range of each output
capacitor must be from 0.001 Ω to 3 Ω for loop stability.
In case the FB pin is shorted to ground, the TPS7B4253-Q1 device functions as a power switch with no need for
the output capacitor.
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8.2.1.3 Application Curve
10 V/div
VIN
100 mV/div
V(OUT_AC)
100 mA/div
IOUT
VIN = 6 to 40 V
VADJ = 5 V
C(OUT) = 10 µF
IOUT = 100 mA, 20 µs/div
Figure 28. 6- to 40-V Line Transient
8.2.2 High-Side Switch Configuration
As shown in Figure 29, by connecting the FB pin to the GND pin, the TPS7B4253-Q1 device can be used as a
high-side switch with current-limit, thermal shutdown, output short-to-battery, and reverse polarity protection. The
switching on and off of the device is then controlled through the EN and ADJ pins.
IN
TPS7B4253-Q1
OUT
V(BAT)
Load
1 µF
10 µF
EN
ADJ
FB
GND
MCU I/O
Figure 29. High-Side Switch Application
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8.2.3 High Accuracy LDO
With an accurate voltage rail, the TPS7B4253-Q1 device can be used as an LDO with ultrahigh-accuracy output
voltage by configuring the device as shown in Figure 30.
IN
TPS7B4253-Q1
OUT
V(BAT)
Load
1 µF
10 µF
EN
Accurate reference rail
For example: TLV431
ADJ
FB
GND
Vref
Figure 30. High-Accuracy LDO Application
For example, assume the reference voltage is a 5-V rail with 0.5% accuracy. Because the tracking accuracy
between the ADJ and OUT pins is specified below 4 mV across temperature, the output accuracy of the
TPS7B4253-Q1 device can be calculated with Equation 4.
V
´ 0.5% + 4 mV
5 ´ 0.5% + 0.004
Accuracy of VOUT = ADJ
´ 100% =
´ 100% = 0.58%
VADJ
5
(4)
9 Power Supply Recommendations
The device is designed to operate with an input voltage supply from 4 V to 40 V. This input supply must be well
regulated. If the input supply is more than a few inches away from the TPS7B4253-Q1 device, TI recommends
adding an electrolytic capacitor with a value of 2.2 µF and a ceramic bypass capacitor at the input.
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10 Layout
10.1 Layout Guidelines
For the layout of the TPS7B4253-Q1 device, place the input and output capacitors close to the devices as shown
in the Functional Block Diagram. To enhance the thermal performance, TI recommends surrounding the device
with some vias.
Minimize equivalent series inductance (ESL) and ESR to maximize performance and ensure stability. Place
every capacitor as close as possible to the device and on the same side of the PCB as the regulator.
Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. TI
strongly discourages the use of vias and long traces for the path between the output capacitor and the OUT pins
because vias can negatively impact system performance and even cause instability.
If possible, and to ensure the maximum performance specified in this data sheet, use the same layout pattern
used for the TPS7B4253-Q1 evaluation board, TPS7B4253EVM, which is available at
www.ti.com/tool/TPS7B4253EVM.
10.2 Layout Example
HTSSOP 20
62 3RZHU3$'Œ-8
OUT
OUT
IN
2
3
Thermal
Pad
7
GND
6
FB
ADJ/EN
4
GND
5
FB
Figure 31. SO PowerPAD Package TPS7B4253-Q1
Layout Example
20
20
2
19
3
18
4
17
8
1
GND
IN
1
5
Thermal Pad
16
GND
6
15
7
14
8
13
9
12
10
11
ADJ
Figure 32. HTSSOP Package TPS7B4253-Q1
Layout Example
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10.3 Power Dissipation and Thermal Considerations
Use Equation 5 to calculate the device power dissipation.
PD = IO ´ (VI - VO ) + IQ ´ VI
where
•
•
•
•
•
PD = continuous power dissipation
IO = output current
VI = input voltage
VO = output voltage
IQ = quiescent current
(5)
As IQ « IO, the term IQ × VI in Equation 5 can be ignored.
For a device under operation at a given ambient air temperature (TA), calculate the junction temperature (TJ) with
Equation 6.
TJ = TA + (qJA ´ PD )
where
•
θJA = junction-to-junction-ambient air thermal impedance
(6)
A rise in junction temperature because of power dissipation can be calculated with Equation 7.
DT = TJ - TA = (qJA ´ PD )
(7)
For a given maximum junction temperature (TJmax), the maximum ambient air temperature (TAmax) at which the
device can operate can be calculated with Equation 8.
TA max = TJ max - (qJA ´ PD )
(8)
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
For the TPS7B4253 PSpice Transient Model, go to www.ti.com/product/TPS7B4253-Q1/toolssoftware.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• TPS7B4253-Q1 Evaluation Module, SLVUAE3
• TPS7B4253-Q1 Pin FMEA, SLVA745
11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
2-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS7B4253QDDARQ1
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
4253
TPS7B4253QPWPRQ1
ACTIVE
PWP
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
7B4253Q
HTSSOP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Feb-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS7B4253QDDARQ1
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
TPS7B4253QPWPRQ1
HTSSOP
PWP
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Feb-2016
*All dimensions are nominal
Device
Package Type
TPS7B4253QDDARQ1
SO PowerPAD
TPS7B4253QPWPRQ1
HTSSOP
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DDA
8
2500
366.0
364.0
50.0
PWP
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
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Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
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