TTI47541505
TMDS461
www.ti.com ............................................................................................................................................................................................... SLLS915 – JANUARY 2009
1080p – Deep Color 4-to-1 HDMI/DVI Switch with Adaptive Equalization
FEATURES
1
• 4:1 Switch Supporting DVI Above 1920 × 1200
and HDMI HDTV Resolutions up to 1080p With
16-bit Color Depth
• Designed for Signaling Rates up to 3 Gbps
• HDMI1.3a Spec Compliant
• Adaptive Equalization to Support up to 20-m
HDMI Cable
• TMDS Input Clock-Detect Circuit
• DDC Repeater Function
• <2 mW Low-Power Mode
• Local I2C or GPIO Configurable
• Enhanced ESD. HBM: 10 kV on All Input
TMDS, DDC I2C pins
• 3.3-Volt Power Supply
2
•
•
•
Temperature Range: 0°C to 70°C
Automatic Port Select Feature
Robust TMDS Receive Stage That Can Work
With Non-Compliant Input Common-Mode
HDMI Signals
APPLICATIONS
•
High-Definition Digital TV
– LCD
– Plasma
– DLP®
DESCRIPTION
The TMDS461 is a 4-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that
allows up to four DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one
hot-plug detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel
supports signaling rates up to 3 Gbps to allow 1080p resolution in 16-bit color depth.
The TMDS461 provides an analog adaptive equalizer for different ranges of cable lengths. The equalizer
automatically compensates for intersymbol interference [ISI] loss of an HDMI/DVI cable for up to 20 dB at 3 Gbps
(see Figure 19 ).
TYPICAL APPLICATION
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DLP is a registered trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TMDS461
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DESCRIPTION (CONTINUED)
When any input port is selected, the integrated terminations (50-Ω termination resistors pulled up to VCC) are
switched on for the TMDS clock channel, the TMDS clock-detection circuit is enabled, and the DDC repeater is
enabled. After a valid TMDS clock is detected, the integrated termination resistors for the data lines are enabled,
and the output TMDS lines are enabled. When an input port is not selected, the integrated terminations are
switched off, the TMDS receivers are disabled, and the DDC repeater is disabled. Clock-detection circuitry
provides an automatic power-management feature, because if no valid TMDS clock is detected, the terminations
on the input TMDS data lines are disconnected and the TMDS outputs are placed in a high-impedance state.
The TMDS461 is designed to be controlled via a local I2C interface or GPIO interface based on the status of the
I2C_SEL pin. The local I2C interface in TMDS461 is a slave-only I2C interface. (See the I2C INTERFACE
NOTES section.)
I2C Mode: When the I2C_SEL pin is set high, the device is in I2C mode. Refer to Table 7 to Table 13 for I2C
register description. With local I2C, the interface port status can be read and the advanced configurations of the
device such as TMDS output edge rate control, DDC I2C buffer output-voltage-select (OVS) settings (See the
DDC I2C Function Description for detailed description on DDC I2C buffer description and OVS description),
device power management, TMDS clock-detect feature, Automatic Port Selection and TMDS input-port
selection can be set. In I2C mode when any system level change such as change in 5V_PWR on the source
side, a change in the selected port, or a change in the selected port's valid clock detect is detected, TMDS461
can issue an Interrupt Request via IRQ pin (refer IRQ Section ). A micro-controller connected to TMDS461 can
read I2C register address 0X01, (See Table 7) to obtain the current status of 5V_PWR, the selected port, and
clock-detect status. Once the micro-controller has read I2C register 0x01, the IRQ pin returns to low.
GPIO mode: When the I2C_SEL pin is set low, the device is in GPIO control mode. The port selection is
controlled with source selectors, S1 and S2. The power-saving mode is controlled through the LP pin. In GPIO
mode, the default TMDS output edge rate that is the fastest setting of rise and fall time is set. The DDC I2C
buffer OVS setting can be changed through OVS GPIO pin, see Table 2. In GPIO mode, IRQ pin reflects the
status of the selected port's clock detect. If a valid clock is detected by the clock detect circuit, IRQ goes high. If
no valid clock is detected, IRQ is driven low.
Following are some of the key features (advantages) that TMDS461 provides to the overall sink-side system
(HDTV).
•
•
•
•
•
•
•
•
2
4:1 switch that supports TMDS data rates up to 3 Gbps on all four input ports.
ESD: Built-in support for high ESD protection (up to 10 kV on the TMDS and DDC I2C pins ). The HDMI
source-side pins on the TMDS461 are connected via the HDMI/DVI exterior connectors and cable to the
HDMI/DVI sources (e.g., DVD player). In TV applications, it can be expected that the source side may be
subjected to higher ESD stresses compared to the sink side that is connected internally to the HDMI receiver.
Adaptive equalization: The built-in analog adaptive equalization support compensates for intersymbol
interference [ISI] loss of up to 20 dB, which represents a typical 20-m HDMI/DVI cable at 3 Gbps. Analog
Adaptive equalization adjusts the equalization gain automatically, based on the cable length and the
incoming TMDS data rate.
TMDS clock-detect circuitry: This feature provides an automatic power-management feature and also ensures
that the TMDS output port is turned on only if there is a valid TMDS input signal. TMDS clock-detect feature
can be by-passed in I2C Mode, (See Table 9 ). It is recommended to enable TMDS clock-detect circuitry
during normal operation. However, for HDMI compliance testing (TMDS Termination Voltage Test), the clock
detect feature should be disabled by using the I2C mode control. To comply with the TMDS Termination
Voltage Test in the GPIO mode (default TMDS clock-detect circuitry enabled), a valid TMDS clock will need to
be provided. With the clock present, the internal terminations are present providing the correct termination
voltage.
DDC I2C buffer: This feature provides isolation on the source side and sink side DDC I2C capacitance, thus
helping the sink system to pass system-level compliance.
Robust TMDS receive stage: This feature ensures that the TMDS461 can work with TMDS input signals
which have common-mode voltage levels that can be either compliant or non-compliant with HDMI/DVI
specifications
VSadj: This feature adjusts the TMDS output swing and can help the sink system to tune the output TMDS
swing of the TMDS461 (if needed) based on the system requirements.
GPIO or local I2C interface to control the device features
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•
•
•
TMDS output edge-rate control: This feature adjusts the TMDS461 TMDS output rise and fall times. There
are four settings that can be chosen. The default setting is the fastest rise and fall time; the other three
settings are slower. Slower edge transitions can potentially help the sink system (HDTV) in passing regulatory
EMI compliance.
Automatic Port Select Feature available in I2C mode
5V_PWR detect for each port connected, Hot Plug Detect (HPD) of non selected port follows 5V_PWR,
whereas HPD of selected port follows HPD_SINK.
FUNCTIONAL BLOCK DIAGRAM
Vcc
RINT
RINT
Dx+_1
Dx-_1
TMDS Rx
w/ AEQ
Vcc
RINT
RINT
CLK+_1
TMDS Rx
CLK-_1
Clock Detect
VSadj
Tx
SCL1
Rx
Dx+_SINK
TMDS Tx
Tx
Dx-_SINK
SDA1
Rx
CLK+_SINK
xx2
4-to-1
MUX
xx3
TMDS Tx
CLK-_SINK
Vcc
Rx
SCL_SINK
RINT
RINT
Tx
Dx+_4
Dx-_4
TMDS Rx
w/ AEQ
Rx
SDA_SINK
Vcc
RINT
Tx
RINT
CLK+_4
Clock Detect
TMDS Rx
CLK-_4
Clock Detect
Tx
SCL4
Rx
Tx
SDA4
Rx
5V_Ind
5V_PWR1
HPD1
HPD_SINK
1kΩ
IRQ
5V_PWR2
HPD2
5V_PWR3
HPD3
1kΩ
Local I2C
&
Control Logic
1kΩ
5V_PWR4
HPD4
1kΩ
LP
S1
S2
OVS
I2C_SEL
Local_SCL
Local_SDA
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Local_SCL
Local_SDA
Local_Addr
OVS
79
78
77
76
I2C_SEL
VCC
81
80
S1
S2
83
82
LP
GND
84
IRQ
86
85
VCC
VSadj
87
D2+_SINK
89
88
GND
D2-_SINK
90
D1+_SINK
92
91
VCC
D1-_SINK
93
D0+_SINK
95
94
GND
D0-_SINK
97
96
CLK-_SINK
CLK+_SINK
98
VCC
99
100
PZT PACKAGE
GND
1
75
SCL_SINK
CLK-_1
2
74
SDA_SINK
CLK+_1
3
73
5V_Ind
VCC
4
72
HPD_SINK
D0-_1
5
71
GND
D0+_1
6
70
HPD1
GND
7
69
5V_PWR1
D1-_1
8
68
SDA1
D1+_1
9
67
SCL1
VCC
10
66
NC
D2-_1
11
65
HPD2
D2+_1
12
64
5V_PWR2
GND
13
63
SDA2
CLK-_2
14
62
SCL2
CLK+_2
15
61
GND
VCC
16
60
HPD3
D0-_2
17
59
5V_PWR3
D0+_2
18
58
SDA3
GND
19
57
SCL3
D1-_2
20
56
VCC
D1+_2
21
55
HPD4
VCC
22
54
5V_PWR4
D2-_2
23
53
SDA4
D2+_2
24
52
SCL4
GND
25
51
GND
49
50
D2+_4
VCC
47
48
GND
D2-_4
45
46
D1-_4
D1+_4
43
44
VCC
42
D0-_4
D0+_4
40
41
GND
39
CLK-_4
CLK+_4
37
38
D2-_3
VCC
36
GND
D2+_3
34
35
D1+_3
VCC
33
31
32
D0+_3
D1-_3
29
30
GND
28
CLK+_3
D0-_3
26
27
VCC
CLK-_3
TMDS461
100-PIN TQFP
TERMINAL FUNCTIONS
TERMINAL
SIGNAL
NO.
I/O
DESCRIPTION
TMDS INPUT PINS
CLK+_1
CLK-_1
D[0:2]+_1
D[0:2]-_1
CLK+_2
CLK-_2
D[0:2]+_2
D[0:2]-_2
CLK+_3
CLK-_3
D[0:2]+_3
D[0:2]-_3
CLK+_4
CLK-_4
4
3
2
I
Port-1 TMDS differential clock
6, 9, 12
5, 8, 11
I
Port-1 TMDS differential data inputs
15
14
I
Port-2 TMDS differential clock
18, 21, 24,
17, 20, 23
I
Port-2 TMDS differential data inputs
28
27
I
Port-3 TMDS differential clock
31, 34, 37
30, 33, 36
I
Port-3 TMDS differential data inputs
40
39
I
Port-4 TMDS differential clock
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TERMINAL FUNCTIONS (continued)
TERMINAL
SIGNAL
D[0:2]+_4
D[0:2]-_4
NO.
I/O
DESCRIPTION
43, 46, 49
42, 45, 48
I
Port-4 TMDS differential data inputs
98
99
O
TMDS sink differential clock
95, 92, 89
96, 93, 90
O
TMDS sink differential data outputs
70, 65, 60, 55
O
Source port hot-plug-detect output
72
I
Sink hot plug detect input
SCL[1:4]
67, 62, 57, 52
I/O
TMDS port bidirectional DDC clock
SDA[1:4]
68, 63, 58, 53
I/O
TMDS port bidirectional DDC data
SCL_SINK
75
I/O
TMDS sink side bidirectional DDC clock
SDA_SINK
74
I/O
TMDS sink side bidirectional DDC data
TMDS OUTPUT PINS
CLK+_SINK
CLK-_SINK
D[0:2]+_SINK
D[0:2]-_SINK
HOT-PLUG-DETECT STATUS PINS
HPD[1:4]
HPD_SINK
DDC PINS
STATUS PINS
IRQ
86
O
Interrupt Request
69, 64, 59, 54
I
Source Port 5V Signal Input
5V_Ind
73
O
Selected Port 5V Power Indicator
LP
85
I
Low-power select bar
5V_PWR[1:4]
CONTROL PINS
S[1:2]
83,82
I
Source Selection GPIO
I2C_SEL
81
I
Local I2C control select
Local_SCL
79
I
Local I2C clock
Local_SDA
78
I/O
Local I2C data
Local_Addr
77
I
Local I2C address
VSadj
87
I
TMDS compliant voltage swing control
OVS
76
I
DDC offset selector
NC
66
No Connect
VCC
4, 10, 16, 22, 26, 32,
38, 44,
50, 56, 80, 88, 94,
100
3.3 V supply
GND
1, 7, 13, 19, 25, 29,
35, 41, 47,
51, 61, 71, 84, 91, 97
Ground
SUPPLY AND GROUND PINS
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Table 1. Source Selection Lookup (1)
CONTROL
PINS
HOT-PLUG DETECT STATUS
Power Mode
S2
S1
Port Selected
SCL_SINK
SDA_SINK
HPD1
HPD2
HPD3
HPD4
L
L
Port 1
Terminations of port 2, 3
and 4 are disconnected.
SCL1
SDA1
HPD_SINK
5V_PWR2
5V_PWR3
5V_PWR4
Normal mode
L
H
Port 2
Terminations of port 1, 3
and 4 are disconnected.
SCL2
SDA2
5V_PWR1
HPD_SINK
5V_PWR3
5V_PWR4
Normal mode
H
L
Port 3
Terminations of port 1, 2
and 4 are disconnected.
SCL3
SDA3
5V_PWR1
5V_PWR2
HPD_SINK
5V_PWR4
Normal mode
H
H
Port 4
Terminations of port 1, 2
and 3 are disconnected.
5V_PWR1
5V_PWR2
5V_PWR3
HPD_SINK
Normal mode
(1)
6
I/O SELECTED
SCL4
SDA4
H: Logic high; L: Logic low
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EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
TMDS Input Stage
TMDS Output Stage
VCC
VCC
50 W
50 W
Y
B
A
Z
10 mA
Status and Source Selector
Output Stage
VCC
VCC
5 V_PWR [x]
HPD_SINK
S1
S2
1kΩ
IRQ, 5V_Ind
DDC Buffer
HPD Output Stage
VCC
Buffer
5 V_PWR [x]
HPD [x]
HPD_SINK
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Table 2. Control Pin Lookup Table (1)
SIGNAL
LEVEL
STATE
H
Normal Mode
L
Low-power
mode
LP
S2
S[2:1]
GPIO Mode
Local_Addr
OVS
VSadj
(1)
Normal operational mode for device.
Device is forced into a low power state, causing the inputs and outputs to go to a
high-impedance state. All other inputs are ignored.
S1
L
L
Port 1
Port 1 is selected as the active port; all other ports are disabled.
L
H
Port 2
Port 2 is selected as the active port; all other ports are disabled.
H
L
Port 3
Port 3 is selected as the active port; all other ports are disabled.
H
Port 4
Port 4 is selected as the active port; all other ports are disabled.
H
I2C_SEL
DESCRIPTION
I2C
H
Device is configured by I2C logic.
L
GPIO
H
0101101
Device is configured by GPIO.
The 7-bit address for the local I2C logic is 0101101
L
0101100
The 7-bit address for the local I2C logic is 0101100
H
Offset 1
DDC sink side VOL and VIL offset range 1, VIL1 (max) : 0.4V, VOL1
L
Offset 2
DDC sink side VOL and VIL offset range 2, VIL2 (max) : 0.4V, VOL2 (max) : 0.6V
Hi-Z
Offset 3
DDC sink side VOL and VIL offset range 3, VIL3 (max) : 0.3V, VOL3 (max) : 0.5V
4.02 kΩ
Compliant
Voltage Swing
(max)
: 0.7V
Driver output voltage swing precision control to aid with system compliance. VSadj resistor
value could be selected to be
4.02 kΩ ±10% based on the system requirement to pass HDMI compliance.
(H) Logic high; (L) Logic low
ORDERING INFORMATION (1)
(1)
PART NUMBER
PART MARKING
PACKAGE
TMDS461PZTR
TMDS461
100-pin TQFP reel
TMDS461PZT
TMDS461
100-pin TQFP tray
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage range (2)
VCC
Voltage range
TMDS I/O
Electrostatic discharge
8
V
–0.3 to 4
–0.3 to 5.5
Control and status I/O
–0.3 to 5.5
Human body model (3) on SCL[1:4], SDA[1:4], D[0:2]+_[1:4], D[0:2]–_[1:4],
CLK+_[1:4], CLK–_[1:4] pins
±10,000
Human body model (3) on all other pins
±6,000
Charged-device model (4)
±1500
V
V
±200
Continuous power dissipation
(2)
(3)
(4)
(5)
UNIT
HPD and DDC I/O
Machine model (5)
(1)
VALUE
–0.3 to 3.6
See Dissipation Ratings
table
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-B
Tested in accordance with JEDEC Standard 22, Test Method C101-A
Tested in accordance with JEDEC Standard 22, Test Method A115-A
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DISSIPATION RATINGS
PACKAGE
PCB JEDEC STANDARD
TA ≤ 25°C
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
Low-K
1329 mW
13.2 mW/°C
731 mW
High-K
1631 mW
16.3 mW/°C
897 mW
100-pin TQFP (PZT)
(1)
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX (1)
UNIT
RθJB
Junction-to-board thermal resistance
37.13
°C/W
RθJC
Junction-to-case thermal resistance
15.3
°C/W
666
PD(1)
Device power dissipation in normal mode LP = HIGH TMDS: VID(pp) = 1200 mV, 3 Gbps
TMDS data pattern; HPD_SINK = HIGH, S1/S2 =
LOW/LOW, LOW/HIGH, HIGH/HIGH, HIGH/LOW.
Device power dissipation in standby
mode
PD(2)
LP = HIGH, TMDS: VID(pp) = 1200 mV, 3 Gbps
TMDS data pattern; HPD_SINK = HIGH, (See
Table 8, Register 0x02[7:6] =[0:1]. Note that
standby power mode is only available when
TMDS461 is configured in I2C mode.
PSD
Device power dissipation in low-power
mode
PNCLK
Device power dissipation in normal mode LP = HIGH, No TMDS input clock, HPD_SINK
with no active TMDS input clock
=HIGH,
S1/S2 = LOW/LOW, LOW/HIGH, HIGH/HIGH,
HIGH/LOW.
(1)
792
mW
20
mW
2
mW
72
mW
10
1
LP = LOW.
61.2
The maximum rating is simulated under 3.6V VCC across worse case temperature and process variation, Typical conditions are
simulated at 3.3V VCC, 25 °C with nominal process material.
RECOMMENDED OPERATING CONDITIONS
MIN NOM
VCC
Supply voltage
3
TA
Operating free-air temperature
0
3.3
MAX
UNIT
3.6
V
70
°C
TMDS DIFFERENTIAL OUTPUT PINS
VID(pp)
Peak-to-peak input differential voltage
0.15
1.56
V
VIC
Input common mode voltage
VCC
–0.4
VCC + 0.01
V
AVCC
TMDS output termination voltage
dR
Data rate
RVSADJ
Resistor for TMDS compliant voltage swing range
Rt
Termination resistance
3
3.3
3.6
3
V
Gbps
3.66
4.02
4.47
KΩ
45
50
55
Ω
5.5
V
100
Kbps
DDC PINS
VI
dR(I2C)
Input voltage
0
2
I C data rate
HPD_SINK, 5V_PWR[x], S1, S2, OVS
VIH
High-level input voltage: HPD_SINK, 5V_PWR[x], S1, S2
2
5.5
V
VIL
Low-level input voltage: HPD_SINK, 5V_PWR[x], S1, S2
0
0.8
V
VIHOVS
High-level input voltage: OVS
3
5.5
V
VILOVS
Low-level input voltage: OVS
0
0.5
V
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DEVICE POWER
The TMDS461 is designed to operate from a single 3.3-V supply voltage. The TMDS461 has three power modes
of operation. These three modes are referred to as normal mode, standby mode, and low-power mode.
Normal mode is designed to be used during typical operating conditions. In normal mode, the device is fully
functional and consumes the greatest amount of power.
Standby mode is designed to be used when reduced power is desired, but DDC and HPD communication must
be maintained. Standby mode can be enabled via the I2C interface (See Table 8) only. In standby mode, the
high-speed TMDS data and clock channels are disabled to reduce power consumption. The internal I2C logic and
DDC function normally. HPD[1:4] of the selected port follows HPD_SINK. HPD[1:4] of the non-selected port
follows 5V_PWR[1:4].
Low-power mode is designed to consume the least possible amount of power while still applying 3.3 V to the
device. Low-power mode can be enabled by either the LP pin or by local I2C (See Table 8). In low-power mode,
all of the inputs and outputs are disabled with the exception of the internal I2C logic and LP pin.
The clock-detect feature in the TMDS461 provides an automatic power-management feature in normal mode. if
no valid TMDS clock is detected, the terminations on the input TMDS data lines are disconnected, and the TMDS
outputs are high-Z. As soon as a valid TMDS clock is detected, the terminations on the TMDS data lines are
connected, the TMDS outputs come out of high-Z, and the device is fully functional and consumes the greatest
amount of power.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
ICC
Normal-mode supply current
LP = HIGH TMDS: VID(pp) = 1200 mV, 3 Gbps TMDS data pattern;
HPD_SINK = HIGH, S1/S2 = LOW/LOW, LOW/HIGH, HIGH/HIGH,
HIGH/LOW.
185
220
mA
ISTBY
Standby supply current
LP = HIGH, TMDS: VID(pp) = 1200 mV, 3 Gbps TMDS data pattern;
HPD_SINK = HIGH, (See Table 8, Register 0x02[7:6] =[0:1]. Note
that standby power mode is only available when TMDS461 is
configured in I2C mode.
3
5.5
mA
ISD
Shutdown current
LP = LOW.
300
555
µA
INCLK
Normal-mode supply current,
with no active TMDS input
clock
LP = HIGH, No TMDS input clock, HPD_SINK =HIGH, S1/S2 =
LOW/LOW,
LOW/HIGH, HIGH/HIGH, HIGH/LOW.
20
mA
17
5V DETECT and HOT PLUG DETECT
5V DETECT: TMDS461 incorporates 5V detect logic on each input port. 5V_PWR is the 5V that an HDMI/DVI
source provides to an HDMI/DVI sink. As soon as TMDS461 detects a high on any of the 5V_PWR[1:4] signals,
the 5V_Ind pin which is 5V Power detect indicator goes high. In I2C mode, a micro controller connected to
TMDS461 can read the status of 5V_PWR[x] signals by reading (See Table 7 ) I2C register 0x01.
Hot Plug Detect: The TMDS461 is designed to support the Hot Plug indication to the input ports. For the
selected port, the state of the Hot Plug output (HPD[1:4]) follows the state of the Hot Plug input (HPD_SINK). For
the non selected ports, the state of the Hot Plug outputs follows logic state of 5V_PWR. (See Table 1). HPD[x]
are internally connected to 5V_PWR[x] via 1KΩ resistor as shown in Figure 1(b). Thus even if the TMDS461 is
powered off, HPD[x] will still follow 5V_PWR[x]. When the HDMI transmitter does not have the capability of
detecting the TMDS receiver termination, using the HPD signal as a reference for sensing port selections is the
only possible method. Thus it is recommended that HPD_SINK can be held low before port selection is done and
then forced high after port selection, this ensures that HPD[x] of the selected port is pulsed High-to-Low at port
selection before HPD[x] follows HPD_SINK.
In Standby power savings mode, HPD functions similar to normal mode. In low (LP) power savings mode, the
HPD[x] follows 5V_PWR[x].
10
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5V_PW
R
UNIT
VOH(HPD[x])
High-level output voltage
5V_PWR =4.5-5.5V
V
VOL(HPD[x])
Low-level output voltage
5V_PWR =4.5-5.5V
0
0.4
V
IH(HPD_SINK)
High-level input current
VIH = 2V, VCC = 3.6 V
–10
10
µA
IL(HPD_SINK)
Low-level input current
VIL = 0.8V, VCC = 3.6 V
–10
10
µA
IH(5V_PWR[x])
High-level input current
VIH = 5.5V, VCC = 3.6 V
–10
10
µA
VOH(5V_Ind)
High-level output voltage
IOH = 100 µA
2.4
VCC
V
VOL(5V_Ind)
Low-level output voltage
IOL = 100 µA
0
0.4
RL(HPD[x])
Output source impedance
RL(HPD[x]) is connected between
5V_PWR[x] and HPD[x].
V
800
1000
1200
kΩ
MIN
TYP
MAX
UNIT
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPD1(HPD)
HPD_SINK propagation delay
HPD_SINK to HPD[1:4]
40
ns
tPD2(HPD)
5V_PWR to HPD propagation delay
5V_PWR[1:4] to HPD[1:4].
30
ns
tS1(HPD)
Selecting port HPD switch time
S[1:2] to HPD[1:4]
40
ns
tS2(HPD)
De-selecting port HPD switch time
S[1:2] to HPD[1:4]
25
ns
tz(HPD)
LP to HPD[x] switch time
LP to HPD[x]
40
ns
tPD3(5v)
5V_PWR to 5V_Ind propagation delay
5V PWR to 5V_Ind propagation Delay
(Load on 5V_Ind: 5 pF)
30
ns
5V
5 V_PWR [x]
5 V_Pwr [x]
5 V_Ind
HPD [x]
1 kW
HPD_SINK
5 pF
5 pF
5 pF
5 pF
(a)
(b)
Figure 1. 5V_PWR and HPD Test Circuit
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5V
HPD_SINK
2.5 V
tpd1(HPD)
HPD_ [x]: Selected Port
5 V_PWR
5 V_ PWR/2
5 V _ PWR[x]
5V
2.5 V
HPD_ [x]: Non Selected
Port
t pd 2(HPD)
5 V_PWR
5 V_PWR/2
5V
2.5 V
t pd3(5 V)
5 V_PWR[x]
VCC
VCC/2
5 V_Ind
5V
LP
2.5 V
2.5 V
HPD_SINK
HPD[x]: selected port
5V
t z(HPD)
t z(HPD)
(5V_PWR[x])/2
5V_PWR[x]
(5V_PWR[x])/2
Figure 2. HPD Timing Diagram #1
12
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5V
S1
2.5V
5V
2.5V
S2
t S1(HPD)
5V
2.5V
tS2 (HPD)
HPD_SINK
tpd1( HPD)
HPD[3]
(5V_PWR3)/2
PORT3 is non selected
port
5 V_PWR3
(5V_PWR3)/2
PORT3 is selected port
(5V_PWR3)/2
PORT3 is non selected
port
Figure 3. HPD Timing Diagram #2
IRQ
I2C mode: When TMDS461 is configured in I2C mode, the IRQ pin in TMDS461 functions as a system level
interrupt indicator pin. The TMDS461 issues Interrupt Requests by raising the IRQ pin from low to high, which
can be detected by the sink micro-controller. An Interrupt Request occurs when any system level change is
detected by TMDS461, which is a change in 5V_PWR on the source side, a change in the selected port, or a
change in the selected port's valid clock detect. The micro-controller can read I2C register address 0x01 to obtain
the current status of 5V_PWR, the selected port, and clock detect status. Once the micro-controller has read
0x01, the IRQ pin returns to low.
It is desired that as soon as the sink micro-controller gets an Interrupt Request, it reads I2C register address
0x01
GPIO mode: When TMDS461 is configured in GPIO mode, the IRQ pin in TMDS461 functions as a clock-detect
indicator pin for the selected port. If a valid clock is detected by the clock detect circuit, IRQ goes high. If no valid
clock is detected, IRQ is driven low. Refer to (TMDS Main Link Switching Characteristics) tCLK1 for valid clock
enable time and (TMDS Main Link Switching Characteristics) tCLK2 for valid clock disable time.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
MAX
UNIT
VOH(IRQ)
High-level output voltage
PARAMETER
IOH = 100 µA
TEST CONDITIONS
MIN
2.4
TYP
VCC
V
VOL(IRQ)
Low-level output voltage
IOL = 100 µA
0
0.4
V
RL(IRQ)
Output source impedance
800 1000
1200
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Automatic Port Select Feature
TMDS461 incorporates an AutoSelect Feature that is available in I2C mode only. Refer to Table 8, bits 3, 4, 5. If
the TMDS461 is configured in AutoSelect Mode, then the port selection is done based on the priority bit (Refer to
Table 8 , bit 3, 4) and 5V_PWR[x] (See Table 7, bit 0, 1, 2, 3) as indicated in Figure 4, Figure 5, Figure 6, and
Figure 7 .
TMDS461 configured in Automatic
Port Selection Mode with
Port 1 as Priority Port
[5V_PWR1 =High &
5V_PWR2 = X &
5V_PWR3 = X &
5V_PWR4 = X ]
Port 1 is selected
[5V_PWR1 = LOW &
5V_PWR2 = HIGH &
5V_PWR3 = X &
5V_PWR4 = X ]
Port 2 is selected
[5V_PWR1 = HIGH &
5V_PWR2 = X &
5V_PWR3 = X &
5V_PWR4 = X ]
[5V_PWR1 = LOW &
5V_PWR2 = LOW &
5V_PWR3 = HIGH &
5V_PWR4 = X ]
[5V_PWR1 = LOW &
5V_PWR2 = HIGH &
5V_PWR3 = X &
5V_PWR4 = X ]
[5V_PWR1 = LOW &
5V_PWR2 = HIGH &
5V_PWR3 = X &
5V_PWR4 = X ]
Port 3 is selected
[5V_PWR1 = LOW &
5V_PWR2 = LOW &
5V_PWR3 = LOW &
5V_PWR4 = HIGH ]
[5V_PWR1 = LOW &
5V_PWR2 = LOW &
5V_PWR3 = HIGH &
5V_PWR4 = X ]
Port 4 is selected
Figure 4. TMDS461 Configured in AutoSelect Mode, with Port 1 as Priority Port
14
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TMDS461 configured in Automatic
Port Selection Mode with
Port 2 as Priority Port
[5V_PWR2 =High &
5V_PWR1 = X &
5V_PWR3 = X &
5V_PWR4 = X ]
Port 2 is selected
[5V_PWR2 = LOW &
5V_PWR1 = HIGH &
5V_PWR3 = X &
5V_PWR4 = X ]
Port 1 is selected
[5V_PWR2 = HIGH &
5V_PWR1 = X &
5V_PWR3 = X &
5V_PWR4 = X ]
[5V_PWR2 = LOW &
5V_PWR1 = LOW &
5V_PWR3 = HIGH &
5V_PWR4 = X ]
[5V_PWR2 = LOW &
5V_PWR1 = HIGH &
5V_PWR3 = X &
5V_PWR4 = X ]
[5V_PWR2 = LOW &
5V_PWR1 = HIGH &
5V_PWR3 = X &
5V_PWR4 = X ]
Port 3 is selected
[5V_PWR2 = LOW &
5V_PWR1 = LOW &
5V_PWR3 = LOW &
5V_PWR4 = HIGH ]
[5V_PWR2 = LOW &
5V_PWR1 = LOW &
5V_PWR3 = HIGH &
5V_PWR4 = X ]
Port 4 is selected
Figure 5. TMDS461 Configured in AutoSelect Mode, with Port 2 as Priority Port
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TMDS461 configured in Automatic
Port Selection Mode with
Port 3 as Priority Port
[5V_PWR3 =High &
5V_PWR1 = X &
5V_PWR2 = X &
5V_PWR4 = X ]
Port 3 is selected
[5V_PWR3 = LOW &
5V_PWR1 = HIGH &
5V_PWR2 = X &
5V_PWR4 = X ]
Port 1 is selected
[5V_PWR3 = HIGH &
5V_PWR1 = X &
5V_PWR2 = X &
5V_PWR4 = X ]
[5V_PWR3 = LOW &
5V_PWR1 = LOW &
5V_PWR2 = HIGH &
5V_PWR4 = X ]
[5V_PWR3 = LOW &
5V_PWR1 = HIGH &
5V_PWR2 = X &
5V_PWR4 = X ]
[5V_PWR3 = LOW &
5V_PWR1 = HIGH &
5V_PWR2 = X &
5V_PWR4 = X ]
Port 2 is selected
[5V_PWR3 = LOW &
5V_PWR1 = LOW &
5V_PWR2 = LOW &
5V_PWR4 = HIGH ]
[5V_PWR3 = LOW &
5V_PWR1 = LOW &
5V_PWR2 = HIGH &
5V_PWR4 = X ]
Port 4 is selected
Figure 6. TMDS461 Configured in AutoSelect Mode, with Port 3 as Priority Port
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TMDS461 configured in Automatic
Port Selection Mode with
Port 4 as Priority Port
[5V_PWR4 =High &
5V_PWR1 = X &
5V_PWR2 = X &
5V_PWR3 = X ]
Port 4 is selected
[5V_PWR4 = LOW &
5V_PWR1 = HIGH &
5V_PWR2 = X &
5V_PWR3 = X ]
Port 1 is selected
[5V_PWR4 = HIGH &
5V_PWR1 = X &
5V_PWR2 = X &
5V_PWR3 = X ]
[5V_PWR4 = LOW &
5V_PWR1 = LOW &
5V_PWR2 = HIGH &
5V_PWR3 = X ]
[5V_PWR4 = LOW &
5V_PWR1 = HIGH &
5V_PWR2 = X &
5V_PWR3 = X ]
[5V_PWR4 = LOW &
5V_PWR1 = HIGH &
5V_PWR2 = X &
5V_PWR3 = X ]
Port 2 is selected
[5V_PWR4 = LOW &
5V_PWR1 = LOW &
5V_PWR2 = LOW &
5V_PWR3 = HIGH ]
[5V_PWR4 = LOW &
5V_PWR1 = LOW &
5V_PWR2 = HIGH &
5V_PWR3 = X ]
Port 3 is selected
Figure 7. TMDS461 Configured in AutoSelect Mode, with Port 4 as Priority Port
TMDS DDC and Local I2C Pins
DDC I2C Buffer or Repeater: The TMDS461 provides buffering on the DDC I2C interface for each of the input
ports connected. This feature isolates the capacitance on the source side from the sink side and thus helps in
passing system-level compliance. See the DDC I2C Function Description section for a detailed description on
how the DDC I2C buffer operates. Note that a key requirement on the sink side is that the VIL(Sink) (input to
TMDS461) should be less than 0.4 V. This requirement should be met for the DDC I2C buffer to function
properly. There are three settings of VIL(Sink) and VOL(Sink) that can be chosen based on OVS settings (See
Table 9).
Local I2C Interface: The TMDS461 includes a slave I2C interface to control device features like TMDS input port
selection, TMDS output edge-rate control, power management, DDC buffer OVS settings, etc. See Table 7
through Table 13. The TMDS461 is designed to be controlled via a local I2C interface or GPIO interface, based
on the status of the I2C_SEL pin. The local I2C interface in the TMDS461 is only a slave I2C interface. See the
I2C INTERFACE NOTES section for a detailed description of I2C functionality.
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ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC = 3.6 V, VI = 0 V
–10
10
µA
Sink pins
VCC = 3.6 V, VI = 4.95 V
–10
10
µA
Input/output capacitance
Sink pins
DC bias = 2.5 V, AC = 3.5 Vp-p, f = 100 kHz
15
pF
High-level input voltage
Sink pins
2.1
5.5
V
VIL1(Sink)
Low-level input voltage
Sink pins
OVS 1
–0.2
0.4
V
VOL1(Sink)
Low-level output voltage
Sink pins
IO = 3 mA, OVS = HIGH
VIL2(Sink)
Low-level input voltage
Sink pins
OVS 2
VOL2(Sink)
Low-level output voltage
Sink pins
IO = 3 mA, OVS = LOW
VIL3(Sink)
Low-level input voltage
Sink pins
OVS 3
VOL3(Sink)
Low-level output voltage
Sink pins
IO = 3 mA, OVS = high-Z
Ilkg(I2C)
Input leakage current
Port[1:4] pins
VCC = 3.6 V, VI = 4.95 V
CIO(I2C)
Input/output capacitance
Port[1:4] pins
DC bias = 2.5 V, AC = 3.5 Vp-p, f = 100 kHz
VIH(I2C)
High-level input voltage
Port[1:4] pins
VIL(I2C)
Low-level input voltage
Port[1:4] pins
VOL(I2C)
Low-level output voltage
Port[1:4] pins
IL
Low-level input current
Ilkg(Sink)
Input leakage current
CIO(Sink)
VIH(Sink)
0.6
0.7
V
–0.2
0.4
V
0.5
0.6
V
–0.2
0.3
V
0.4
0.5
V
–10
10
µA
15
pF
2.1
5.5
V
–0.2
1.5
V
0.2
V
IO = 3 mA
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH2
Propagation delay time, low to high
Source to sink
80
251
ns
tPHL2
Propagation delay time, high to low
Source to sink
35
200
ns
tPLH1
Propagation delay time, low to high
Sink to source
204
459
ns
tPHL1
Propagation delay time, high to low
Sink to source
35
200
ns
tf1
Output signal fall time
Sink side
20
72
ns
tf2
Output-signal fall time
Source side
20
72
ns
fSCL
SCL clock frequency for internal register
Local I2C
100
kHz
tW(L)
Clock LOW period for I2C register
Local I2C
4.7
µs
tW(H)
Clock HIGH period for internal register
Local I2C
4
µs
tSU1
Internal register setup time, SDA to SCL
Local I2C
250
ns
th(1)*1
Internal register hold time, SCL to SDA
Local I C
0
µs
t(buf)
Internal register bus free time between STOP and START
Local I2C
4.7
µs
tsu(2)
Internal register setup time, SCL to START
Local I2C
4.7
µs
th(2)
Internal register hold time, START to SCL
Local I2C
4
µs
4
µs
tsu(3)
2
2
Internal register hold time, SCL to STOP
Local I C
VCC
5V
RL = 2 kW
PULSE
GENERATOR
D.U.T.
CL = 100 pF
RT
VIN
VOUT
Figure 8. Sink-Side Test Circuit
18
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VCC
5V
RL = 2 kW
PULSE
GENERATOR
D.U.T.
CL = 400 pF
RT
VOUT
VIN
Figure 9. Source-Side Test Circuit
5V
SCL[x]
SDA[x]
Input
1.6 V
0.1 V
tPHL2
tPLH2
5V
SCL_SINK
SDA_SINK
Output
80%
1.6 V
20%
VOL
tf2
T0388-01
Figure 10. Sink-Side Output AC Measurements
5V
SCL_SINK
SDA_SINK
Input
1.6 V
0.1 V
tPHL1
5V
SCL[x]
SDA[x]
Output
80%
1.6 V
20%
VOL
tf1
T0389-01
Figure 11. Source-Side Output AC Measurements
5V
SCL_SINK
SDA_SINK
Input
VOL
tPLH1
5V
SCL[x]
SDA[x]
Output
1.6 V
T0390-01
Figure 12. Source-Side Output AC Measurements Cont.
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TMDS Main Link Pins
The TMDS port of the TMDS461 is designed to be compliant with the Digital Video Interface (DVI) 1.0 and High
Definition Multimedia Interface (HDMI) 1.3a specifications. The differential output voltage swing can be fine-tuned
with the VSadj resistor.
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
AVCC = 3.3 V, RT = 50 Ω. See Figure 13
VOH
Single-ended HIGH-level output voltage
VOL
Single-ended LOW-level output voltage
VSWING
Single-ended output voltage swing
VOC(SS)
Change in steady-state common-mode output voltage
between logic states
VOD(pp)
Peak-to-peak output differential voltage
V(O)SBY
Single-ended standby output voltage
TYP
MAX
UNIT
AVCC – 10
AVCC + 10
mV
AVCC –
600
AVCC –
400
mV
400
600
mV
5
mV
800
1200
mV
AVCC – 10
AVCC + 10
mV
–10
10
µA
15
mA
I(O)OFF
Single-ended power-down output current
0 V ≤ VCC ≤ 1.5 V, AVCC = 3.3 V,
RT = 50 Ω
IOS
Short-circuit output current
See Figure 20
–15
VCD(pp)
Minimum valid clock differential voltage (peak-to-peak)
Input TMDS clock frequency = 300 MHz
100
12
mV
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN TYP (1) MAX
TEST CONDITIONS
UNIT
tPLH
Propagation delay time
250
800
ps
tPHL
Propagation delay time
250
800
ps
tR1
Rise time, fastest mode (default setting): Fastest
Setting
84
110
140
ps
tF1
Fall time, fastest mode (default setting): Fastest
Setting
84
110
140
ps
tR2
Rise time, fastest mode + 50 ps (approximately)
142
160
190
ps
AVCC = 3.3 V, RT = 50 Ω. See Figure 13 and
Figure 14.
tF2
Fall time, fastest mode + 50 ps (approximately)
142
160
190
ps
tR3
Rise time, fastest mode + 100 ps (approximately)
187
210
230
ps
tF3
Fall time, fastest mode + 100 ps (approximately)
187
210
230
ps
tR4
Rise time, fastest mode + 120 ps
(approximately): Slowest Setting
216
230
260
ps
tF4
Fall time, fastest mode + 120 ps (approximately):
Slowest Setting
216
230
260
ps
tSK(P)
Pulse skew (see
8
15
ps
tSK(D)
Intra-pair skew
10
30
ps
tSK(O)
Inter-pair skew (see
100
ps
tJITD(PP)
Peak-to-peak output residual data jitter
88
ps
(1)
(2)
(3)
20
(2)
)
AVCC = 3.3 V, RT = 50 Ω. See Figure 15.
(3)
)
AVCC = 3.3 V, RT = 50 Ω, dR = 2.25 Gbps.
See Figure 18 for measurement setup;
residual jitter is the total jitter measured at
TTP4 minus the jitter measured at TTP1. See
Figure 19 for the loss profile of the cable used
for tJITD(PP) measurement. Also see Typical
Characteristics for tJITD(PP) across cable
length and input TMDS data rate.
40
All typical values are at 25°C and with a 3.3-V supply.
tsk(p) is the magnitude of the time difference between tPLH and tPHL of a specified terminal.
tsk(o) is the magnitude of the difference in propagation delay times between any specified terminals of a sink-port bank when inputs of
the active source port are tied together.
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SWITCHING CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN TYP (1) MAX
TEST CONDITIONS
UNIT
tJITC(PP)
Peak-to-peak output residual clock jitter
AVCC = 3.3 V, RT = 50 Ω, input TMDS clock
frequency = 225 MHz. See Figure 18 for
measurement setup; residual jitter is the total
jitter measured at TTP4 minus the jitter
measured at TTP1. See Figure 19 for the loss
profile of the cable used for tJITC(PP)
measurement.
10
35
ps
tCLK1
Valid clock-detect enable time
AVCC = 3.3 V, RT = 50 Ω, input TMDS clock
frequency = 300 MHz. See Figure 17.
300
500
ns
tCLK2
Invalid clock-detect disable time
AVCC = 3.3 V, RT = 50 Ω, input TMDS clock
frequency = 1 MHz. See Figure 17.
500
800
ns
tSEL1
Port selection time (see
AVCC = 3.3 V, RT = 50 Ω
300
500
ns
tSEL2
Port deselection time (see
AVCC = 3.3 V, RT = 50 Ω
40
50
ns
fCD
Clock-detect frequency
300
MHz
(4)
(5)
(4)
(5)
)
AVCC = 3.3 V, RT = 50 Ω. See Figure 17.
25
tSEL1 includes the time for the valid clock detect enable time and tS1(HPD), because the tS1(HPD) event happens in parallel with tSEL1; thus,
the tSEL1 time is primarily the tCLK1 time.
tSEL2 is primarily the tS2(HPD) time.
VCC
AVCC
50 W
50 W
50 W
50 W
0.5 pF
D+
Y
VD+ VID
VY
D-
VD-
VID = VD+ - VDVICM = (VD+ + VD-)
2
Z
VOD = VY - VZ
VOC = (VY + VZ)
VZ
2
Figure 13. TMDS Main Link Test Circuit
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3.3 V
VID
2.8 V
VID
VID(PP)
0V
VIDtPLH
tPHL
80%
80%
VOD
VOD(PP)
0V
20%
20%
tr
tf
Figure 14. TMDS Main Link Timing Measurements
VOH
VY
50%
VZ
VOL
tsk(D)
Figure 15. Definition of Intra-Pair Differential Skew
0
ΔVOC(SS)
VOC
Figure 16. TMDS Main Link Common Mode Measurements
VCD(PP)
Valid Input TMDS clock
that meets the min
Frequency Threshold and
Amplitude
tclk1
tclk2
TMDS outputs
Hi Z during this duration
VOD(PP)
TMDS
outputs
Hi Z
TMDS output clock with
peak to peak swing
compliant to the HDMI
spec and same frequency
as the Input TMDS clock
frequency
T0424-01
Figure 17. Clock-Detect Timing Diagram
22
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(4)
AVCC
RT
Data+
Video Data–
Patterm
Generator
1000-mVpp
Differential
Coax
Coax
SMA
(6)
RX
+EQ
SMA
SMA
<2-Inch 50-W
Transmission Line
OUT
(6)
SMA
<2-Inch 50-W
Transmission Line
Coax
Coax
Jitter Test
HDMI Cable
AVCC Instrument(2, 3)
(1)
TMDS461
RT
Clk+
Clk–
(5)
RT
Coax
Coax
SMA
(6)
RX
+EQ
SMA
SMA
<2-Inch 50-W
Transmission Line
OUT
(6)
SMA
<2-Inch 50-W
Transmission Line
RT
Coax
Coax
Jitter Test
(2, 3)
Instrument
TTP1
TTP2
TTP4
TTP3
(1)
The HDMI cable between TTP1 and TTP2 is 20 m. See Figure 19 for the loss profile of the cable.
(2)
All jitter is measured at a BER of 10–9.
(3)
Residual jitter is the total jitter measured at TTP4 minus the jitter measured at TTP1.
(4)
AVCC = 3.3 V.
(5)
RT = 50 Ω.
(6)
2 inches = 5.08 cm.
Figure 18. TMDS Jitter Measurements
0
HDMI Cable 20 m
−5
Amplitude − dB
−10
−15
−20
−25
−30
−35
0.0
0.5
1.0
1.5
2.0
2.5
3.0
f − Frequency − GHz
G001
Figure 19. Loss Profile of 20-m Cable
50 W
Driver
IOS
50 W
+
-
0 V or 3.6 V
Figure 20. TMDS Main Link Short Circuit Output Circuit
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TYPICAL CHARACTERISTICS
AVCC = 3.3 V, RT = 50 Ω
POWER
vs
AMBIENT TEMPERATURE
POWER
vs
INPUT TMDS DATA RATE
590
590
VCC = 3.3 V, Input TMDS Data Rate = 2.25 Gbps
580
580
TA = 25°C, VCC = 3.3 V, VSadj = 4.02 KΩ
VSadj = 4.02 KΩ
570
570
Fastest (Default) TMDS Output Edge Rate
Fastest (Default) TMDS Output Edge Rate
560
550
Power − mW
Power − mW
560
540
530
520
550
540
530
520
Slowest TMDS Output Edge Rate
510
510
500
500
490
0
10
20
30
40
50
60
TA − Ambient Temperature − °C
Slowest TMDS Output Edge Rate
490
0.0
70
0.5
1.0
1.5
2.0
Figure 21.
Figure 22.
PEAK-PEAK RESIDUAL DATA JITTER
vs
INPUT TMDS DATA RATE
PEAK-PEAK RESIDUAL DATA JITTER
vs
HDMI CABLE LENGTH
140
TA = 25°C
VCC = 3.3 V
VSadj = 4.02 kΩ
Peak-to-Peak Residual Data Jitter − ps
Peak-to-Peak Residual Data Jitter − ps
90
20 m, 24 AWG
HDMI Cable
70
15 m, 26 AWG
HDMI Cable
60
50
40
10 m, 28 AWG
HDMI Cable
30
20
10
3 m, 28 AWG
HDMI Cable
0.5
1.0
1.5
2.0
2.5
120
100
80
60
40
20
0
3.0
3.5
20 m
28 AWG
20 m
24 AWG
Input TMDS Data Rate − Gbps
G005
Figure 23.
24
3.5
G003
VSadj = 4.02 kΩ, TA =25°C, VCC = 3.3 V
0
0.0
3.0
G002
100
80
2.5
Input TMDS Data Rate − Gbps
15 m
10 m
26 AWG 28 AWG
5m
3m
3m
1m
1m
28 AWG 28 AWG 30 AWG 28 AWG 30 AWG
HDMI Cable Length
G007
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
VOD(pp)
vs
VSadj
VOD(pp) − Differential Output Voltage − mV
1600
TA = 25°C
1400
VCC = 3.6 V
1200
VCC = 3.3 V
1000
VCC = 3 V
800
600
400
200
0
3
4
5
6
7
VSadj Resistance − kΩ
G008
Figure 25.
TP1
TP2
TP3
TMDS461 T est Board
Video
HDMI Cable
TMDS
461
Format
Generator
Figure 26. HDMI Cable Test-Point Configuration
Figure 27. Eye at TP3 (output of TMDS461) with 20 m, 24
AWG HDMI cable, 2.25 Gbps Input TMDS data Rate,
Fastest Rise and Fall Time Setting on TMDS outputs
Figure 28. Eye at TP3 (output of TMDS461) with 20 m, 24
AWG HDMI cable, 3 Gbps Input TMDS data Rate, Fastest
Rise and Fall Time Setting on TMDS outputs
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TYPICAL CHARACTERISTICS (continued)
Figure 29. Eye at TP3 (output of TMDS461) with 3 m, 28
AWG HDMI cable, 3 Gbps Input TMDS data Rate, Fastest
Rise and Fall Time Setting on TMDS outputs
Figure 30. Eye at TP3 (output of TMDS461) with 3 m, 28
AWG HDMI cable, 3 Gbps Input TMDS data Rate, Slowest
Rise and Fall Time Setting on TMDS outputs
Figure 31. Eye at TP3 (output of TMDS461) with 20 m, 24
AWG HDMI cable, 2.25 Gbps Input TMDS data Rate,
Slowest Rise and Fall Time Setting on TMDS outputs
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APPLICATION INFORMATION
Supply Voltage
The TMDS461 is powered up with a single power source that is 3.3-V VCC for the TMDS circuitry for HPD, DDC,
and most of the control logic.
TMDS Input Fail-Safe
The TMDS461 incorporates clock-detect circuitry. If there is no valid TMDS clock from the connected HDMI/DVI
source, the TMDS461 does not switch on the terminations on the source-side data channels. Additionally, the
TMDS outputs are placed in the high-impedance state. This prevents the TMDS461 from turning on its outputs if
there is no valid incoming HDMI/DVI data.
TMDS Outputs
A 10% precision resistor, 4.02-kΩ, is recommended to control the output swing to the HDMI-compliant 800-mV to
1200-mV range VOD(pp) (1000 mV typical).
DDC I2C Function Description
The TMDS461 provides buffers on the DDC I2C lines on all four input ports. This section explains the operation
of the buffer. For representation, the source side of the TMDS461 is represented by RSCL/RSDA, and the sink
side is represented by TSCL/TSDA. The buffers on the RSCL/RSDA and TSCL/TSDA pins are 5-V tolerant when
the device is powered off and high-impedance under low supply voltage, 1.5 V or below. If the device is powered
up, the driver T (see Figure 32) is turned on or off depending on the corresponding R-side voltage level.
When the R side is pulled low below 1.5 V, the corresponding T-side driver turns on and pulls the T side down to
a low level output voltage, VOL. The value of VOL and VIL on the T side or the sink side of the TMDS461 switch
depends on the output-voltage select (OVS) control settings. OVS control can be changed by the slave I2C, see
Table 9. When the OVS1 setting is selected, VOL is typically 0.7 V and VIL is typically 0.4 V. When the OVS2
setting is selected, VOL is typically 0.6 V and VIL is typically 0.4 V. When OVS3 setting (default) is selected, VOL is
typically 0.5 V and VIL is typically 0.3 V. VOL is always higher than the driver-R input threshold, VIL on the T side
or the sink side, preventing lockup of the repeater loop. The TMDS461 is targeted primarily as a switch in the
HDTV market and is expected to be a companion chip to an HDMI receiver; thus, the OVS control has been
provided on the sink side, so that the requirement of VIL to be less than 0.4 V can be met. The VOL value can be
selected to improve or optimize noise margins between VOL and VIL of the repeater itself or VIL of some external
device connected on the T side.
When the R side is pulled up, above 1.5 V, the T-side driver turns off and the T-side pin is high-impedance.
OVS
T
RSCL
RSDA
TSCL
TSDA
R
B0344-01
Figure 32. I2C Drivers in the TMDS461 = Side Is the HDMI Source Side, T Side Is the HDMI Sink Side)
When the T side is pulled below 0.4 V by an external I2C driver, both drivers R and T are turned on. Driver R
pulls the R side to near 0 V, and driver T is on, but is overridden by the external I2C driver. If driver T is already
on, due to a low on the R side, driver R just turns on.
When the T side is released by the external I2C driver, driver T is still on, so the T side is only able to rise to the
VOL of driver T. Driver R turns off, because VOL is above its 0.4-V VIL threshold, releasing the R side. If no
external I2C driver is keeping the R side low, the R side rises, and driver T turns off once the R side rises above
1.5 V, see Figure 33.
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Vcc
TSCL/TSDA
0.5V
tPLH
5V +
10%
RSCL/RSDA
Vcc/2
Figure 33. Waveform of Driver T Turning Off
It is important that any external I2C driver on the T side is able to pull the bus below 0.4 V to achieve full
operation. If the T side cannot be pulled below 0.4 V, driver R may not recognize and transmit the low value to
the R side.
DDC I2C Behavior
The typical application of the TMDS461 is as a 4:1 switch in a TV connecting up to four HDMI input sources to
an HDMI receiver. The I2C repeater is 5-V tolerant, and no additional circuitry is required to translate between
3.3-V and 5-V bus voltages. In the following example, the system master is running on an R-side I2C-bus while
the slave is connected to a T-side bus. Both buses run at 100 kHz, supporting standard-mode I2C operation.
Master devices can be placed on either bus.
VRdd
V Tdd
Driver T
RRup
RTup
Master
Slave
CSOURCE
CI
CO
Cslave
Driver R
Cmedium
CCABLE
Figure 34. Typical Application
Figure 35 illustrates the waveforms seen on the R-side I2C-bus when the master writes to the slave through the
I2C repeater circuit of the TMDS461. This looks like a normal I2C transmission, and the turnon and turnoff of the
acknowledge signals are slightly delayed.
9th Clock Pulse - Acknowledge From Slave
RSCL
RSDA
Figure 35. Bus-R Waveform
28
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Figure 36 illustrates the waveforms seen on the T-side I2C-bus under the same operation as in Figure 35. On the
T-side of the I2C repeater, the clock and data lines would have a positive offset from ground equal to the VOL of
the driver T. After the 8th clock pulse, the data line is pulled to the VOL of the slave device, which is very close to
ground in this example. At the end of the acknowledge, the slave device releases and the bus level rises back to
the VOL set by the driver until the R-side rises above VCC/2, after which it continues to be high. It is important to
note that any arbitration or clock-stretching events require that the low level on the T-side bus at the input of the
TMDS461 I2C repeater is below 0.4 V to be recognized by the device and then transmitted to the R-side I2C bus.
9th Clock Pulse - Acknowledge From Slave
TSCL
TSDA
VOL Of Driver T
V OL Of Slave
Figure 36. Bus T Waveform
I2C Pullup Resistors
The pullup resistor value is determined by two requirements:
1. The maximum sink current of the I2C buffer is 3 mA or slightly higher for an I2C driver supporting
standard-mode I2C operation.
Rup(min) = VDD/Isink
(1)
2. The maximum transition time, T, of an I2C on the bus is set by an RC time constant, where R is the pullup
resistor value and C is the total load capacitance. The parameter, k, can be calculated from Equation 3 by
solving for t, the times at which certain voltage thresholds are reached. Different input threshold
combinations introduce different values of t. Table 3 summarizes the possible values of k under different
threshold combinations.
T = k × RC
(2)
–t/RC
V(t) = VDD(1 – e
)
(3)
Table 3. Value of k for Different Input Threshold Voltages
Vth–\Vth+
0.7 VDD
0.65 VDD
0.6 VDD
0.55 VDD
0.5 VDD
0.45 VDD
0.4 VDD
0.35 VDD
0.3 VDD
0.1 VDD
1.0986
0.9445
0.8109
0.6931
0.5878
0.4925
0.4055
0.3254
0.2513
0.15 VDD
1.0415
0.8873
0.7538
0.6360
0.5306
0.4353
0.3483
0.2683
0.1942
0.2 VDD
0.9808
0.8267
0.6931
0.5754
0.4700
0.3747
0.2877
0.2076
0.1335
0.25 VDD
0.9163
0.7621
0.6286
0.5108
0.4055
0.3102
0.2231
0.1431
0.0690
0.3 VDD
0.8473
0.6931
0.5596
0.4418
0.3365
0.2412
0.1542
0.0741
—
From Equation 1, Rup(min) = 5.5 V/3 mA = 1.83 kΩ to operate the bus under a 5-V pullup voltage and provide less
than 3 mA when the I2C device is driving the bus to a low state. If a higher sink current, for example 4 mA, is
allowed, Rup(min) can be as low as 1.375 kΩ.
Given a 5-V I2C device with input low and high threshold voltages at 0.3 Vdd and 0.7 Vdd, respectively, the value
of k is 0.8473 from Table 3. Taking into account the 1.83-kΩ pullup resistor, the maximum total load capacitance
is C(total-5V) = 645 pF. Ccable(max) should be restricted to be less than 545 pF if Csource and CI can be as high as 50
pF. Here the CI is treated as Csink, the load capacitance of a sink device.
Fixing the maximum transition time from Table 3, T = 1 µs, and using the k values from Table 3, the
recommended maximum total resistance of the pullup resistors on an I2C bus can be calculated for different
system setups.
To support the maximum load capacitance specified in the HDMI spec, Ccable(max) = 700 pF/Csource = 50 pF/CI =
50 pF, R(max) can be calculated as shown in Table 4.
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Table 4. Pullup Resistor for Different Threshold Voltages and 800-pF Load
Vth–\Vth+
0.7 VDD
0.65 VDD
0.6 VDD
0.55 VDD
0.5 VDD
0.45 VDD
0.4 VDD
0.35 VDD
0.3 VDD
UNIT
0.1 VDD
1.14
1.32
1.54
1.80
2.13
2.54
3.08
3.84
4.97
kΩ
0.15 VDD
1.20
1.41
1.66
1.97
2.36
2.87
3.59
4.66
6.44
kΩ
0.2 VDD
1.27
1.51
1.80
2.17
2.66
3.34
4.35
6.02
9.36
kΩ
0.25 VDD
1.36
1.64
1.99
2.45
3.08
4.03
5.60
8.74
18.12
kΩ
0.3 VDD
1.48
1.80
2.23
2.83
3.72
5.18
8.11
16.87
—
kΩ
Or, limiting the maximum load capacitance of each cable to 400 pF to accommodate with I2C spec version 2.1.
Ccable(max) = 400 pF/Csource = 50 pF/CI = 50 pF, the maximum values of R(max) are calculated as shown in Table 5.
Table 5. Pullup Resistor Upon Different Threshold Voltages and 500-pF Loads
Vth–\Vth+
0.7 VDD
0.65 VDD
0.6 VDD
0.55 VDD
0.5 VDD
0.45 VDD
0.4 VDD
0.35 VDD
0.3 VDD
0.1 VDD
1.82
2.12
2.47
2.89
3.40
4.06
4.93
6.15
7.96
UNIT
kΩ
0.15 VDD
1.92
2.25
2.65
3.14
3.77
4.59
5.74
7.46
10.30
kΩ
0.2 VDD
2.04
2.42
2.89
3.48
4.26
5.34
6.95
9.63
14.98
kΩ
0.25 VDD
2.18
2.62
3.18
3.92
4.93
6.45
8.96
13.98
28.99
kΩ
0.3 VDD
2.36
2.89
3.57
4.53
5.94
8.29
12.97
26.99
—
kΩ
Obviously, to accommodate the 3-mA drive current specification, a narrower threshold voltage range is required
to support a maximum 800-pF load capacitance for a standard-mode I2C bus.
When the input low- and high-level threshold voltages, Vth– and Vth+, are 0.7 V and 1.9 V, respectively, which is
0.15 VDD and 0.4 VDD, approximately. With VDD = 5 V from Table 4, the maximum pullup resistor is 3.59 kΩ. The
allowable pullup resistor is in the range of 1.83 kΩ and 3.59 kΩ.
Layout Considerations
The high-speed differential TMDS inputs are the most critical paths for the TMDS461. There are several
considerations to minimize discontinuities on these transmission lines between the connectors and the device:
• Maintain 100-Ω differential transmission line impedance into and out of the TMDS461.
• Keep an uninterrupted ground plane beneath the high-speed I/Os.
• Keep the ground-path vias to the device as close as possible to allow the shortest return current path.
• Keep the trace lengths of the TMDS signals between connector and device as short as possible.
Using the TMDS461 in Systems with CEC Link Requirements
The TMDS461 supports a DTV with up to four HDMI inputs when used in conjunction with a signal-port HDMI
receiver. The CEC is an optional feature of the HDMI interface for centralizing and simplifying user control
instructions from multiple audio/video products in an interconnected system, even when all the audio/video
products are from different manufacturers. This feature minimizes the number of remote controls in a system, as
well as reducing the number of times buttons must be pressed.
In TMDS461, the HPD[x] of non-selected port follows the 5V_PWR[x] in normal operation. In Low Power mode (
LP mode) or if the TMDS461 is powered off, the HPD[x] will still follow 5V_PWR[x] from source, thus if it is
desired for the source to read the E-EDID memory in LP mode, a possible configuration in Figure 37 is
recommended.
30
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A DTV Supporting an Active CEC Link
In Figure 37, the CEC PHY and CEC LOGIC functions are included. The DTV can initiate and/or react to CEC
signals from its remote control or other audio/video products on the same CEC bus. All sources must have their
own CEC physical address to support the full functionality of the CEC link.
A source reads its CEC physical address stored its E-EDID memory after receiving a logic-high from the HPD
feedback. When HPD is high, the sink-assigned CEC physical address should be maintained. Otherwise, when
HPD is low, the source sets CEC physical address value to (F.F.F.F).
SINK
HPD
5V
HPD1
HPD
5V
5V_PWR[1]
5V
SOURCE 1
SDA
SCL
CEC
SDA
SCL
CLK
D0
CEC
CLK
D0
D1
D2
47kW
CEC E-EDID
D1
D2
VCC
(3.3 V)
Local_SCL
Local_SDA
SDA1
SCL1
mController
CEC
LOGIC
A11/B11
A12/B12
A13/B13
A14/B14
CEC
PHY
HPD
5V
SDA
SCL
CEC
SDA
SCL
CEC
CLK
D0
CLK
D0
D1
D2
HPD
5V
47kW
CEC E-EDID
D1
D2
SOURCE 3
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
CLK
D0
SOURCE 4
47kW
CEC E-EDID
D1
D2
CLK
D0
D1
D2
D1
D2
A21/B21
A22/B22
A23/B23
A24/B24
HDMI RX
5V_Ind
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
VSADJ
SDA3
SCL3
4.02 k W 10%
A31/B31
A32/B32
A33/B33
A34/B34
HPD4
HPD
5V
SDA
SCL
CEC
CLK
D0
SDA2
SCL2
5V_PWR[3]
5V_PWR[4]
5V
SDA
SCL
CEC
3.3V
4.7kW
4.7kW
DDC_SDA
SDA_SINK
DDC_SCL
SCL_SINK
HPD3
HPD
5V
5V
SDA
SCL
CEC
1 kW
5V_PWR[2]
5V
SOURCE 2
HPD_SINK
HPD2
HPD
5V
47kW
CEC E-EDID
SDA4
SCL4
A41/B41
A42/B42
A43/B43
A44/B44
GND
Figure 37. Four-Port HDMI-Enabled DTV With TMDS461 – CEC Commands Active
I2C INTERFACE NOTES
The I2C interface is used to access the internal registers of the TMDS461. I2C is a two-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA and
SCL. A master device, usually a micro controller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addressing information. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on
the bus under control of the master device. The TMDS461 works as a slave and supports standard-mode
transfer (100 kbps).
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The basic I2C start and stop access cycles are shown in Figure 38.
The basic access cycle consists of the following:
• A start condition
• A slave address cycle
• Any number of data cycles
• A stop condition
SDA
SDA
SCL
SCL
S
P
Start
Condition
Stop
Condition
T0393-01
2
Figure 38. I C Start and Stop Conditions
GENERAL I2C PROTOCOL
•
•
•
•
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 38. All I2C-compatible devices should
recognize a start condition.
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 39). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 40) by pulling the SDA line low during
the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from
the slave (R/W bit 1). In either case, the receiver must acknowledge the data sent by the transmitter. So an
acknowledge signal can be generated either by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (See Figure 42 through Figure 45).
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 38). This releases the bus and stops the communication link
with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
SDA
SCL
Data Line
Stable;
Data Valid
Change of Data Allowed
T0394-01
Figure 39. I2C Bit Transfer
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Data Output
by Transmitter
Not Acknowledge
Data Output
by Receiver
Acknowledge
SCL From
Master
1
2
8
9
S
Clock Pulse for
Acknowledgement
START
Condition
T0395-01
2
Figure 40. I C Acknowledge
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
SCL
SDA
MSB
Acknowledge
Slave Address
Stop
Acknowledge
Data
T0396-01
2
Figure 41. I C Address, Data Cycle(s), and Stop
During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting
device after the last byte is transferred. An example of a write cycle can be found in Figure 42 and Figure 43.
Note that the TMDS461 allows multiple write transfers to occur. See the Example – Writing to the TMDS461
section for more information.
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not-acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 44 and Figure 45.
See the Example – Reading from the TMDS461 section for more information.
From Receiver
S
Slave Address
W
A
Data
A
Data
A
P
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
From Transmitter
R0007-01
Figure 42. I2C Write Cycle
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Acknowledge
(From Receiver)
Start
Condition
A5
A6
SDA
A1
A0
R/W ACK
D7
2
I C Device Address and
Read/Write Bit
Acknowledge
(Receiver)
D6
D1
Acknowledge
(Receiver)
D0 ACK
D7
D6
D1
D0 ACK
Stop
Condition
Other Last Data Byte
Data Bytes
First Data Byte
T0397-01
Figure 43. Multiple-Byte Write Transfer
S
Slave Address
W
A
Data
Data
A
A
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
P
Transmitter
Receiver
R0008-01
2
Figure 44. I C Read Cycle
Acknowledge
Acknowledge
(From Receiver) (From Transmitter)
Start
Condition
A0 R/W ACK
A6
SDA
2
I C Device Address and
Read/Write Bit
D7
D0
ACK
D7
Not Acknowledge
(Transmitter)
D6
D1
D0
First Data
Other Last Data Byte
Byte
Data Bytes
ACK
Stop
Condition
T0398-01
Figure 45. Multiple-Byte Read Transfer
Slave Address
Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. These resistors should
comply with the I2C specification that ranges from 2 kΩ to 19 kΩ. When the bus is free, both lines are high. The
address byte is the first byte received following the START condition from the master device. The 7-bit address is
factory preset to 0101100 or 0101101 based on the status of the Local_Addr pin . Table 6 lists the calls to which
the TMDS461 responds.
Table 6. TMDS461 Slave Address
FIXED ADDRESS
READ/WRITE BIT
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (R/W)
0
1
0
1
1
0
0 (Local_Addr pin =LOW)
1 (Local_Addr pin = HIGH)
1/0
EXAMPLE – WRITING TO THE TMDS461
The proper way to write to the TMDS461 is illustrated as follows:
An I2C master initiates a write operation to the TMDS461 by generating a start condition (S) followed by the
TMDS461 I2C address (as shown following, in MSB-first bit order, followed by a 0 to indicate a write cycle. After
receiving an acknowledge from the TMDS461, the master presents the subaddress (sink port) to be written,
consisting of one byte of data, MSB-first. The TMDS461 acknowledges the byte after completion of the transfer.
Finally, the master presents the data to be written to the register (sink port), and the TMDS461 acknowledges the
byte. The master can continue presenting data to be written after TMDS461 acknowledges the previous byte
(steps 6, 7). After the last byte to be written has been acknowledged by TMDS461, the I2C master then
terminates the write operation by generating a stop condition (P).
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Step 1
2
0
I C start (master)
S
Step 2
7
6
5
4
3
2
1
0
0
1
0
1
1
0
0 (Local_Addr pin =LOW)
1 (Local_Addr pin = HIGH)
0
2
I C general address (master)
Step 3
8
I2C acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C write sink logic address (master)
0
0
0
0
Addr
Addr
Addr
Addr
Step 5
8
I2C acknowledge (slave)
A
Step 6
I2C write data (master)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Data is the register address or register data to be written
Step 7
8
2
I C acknowledge (slave)
A
Step 8
0
2
I C stop (master)
P
An example of the proper bit control for selecting port 2 is:
Step 4: 0000 0011
Step 6: 00101000
EXAMPLE – READING FROM THE TMDS461
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master
initiates a write operation to the TMDS461 by generating a start condition (S) followed by the TMDS461 I2C
address, in MSB-first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the
TMDS461, the master presents the subaddress of the register to be read. After the cycle is acknowledged (A),
the master may optionally terminate the cycle by generating a stop condition (P).
The second phase is the data phase. In this phase, an I2C master initiates a read operation to the TMDS461 by
generating a start condition followed by the TMDS461 I2C address (as shown following for a read operation), in
MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TMDS461, the I2C
master receives one byte of data from the TMDS461. The master can continue receiving data byes by issuing an
acknowledge after each byte read (steps 10, 11). After the last data byte has been transferred from the
TMDS461 to the master, the master generates a not-acknowledge followed by a stop.
TMDS461 Read Phase 1
Step 1
0
I2C start (master)
S
Step 2
7
6
5
4
3
2
1
0
I2C general address (master)
0
1
0
1
1
0
0 (Local_Addr pin =LOW)
1 (Local_Addr pin = HIGH)
0
Step 3
8
2
I C acknowledge (slave)
A
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Step 4
7
6
5
4
3
2
1
0
I2C write sink logic address (master)
0
0
0
0
Addr
Addr
Addr
Addr
Where Addr is determined by the values shown in Table 6.
Step 5
8
I2C acknowledge (slave)
A
Step 6
0
I2C stop (master)
P
Step 6 is optional.
TMDS461 Read Phase 2
Step 7
0
I2C start (master)
S
Step 8
7
6
5
4
3
2
1
0
I2C general address (master)
0
1
0
1
1
0
0 (Local_Addr pin =LOW)
1 (Local_Addr pin = HIGH)
1
Step 9
8
2
I C acknowledge (slave)
A
Step 10
I2C read data (slave)
7
6
5
4
3
2
1
0
Data
Data
Data
Data
Data
Data
Data
Data
Where data is determined by the logic values contained in the internal registers.
Step 11A
8
I2C acknowledge (master)
A
If Step 11A is executed, go to step 10. If Step 11B is executed, go to Step 12.
Step 11B
2
8
I C not acknowledge (master)
A
Step 12
0
2
I C stop (master)
36
P
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Table 7. I2C Register 0x01 Lookup Table (1)
BIT
VALUE
STATE
7
0
RSVD
6:5
Bit 6
Bit 5
0
0
0
1
Indicates Port 2 is selected as the active port, all other ports are disabled
1
0
Indicates Port 3 is selected as the active port, all other ports are disabled
1
1
Indicates Port 4 is selected as the active port, all other ports are disabled
1
Valid TMDS
Clock Detected
0
No Valid TMDS
Clock Detected
1
Port 4
5V_PWR
Detected
0
Port 4
5V_PWR not
Detected
1
Port 3
5V_PWR
Detected
0
Port 3
5V_PWR not
Detected
1
Port 2
5V_PWR
Detected
0
Port 2
5V_PWR not
Detected
1
Port 1
5V_PWR
Detected
0
Port 1
5V_PWR not
Detected
4
3
2
1
0
DEFAULT DESCRIPTION
X
Reserved
Port Select Status Indicator
X
Indicates Port 1 is selected as the active port, all other ports are disabled
A valid TMDS clock signal is detected on the selected input port. If clock-detect circuit is
disabled in I2C register 0x03, then bit 4 of I2C register 0x01 will always be 1.
X
The selected port does not have a valid TMDS clock signal
5V_PWR is detected as HIGH on Port 4
X
5V_PWR is detected as LOW on Port 4
5V_PWR is detected as HIGH on Port 3
X
5V_PWR is detected as LOW on Port 3
5V_PWR is detected as HIGH on Port 2
X
5V_PWR is detected as LOW on Port 2
5V_PWR is detected as HIGH on Port 1
X
5V_PWR is detected as LOW on Port 1
I2C register 0x01 is Read Only. This register is supposed to be read by the sink micro-controller on IRQ interrupt (IRQ goes high). The
register values get updated in real time. IRQ will be reset (IRQ goes low) once the sink micro controller has completed reading this
register.
(1)
Table 8. I2C Register 0x02 Lookup Table (1)
BIT
VALUE
STATE
7:6
Bit 7
Bit 6
1
0
Device enters low power mode (LP mode)
1
1
Device enters low power mode (LP mode)
0
1
0
0
1
Automatic Port
Select On
0
Automatic Port
Select Off
5
(1)
DEFAULT
DESCRIPTION
Power Mode
Device is in Standby mode
X
Device is in normal power mode
Port Selection will be automatic based on state of 5V_PWR[1:4] as indicated by I2C
register 0x01:bits[3:0] and priority bit which is I2C register 0x02:bits [4:3]
X
Port Selection based on I2C register 0x03:bits [6:5]
During switching of modes between Auto-select on/off, it is required that the sink micro controller reads the register 0x01 to determine
which port is selected. Register 0x02 is Read/Write.
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Table 8. I2C Register 0x02 Lookup Table (continued)
BIT
VALUE
STATE
DEFAULT
DESCRIPTION
4:3
Bit 4
Bit 3
0
0
0
1
Port 2 is the priority port
1
0
Port 3 is the priority port
1
1
2
0
Reserved
1:0
Bit 1
Bit 0
1
1
Fastest TMDS output rise and fall time setting + 120 ps approximately (slowest rise and
fall time setting)
1
0
Fastest TMDS output rise and fall time setting + 100 ps approximately
0
1
0
0
Priority Select
X
Port 1 is the priority port
Port 4 is the priority port
X
Reserved (Do not write a 1 to this bit)
Output Edge Rate Control
Fastest TMDS output rise and fall time setting + 50 ps approximately
X
Fastest TMDS output rise and fall time setting
Table 9. I2C Register 0x03 Lookup Table (1)
BIT
VALUE
STATE
DEFAULT
DESCRIPTION
7
0
Clock
Detect
Enabled
X
Clock Detect Circuit Enabled. It is recommended that TMDS461 is used in this default mode in
the normal operation, where clock-detect circuit is enabled. The terminations on the TMDS input
data lines are connected only when valid TMDS clock is detected on the selected port.
1
Clock
Detect
Disabled
Bit 6
Bit 5
0
0
0
1
Port 2 is selected as the active port, all other ports disabled.
1
0
Port 3 is selected as the active port, all other ports disabled.
1
1
Port 4 is selected as the active port, all other ports disabled.
Bit 4
Bit 3
0
0
0
1
6:5
4:3
2:0
(1)
1
1
0
RSVD
Clock Detect Circuit Disabled. For HDMI compliance testing (TMDS Termination Voltage Test),
clock-detect feature should be disabled. In this mode the terminations on the TMDS input data
lines are always connected when the port is selected.
Port select I2C mode
X
Port 1 is selected as the active port, all other ports disabled.
OVS Control
X
X
DDC sink side VOL and VIL offset range 2: VIL2 (max) : 0.4V, VOL2
(max)
: 0.6V
DDC sink side VOL and VIL offset range 3: VIL3 (max) : 0.3V, VOL3
(max)
: 0.5V
DDC sink side VOL and VIL offset range 1: VIL1 (max) : 0.4V, VOL1
(max)
: 0.7V
Reserved
Register 0x03 is Read/Write.
Table 10. I2C Register 0x04 Lookup Table (1)
BIT
VALUE
STATE
DEFAULT
7:0
—
RSVD
X
(1)
DESCRIPTION
Reserved. Read-only, value is indeterministic.
Register x04 is TI internal usage only.
Table 11. I2C Register 0x05 Lookup Table (1)
BIT
VALUE
STATE
DEFAULT
7:0
—
RSVD
X
(1)
DESCRIPTION
Reserved. Read-only, value is indeterministic.
Register x05 is TI internal usage only.
Table 12. I2C Register 0x06 Lookup Table (1)
BIT
VALUE
STATE
DEFAULT
7:0
—
RSVD
X
(1)
Register x06 is TI internal usage only.
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DESCRIPTION
Reserved. Read-only, value is indeterministic.
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Table 13. I2C Register 0x07 Lookup Table (1)
BIT
VALUE
7:6
5
4
3
2
1
0
(1)
STATE
DEFAULT
0
RSVD
X
1
Port Select
Changed
0
Port Select
Unchanged
1
Clock-Detect
Changed
0
Clock-Detect
Unchanged
1
Port 4
5V_PWR
Changed
0
Port 4
5V_PWR
Unchanged
1
Port 3
5V_PWR
Changed
0
Port 3
5V_PWR
Unchanged
1
Port 2
5V_PWR
Changed
0
Port 2
5V_PWR
Unchanged
1
Port 1
5V_PWR
Changed
0
Port 1
5V_PWR
Unchanged
DESCRIPTION
Reserved
The selected port has changed since reading 0x01
X
The selected port has not changed since reading 0x01
The selected port’s clock detect status has changed since reading 0x01
X
The selected port’s clock detect status has not changed since reading 0x01
5V_PWR on Port 4 has changed since reading 0x01
X
5V_PWR on Port 4 has not changed since reading 0x01
5V_PWR on Port 3 has changed since reading 0x01
X
5V_PWR on Port 3 has not changed since reading 0x01
5V_PWR on Port 2 has changed since reading 0x01
X
5V_PWR on Port 2 has not changed since reading 0x01
5V_PWR on Port 1 has changed since reading 0x01
X
5V_PWR on Port 1 has not changed since reading 0x01
I2C register 0x07 is Read Only. The register values get latched whenever a system-level interrupt occurs (IRQ goes high); and, the
register values are cleared when the IRQ gets cleared upon reading register 0x01. This I2C register can be used for debug purposes, if
needed. If register 0x01 is not read, then the latched values in register x07, will keep on updating based on any system level event.
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39
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TMDS461PZTR
Package Package Pins
Type Drawing
TQFP
PZT
100
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
17.0
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
17.0
1.5
20.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TMDS461PZTR
TQFP
PZT
100
1000
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF012B – OCTOBER 1994 – REVISED DECEMBER 1996
PZT (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
0,13 NOM
25
1
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
1,20 MAX
0,08
4073179 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
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