AOZ1110 4A Synchronous EZBuck Regulator General Description

AOZ1110 4A Synchronous EZBuck Regulator  General Description
AOZ1110
4A Synchronous EZBuck Regulator
Not Recommended For New Designs
General Description
Features
The AOZ1110QI is a high efficiency, easy to use, 4A
synchronous buck regulator optimized for portable
electronic devices. The AOZ1110QI works from a 2.7V to
5.5V input voltage range, and provides up to 4A of
continuous output current with an output voltage
adjustable down to 0.8V. With a 1% output accuracy
rating, the AOZ1110 is designed for low tolerance
applications, such as DSPs and FPGAs.
z 2.7V to 5.5V input voltage range
The AOZ1110QI is available in a 24-pin 4X4 QFN
package and is rated over a -40°C to +85°C ambient
temperature range.
z Cycle-by-cycle current limit
z 30mΩ high-side and 20mΩ low-side MOSFET
ns
z Efficiency up to 95%
z Adjustable soft start
ig
z Output voltage adjustable down to 0.8V
es
z 4A continuous output current
D
z Selectable 500kHz & 1MHz PWM operation
z Over-voltage protection
ew
z Short-circuit protection
z Thermal shutdown
N
z Power good indicator
Fo
r
z Small size 4x4 QFN-24 package
Applications
z Point of load DC/DC conversion for DSPs, FPGAs,
d
ASICs and microprocessors
de
z DVD and HDD
z Notebook PCs
om
m
en
z Telecom/Networking/Datacom equipment
Typical Application
5V
ec
VIN
R
C1
22µF
Ceramic
MCU
ot
R3
VDD
VIN
PGOOD
N
EN
L1 1.0uH
FSEL
AOZ1110QI
COMP
RC
R1
FB
SS
AGND
CC
VOUT
LX
PGND
Css = NC
R2
C2, C3
22µF
Ceramic
Figure 1. Typical Application
Rev. 1.0 October 2010
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Page 1 of 16
AOZ1110
Ordering Information
Part Number
Ambient Temperature Range
Package
Environmental
AOZ1110QI
-40°C to +85°C
24-pin 4mm x 4mm QFN
Green Product
AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.
Please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information.
19
ns
LX
20
ig
LX
21
3
16
LX
PG
4
15
LX
NC
5
14
LX
NC
6
13
LX
9
10
11
12
VIN
8
Fo
r
7
VIN
LX
EN
VIN
LX
17
VDD
18
2
AGND
1
FB
FSEL
COMP
es
PGND
22
D
PGND
23
ew
AGND
24
N
SS
Pin Configuration
24-Pin 4mm x 4mm QFN
(Top View)
d
Pin Description
Pin Name
1
COMP
2
FB
The FB pin is used to determine the output voltage via a resistor divider between the
output and GND.
3
EN
Device enable pin, active high.
4
PGOOD
de
Pin Number
Pin Function
om
m
en
External loop compensation pin.
Power good signal output pin. It is an open drain logic output used to indicate the status of
output voltages. Connect a pull up resistor to VIN.
NC
7
FSEL
Frequency Selection Pin. Tie this pin to ground, to set the switching frequency to 500kHz;
tie this pin to VDD, to set the switching frequency to 1MHz.
AGND
Reference connection for controller circuit. All AGND pins are connected internally.
Electrically needs to be connected to PGND. Also used as thermal connection for
controller circuit.
R
No connect.
VDD
Supply voltage to control circuit and gate drivers. Connect a 10Ω resistor between VIN
and VDD and a 0.1μF capacitor from VDD to AGND to decouple noise voltage.
10, 11, 12
VIN
Supply voltage input. All VIN pins must be connected together externally. When VIN
voltage rises above the UVLO threshold the device starts up.
13, 14, 15, 16, 17,
18, 19, 20
LX
PWM output connection to inductor. All LX pins must be connected together externally.
Also used as thermal connection for internal MOSFET.
21, 22
PGND
24
SS
N
9
ot
8, 23
ec
5,6
Rev. 1.0 October 2010
Power ground. All PGND pins must be connected together. Electrically needs to be
connected to AGND.
Soft start pin. Connect a capacitor externally to control soft start period. Leave it open for
internal set soft-start time.
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Page 2 of 16
AOZ1110
Functional Block Diagram
VDD
UVLO
& POR
EN
VIN
OTP
+
ISen
–
Reference
& Bias
Softstart
ns
Q1
ILimit
ig
SS
EAmp
FB
–
–
PWM
Control
Logic
PWM
Comp
+
Level
Shifter
+
FET
Driver
PGood Logic
N
500kHz / 1 MHz
Oscillator
Fo
r
PGOOD
PGND
Absolute Maximum Ratings
en
de
AGND
d
FESL
Recommended Operating Conditions
om
m
Exceeding the Absolute Maximum ratings may damage the
device.
Supply Voltage (VIN)
Supply Voltage (VDD)
FB to GND
R
ot
EN to GND
The device is not guaranteed to operate beyond the Maximum
Recommended Operating Conditions.
Rating
ec
Parameter
LX to GND
Parameter
6V
Supply Voltage (VIN)
6V
Output Voltage Range
-0.7V to 6V
Ambient Temperature (TA)
-0.3V to 6V
Package Thermal Resistance (2)
4x4 QFN-24 (ΘJA)
-0.3V to 6V
-0.3V to 6V
SS to GND
-0.3V to 6V
N
COMP to GND
Junction Temperature (TJ)
+150°C
Storage Temperature (TS)
-65°C to +150°C
ESD Rating
LX
Q2
ew
COMP
D
+
es
+
0.8V
(1)
2kV
PGOOD
-0.3V to 6V
FSEL
-0.3V to 6V
NC
-0.3V to 6V
Rev. 1.0 October 2010
Rating
2.7V to 5.5V
0.8V to VIN
-40°C to +85°C
45°C/W
Note:
1. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5kΩ in series with 100pF.
2. The value of ΘJA is measured with the device mounted on 1-in2
FR-4 board with 2oz. Copper, in a still air environment with TA = 25°C.
The value in any given application depends on the user's specific board
design.
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Page 3 of 16
AOZ1110
Electrical Characteristics
TA = 25°C, VIN = VEN = 3.3V, unless otherwise specified(3)
Condition
Min.
Supply Current (Quiescent)
VFB = 1.0V, L disconnected
IOFF
Shutdown Supply Current
VEN = 0V,
Active PGood = 100kΩ
Excluding PG current
VFB
Feedback Voltage
TA = 25°C
TA = -40°C to 85°C
Load Regulation
0A < Iload < 3A,
VIN = 3.3V, VOUT =1 .5V
Line Regulation
2.7V < VIN < 5.5V,
VOUT = 1.5V Iload = 100mA
IFB
2.20
FB Input Current
Off threshold
On threshold
EN Input Hysteresis
OSCILLATOR
1.5
3
mA
1
μA
Cycle(4)
Minimum Controllable on
time(4)
ERROR AMPLIFIER
0.800
0.800
0.808
0.816
V
0.2
%
0.2
%
200
nA
0.4
V
V
200
mV
0.85
1.0
1.15
MHz
FSEL = GND
425
500
575
kHz
de
tON_MIN
Maximum Duty
V
V
1.2
100
%
200
en
DMAX
2.60
FSEL = VDD
d
Frequency
fO
2.50
2.30
N
EN Input Threshold
Fo
r
VHYS
V
D
0.792
0.784
ENABLE
VEN
5.5
ns
VIN rising
VIN falling
IIN
Units
2.7
Input Under-Voltage Lockout
Threshold
VUVLO
Max.
ig
Supply Voltage
Typ.
ew
VIN
Parameter
es
Symbol
ns
Error Amplifier Open Loop Voltage
gain(4)
60
dB
GEA
Error Amplifier
Transconductance(4)
200
μA / V
om
m
GVEA
ILIM
ec
OVER CURRENT, OVER VOLTAGE AND OVER TEMPERATURE
Current Limit
VIN = 3.3V
5
(4)
Short Circuit Latch off Time
VFB = 0V
ot
OVP
R
Current Limit Response Time
TLO
Over Voltage Protection
N
OVP Hyteresis
Over-Temperature shutdown limit
TJ rising
TJ falling
6
7
A
200
ns
2
ms
115
%
3
%
150
100
°C
°C
OSCILLATOR
ISS_OUT
ISS_IN
tSS
Soft Start Pin Source Current
SS = 0V,
CSS = 0.001μF to 0.1μF
1.5
2.0
3.0
μA
Soft Start Pin Sink Current
VIN = 2.7V,
CSS = 0.001μF to 0.1μF
1.5
3.0
5.0
mA
Internal Soft Time
CSS = open
Rev. 1.0 October 2010
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500
μs
Page 4 of 16
AOZ1110
Electrical Characteristics (Continued)
TA = 25°C, VIN = VEN = 3.3V, unless otherwise specified(3)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
33
64
mΩ
PWM OUTPUT STAGE
RDS(ON)
High-Side PFET On-Resistance
VIN = 5V
High-Side PFET Leakage
VEN = 0V, VLX = 0V
Low-Side NFET On-Resistance
VLX = 5V
Low-Side NFET Leakage
VEN = 0V
19
PG Upper Threshold Voltage
Fraction of set point
110
PG Lower Threshold Voltage
Fraction of set point
80
PG Hysteresis Voltage
PG Falling Edge Deglitch Time
ew
tPG
mΩ
10
μA
V
μA
115
120
%
85
90
%
0.3
ig
V = 5.5V
es
I(sink) = 1.0mA
PG Leakage Current
D
PG LOW Voltage
μA
30
±1
POWER GOOD
VOLPG
10
ns
RDS(ON)
Notes:
3
%
120
μs
N
3. Specification in BOLD indicate an ambient temperature range of -40°C to +85°C. These specifications are guaranteed by design.
N
ot
R
ec
om
m
en
de
d
Fo
r
4. Guaranteed by design.
Rev. 1.0 October 2010
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Page 5 of 16
AOZ1110
Typical Performance Characteristics
Circuit of Figure 1 with internal soft-start. TA = 25°C, VIN = VEN = 3.3V, VOUT = 1.2V unless otherwise specified.
Switching Waveforms at Light Load
Switching Waveforms at Heavy Load
Vo ripple
10mV/div
Vo ripple
10mV/div
Vin ripple
0.1V/div
Vin ripple
0.1V/div
VLX
5V/div
es
ig
ns
VLX
5V/div
IL
1A/div
D
IL
1A/div
400ns/div
ew
400ns/div
Short-Circuit Protection Waveforms
N
Start Up Waveforms
Pgood
2V/div
d
Pgood
2V/div
LX
5V/div
Fo
r
Enable
5V/div
Vo
1V/div
IIN
2A/div
IL
5A/div
om
m
en
de
Vo
0.5V/div
1ms/div
Load Transient Waveforms
Short-Circuit Recovery Waveforms
R
ec
200us/div
LX
5V/div
Vo
50mV/div
N
ot
Pgood
2V/div
Vo
1V/div
Io
2A/div
IL
5A/div
1ms/div
Rev. 1.0 October 2010
1ms/div
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Page 6 of 16
AOZ1110
Efficiency
Efficiency (fSW = 1MHz, VIN = 5V) vs. Load Current
Efficiency (fSW = 1MHz, VIN = 3.3V) vs. Load Current
100
100
OUTPUT:
OUTPUT:
95
95
1.8V
85
1.2V
1.8V
85
80
75
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0.5
1.0
1.2V
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Load Current (A)
Efficiency (fSW = 500kHz, VIN = 5V) vs. Load Current
Efficiency (fSW = 500kHz, VIN = 3.3V) vs. Load Current
100
Fo
r
100
OUTPUT:
OUTPUT:
95
d
3.3V
90
de
1.8V
85
75
0
0.5
1.0
1.5
om
m
en
1.2V
80
2.0
2.5
3.0
3.5
Efficieny (%)
95
Efficieny (%)
N
ew
Load Current (A)
D
75
es
80
90
ns
90
ig
Efficieny (%)
Efficieny (%)
3.3V
90
1.8V
85
1.2V
80
75
4.0
4.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Load Current (A)
N
ot
R
ec
Load Current (A)
Rev. 1.0 October 2010
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Page 7 of 16
AOZ1110
Power Good
ns
ig
es
Switching Frequency
The AOZ1110QI switching frequency can be selected by
FSEL pin. When the FSEL logic is tied to VDD, the
switching frequency will be 1.0 MHz. When the FSEL
logic is tied to GND, the switching frequency will be
0.5 MHz.
Output Voltage Programming
Output voltage can be set by feeding back the output to
the FB pin by using a resistor divider network. In the
application circuit shown in Figure 1. The resistor divider
network includes R1 and R2. Usually, a design is started
by picking a fixed R2 value and calculating the required
R1 with equation below.
om
m
en
de
d
The output of power good is an open drain N-MOSFET,
which supplies an active high power good stage. A pullup resistor (R3) should connect this pin to a DC power
trail with maximum voltage no higher than 6V. The
AOZ1110QI monitors the FB voltage: when the FB pin
voltage is lower than 85% of the target voltage or higher
than 115% of the target voltage, N-MOSFET turns on and
the power good pin is pulled low, which indicates the
power is abnormal.
The AOZ1110QI uses a P-MOSFET as the high-side
switch. It saves the bootstrap capacitor normally seen in
a circuit which is using an N-MOSFET switch.
D
The AOZ1110QI has both internal and external soft start
feature to limit in-rush current and ensure the output
voltage ramps up smoothly to regulation voltage. A soft
start process begins when the input voltage rises to 2.5V
and voltage on EN pin is HIGH. In the soft start, a 2μA
internal current source charges the external capacitor at
SS. As the SS capacitor is charged, the voltage at SS
rises. The SS voltage clamps the reference voltage of the
error amplifier, therefore output voltage rising time follows
the SS pin voltage. With the slow ramping up output
voltage, the inrush current can be prevented. If there is no
external capacitor connected to the SS pin, the internal
soft start will operate at 500μs.
ew
Enable and Soft Start
Comparing with regulators using freewheeling Schottky
diodes, the AOZ1110QI uses freewheeling N-MOSFET to
realize synchronous rectification. It greatly improves the
converter efficiency and reduces power loss in the
low-side switch.
N
The AOZ1110QI is a current-mode synchronous step
down regulator with complimentary MOSFET switches.
The operating input voltage range is 2.7V to 5.5V. The
output range can be adjusted to a minimum of 0.8V and
supplies up to 4A of continuous current. Features include
cycle-by-cycle current limiting, short circuit protection,
adjustable soft start and a power good output signal.
voltage, the high-side switch is off. The inductor current is
freewheeling through the internal low-side N-MOSFET
switch to output. The internal adaptive FET driver
guarantees no turn on overlap of both high-side and
low-side switch.
Fo
r
Detailed Description
R 1⎞
⎛
V O = 0.8 × ⎜ 1 + -------⎟
R 2⎠
⎝
Some standard value of R1, R2 and most used output
voltage values are listed in Table 1.
Steady-State Operation
Table 1.
R
ec
Under steady-state conditions, the converter operates in
fixed frequency and Continuous-Conduction Mode
(CCM).
N
ot
The AOZ1110QI integrates an internal P-MOSFET as the
high-side switch. Inductor current is sensed by amplifying
the voltage drop across the drain to source of the high
side power MOSFET. Output voltage is divided down by
the external voltage divider at the FB pin. The difference
of the FB pin voltage and reference is amplified by the
internal transconductance error amplifier. The error
voltage, which shows on the COMP pin, is compared
against the current signal, which is sum of inductor
current signal and ramp compensation signal, at PWM
comparator input. If the current signal is less than the
error voltage, the internal high-side switch is on. The
inductor current flows from the input through the inductor
to the output. When the current signal exceeds the error
Rev. 1.0 October 2010
Vo (V)
R1 (kΩ)
Rs (kΩ)
0.8
1.0
open
1.2
4.99
10
1.5
10
11.5
1.8
12.7
10.2
2.5
21.5
10
3.3
31.1
10
5.0
52.3
10
The combination of R1 and R2 should be large enough to
avoid drawing excessive current from the output, which
will cause power loss.
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Page 8 of 16
AOZ1110
Since the switch duty cycle can be as high as 100%, the
maximum output voltage can be set as high as the input
voltage minus the voltage drop on upper P-MOSFET and
inductor.
The input ripple voltage can be approximated by
equation below:
IO
VO ⎞ VO
⎛
ΔV IN = ----------------- × ⎜ 1 – ---------⎟ × --------V IN⎠ V IN
f × C IN ⎝
Protection Features
es
ig
VO ⎛
VO ⎞
I CIN_RMS = I O × --------- ⎜ 1 – ---------⎟
V IN ⎝
V IN⎠
if we let m equal the conversion ratio:
VO
-------- = m
V IN
Power-On Reset (POR)
Output Over Voltage Protection (OVP)
en
de
N
d
The AOZ1110QI monitors the feedback voltage: when
the feedback voltage is higher than 15% of set value, it
immediately turns off P-MOSFET cycle by cycle to
protect the output voltage overshoot at fault condition.
The relation between the input capacitor RMS current
and voltage conversion ratio is calculated and shown in
Figure 2. It can be seen that when VO is half of VIN,
CIN is under the worst current stress. The worst current
stress on CIN is 0.5 x IO.
Fo
r
A power-on reset circuit monitors the input voltage. When
the input voltage exceeds 2.5V, the converter starts
operation. When input voltage falls below 2.3V, the
converter will be shut down.
Thermal Protection
ICIN_RMS(m) 0.3
IO
0.2
0.1
ec
0
R
ot
The basic AOZ1110QI application circuit is show in
Figure 1. Component selection is explained below.
Input Capacitor
N
0
0.5
m
1
Figure 2. ICIN vs. Voltage Conversion Ratio
Application Information
The input capacitor must be connected to the VIN pin and
PGND pin of AOZ1110QI to maintain steady input voltage
and filter out the pulsing input current. The voltage rating
of input capacitor must be greater than maximum input
voltage plus ripple voltage.
Rev. 1.0 October 2010
0.5
0.4
om
m
An internal temperature sensor monitors the junction
temperature. It shuts down both high side P-MOSFET
and low side N-MOSFET if the junction temperature
exceeds 150ºC. The regulator will restart automatically
under the control of soft start circuit when the junction
temperature decreases to 100ºC.
D
The sensed inductor current signal is also used for over
current protection. Since the AOZ1110QI employs peak
current mode control, the COMP pin voltage is
proportional to the peak inductor current. The COMP pin
voltage is limited to be between 0V and 2.2V internally.
The peak inductor current is automatically limited cycle
by cycle.
ew
Over Current Protection (OCP)
ns
Since the input current is discontinuous in a buck
converter, the current stress on the input capacitor is
another concern when selecting the capacitor. For a buck
circuit, the RMS value of input capacitor current can be
calculated by:
The AOZ1110QI has multiple protection features to
prevent system circuit damage under abnormal
conditions.
For reliable operation and best performance, the input
capacitors must have current rating higher than ICIN_RMS
at worst operating conditions. Ceramic capacitors are
preferred for input capacitors because of their low ESR
and high current rating. Depending on the application
circuits, other low ESR tantalum capacitor may also be
used. When selecting ceramic capacitors, X5R or X7R
type dielectric ceramic capacitors should be used for
their better temperature and voltage characteristics.
Note that the ripple current rating from capacitor
manufactures are based on certain amount of life time.
Further de-rating may be necessary in practical design.
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Page 9 of 16
AOZ1110
Inductor
where;
The inductor is used to supply constant current to output
when it is driven by a switching voltage. For given input
and output voltage, inductance and switching frequency
together decide the inductor ripple current, which is:
CO is output capacitor value,
and ESRCO is the Equivalent Series Resistor of output
capacitor.
The peak inductor current is:
1
ΔV O = ΔI L × ⎛ -------------------------⎞
⎝8 × f × C ⎠
ΔI L
I Lpeak = I O + -------2
ig
O
ns
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the switching
frequency dominates. Output ripple is mainly caused by
capacitor value and inductor ripple current. The output
ripple voltage calculation can be simplified to:
VO ⎞
VO ⎛
ΔI L = ----------- × ⎜ 1 – ---------⎟
V IN⎠
f×L ⎝
es
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided by
capacitor ESR and inductor ripple current. The output
ripple voltage calculation can be further simplified to:
D
High inductance gives low inductor ripple current but
requires larger size inductor to avoid saturation. Low
ripple current reduces inductor core losses. It also
reduces RMS current through inductor and switches,
which results in less conduction loss. Usually, peak to
peak ripple current on inductor is designed to be
20% to 30% of output current.
ew
ΔV O = ΔI L × ESR CO
N
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It can
be calculated by:
de
d
The inductor takes the highest current in a buck circuit.
The conduction loss on inductor need to be checked for
thermal and efficiency requirements.
Fo
r
When selecting the inductor, make sure it is able to
handle the peak current without saturation even at the
highest operating temperature.
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum are recommended
to be used as output capacitors.
om
m
en
Surface mount inductors in different shape and styles are
available from Coilcraft, Elytone and Murata. Shielded
inductors are small and radiate less EMI noise. But they
cost more than unshielded inductors. The choice
depends on EMI requirement, price and size.
Output Capacitor
R
ec
The output capacitor is selected based on the DC output
voltage rating, output ripple voltage specification and
ripple current rating.
N
ot
The selected output capacitor must have a higher rated
voltage specification than the maximum desired output
voltage including ripple. De-rating needs to be
considered for long term reliability.
Output ripple voltage specification is another important
factor for selecting the output capacitor. In a buck
converter circuit, output ripple voltage is determined by
inductor value, switching frequency, output capacitor
value and ESR. It can be calculated by the equation
below:
1
ΔV O = ΔI L × ⎛ ESR CO + -------------------------⎞
⎝
8×f×C ⎠
ΔI L
I CO_RMS = ---------12
Usually, the ripple current rating of the output capacitor is
a smaller issue because of the low current stress. When
the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
Loop Compensation
The AOZ1110QI employs peak current mode control for
easy use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole can be
calculated by:
1
f p1 = ----------------------------------2π × C O × R L
O
Rev. 1.0 October 2010
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Page 10 of 16
AOZ1110
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
1
f Z1 = -----------------------------------------------2π × C O × ESR CO
designing the compensation loop, converter stability
under all line and load condition must be considered.
Usually, it is recommended to set the bandwidth to be
equal or less than 1/10 of switching frequency. The
strategy for choosing Rc and Cc is to set the cross over
frequency with Rc and set the compensator zero with CC.
Using selected crossover frequency, fC, to calculate RC:
CO is the output filter capacitor,
2π × C O
VO
R C = f C × ---------- × -----------------------------V
G ×G
RL is load resistor value,
ESRCO is the equivalent series resistance of output capacitor.
FB
ig
es
VFB is 0.8V,
D
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V;
GCS is the current sense circuit transconductance, which is
10 A/V.
The compensation capacitor CC and resistor RC together
make a zero. This zero is put somewhere close to the
dominate pole fp1 but lower than 1/5 of selected crossover frequency. CC can is selected by:
de
GEA is the error amplifier transconductance, which is
200 x 10-6 A/V,
d
where;
en
GVEA is the error amplifier voltage gain, which is 500 V/V,
om
m
and, CC is the compensation capacitor in Figure1.
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
1.5
C C = ----------------------------------2π × R C × f p1
The equation above can also be simplified to:
CO × RL
C C = --------------------RC
An easy-to-use application software which helps to
design and simulate the compensation loop can be found
at www.aosmd.com.
ec
1
f Z2 = ----------------------------------2π × C C × R C
fC is desired crossover frequency. For best performance, fC is
set to be about 1/10 of switching frequency,
Fo
r
G EA
f p2 = ------------------------------------------2π × C C × G VEA
where;
CS
ew
In the AOZ1110QI, FB pin and COMP pin are the
inverting input and the output of internal error amplifier. A
series R and C compensation network connected to
COMP provides one pole and one zero. The pole is:
EA
N
The compensation design is actually to shape the
converter control loop transfer function to get desired
gain and phase. Several different types of compensation
network can be used for the AOZ1110QI. For most
cases, a series capacitor and resistor network connected
to the COMP pin sets the pole-zero and is adequate for a
stable high-bandwidth control loop.
ns
where;
N
ot
R
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The system
crossover frequency is where control loop has unity gain.
The crossover is the also called the converter bandwidth.
Generally a higher bandwidth means faster response to
load transient. However, the bandwidth should not be too
high because of system stability concern. When
Rev. 1.0 October 2010
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Page 11 of 16
AOZ1110
Thermal Management and Layout
Consideration
Several layout tips are listed below for the best electric
and thermal performance.
In the AOZ1110QI buck regulator circuit, high pulsing
current flows through two circuit loops. The first loop
starts from the input capacitors, to the VIN pin, to the LX
pins, to the filter inductor, to the output capacitor and
load, and then return to the input capacitor through
ground. Current flows in the first loop when the high side
switch is on. The second loop starts from inductor, to the
output capacitors and load, to the low-side N-MOSFET.
Current flows in the second loop when the low side NMOSFET is on.
1. The LX pins are connected to internal P-MOSFET
and N-MOSFET drains. They are low resistance
thermal conduction path and most noisy switching
node. Connect a large copper plane to LX pin to help
thermal dissipation. For full load (4A) application,
also connect the LX pads to the bottom layer by
thermal vias to enhance the thermal dissipation.
P total_loss = V IN × I IN – V O × I O
ns
ig
es
D
ew
5. Make the current trace from LX pins to L to Co to the
PGND as short as possible.
6. Pour copper plane on all unused board area and
connect it to stable DC nodes, like VIN, GND or
VOUT.
7. Keep sensitive signal trace far away form the LX
pins.
de
d
The power dissipation of inductor can be approximately
calculated by output current and DCR of inductor:
4. A ground plane is preferred. If a ground plane is not
used, separate PGND from AGND and connect them
only at one point to avoid the PGND pin noise
coupling to the AGND pin.
N
In the AOZ1110QI buck regulator circuit, the major power
dissipating components are the AOZ1110QI and the
output inductor. The total power dissipation of converter
circuit can be measured by input power minus output
power:
3. Input capacitor should be connected to the VIN pin
and the PGND pin as close as possible.
Fo
r
In PCB layout, minimizing the two loops area reduces the
noise of this circuit and improves efficiency. A ground
plane is strongly recommended to connect input
capacitor, output capacitor, and PGND pin of the
AOZ1110QI.
2. Do not use thermal relief connection to the VIN and
the PGND pin. Pour a maximized copper area to the
PGND pin and the VIN pin to help thermal
dissipation.
en
P inductor_loss = IO2 × R inductor × 1.1
om
m
The actual junction temperature can be calculated with
power dissipation in the AOZ1012D and thermal
impedance from junction to ambient:
ec
T junction = ( P total_loss – P inductor_loss ) × Θ JA
R
The maximum junction temperature of AOZ1110QI is
150ºC, which limits the maximum load current capability.
N
ot
The thermal performance of the AOZ1110QI is strongly
affected by the PCB layout. Extra care should be taken
by users during design process to ensure that the IC will
operate under the recommended environmental
conditions.
Rev. 1.0 October 2010
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Page 12 of 16
AOZ1110
Package Dimensions, QFN 4x4-24L
D
A
D/2
18
B
13
19
2
12
INDEX AREA
E/2
e
ns
(D/2xE/2)
24
es
2x
aaa C
ig
E
1
D
7
6
A3
ew
2x
aaa C
N
TOP VIEW
A3
Fo
r
ccc C
A
C
SEATING
PLANE
d
A1
4
3
24 x b
de
ddd C
bbb M C A B
om
m
en
SIDE VIEW
PIN#1 DIA
R0.30
e
e/2
6
ec
1
D1
D1/2
E1
7
e/2
L3
ot
R
24
N
L2
E2
19
12
L
18
13
L
D1/2
D1
L1 (4x)
BOTTOM VIEW
Rev. 1.0 October 2010
www.aosmd.com
Page 13 of 16
AOZ1110
Package Dimensions, QFN 4x4-24L (Continued)
RECOMMENDED LAND PATTERN
2.60
0.30
0.30
1.30
0.25
0.50
0.95
ns
0.30
1.85
ig
0.05
es
0.35
2.60
1.85
ew
0.30
D
1.30
1.25
0.25
1.85
N
0.50 Ref (20x)
0.25 x 45˚
Fo
r
1.85
Dimensions in millimeters
UNIT: MM
Dimensions in inches
Min.
Typ.
Max.
Symbols
Min.
Typ.
Max.
A
A1
A3
b
D
D1
E
E1
E2
e
L
L1
L2
L3
aaa
bbb
ccc
ddd
0.70
0.00
0.75
0.02
0.20 REF
0.25
4.00 BSC
2.60
4.00 BSC
1.25
0.95
0.50 BSC
0.40
0.30
0.35
0.05
0.15
0.10
0.10
0.08
0.80
0.05
A
A1
A3
b
D
D1
E
E1
E2
e
L
L1
L2
L3
aaa
bbb
ccc
ddd
0.028
0.000
0.030
0.001
0.008 REF.
0.010
0.157 BSC
0.102
0.157 BSC
0.049
0.037
0.020 BSC
0.016
0.012
0.014
0.002
0.006
0.004
0.004
0.003
0.031
0.002
om
m
2.50
ec
1.15
0.85
N
ot
R
0.35
0.20
0.25
---
Rev. 1.0 October 2010
de
en
0.20
d
Symbols
0.30
2.70
1.35
1.05
0.45
0.40
0.45
0.15
www.aosmd.com
0.008
0.098
0.045
0.033
0.014
0.008
0.010
---
0.012
0.106
0.053
0.041
0.018
0.016
0.018
0.006
Page 14 of 16
AOZ1110
Tape and Reel Dimensions, QFN 4x4-24L
Carrier Tape
P1
D1
P2
T
E1
E2
E
C
L
ig
ns
B0
K0
D0
A0
Feeding Direction
es
P0
D
UNIT: MM
A0
B0
K0
D0
D1
E
E1
E2
P0
P1
P2
T
4.35
±0.10
4.35
±0.10
1.10
±0.10
1.50
Min.
1.50
+0.1/-0.0
12.0
±0.3
1.75
±0.10
5.50
±0.05
8.00
±0.10
4.00
±0.10
2.00
±0.05
0.30
±0.05
Fo
r
W1
d
G
de
K
en
V
S
N
M
om
m
R
UNIT: MM
N
Reel
ew
Package
QFN 4x4
(12 mm)
H
W
Reel Size
M
N
W
W1
H
K
S
G
R
V
12 mm
ø330
ø330.0
ø79.0
10.5
±0.2
2.0
±0.5
—
—
—
±1.0
17.0
+2.6/-1.2
ø13.0
±2.0
12.4
+2.0/-0.0
±0.5
R
ec
Tape Size
N
ot
Leader/Trailer and Orientation
Trailer Tape
300mm min. or
75 empty pockets
Rev. 1.0 October 2010
Components Tape
Orientation in Pocket
www.aosmd.com
Leader Tape
500mm min. or
125 empty pockets
Page 15 of 16
AOZ1110
Part Marking
AOZ1110Q1
(QFN 4 x 4)
Z1110QI
Part Number Code
es
ig
ns
FAYWLT
Assembly Lot Code
D
Fab & Assembly Location
ec
om
m
en
de
d
Fo
r
N
ew
Year & Week Code
R
This datasheet contains preliminary data; supplementary data may be published at a later date.
Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.
ot
LIFE SUPPORT POLICY
N
ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body or (b) support or sustain life, and (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of
the user.
Rev. 1.0 October 2010
2. A critical component in any component of a life
support, device, or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
www.aosmd.com
Page 16 of 16
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