FRS00660410
Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33882/D
Rev 3.0, 12/2003
SEMICONDUCTOR TECHNICAL DATA
Advance Information
33882
Six-Output Low-Side Switch with
SPI and Parallel Input Control
Freescale Semiconductor, Inc...
The 33882 is a smart six-output low-side switch able to control system loads
up to 1.0 A. The six outputs can be controlled via both serial peripheral
interface (SPI) and parallel input control, making the device attractive for faulttolerant system applications. There are two additional 30 mA low-side
switches with SPI diagnostic reporting (with parallel input control only).
SIX-OUTPUT LOW-SIDE SWITCH
The 33882 is designed to interface directly with industry-standard
microcontrollers via SPI to control both inductive and incandescent loads.
Outputs are configured as open-drain power MOSFETs incorporating internal
dynamic clamping and current limiting. The device has multiple monitoring and
protection features, including low standby current, fault status reporting,
internal 52 V clamp on each output, output-specific diagnostics, and protective
shutdown. In addition, it has a mode select terminal affording a dual means of
input control.
Features
• Outputs Clamped for Switching Inductive Loads
• Very Low Operational Bias Currents (< 2.0 mA)
• CMOS Input Logic Compatible with 5.0 V Logic Levels
• Load Dump Robust (60 V Transient at VPWR on OUT0–OUT5)
• Daisy Chain Operation of Multiple Devices Possible
• Switch Outputs Can Be Paralleled for Higher Currents
• RDS(ON) of 0.4 Ω per Output (25°C) at 13 V VPWR
• SPI Operation Guaranteed to 2.0 MHz
DH SUFFIX
CASE 979A-09
30-TERMINAL HSOP
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC33882DH/R2
-40°C to 125°C
30 HSOP
MC33882FC/R2
-40°C to 125°C
32 QFN
33882
Simplified
Application
Diagram
Simplified
Application
Diagram
VDD
VPWR
33882
MCU
Optional Parallel
Control of
Outputs 0 through 7
VPWR
OUT0
VDD
OUT1
CS
OUT2
SCLK
OUT3
SI
OUT4
SO
IN0
OUT5
OUT7
IN2
IN0 & IN1
IN3
IN2 & IN3
IN4
IN4 & IN5
IN5
IN6
High-Power
Outputs
Low-Power
LED
Outputs
OUT6
IN1
Optional Control
of Paired Outputs
MODE
GND
IN7
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2003
FC SUFFIX
CASE 1306-01
32-TERMINAL QFN
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33882
2
DQ
C
0
1
DQ
C
2
DQ
C
3
DQ
C
4
5
6
DQ
C
7
On Open
Detect
Logic
DQ
C
Shift
Enable
Note Terminal numbers shown in this figure are applicable only to the 30-lead HSOP package.
Tri-state
I LIM
OFF/ON
Open
Load
Detect
- +
15 (SO)
14 (CS)
Serial Out
V REF
- +
13 (SCLK)
SO Fault Latch/Shift Register
V OF (th)
3.0 V
I O(OFF)
40 mA
OUT1
to OUT5
High
Power
52 V
+ -
3.0 A
Load
Short
Detect
Gate 0
Gate 0
Gate 2
Gate 3
Gate 4
Gate 5
Gate 6
Internal
Bias
16 (VDD)
OUT6
and OUT7
Unclamped
Low
Power
Undervoltage
Shutdown
Gate 7
Overvoltage
Shutdown
Output Status
1 through 7
Serial In
DQ
C
2 (IN0 & IN1)
DQ
C
Output 0 Status
V DD
V DD
4 (IN0)
6 (IN1)
19 (IN2 & IN3)
9 (IN2)
21 (IN3)
28 (IN4 & IN5)
24 (IN4)
27 (IN5)
29 (IN6)
18 (IN7)
3 (MODE)
12 (SI)
1 (VPWR)
Freescale Semiconductor, Inc...
GND (Heat Sink)
5 (OUT0)
7 (OUT1)
10 (OUT2)
20 (OUT3)
23 (OUT4)
26 (OUT5)
30 (OUT6)
17 (OUT7)
Freescale Semiconductor, Inc.
Figure 1. 33882 Simplified Internal Block Diagram
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VPWR
IN0 & IN1
MODE
OUT6
IN6
IN4 & IN5
IN5
OUT5
NC
IN4
OUT4
NC
IN3
OUT3
IN2 & IN3
IN7
OUT7
VDD
HEAT
SINK
GND
Freescale Semiconductor, Inc...
IN0
OUT0
IN1
OUT1
NC
IN2
OUT2
NC
SI
SCLK
CS
SO
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
HSOP TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal
Name
Formal Name
Definition
1
VPWR
Load Supply Voltage
This terminal is connected to battery voltage. A decoupling cap is required from VPWR
to ground.
2
19
28
IN0 & IN1
IN2 & IN3
IN4 & IN5
Input 0 & Input 1
Input 2 & Input 3
Input 4 & Input 5
These input terminals control two output channels each when the MODE terminal is
pulled high. These terminals may be connected to pulse width modulated (PWM)
outputs of the control IC while the MODE terminal is high. The states of these terminals
are ignored during normal operation (MODE terminal low) and override the normal
inputs (serial or parallel) when the MODE terminal is high. These terminals have
internal active 25 µA pull-downs.
3
MODE
Mode Select
The MODE terminal is connected to the MODE terminal of the control IC. This terminal
has an internal active 25 µA pull-up.
4
6
9
18
21
24
27
29
IN0
IN1
IN2
IN7
IN3
IN4
IN5
IN6
Input 0–Input7
These are parallel control input terminals. These terminals have internal 25 µA active
pull-downs.
5
7
10
17
20
23
26
30
OUT0
OUT1
OUT2
OUT7
OUT3
OUT4
OUT5
OUT6
Output 0–Output7
8, 11, 22, 25
NC
No Connect
Not connected.
12
SI
Serial Input
The Serial Input terminal is connected to the SPI Serial Data Output terminal of the
control IC from where it receives output command data. This input has an internal
active 25 µA pull-down and requires CMOS logic levels.
13
SCLK
Serial Clock
The SCLK terminal of the control IC is a bit (shift) clock for the SPI port. It transitions
one time per bit transferred when in operation. It is idle between command transfers. It
is 50% duty cycle, and has CMOS levels.
14
CS
Chip Select
This terminal is connected to a chip select output of the control IC. This input has an
internal active 25 µA pull-up and requires CMOS logic levels.
Each terminal is one channel's drain, sinking current for the respective load.
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3
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HSOP TERMINAL FUNCTION DESCRIPTION (continued)
Terminal
Terminal
Name
Formal Name
Definition
15
SO
Serial Output
This terminal is connected to the SPI Serial Data Input terminal of the control IC or to
the SI terminal of the next device in a daisy chain. This output will remain tri-stated
unless the device is selected by a low CS terminal or the MODE terminal goes low. The
output signal generated will have CMOS logic levels and the output data will transition
on the falling edges of SCLK. The serial output data provides fault information for each
output and is returned MSB first when the device is addressed.
16
VDD
Logic Supply Voltage
Heat Sink
(exposed pad)
GND
Ground
This terminal is connected to the 5.0 V power supply of the system. A decoupling
capacitor is required from VDD to ground.
Freescale Semiconductor, Inc...
The exposed pad on this package provides the circuit ground connection for this IC.
Ground continuity is required for the outputs to turn on.
33882
4
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IN7
IN2 & IN3
25
OUT3
26
IN3
27
OUT4
28
IN4
29
30
7
18
8
17
VDD
GND
GND
GND
GND
SO
CS
SI
SCLK
IN2
OUT2
OUT7
16
19
15
6
14
20
13
5
12
21
9
MODE
4
IN0
Freescale Semiconductor, Inc...
IN0 & IN1
22
IN1
GND
VPWR
3
OUT1
GND
23
11
OUT6
24
2
10
IN6
1
OUT0
IN4 & IN5
31
32
IN5
Transparent Top View of Package
OUT5
Freescale Semiconductor, Inc.
QFN TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal
Name
Formal Name
Definition
7
26
1
IN0 & IN1
IN2 & IN3
IN4 & IN5
Input 0 & Input 1
Input 2 & Input 3
Input 4 & Input 5
These input terminals control two output channels each when the MODE terminal is
pulled high. These terminals may be connected to pulse width modulated (PWM)
outputs of the control IC while the MODE terminal is high. The states of these terminals
are ignored during normal operation (MODE terminal low) and override the normal
inputs (serial or parallel) when the MODE terminal is high. These terminals have internal
active 25 µA pull-downs.
2
9
11
13
25
28
30
32
IN6
IN0
IN1
IN2
IN7
IN3
IN4
IN5
Input 0–Input 7
These are parallel input terminals. These terminals have internal 25 µA active pulldowns.
3
10
12
14
24
27
29
31
OUT6
OUT0
OUT1
OUT2
OUT7
OUT3
OUT4
OUT5
Output 0–Output 7
4, 5, 19–22
GND
Ground
6
VPWR
Load Supply Voltage
This terminal is connected to battery voltage. A decoupling capacitor is required from
VPWR to ground.
8
MODE
Mode Select
The MODE terminal is connected to the MODE terminal of the control IC. This terminal
has an internal active 25 µA pull-up.
15
SI
Serial Input
The Serial Input terminal is connected to the SPI Serial Data Output terminal of the
control IC from where it receives output command data. This input has an internal
active 25 µA pull-down and requires CMOS logic levels.
Each terminal is one channel's drain, sinking current for the respective load.
Ground continuity is required for the outputs to turn on.
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5
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QFN TERMINAL FUNCTION DESCRIPTION (continued)
Terminal
Name
Formal Name
Definition
16
SCLK
Serial Clock
The SCLK terminal of the control IC is a bit (shift) clock for the SPI port. It transitions
one time per bit transferred when in operation. It is idle between command transfers. It
is 50% duty cycle, and has CMOS levels.
17
CS
Chip Select
This terminal is connected to a chip select output of the control IC.This input has an
internal active 25 µA pull-up and requires CMOS logic levels.
18
SO
Serial Output
23
VDD
Logic Supply Voltage
Freescale Semiconductor, Inc...
Terminal
33882
6
This terminal is connected to the SPI Serial Data Input terminal of the control IC or to
the SI terminal of the next device in a daisy chain. This output will remain tri-stated
unless the device is selected by a low CS terminal or the MODE terminal goes low. The
output signal generated will have CMOS logic levels and the output data will transition
on the falling edges of SCLK. The serial output data provides fault information for each
output and is returned MSB first when the device is addressed.
This terminal is connected to the 5.0 V power supply of the system. A decoupling
capacitor is required from VDD to ground.
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MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Limit
VPWR(SS)
25
VPWR(T)
-1.5 to 60
Logic Supply Voltage (Note 2)
VDD
-0.3 to 7.0
V
Input Terminal Voltage (Note 3)
VIN
-0.3 to VDD + 0.3
V
ELECTRICAL RATINGS
Load Supply Voltage
V
Normal Operation (Steady-State)
Transient Survival (Note 1)
Output Clamp Voltage (OUT0 to OUT5) (Note 4)
VO(OFF)
V
48 to 64
Freescale Semiconductor, Inc...
20 mA = IO = 0.2 A
IO(LIM)
Output Self-Limit Current
A
3.0 to 6.0
OUT0 to OUT5
OUT6 and OUT7
0.05 to 0.15
V
ESD Voltage (HSOP and QFN)
Human Body Model (Note 5)
VESD1
±2000
Machine Model (Note 6)
VESD2
±200
Output Clamp Energy (Note 7)
ECLAMP
mJ
OUT0 to OUT5: Single Pulse at 1.5 A, TJ = 150°C
100
OUT6 and OUT7: Single Pulse at 0.45 A, TJ = 150°C
50
fOF
3.2
MHz
TSTG
-55 to 150
°C
Operating Junction Temperature
TJ
-40 to 150
°C
Terminal Soldering Temperature
TSOLDER
Maximum Operating Frequency (SPI) SO (Note 8)
THERMAL RATINGS
Storage Temperature
°C
HSOP
220
QFN
240
Notes
1. Transient capability with external 100 Ω resistor in series with VPWR terminal and supply.
2.
3.
4.
5.
Exceeding these voltages may cause a malfunction or permanent damage to the device.
Exceeding the limits on any parallel inputs or SPI terminals may cause permanent damage to the device.
With output OFF.
ESD1 testing is performed in accordance with the Human Body Model (CZAP =100 pF, RZAP =1500 Ω).
6.
ESD2 testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP =0 Ω).
7.
8.
Maximum output clamp energy capability at indicated junction temperature using a single pulse method.
Serial Frequency Specifications assume the IC is driving 8 tri-stated devices (20 pF each).
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7
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MAXIMUM RATINGS (continued)
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Value
Limit
THERMAL RESISTANCE (Note 9), (Note 10)
Junction-to-Ambient, Natural Convection, Single-Layer Board (1s) (Note 11)
°C/W
41
QFN
85
Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p) (Note 12)
RθJMA
°C/W
HSOP
18
QFN
27
Junction-to-Board (Bottom)
Freescale Semiconductor, Inc...
RθJA
HSOP
°C/W
RθJB
HSOP
3.0
QFN
10
Junction-to-Case (Top) (Note 13)
°C/W
RθJC
HSOP
0.2
QFN
1.2
Notes
9.
10.
11.
12.
13.
33882
8
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface
of the board near the package.
Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
Per JEDEC JESD51-6 with the board horizontal.
Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC 883,
Method 1012.1) with the cold plate temperature used for the case temperature.
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STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
VDD
5.5
4.5
8.0
V PWR
8.0
–
25
Unit
POWER INPUT
Supply Voltage Ranges
V
Functional Threshold (Note 14)
Full Operation
VDD Supply Current (All Outputs ON) (Note 15)
I PWR(ON)
–
–
7.5
V PWR (OV)
30
–
40
V
Overvoltage Shutdown Hysteresis (Note 17)
V PWR (OV) HYS
0.4
–
1.5
V
Power-ON Reset Threshold, VDD (Note 18)
V POR
2.5
–
3.5
V
–
–
5.0
–
0.6
0.8
IO = 1.0 A Each
Overvoltage Shutdown (Note 16)
Freescale Semiconductor, Inc...
mA
Logic Supply Current (All Outputs ON)
mA
I DD
VDD = 5.5 V
POWER OUTPUT
Output Drain-to-Source ON Resistance
Ω
RDS(ON)
OUT0 to OUT5: TJ = 150°C, VPWR = 13.0 V, IO = 1.0 A
Output Drain-to-Source ON Resistance
Ω
RDS(ON)
OUT0 to OUT5: TJ = 25°C, VPWR = 13.0 V, IO = 1.0 A
Output Self-Limiting Current
–
0.4
0.6
3.0
–
6.0
2.5
–
3.5
A
I O(LIM)
VPWR = 13.0 V, VDD = 4.5 V, VIN = 5.0 V
Open Load OFF Detection (Outputs Programmed OFF)
Output OFF (Open Load Detect) Drain Current (Output Terminals
Programmed OFF) (Note 19)
V OFF(TH)
µA
I O(OFF)
OUT0 to OUT5
20
–
120
OUT6 and OUT7
20
–
80
20
–
200
48
52
64
Output ON (Open Load Detect) Drain Current (Output Terminals
Programmed ON) (Note 20)
Output Clamp Voltage
–
mA
V
V OK
OUT0 to OUT5: IO = 20 mA, tCLAMP = 100 µs
Output Leakage Current
µA
I OLK
–
1.0
10
ISD = 1.0 mA @ 25°C
–
–
1.4
ISD = 1.0 mA @ 125°C
–
–
0.9
VDD = VPWR = 0.5 V, VOUT = 24 V
V
V SD
Drain-to-Source Diode Forward Voltage
V
Notes
14. Outputs of device functionally turn-on (RDS(ON) = 0.95 Ω @125°C). SPI/parallel inputs and power outputs are operational. Fault detection
and reporting may not be fully operational within this range.
15. Value reflects all outputs ON and equally conducting 1.0 A each. VPWR = 5.5 V, CS = 5.0 V.
16.
17.
18.
An overvoltage condition will cause any enabled outputs to latch OFF (disabled).
This parameter is guaranteed by design; however, it is not production tested.
For VDD less than the Power-ON Reset voltage, all outputs are disabled and the serial fault register is reset to all 0s.
19.
Drain current per output with VPWR = 24 V and VLOAD = 9.0 V.
20.
Drain current per output with VPWR = 13 V, VLOAD = 9.0 V.
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STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SI Logic High
SIV IH
4.0
–
–
V
SI Logic Low
SIV IL
–
–
2.0
V
CS and SCLK Logic High
CSV IH
3.0
–
–
V
CS and SCLK Logic Low
CSV IL
–
–
3.0
V
Input Logic High
V IH
3.15
–
–
V
Input Logic Low
V IL
–
–
1.35
V
5.0
–
25
-25
–
-5.0
3.5
–
–
0
–
0.4
CS = 0.7 VDD, VSO = 0.3 VDD
-10
–
–
CS = 0.7 VDD, VSO = 0.7 VDD
–
–
10
–
–
12
–
–
20
Freescale Semiconductor, Inc...
DIGITAL INTERFACE
Input Pull-Down Current (Note 21)
Input Pull-Up Current (Note 22)
V SOL
IOL = 1.0 mA
SO and Tri-State Leakage Current
Input Capacitance (Note 23)
0 = VIN = 5.5 V
V
µA
I SOT
pF
C IN
0 = VIN = 5.5 V
SO and Tri-State Capacitance (Note 24)
V
V SOH
IOH = -1.0 mA
SO and Low-State Output Voltage
µA
I IN(PU)
VIN = 3.5 V
SO and High-State Output Voltage
µA
I IN(PD)
VIN = 1.5 V
C SOT
pF
Notes
21. Inputs SI, IN0 & IN1, IN2 & IN3, IN4 & IN5, and IN0 to IN7 incorporate active internal pull-down current sinks for noise immunity enhancement.
22. The MODE and CS inputs incorporate active internal pull-up current sources for noise immunity enhancement.
23. This parameter applies to inputs SI, CS, SCLK, MODE, IN0 & IN1, IN2 & IN3, IN4 & IN5, and IN0 to IN7. It is guaranteed by design; however,
it is not production tested.
24. This parameter applies to the OFF state (tri-stated) condition of SO and is guaranteed by design; however, it is not production tested.
33882
10
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DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Output Rise Time (Note 25)
tR
1.0
–
10
µs
Output Fall Time (Note 25)
tF
1.0
–
10
µs
Output Turn-ON Delay Time (Note 26)
t DLY (ON)
1.0
–
10
µs
Output Turn-OFF Delay Time (Note 27)
t DLY(OFF)
1.0
–
10
µs
25
–
100
3.0
4.5
6.0
POWER OUTPUT TIMING
Output Short Fault Sense Time (Note 28)
RLOAD = < 1.0 V
Freescale Semiconductor, Inc...
µs
t SS
Output Short Fault Refresh Time (Note 29)
ms
t REF
RLOAD = < 1.0 V
Output OFF Open Load Sense Time (Note 30)
t OS(OFF)
25
60
100
µs
Output ON Open Load Sense Time (Note 31)
t OS(ON)
3.0
–
12
ms
Output Short Fault ON Duty Cycle (Note 32)
SC DC
0.42
–
3.22
%
SCLK Clock High Time (SCLK = 3.2 MHz) (Note 33)
t SCLKH
–
–
141
ns
SCLK Clock Low Time (SCLK = 3.2 MHz) (Note 33)
t SCLKL
–
–
141
ns
Falling Edge (0.8 V) of CS to Rising Edge (2.0 V) of SCLK
t LEAD
–
–
140
DIGITAL INTERFACE TIMING
Required Setup Time (Note 33)
Falling Edge (0.8 V) of SCLK to Rising Edge (2.0 V) of CS
ns
t LAG
Required Setup Time (Note 33)
ns
–
–
50
SI, CS, SCLK Incoming Signal Rise Time (Note 33)
t RSI
–
–
50
ns
SI, CS, SCLK Incoming Signal Fall Time (Note 33)
t FSI
–
–
50
ns
Notes
25. Output Rise and Fall time measured at 10% to 90% and 90% to 10% voltage points respectively across 15 Ω resistive load to a VBAT of
15 V, VPWR = 15 V.
26.
Output Turn-ON Delay Time measured from rising edge (3.0 V) VIN (CS for serial) to 90% VO using a 15 Ω load to a VBAT of 15 V,
VPWR = 15 V.
27.
Output Turn-OFF Delay Time measured from falling edge (1.0 V) VIN (3.0 V rising edge of CS for serial) to 10% VO using a 15 Ω load to a
VBAT of 15 V, VPWR = 15 V.
28.
The shorted output is turned ON during tSS to retry and check if the short has cleared. The shorted output is in current limit during tSS. The
tSS is measured from the start of current limit to the end of current limit.
29.
The Short Fault Refresh Time is the waiting period between tSS retry signals. The shorted output is disabled during this refresh time. The
tREF is measured from the end of current limit to the start of current limit.
30.
32.
The tOS(OFF) is measured from the time the faulted output is turned OFF until the fault bit is available to be loaded into the internal fault
register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 100 µs after the faulted output is off.
The tOS(ON) is measured from the time the faulted output is turned ON until the fault bit is available to be loaded into the internal fault register.
To guarantee a fault is reported on SO, the falling edge of CS must occur at least 12 ms after the faulted output is ON.
Percent Output Short Fault ON Duty Cycle is defined as (tSS) ÷ (tREF) x 100. This specification item is provided FYI and is not tested.
33.
Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.
31.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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33882
11
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, 9.0 V ≤ VPWR ≤ 17 V, -40°C ≤ TA ≤ 125°C unless otherwise noted.
Characteristic
Symbol
SI Setup to Rising Edge (2.0 V) of SCLK (at 3.2 MHz)
–
–
45
90
–
–
ns
ns
–
SO Hold After SCLK Rising (2.0 V)/Falling (0.8 V) Edge
SO Rise Time
–
45
ns
t SOHOLD
Required Hold Time (Note 34)
90
–
–
–
–
50
–
50
ns
t RSO
CL = 200 pF
SO Fall Time
t FSO
Unit
ns
t SIHOLD
Required Hold Time (Note 34)
Freescale Semiconductor, Inc...
Max
t SOSU
Required Setup Time (Note 34)
SI Hold After Rising Edge (2.0 V) of SCLK (at 3.2 MHz)
Typ
t SISU
Required Setup Time (Note 34)
SO Setup to SCLK Rising (2.0 V)/Falling (0.8 V) Edge
Min
–
CL = 200 pF
ns
Falling Edge of CS (0.8 V) to SO Low-Impedance (Note 35)
t SOEN
–
–
110
ns
Rising Edge of CS (2.0 V) to SO High-Impedance (Note 36)
t SODIS
–
–
110
ns
–
65
80
–
–
1.0
Falling Edge of SCLK (0.8 V) to SO Data Valid
t SOVALID
CL = 200 pF at 3.2 MHz (Note 37)
CS Rising Edge to Next Falling Edge (Note 34)
Notes
34.
35.
36.
37.
33882
12
Xfer DELAY
ns
µs
Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.
Enable time required for SO. Pull-up resistor = 10 kΩ.
Disable time required for SO. Pull-up resistor = 10 kΩ.
Time required to obtain valid data out of SO following the falling edge of SCLK.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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This Product,
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Freescale Semiconductor, Inc.
Timing Diagrams
NORMAL OPERATION
PUT
InputXX
GateXX
ATE
IOUT
UT
XX
5.0
V
5V
00V
V
ON
ON
OFF
OFF
IO(LIM)
IDLIM
IILOAD
LOAD
00AA
Normal
Operation
Fault Bit X
ULT
BIT X
Freescale Semiconductor, Inc...
OFF
PUT
X
Input X
5.0
V
5V
00VV
Gate XX
ATE
ON
ON
OFF
OFF
IOUT
UT
XX
SHORT OCCURS W HILE ON, ENDS DURING REFRESH
SHORTED
LOAD
/ SHORT - TO
- VBAT
Shorted
Load/Short-to-V
PWR
tSSD
I
I
0A
O(LIM)
IDLIM
LOAD
ILOAD
0A
TSSD
tREF
TREF
tTREF
REF
Fault Bit X
ULT BIT X
SB
CB
tSSA
TSSA
TREF
tREF
Fault
FAULT
tSSD
TSSD
tTREF
REF
Shorted
Operation
Fault
FAULT
GATE X = COMMAND SIGNAL AT THE GATE OF DRIVER X
CommandFAULT
Signal at
the Gate of
X
FAULT Gate
BIT XX==INTERNAL
REGISTER
BITDriver
STATE
TREF x
Fault Bit X = Internal Fault Register Bit State
= FIRST
REFRESH
THANt TREF
tREF
X = First
RefreshTIME
TimeMAY
mayBE
beLESS
less than
REF
ILOAD = 1.0 A
ILOAD = 1A
Figure 2. Short Occurring While On, Ending During Refresh (ILOAD = 1.0 A)
NORMAL OPERATION
PUT
InputXX
ATE
GateXX
UT
XX
IOUT
5.0
V
5V
0 0V
V
ON
ON
OFF
OFF
IIDLIM
O(LIM)
IILOAD
LOAD
00AA
Normal
Operation
Fault BIT
Bit X X
AULT
SHORT OCCURS W HILE ON, ENDS DURING RETRY
PUT
X
Input X
Gate X
X
ATE
IOUTX X
UT
Shorted LOAD
Load/Short-to-V
SHORTED
/ SHORT - PWR
TO - VBAT
5.0
5V V
0 0V
V
ON
ON
OFF
OFF
IO(LIM)
IDLIM
ILOAD
ILOAD
0A
0A
tSSD
TSSD
tREF
TREF
Fault Bit X
AULT BIT X
SB
CB
tREF
TREF
tSSA
TSSD
tTREF
REF
tTREF
REF
TSSA
Fault
FAULT
tSSD
Shorted
Operation
Fault
FAULT
GATE X = COMM AND SIGNAL AT THE GATE OF DRIVER X
Gate X = Command Signal at the Gate of Driver X
Fault
X INTERNAL
= Internal Fault
Register
Bit State
FAULT
BIT Bit
X =
FAULT
REGISTER
BIT STATE
tREF X = First Refresh Time may be less than tREF
TREF Ix = FIRST
REFRESH TIM E M AY BE LESS THAN TREF
LOAD = 1.0 A
ILOAD = 1A
Figure 3. Short Occurring While On, Ending During Retry (ILOAD = 1.0 A)
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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13
Freescale Semiconductor, Inc.
PUT
InputXX
ATE
GateXX
IOUT
UT
XX
5.0
5V V
0 0V
V
ON
ON
OFF
OFF
IIDLIM
O(LIM)
IILOAD
LOAD
00AA
Normal
Operation
Fault BIT
Bit X X
AULT
Freescale Semiconductor, Inc...
SHORT OCCURS W HILE ON, ENDS DURING REFRESH
PUT
X
Input X
5.0
V
5V
0 0V
V
Gate X
X
ATE
ON
ON
OFF
IOUTXX
UT
Shorted
Load/Short-to-V
SHORTED
LOA
D / SHORT - TOPWR
- VBAT
OFF
tTREF
REF
Fault Bit X
AULT BIT X
SB
CB
tSSD
tTSSA
SSA
IO(LIM)
I
0A
IDLIM
LOAD
ILOAD
0A
TSSD
tTREF
REF
tREF
TR EF
FAULT
Fault
tREF
TREF
Shorted
Operation
Fault
FAULT
G ATE X = COM MAND SIGNA L AT THE GATE OF DRIVER X
Gate X = Command Signal at the Gate of Driver X
FAULT Fault
BIT XBit
=X
INTERNAL
REGIS TER
BIT STATE
= InternalFAULT
Fault Register
Bit State
t = FIRST
X = First
Refresh Time may be less than t TREF
TREF x REF
REFRESH TIM E MAY BE LESS THANREF
ILOAD = 20 mA
ILOAD = 20mA
Figure 4. Short Occurring While On, Ending During Refresh (ILOAD = 20 mA)
NORMAL OPERATION
PUT
Input X
X
ATE
Gate X
O UT
IOUTXX
5.05VV
0V
0V
ON
ON
OFF
OFF
IO(LIM)
IDLIM
ILOAD
ILOAD
0 0A
A
Normal
Operation
Fault Bit
X X
AULT
BIT
SHORT OCCURS W HILE ON, ENDS DURING RETRY
NPUT
Input XX
Gate XX
ATE
IOUTXX
OUT
Shorted LOAD
Load/Short-to-V
SHORTED
/ SHORT - TO
PWR- VBAT
5.05VV
0V
0V
ON
ON
OFF
OFF
IIDLIM
O(LIM)
IILOAD
LOAD
00AA
tSSA
TSSA
tREF
TREF
Fault Bit X
AULT BIT X
SB
CB
tTSSD
SSD
tREF
TREF
Fault
FAULT
tSSD
TSSD
tTREF
REF
tREF
TREF
Shorted
Operation
Fault
FAULT
GATE X = COMM AND SIGNAL AT THE GATE OF DRIVER X
Gate X = Command Signal at the Gate of Driver X
FAULTFault
BIT Bit
X =XINTERNAL
FAULT
REGISTER
BIT STATE
= Internal Fault
Register
Bit State
tREF X = First Refresh Time may be less than tREF
TREF x = FIRST REFRESH TIM E M AY BE LESS THAN TREF
ILOAD = 20 mA
ILOAD = 20m A
Figure 5. Short Occurring While On, Ending During Retry (ILOAD = 20 mA)
33882
14
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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Freescale Semiconductor, Inc.
Electrical Performance Curves
RDS(ON)
0.42
54.8
0.41
54.6
0.4
54.4
0.39
Freescale Semiconductor, Inc...
0.38
54.2
54.0
0.37
53.8
0.36
53.6
0.35
25
40
55
70
85
VCLAMP
55.0
VOLTS
OHMS
0.43
100
115
AMBIENT TEMPERATURE (°C)
Figure 6. Output RDS(ON) Versus Temperature
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
130
53.4
-50
-25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
Figure 7. Output Clamp Voltage Versus Temperature
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15
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Table 1. Logic Table
Mode of Operation
Normal Operation
Default
Terminal
HPW01
HPW45
Input
Terminals
543210
Gates
543210
Outputs
543210
00111111
00000000
00111111
L
X
X
XXXXXX HHHHHH
LLLLLL
001X1010
00000000
001Y1010
L
X
X
XHXLXL HHHLHL
LLLHLH
000101X1
00000000
000101Y1
L
X
X
LXLXHX LHLHHH
HLHLLL
00XXX000
00000000
00YYY000
L
X
X
HHHLLL HHHLLL
LLLHHH
00XXXXXX
11111111
11111111
H
H
H
XXHLXX HHHLHH
LLLHLL
00XXXXXX
11111111
11111111
H
H
L
XXLHXX HHLHLL
LLHLHH
00XXXXXX
11111111
11111111
H
L
H
XXHLXX LLHLHH
HHLHLL
00XXXXXX
11111111
11111111
H
L
L
XXLHXX LLLHLL
HHHLHH
Overvoltage Shutdown
00XXXXXX
00XXXXXX
00XXXXXX
X
X
X
XXXXXX LLLLLL
HHHHHH
Short-to-Battery /
Short Circuit Output 0
00XXXXX0
00000000
00YYYYY0
L
X
X
XXXXXL YYYYYL
YYYYYH
00XXXXX1
00000001
00YYYYY0
L
X
X
XXXXXX YYYYYH YYYYYH
Open Load/
Short-to-Ground Output 0
00XXXXX0
00000001
00YYYYY1
L
X
X
XXXXXL YYYYYL
YYYYYL
00XXXXX1
00000000
00YYYYY1
L
X
X
XXXXXX YYYYYH
YYYYYL
Default Mode
Freescale Semiconductor, Inc...
Status
Status
Command
Transmitted Transmitted
Sent
Next SO
SO
Legend
0011XXYY = Serial (SPI) commands and status bytes (8-bit operation mode) MSB to LSB.
0 = Off command, SO OK status.
1 = On command, SO FAULT status.
X = Don’t care.
Y = Defined by state of X.
H = High-voltage level: Active state for inputs/gates, inactive state for outputs.
L = Low-voltage level: Inactive state for inputs/gates, active state for outputs.
33882
16
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33882 incorporates six 1.0 A low-side switches using
both Serial Peripheral Interface (SPI) I/O as well as optional
parallel input control to each output. There are also two lowpower (30 mA) low-side switches with SPI diagnostic feedback,
but parallel-only input control. The 33882 incorporates
SMARTMOS technology with CMOS logic, bipolar/MOS
analog circuitry, and DMOS power MOSFETs. Designed to
interface directly with a microcontroller, it controls inductive or
incandescent loads. Each output is configured as an open drain
transistor with dynamic clamping.
Freescale Semiconductor, Inc...
FUNCTIONAL TERMINAL DESCRIPTION
VPWR Terminal
SI Terminal
The VPWR terminal is connected to battery voltage. This
supply is provided for overvoltage shutdown protection and for
added gate drive capabilities. A decoupling capacitor is
required from VPWR to ground.
The Serial Input terminal is connected to the SPI Serial Data
Output terminal of the control IC from where it receives output
command data. This input has an internal active 25 µA pulldown and requires CMOS logic levels. The serial data
transmitted on this line is an 8- or 16-bit control command sent
MSB first, controlling the six output channels. Bits A5 through
A0 control channels 5 through 0, respectively. Bits A6 and A7
enable ON open load fault detection on channels 5 through 0.
The control IC will ensure that data is available on the rising
edge of SCLK. Each channel has its serial control bit high with
its parallel input to determine its state.
IN0 & IN1, IN2 & IN3, and IN4 & IN5 Terminals
These input terminals control two output channels each
when the MODE terminal is pulled high: IN0 & IN1 controls
OUT0 and OUT1, IN2 & IN3 controls OUT2 and OUT3, while
IN4 & IN5 controls OUT4 and OUT5. These terminals may be
connected to PWM outputs of the control IC and pulled high or
pulled low to control output channel states while the MODE
terminal is high. The states of these terminals are ignored
during normal operation (MODE terminal low) and override the
normal inputs (serial or parallel) when the MODE terminal is
high. These terminals have internal active 25 µA pull-downs.
MODE Terminal
The MODE terminal is connected to the MODE terminal of the
control IC. This terminal has an internal active 25 µA pull-up.
When pulled high, the MODE terminal does the following:
• Disables all serial control of the outputs while still reading
any serial input commands.
• Disables parallel inputs IN0, IN1, IN2, IN3, IN4, and IN5
control of the outputs.
• Selects IN0 & IN1, IN2 & IN3, and IN4 & IN5 input
terminals for control of OUT0 and OUT1, OUT2 and
OUT3, OUT4 and OUT5, respectively.
• Turns off OUT6 and OUT7.
• Tri-states the SO terminal.
IN0 to IN7 Terminals
These are parallel input terminals connected to output
terminals of the control IC. Each parallel input is logic high with
the corresponding SPI control bit to control each output
channel. These terminals have internal 25 µA active pulldowns.
OUT0 to OUT7 Terminals
Each terminal is one channel's low-side switch output. OUT0
to OUT5 are actively clamped to handle inductive loads.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
SCLK Terminal
The SCLK terminal of the control IC is a bit (shift) clock for
the SPI port. It transitions one time per bit transferred when in
operation. It is idle between command transfers. It is 50% duty
cycle and has CMOS levels. This signal is used to shift data to
and from the device. For proper fault reporting operation, the
SCLK input must be low when CS transitions from high to low.
CS Terminal
The CS terminal is connected to a chip select output of the
control IC. The control IC controls which device is addressed by
pulling the CS terminal of the desired device low, enabling the
SPI communication with the device, while other devices on the
serial link keep their serial outputs tri-stated. This input has an
internal active 25 µA pull-up and requires CMOS logic levels.
SO Terminal
The Serial Output terminal is connected to the SPI Serial
Data Input terminal of the control IC or to the SI terminal of the
next device in a daisy chain. This output will remain tri-stated
unless the device is selected by a low CS terminal or the MODE
terminal goes low. The output signal generated will have CMOS
logic levels and the output data will transition on the falling
edges of SCLK. The serial output data provides fault
information for each output and is returned MSB first when the
device is addressed. Fault bit assignments for return data are
as follows: MSB-0 through MSB-7 are output fault bits for OUT7
to OUT0, respectively. In 8-bit SPI mode, under normal
conditions, the SO terminal (not daisy chained) returns all 0s,
representing no faults. If a fault is present, a 1 is returned for the
appropriate bit. In 16-bit SPI mode, sending a double command
byte will provide a command verification byte following the fault
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17
Freescale Semiconductor, Inc.
status byte returned from the SO terminal (non-daisy chained).
With the MODE terminal high, the serial output terminal tristates. If nothing is connected to the SO terminal except an
external 10 kΩ pull-up resistor, data is read as all 1s by the
control IC.
VDD Terminal
This terminal is connected to the 5.0 V power supply of the
system. A decoupling capacitor is required from VDD to ground.
Freescale Semiconductor, Inc...
PERFORMANCE FEATURES
Normal Operation
SO Terminal Operation
OUT0 to OUT7 are independent during normal operation.
OUT0 to OUT5 may be driven serially or by their parallel input
terminals. OUT6 and OUT7 can only be controlled by their
parallel input terminals. Device operation is considered normal
only if the following conditions apply:
The SO terminal provides SPI status, allowing daisy
chaining. The status bits returned to the IC are the fault register
bits with logic [1]s indicating a fault on the designated output or
MODE if all bits return logic [1] (with a 10 kΩ pull-up resistor on
the SO terminal). A command verification is possible if the SPI
mode is switched to 16 bits. The first byte (8 bits) returned
would be the fault status, while the second byte returned would
be the first byte sent feeding through the 33882 IC.
• VPWR of 5.5 V to 24 V and VDD voltage of 4.75 V to 5.25 V.
• Junction temperatures less than 150°C.
• For each output, drain voltage exceeds the Open Load
OFF Detection Voltage, specified in the specification
table, while the output is OFF. For open load detection, an
open condition existing for less than the Open Load
Detection time, specified in the specification table, is not
considered a fault nor is it reported to the fault status
register.
• The MODE terminal is held at the logic low level, keeping
the serial channel/parallel input terminals in control of the
eight outputs.
Serial/Parallel Input Control
Input control is accomplished by the serial control byte sent
via the SPI port from the control IC or by the parallel control
terminals for each channel. For channels 0 to 5 with serial and
parallel control the output state is determined by the OR of the
serial bit and the parallel input terminal state. Serial
communication is initiated by a low state on the CS terminal and
timed by the SCLK signal. After CS switches low, the IC initiates
eight or 16 clock pulses with the control bits being available on
the SI terminal at the rising edge of SCLK.
The bits are transferred in descending bit-significant order.
Any fault or MODE indications on bits returned are logic [1]s.
The last six bits are the command signals to the six outputs.
Upon completion of the serial communication the CS terminal
will switch high. This terminates the communication with the
slave device and loads the control bits just received to the
output channels. Upon device power-up, the serial register is
cleared.
In the application for non-daisy chain configurations, the
number of SPI devices available to be driven by the SO terminal
is limited to eight devices.
Serial Status Output
Serial output information sent on the SPI port is a check on
the fault status of each output channel as well as a check for
MODE initiation. Serial command verification is also possible.
33882
18
The second command byte sent would be latched into the
33882 IC. The CS terminal switching low indicates the device is
selected for serial communication with the IC. Once CS
switches low, the fault status register cannot receive new fault
information and serial communication begins. As the control
bits are clocked from the IC MSB first, they are received on
rising SCLK edges at the SI terminal.
The fault status bits transition on the SO terminal on falling
SCLK edges and are sampled on rising SCLK edges at the
input terminal of the IC SPI device. When the command bit
transmissions for serial communication are complete, the CS
terminal is switched high. This terminates communication with
the device. The SO terminal tri-states, the fault status register is
opened to accept new fault information, and the transmitted
command data is loaded to the outputs. At the same time, the
IC can read the status byte it received.
Daisy Chain Operation (Only Possible with SO
Terminal)
Daisy chain configurations can be used with the SO terminal
to save CS outputs on the IC. Clocking and terminal operations
are as defined in the SO Terminal Operation paragraph. For
daisy chaining two 8-bit devices, a 16-bit SPI command is sent,
the first command byte for the second daisy chain device and
the second command byte for the first daisy chain device. A
command verification is possible if the SPI mode is switched to
32 bits. The first word sent is command verification data fed
through the two 33882 ICs. Data returned in the 32 bits is the
two fault status bytes, followed by the first word sent. Bits sent
out are sampled on rising SCLK edges at the input terminal of
the next IC in the daisy chain.
Note Because SO terminals of the 33882 ICs are tri-stated,
any device receiving its SPI data from a previous 33882 IC SO
terminal in a daisy chain will not receive data if the MODE
terminal is low. This prohibits setting SPI-controlled channels
ON with a SPI command while the MODE terminal is low.
Therefore, all channels remain OFF when the MODE terminal
changes from low to high at vehicle power-up.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
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MODE Operation
During normal operation output channels are controlled by
either the Serial Input control bits or the parallel input terminals.
If the MODE terminal is pulled high:
• Serial input control is disabled.
• Parallel input terminals IN0 to IN5 are ignored.
• The SO terminal is tri-stated.
Freescale Semiconductor, Inc...
OUT0 and OUT1, OUT2 and OUT3, and OUT4 and OUT5
are controlled by the IN0 & IN1, IN2 & IN3, and IN4 & IN5
terminals, respectively. When a 10 kΩ pull-up resistor is used,
a logic high on the MODE terminal or an open serial output
terminal is flagged by the SPI when all bits are returned as
logic [1]s.
Although a logic high on the MODE terminal disables serial
control of outputs, data can still be clocked into the serial input
register. This allows programming of a desired state for the
outputs taking effect only when the MODE terminal returns to a
logic low. For applications using the SO terminal, daisy chaining
is permitted, but if the MODE terminal is high, writing to other
than the first IC in a daisy chain is not possible because the
serial outputs are tri-stated.
Output Drivers
The high-power OUT0 to OUT5 outputs are active clamped,
low-side switches driving 1.0 A typical or less loads. The lowpower OUT6 and OUT7 outputs are unclamped low-side
switches driving 30 mA typical or less loads. All outputs are
individually protected from short circuit or short-to-battery
conditions and transient voltages. The outputs are also
protected by short circuit device shutdown. Each output
individually detects and reports open load/short-to-ground and
short circuit/short-to-battery faults.
Fault Sense/Protection Circuitry
Each output channel individually detects shorted loads/
short-to-battery while the output is ON and open load/short-toground while the output is OFF. OUT0 to OUT5 may also be
programmed via SPI bits 6 and 7 to detect open loads and
shorts-to-ground while the output is ON. Whenever a short or
open fault condition is present on a particular output channel, its
fault bit in the internal fault register indicates the fault with a
logic [1].
When a fault ends, its fault bit remains set until the SPI
register is read, then it returns to a logic [0], indicating a normal
condition. When the CS terminal is pulled low for serial
communication, the fault bits in the internal fault register latch,
preventing erroneous status transmissions and the forthcoming
communication reports this latched fault status. The SO
terminal serial output data for 8-bit SPI mode are the fault status
register bits.
For 16-bit SPI mode and SO terminal (non-daisy chained)
use, a transmitted double command provides the fault byte
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
followed by the first byte of the double command, becoming a
command verification. The status is sent back to the IC for fault
monitoring. Diagnostic interpretation of the following fault types
can be accomplished using the procedure described in the
paragraph entitled Extensive Fault Diagnostics, page 20:
• Communication error
• Open load/short-to-ground
• Short-to-battery or short circuit
When serial communication is ended, the CS terminal
returns high, opening the fault status register to new fault
information and tri-stating the SO terminal.
Two fault conditions initiate protective action by the device:
• A short circuit or short-to-battery on a particular output will
cause that output to go into a low duty cycle operation until
the fault condition is removed or the input to that channel
turns OFF.
• A short circuit condition causes all channels to shut down,
ignoring serial and parallel inputs to the device.
To be detected and reported as a fault, a fault condition must
last a specified time (fault sense time or fault mask time). This
prevents any normal switching transients from causing
inadvertent fault status indications.
Fault status information should be ignored for VBAT levels
outside the 9.0 V to 17 V range. The fault reporting may appear
to function properly but may not be 100 percent reliable.
Short Circuit/Short-to-Battery Sensing and
Protection
When an output is turned ON, if the drain current limit is
reached, the current remains at the limit until the short circuit
sense time, tSS, has elapsed. At this time, the affected output
will shut down and its fault status bit switches to a logic [1]. The
output goes into a low duty cycle operation as long as the short
circuit condition exists and the input to that channel is ON.
This duty cycle is defined by the sense and refresh times. If
a short occurs after the output is ON, the fault sense time
indicates the fault and enters the low duty cycle mode at much
less than t SS. The duty cycle is low enough to keep the driver
from exceeding its thermal capabilities. When the short is
removed, the driver resumes normal operation at the next retry,
but the fault status bit does not return to a normal logic [0] state
until it is read from the SPI. When the CS terminal of this device
is pulled low, the fault status bits are latched, after which any
new fault information is not a part of this serial communication
event.
The low duty cycle operation for a short circuit condition is
required to protect the output. It is possible to override this duty
cycle if the input signal (parallel or SPI) turns the channel ON
and OFF faster than 10 kHz. For this reason control signals
should not exceed this frequency.
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19
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Open Load/Short-to-Ground While Off Sensing
If the drain voltage falls below the Open Load OFF Detection
Voltage at turn OFF for a period of time exceeding the Open
Load Sense Time, the fault status bit for this output switches to
a logic [1].
Freescale Semiconductor, Inc...
If a drain voltage falls below the Open Load OFF Detection
Voltage threshold when the output has been OFF, a fault is
indicated with a delay much less than the Open Load Sense
Time. When the fault is removed, normal operation resumes
and the fault status bit will return to a normal logic [0] state.
When the CS terminal of this device is pulled low, the fault
status bits are latched, after which any new fault information is
not part of this serial communication event.
Overvoltage Sensing and Protection
When VPWR exceeds the Overvoltage Shutdown Threshold,
all channels are shut down. Serial input data and parallel inputs
are ignored. The device resumes normal operation when the
VPWR voltage drops below the Overvoltage Shutdown
Hysteresis voltage. During overvoltage shutdown, some faults
may appear to report accurately; however, fault sensing
operation is only guaranteed for battery voltage levels from
9.0 V to 17 V.
Fault Status Monitoring Requirements for Serially
Controlled Outputs, SO Terminal
Fault monitoring over the serial channel by the IC requires a
minimal amount of overhead for normal operation. Each status
byte received consists of all logic [0]s when faults are not
present. If any logic [1]s are returned, a communication error
occurred, an output fault occurred, or the MODE terminal has
been set low. Upon receiving any logic [1] bits, the IC must
resend the last command, verifying the returned logic [1]s, or
correct any communication error.
A 16-bit SPI transmission with a double command byte to
this 8-bit device allows verification of the command (second
byte returned) in addition to the fault byte (first byte returned).
The command (second) byte returned should mirror the bits
sent unless a communication error occurred, in which case the
command resent should accomplish the correction.
If the returned logic [1] validates, it may indicate a MODE
terminal high or a confirmed output fault. If it was a confirmed
output fault, extensive diagnostics could be performed,
determining the fault type, especially if vehicle service is being
performed. If all bits return high and verify such, the IC must
verify sending a logic low to the MODE terminal. It should then
resend the command, verifying the MODE terminal is at a logic
low level, allowing resumption of a normal operation. If all
logic [1]s are again returned, there is an open SO line, an open
MODE line, or the SPI is not functioning.
33882
20
If the fault does not verify on the command resend, normal
operation is resumed. The error could be a communication
mistake, a momentary output fault, or a fault condition no longer
sensed due to switching the state of the output. For the first two
cases, normal operation is resumed and the software continues
its normal functions. However, in the third case, additional
commands are required for extensive diagnosis of the fault type
if this information is mandatory.
Extensive Fault Diagnostics
More extensive diagnosis may be required under the
following conditions:
• When the fault type of a confirmed fault is desired, the
following scenarios are possible:
– If MSB-2 to MSB-7 indicates a fault, it is an open load/
short-to-ground fault if the output is OFF when the
fault is reported because only open load/short-toground sensing remains operable while an output is
OFF.
– If the output is ON when the fault is reported, the fault
is a short circuit/short-to-battery if ON open load
detection is not enabled via SPI. If ON open load
detection is enabled, it must be disabled and the fault
status reread. If the fault remains, it is a short circuit/
short-to-battery or it is an open load/short-to-ground.
– If MSB-0 to MSB-2 indicates a fault, it is an open load/
short-to-ground fault if the output is OFF when the
fault is reported because only open load/short-toground sensing remains operable while an output is
OFF.
– If the output is ON when the fault is reported, the fault
is a short circuit/short-to-battery.
• When a fault did not confirm on resend, the fault could
either be an short circuit/short-to-battery fault, not sensed
when turned OFF; an open load/short-to-ground fault, not
sensed when turned ON; or a corrected communication
error.
To determine if it is an output fault condition, the faulted
output must be turned back to its previous state with a
new command. This command should be sent twice to
read the status after the output is latched in this state,
thus confirming the fault and reporting it again.
Parallel control of outputs is a mode of control, potentially
requiring extensive diagnostics if a fault is reported. This is
because parallel control signals are completely asynchronous
to the serial commands. Status reports for parallel controlled
outputs could require additional information exchange in
software to:
• Avoid status reads when outputs are transitioned, thereby
avoiding fault masking times.
• Obtain the state of a faulted output for determining fault
type (if required).
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System Actuator Electrical Characteristics (at Room
Temperature)
The device is insensitive to power sequencing for VPWR and
VDD, as well as intolerant to latch-up on all I/O terminals. Upon
power-up, an internal power-ON reset clears the serial
registers, allowing all outputs to power up in the off-state when
parallel control terminals are also low. Although the serial
register is cleared by this power-ON reset, software must still
initialize the outputs with an SPI command prior to changing the
MODE terminal from a high to a low state. This assures known
output states when MODE is low.
Freescale Semiconductor, Inc...
All drains should have a 0.01 µF filter capacitor connected to
ground. Any unused output terminal should not be energized. A
20 Ω resistor to the battery is required to prevent false open
load reporting. There must also be a maximum of 100 Ω of
resistance from VPWR to ground, keeping battery-powered
loads OFF when the IC is powered down. However, all loads
should be powered by VPWR to protect the device from full
transient voltages on the battery voltage.
Power-Up
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33882
21
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
DH SUFFIX
30-TERMINAL HSOP
PLASTIC PACKAGE
CASE 979A-09
ISSUE H
Freescale Semiconductor, Inc...
2X
7.3
6.121
1.1 MAX x 45˚ ± 5˚
2X 2.7
2.5
PIN ONE ID
4X
1 MAX
30
1
1.1
0.9
4X
1 MAX
EXPOSED
HEATSINK
AREA
16
15.8
28X
12.6
11.7
0.8
15
16
11.1
10.9
14.45
13.95
B
0.20
M
2.9
2.7
A
BOTTOM VIEW
C B
H
DATUM
PLANE
0.432
0.35
3.404 3.3
3
2.9
0.32
0.23
DETAIL Y
C
0.28
0.23
0.475
0.35
SEATING
PLANE
0.20
M
C A
SECTION W−W
0.20 C
0.35
W
8˚
MAX
1.1
0.84
GAUGE
PLANE
W
0.152
0.025
30X
.127 C
NOTES:
1. CONTROLLING DIMENSION: MILLIMETER.
2. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M, 1994.
3. DATUM PLANE −H− IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.150 PER SIDE. DIMENSIONS D AND E1 DO
INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −H−.
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE b DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. DATUMS −A− AND −B− TO BE DETERMINED AT
DATUM PLANE −H−.
7. DIMENSION D DOES NOT INCLUDE TIEBAR
PROTRUSIONS. ALLOWABLE TIEBAR
PROTRUSIONS ARE 0.150 PER SIDE.
N
(1.6)
DETAIL Y
33882
22
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
FC SUFFIX
32-TERMINAL QFN
PLASTIC PACKAGE
CASE 1306-01
ISSUE D
PIN 1
INDEX AREA
0.1
0.1 C
7
A
2X
M
C
0.1 C
2X
1.0 1.00
0.8 0.75
0.05 C
5
Freescale Semiconductor, Inc...
7
(0.325)
(0.65)
0.05
0.00
C
SEATING PLANE
DETAIL G
VIEW ROTATED 90o CLOCKWISE
M
B
0.1 C A B
DETAIL M
PIN 1 INDEX
4.85
4.55
25
EXPOSED DIE
ATTACH PAD
32
0.325
1
24
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
4. CORNER CHAMFER MAY NOT BE PRESENT.
DIMENSIONS OF OPTIONAL FEATURES ARE FOR
REFERENCE ONLY.
5. COPLANARITY APPLIES TO LEADS, CORNER LEADS
AND DIE ATTACH PAD.
6. FOR ANVIL SINGULATED QFN PACKAGES, MAXIMUM
DRAFT ANGLE IS 12o.
4.85
4.55
0.1 C A B
17
16
32X
0.65
8
28X
N
9
0.75
0.50
32X
VIEW M-M
0.37
0.23
0.1
M
C A B
0.05
M
C
(45 °)
(2.53)
0.065
0.015
32X
0.60
0.24
0.60
0.24
(0.25)
DETAIL N
DETAIL N
PREFERRED CORNER CONFIGURATION
CORNER CONFIGURATION OPTION
4
4
0.475
0.425
(90)
BACKSIDE
PIN 1 INDEX
°
2.4
2.3
DETAIL T
2X 0.39
0.31
R 0.25
0.15
DETAIL M
PREFERRED BACKSIDE PIN 1 INDEX
2X
DETAIL M
BACKSIDE PIN 1 INDEX OPTION
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
0.1
0.0
DETAIL T
PREFERRED BACKSIDE PIN 1 INDEX
33882
23
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
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MC33882/D
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