datasheet for CH7517 by Chrontel
CH7517
Chrontel
Brief Datasheet
CH7517 DisplayPort to VGA Converter
FEATURES
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GENERAL DESCRIPTION
Compliant with DisplayPort specification version 1.2
and Embedded DisplayPort (eDP) specification version
1.3.
Support 2 Main Link Lanes at either 1.62Gb/s or
2.7Gb/s link rate
Support analog RGB output for VGA with Triple 9-bit
DAC up to 200MHz pixel rate. Sync signals can be
provided in separated or composite manner. Support
VESA and CEA timing standards up to
1920x1200@60Hz
VGA output is compliant with VESA VSIS v1r2
specification
HDCP engine compliant with HDCP 1.3 specification
with internal HDCP Keys
Embedded MCU to handle the control logic
Support device boot up by automatically loading
firmware from on-chip flash Boot ROM
Integrated EDID Buffer, and MCCS bypass supported
Supports Enhanced Framing Mode
Fast and full Link Training for embedded DisplayPort
system
Support eDP Authentication: Alternative Scramble Seed
Reset and Alternative Framing
2 work modes: connect 27MHz crystal, inject 27MHz
clock
DAC connection detection supported
DP input detection supported
Support Auto Power Saving mode and low stand-by
current
Support Spread Spectrum Clocking (de-spreading) for
EMI reduction
DP AUX channel and IIC slave interface are available
for firmware update and debug
Low power architecture
RoHS compliant and Halogen free package
Offered in 40-Pin QFN package (5 x 5 mm)
Chrontel’s CH7517 is a low-cost, low-power
semiconductor device that translates the DisplayPort
signal to the VGA. This innovative DisplayPort receiver
with an integrated VGA encoder is specially designed to
target the notebook/ultrabook, tablet device and PC
market segments. Through the CH7517’s advanced
decoding / encoding algorithm, the input DisplayPort
high-speed serialized multimedia data can be seamlessly
converted to analog RGB video output.
The CH7517 is compliant with the DisplayPort
specification version 1.2 and the Embedded DisplayPort
Specification version 1.3. With internal HDCP key
Integrated, the device support HDCP 1.3 specifications.
In the device’s receiver block, which supports two
DisplayPort Main Link Lanes input with data rate running
at either 1.62Gb/s or 2.7Gb/s, can accept RGB digital
formats in either 18-bit 6:6:6 or 24-bit 8:8:8, and
converted the input signal to VGA output up to
1920x1200@60Hz. Leveraging the DisplayPort’s unique
source/sink “Link Training” routine, the CH7517 is
capable of instantly bring up the video display to the
VGA monitor when the initialization process is
completed between CH7517 and the graphic chip.
The DACs are based on current source architecture. And
the VGA output meet VESA VSIS v1r2 clock jitter target.
With sophisticated MCU and the Boot ROM embedded,
CH7517 support auto-boot and EDID buffer. After the
configuration by firmware, which is auto loaded from
Boot ROM, CH7517 can support DP input detection,
DAC connection detection and determine to enter into
Power saving mode automatically.
APPLICATION
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Notbook/Ultrabook
Tablet Device
Handheld/Portable Device
PC
209-1000-054
Rev 0.3
2012-10-9
1
CHRONTEL
CH7517
HPD
Ref Clock Generator
HPD Generator
Sync generator
DisplayPort
2 lane
DP
Main Stream RX
Video Decoder
HDCP
AUX
H/V/C
Sync
Analog
RGB
DAC
On Chip Flash
MCU & EDID Buffer
DDC
Figure 1: CH7517 Functional Block Diagram
2
209-1000-054
Rev 0.3
2012-10-9
CHRONTEL
CH7517
1.0 PIN-OUT
1.1
Package Diagram
RBIAS
RB
HPD
DVDD
DGND
D1N
D1P
AVDD
D0N
D0P
40
39
38
37
36
35
34
33
32
31
XO
1
30
AGND
XI
2
29
AVSS
AUXP
3
28
RDAC
AUXN
4
27
AVCC
AVSS
5
26
GDAC
AVCC
6
25
AVSS
RESERVED
7
24
BDAC
RESERVED
8
23
AVCC
GNDPLL
9
22
HO/CSYNC
VDDPLL
10
21
VO
CHRONTEL
CH7517
13
14
15
16
17
18
19
20
SPD0
GPIO0
GPIO1
AVSS
AVCC
VGA_SCL
VGA_SDA
12
DGND
SPC0
11
DVDD
QFN40
Figure 2: CH7517 40-pin QFN pin out
209-1000-054
Rev 0.3
2012-10-9
3
CHRONTEL
1.2
CH7517
Pin Description
Table 1: Pin Name Descriptions
Pin #
1
Type
Out
Symbol
XO
2
In
XI
3,4
In/Out
AUXP/N
7,8
RESERVED
Description
Crystal Output
A parallel resonance crystal should be attached between this pin and
XI. If an external CMOS clock is injected to XI, XO should be left
open.
Crystal Input
A parallel resonance crystal should be attached between this pin and
XO.
DisplayPort AUX Port
These two pins are DisplayPort AUX Channel control, which supports
a half-duplex, bi-directional AC-coupled differential signal.
Reserved Pins
13
In
SPC0
14
In/out
SPD0
15,16
In/Out
GPIO[1:0]
19
Out
VGA_SCL
20
In/Out
VGA_SDA
21
Out
VO
22
Out
HO/CSYNC
24
Out
BDAC
VGA HSYNC/CSYNC Output
XOR Gate is default
Blue Component Output
26
Out
GDAC
Green Component Output
28
Out
RDAC
Red Component Output
31,32,34,35
In
D[1:0]P/N
DP Rx Input Lane 1 and Lane 0
38
Out
HPD
DP Receiver Hot Plug Output
39
In
RB
40
In
RBIAS
6,18,23,27
Power
AVCC
Chip Reset
Low to 0V for reset. Typical High level is 3.3V
Current Set Resistor Input
This pin sets the DAC current. A 10KΩ, 1% tolerance resistor should
be connected between this pin and AVSS using short and wide traces
Analog Power Supply (3.3V)
5,17,25,29,
Pad
9,
Power
AVSS
Analog Power Ground
Power
GNDPLL
PLL Power Ground
10
Power
VDDPLL
PLL Power Supply (1.2V)
11,37
Power
DVDD
Digital Power Supply (1.2V)
12,36
Power
DGND
Digital Ground
30
Power
AGND
Analog Power Ground
4
Serial Port Clock Input
This pin functions as the clock pin of the serial port. External pull-up
6.8 KΩ resister is required
Serial Port Data Input / Output
This pin functions as the bi-directional data pin of the serial port.
External pull-up 6.8 KΩ resister is required
General Purpose Input/Output
Serial Port Clock Output to VGA Receiver
The pin should be connected to clock signal of VGA DDC. This pin
requires a pull-up 10 kΩ resistor to the desired voltage level
Serial Port Data to VGA Receiver
The pin should be connected to data signal of VGA DDC. This pin
requires a pull-up 10 kΩ resistor to the desired voltage level
VGA VSYNC Output
209-1000-054
Rev 0.3
2012-10-9
CHRONTEL
33
209-1000-054
Power
Rev 0.3
CH7517
AVDD
2012-10-9
Analog Power supply (1.2v)
5
CHRONTEL
CH7517
2.0 PACKAGE DIMENSION
TOP VIEW
BOTTOM VIEW
B
A
40
B/2
31
1
40
31
30
A
30
1
21
10
C
C/2
10
21
11
11
20
20
F
E
D
I
G
H
Figure 3: 40 Pin QFN Package
Table 2: Table of Dimensions
No. of Leads
40 (5 X 5 mm)
Millimeters
MIN
MAX
SYMBOL
A
B
C
D
E
F
G
H
I
4.90
5.10
3.20
3.75
3.20
3.75
0.4
0.15
0.25
0.35
0.55
0.7
0.8
0
0.05
0.20
0.203
Notes:
Conforms to JEDEC standard JESD-30 MO-220.
6
209-1000-054
Rev 0.3
2012-10-9
CHRONTEL
CH7517
Disclaimer
This document provides technical information for the user. Chrontel reserves the right to make changes at any time
without notice to improve and supply the best possible product and is not responsible and does not assume any
liability for misapplication or use outside the limits specified in this document. We provide no warranty for the use
of our products and assume no liability for errors contained in this document. The customer should make sure that
they have the most recent data sheet version. Customers should take appropriate action to ensure their use of the
products does not infringe upon any patents. Chrontel, Inc. respects valid patent rights of third parties and does not
infringe upon or assist others to infringe upon such rights.
Chrontel PRODUCTS ARE NOT AUTHORIZED FOR AND SHOULD NOT BE USED WITHIN LIFE SUPPORT
SYSTEMS OR NUCLEAR FACILITY APPLICATIONS WITHOUT THE SPECIFIC WRITTEN CONSENT OF
Chrontel. Life support systems are those intended to support or sustain life and whose failure to perform when used
as directed can reasonably expect to result in personal injury or death.
ORDERING INFORMATION
Part Number
Package Type
Operating Temperature Range
Minimum Order Quantity
CH7517A-BF
40 QFN, Lead-free
Commercial : -20 to 70°C
490/Tray
CH7517A-BFI
40 QFN, Lead-free
Industrial : -40 to 85°C
490/Tray
Chrontel
Chrontel International Limited
129 Front Street, 5th floor,
Hamilton, Bermuda HM12
www.chrontel.com
E-mail: sales@chrontel.com
2012 Chrontel - All Rights Reserved.
209-1000-054
Rev 0.3
2012-10-9
7
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