AN-2255 LM3463 Evaluation Board User's Guide 1 Introduction

AN-2255 LM3463 Evaluation Board User's Guide 1 Introduction
User's Guide
SNVA642A – May 2012 – Revised May 2013
AN-2255 LM3463 Evaluation Board
1
Introduction
The LM3463 is a 6-channel linear LED driver with Dynamic Headroom Control (DHC) designed to drive six
strings of high brightness LEDs at maximum supply voltage up to 95V. Each output channel of the
LM3463 evaluation board is designed to deliver 200 mA of LED driving current. The LED turn on voltage
is set to 48V by default, thus the board is able to deliver up to 57.6W total output power. The six output
channels are divided into 4 individual groups to facilitate average LED current control by means of PWM
dimming. The PWM dimming control interface of the LM3463 can accept standard TTL level PWM signals,
analog voltage or serial data to control the dimming duty of the four LED groups individually. The analog
dimming control interface accepts an analog control voltage in the range from 0V to 2.5V to adjust the
reference voltage of the linear current regulators, which enables true LED current adjustment. This
evaluation board is designed to be connected to an external primary power supply. Using three connection
wires, the VIN, GND and VFB, the dynamic Headroom Control (DHC) circuit of the LM3463 adjusts the
output voltage of the primary power supply to maximize system efficiency.
2
Standard Settings of the LM3463 Evaluation Board
•
•
•
•
•
•
•
Input voltage range: 12V to 95V
LED turn on voltage: 48V
Nominal forward voltage of a LED string: 42V
Output current per ch.: 200 mA
System clock freq.: 246 kHz
DHC cut-off freq.: 0.1Hz
Mode of dimming control: Direct PWM Mode
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LM3463 Evaluation Board Schematic
3
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LM3463 Evaluation Board Schematic
J0
TP1
VRAIL
TP2
J1
R2
150 k
C1
1µF
100V
TP3
R4
8.25 k
GND
C2
1 µF
100V
J2
J11
GND
TP4
J3
VFB
NC
GND
1
2
3
TP16
TP12
TP8
TP18
TP14
TP20
TP10
1
2
3
4
5
6
7
8
1
2
3
VLedFB
J7 1
2
3
J6 1
2
3
GND
J5 1
2
3
GND
J4 1
2
3
GND
J8
GND
1
2
D2
(Blue LED)
GND
TP53
TP54
TP55
TP56
TP57
J16
CH4
VCC
TP26
R37
0
R7
NC
TP27
TP28
TP29
TP24
CH5
R9
NC
C4
1 µF
16V
LM3463
IOUTADJ
TP34
TP35
TP36
TP64
TP50
Q4
FDD2572
Q3
FDD2572
GD2
TP48
Q2
FDD2572
TP47
Q1
FDD2572
TP41
R12
NC
CLKOUT
SYNC
GND
TP33
TP63
TP49
TP42
SE5
SE4
SE3
SE2
SE1
SE0
TP31
R11
NC
TP62
Q6
FDD2572
GD0
VREF
C6
0.47 µF
25V
GND
TP61
Q5
FDD2572
GD3
TP30
R10
0
TP60
TP52
GD4
DRVLIM
FS
ISR
CDHC
FCAP
C5
22 nF
25V
TP59
TP51
GD1
R8
64.9 k
TP58
GD5
TP22
VCC
C3
1 µF
16V
J15
CH3
DR5
DR4
DR3
DR2
DR1
DR0
OutP
R6
1.54 k
J9
VIN
Faultb
EN
MODE
DIM01
DIM23
DIM4
DIM5
GND
J14
CH2
U1
GND
EN
Faultb
DIM01
DIM23
DIM4
DIM5
MODE
GND
J13
CH1
BAV20W-TP
VCC
GND
J10
J12
CH0
TP6
R5
2.94 k
D1
R13
1
R14
NC
TP43
R15
1
R16
NC
TP44
R17
1
R18
NC
TP46
TP45
R19
1
R20
NC
R21
1
R22
NC
R23
1
REFRTN
REFRTN
TP37
TP38
TP39
TP40
Power pad of the LM3463 connected to GND
GND
REFRTN
Figure 1. Circuit diagram of the LM3463 evaluation board
2
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Bill Of Materials
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Bill Of Materials
Designator
Description
Package
Part Number
Manufacturer
U1
LED driver
WQFN-48
LM3463
Texas Instruments
C1, C2
Capacitor, 1uF, 100V, X7R
1206
GRM31CR72A105KA01L
MuRata
C3, C4
Capacitor, 1uF, 16V, X7R
0603
C1608X7R1C105K
TDK
C5
Capacitor, 2200 pF, 25V, X7R
0603
GRM188R71E222KA01D
MuRata
C6
Capacitor, 0.47uF, 25V, X5R
0603
GRM188R61E474KA12D
MuRata
D1
Diode, 200V, 200 mA
SOD-123
BAV20W-TP
Micro Commercial
D2
Green LED
Gull-wing
HLMP-6500-F0011
Avago Technologies
J0, J1, J2
Terminal screw
vertical, snapin
7693
Keystone
J3
3 Pos. connector
100 mil pitch
3-641216-3
TE Connectivity
J4, J5, J6, J7, J8
3 Pos. header
100 mil pitch
TSW-103-07-G-S
Samtec
J9
2 Pos. header
100 mil pitch
TSW-102-07-G-S
Samtec
J10
8 Pos. connector
100 mil pitch
3-641216-8
TE Connectivity
J11, J12, J13, J14,
J15, j16
Banana jack connector
8.9 mm dia.
575-8
Keystone
Q1, Q2, Q3, Q4,
Q5, Q6
MOSFET, N-CH, 150V, 29A
DPAK
FDD2572
Fairchild Semiconductor
R2
Resistor, 150 kΩ, 1%, 0.1W
0603
CRCW0603150KFKEA
Vishay-Dale
R4
Resistor, 8.25 kΩ, 1%, 0.1W
0603
CRCW06038K25FKEA
Vishay-Dale
R5
Resistor, 2.94 kΩ, 1%, 0.1W
0603
CRCW06032K94FKEA
Vishay-Dale
R6
Resistor, 1.54 kΩ, 1%, 0.1W
0603
CRCW06031K54FKEA
Vishay-Dale
R8
Resistor, 64.9 kΩ, 1%, 0.1W
0603
CRCW060364K9FKEA
Vishay-Dale
R10, R37
Resistor, 0Ω, 5%, 0.1W
0603
CRCW06030000Z0EA
Vishay-Dale
R13, R15, R17,
R19, R21, R23
Resistor, 1.00Ω, 1%, 0.125W
0805
CRCW08051R00FKEA
Vishay-Dale
R7, R9, R11
Resistor, 1.00kΩ, 1%, 0.1W
0603
CRCW06031K00FKEA
Vishay-Dale
R12, R14, R16,
R18, R20, R22
Resistor, 1.00 kΩ, 1%, 0.125W
0603
CRCW08051K00FKEA
Vishay-Dale
TP1, TP4, TP6,
TP8, TP10, TP12,
TP14, TP16, TP18,
TP20, TP22, TP24,
TP31, TP33, TP35,
TP37, TP40, TP54,
TP56, TP58, TP60,
TP62, TP64
Terminal, Turret
1502–2
Keystone
Orange
5008
Keystone
TP3, TP26, TP27,
TP28, TP29, TP30,
TP34, TP36, TP41,
TP42, TP43, TP44,
TP45, TP46, TP47,
TP48, TP49, TP50,
TP51, TP52, TP53,
TP55, TP57, TP59,
TP61, TP63
TP2
Test Point
Red
5005
Keystone
TP38
Test Point
White
5007
Keystone
TP39
Test Point
Black
5006
Keystone
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Board Layout
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Board Layout
Figure 2. Top Layer
Figure 3. Bottom Layer
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Connection Diagram
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Connection Diagram
LED strings x 6
Default operation conditions of the board:
IOUT per channel:
200 mA
No. of LED per string:
14 (~3.2V forward voltage per LED)
LED turn on voltage:
VRAIL = 48V
Dimming mode:
Direct PWM dimming mode
@ 100% dimming duty
Assumed characteristics of the primary power supply:
VFB = 2.5V
RVFB1 = 39.8 k
RVFB2 = 3.9 k
CH3
CH4
J15
CH5
J16
CH2
J14
J0
CH1
J13
CH0
J11
VRAIL
J12
Primary power supply
(e.g. AC/DC offline converter, DC power supply)
RVFB1
J1
VRAIL
2.5V
WARNING:
HIGH DC
VOLTAGE
VFB
RVFB2
GND
VFB
J2
GND
J10
J7
J5
J8
J6
LM3463 EVALUATION
BOARD
J9
J4
J3
LM3463 evaluation board
Figure 4. Connecting the LM3463 evaluation board to a primary power supply
7
Primary Power Supply
The LM3463 evaluation board is designed to operate with an external primary power supply. A primary
power supply can be any kind of DC power supply with an accessible output voltage feedback node. For
instance, either an AC/DC off-line power converter or a DC/DC switching converter can be used as a
primary power supply. The LM3463 evaluation board should connect to the primary power supply via three
terminals, the VRAIL, GND and VFB as shown in Figure 1.
The board includes three screw type connectors for high current connections, namely J0, J1 and J2. The
J1 and J2 should connect to the positive and GND output terminals of the primary power supply
accordingly with minimum of wire 18 AWG.
Generally, the board is designed to drive from one to six LED strings of 14 serial LEDs per string. The
driving current of each sting is set to 200 mA by default, thus assuming each LED carries a 3.2V forward
voltage, the maximum total output power of this evaluation board under steady state is about 54W.
Because the output voltage of the primary power supply, VRAIL is controlled by the Dynamic Headroom
Control (DHC) circuit of the LM3463 to maintain maximum system efficiency, therefore the VRAIL must have
a wide and adjustable voltage range.
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Primary Power Supply
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Generally the required range of the VRAIL is determined by the highest and lowest possible forward
voltages of the LED strings (respectively, VLED-MAX-COLD and VLED-MIN-HOT). Since the forward voltage of the
LED strings varies according to the changing of the ambient temperature, the voltage for turning the LEDs
on at system startup must be set higher than the VLED-MAX-COLD.Figure 5 shows the different voltage level of
VRAIL at system startup.
VRAIL
VRAIL(peak)
VDHC_READY
VRAIL(steady)
VRAIL(nom)
0
Time
Initiated by
Pushed up
primary power by LM3463
supply
DHC activated
Figure 5. Different voltage levels of the VRAIL at system startup
In Figure 5, the VRAIL is the output voltage of the primary power supply under the control of the LM3463.
VRAIL(peak) is the highest level of VRAIL when the voltage of the OutP pin of the LM3463 equals 0V. VDHC_READY
is the voltage level that the LM3463 turns all output channels on. VRAIL(nom) is the nominal output voltage of
the primary power supply when the OutP pin voltage is higher than VFB+0.6V (i.e. prior to DHC starting)
In order to secure sufficient rail voltage to maintain regulated LED currents when enabling the output
channels, the VRAIL(peak) and VDHC_READY must be set higher than VLED-MAX-COLD (the highest forward voltage of
the LED strings under low ambient temperature). The following settings are suggested to ensure correct
system startup sequence:
1. VRAIL(nom) = VLED-MIN-HOT - 5V
2. VDHC_READY = VLED-MAX-COLD + 5V
3. VRAIL(peak) = VDHC_READY + 5V
Figure 6 shows a suggested procedure to determine the VRAIL(nom), VDHC_READY and VRAIL(peak).
6
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Primary Power Supply
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PROCEDURES
REMARKS
Begin of design
Identify VLED-MAX-COLD
Identify VLED-MIN-HOT
Adjust the nominal output voltage of the
primary power supply,
VRAIL(nom) = VLED-MIN-HOT - 5V
Set the peak output voltage of the primary
power supply (at VOutP = 0.15V),
VRAIL(peak) = VLED-MAX-COLD + 10V
Set the LED turn on voltage,
VDHC_READY = VLED-MAX-COLD + 5V
VLED-MAX-COLD, the highest forward
voltage of LED strings under low
temperature
VLED-MIN-HOT, the lowest forward voltage
of LED strings under high temperature
VRAIL(nom), the nominal output voltage
of the primary power supply.
e.g. Assume VFB = 2.5V,
R1 + R2
VRAIL(nom) = 2.5V x
R2
VRAIL(peak), the output voltage of the
primary power supply when the OutP
pin is pulling to its minimum.
VRAIL(peak) = R1 x
VFB VFB - 0.15 - 0.6
+
+ VFB
R2
RDHC
VDHC_READY, the LED turn on voltage is
defined by RFB1 and RFB2 connected to
the VLedFB pin.
RFB1 + RFB2
VDHC_READY = 2.5V +
RFB2
End of design
Figure 6. Procedures of setting the rail voltage levels.
Because the VRAIL(peak) is the possible highest output voltage of the primary power supply with the LEDs
turned on, the primary power supply must be able to deliver an output power no less than the total LED
current multiplied by the VRAIL(peak). The flow chart in Figure 7 shows the recommended procedure of
selecting a power supply for the LM3463 evaluation board. If the power supply is an off-the-shelf product,
the output voltage and value of the output voltage feedback resistor divider may need to be changed to
allow DHC.
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Response of the DHC Loop
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PROCEDURES
REMARKS
Begin of power
supply selection
Determine:
ILEDx, VRAIL(peak) and VRAIL(nom)
Calculate the required maximum output
Power, PRAIL(peak) of the power supply
Prepare a power converter which has a
maximum output power > POUT(nom) and a
maximum output voltage > VRAIL(peak)
Adjust R1 and R2 to reduce the nominal
output voltage of the power converter to
VRAIL(nom)
VRAIL(peak) is the highest output voltage
that the power converter needs to
deliver.
ILEDx is the forward current of an LED
string.
PRAIL(peak) = No. of output ch. x ILEDx x VRAIL(peak)
The power converter must be able to
deliver a power no less than PRAIL(peak)
even if the VRAIL is pushed to the
maximum by the LM3463, VRAIL(peak)
Adjust the value of R1 and R2 so as to
meet the equation:
R2
VRAIL(nom) = VFB x
R1 + R2
End of power
supply selection
Figure 7. Procedure of selecting a primary power supply
Going through the above procedures, the value of the R5, R2 and R4 are determined. The values of the
R5, R2 and R4 on the LM3463 evaluation board are 2.94 kΩ, 150 kΩ and 8.25 kΩ respectively. The
resistors may need replacing as needed to interface the board to a primary power supply.
8
Response of the DHC Loop
The cut-off frequency of the DHC loop fC(LM3463) is determined by the value of the external capacitor, C4.
The fC(LM3463) is governed by the following equation.
(1)
The default value of the C4 on the board is 1 uF which sets the cut-off frequency of the DHC loop to
0.1Hz.
In order to secure stable operation of the system, the cut-off frequency of the DHC loop of the LM3463
must be set lower than that of the primary power supply. Usually a DHC response of 1/10 of which of the
primary power supply is enough to secure stable operation. In the case where the primary power supply
has an unknown frequency response, the selection of the value of the C4 can be based on estimation.
Use a 1 uF ceramic capacitor as an initial value and reduce the value of C4 to increase the DHC loop
response as needed.
8
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Reducing the System Startup Time
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9
Reducing the System Startup Time
The total system startup time is generally dependent on the frequency response of both the primary power
supply and DHC loop of the LM3463. The slower response of the two circuits, the longer time the system
takes to startup. Because the response of the primary is usually not user programmable, the overall
system startup time can be reduced by shortening the time for the VRAIL to increase from VRAIL(nom) to
VDHC_READY, namely the tST. as shown in Figure 8. The tST is adjusted dependent on the value of the C4 and
RISR, which governed by the following equation:
(2)
where
(3)
VRAIL
tST-1
tST-2
tST-3
VDHC_READY
VLED
VRAIL(nom)
VIN-UVLO
6.67V
0
Startup time
RISR
tST-1
open
tST-2
high
tST-3
low
Time
Figure 8. Adjusting the tST with different value of RISR
The R9 on this evaluation board is opened by default, thus the system startup time is set to the longest.
The startup time of the board can be reduced by putting a 0603 resistor to the position of R9. The value of
the R9 should be no less than 130kΩ.
10
MOSFET Power Dissipation Limit
As the drain voltage of the MOSFETs (Q1, Q2, Q3, Q4, Q5 and Q6) exceeds four times the voltage of the
DRVLIM pin, the output currents are reduced to reduce the power dissipations on the MOSFETs. The
DRVLIM of the LM3463 of this evaluation board is connected to VCC via a 0Ω resistor, R37. Thus the
drain voltage threshold to perform MOSFET power dissipation limit is about 26.4V by default.
11
Analog Dimming Control
The reference voltage for the LED current regulators can be adjusted by changing the voltage at the
IOUTADJ pin of the LM3463. In this evaluation board, the reference voltage for current regulation is set to
200mV by connecting the IOUTADJ pin to VCC via a 0Ω resistor, R10. By default the pull-down resistor to
the IOUTADJ pin, R11 is opened. To adjust the IOUTADJ pin voltage, the R10 and R11 should be
replaced according to the required output current following the equation below:
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PWM Dimming Control
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(4)
The IOUTADJ pin can be biased by a positive voltage in the range of 0V to 2.5V across the terminals
TP31and TP39. If the IOUTADJ pin is going to be biased by an external voltage source, the R10 and R11
should be removed.
12
PWM Dimming Control
The LM3463 evaluation board allows three different modes of PWM dimming control:
• Direct PWM Dimming Mode
• Serial Interface Mode
• DC Interface Mode
• The mode of PWM dimming control is selected by changing the position of the shunt jumper of J8.
Mode of dimming control
Setting of J8
Direct PWM dimming mode
Short Pos. 2–3
Serial interface mode
Open
DC interface mode
Short Pos. 1–2
Using PWM dimming control, the six output channels of the board are grouped into four individual groups
which are controlled by four individual PWM signals at the terminals TP12, TP14, TP16 and TP18.
Terminal
Involved channels
TP12
CH0, CH1
TP14
CH2, CH3
TP16
CH4
TP18
CH5
The terminals J4, J5, J6 and J7 are used to connect the DIM01(TP12), DIM23(TP14), DIM4(TP16) and
DIM5(TP18) pins of the LM3463 to either VCC or GND. The jumpers on these terminals should be
removed if external dimming control signals are applied to the board.
Direct PWM Dimming Mode
In the direct PWM dimming mode, the board accepts standard active high TTL level PWM signals to
perform dimming control. The minimum on duty is generally limited by the gate capacitance of the external
MOSFETs. Normally, an 8 µs minimum on time is suggested.
Serial Interface Mode
In the serial interface mode, the on duty of each output channel is controlled by a data byte of 8 bits wide.
In this mode the terminals TP12, TP14 and TP16 on the board comprise a serial data interface to receive
data bytes from external data source. The connection to the DIM5 pin is not used and should be
connected to GND by shortening the pins 2 and 3 of J7. The functions of the TP12, TP14 and TP16 in the
serial interface mode are as listed in the following table:
Serial Interface Mode
10
Terminal
Function
TP12
Serial data input
TP14
Clock signal input
TP16
End Of data Frame (EOF) signal input
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PWM Dimming Control
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In the serial interface mode the LM3463 evaluation board accepts a data frame which consists of four data
bytes to control the on duty of the four groups of output channels via the terminal TP12 (DIM01). Every
data byte contains 8 bits in LSB (Least Significant Bit) first ordering and is clocked into the data buffer of
the LM3463 at every rising edge of clock signal at the terminal TP14 (DIM23). Every time a data frame is
clocked in to the LM3463 the terminal TP16 (DIM4) should be pulled low to generate a falling edge to
indicate an ‘End-Of-Frame (EOF)’. Figure 9 shows the typical waveform of a data frame and the
corresponding clock and EOF signals.
DIM23
(Clock signal)
DIM01
(Data)
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
LSB
BIT7
MSB
One data byte
DIM23
(Clock signal)
BYTE1
(Group D)
DIM01
(Data)
BYTE2
(Group C)
BYTE3
(Group B)
BYTE4
(Group A)
DIM4
(End of Frame)
BOF
EOF
One data frame
Figure 9. Typical waveforms of a complete data frame in the serial interface mode
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PWM Dimming Control
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PWM dimming duty
256/256
255/256
254/256
253/256
252/256
6/256
5/256
4/256
3/256
2/256
(Skipped)1/256
Input Data Code
(Decimal)
1
2
3
4
5
25
25
25
25
25
5
4
3
2
1
0
0
Figure 10. PWM dimming duty vs code value of a data byte
In the serial interface mode, the six output channels are grouped into four individual groups. The on duty
of each group is controlled by the value of a specific data byte as listed in the following table:
Output channel
Data byte
CH0, CH1
BYTE1
CH2, CH3
BYTE2
CH4
BYTE3
CH5
BYTE4
Because the data width of a data byte is fixed to 8 bits, the step size of the LED current is equal to 1/256
of the full scale current. To allow the use of 0% on duty, the steps 1 and 2 are combined to give a 2/256
on duty. Thus either applying a hexadecimal code 001h or 002h the LM3463 will give a 2/256 on duty. The
dimming duty in the serial interface mode is governed by the following equation:
(5)
Figure 10 shows the relationship of the code value of a data byte and PWM dimming duty.
DC Interface Mode
In the DC interface mode, the on duty of the output channels are adjusted according to the voltage on the
terminals TP12, TP14, TP16 and TP20. In this mode, the six output channels are grouped into four groups
and controlled by the voltage on four terminals individually as listed in the following table:
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Disabling Output Channel(s)
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Output channel
Terminal
CH0, CH1
TP12
CH2, CH3
TP14
CH4
TP16
CH5
TP18
The voltage being applied to the terminals should be in the range of 0.8V to 5.7V. The dimming duty in the
DC interface mode is governed by the following equation:
(6)
In this mode, the conversion of analog voltage to dimming duty is accomplished by an internal 8-bit ADC
of the LM3463, thus the step size of the LED current is equal to 1/256 of the full scale current. To allow
the use of 0% on duty, the steps 1 and 2 are combined to give a 2/256 on duty. Thus either applying a
voltage in the range of 0.8V to 0.8V+VLSB to the dimming control inputs will result in a 2/256 on duty.
Figure 11 shows the Conversion characteristics of the analog voltage to PWM dimming control circuit:
PWM dimming duty
256/256
255/256
254/256
253/256
252/256
VLSB =
5.7V - 0.8V
256
6/256
5/256
4/256
3/256
2/256
(Skipped) 1/256
Analog voltage
at the DIMn pin
V
SB
5.7
5.7
V4
5.7 VLSB
V3V
LS
5.7
B
V2V
5.7 LSB
VVL
0.8
SB
0.8
V
V+
VL
0.8
SB
V+
2V
0.8
L
V+ SB
3V
0.8
L
V+ SB
4V
L
0
Figure 11. Conversion characteristic of the analog voltage to PWM dimming control circuit
13
Disabling Output Channel(s)
An output channel of this evaluation board can be disabled by not connecting an LED string to the output
terminal. A disabled channel is excluded from the DHC loop and remained in OFF state until a falling edge
at the EN pin or system repower is applied. The channel 0 must be used regardless of the number of
disabled channel.
SNVA642A – May 2012 – Revised May 2013
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13
Cascading the LM3463 evaluation board
14
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Cascading the LM3463 evaluation board
A number of the LM3463 evaluation boards can be cascaded to expand the number of output channels.
The connection among boards differs depending on the selected mode for dimming control. The
connection diagrams for the serial interface mode, DC interface mode and direct PWM mode are as
illustrated in the Figure 12, Figure 13, and Figure 14, respectively.
When a number of the LM3463 evaluation boards are cascaded, one of the boards must be set as master
unit and the other boards must be set as slave units. The master unit is the board which has the VFB
terminal connected to the primary power supply. The master unit controls the system startup time and
distributes dimming control signals to the slave units, the connections among the boards differs depending
on the mode of dimming control being selected.
By default, the LM3463 evaluation board is set as a master unit in direct PWM dimming mode with 100%
on duty. To set a board to be a slave unit, the resistors R2 and R4 must be removed and the terminal TP3
(VLedFB pin of the LM3463) should be connected to the terminal TP22 (VCC pin of the LM3463) using an
external connection.
In cascade operation, the number of slave units is virtually unlimited. However, in high power applications
the accumulated voltage drop on the power return part could impair the function of the DHC. Generally it
is suggested not to cascade more than four pieces of the LM3463 evaluation board to secure stable
system operation.
15
PCB Design
Good heat dissipation helps optimize the performance of the LM3463. The ground plane should be used
to connect the exposed pad of the LM3463, which is internally connected to the LM3463 die substrate.
The area of the ground plane should be extended as much as possible on the same copper layer around
the LM3463. Using numerous vias beneath the exposed pad to dissipate heat of the LM3463 to another
copper layer is also a good practice.
CH4
CH5
VRAIL
J1
J7
J8
J5
J6
J9
HIGH DC VOLTAGE
VFB
J2
VFB
J7
TP35
J8
J5
J6
J9
TP16 TP12
J7
TP35
TP3
J8
TP3
TP22
TP22
J4 = OPEN
J5 = OPEN
J6 = OPEN
J7 = SHORT 2-3
J8 = OPEN
J9 = OPEN
SLAVE 1
J4 = OPEN
J5 = OPEN
J6 = SHORT 2-3
J5
J6
J9
LM3463 EVALUATION BOARD
J4
TP3
J3
TP22
J7 = SHORT 2-3
J8 = OPEN
J9 = OPEN
VLedFB = VCC
R2 = OPEN
R4 = OPEN
VFB
CH5
TP12
J3
MASTER
CH4
TP14
TP33
TP12
J3
CH3
GND
J10
LM3463 EVALUATION BOARD
J4
TP14
TP33
CH2
J2
GND
J10
LM3463 EVALUATION BOARD
J4
TP14
CH1
J1
WARNING:
HIGH DC VOLTAGE
WARNING:
HIGH DC VOLTAGE
J2
GND
J10
CH0
J0
J16
CH3
J15
CH2
J14
CH1
J13
J16
J1
CH0
J12
J15
J0
J11
J14
VRAIL
J16
CH5
J15
CH4
J14
CH3
J13
CH2
J12
CH1
J11
CH0
LED array 3
WARNING:
Primary Power Supply
J0
J13
VRAIL
LED array 2
J12
LED array 1
J11
VRAIL
SLAVE 2
J4 = OPEN
J5 = OPEN
J6 = SHORT 2-3
J7 = SHORT 2-3
J8 = OPEN
J9 = OPEN
VLedFB = VCC
R2 = OPEN
R4 = OPEN
GND
LOAD
Interface to MCU for
dimming control
SCLK
SDAT
Figure 12. A 12 channel lighting system using serial interface mode for dimming control
14
AN-2255 LM3463 Evaluation Board
SNVA642A – May 2012 – Revised May 2013
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PCB Design
www.ti.com
CH4
CH5
VRAIL
J1
HIGH DC VOLTAGE
J2
VFB
J7
J5
J8
J6
J9
VFB
J7
TP35
J8
J5
J9
J6
TP16 TP12
J7
TP35
J8
TP3
TP3
CH4
J5
J9
J6
CH5
LM3463 EVALUATION BOARD
J4
TP14
TP33
TP12
TP3
TP12
J3
TP22
SLAVE 1
J4 = OPEN
J5 = OPEN
J6 = SHORT 2-3
MASTER
J7 = OPEN
J8 = SHORT 1-2
J9 = OPEN
J3
TP22
TP22
J4 = OPEN
J5 = OPEN
J6 = OPEN
CH3
GND
J10
LM3463 EVALUATION BOARD
J4
TP14
TP33
J3
CH2
J2
GND
J10
LM3463 EVALUATION BOARD
J4
TP18 TP14
CH1
J1
WARNING:
HIGH DC VOLTAGE
WARNING:
HIGH DC VOLTAGE
J2
GND
J10
CH0
J0
J16
CH3
J15
CH2
J14
CH1
J13
J16
J1
CH0
J12
J15
J0
J11
J14
VRAIL
J16
CH5
J15
CH4
J14
CH3
J13
CH2
J12
CH1
J11
CH0
LED array 3
WARNING:
Primary Power Supply
J0
J13
VRAIL
LED array 2
J12
LED array 1
J11
VRAIL
SLAVE 2
J4 = OPEN
J5 = OPEN
J6 = SHORT 2-3
J7 = SHORT 2-3
J8 = SHORT 1-2
J9 = OPEN
VLedFB = VCC
R2 = OPEN
R4 = OPEN
VFB
J7 = SHORT 2-3
J8 = SHORT 1-2
J9 = OPEN
VLedFB = VCC
R2 = OPEN
R4 = OPEN
GND
VDIM5
VDIM4
DC voltages for
dimming control
VDIM23
VDIM01
Figure 13. A 12 channel lighting system using DC interface mode for dimming control
CH4
CH5
VRAIL
J1
J7
J5
J8
J6
J9
HIGH DC VOLTAGE
VFB
J2
TP35
VFB
J7
J5
J8
J6
J9
TP35
TP3
TP3
TP22
TP22
J4 = OPEN
J5 = OPEN
J6 = OPEN
J7 = OPEN
J8 = SHORT 2-3
J9 = OPEN
SLAVE 1
J4 = OPEN
J5 = OPEN
J6 = OPEN
J7
J5
J8
J6
J9
LM3463 EVALUATION BOARD
J4
TP3
J3
TP22
J7 = OPEN
J8 = SHORT 2-3
J9 = OPEN
VLedFB = VCC
R2 = OPEN
R4 = OPEN
VFB
CH5
TP16 TP12
J3
MASTER
CH4
TP18 TP14
TP33
TP16 TP12
TP16 TP12
J3
CH3
GND
J10
LM3463 EVALUATION BOARD
J4
TP18 TP14
TP33
CH2
J2
GND
J10
LM3463 EVALUATION BOARD
J4
TP18 TP14
CH1
J1
WARNING:
HIGH DC VOLTAGE
WARNING:
HIGH DC VOLTAGE
J2
GND
J10
CH0
J0
J16
CH3
J15
CH2
J14
CH1
J13
J16
J1
CH0
J12
J15
J0
J11
J14
VRAIL
J16
CH5
J15
CH4
J14
CH3
J13
CH2
J12
CH1
J11
CH0
LED array 3
WARNING:
Primary Power Supply
J0
J13
VRAIL
LED array 2
J12
LED array 1
J11
VRAIL
SLAVE 2
J4 = OPEN
J5 = OPEN
J6 = OPEN
J7 = OPEN
J8 = SHORT 2-3
J9 = OPEN
VLedFB = VCC
R2 = OPEN
R4 = OPEN
GND
DIM5
Logic level PWM
dimming control
signals
DIM4
DIM23
DIM01
Figure 14. A 12 channel lighting system using Direct PWM mode for dimming control
SNVA642A – May 2012 – Revised May 2013
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Copyright © 2012–2013, Texas Instruments Incorporated
15
Typical Waveforms
16
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Typical Waveforms
All curves taken at VIN = 48V with configuration in typical application for driving twelve power LEDs with six
output channels active and 200 mA output current per channel. TA = 25°C, unless otherwise specified.
16
Figure 15. Direct PWM Dimming Mode
250Hz 50% dimming duty at DIMn pin
Figure 16. DC Interface Mode
10Hz 3V to 2V ramp at DIMn pin
Figure 17. PWM dimming
IOUTn delay at VDIMn rising
Figure 18. PWM dimming
IOUTn delay at VDIMn falling
Figure 19. IOUTn ch-ch delay
IOUTn rising
Figure 20. IOUTn ch-ch delay
IOUTn falling
AN-2255 LM3463 Evaluation Board
SNVA642A – May 2012 – Revised May 2013
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Copyright © 2012–2013, Texas Instruments Incorporated
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