Intel Itanium Architecture Update

Intel Itanium Architecture Update
Intel® Itanium® Architecture Update
5th October, 2006
Dr. Feixiong Liu
Technical Manager for HP TSG
Intel EMEA
Copyright © 2006 Intel Corporation
Agenda
Itanium® Processor Family Roadmap
Itanium® 2 Processor update & technology highlights
Montecito Processor Performance update
Itanium® 2 Processor Vs Power 5+ competitive position
Itanium® 2 Processor Vs X86 Positioning
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Quiz
How many transistors in the next generation of
Intel® Itanium® 2 processors?
1.72 billion transistors
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Intel® Itanium® Architecture Update
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Intel Confidential
How big is the transistor in the next generation
Itanium® Processor?
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Intel® Itanium® Architecture Update
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Intel Confidential
Intel® Itanium® Processor Family
2001
2002
2003
2004
2006
future
Itanium® 2
Madison**
Madison9M
Montecito**
Tukwila**
Common Platform
800MHz
4MB L3-Cache
460GX Chip-set
OEM Chip-sets
180nm
1GHz
3MB iL3-Cache
E8870 Chip-set
OEM Chip-sets
180nm
1.5GHz
6MB iL3-Cache
E8870 Chip-set
OEM Chip-sets
130nm
1.5GHz
9MB iL3-Cache
E8870 Chip-set
OEM Chip-sets
130nm
1.5GHz
24MB iL3Cache
Dual-Core
E8870
OEM Chip-sets
90nm
Multi-Core
Developed by
former Alpha
team
**codename
All features and dates specified are targets provided for planning purposes only and are subject to change.
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Intel® Itanium® Processor Family
Roadmap Update
2005
2006
2007
2008
Future
Richford Platform
Itanium
Itanium 22
(Madison
(Madison 9M)
9M)
Montecito
Montecito
Tukwila
Tukwila
Montvale
Montvale
Poulson
Poulson
Rose Hill/OEM
Intel® E8870 Chipset/OEM
New Technologies
• Dual-core
• Multi-threading
• Intel® Virtualization Technology
• New instructions
• Cache reliability (Intel® Cache safe Technology)
• Faster FSB
Single
Single
Core
Core
Dual
Dual
Core
Core
Quad
Quad
Core
Core
Multi
Multi
Core
Core
• Multi-core
• Common system architecture w/
Intel® Xeon®
• Enhanced RAS
• Enhanced virtualization
• Enhanced I/O & memory
All features and dates specified are targets provided for planning purposes only and are subject to change without notice
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Agenda
Itanium® Processor Family Roadmap
Itanium® 2 Processor update & technology highlights
Montecito Processor Performance update
64-bit Windows and SQL Server 2005 on Itanium® processor
Itanium® 2 Processor Vs Power 5+ competitive position
Itanium® 2 Processor Vs X86 Positioning
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Intel® Itanium® Architecture Update
Rev i1.1_4718844
Intel Confidential
Introducing
Dual core Intel® Itanium® 2 Processor 9000 Series processor
New features for performance
Performance
2X
Higher
Dual-Core
24MB on-die level 3 cache + new 1MB L2 D-cache
Intel® Hyper-Threading Technology
Intel® Virtualization Technology
Intel® Cache Safe Technology
104W, 2.5x performance/watt improvement
PCI-Express & DDR2
Plus…
Based on EPIC architecture
Power
20%
Lower
Scalability: Systems scaling to 32P, 64P, and
beyond
Mainframe class reliability features
First 1.72 billion transistors processor
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Itanium® Momentum Continues
$10B ISA investment ’06-’10
“Global 100” Deployments
• More than 70 of the world’s 100 largest
companies committed to IPF
8000+
Application Growth
7000
Price / Performance Leadership
$3.93
/tpmc
2400
700
2003
2004
2005
1H’06
Source: Itanium Solutions Alliance
2P
4C
$4.99
/tpmc
$2.75
/tpmc
2P
4C
TPC-C 2P1
Lower is better
$2.71
/tpmc
4P
8C
4P
8C
Power5 570
Platforms based on
DualDual-Core Itanium®
2 Processor 9000
Series
TPC-C 4P2
1 Source www.tpc.org : Source www.tpc.org : IBM eServer p5 570 4P, POWER5 1.9GHz, 4P, (2 processors, 4 cores, 8 threads), 128 GB memory, Oracle Database 10g Enterprise Edition, IBM
AIX 5L V5.3, result of 203,439 tpmC $3.93/tpmC, published on 10/17/05. Itanium® 2 processor results of 200,829 tpmC and $2.75/tpmC on HP Integrity rx4640 using 2 Itanium® 2
processors 1.6GHz with 24MB L3 cache, (2 processors, 4 cores, 8 threads), 128GB memory, Oracle Database 10g Enterprise Edition, HP UX 11.iv2 64-Bit Base OS, was published on 03/21/06.
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2 Source www.tpc.org : HP Integrity rx4640-8 4p c/s, on Intel DC Itanium2 Processor 9050 1.6 Ghz, (4 processors, 8 cores, 16 threads) , with 24M L3 Cache, 128GB memory, Microsoft SQL
Server 2005 Enterprise Itanium Ed., Microsoft Windows Server 2003 Enterprise Edition SP1, published a result of 290,644 tpmc, $/tpmc of 2.71 USD, on 3/27/2006. IBM eServer p5 570 8P,
IBM POWER5
1.9GHz,
(4 processors,
8 cores,
16 threads), Architecture
256GB memory, IBM
DB2 UDB 8.1, submitted a result of 429900 tpmc, 4.99 USD/tpmc on 8/31/2004.
20th July
2006
Intel®
Itanium®
Update
Rev i1.1_4718844
Intel Confidential
Rapid Growth in System Revenue
Relative Itanium System Revenue vs.
SPARC1 and Power1
60%
60%
vs. SPARC1
50%
50%
vs. Power2
Specific
Specific Countries
Countries
45%
40%
40%
versus
1
SPARC
versus
2
Power
Japan
110%
109%
Korea
68%
51%
PRC
55%
43%
352%
97%
42%
30%
30%
20%
20%
10%
10%
Russia
QQ1
100
66
QQ3
300
55
QQ1
100
55
QQ3
300
44
QQ1
100
44
QQ3
300
33
QQ1
100
33
0%
0%
1: SPARC Includes: SPARC I, SPARC II, SPARC III, SPARC IV, SPARC 64 and SPARC 64 V;
2: POWER Includes: Power RS64 II, Power RS64 III, Power RS64 III, Power 3, Power 4, Power 5, and PowerPC
Source: IDC Q1’06 WW Quarterly Server Tracker
Other names and brands may be claimed as the property of others
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Intel® Itanium® Architecture
Processors
Madison9M
Technology
Number of cores
Clockrate
- INT Units
- MM Units
- FP Units
- ADDR Units
L1-Caches (I/D)
L2-Cache (I/D)
L3-Cache
System Bus
- Clockrate
- Width
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130nm
1
1600MHz
6
6
2 (*,+)
2L+2S or 4L
16/16KB
256KB Unified
9MB
6.4GB/s
400MHz
128 bit
Intel® Itanium® Architecture Update
Montecito
90nm
2
1600MHz
6
6
2 (*,+)
2L+2S or 4L
16/16KB
1MB/256KB
24MB on die
8.5GB/s
533MHz
128 bit
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Why Multi-Core?
Performance
Power
1.00x
Max Frequency
Relative single-core frequency and Vcc
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Over-clocking
1.73x
Performance
Power
1.13x
1.00x
Over-clocked
(+20%)
Max Frequency
Relative single-core frequency and Vcc
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Under-clocking
1.73x
Performance
Power
1.13x
1.00x
0.87x
0.51x
Over-clocked
(+20%)
Max Frequency
Under-clocked
(-20%)
Relative single-core frequency and Vcc
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Multi-Core = Energy Efficient Performance
Dual-Core
1.73x
Performance
1.73x
Power
1.13x
1.02x
1.00x
Over-clocked
(+20%)
Max Frequency
Dual-core
(-20%)
Relative single-core frequency and Vcc
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Out-of-order versus Explicit Parallelism
Legacy Architecture
Original
Source
Code
Hardware
Implicitly
Implicitly
parallel
parallel
compiler
compiler
Itanium® Architecture
Parallel
Machine Code
Original
Source
Code
Itanium 2based
compiler
Sequential
Machine Code
Execution Units difficult to
use efficiently
.. .. .. ..
. . . .
Multiple execution
units used more
efficiently but
compiler more
complex
.. .. .. ..
. . . .
Massive
Resources
Compiler for Itanium® key for
successful exploitation of resources
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Multi-Threading Approaches
High utilization
High complexity
Medium latency hiding
Sharing
resources
Single
thread/cycle
Medium utilization
Low complexity
Medium latency hiding
TMT
Multiple
thread/cycle
SMT
A A A B B
A A B B B
Temporal
Event
A A B B B
A A A B B B
A A A
A A A A
B B B B B
A A A A A
A A A A
B B B
A A A
B B B
B B B B
B B B B B
B B B B B
A A B B B B
Medium utilization
Low complexity
High latency hiding
“Event” for the core and “Multiple” for the caches
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Montecito Thread Switching
•
Switch events
– L3 miss/return
• Instruction, Data or HPW access
– Time slice expiration
– Low power state entered/exited
– Switch hint execution (hint@pause instruction retired)
– ALAT invalidation
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Montecito Multi-threading
Serial Execution
Ai
Idle
Ai+1
Bi
Idle
Bi+1
Montecito Multi-threaded Execution
Ai
Idle Ai+1
Bi
Bi+1
Multi-threading decreases stalls and increase performance
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Temporal Multi-Threading
Thread
Thread 11
Run
Run
CC
Stall
Stall
Run
Run
CC
Stall
Stall
Run
Run
Switch
Thread
Thread 22
Run
Run
CC
Stall
Stall
Run
Run
Overlap memory latency stall of
Thread 1 with execution of Thread 2
Stalled Cycles
100%
90%
80%
15-35%
Performance
Gain
70%
60%
CC
Stall
Stall
15 cycle penalty
Database
workloads get a
significant
speedup
50%
40%
30%
20%
10%
0%
SpecInt CPI
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SpecFP CPI
Intel® Itanium® Architecture Update
T PC-C Single
T hread CPI
T PC-C Dualthread CPI
2% core area
impact and 0%
cycle time
impact
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Unmatched Flexibility
Itanium® 2 Architecture Virtualization Benefits
Reduce Data Center Complexity
Reduce Costs
Consolidate applications
Increase server utilization
• Dynamic load balancing between apps
Rapid deployment
Improve manageability
Smaller data center footprint
VM1
VMn
…
App
App
VM1
App
VMn
…
OS
OS
App
OS
OS
VMM
HW0
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HWn
Intel® Itanium® Architecture Update
HW
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Hardware Assisted Virtualization
on Itanium ® Architecture
Itanium® Virtualization Architecture
• Combination of new processor hardware and PAL firmware functionality
• PAL provides a uniform programming
interface across different processor
generations
• Extended the PAL to provide run-time
services for VMM to manage application
and system register state
System Abstraction Layer
(SAL)
Processor Abstraction
Layer (PAL)
Processor (Hardware)
Platform (Hardware)
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Itanium® Virtualization Overview
Processor Status
Register
Guest Software
(Virtualized)
PSR.vm=1
Host Software/
VMM
Intercepts
Non-privileged
Resources
Privileged
Resources
PSR.vm=0
•TLB Accesses
•Privileged Registers
(PSR, Control, Debug)
•Register Stack
Engine (RSE)
Host Virtual Address
Virtualization-supported CPU
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Shared and Dedicated VMs
Dedicated Policy
Shared Policy
• OS solely owns a set of processor
• Processors are shared across
• Reduce conditions that cause
• Avoid intercepts by using shadowed
resources
intercepts
–
(Disable controls)
VM0
App
App
multiple virtual images
processor state
–
...
(Accelerations)
VM1
App
Managed Runtime
App
App
...
VM2
App
Managed Runtime
Guest OS0
Guest OS1
Virtual Host Hardware
Virtual Host Hardware
App
App
...
App
Managed Runtime
Guest OS2
Virtual Host Hardware
Platform (Hardware)
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Advanced Cache Reliability
Intel® cache safe Technology
L3 cache
1. Cache line access
with error detected
2
2. Montecito test for
hard error in cache
line
3
PAL
If hard error
detected, cache
line disabled
3. If hard error is
detected, cache
line is disabled.
Processor and
system continue
normal operation
Error Check
Corrected Path
Data is Consumed by Core
1
Error detected
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Montecito Processor Error Coverage
Structure
Hardware
Action
L1 data cache
Parity
PAL-correctable
L1 tags
Parity
PAL-correctable
L2 cache data
ECC
HW-correctable
L2 cache tags
ECC
L3 cache data
ECC
HW-correctable
HW-correctable +
L3 cache tags
ECC
Cache Safe® cache reliability
HW-correctable
Register
Parity
Recoverable
TLB
Parity
Recoverable
Bus
ECC
1-bit errors HW-correctable,
2-bit errors recoverable
PAL-Correctable and Recoverable errors are dependent upon microarchitectural state
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Comparing reliability Features
Characteristic
Advanced error detection/ correction/
recovery/ logging (MCA)
Itanium® 2
IBM*
Intel® Xeon™
Power* 5
MP
Intel®
Xeon™ DP
3
Internal soft error logic check
Montecito
Cache reliability (Pellston)
Montecito
Processor-level lockstep
Montecito
Memory mirroring and sparing
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Hot Plug I/O (PCI-X, PCI-E) & I/O CRC
3
3
3
3
Error recovery on data bus (ECC and retry)
Partitioning
Memory SDEC, retry on double-bit
Memory scrubbing
AMD*
Opteron*
3
Reliability* Other
required
to replace RISC and mainframes
brands and names are the property of their respective owners.
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Mission Critical Reliability
HP Integrity
NonStop
99.99999%
3 Seconds per
Year
IBM zSeries
5 Minutes 15 Seconds
Downtime per Year
0
1
2
3
4
Minutes
99.999%
5
6
*Other brands and names are the property of their respective owners.
owners.
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Agenda
Itanium® Processor Family Roadmap
Itanium® 2 Processor update & technology highlights
Montecito Processor Performance update
Itanium® 2 Processor Vs Power 5+ competitive position
Itanium® 2 Processor Vs X86 Positioning
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Powerful Database Performance
Comparison
Comparison to
to RISC
RISC
2P/4C TPC-C* Database
A 33%
Better Value
13% higher
performance
Higher is better
230,569
$3.93/tpmc
203,440
&
2P/
4C
P5* 1.9Ghz DC
IBM P570 eServer
Lower is better
$2.63/tpmc
2P/
4C
Itanium 2 9050
1.6 GHz DC
IBM P5* 1.9Ghz DC
IBM P570 eServer
Itanium 2 9050
GHz DC
1.6
Better Value Compared to RISC based Servers
Data Source: Published or Submitted results as of August 30th, 2006 (http://www.tpc.org Dual Core Itanium® 2 Processor 9050.
“p” is a processor or socket and “C” is a core
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Dual-Core Intel® Itanium® 2 processor 9000 sequence server
Scaling performance on Java Benchmark
SPECJBB2005
Ne
a
ine
L
r
S
ar
c
3772246
ng
i
l
a
1887226
942831
471030
16P
32P
64P
128P
Intel Itanium 2 9000 sequence
Data Source: Published or Submitted results as of July 18th, 2006. See backup for details
Itanium 2 9000 sequence: Dual Core Itanium 2 “Montecito 1.6Ghz”
“p” is a processor or socket and “C” is a core
Itanium 2 Platform Shows Excellent scaling
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Business Analytics Performance
1000
1000 GB
GB database
database
Maximum Value
Maximum Performance
2.35x faster than before
OR
With HALF the Processors,
And Lower SW Licensing Costs
Still 80% faster
TPC-H*
TPC-H* with
with Oracle
Oracle 10g
10g R2
R2*
TPC-H* with Microsoft* SQL server
Higher is better
Higher is better
33488
27143
14203
16P/ 16C
Intel Itanium 2
processor 9M
16P/ 32C
Itanium 2 9050
1.6 GHz DC
1.80x
Queries per minute
Queries per minute
2.35x
15069
Compare
8P to 16P
32P/
32C 16P/ 16C
Intel Itanium 2
processor 9M
16P/
8P/32C
16C
Itanium 2 9050
1.6 GHz DC
Data Source: Published or Submitted results as of August 30th, 2006 (http://www.tpc.org Dual Core Itanium® 2 Processor 9050. “p” is a processor or socket and “C” is a core
Performance tests and ratings are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by
those tests. Any difference in system hardware or software design or configuration may affect actual performance. Buyers should consult other sources of information to
evaluate the performance of systems or components they are considering purchasing. For more information on performance tests and on the performance of Intel products,
visit http://www.intel.com/performance/resources/limits.htm or call (U.S.) 1-800-628-8686 or 1-916-356-3104.
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Dual-Core Intel® Itanium® 2 processor 9000 sequence server
Energy efficiency on STAR-CD* 3.22
Lower System Power
AND
Higher Performance
Higher is better
Lower is better
=
Superior Performance/Watt
Higher is better
Measured System Power in Watts
2,6
2,23
2.60x
766
2.23x
660
1
1
0.86x
4P/
4C
Intel Itanium 2
processor-9M
4P/
8C
4P/
4C
Itanium 2 9050
1.6 GHz DC
Intel Itanium 2
processor-9M
4P/
8C
Itanium 2 9050
1.6 GHz DC
4P/
4C
Intel Itanium 2
processor-9M
4P/
8C
Itanium 2 9050
1.6 GHz DC
Data Source: Intel internal measurement, See backup for details
Itanium 2 9000 sequence: Dual Core Itanium 2 “Montecito 1.6Ghz”
“p” is a processor or socket and “C” is a core
Itanium 2 shows 2.6x better performance/watt over Previous generation
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Agenda
Itanium® Processor Family Roadmap
Itanium® 2 Processor update & technology highlights
Montecito Processor Performance update
Itanium® 2 Processor Vs Power 5+ competitive
Itanium® 2 Processor Vs X86 Positioning
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High-end microarchitectures comparisons
Itanium® 2 processor (Montecito)
IBM POWER5+ Processor
1024 TB
16
GB/s
1.9 MB L2 (shared)*
30 GB/s, 87 cycles
Physical Memory Addressing
1024 TB
Max memory bandwidth
8.5 GB/s**
On-die Cache
L3 cache b/w, latency
102 GB/s***, 14 cycles
2
2
Cores / Socket
Threads / Core
2
2
16
Pipeline Stages
8
72 Registers
On-die Registers
264 Application + 64 Predicate
1 Branch
2 Integer
1 Con Reg
2 FP
MAC
2
Load/
Store
2.2 GHz
5 Instructions / Cycle
RISC Architecture
Execution Units
20th July 2006
6 Integer,
3 Branch
2 FP
MAC
2 Load and
2 Store
Core Frequency
1.6 GHz
Max Instructions
Retired / Cycle
6 Instructions / Cycle
* Off-die 36MB shared L3 Cache
** Shared per FSB, assumes one CPU/FSB
35
24 MB L3 (split – 12MB/core)
Intel® Itanium® Architecture Update
EPIC Architecture
*** 51 GB/s for each core
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Industry standards-based platform for mission-critical
solutions provides choice & flexibility
OS Choice
ƒLinux*,
ƒUnix*,
ƒWindows*,
ƒVMS,
ƒ& more
Choice &
Flexibility
Wide OS support helps lower cost
and risk for your mission-critical
solution
Application Choice
ƒ8000+ native applications
Choice &
ƒIA-32 & MIPS
application support
Flexibility
ƒSolaris*, z/OS*, &
OS/390* app support
Server Systems
Choice
ƒBroad selection from
top global & regional
OEMs
ƒ1P to 512P systems
ƒ>15 large SMP systems
Choice &
Flexibility
Migrate and run your mission-critical
application on industry standard
platform at your own pace
Take advantage of rich and broad
vendor support infrastructure
Greater choice helps lower cost and risk
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New Oracle pricing structure for
multi-core processors
Processor
Oracles Core
Multiplier
Niagara
.25
AMD / Intel
.5
All other Multi-core
.75
All Single Core
1.0
Processor
Number of
Oracle licenses
Madison
1
Montecito (dual core)
1
Power5+* (dual core)
1.5
The Intel Advantage:
•Montecito take the advantage away from Power5+*
• 1 Montecito (dual core) = 1 Oracle license
• 1 Power5+* (dual core) = 1.5 Oracle licenses
With the new Oracle pricing structure for multi-core processor
Montecito gains the advantage over Power5+*
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Agenda
Itanium® Processor Family Roadmap
Itanium® Montecito Processor refresh and Recap and technology
highlights
Montecito Processor Performance update
Itanium® 2 Processor Vs Power 5+ competitive
Itanium® 2 Processor Vs X86 Positioning
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Intel’s 64-bit enterprise microarchitectures
Itanium® 2 Processor 9M
Xeon™ EM64T (X86)
1TB 40 bit
6.4 GB/s
Memory Addressing
System Bus Bandwidth
1 MB
HyperHyper-Threading
Technology
HyperHyper-Threading
Technology
32
1 2 3 4
24 Registers
2 2x Integer
1 1x Integer,
1 MMx & SSE
1024 TB
2
Floating
Point
6.4 – 10.6 GB/s
On-die Cache
On-die
multi-thread
Pipeline Stages
Issue
Ports
On-die
Registers
Execution Units
~3.6 GHz
Core Frequency
3 Instructions / Cycle
Instructions / Clk
Performance via Megahertz
9 MB
8
1 2 3 4 5 6 7 8 9 10 11
264 Application Registers
+ 64 Predicate Registers*
6 Integer,
3 Branch
2 FP,
1 SIMD
2 Load and
2 Store
1.6 GHz
6 Instructions / Cycle
Performance via Parallelism
* Intel’s EPIC technology includes 64 single-bit predicate registers
to accelerate loop unrolling and branch intensive code execution.
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Intel® Itanium®2 or Intel® Xeon®?
For Your Most Critical
Data Center Requirements
Scalable
Mainframe-class server
Ultimate Flexibility & Reliability
To Standardize
Your IT Infrastructure
Cost Effective
Reliable
High Performance Servers
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Intel® Itanium® Architecture Update
Itanium
9000 Sequence
RISC / Mainframe Replacement
Medium and Large Enterprise
Xeon
7000 Sequence
5000 Sequence
3000 Sequence
Small, Medium & Large Enterprise
Small and Medium Business
Rev i1.1_4718844
Intel Confidential
Summary
• Itanium architecture’s strong roadmap delivers investment protection
- Multi-core, virtualization, power management, and enhanced system
bandwidth in 2006 with Montecito
• Itanium 2-based platforms deliver outstanding price/performance along
with choice that you don’t get with RISC
• Itanium® = Platform of choice for SQL server Database
• Itanium® = Alternative to proprietary RISC platforms
•
Itanium® = Choice of hardware, OSs and Applications
•
Itanium® = RISC/ mainframe class reliability &
scalability & Performance
Other brands and names are the property of their respective owners
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Quiz
1) What Micro-architecture is dual-core Itanium 2 (Montecito) CPU based?
EPIC
2) How many threads an 8-way integrity server can support
32 threads
3) What is L3 cache memory size in the new dual-core Itanium 2
(Montecito) processor?
24 MB !
4). What new technology is used in Montecito Processor to provide advanced
Cache reliability?
Intel Cache Safe Technology
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For More Information
Intel® Itanium® 2 processor product information
•
intel.com/products/server/processors/server/Itanium®2/
End-user usage – case Studies, testimonials
•
intel.com/business/casestudies/prodserv/index.htm
Reference Solutions and configurations guides
•
43
www.intel.com/business/bss/products/server/itanium2/index.htm?ii
d=ibe_server+dss&#DSS
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Intel Confidential
Thank
You
Questions?
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Intel Confidential
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