E. T. TELECOMUNICACIONS 1BT4 - DIGITAL ELECTRONICS Prof. F. J. Sànchez i Robert 17/10/2007 First minimum control: 20 min. Grades will be available on October 23rd Questions about the examination: TU:15 h – 17 h; TH: 15 h-19h VERY IMPORTANT: Draw a general schematic or plan, develop the exercise and justify the results always explaining what are you doing Minimum 2 Fig. 1 shows the chip to be designed using logic gates, a Gray to 7-segment display decoder to represent the 10 different codes if 4 bits are used and the last 6 combinations are not relevant. . 0 0 0 0 GRAY_DIGIT a X3 b X2 c X1 d X0 e f g R1 220 GRAY_DIGIT Fig. 1 Chip to be designed 1. 2. 3. 4. 5. Deduce the chip’s truth table Write the algebraic equation as a product of maxterms of the output g Write the algebraic equation as a sum of minterns of the output c Simplify by ones the output a using a Karnaugh map Draw the logic circuit for the previously simplified output a using a) only NAND, and b) only NOR You can use the same exercise to study further about: 6. Simplify by zeros (POS) all the outputs using Minilog, implement the logic circuit using only NAND gates and verify it using Proteus-VSM ------------------------------ For example, for knowledge associated with minimum 3: 7. You can ask which is the power consumption of the circuit designed in (6) and which is the maximum frequency of operation if LS-TTL technology is used ------------------------------ For example, for knowledge associated with minimum 4: 8. Solve the circuit by the method of decoders and verify it in Proteus 9. Solve the function g by ones, and implement it by the method of multiplexers using a MUX2 Why the method of decoders is one of the best solutions to build such circuits if they have not many inputs and a lot of outputs?
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