STK5U4UCC0D E D
STK5U4UCC0D-E
Product Preview
30A/600V Intelligent Power Module
in DIP package
The STK5U4UCC0D-E is a fully-integrated inverter power module
consisting of an independent gate driver, six IGBT’s and a thermistor,
suitable for driving permanent magnet synchronous (PMSM) motors,
brushless DC (BLDC) motors and AC asynchronous motors. The IGBT’s
are configured in a 3-phase bridge with separate emitter connections for
the lower legs for maximum flexibility in the choice of control algorithm.
The power stage has under-voltage lockout protection (UVP) and
desaturation protection (DESATP) with a fault detection output flag.
Internal boost diodes are provided for high side gate boost drive.
www.onsemi.com
PACKAGE PICTURE
Features






Three-phase 30A/600V IGBT module with independent drivers.
Negative logic interface.
Built-in under-voltage protection (UVP) and VCE desaturation
Protection (DESATP) with a fault detection output flag.
Integrated bootstrap diodes and resistors.
Separate low-side IGBT emitter connections for individual current
sensing of each phase
Thermistor.
MARKING DIAGRAM
Typical Applications
1
Industrial Drives
Industrial Pumps
Industrial Fans
Industrial Automation
VDU
HINU
FoU
GNDU
Gate Driver
with desaturation
detection
VDV
HINV
FoV
GNDV
Gate Driver
with desaturation
detection
VDW
HINW
FoW
GNDW
Gate Driver
with desaturation
detection
32
ABCDD
W
V
U
STK5U4UCC0D
VP




64
UH
33
Desat UH
STK5U4UCC0D = Specific Device Code
A = Year
B = Month
C = Production Site
DD = Factory Lot Code
VH
Desat VH
UH
VH
WH
UL
VL
WL
WH
Desat WH
ORDERING INFORMATION
Device
Package
TBD
Shipping
(Qty / Packing)
TBD
NW
NV
NU
STK5U4UCC0D-E
TH1
3x Gate Driver
with desaturation
detection
UL
VL
WL
Desat UL
Desat VL
Desat WL
TH2
VDN
LINU
LINV
LINW
FoN
GND
Figure 1. Functional Diagram
This document contains information on a product under development. ON Semiconductor reserves
the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2016
April 2016 - Rev. P1
1
Publication Order Number:
STK5U4UCC0D-E/D
STK5U4UCC0D-E
VDU
VP
FoU
Interface Circuit
(see detail)
+
CS
Gate Driver
with
Desaturation
Cbulk
Protection
HINU
GNDU
U
VDV
FoV
Gate Driver
with
Desaturation
Interface Circuit
(see detail)
Protection
HINV
GNDV
V
Motor
VDW
FoW
Gate Driver
with
Desaturation
Protection
Interface Circuit
(see detail)
HINW
GNDW
W
VDN
MCU
GND
Interface Circuit
(see detail)
LINU
Gate Driver
with
Desaturation
Protection
NU
Interface Circuit
(see detail)
LINV
Gate Driver
with
Desaturation
Protection
NV
LINW
Gate Driver
with
Desaturation
Interface Circuit
(see detail)
Protection
FoN
NW
TH1
Sensing, isolation
TH2
To op-amp circuit
Sample interface circuit detail
VDx
To DESAT circuit
MCU
Fox
HINx
/LINx
To IGBT Gate drive
GNDx
GND
Figure 2. Application Schematic
www.onsemi.com
2
STK5U4UCC0D-E
VDU (29)
VP (33,34,35)
FoU (31)
HINU (30)
Gate Driver
With
Desaturation
Protection
GNDU (32)
U (39,40,41)
VDV (22)
FoV (24)
HINV (23)
Gate Driver
With
Desaturation
Protection
GNDV (25)
V (45,46,47)
VDW (15)
FoW (17)
HINW (16)
Gate Driver
With
Desaturation
Protection
GNDW (18)
W (51,52,53)
VDN (10)
GND (11)
LINU (8)
Gate Driver
With
Desaturation
Protection
NU (57,58)
LINV (7)
Gate Driver
With
Desaturation
Protection
NV (60,61)
FoN (5)
LINW (6)
Gate Driver
With
Desaturation
Protection
NW (63,64)
TH1 (3)
TH2 (2)
Figure 3. Equivalent Block Diagram
www.onsemi.com
3
STK5U4UCC0D-E
PIN FUNCTION DESCRIPTION
Pin
2
3
5
6
7
8
10
11
15
16
17
18
22
23
24
25
29
30
31
32
33,34,35
39,40,41
45,46,47
51,52,53
57,58
60,61
63,64
Name
TH1
TH2
FoN
LINW
LINV
LINU
VDN
GND
VDW
HINW
FoW
GNDW
VDV
HINV
FoV
GNDV
VDU
HINU
FoU
GNDU
VP
U
V
W
NU
NV
NW
Description
Thermistor connection
Thermistor connection
Fault output low side
Logic Input Low Side Gate Driver - Phase W
Logic Input Low Side Gate Driver - Phase V
Logic Input Low Side Gate Driver - Phase U
Control power supply low side
Control power GND low side
Control power supply high side – Phase W
Logic input high side – Phase W
Fault output high side – Phase W
Control power GND high side – Phase W
Control power supply high side – Phase V
Logic input high side – Phase V
Fault output high side – Phase V
Control power GND high side – Phase V
Control power supply high side – Phase U
Logic input high side – Phase U
Fault output high side – Phase U
Control power GND high side – Phase U
Positive Bus Input Voltage
U Phase Output
V Phase Output
W Phase Output
Low Side Emitter Connection - Phase U
Low Side Emitter Connection - Phase V
Low Side Emitter Connection - Phase W
Note : Pins 1, 4, 9, 12, 13, 14, 19, 20, 21, 26, 27, 28, 36, 37, 38, 42, 43, 44, 48, 49, 50, 54, 55, 56, 59, and 62 are not present
www.onsemi.com
4
STK5U4UCC0D-E
ABSOLUTE MAXIMUM RATINGS at Tc= 25°C (Notes 1,2)
Rating
Symbol
Conditions
Value
Unit
450
V
VP to U,V,W; U to NU, V to NV, W to NW
600
V
VD1,2,3,4 = between 13.5V and 16.5V,
Tj ≤ 150°C, up to “tdesatbl”, non-repetitive
400
V
±30
A
±60
A
0.3 to VD
V
0.3 to VD
V
0.3 to VD
V
Supply voltage
VCC
VP to NU,NV,NW, surge < 400V
Collector-emitter voltage
Self-protection supply
voltage limit (DESATP
capability)
Output current
VCE
VCC(SC)
Output peak current
Iop
Gate driver supply voltages
VD1, 2,3,4
Input signal voltage
VIN
FAULT terminal voltage
VFo
Fault output
IFo
Maximum power dissipation
Pd
IGBT per channel
TBD
W
Junction temperature
Tj
IGBT, FRD
150
C
Storage temperature
Tstg
40 to +125
C
Operating case temperature
Tc
Io
Package mounting torque
Isolation voltage
1.
2.
3.
4.
VP,NU,NV,NW,U,V,W terminal current
VP,NU,NV,NW,U,V,W terminal current
pulse width 1ms
VDU to GNDU, VDV to GNDV, VDW to GNDW,
VDN to GND
(Note 4)
HINU to GNDU, HINV to GNDV, HINW to GNDW,
LINU / LINV / LINW to GND
FoU to GNDU, FoV to GNDV, FoW to GNDW,
FoN to GND
FoU, FoV, FoW, FoN Source current
25
FoU, FoV, FoW, FoN Sink current
mA
10
IPM case temperature
Case mounting screw M4
Vis
(Note 3)
40 to +100
C
1.17
Nm
2500
Vrms
(Note 4)
50Hz sine wave AC 1 minute
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device
functionality should not be assumed, damage may occur and reliability may be affected.
Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for
Safe Operating parameters.
This surge voltage developed by the switching operation due to the wiring inductance between VP and NU(NV,NW) terminal.
Flatness tolerance of the heatsink should be within 50m to +100m.
RECOMMENDED OPERATING RANGES (Note 5)
Rating
Supply voltage
Gate driver supply voltage
Symbol
VCC
VD1,2,3
VD4
ON-state input voltage
VIN(ON)
OFF-state input voltage
VIN(OFF)
PWM frequency
fPWM
Conditions
VP to NU, NV, NW
VDU to GNDU; VDV to GNDV;
VDW to GNDW
VDD to GND
HINU to GNDU, HINV to GNDV, HINW
to GNDW, LINU / LINV / LINW to GND
Min
Typ
0
Max
Unit
400
V
V
12.6
15
17.5
13.5
15
16.5
V
0
-
0.7
V
3.3
-
15
V
1
-
20
kHz
μs
Dead time
DT
Turn-off to turn-on (external)
2
-
-
Allowable input pulse width
PWIN
ON and OFF
1
-
-
μs
0.79
-
1.17
Nm
Package mounting torque
5.
M4 type screw
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to
stresses beyond the Recommended Operating Ranges limits may affect device reliability.
www.onsemi.com
5
STK5U4UCC0D-E
ELECTRICAL CHARACTERISTICS (Note 6)
at Tc=25C, VD1, VD2, VD3, VD4=15V
Parameter
Test Conditions
Symbol
Min
Typ
Max
Unit
-
-
1
mA
-
(1.6)
TBD
V
-
(1.7)
-
V
-
(1.7)
TBD
V
-
(1.8)
-
V
Power output section
Collector-emitter leakage current
Collector to emitter saturation voltage
Diode forward voltage
Junction to case thermal resistance
Switching time
VCE = 600V
ICE
Ic = 30A, Tj = 25C
VCE(SAT)
Ic = 30A, Tj = 100C
IF = 30A, Tj = 25C
VF
IF = 30A, Tj = 100C
IGBT
θj-c(T)
-
(0.85)
TBD
C/W
FWD
θj-c(D)
-
(1.06)
TBD
C/W
tON
-
(0.3)
-
μs
Ic = 30A, VCC = 300V, Tj = 25°C
tOFF
-
(0.6)
-
μs
EON
-
(0.8)
-
mJ
EOFF
-
(0.7)
-
mJ
Total switching loss
ETOT
-
(1.5)
-
mJ
Turn-on switching loss
EON
-
(0.9)
-
mJ
EOFF
-
(0.8)
-
mJ
ETOT
-
(1.7)
-
mJ
EREC
-
(0.05)
-
mJ
trr
-
(0.1)
-
μs
-
8
17
mA
-
24
51
mA
Turn-on switching loss
Turn-off switching loss
Turn-off switching loss
Ic = 30A, VCC = 300V, Tj = 25°C
Ic = 30A, VCC = 300V, Tj = 100°C
Total switching loss
Diode reverse recovery energy
Diode reverse recovery time
Ic = 30A, VCC = 300V, Tj = 100°C
(di/dt set by internal driver)
Driver Section
Gate driver power dissipation
High level Input voltage
VD1, 2, 3 = 15V
ID
VD4 = 15V
VIN H
3.2
-
-
V
Low level Input voltage
HINU to GNDU, HINV to GNDV, HINW
to GNDW, LINU / LINV / LINW to GND
VIN L
-
-
1.2
V
Logic 1 input current
VIN=3.0V
IIN+
-
-
500
μA
Logic 0 input current
VIN=1.2V
IIN-
-
-
100
μA
FoU, FoV, FoW, FoN Sink: 5mA
VFL
-
0.2
1.0
V
FoU, FoV, FoW, FoN Source: 20mA
VFH
12
13.3
-
V
-
2
-
μs
VDUVP+
11.3
12.0
12.6
V
VDUVP-
10.4
11.0
11.7
V
FAULT terminal output voltage
Desaturation protection blanking time
tdeasatbl
VD supply undervoltage
positive going input threshold
VD supply undervoltage
negative going input threshold
Bootstrap diode reverse current
VR(BD) = 600V
IR(BD)
-
-
1
mA
Bootstrap diode forward voltage
IF(BD) = 0.1A
Including voltage drop by resistor
VF(BD)
-
(2.3)
-
V
RB
-
15
-
Ω
Bootstrap current controlling resistor
6.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
www.onsemi.com
6
STK5U4UCC0D-E
APPLICATIONS INFORMATION
Logic and Protection Timing Chart
DESAT protection reset signal
/VIN
OFF
ON
VD undervoltage protection reset voltage
VD*
Output
Current
OFF
ON
VDESAT threshold
Internal
DESAT
Voltage
Desaturation blanking time
Fault
output
Figure 4. Logic and Protection Timing Chart
Notes
1.
2.
3.
The VD supply under voltage protection protects the module when the pre-driver supply voltage falls due to an operating
malfunction. It will typically start up at 12 V (typical). The UVP circuit has typically 1.0 V of hysteresis and will disable the
output if the supply voltage falls below 11 V (typical). The driver power supply low voltage protection turns off the gate and
will automatically reset when recovering to normal voltage. It does not depend on input signal voltage.
The three high-side and three low-side gate driver ICs have their own separate under-voltage shutdown protection which
functions independently of the other phases. For the low-side drivers, there is one combined fault output; it is therefore not
possible to determine which output has caused the desaturation fault. The fault condition is cleared as soon as the input
signal is set HIGH (off state, negative logic levels).
When using the over-current protection with an external shunt resistor, please set the current protection level to be less than
or equal to the peak output current rating (Iop).
Input / Output Logic Table
IGBT output
Protected
Operation
High side - U
High side - V
High side - W
Low side - U
Low side - V
Low side - W
UVP
DESATP
UVP
DESATP
UVP
DESATP
UVP
DESATP
UVP
DESATP
UVP
DESATP
High side
Fault output
Low side
High side
U
V
W
U
V
W
U
V
W
Low
side
OFF
OFF
-
OFF
OFF
-
OFF
OFF
-
OFF
OFF
OFF
OFF
-
OFF
OFF
OFF
OFF
-
OFF
OFF
OFF
OFF
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
High
Low
High
Low
High
*) - (hyphen) follows the actual input signals using negative logic (e.g. LINU = LOW turns on the low-side U phase IGBT).
www.onsemi.com
7
STK5U4UCC0D-E
Thermistor characteristics
Symbol
Condition
Min
Typ.
Max
Unit
Resistance
Parameter
R25
Tc = 25C
Resistance
R100
Tc = 100C
B-Constant (25-50C)
-
B
Temperature range
-
-
97
5.07
4208
40
100
5.38
4250
-
103
5.71
4293
+125
kΩ
kΩ
K
C
Thermistor resistance Rt versus Case temperature Tc
Thermistor resistance Rt [kΩ]
10000
1000
min
typ
max
100
10
1
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100 110 120 130
Case temperature Tc [C]
Figure 5. Thermistor Resistance versus Case Temperature
www.onsemi.com
8
STK5U4UCC0D-E
verified prior to production. When not using the
bootstrap circuit, each high side driver power supply
requires an external independent floating power supply.
If the selected capacitance is more than 47μF (±20%),
connect a resistor (about 40Ω) in series between each
3-phase upper side power supply terminals (VDU,
VDV. VDW) and each bootstrap capacitor. When not
using the bootstrap circuit, each upper side gate driver
power supply requires an external independent floating
power supply.
Also we recommend adopting safety measures such as
using Zener diodes for surge absorption or low
impedance capacitors around each power supply
terminal to suppress voltage transients.
Under-voltage lockout (UVLO)
If VDx goes below the VDx supply under-voltage
negative going input threshold, the IGBT gate drives
will be turned off. If VDx rises above the positive
going input threshold, the IGBT gate drivers will return
to normal operation. The FoX signal outputs stay low
during the UVLO protection state. The UVLO
protection does not depend on input signal voltage.
Desaturation Protection function (DESATP)
The Desaturation Protection function (DESATP) is
implemented by comparing the voltage between the
collector and the emitter of IGBT with an internal
reference of 6.5V (typ). If a short circuit occurs after
the IGBT is turned on and saturated, there will be a
delay while the blanking capacitor is charged from the
VCE(sat) level of the IGBT to the trip voltage of the
comparator. If the collector voltage exceeds the trip
level, a DESATP fault is triggered and the FoX signal
(FoU, FoV, FoW, FoN) is set HIGH. The fault
condition is cleared after the input signal is set to
inactive (HIGH due to negative logic on input).
Additional protection against abnormal current levels
such as a protection circuit using external shunt
resistors, and a fuse on the input voltage line is
strongly recommended.
CB value calculation for bootstrap circuit
Calculate condition
Item
Symbol
High-side power supply.
VBS
Total gate charge of output
Qg
power IGBT at 15V.
High-side power supply low
UDUVvoltage protection.
High-side power dissipation. IDmax
ON time required for CB
voltage to fall from 15V to Ton-max
UVLO
Capacitors on High Voltage and VD supplies
Both the high voltage and VDD supplies require an
electrolytic capacitor and an additional high frequency
capacitor.
Value
Unit
15
V
174
nC
12
V
17
mA
-
s
Capacitance calculation formula
CB must not be discharged below to the upper limit of
the UVLO - the maximum allowable on-time (Tonmax) of the upper side is calculated as follows:
Disconnection of U, V and W terminals
Disconnection of terminals U, V, or W during normal
motor operation will cause damage to IPM, use caution
with this connection.
VBS * CB – Qg – IDmax * Ton-max = UVLO * CB
CB = (Qg + IDmax * Ton-max) / (VBS – UVLO)
Minimum input pulse width
When input pulse width is less than 1μs, an output may
not react to the pulse. (Both ON signal and OFF signal)
CB is recommended to be approximately 3 times the
value calculated above. The recommended value of CB
is in the range of 1 to 47μF, however, the value needs
to be verified prior to production.
Layout
The traces between the IPM terminals and each
optocoupler must be as short as possible , and the stray
capacitance between the primary and the secondary
must be considered in order to select a layout pattern.
It is essential that trace length between terminals in the
snubber circuit be kept as short as possible to reduce
the effect of surge voltages. Recommended value of
“CS” is in the range of 0.1 to 10μF. This capacitor
should be a high frequency capacitor.
Boot strap capacitance CB
[uF]
100
CB vs. Ton-max
10
Thermistor
1
0.1
Inside the IPM, a thermistor used as the temperature
monitor for internal substrate is connected between
“TH1” and “TH2”. The variation of thermistor
resistance with temperature is shown in this datasheet.
0.01
0.01
0.1
1
Ton-max [ms]
Figure 6. Bootstrap selection as a function of
maximum ON time
Dimensioning of bootstrap capacitor
The module includes an internal bootstrap circuit
requiring one bootstrap capacitor for each phase, each
with a value CB. The recommended value of CB is in
the range of 1 to 47μF, however, this value needs to be
www.onsemi.com
9
10
STK5U4UCC0D-E
Mounting Instructions
Item
Recommended Condition
Pitch
67.8±0.1mm (Please refer to Package Outline Diagram)
Screw
diameter : M4
Bind machine screw, Truss machine screw, Pan machine screw
Washer
Plane washer
The size is D:9mm, d:4.8mm and t:0.8mm JIS B 1256
Heat sink
Torque
Grease
Material: Aluminum or Copper
Warpage (the surface that contacts IPM ) : 50 to 100 μm
Screw holes must be countersunk.
No contamination on the heat sink surface that contacts IPM.
Temporary tightening : 20 to 30 % of final tightening on first screw
Temporary tightening : 20 to 30 % of final tightening on second screw
Final tightening : 0.79 to 1.17Nm on first screw
Final tightening : 0.79 to 1.17Nm on second screw
Silicone grease.
Thickness : 100 to 200 μm
Uniformly apply silicon grease to whole back.
Thermal foils are only recommended after careful evaluation. Thickness, stiffness and
compressibility parameters have a strong influence on performance.
Recommended
Not recommended
Figure 7. Module mounting details: components; washer drawing; need for even spreading of thermal grease
www.onsemi.com
10
STK5U4UCC0D-E
TYPICAL CHARACTERISTICS
70
VD = 15V
TJ = 25°C
60
IC, COLLECTOR CURRENT (A)
IC, COLLECTOR CURRENT (A)
70
VD = 17V
50
VD = 13V
40
30
20
10
0
VD = 17V
50
VD = 13V
40
30
20
10
0
0
0.5
1
1.5
2
2.5
VCE, COLLECTOR-EMITTER VOLTAGE (V)
3
0
0.5
1
1.5
2
2.5
VCE, COLLECTOR-EMITTER VOLTAGE (V)
Figure 8. IC versus VCE for different VD
1
60
50
STANDARDIZED SQUARE-WAVE PEAK
R(t)
IF, FORWARD CURRENT (A)
3
Figure 9. IC versus VCE for different VD
70
TJ = 25°C
40
TJ = 100°C
30
20
10
0
0
0.5
1
1.5
VF, FORWARD VOLTAGE (V)
2
2.5
0.1
0.01
0.001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
ON-PULSE WIDTH (s)
Figure 10. IF versus VF for different temperatures
Figure 11. IGBT thermal impedance plot
900
250
VCC = 300V
VD = 15V
200
TJ = 100°C
800
toff, SWITCHING TIME (ns)
tON, SWITCHING TIME (ns)
VD = 15V
TJ = 100°C
60
TJ = 25°C
150
100
50
VCC = 300V
VD = 15V
TJ = 100°C
700
600
TJ = 25°C
500
400
300
200
100
0
0
0
5
10
15
20
25
IC, COLLECTOR CURRENT (A)
30
0
35
Figure 12. ton versus IC for different temperatures
10
15
20
25
IC, COLLECTOR CURRENT (A)
30
35
Figure 13. toff versus IC for different temperatures
1.0
0.8
0.9
VCC = 300V
VD = 15V
0.8
Eoff, SWITCHING LOSS (mJ)
EON, SWITCHING LOSS (mJ)
5
TJ = 100°C
0.7
0.6
TJ = 25°C
0.5
0.4
0.3
0.2
0.1
VCC = 300V
VD = 15V
0.7
0.6
TJ = 100°C
0.5
0.4
TJ = 25°C
0.3
0.2
0.1
0.0
0.0
0
5
10
15
20
25
IC, COLLECTOR CURRENT (A)
30
0
35
Figure 14. Eon versus IC for different temperatures
5
10
15
20
25
IC, COLLECTOR CURRENT (A)
30
35
Figure 15. Eoff versus IC for different temperatures
www.onsemi.com
11
STK5U4UCC0D-E
t:100ns/div
t:100ns/div
Io:10A/div
VCE: 100V/div
VCE: 100V/div
Io:10A/div
Figure 16. Turn-on waveform Tj=25°C, VCC=300V
Figure 17. Turn-off waveform Tj=25°C, VCC=300V
t:100ns/div
t:100ns/div
Io:10A/div
VCE: 100V/div
VCE: 100V/div
Io:10A/div
Figure 18. Turn-on waveform Tj=100°C, VCC=300V
Figure 19. Turn-off waveform Tj=100°C, VCC=300V
www.onsemi.com
12
STK5U4UCC0D-E
PACKAGE DIMENSIONS
unit : mm
[TENTATIVE]
Missing pin : 1, 4, 9, 12, 13, 14, 19, 20, 21, 26, 27, 28,
36, 37, 38, 42, 43, 44, 48, 49, 50, 54, 55, 56, 59, 62
to
www.onsemi.com
13
STK5U4UCC0D-E
ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States
and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of
SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf . SCILLC reserves the right to make changes without
further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose,
nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can
and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are
not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers,
employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was
negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all
applicable copyright laws and is not for resale in any manner.
www.onsemi.com
14
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising