Maxim DS28E80 1-Wire Memory Chip Datasheet
EVALUATION KIT AVAILABLE
DS28E80
Gamma Radiation Resistant 1-Wire Memory
General Description
The DS28E80 is a user-programmable nonvolatile memory chip. In contrast to the floating-gate storage cells,
the DS28E80 employs a storage cell technology that is
resistant to gamma radiation. The DS28E80 has 248
bytes of user memory that are organized in blocks of
8 bytes. Individual blocks can be write-protected. Each
memory block can be written 8 times. The DS28E80
communicates over the single-contact 1-Wire® bus at
standard speed or overdrive speed. Each device has its
own guaranteed unique 64-bit registration number that is
factory programmed into the chip. The communication follows the 1-Wire protocol with a 64-bit registration number
acting as node address in the case of a multiple-device
1-Wire network.
Applications
●● Identification of Medical Consumables
●● Identification and Calibration Medical Tools/Accessories
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
Ordering Information appears at end of data sheet.
Features and Benefits
●● High Gamma Resistance Allows User-Programmable
Manufacturing or Calibration Data Before Medical
Sterilization
• Resistant Up to 75kGy (kiloGray) of Gamma Radiation
• Reprogrammable 248 Bytes of User Memory
●● Lower Block Size Provides Greater Flexibility in
Programming User Memory
• Memory is Organized as 8-Byte Blocks
• Each Block Can Be Written 8 Times
• User-Programmable Write Protection for Individual
Memory Blocks
●● Advanced 1-Wire Protocol Minimizes Interface to
Just Single Contact
●● Compact Package and Single IO Interface Reduces
Board Space and Enhances Reliability
• Unique Factory-Programmed, 64-Bit Identification
Number
• Communicates at 1-Wire Standard Speed
(15.3kbps max) and Overdrive Speed (76kbps max)
• Operating Range: 3.3V ±10%, -40°C to + 85°C
Reading, 0°C to +50°C Writing
• ±8kV HBM ESD Protection (typ) for IO Pin
• 6-Pin TDFN Package
Typical Application Circuit
VCC
10kΩ
RPUP
VCC
PIOX
µC
PIOY
GND
19-7120; Rev 0; 9/14
BSS84
DS28E80
IO
GND
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Absolute Maximum Ratings
IO Voltage Range to GND.....................................-0.5V to +4.0V
IO Sink Current.................................................................±20mA
Operating Temperature Range............................ -40°C to +85°C
Junction Temperature.......................................................+150°C
Storage Temperature Range............................. -55°C to +125°C
Lead Temperature (soldering, 10s).................................. +300°C
Soldering Temperature (reflow)
TDFN............................................................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics (Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (θJA)...........60°C/W
Junction-to-Case Thermal Resistance (θJC)................11°C/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
IO PIN: GENERAL DATA
1-Wire Pullup Voltage
VPUP
(Note 3)
2.97
3.63
V
1-Wire Pullup Resistance
RPUP
VPUP = 3.3V ±10% (Note 4)
300
750
Ω
Input Capacitance
CIO
Input Load Current
IL
High-to-Low Switching
Threshold
Input Low Voltage
(Notes 5, 6)
6.5
IO pin at VPUP
5
VTL
(Notes 6, 7, 8)
0.65 x
VPUP
VIL
(Notes 3, 9)
Low-to-High Switching
Threshold
VTH
Switching Hysteresis
nF
22
µA
V
0.3
V
(Notes 6, 7, 10)
0.75 x
VPUP
V
VHY
(Notes 6, 7, 11)
0.3
V
Output Low Voltage
VOL
IOL = 4mA (Note 12)
Recovery Time
tREC
RPUP = 750Ω (Notes 3, 13)
10
Time Slot Duration
(Notes 3, 14)
tSLOT
Standard speed
65
Overdrive speed
13
0.4
V
µs
µs
IO PIN: 1-Wire RESET, PRESENCE DETECT CYCLE
Reset Low Time (Note 3)
tRSTL
Reset High Time (Note 15)
tRSTH
Presence Detect Sample Time
(Notes 3, 16)
tMSP
Standard speed
480
640
Overdrive speed
48
80
Standard speed
480
Overdrive speed
48
Standard speed
60
72
Overdrive speed
8
10
Standard speed
60
120
Overdrive speed
8
16
µs
µs
µs
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 3, 17)
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tW0L
µs
Maxim Integrated │ 2
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Electrical Characteristics (continued)
(TA = -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER
Write-One Low Time
(Notes 3, 17)
SYMBOL
tW1L
CONDITIONS
MIN
TYP
MAX
Standard speed
1
15
Overdrive speed
1
2
Standard speed
5
15 - d
Overdrive speed
1
Standard speed
tRL + d
2-d
15
UNITS
µs
IO PIN: 1-Wire READ
Read Low Time
(Notes 3, 18)
Read Sample Time
(Notes 3, 18)
tRL
tMSR
Overdrive speed
MEMORY
tRL + d
2
µs
µs
Programming Current
IPROG
VPUP = 3.63V (Notes 6, 19, 20)
12
mA
Programming Time for a
Memory Block
tPROG
(Notes 20, 21)
20
ms
Data Retention
tDR
TA = +85°C (Note 22)
10
Years
Note 2: Limits are 100% production tested at TA = +25°C or TA = +85°C. Limits over the operating temperature range and relevant
supply voltage range are guaranteed by design and characterization. Typical values are at TA = +25°C.
Note 3: System requirement.
Note 4: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 5: Typical value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Note 6: Guaranteed by design and/or characterization only. Not production tested.
Note 7: VTL, VTH, and VHY are functions of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values
of VTL, VTH, and VHY.
Note 8: Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 9: The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic-zero level.
Note 10:Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 11:After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic-zero.
Note 12:The I-V characteristic is linear for voltages less than 1V.
Note 13:Applies to a single device attached to a 1-Wire line.
Note 14:Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Note 15:An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 16:Interval after tRSTL during which a bus master can read a logic-zero on IO if there is a DS28E80 present. The power-up
presence detect pulse can be outside this interval, but it is completed within 2ms after power-up. 1-Wire communication
should be considered invalid until 2ms after power-up. Send a 1-Wire reset after POR for presence detect.
Note 17:ε in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 18:δ in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Note 19:Current drawn from IO during the programming interval. The pullup circuits on IO during the programming interval should
be such that the voltage at IO is greater than or equal to VPUPMIN. A low-impedance bypass of RPUP, which can be activated during programming, may need to be added.
Note 20:TA = 0°C to +50°C.
Note 21:The tPROG interval begins immediately after the trailing rising edge on IO for the last time slot of the Release byte (FFh) for
a valid Write Block sequence. The interval ends once the device’s self-timed programming cycle is complete and the current drawn by the device has returned from IPROG to IL.
Note 22:Data retention is tested in compliance with JESD47G. No elevated gamma radiation level.
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Maxim Integrated │ 3
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Pin Configuration
TOP VIEW
DS28E80
N.C. 1
IO
2
GND
3
+
EP*
6
N.C.
4
N.C.
5
N.C.
TDFN-EP
3mm x 3mm
*EP = EXPOSED PAD
Pin Description
PIN
NAME
1, 4–6
N.C.
2
IO
3
GND
—
EP
Detailed Description
FUNCTION
Not Connected
1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor.
Ground Reference
Exposed Pad. Solder evenly to the board’s ground plane for proper operation. Refer to
Application Note 3273: Exposed Pads: A Brief Introduction for additional information.
The DS28E80 combines 1984 bits of 8-times programmable radiation hard nonvolatile user memory, administration memory, protection memory, and a 64-bit ROM ID
in a single chip. A data buffer assists when writing to the
memory. Data is transferred serially through the 1-Wire
protocol that requires only a single data lead and a
ground return. The user memory can be write protected
to prevent overwriting the memory data. The protection
applies to individual memory blocks. To protect against
adverse effects caused by bit errors, the communication
relies on 16-bit CRCs that the DS28E80 generates at
various places in the protocol. The master verifies the
CRC and, when found correct, transmits a release byte
(any value from 00h to FFh) to approve EEPROM programming cycle. In case of a CRC error, the master can
abort the communication and start over.
The device’s 64-bit ROM ID can be used to electronically
identify the object in which the DS28E80 is used. The
ROM ID guarantees unique identification and functions as
logical address in a multidrop 1-Wire network environment
where multiple devices reside on a common 1-Wire bus
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and operate independently of each other. The main application of the DS28E80 is identification and monitoring of
consumables for medical applications.
Overview
The block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
DS28E80. The device has five main data components:
user memory (31 blocks of 8 bytes), administration memory, protection memory, 64-bit ROM ID, and a 64-bit data
buffer. Figure 2 shows the hierarchical structure of the
1-Wire protocol. The bus master must first provide one of
the seven ROM function commands: Read ROM, Match
ROM, Search ROM, Skip ROM, Resume Communication,
Overdrive-Skip ROM and Overdrive-Match ROM. The
protocol required for these ROM function commands is
described in Figure 8. After a ROM function command
is successfully executed, the memory functions become
accessible and the master can provide any one of the
5 available memory function commands. The function
protocols are described in Figure 6. All data is read and
written least-significant bit first.
Maxim Integrated │ 4
DS28E80
Gamma Radiation Resistant 1-Wire Memory
PARASITE POWER
1-Wire BUS
1-Wire
FUNCTION CONTROL
64-BIT
ROM ID
MEMORY
FUNCTION CONTROL
ADMINISTRATION
MEMORY
CRC-16
GENERATOR
PROTECTION
MEMORY
USER
MEMORY
WRITE BUFFER
DS28E80
Figure 1. DS28E80 Block Diagram
DS28E80
COMMAND
LEVEL:
1-Wire ROM
FUNCTION COMMANDS
DS28E80-SPECIFIC
MEMORY FUNCTION
COMMANDS
AVAILABLE
COMMANDS:
DATA FIELD
AFFECTED:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
RC-FLAG
RC-FLAG
RC-FLAG, OD-FLAG
64-BIT ROM ID, RC-FLAG, OD-FLAG
WRITE BLOCK
USER MEMORY, ADMINISTRATION
MEMORY, PROTECTION
MEMORY, WRITE BUFFER
USER MEMORY
PROTECTION MEMORY
PROTECTION MEMORY
ADMINISTRATION MEMORY
READ MEMORY
WRITE PROTECT BLOCK
READ BLOCK PROTECTION
READ REMAINING CYCLES
Figure 2. Hierarchical Structure for 1-Wire Protocol
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Maxim Integrated │ 5
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Using Cyclic Redundancy Checks with Maxim iButton®
Products.
64-Bit ROM ID
Each DS28E80 contains a unique ROM ID that is 64 bits
long. The first 8 bits are a 1-Wire family code: 4Ah. The
next 48 bits are a unique serial number. The last 8 bits
are a cyclic redundancy check (CRC) of the first 56 bits.
See Figure 3 for details. The CRC is generated using a
polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X8 +
X5 + X4 + 1. Additional information about the 1-Wire CRC
is available in Application Note 27: Understanding and
The shift register bits are initialized to 0. Then, starting
with the least-significant bit of the family code, one bit at
a time is shifted in. After the 8th bit of the family code has
been entered, the serial number is entered. Then the fixed
data is entered. After the last bit of the serial data has
been entered, the shift register contains the CRC value.
Shifting in the 8 bits of the CRC returns the shift register
to all 0s.
MSb
LSb
8-BIT
CRC CODE
MSb
8-BIT FAMILY CODE
(4Ah)
48-BIT SERIAL NUMBER
LSb MSb
LSb
LSb MSb
Figure 3. 64-Bit ROM ID
POLYNOMIAL = X8 + X5 + X4 + 1
MSb
LSb
1ST
STAGE
X0
2ND
STAGE
X1
3RD
STAGE
X2
4TH
STAGE
X3
5TH
STAGE
X4
6TH
STAGE
X5
7TH
STAGE
X6
8TH
STAGE
X7
X8
INPUT DATA
Figure 4. 8-Bit CRC Generator
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Maxim Integrated │ 6
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Memory Resources
Memory Function Commands
The memory of the DS28E80 consists of user memory,
administration memory, protection memory, a write buffer,
and a ROM ID. Table 1 shows the size, access mode, and
purpose of the various memory areas. Brackets around
an access mode indicate possible restrictions, such as
write protection.
Figure 6 describes the protocols to access the memory of
the DS28E80. Common to all functions is one parameter
byte that is to be transmitted after the command code. If
the parameter byte is valid, the master receives a 16-bit
CRC as confirmation. All subsequent communication
depends on the command issued. The user memory is
written in blocks of 8 bytes. The write buffer serves as
intermediate storage space when writing a memory block.
Each block can be programmed 8 times. The Write Protect
Block command is implemented to set the block protection. The Read Block Protection command allows reading
the block protection settings. The Read Remaining Cycles
command reports how many more write accesses are left
for each block. The data transmission sequence is leastsignificant byte and least-significant bit first. The CRC-16
is always communicated in its inverted form.
The user memory (Figure 5) is organized as 31 blocks
of 8 bytes each, totaling of 248 bytes. Write protection is
activated through the Write Protect Block command. Once
a protection is activated, it cannot be reversed. The currently valid protection settings are read accessible through
the Read Block Protection command. See the Memory
Function Commands section for command flow details.
Table 1. Memory Resources
NAME
SIZE (BYTES)
User Memory
ACCESS MODE
PURPOSE
248
Read, (write)
Administration Memory
32
Read, internal read,
and write
Application-specific data storage
Block erase/rewrite control
Protection Memory
4
Read, internal read,
and write
Block write protection settings
Write Buffer (SRAM)
8
Write, internal read
Intermediate data storage when writing to the memory
ROM ID
8
Read
1-Wire network device address
BLOCK NUMBER (HEX)
BLOCK NUMBER (DECIMAL)
00h
0
First block of user memory
COMMENT
01h
1
Second block of user memory
02h to 1Ch
2 to 28
1Dh
29
1Eh
30
User memory (continued)
Highest block number of user memory
Figure 5. User Memory Map
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Maxim Integrated │ 7
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Write Block
The Write Block command writes an entire 8-byte memory block. This command affects the remaining cycles counter.
The data provided with the command is temporarily stored in the write buffer. The protocol allows writing multiple adjacent
blocks, up to the end of the memory in a single write block command flow. To detect transmission errors when issuing this
command, the DS28E80 generates and transmits a CRC after the parameter byte as well as after having received the
new block data. In case of an invalid CRC, the master aborts the command by issuing a 1-Wire reset. To start the transfer
to user memory, the master must transmit a release byte. After the programming time is over, the DS28E80 transmits a
CS byte. In case of an error (CS byte ≠ xAh) the master should end the command by issuing a reset.
WRITE BLOCK
Command Code
55h
Parameter Byte
Starting block number (Table 2)
Restrictions
•
•
The memory block must not be write-protected.
There must still be at least one write access left for the block.
Protocol Variations
•
•
Write one block.
Write multiple consecutive blocks.
Error Conditions
•
•
•
•
Invalid parameter byte
The block is write protected.
Write accesses are exhausted.
Internal programming error
CS Byte
xAh = Success; the upper nibble reports the number of remaining write accesses.
55h = The command failed because the block is write protected.
33h = The command failed because of write accesses exhausted.
EEh = The command failed because of an internal programming error.
CRCS
Computation
First occurrence: Shifting (least-significant bit first) the command code and then the parameter byte into the
cleared CRC-16 generator.
Subsequent occurrences: Shifting the new block data (8 bytes) into the cleared CRC-16 generator. The new
data is shifted into the CRC-16 generator in the same byte and bit sequence as sent by the master.
Table 2. Parameter Byte Bitmap
BIT 7
BIT 6
BIT 5
X
X
X
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BN
Bits marked as X can be transmitted as 0 or 1 without affecting the command.
Bits[4:0]: Block Number (BN). These bits specify the location where the writing begins. Valid block numbers are 00000b
(start of memory) to 11110b (last block of user memory).
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Maxim Integrated │ 8
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Read Memory
The Read Memory command is used to read the user memory. The protocol allows reading multiple blocks up to the end
of the memory in a single read memory command flow. After the last byte of a block is read, the DS28E80 transmits a
CRC of the block data for the master to verify the data integrity. If the master continues reading, the DS28E80 transmits
data from the next block, and so on. After the last memory block is read and the master continues reading beyond the
CRC, the resulting data is FFh. The master can end the Read Memory command at any time by issuing a reset pulse.
READ MEMORY
Command Code
F0h
Parameter Byte
Starting block number (Table 3)
Restrictions
None. The command can be issued at any time.
Protocol Variations
•
•
Read one block.
Read multiple consecutive blocks.
Error Conditions
•
Invalid parameter byte
CS Byte
N/A
CRCS Computation
First occurrence: Shifting (lease-significant bit first) the command code and then the parameter byte
into the cleared CRC-16 generator.
Subsequent occurrences: Shifting the block data into the cleared CRC-16 generator. The shifting takes
place in the same bit and byte sequence as transmitted by the DS28E80.
Table 3. Parameter Byte Bitmap
BIT 7
BIT 6
BIT 5
X
X
X
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BN
Bits marked as X can be transmitted as 0 or 1 without affecting the command.
Bits[4:0]: Block Number (BN). These bits specify the location where the reading begins. Valid block numbers are
00000b (start of memory) to 11110b (last block of user memory).
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Maxim Integrated │ 9
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Write Protect Block
The Write Protect Block command is used to protect a user memory block from changes. Once set, the protection cannot
be reset. To detect transmission errors when issuing this command, the DS28E80 generates and transmits a CRC after
the parameter byte. In case of an invalid CRC, the master aborts the command by issuing a 1-Wire reset. To activate the
protection the master must transmit a release byte. After the programming time is over, the DS28E80 transmits a CS byte.
WRITE PROTECT BLOCK
Command Code
C3h
Parameter Byte
Block to be write protected (Table 4)
Restrictions
None. The command can be issued at any time.
Protocol Variations
None
Error Conditions
•
•
•
CS Byte
AAh = Success
55h = The command failed because the block is already write protected.
EEh = The command failed because of an internal programming error.
CRCS Computation
Shifting (least-significant bit first) the command code and then the parameter byte PB into the cleared
CRC-16 generator.
Invalid parameter byte
The block is already write protected.
Internal programming error
Table 4. Parameter Byte Bitmap
BIT 7
BIT 6
BIT 5
X
X
X
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BN
Bits marked as X can be transmitted as 0 or 1 without affecting the command.
Bits[4:0]: Block Number (BN). These bits specify the number of the memory block to be write protected. Valid block
numbers are 00000b (start of memory) to 11110b (last block of user memory).
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Maxim Integrated │ 10
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Read Block Protection
The Read Block Protection command is used to read the protection status of a memory block. To detect transmission
errors when issuing this command, the DS28E80 generates and transmits a CRC after the parameter byte. After the
CRC, the master receives the protection status byte. If the block is unprotected, the code is 0Fh; the code for a protected
block is F0h. If the master continues reading, the DS28E80 transmits the protection status byte of the next block, and
so on. After the status byte of the last memory block is read and the master continues reading, it reads FFh bytes. The
master can end the Read Block Protection command at any time by issuing a reset pulse.
READ BLOCK PROTECTION
Command Code
AAh
Parameter Byte
Starting block number (Table 5)
Restrictions
None. The command can be issued at any time.
Protocol Variations
None
Error Conditions
•
CS Byte
N/A
CRCS Computation
Shifting (least-significant bit first) the command code and then the parameter byte into the cleared
CRC-16 generator.
Invalid parameter byte
Table 5. Parameter Byte Bitmap
BIT 7
BIT 6
BIT 5
X
X
X
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BN
Bits marked as X can be transmitted as 0 or 1 without affecting the command.
Bits[4:0]: Block Number (BN). These bits specify the number of the first memory block for which to read the protection.
Valid block numbers are 00000b (start of memory) to 11110b (last block of user memory).
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DS28E80
Gamma Radiation Resistant 1-Wire Memory
Read Remaining Cycles
The Read Remaining Cycles command is used to read how many more times the Write Block command can be executed
for a given memory block. The value for an unprogrammed memory block is 08h. The value 00h indicates that the write
cycles for the block are exhausted. To detect transmission errors when issuing this command, the DS28E80 generates
and transmits a CRC after the parameter byte. After the CRC, the master receives the remaining write cycles number for
the specific block. If the master continues reading, the DS28E80 transmits the remaining write cycles number of the next
block, and so on. After the remaining write cycles number of the last memory block is read and the master continues reading, it reads FFh bytes. The master can end the Read Remaining Cycles command at any time by issuing a reset pulse.
READ REMAINING CYCLES
Command Code
A5h
Parameter Byte
Starting block number (Table 6)
Restrictions
None. The command can be issued at any time.
Protocol Variations
None
Error conditions
•
CS Byte
N/A
CRCS computation
Shifting (least-significant bit first) the command code and then the parameter byte into the cleared
CRC-16 generator.
Invalid parameter byte
Table 6. Parameter Byte Bitmap
BIT 7
BIT 6
BIT 5
X
X
X
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BN
Bits marked as X can be transmitted as 0 or 1 without affecting the command.
Bits[4:0]: Block Number (BN). These bits specify the number of the first memory block for which to read the remaining
cycles. Valid block numbers are 00000b (start of memory) to 11110b (last block of user memory).
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Maxim Integrated │ 12
DS28E80
Gamma Radiation Resistant 1-Wire Memory
55h
WRITE
BLOCK?
MASTER Tx MEMORY
FUNCTION COMMAND
N
TO FIGURE 6b
Y
FROM ROM
FUNCTIONS FLOW
CHART
MASTER Tx PARAMETER BYTE
N
P.- BYTE
VALID?
Y
MASTER Rx CRC-16 OF COMMAND,
PARAMETER BYTE
DS28E80 SETS BYTE COUNTER = 0,
SETS BLOCK NUMBER FROM
PARAMETER BYTE
MASTER Tx DATA BYTE
DS28E80 INCREMENTS
BYTE COUNTER
N
BYTE
COUNT = 7?
Y
DS28E80 INCREMENTS
BLOCK NUMBER, SETS
BYTE COUNTER = 0
MASTER Rx CRC-16
OF DATA BYTES
N
MASTER Tx
RELEASE?
Y
MASTER WAITS 1 X tPROG
MASTER Rx CS BYTE
Y
MASTER
Tx RESET?
N
BLOCK #
= 1Eh
N
Y
MASTER
Tx RESET?
TO ROM FUNCTIONS
FLOW CHART
Y
N
MASTER Rx 1s
FROM FIGURE 6b
Figure 6a. Memory Functions Flow Chart
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Maxim Integrated │ 13
DS28E80
Gamma Radiation Resistant 1-Wire Memory
FROM FIGURE 6a
F0h
READ
MEMORY?
TO FIGURE 6c
N
Y
MASTER Tx PARAMETER BYTE
N
P. – BYTE
VALID?
Y
MASTER Rx CRC–16 OF
COMMAND, PARAMETER BYTE
DS28E80 SETS BYTE COUNTER = 0, SETS
BLOCK NUMBER FROM PARAMETER BYTE
DS28E80
INCREMENTS
BYTE COUNTER
DS28E80 INCREMENTS
BLOCK NUMBER, SETS
BYTE COUNTER = 0
MASTER Rx
DATA BYTE
N
BYTE
COUNT = 7?
Y
MASTER Rx CRC – 16
OF DATA
END OF
MEMORY?
N
Y
MASTER Rx 1s
TO FIGURE 6a
N
MASTER
Tx RESET?
Y
FROM FIGURE 6c
Figure 6b. Memory Functions Flow Chart
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Maxim Integrated │ 14
DS28E80
Gamma Radiation Resistant 1-Wire Memory
C3h
WRITE PROTECT
BLOCK?
FROM FIGURE 6b
TO FIGURE 6d
N
Y
MASTER Tx PARAMETER BYTE
N
P. – BYTE
VALID?
Y
MASTER Rx CRC–16 OF
COMMAND, PARAMETER BYTE
DS28E80 SETS BLOCK NUMBER FROM
PARAMETER BYTE
N
MASTER
Tx RELEASE?
Y
MASTER WAITS
1 x tPROG
MASTER Rx
CS BYTE
MASTER Rx 1s
N
MASTER
Tx RESET?
Y
TO FIGURE 6b
FROM FIGURE 6d
Figure 6c. Memory Functions Flow Chart
www.maximintegrated.com
Maxim Integrated │ 15
DS28E80
Gamma Radiation Resistant 1-Wire Memory
AAh
READ BLOCK
PROTECTION?
FROM FIGURE 6c
N
TO FIGURE 6e
Y
MASTER Tx PARAMETER BYTE
N
P. – BYTE
VALID?
Y
MASTER Rx CRC–16 OF
COMMAND, PARAMETER BYTE
DS28E80 SETS BLOCK NUMBER FROM
PARAMETER BYTE
MASTER Rx BLOCK
PROTECTION STATUS
DS28E80 INCREMENTS
BLOCK NUMBER
N
BLOCK #
= 1Eh?
Y
MASTER Rx 1s
N
MASTER
Tx RESET?
Y
TO FIGURE 6c
FROM FIGURE 6e
Figure 6d. Memory Functions Flow Chart
www.maximintegrated.com
Maxim Integrated │ 16
DS28E80
Gamma Radiation Resistant 1-Wire Memory
FROM FIGURE 6d
A5h
READ REMAIN.
CYCLES?
N
Y
MASTER Tx PARAMETER BYTE
N
P. – BYTE
VALID?
Y
MASTER Rx CRC–16 OF
COMMAND, PARAMETER BYTE
DS28E80 SETS BLOCK NUMBER FROM
PARAMETER BYTE
MASTER Rx REMAINING
CYCLES COUNT
DS28E80 INCREMENTS
BLOCK NUMBER
N
BLOCK #
= 1Eh?
Y
MASTER Rx 1s
N
MASTER
Tx RESET?
Y
TO FIGURE 6d
Figure 6e. Memory Functions Flow Chart
www.maximintegrated.com
Maxim Integrated │ 17
DS28E80
Gamma Radiation Resistant 1-Wire Memory
1-Wire Bus System
The idle state for the 1-Wire bus is high. If for any reason
a transaction must be suspended, the bus must be left in
the idle state if the transaction is to resume. If this does
not occur and the bus is left low for more than 16µs (overdrive speed) or more than 120µs (standard speed), one or
more devices on the bus could be reset.
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances, the DS28E80 is
a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down
into three topics: hardware configuration, transaction
sequence, and 1-Wire signaling (signal types and timing).
The 1-Wire protocol defines bus transactions in terms of
the bus state during specific time slots that are initiated
on the falling edge of sync pulses from the bus master.
Transaction Sequence
The protocol for accessing the DS28E80 through the
1-Wire port is as follows:
•Initialization
Hardware Configuration
• ROM Function Command
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or threestate outputs. The 1-Wire port of the DS28E80 is open
drain with an internal circuit equivalent to that shown in
Figure 7.
• Memory Function Command
• Transaction Data
Initialization
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by
presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS28E80 is
on the bus and is ready to operate. For more details, see
the 1-Wire Signaling section.
A multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS28E80 supports both standard
and overdrive communication speed of 15.3kbps (max)
and 76kbps (max), respectively. The value of the pullup
resistor primarily depends on the 1-Wire pullup voltage,
network size, and load conditions. The DS28E80 requires
a pullup resistor of maximum 750Ω.
VPUP
BUS MASTER
DS28E80 1-Wire PORT
RPUP
DATA
Rx
Tx
OPEN-DRAIN
PORT PIN
Rx = RECEIVE
Tx = TRANSMIT
Rx
IL
Tx
100Ω MOSFET
Figure 7. Hardware Configuration
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Maxim Integrated │ 18
DS28E80
Gamma Radiation Resistant 1-Wire Memory
1-Wire ROM Function Commands
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that the
DS28E80 supports. All ROM function commands are 8
bits long. A list of these commands follows (Figure 8).
Read ROM [33h]
The Read ROM command allows the bus master to read
the DS28E80’s ROM ID (8-bit family code, unique 48-bit
serial number, and 8-bit CRC). This command can only
be used if there is a single slave on the bus. If more than
one slave is present on the bus, a data collision occurs
when all slaves try to transmit at the same time (open
drain produces a wired-AND result). The family code and
48-bit serial number as read by the master are unlikely to
match the CRC.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM ID,
allows the bus master to address a specific DS28E80 on
a multidrop bus. Only the DS28E80 that exactly matches
the 64-bit ROM ID responds to the following memory or
SHA function command. All other slaves wait for a reset
pulse. This command can be used with a single or multiple devices on the bus.
Search ROM [F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire bus
or their ROM ID numbers. By taking advantage of the
wired-AND property of the bus, the master can use a process of elimination to identify the ID of all slave devices.
For each bit of the ID number, starting with the leastsignificant bit, the bus master issues a triplet of time slots.
On the first slot, each slave device participating in the
search outputs the true value of its ID number bit. On the
second slot, each slave device participating in the search
outputs the complemented value of its ID number bit. On
the third slot, the master writes the true value of the bit
to be selected. All slave devices that do not match the
bit written by the master stop participating in the search.
If both of the read bits are zero, the master knows that
slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the
search tree. After one complete pass, the bus master
knows the ROM ID number of a single device. Additional
passes identify the ID numbers of the remaining devices.
www.maximintegrated.com
Refer to Application Note 187: 1-Wire Search Algorithm
for a detailed discussion including an example.
Skip ROM [CCh]
This command can save time in a single-drop bus system by allowing the bus master to access the memory
functions without providing the 64-bit ROM ID. If more
than one slave is present on the bus and, for example,
a read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves
transmit simultaneously (open-drain pulldowns produce a
wired-AND result).
Resume Command [A5h]
To maximize the data throughput in a multidrop environment, the Resume command is available. This command
checks the status of the RC bit and, if it is set, directly
transfers control to the memory functions, similar to a
Skip ROM command. The only way to set the RC bit is
through successfully executing the Match ROM or Search
ROM command. Once the RC bit is set, the device can
repeatedly be accessed through the Resume command.
Accessing another device on the bus clears the RC bit,
preventing two or more devices from simultaneously
responding to the Resume command.
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the memory functions
without providing the 64-bit ROM ID. Unlike the normal
Skip ROM command, the Overdrive-Skip ROM sets the
DS28E80 in the overdrive mode (OD = 1). All communication following this command must occur at overdrive
speed until a reset pulse of minimum 480µs duration
resets all devices on the bus to standard speed (OD = 0).
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To subsequently address a specific overdrive-supporting device,
a reset pulse at overdrive speed must be issued followed
by a Match ROM or Search ROM command sequence.
This speeds up the time for the search process. If more
than one slave that supports overdrive is present on the
bus and the Overdrive-Skip ROM command is followed
by a read command, data collision occurs on the bus as
multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result).
Maxim Integrated │ 19
DS28E80
Gamma Radiation Resistant 1-Wire Memory
BUS MASTER Tx
RESET PULSE
FROM MEMORY FUNCTIONS
FLOW CHART (FIGURE 6)
FROM FIGURE 8b
OD
RESET PULSE?
N
OD = 0
Y
BUS MASTER Tx ROM
FUNCTION COMMAND
33h
READ ROM
COMMAND?
DS28E80 Tx
PRESENCE PULSE
N
55h
MATCH ROM
COMMAND?
F0h
SEARCH ROM
COMMAND?
N
N
CCh
SKIP ROM
COMMAND?
Y
Y
Y
Y
RC = 0
RC = 0
RC = 0
RC = 0
DS28E80 Tx
FAMILY CODE
(1 BYTE)
MASTER Tx BIT 0
DS28E80 Tx BIT 0
DS28E80 Tx BIT 0
MASTER Tx BIT 0
BIT 0
MATCH?
N
N
BIT 0
MATCH?
Y
Y
DS28E80 Tx
SERIAL NUMBER
(6 BYTES)
DS28E80 Tx BIT 1
MASTER Tx BIT 1
DS28E80 Tx BIT 1
MASTER Tx BIT 1
BIT 1
MATCH?
N
N
BIT 1
MATCH?
Y
Y
DS28E80 Tx
CRC BYTE
TO FIGURE 8b
N
DS28E80 Tx BIT 63
MASTER Tx BIT 63
DS28E80 Tx BIT 63
MASTER Tx BIT 63
BIT 63
MATCH?
N
N
BIT 63
MATCH?
Y
Y
RC = 1
RC = 1
TO FIGURE 8b
FROM FIGURE 8b
TO MEMORY FUNCTIONS
FLOW CHART (FIGURE 6)
Figure 8a. ROM Functions Flow Chart
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Maxim Integrated │ 20
DS28E80
Gamma Radiation Resistant 1-Wire Memory
TO FIGURE 8a
FROM FIGURE 8a
A5h
RESUME
COMMAND?
3Ch
OVERDRIVE-SKIP
ROM ?
N
Y
Y
RC = 1?
N
Y
MASTER Tx
RESET?
N
Y
RC = 0; OD = 1
N
69h
OVERDRIVE-MATCH
ROM ?
RC = 0; OD = 1
Y
MASTER Tx BIT 0
N
MASTER Tx
RESET?
Y
N
BIT 0
MATCH?
N
(SEE NOTE)
OD = 0
Y
MASTER Tx BIT 1
BIT 1
MATCH?
N
(SEE NOTE)
OD = 0
Y
MASTER Tx BIT 63
BIT 63
MATCH?
N
(SEE NOTE)
OD = 0
Y
FROM FIGURE 8a
RC = 1
TO FIGURE 8a
NOTE: THE OD FLAG REMAINS AT 1 IF THE DEVICE WAS ALREADY AT OVERDRIVE
SPEED BEFORE THE OVERDRIVE-MATCH ROM COMMAND WAS ISSUED.
Figure 8b. ROM Functions Flow Chart (continued)
www.maximintegrated.com
Maxim Integrated │ 21
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Overdrive-Match ROM [69h]
VILMAX is relevant for the DS28E80 when determining a
logical level, not triggering any events.
The Overdrive-Match ROM command followed by a
64-bit ROM ID transmitted at overdrive speed allows the
bus master to address a specific DS28E80 on a multidrop bus and to simultaneously set it in overdrive mode.
Only the DS28E80 that exactly matches the 64-bit ROM
ID responds to the subsequent memory function command. Slaves already in overdrive mode from a previous Overdrive-Skip ROM or successful Overdrive-Match
ROM command remain in overdrive mode. All overdrivecapable slaves return to standard speed at the next reset
pulse of minimum 480µs duration. The Overdrive-Match
ROM command can be used with a single or multiple
devices on the bus.
Figure 9 shows the initialization sequence required to
begin any communication with the DS28E80. A reset
pulse followed by a presence pulse indicates that the
DS28E80 is ready to receive data, given the correct ROM
and memory/control function command. If the bus master
uses slew-rate control on the falling edge, it must pull
down the line for tRSTL + tF to compensate for the edge.
After the bus master has released the line it goes into
receive mode. Now the 1-Wire bus is pulled to VPUP
through the pullup resistor. When the threshold VTH is
crossed, the DS28E80 waits and then transmits a presence pulse by pulling the line low. To detect a presence
pulse, the master must test the logical state of the 1-Wire
line at tMSP.
1-Wire Signaling
The DS28E80 requires strict protocols to ensure data
integrity. The protocol consists of four types of signaling
on one line: reset sequence with reset pulse and presence pulse, write-zero, write-one, and read-data. Except
for the presence pulse, the bus master initiates all falling
edges. The DS28E80 communicates at overdrive speed
only.
Read/Write Time Slots
Data communication with the DS28E80 takes place in
time slots that carry a single bit each. Write time slots
transport data from bus master to slave. Read time slots
transfer data from slave to master. Figure 10 illustrates
the definitions of the write and read time slots.
To get from idle to active, the voltage on the 1-Wire line
needs to fall from VPUP below the threshold VTL. To get
from active to idle, the voltage needs to rise from VILMAX
past the threshold VTH. The time it takes for the voltage
to make this rise is seen in Figure 9 as ε, and its duration depends on the pullup resistor (RPUP) used and the
capacitance of the 1-Wire network attached. The voltage
All communication begins with the master pulling the data
line low. As the voltage on the 1-Wire line falls below
the threshold VTL, the DS28E80 starts its internal timing
generator that determines when the data line is sampled
during a write time slot and how long data is valid during
a read time slot.
MASTER Tx RESET PULSE
MASTER Rx PRESENCE PULSE
ε
tMSP
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tREC
tRSTL
tF
tRSTH
RESISTOR
MASTER
DS28E80
Figure 9. Reset/Presence pulse
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Maxim Integrated │ 22
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Master to Slave
For a write-one time slot, the voltage on the data line must
have crossed the VTH threshold before the write-one low
time tW1LMAX expires. For a write-zero time slot, the voltage on the data line must stay below the VTH threshold
until the write-zero low time tW0LMIN expires. For the
most reliable communication, the voltage on the data line
should not exceed VILMAX during the entire tW0L or tW1L
window. After the VTH threshold has been crossed, the
DS28E80 needs a recovery time tREC before it is ready
for the next time slot.
Slave to Master
A read-data time slot begins like a write-one time slot. The
voltage on the data line must remain below VTL until the
read low time tRL is expired. During the tRL window, when
responding with a 0, the DS28E80 starts pulling the data
line low; its internal timing generator determines when this
pulldown ends and the voltage starts rising again. When
responding with a 1, the DS28E80 does not hold the data
line low at all, and the voltage starts rising as soon as tRL
is over.
WRITE-ONE TIME SLOT
tW1L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tF
tSLOT
WRITE-ZERO TIME SLOT
tW0L
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
ε
tF
tSLOT
tREC
READ-DATA TIME SLOT
tRL
VPUP
VIHMASTER
VTH
VTL
VILMAX
0V
tMSR
MASTER
SAMPLING
WINDOW
δ
tF
tSLOT
RESISTOR
MASTER
tREC
DS28E80
Figure 10. Read/Write Timing Diagram
www.maximintegrated.com
Maxim Integrated │ 23
DS28E80
Gamma Radiation Resistant 1-Wire Memory
The sum of tRL + δ (rise time) on one side and the internal
timing generator of the DS28E80 on the other side define
the master sampling window (tMSRMIN to tMSRMAX), in
which the master must perform a read from the data line.
For the most reliable communication, tRL should be as
short as permissible, and the master should read close
to but no later than tMSRMAX. After reading from the data
line, the master must wait until tSLOT is expired. This
guarantees sufficient recovery time tREC for the DS28E80
to get ready for the next time slot. Note that tREC specified herein applies only to a single DS28E80 attached to a
1-Wire line. For multidevice configurations, tREC must be
extended to accommodate the additional 1-Wire device
input capacitance.
Such reflections are visible as glitches or ringing on the
1-Wire communication line. Noise coupled onto the 1-Wire
line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can cause
a slave device to lose synchronization with the master and,
consequently, result in a Search ROM command coming to
a dead end or cause a device-specific function command
to abort. The DS28E80 uses a 1-Wire front-end with built-in
hysteresis at the low-to-high switching threshold VTH. If a
negative glitch crosses VTH but does not go below VTL, it
is not recognized (Figure 11).
CRC Generation
The 1-Wire port of the DS28E80 uses two different types
of CRCs. One CRC is an 8-bit type that is computed at
the factory and is stored in the most-significant byte of
the 64-bit ROM ID. The bus master can compute a CRC
value from the first 56 bits of the 64-bit ROM ID and compare it to the value read from the DS28E80 to determine
whether the ID number has been received error-free. The
equivalent polynomial function of this CRC is X8 + X5 + X4
+ 1. This 8-bit CRC is received in the true (noninverted)
form.
Improved Network Behavior
(Switchpoint Hysteresis)
In a 1-Wire environment, line termination is possible only
during transients controlled by the bus master (1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of
various origins. Depending on the physical size and topology of the network, reflections from end points and branch
points can add up or cancel each other to some extent.
VPUP
VTH
VTL
VHY
0V
Figure 11. Noise Suppression Scheme
POLYNOMIAL = X16 + X15 + X2 + 1
1ST
STAGE
X0
X2
X1
9TH
STAGE
X8
3RD
STAGE
2ND
STAGE
10TH
STAGE
X9
11TH
STAGE
X10
4TH
STAGE
X3
12TH
STAGE
X11
5TH
STAGE
X4
13TH
STAGE
X12
6TH
STAGE
X5
14TH
STAGE
X13
7TH
STAGE
X6
8TH
STAGE
X7
15TH
STAGE
X14
16TH
STAGE
X15
X16
CRC OUTPUT
INPUT DATA
Figure 12. CRC-16 Generator
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Maxim Integrated │ 24
DS28E80
Gamma Radiation Resistant 1-Wire Memory
The other CRC is a 16-bit type, generated according to the standardized CRC-16 polynomial function X16 + X15 + X2 +
1. This CRC is used for error detection with all memory function commands. In contrast to the 8-bit CRC, the 16-bit CRC
is always communicated in the inverted form. A CRC generator inside the DS28E80 chip (Figure 12) calculates a new
16-bit CRC, as shown in the memory function flowchart (Figure 6). The bus master compares the CRC value read from
the device to the one it calculates from the data and decides whether to continue with an operation or to start over again.
1-Wire Communication Examples
See Table 7 and Table 8 for the 1-Wire Communication legend and the data direction color codes.
Table 7. 1-Wire Communication—Legend
SYMBOL
DESCRIPTION
WB
Command “Write Block”, 55h
RM
Command “Read Memory”, F0h
WPB
Command “Write Protect Block”, C3h
RBP
Command “Read Block Protection”, AAh
RRC
Command “Read Remaining Cycles”, A5h
RST
Reset pulse
PD
Presence detect pulse
Select
Any communication that satisfies the network functions
PB
Parameter byte, always follows the command code
CRCS
Slave-generated CRC-16, always transmitted inverted, LS-bit first
CS
Command Success indicator
Byte sent by the master to start a write activity in the slave. Byte can be any value from 00h
to FFh.
Release
<n bytes>
Transfer of n bytes
FF loop
Indefinite loop where the bus master reads FF bytes
Table 8. Data Direction Color Codes
MASTER TO SLAVE
SLAVE TO MASTER
MASTER WAITS (1-Wire IDLE HIGH)
1-Wire Communication Examples
WRITE BLOCK
SUCCESSFUL WRITING
RST
PD
SELECT
WB
PB
CRCS
<8 bytes>
CRCS
RELEASE
WAIT tPROG
CS = xAh
RST
CS ≠ xAh
RST
REPEAT FOR ADDITIONAL BLOCKS
WRITING FAILS WITH ERROR
RST
PD
SELECT
WB
PB
CRCS
<8 bytes>
CRCS
RELEASE
WAIT tPROG
FAILURE (INVALID PARAMETER BYTE)
RST
PD
www.maximintegrated.com
SELECT
WB
PB = 1Fh
FF LOOP
Maxim Integrated │ 25
DS28E80
Gamma Radiation Resistant 1-Wire Memory
READ MEMORY
STARTING AT BLOCK NUMBER 05h, READING 3 BYTES
RST
PD
SELECT
RM
PB = 05h
CRCS
<3 bytes>
RST
<8 bytes>
CRCS
STARTING AT BLOCK NUMBER 12h, READING 2 BLOCKS
RST
PD
SELECT
RM
PB = 12h
CRCS
<8 bytes>
CRCS
RST
REPEAT FOR ADDITIONAL BLOCKS
FAILURE (INVALID PARAMETER BYTE)
RST
PD
SELECT
RM
PB = 1Fh
FF LOOP
WRITE PROTECT BLOCK
SUCCESSFUL WRITE-PROTECTING MEMORY BLOCK 10h
RST
PD
SELECT
WPB
PB = 10h
CRCS
RELEASE
WAIT tPROG
CS = AAh
RST
WRITING FAILS BECAUSE THE BLOCK IS ALREADY WRITE PROTECTED.
RST
PD
SELECT
WPB
PB
CRCS
RELEASE
WAIT tPROG
CS = 55h
RST
FAILURE (INVALID PARAMETER BYTE)
RST
PD
SELECT
WPB
PB = 1Fh
FF LOOP
READ BLOCK PROTECTION
READ THE PROTECTION OF MEMORY BLOCKS 10h TO 12h
RST
PD
SELECT
RBP
PB = 10h
CRCS
<3 bytes>
RST
FAILURE (INVALID PARAMETER BYTE)
RST
PD
SELECT
RBP
PB = 1Fh
FF LOOP
READ REMAINING CYCLES
READ THE REMAINING CYCLES OF MEMORY BLOCKS 10h TO 15h
RST
PD
SELECT
RRC
PB = 10h
CRCS
<6 bytes>
RST
FAILURE (INVALID PARAMETER BYTE)
RST
www.maximintegrated.com
PD
SELECT
RRC
PB = 1Fh
FF LOOP
Maxim Integrated │ 26
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Package Information
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS28E80Q+U
-40°C to +85°C
6 TDFN
DS28E80Q+T
-40°C to +85°C
6 TDFN (2.5k pcs)
+Denotes lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
www.maximintegrated.com
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
6 TDFN
T633MK+1
21-0137
90-0058
Maxim Integrated │ 27
DS28E80
Gamma Radiation Resistant 1-Wire Memory
Revision History
REVISION
NUMBER
REVISION
DATE
0
9/14
DESCRIPTION
Initial release
PAGES
CHANGED
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2014 Maxim Integrated Products, Inc. │ 28
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